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targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_spi.h@149:1fb5f62b92bd, 2014-04-03 (annotated)

Committer:: mbed_official
Date:: Thu Apr 03 11:45:06 2014 +0100
Revision:: 149:1fb5f62b92bd
Parent:: targets/hal/TARGET_Freescale/TARGET_KSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_spi.h@146:f64d43ff0c18

Synchronized with git revision 220c0bb39ceee40016e1e86350c058963d01ed42



Full URL: https://github.com/mbedmicro/mbed/commit/220c0bb39ceee40016e1e86350c058963d01ed42/

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	146:f64d43ff0c18	1	/*
mbed_official	146:f64d43ff0c18	2	* Copyright (c) 2014, Freescale Semiconductor, Inc.
mbed_official	146:f64d43ff0c18	3	* All rights reserved.
mbed_official	146:f64d43ff0c18	4	*
mbed_official	146:f64d43ff0c18	5	* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official	146:f64d43ff0c18	6	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official	146:f64d43ff0c18	7	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
mbed_official	146:f64d43ff0c18	8	* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
mbed_official	146:f64d43ff0c18	9	* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
mbed_official	146:f64d43ff0c18	10	* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official	146:f64d43ff0c18	11	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official	146:f64d43ff0c18	12	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
mbed_official	146:f64d43ff0c18	13	* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
mbed_official	146:f64d43ff0c18	14	* OF SUCH DAMAGE.
mbed_official	146:f64d43ff0c18	15	*/
mbed_official	146:f64d43ff0c18	16	/*
mbed_official	146:f64d43ff0c18	17	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official	146:f64d43ff0c18	18	*
mbed_official	146:f64d43ff0c18	19	* This file was generated automatically and any changes may be lost.
mbed_official	146:f64d43ff0c18	20	*/
mbed_official	146:f64d43ff0c18	21	#ifndef __HW_SPI_REGISTERS_H__
mbed_official	146:f64d43ff0c18	22	#define __HW_SPI_REGISTERS_H__
mbed_official	146:f64d43ff0c18	23
mbed_official	146:f64d43ff0c18	24	#include "regs.h"
mbed_official	146:f64d43ff0c18	25
mbed_official	146:f64d43ff0c18	26	/*
mbed_official	146:f64d43ff0c18	27	* MK64F12 SPI
mbed_official	146:f64d43ff0c18	28	*
mbed_official	146:f64d43ff0c18	29	* Serial Peripheral Interface
mbed_official	146:f64d43ff0c18	30	*
mbed_official	146:f64d43ff0c18	31	* Registers defined in this header file:
mbed_official	146:f64d43ff0c18	32	* - HW_SPI_MCR - Module Configuration Register
mbed_official	146:f64d43ff0c18	33	* - HW_SPI_TCR - Transfer Count Register
mbed_official	146:f64d43ff0c18	34	* - HW_SPI_CTARn - Clock and Transfer Attributes Register (In Master Mode)
mbed_official	146:f64d43ff0c18	35	* - HW_SPI_CTARn_SLAVE - Clock and Transfer Attributes Register (In Slave Mode)
mbed_official	146:f64d43ff0c18	36	* - HW_SPI_SR - Status Register
mbed_official	146:f64d43ff0c18	37	* - HW_SPI_RSER - DMA/Interrupt Request Select and Enable Register
mbed_official	146:f64d43ff0c18	38	* - HW_SPI_PUSHR - PUSH TX FIFO Register In Master Mode
mbed_official	146:f64d43ff0c18	39	* - HW_SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode
mbed_official	146:f64d43ff0c18	40	* - HW_SPI_POPR - POP RX FIFO Register
mbed_official	146:f64d43ff0c18	41	* - HW_SPI_TXFRn - Transmit FIFO Registers
mbed_official	146:f64d43ff0c18	42	* - HW_SPI_RXFRn - Receive FIFO Registers
mbed_official	146:f64d43ff0c18	43	*
mbed_official	146:f64d43ff0c18	44	* - hw_spi_t - Struct containing all module registers.
mbed_official	146:f64d43ff0c18	45	*/
mbed_official	146:f64d43ff0c18	46
mbed_official	146:f64d43ff0c18	47	//! @name Module base addresses
mbed_official	146:f64d43ff0c18	48	//@{
mbed_official	146:f64d43ff0c18	49	#ifndef REGS_SPI_BASE
mbed_official	146:f64d43ff0c18	50	#define HW_SPI_INSTANCE_COUNT (3U) //!< Number of instances of the SPI module.
mbed_official	146:f64d43ff0c18	51	#define HW_SPI0 (0U) //!< Instance number for SPI0.
mbed_official	146:f64d43ff0c18	52	#define HW_SPI1 (1U) //!< Instance number for SPI1.
mbed_official	146:f64d43ff0c18	53	#define HW_SPI2 (2U) //!< Instance number for SPI2.
mbed_official	146:f64d43ff0c18	54	#define REGS_SPI0_BASE (0x4002C000U) //!< Base address for SPI0.
mbed_official	146:f64d43ff0c18	55	#define REGS_SPI1_BASE (0x4002D000U) //!< Base address for SPI1.
mbed_official	146:f64d43ff0c18	56	#define REGS_SPI2_BASE (0x400AC000U) //!< Base address for SPI2.
mbed_official	146:f64d43ff0c18	57
mbed_official	146:f64d43ff0c18	58	//! @brief Table of base addresses for SPI instances.
mbed_official	146:f64d43ff0c18	59	static const uint32_t __g_regs_SPI_base_addresses[] = {
mbed_official	146:f64d43ff0c18	60	REGS_SPI0_BASE,
mbed_official	146:f64d43ff0c18	61	REGS_SPI1_BASE,
mbed_official	146:f64d43ff0c18	62	REGS_SPI2_BASE,
mbed_official	146:f64d43ff0c18	63	};
mbed_official	146:f64d43ff0c18	64
mbed_official	146:f64d43ff0c18	65	//! @brief Get the base address of SPI by instance number.
mbed_official	146:f64d43ff0c18	66	//! @param x SPI instance number, from 0 through 2.
mbed_official	146:f64d43ff0c18	67	#define REGS_SPI_BASE(x) (__g_regs_SPI_base_addresses[(x)])
mbed_official	146:f64d43ff0c18	68
mbed_official	146:f64d43ff0c18	69	//! @brief Get the instance number given a base address.
mbed_official	146:f64d43ff0c18	70	//! @param b Base address for an instance of SPI.
mbed_official	146:f64d43ff0c18	71	#define REGS_SPI_INSTANCE(b) ((b) == REGS_SPI0_BASE ? HW_SPI0 : (b) == REGS_SPI1_BASE ? HW_SPI1 : (b) == REGS_SPI2_BASE ? HW_SPI2 : 0)
mbed_official	146:f64d43ff0c18	72	#endif
mbed_official	146:f64d43ff0c18	73	//@}
mbed_official	146:f64d43ff0c18	74
mbed_official	146:f64d43ff0c18	75	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	76	// HW_SPI_MCR - Module Configuration Register
mbed_official	146:f64d43ff0c18	77	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	78
mbed_official	146:f64d43ff0c18	79	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	80	/*!
mbed_official	146:f64d43ff0c18	81	* @brief HW_SPI_MCR - Module Configuration Register (RW)
mbed_official	146:f64d43ff0c18	82	*
mbed_official	146:f64d43ff0c18	83	* Reset value: 0x00004001U
mbed_official	146:f64d43ff0c18	84	*
mbed_official	146:f64d43ff0c18	85	* Contains bits to configure various attributes associated with the module
mbed_official	146:f64d43ff0c18	86	* operations. The HALT and MDIS bits can be changed at any time, but the effect
mbed_official	146:f64d43ff0c18	87	* takes place only on the next frame boundary. Only the HALT and MDIS bits in the
mbed_official	146:f64d43ff0c18	88	* MCR can be changed, while the module is in the Running state.
mbed_official	146:f64d43ff0c18	89	*/
mbed_official	146:f64d43ff0c18	90	typedef union _hw_spi_mcr
mbed_official	146:f64d43ff0c18	91	{
mbed_official	146:f64d43ff0c18	92	uint32_t U;
mbed_official	146:f64d43ff0c18	93	struct _hw_spi_mcr_bitfields
mbed_official	146:f64d43ff0c18	94	{
mbed_official	146:f64d43ff0c18	95	uint32_t HALT : 1; //!< [0] Halt
mbed_official	146:f64d43ff0c18	96	uint32_t RESERVED0 : 7; //!< [7:1]
mbed_official	146:f64d43ff0c18	97	uint32_t SMPL_PT : 2; //!< [9:8] Sample Point
mbed_official	146:f64d43ff0c18	98	uint32_t CLR_RXF : 1; //!< [10]
mbed_official	146:f64d43ff0c18	99	uint32_t CLR_TXF : 1; //!< [11] Clear TX FIFO
mbed_official	146:f64d43ff0c18	100	uint32_t DIS_RXF : 1; //!< [12] Disable Receive FIFO
mbed_official	146:f64d43ff0c18	101	uint32_t DIS_TXF : 1; //!< [13] Disable Transmit FIFO
mbed_official	146:f64d43ff0c18	102	uint32_t MDIS : 1; //!< [14] Module Disable
mbed_official	146:f64d43ff0c18	103	uint32_t DOZE : 1; //!< [15] Doze Enable
mbed_official	146:f64d43ff0c18	104	uint32_t PCSIS : 6; //!< [21:16] Peripheral Chip Select x Inactive
mbed_official	146:f64d43ff0c18	105	//! State
mbed_official	146:f64d43ff0c18	106	uint32_t RESERVED1 : 2; //!< [23:22]
mbed_official	146:f64d43ff0c18	107	uint32_t ROOE : 1; //!< [24] Receive FIFO Overflow Overwrite Enable
mbed_official	146:f64d43ff0c18	108	uint32_t PCSSE : 1; //!< [25] Peripheral Chip Select Strobe Enable
mbed_official	146:f64d43ff0c18	109	uint32_t MTFE : 1; //!< [26] Modified Timing Format Enable
mbed_official	146:f64d43ff0c18	110	uint32_t FRZ : 1; //!< [27] Freeze
mbed_official	146:f64d43ff0c18	111	uint32_t DCONF : 2; //!< [29:28] SPI Configuration.
mbed_official	146:f64d43ff0c18	112	uint32_t CONT_SCKE : 1; //!< [30] Continuous SCK Enable
mbed_official	146:f64d43ff0c18	113	uint32_t MSTR : 1; //!< [31] Master/Slave Mode Select
mbed_official	146:f64d43ff0c18	114	} B;
mbed_official	146:f64d43ff0c18	115	} hw_spi_mcr_t;
mbed_official	146:f64d43ff0c18	116	#endif
mbed_official	146:f64d43ff0c18	117
mbed_official	146:f64d43ff0c18	118	/*!
mbed_official	146:f64d43ff0c18	119	* @name Constants and macros for entire SPI_MCR register
mbed_official	146:f64d43ff0c18	120	*/
mbed_official	146:f64d43ff0c18	121	//@{
mbed_official	146:f64d43ff0c18	122	#define HW_SPI_MCR_ADDR(x) (REGS_SPI_BASE(x) + 0x0U)
mbed_official	146:f64d43ff0c18	123
mbed_official	146:f64d43ff0c18	124	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	125	#define HW_SPI_MCR(x) ((__IO hw_spi_mcr_t ) HW_SPI_MCR_ADDR(x))
mbed_official	146:f64d43ff0c18	126	#define HW_SPI_MCR_RD(x) (HW_SPI_MCR(x).U)
mbed_official	146:f64d43ff0c18	127	#define HW_SPI_MCR_WR(x, v) (HW_SPI_MCR(x).U = (v))
mbed_official	146:f64d43ff0c18	128	#define HW_SPI_MCR_SET(x, v) (HW_SPI_MCR_WR(x, HW_SPI_MCR_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	129	#define HW_SPI_MCR_CLR(x, v) (HW_SPI_MCR_WR(x, HW_SPI_MCR_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	130	#define HW_SPI_MCR_TOG(x, v) (HW_SPI_MCR_WR(x, HW_SPI_MCR_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	131	#endif
mbed_official	146:f64d43ff0c18	132	//@}
mbed_official	146:f64d43ff0c18	133
mbed_official	146:f64d43ff0c18	134	/*
mbed_official	146:f64d43ff0c18	135	* Constants & macros for individual SPI_MCR bitfields
mbed_official	146:f64d43ff0c18	136	*/
mbed_official	146:f64d43ff0c18	137
mbed_official	146:f64d43ff0c18	138	/*!
mbed_official	146:f64d43ff0c18	139	* @name Register SPI_MCR, field HALT[0] (RW)
mbed_official	146:f64d43ff0c18	140	*
mbed_official	146:f64d43ff0c18	141	* The HALT bit starts and stops frame transfers. See Start and Stop of Module
mbed_official	146:f64d43ff0c18	142	* transfers
mbed_official	146:f64d43ff0c18	143	*
mbed_official	146:f64d43ff0c18	144	* Values:
mbed_official	146:f64d43ff0c18	145	* - 0 - Start transfers.
mbed_official	146:f64d43ff0c18	146	* - 1 - Stop transfers.
mbed_official	146:f64d43ff0c18	147	*/
mbed_official	146:f64d43ff0c18	148	//@{
mbed_official	146:f64d43ff0c18	149	#define BP_SPI_MCR_HALT (0U) //!< Bit position for SPI_MCR_HALT.
mbed_official	146:f64d43ff0c18	150	#define BM_SPI_MCR_HALT (0x00000001U) //!< Bit mask for SPI_MCR_HALT.
mbed_official	146:f64d43ff0c18	151	#define BS_SPI_MCR_HALT (1U) //!< Bit field size in bits for SPI_MCR_HALT.
mbed_official	146:f64d43ff0c18	152
mbed_official	146:f64d43ff0c18	153	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	154	//! @brief Read current value of the SPI_MCR_HALT field.
mbed_official	146:f64d43ff0c18	155	#define BR_SPI_MCR_HALT(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_HALT))
mbed_official	146:f64d43ff0c18	156	#endif
mbed_official	146:f64d43ff0c18	157
mbed_official	146:f64d43ff0c18	158	//! @brief Format value for bitfield SPI_MCR_HALT.
mbed_official	146:f64d43ff0c18	159	#define BF_SPI_MCR_HALT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_HALT), uint32_t) & BM_SPI_MCR_HALT)
mbed_official	146:f64d43ff0c18	160
mbed_official	146:f64d43ff0c18	161	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	162	//! @brief Set the HALT field to a new value.
mbed_official	146:f64d43ff0c18	163	#define BW_SPI_MCR_HALT(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_HALT) = (v))
mbed_official	146:f64d43ff0c18	164	#endif
mbed_official	146:f64d43ff0c18	165	//@}
mbed_official	146:f64d43ff0c18	166
mbed_official	146:f64d43ff0c18	167	/*!
mbed_official	146:f64d43ff0c18	168	* @name Register SPI_MCR, field SMPL_PT[9:8] (RW)
mbed_official	146:f64d43ff0c18	169	*
mbed_official	146:f64d43ff0c18	170	* Controls when the module master samples SIN in Modified Transfer Format. This
mbed_official	146:f64d43ff0c18	171	* field is valid only when CPHA bit in CTARn[CPHA] is 0.
mbed_official	146:f64d43ff0c18	172	*
mbed_official	146:f64d43ff0c18	173	* Values:
mbed_official	146:f64d43ff0c18	174	* - 00 - 0 protocol clock cycles between SCK edge and SIN sample
mbed_official	146:f64d43ff0c18	175	* - 01 - 1 protocol clock cycle between SCK edge and SIN sample
mbed_official	146:f64d43ff0c18	176	* - 10 - 2 protocol clock cycles between SCK edge and SIN sample
mbed_official	146:f64d43ff0c18	177	* - 11 - Reserved
mbed_official	146:f64d43ff0c18	178	*/
mbed_official	146:f64d43ff0c18	179	//@{
mbed_official	146:f64d43ff0c18	180	#define BP_SPI_MCR_SMPL_PT (8U) //!< Bit position for SPI_MCR_SMPL_PT.
mbed_official	146:f64d43ff0c18	181	#define BM_SPI_MCR_SMPL_PT (0x00000300U) //!< Bit mask for SPI_MCR_SMPL_PT.
mbed_official	146:f64d43ff0c18	182	#define BS_SPI_MCR_SMPL_PT (2U) //!< Bit field size in bits for SPI_MCR_SMPL_PT.
mbed_official	146:f64d43ff0c18	183
mbed_official	146:f64d43ff0c18	184	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	185	//! @brief Read current value of the SPI_MCR_SMPL_PT field.
mbed_official	146:f64d43ff0c18	186	#define BR_SPI_MCR_SMPL_PT(x) (HW_SPI_MCR(x).B.SMPL_PT)
mbed_official	146:f64d43ff0c18	187	#endif
mbed_official	146:f64d43ff0c18	188
mbed_official	146:f64d43ff0c18	189	//! @brief Format value for bitfield SPI_MCR_SMPL_PT.
mbed_official	146:f64d43ff0c18	190	#define BF_SPI_MCR_SMPL_PT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_SMPL_PT), uint32_t) & BM_SPI_MCR_SMPL_PT)
mbed_official	146:f64d43ff0c18	191
mbed_official	146:f64d43ff0c18	192	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	193	//! @brief Set the SMPL_PT field to a new value.
mbed_official	146:f64d43ff0c18	194	#define BW_SPI_MCR_SMPL_PT(x, v) (HW_SPI_MCR_WR(x, (HW_SPI_MCR_RD(x) & ~BM_SPI_MCR_SMPL_PT) \| BF_SPI_MCR_SMPL_PT(v)))
mbed_official	146:f64d43ff0c18	195	#endif
mbed_official	146:f64d43ff0c18	196	//@}
mbed_official	146:f64d43ff0c18	197
mbed_official	146:f64d43ff0c18	198	/*!
mbed_official	146:f64d43ff0c18	199	* @name Register SPI_MCR, field CLR_RXF[10] (WORZ)
mbed_official	146:f64d43ff0c18	200	*
mbed_official	146:f64d43ff0c18	201	* Flushes the RX FIFO. Writing a 1 to CLR_RXF clears the RX Counter. The
mbed_official	146:f64d43ff0c18	202	* CLR_RXF bit is always read as zero.
mbed_official	146:f64d43ff0c18	203	*
mbed_official	146:f64d43ff0c18	204	* Values:
mbed_official	146:f64d43ff0c18	205	* - 0 - Do not clear the RX FIFO counter.
mbed_official	146:f64d43ff0c18	206	* - 1 - Clear the RX FIFO counter.
mbed_official	146:f64d43ff0c18	207	*/
mbed_official	146:f64d43ff0c18	208	//@{
mbed_official	146:f64d43ff0c18	209	#define BP_SPI_MCR_CLR_RXF (10U) //!< Bit position for SPI_MCR_CLR_RXF.
mbed_official	146:f64d43ff0c18	210	#define BM_SPI_MCR_CLR_RXF (0x00000400U) //!< Bit mask for SPI_MCR_CLR_RXF.
mbed_official	146:f64d43ff0c18	211	#define BS_SPI_MCR_CLR_RXF (1U) //!< Bit field size in bits for SPI_MCR_CLR_RXF.
mbed_official	146:f64d43ff0c18	212
mbed_official	146:f64d43ff0c18	213	//! @brief Format value for bitfield SPI_MCR_CLR_RXF.
mbed_official	146:f64d43ff0c18	214	#define BF_SPI_MCR_CLR_RXF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_CLR_RXF), uint32_t) & BM_SPI_MCR_CLR_RXF)
mbed_official	146:f64d43ff0c18	215
mbed_official	146:f64d43ff0c18	216	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	217	//! @brief Set the CLR_RXF field to a new value.
mbed_official	146:f64d43ff0c18	218	#define BW_SPI_MCR_CLR_RXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CLR_RXF) = (v))
mbed_official	146:f64d43ff0c18	219	#endif
mbed_official	146:f64d43ff0c18	220	//@}
mbed_official	146:f64d43ff0c18	221
mbed_official	146:f64d43ff0c18	222	/*!
mbed_official	146:f64d43ff0c18	223	* @name Register SPI_MCR, field CLR_TXF[11] (WORZ)
mbed_official	146:f64d43ff0c18	224	*
mbed_official	146:f64d43ff0c18	225	* Flushes the TX FIFO. Writing a 1 to CLR_TXF clears the TX FIFO Counter. The
mbed_official	146:f64d43ff0c18	226	* CLR_TXF bit is always read as zero.
mbed_official	146:f64d43ff0c18	227	*
mbed_official	146:f64d43ff0c18	228	* Values:
mbed_official	146:f64d43ff0c18	229	* - 0 - Do not clear the TX FIFO counter.
mbed_official	146:f64d43ff0c18	230	* - 1 - Clear the TX FIFO counter.
mbed_official	146:f64d43ff0c18	231	*/
mbed_official	146:f64d43ff0c18	232	//@{
mbed_official	146:f64d43ff0c18	233	#define BP_SPI_MCR_CLR_TXF (11U) //!< Bit position for SPI_MCR_CLR_TXF.
mbed_official	146:f64d43ff0c18	234	#define BM_SPI_MCR_CLR_TXF (0x00000800U) //!< Bit mask for SPI_MCR_CLR_TXF.
mbed_official	146:f64d43ff0c18	235	#define BS_SPI_MCR_CLR_TXF (1U) //!< Bit field size in bits for SPI_MCR_CLR_TXF.
mbed_official	146:f64d43ff0c18	236
mbed_official	146:f64d43ff0c18	237	//! @brief Format value for bitfield SPI_MCR_CLR_TXF.
mbed_official	146:f64d43ff0c18	238	#define BF_SPI_MCR_CLR_TXF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_CLR_TXF), uint32_t) & BM_SPI_MCR_CLR_TXF)
mbed_official	146:f64d43ff0c18	239
mbed_official	146:f64d43ff0c18	240	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	241	//! @brief Set the CLR_TXF field to a new value.
mbed_official	146:f64d43ff0c18	242	#define BW_SPI_MCR_CLR_TXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CLR_TXF) = (v))
mbed_official	146:f64d43ff0c18	243	#endif
mbed_official	146:f64d43ff0c18	244	//@}
mbed_official	146:f64d43ff0c18	245
mbed_official	146:f64d43ff0c18	246	/*!
mbed_official	146:f64d43ff0c18	247	* @name Register SPI_MCR, field DIS_RXF[12] (RW)
mbed_official	146:f64d43ff0c18	248	*
mbed_official	146:f64d43ff0c18	249	* When the RX FIFO is disabled, the receive part of the module operates as a
mbed_official	146:f64d43ff0c18	250	* simplified double-buffered SPI. This bit can only be written when the MDIS bit
mbed_official	146:f64d43ff0c18	251	* is cleared.
mbed_official	146:f64d43ff0c18	252	*
mbed_official	146:f64d43ff0c18	253	* Values:
mbed_official	146:f64d43ff0c18	254	* - 0 - RX FIFO is enabled.
mbed_official	146:f64d43ff0c18	255	* - 1 - RX FIFO is disabled.
mbed_official	146:f64d43ff0c18	256	*/
mbed_official	146:f64d43ff0c18	257	//@{
mbed_official	146:f64d43ff0c18	258	#define BP_SPI_MCR_DIS_RXF (12U) //!< Bit position for SPI_MCR_DIS_RXF.
mbed_official	146:f64d43ff0c18	259	#define BM_SPI_MCR_DIS_RXF (0x00001000U) //!< Bit mask for SPI_MCR_DIS_RXF.
mbed_official	146:f64d43ff0c18	260	#define BS_SPI_MCR_DIS_RXF (1U) //!< Bit field size in bits for SPI_MCR_DIS_RXF.
mbed_official	146:f64d43ff0c18	261
mbed_official	146:f64d43ff0c18	262	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	263	//! @brief Read current value of the SPI_MCR_DIS_RXF field.
mbed_official	146:f64d43ff0c18	264	#define BR_SPI_MCR_DIS_RXF(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_RXF))
mbed_official	146:f64d43ff0c18	265	#endif
mbed_official	146:f64d43ff0c18	266
mbed_official	146:f64d43ff0c18	267	//! @brief Format value for bitfield SPI_MCR_DIS_RXF.
mbed_official	146:f64d43ff0c18	268	#define BF_SPI_MCR_DIS_RXF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_DIS_RXF), uint32_t) & BM_SPI_MCR_DIS_RXF)
mbed_official	146:f64d43ff0c18	269
mbed_official	146:f64d43ff0c18	270	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	271	//! @brief Set the DIS_RXF field to a new value.
mbed_official	146:f64d43ff0c18	272	#define BW_SPI_MCR_DIS_RXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_RXF) = (v))
mbed_official	146:f64d43ff0c18	273	#endif
mbed_official	146:f64d43ff0c18	274	//@}
mbed_official	146:f64d43ff0c18	275
mbed_official	146:f64d43ff0c18	276	/*!
mbed_official	146:f64d43ff0c18	277	* @name Register SPI_MCR, field DIS_TXF[13] (RW)
mbed_official	146:f64d43ff0c18	278	*
mbed_official	146:f64d43ff0c18	279	* When the TX FIFO is disabled, the transmit part of the module operates as a
mbed_official	146:f64d43ff0c18	280	* simplified double-buffered SPI. This bit can be written only when the MDIS bit
mbed_official	146:f64d43ff0c18	281	* is cleared.
mbed_official	146:f64d43ff0c18	282	*
mbed_official	146:f64d43ff0c18	283	* Values:
mbed_official	146:f64d43ff0c18	284	* - 0 - TX FIFO is enabled.
mbed_official	146:f64d43ff0c18	285	* - 1 - TX FIFO is disabled.
mbed_official	146:f64d43ff0c18	286	*/
mbed_official	146:f64d43ff0c18	287	//@{
mbed_official	146:f64d43ff0c18	288	#define BP_SPI_MCR_DIS_TXF (13U) //!< Bit position for SPI_MCR_DIS_TXF.
mbed_official	146:f64d43ff0c18	289	#define BM_SPI_MCR_DIS_TXF (0x00002000U) //!< Bit mask for SPI_MCR_DIS_TXF.
mbed_official	146:f64d43ff0c18	290	#define BS_SPI_MCR_DIS_TXF (1U) //!< Bit field size in bits for SPI_MCR_DIS_TXF.
mbed_official	146:f64d43ff0c18	291
mbed_official	146:f64d43ff0c18	292	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	293	//! @brief Read current value of the SPI_MCR_DIS_TXF field.
mbed_official	146:f64d43ff0c18	294	#define BR_SPI_MCR_DIS_TXF(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_TXF))
mbed_official	146:f64d43ff0c18	295	#endif
mbed_official	146:f64d43ff0c18	296
mbed_official	146:f64d43ff0c18	297	//! @brief Format value for bitfield SPI_MCR_DIS_TXF.
mbed_official	146:f64d43ff0c18	298	#define BF_SPI_MCR_DIS_TXF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_DIS_TXF), uint32_t) & BM_SPI_MCR_DIS_TXF)
mbed_official	146:f64d43ff0c18	299
mbed_official	146:f64d43ff0c18	300	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	301	//! @brief Set the DIS_TXF field to a new value.
mbed_official	146:f64d43ff0c18	302	#define BW_SPI_MCR_DIS_TXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_TXF) = (v))
mbed_official	146:f64d43ff0c18	303	#endif
mbed_official	146:f64d43ff0c18	304	//@}
mbed_official	146:f64d43ff0c18	305
mbed_official	146:f64d43ff0c18	306	/*!
mbed_official	146:f64d43ff0c18	307	* @name Register SPI_MCR, field MDIS[14] (RW)
mbed_official	146:f64d43ff0c18	308	*
mbed_official	146:f64d43ff0c18	309	* Allows the clock to be stopped to the non-memory mapped logic in the module
mbed_official	146:f64d43ff0c18	310	* effectively putting it in a software-controlled power-saving state. The reset
mbed_official	146:f64d43ff0c18	311	* value of the MDIS bit is parameterized, with a default reset value of 0. When
mbed_official	146:f64d43ff0c18	312	* the module is used in Slave Mode, we recommend leaving this bit 0, because a
mbed_official	146:f64d43ff0c18	313	* slave doesn't have control over master transactions.
mbed_official	146:f64d43ff0c18	314	*
mbed_official	146:f64d43ff0c18	315	* Values:
mbed_official	146:f64d43ff0c18	316	* - 0 - Enables the module clocks.
mbed_official	146:f64d43ff0c18	317	* - 1 - Allows external logic to disable the module clocks.
mbed_official	146:f64d43ff0c18	318	*/
mbed_official	146:f64d43ff0c18	319	//@{
mbed_official	146:f64d43ff0c18	320	#define BP_SPI_MCR_MDIS (14U) //!< Bit position for SPI_MCR_MDIS.
mbed_official	146:f64d43ff0c18	321	#define BM_SPI_MCR_MDIS (0x00004000U) //!< Bit mask for SPI_MCR_MDIS.
mbed_official	146:f64d43ff0c18	322	#define BS_SPI_MCR_MDIS (1U) //!< Bit field size in bits for SPI_MCR_MDIS.
mbed_official	146:f64d43ff0c18	323
mbed_official	146:f64d43ff0c18	324	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	325	//! @brief Read current value of the SPI_MCR_MDIS field.
mbed_official	146:f64d43ff0c18	326	#define BR_SPI_MCR_MDIS(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MDIS))
mbed_official	146:f64d43ff0c18	327	#endif
mbed_official	146:f64d43ff0c18	328
mbed_official	146:f64d43ff0c18	329	//! @brief Format value for bitfield SPI_MCR_MDIS.
mbed_official	146:f64d43ff0c18	330	#define BF_SPI_MCR_MDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_MDIS), uint32_t) & BM_SPI_MCR_MDIS)
mbed_official	146:f64d43ff0c18	331
mbed_official	146:f64d43ff0c18	332	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	333	//! @brief Set the MDIS field to a new value.
mbed_official	146:f64d43ff0c18	334	#define BW_SPI_MCR_MDIS(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MDIS) = (v))
mbed_official	146:f64d43ff0c18	335	#endif
mbed_official	146:f64d43ff0c18	336	//@}
mbed_official	146:f64d43ff0c18	337
mbed_official	146:f64d43ff0c18	338	/*!
mbed_official	146:f64d43ff0c18	339	* @name Register SPI_MCR, field DOZE[15] (RW)
mbed_official	146:f64d43ff0c18	340	*
mbed_official	146:f64d43ff0c18	341	* Provides support for an externally controlled Doze mode power-saving
mbed_official	146:f64d43ff0c18	342	* mechanism.
mbed_official	146:f64d43ff0c18	343	*
mbed_official	146:f64d43ff0c18	344	* Values:
mbed_official	146:f64d43ff0c18	345	* - 0 - Doze mode has no effect on the module.
mbed_official	146:f64d43ff0c18	346	* - 1 - Doze mode disables the module.
mbed_official	146:f64d43ff0c18	347	*/
mbed_official	146:f64d43ff0c18	348	//@{
mbed_official	146:f64d43ff0c18	349	#define BP_SPI_MCR_DOZE (15U) //!< Bit position for SPI_MCR_DOZE.
mbed_official	146:f64d43ff0c18	350	#define BM_SPI_MCR_DOZE (0x00008000U) //!< Bit mask for SPI_MCR_DOZE.
mbed_official	146:f64d43ff0c18	351	#define BS_SPI_MCR_DOZE (1U) //!< Bit field size in bits for SPI_MCR_DOZE.
mbed_official	146:f64d43ff0c18	352
mbed_official	146:f64d43ff0c18	353	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	354	//! @brief Read current value of the SPI_MCR_DOZE field.
mbed_official	146:f64d43ff0c18	355	#define BR_SPI_MCR_DOZE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DOZE))
mbed_official	146:f64d43ff0c18	356	#endif
mbed_official	146:f64d43ff0c18	357
mbed_official	146:f64d43ff0c18	358	//! @brief Format value for bitfield SPI_MCR_DOZE.
mbed_official	146:f64d43ff0c18	359	#define BF_SPI_MCR_DOZE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_DOZE), uint32_t) & BM_SPI_MCR_DOZE)
mbed_official	146:f64d43ff0c18	360
mbed_official	146:f64d43ff0c18	361	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	362	//! @brief Set the DOZE field to a new value.
mbed_official	146:f64d43ff0c18	363	#define BW_SPI_MCR_DOZE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DOZE) = (v))
mbed_official	146:f64d43ff0c18	364	#endif
mbed_official	146:f64d43ff0c18	365	//@}
mbed_official	146:f64d43ff0c18	366
mbed_official	146:f64d43ff0c18	367	/*!
mbed_official	146:f64d43ff0c18	368	* @name Register SPI_MCR, field PCSIS[21:16] (RW)
mbed_official	146:f64d43ff0c18	369	*
mbed_official	146:f64d43ff0c18	370	* Determines the inactive state of PCSx.
mbed_official	146:f64d43ff0c18	371	*
mbed_official	146:f64d43ff0c18	372	* Values:
mbed_official	146:f64d43ff0c18	373	* - 0 - The inactive state of PCSx is low.
mbed_official	146:f64d43ff0c18	374	* - 1 - The inactive state of PCSx is high.
mbed_official	146:f64d43ff0c18	375	*/
mbed_official	146:f64d43ff0c18	376	//@{
mbed_official	146:f64d43ff0c18	377	#define BP_SPI_MCR_PCSIS (16U) //!< Bit position for SPI_MCR_PCSIS.
mbed_official	146:f64d43ff0c18	378	#define BM_SPI_MCR_PCSIS (0x003F0000U) //!< Bit mask for SPI_MCR_PCSIS.
mbed_official	146:f64d43ff0c18	379	#define BS_SPI_MCR_PCSIS (6U) //!< Bit field size in bits for SPI_MCR_PCSIS.
mbed_official	146:f64d43ff0c18	380
mbed_official	146:f64d43ff0c18	381	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	382	//! @brief Read current value of the SPI_MCR_PCSIS field.
mbed_official	146:f64d43ff0c18	383	#define BR_SPI_MCR_PCSIS(x) (HW_SPI_MCR(x).B.PCSIS)
mbed_official	146:f64d43ff0c18	384	#endif
mbed_official	146:f64d43ff0c18	385
mbed_official	146:f64d43ff0c18	386	//! @brief Format value for bitfield SPI_MCR_PCSIS.
mbed_official	146:f64d43ff0c18	387	#define BF_SPI_MCR_PCSIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_PCSIS), uint32_t) & BM_SPI_MCR_PCSIS)
mbed_official	146:f64d43ff0c18	388
mbed_official	146:f64d43ff0c18	389	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	390	//! @brief Set the PCSIS field to a new value.
mbed_official	146:f64d43ff0c18	391	#define BW_SPI_MCR_PCSIS(x, v) (HW_SPI_MCR_WR(x, (HW_SPI_MCR_RD(x) & ~BM_SPI_MCR_PCSIS) \| BF_SPI_MCR_PCSIS(v)))
mbed_official	146:f64d43ff0c18	392	#endif
mbed_official	146:f64d43ff0c18	393	//@}
mbed_official	146:f64d43ff0c18	394
mbed_official	146:f64d43ff0c18	395	/*!
mbed_official	146:f64d43ff0c18	396	* @name Register SPI_MCR, field ROOE[24] (RW)
mbed_official	146:f64d43ff0c18	397	*
mbed_official	146:f64d43ff0c18	398	* In the RX FIFO overflow condition, configures the module to ignore the
mbed_official	146:f64d43ff0c18	399	* incoming serial data or overwrite existing data. If the RX FIFO is full and new data
mbed_official	146:f64d43ff0c18	400	* is received, the data from the transfer, generating the overflow, is ignored
mbed_official	146:f64d43ff0c18	401	* or shifted into the shift register.
mbed_official	146:f64d43ff0c18	402	*
mbed_official	146:f64d43ff0c18	403	* Values:
mbed_official	146:f64d43ff0c18	404	* - 0 - Incoming data is ignored.
mbed_official	146:f64d43ff0c18	405	* - 1 - Incoming data is shifted into the shift register.
mbed_official	146:f64d43ff0c18	406	*/
mbed_official	146:f64d43ff0c18	407	//@{
mbed_official	146:f64d43ff0c18	408	#define BP_SPI_MCR_ROOE (24U) //!< Bit position for SPI_MCR_ROOE.
mbed_official	146:f64d43ff0c18	409	#define BM_SPI_MCR_ROOE (0x01000000U) //!< Bit mask for SPI_MCR_ROOE.
mbed_official	146:f64d43ff0c18	410	#define BS_SPI_MCR_ROOE (1U) //!< Bit field size in bits for SPI_MCR_ROOE.
mbed_official	146:f64d43ff0c18	411
mbed_official	146:f64d43ff0c18	412	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	413	//! @brief Read current value of the SPI_MCR_ROOE field.
mbed_official	146:f64d43ff0c18	414	#define BR_SPI_MCR_ROOE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_ROOE))
mbed_official	146:f64d43ff0c18	415	#endif
mbed_official	146:f64d43ff0c18	416
mbed_official	146:f64d43ff0c18	417	//! @brief Format value for bitfield SPI_MCR_ROOE.
mbed_official	146:f64d43ff0c18	418	#define BF_SPI_MCR_ROOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_ROOE), uint32_t) & BM_SPI_MCR_ROOE)
mbed_official	146:f64d43ff0c18	419
mbed_official	146:f64d43ff0c18	420	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	421	//! @brief Set the ROOE field to a new value.
mbed_official	146:f64d43ff0c18	422	#define BW_SPI_MCR_ROOE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_ROOE) = (v))
mbed_official	146:f64d43ff0c18	423	#endif
mbed_official	146:f64d43ff0c18	424	//@}
mbed_official	146:f64d43ff0c18	425
mbed_official	146:f64d43ff0c18	426	/*!
mbed_official	146:f64d43ff0c18	427	* @name Register SPI_MCR, field PCSSE[25] (RW)
mbed_official	146:f64d43ff0c18	428	*
mbed_official	146:f64d43ff0c18	429	* Enables the PCS5/ PCSS to operate as a PCS Strobe output signal.
mbed_official	146:f64d43ff0c18	430	*
mbed_official	146:f64d43ff0c18	431	* Values:
mbed_official	146:f64d43ff0c18	432	* - 0 - PCS5/ PCSS is used as the Peripheral Chip Select[5] signal.
mbed_official	146:f64d43ff0c18	433	* - 1 - PCS5/ PCSS is used as an active-low PCS Strobe signal.
mbed_official	146:f64d43ff0c18	434	*/
mbed_official	146:f64d43ff0c18	435	//@{
mbed_official	146:f64d43ff0c18	436	#define BP_SPI_MCR_PCSSE (25U) //!< Bit position for SPI_MCR_PCSSE.
mbed_official	146:f64d43ff0c18	437	#define BM_SPI_MCR_PCSSE (0x02000000U) //!< Bit mask for SPI_MCR_PCSSE.
mbed_official	146:f64d43ff0c18	438	#define BS_SPI_MCR_PCSSE (1U) //!< Bit field size in bits for SPI_MCR_PCSSE.
mbed_official	146:f64d43ff0c18	439
mbed_official	146:f64d43ff0c18	440	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	441	//! @brief Read current value of the SPI_MCR_PCSSE field.
mbed_official	146:f64d43ff0c18	442	#define BR_SPI_MCR_PCSSE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_PCSSE))
mbed_official	146:f64d43ff0c18	443	#endif
mbed_official	146:f64d43ff0c18	444
mbed_official	146:f64d43ff0c18	445	//! @brief Format value for bitfield SPI_MCR_PCSSE.
mbed_official	146:f64d43ff0c18	446	#define BF_SPI_MCR_PCSSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_PCSSE), uint32_t) & BM_SPI_MCR_PCSSE)
mbed_official	146:f64d43ff0c18	447
mbed_official	146:f64d43ff0c18	448	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	449	//! @brief Set the PCSSE field to a new value.
mbed_official	146:f64d43ff0c18	450	#define BW_SPI_MCR_PCSSE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_PCSSE) = (v))
mbed_official	146:f64d43ff0c18	451	#endif
mbed_official	146:f64d43ff0c18	452	//@}
mbed_official	146:f64d43ff0c18	453
mbed_official	146:f64d43ff0c18	454	/*!
mbed_official	146:f64d43ff0c18	455	* @name Register SPI_MCR, field MTFE[26] (RW)
mbed_official	146:f64d43ff0c18	456	*
mbed_official	146:f64d43ff0c18	457	* Enables a modified transfer format to be used.
mbed_official	146:f64d43ff0c18	458	*
mbed_official	146:f64d43ff0c18	459	* Values:
mbed_official	146:f64d43ff0c18	460	* - 0 - Modified SPI transfer format disabled.
mbed_official	146:f64d43ff0c18	461	* - 1 - Modified SPI transfer format enabled.
mbed_official	146:f64d43ff0c18	462	*/
mbed_official	146:f64d43ff0c18	463	//@{
mbed_official	146:f64d43ff0c18	464	#define BP_SPI_MCR_MTFE (26U) //!< Bit position for SPI_MCR_MTFE.
mbed_official	146:f64d43ff0c18	465	#define BM_SPI_MCR_MTFE (0x04000000U) //!< Bit mask for SPI_MCR_MTFE.
mbed_official	146:f64d43ff0c18	466	#define BS_SPI_MCR_MTFE (1U) //!< Bit field size in bits for SPI_MCR_MTFE.
mbed_official	146:f64d43ff0c18	467
mbed_official	146:f64d43ff0c18	468	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	469	//! @brief Read current value of the SPI_MCR_MTFE field.
mbed_official	146:f64d43ff0c18	470	#define BR_SPI_MCR_MTFE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MTFE))
mbed_official	146:f64d43ff0c18	471	#endif
mbed_official	146:f64d43ff0c18	472
mbed_official	146:f64d43ff0c18	473	//! @brief Format value for bitfield SPI_MCR_MTFE.
mbed_official	146:f64d43ff0c18	474	#define BF_SPI_MCR_MTFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_MTFE), uint32_t) & BM_SPI_MCR_MTFE)
mbed_official	146:f64d43ff0c18	475
mbed_official	146:f64d43ff0c18	476	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	477	//! @brief Set the MTFE field to a new value.
mbed_official	146:f64d43ff0c18	478	#define BW_SPI_MCR_MTFE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MTFE) = (v))
mbed_official	146:f64d43ff0c18	479	#endif
mbed_official	146:f64d43ff0c18	480	//@}
mbed_official	146:f64d43ff0c18	481
mbed_official	146:f64d43ff0c18	482	/*!
mbed_official	146:f64d43ff0c18	483	* @name Register SPI_MCR, field FRZ[27] (RW)
mbed_official	146:f64d43ff0c18	484	*
mbed_official	146:f64d43ff0c18	485	* Enables transfers to be stopped on the next frame boundary when the device
mbed_official	146:f64d43ff0c18	486	* enters Debug mode.
mbed_official	146:f64d43ff0c18	487	*
mbed_official	146:f64d43ff0c18	488	* Values:
mbed_official	146:f64d43ff0c18	489	* - 0 - Do not halt serial transfers in Debug mode.
mbed_official	146:f64d43ff0c18	490	* - 1 - Halt serial transfers in Debug mode.
mbed_official	146:f64d43ff0c18	491	*/
mbed_official	146:f64d43ff0c18	492	//@{
mbed_official	146:f64d43ff0c18	493	#define BP_SPI_MCR_FRZ (27U) //!< Bit position for SPI_MCR_FRZ.
mbed_official	146:f64d43ff0c18	494	#define BM_SPI_MCR_FRZ (0x08000000U) //!< Bit mask for SPI_MCR_FRZ.
mbed_official	146:f64d43ff0c18	495	#define BS_SPI_MCR_FRZ (1U) //!< Bit field size in bits for SPI_MCR_FRZ.
mbed_official	146:f64d43ff0c18	496
mbed_official	146:f64d43ff0c18	497	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	498	//! @brief Read current value of the SPI_MCR_FRZ field.
mbed_official	146:f64d43ff0c18	499	#define BR_SPI_MCR_FRZ(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_FRZ))
mbed_official	146:f64d43ff0c18	500	#endif
mbed_official	146:f64d43ff0c18	501
mbed_official	146:f64d43ff0c18	502	//! @brief Format value for bitfield SPI_MCR_FRZ.
mbed_official	146:f64d43ff0c18	503	#define BF_SPI_MCR_FRZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_FRZ), uint32_t) & BM_SPI_MCR_FRZ)
mbed_official	146:f64d43ff0c18	504
mbed_official	146:f64d43ff0c18	505	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	506	//! @brief Set the FRZ field to a new value.
mbed_official	146:f64d43ff0c18	507	#define BW_SPI_MCR_FRZ(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_FRZ) = (v))
mbed_official	146:f64d43ff0c18	508	#endif
mbed_official	146:f64d43ff0c18	509	//@}
mbed_official	146:f64d43ff0c18	510
mbed_official	146:f64d43ff0c18	511	/*!
mbed_official	146:f64d43ff0c18	512	* @name Register SPI_MCR, field DCONF[29:28] (RO)
mbed_official	146:f64d43ff0c18	513	*
mbed_official	146:f64d43ff0c18	514	* Selects among the different configurations of the module.
mbed_official	146:f64d43ff0c18	515	*
mbed_official	146:f64d43ff0c18	516	* Values:
mbed_official	146:f64d43ff0c18	517	* - 00 - SPI
mbed_official	146:f64d43ff0c18	518	* - 01 - Reserved
mbed_official	146:f64d43ff0c18	519	* - 10 - Reserved
mbed_official	146:f64d43ff0c18	520	* - 11 - Reserved
mbed_official	146:f64d43ff0c18	521	*/
mbed_official	146:f64d43ff0c18	522	//@{
mbed_official	146:f64d43ff0c18	523	#define BP_SPI_MCR_DCONF (28U) //!< Bit position for SPI_MCR_DCONF.
mbed_official	146:f64d43ff0c18	524	#define BM_SPI_MCR_DCONF (0x30000000U) //!< Bit mask for SPI_MCR_DCONF.
mbed_official	146:f64d43ff0c18	525	#define BS_SPI_MCR_DCONF (2U) //!< Bit field size in bits for SPI_MCR_DCONF.
mbed_official	146:f64d43ff0c18	526
mbed_official	146:f64d43ff0c18	527	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	528	//! @brief Read current value of the SPI_MCR_DCONF field.
mbed_official	146:f64d43ff0c18	529	#define BR_SPI_MCR_DCONF(x) (HW_SPI_MCR(x).B.DCONF)
mbed_official	146:f64d43ff0c18	530	#endif
mbed_official	146:f64d43ff0c18	531	//@}
mbed_official	146:f64d43ff0c18	532
mbed_official	146:f64d43ff0c18	533	/*!
mbed_official	146:f64d43ff0c18	534	* @name Register SPI_MCR, field CONT_SCKE[30] (RW)
mbed_official	146:f64d43ff0c18	535	*
mbed_official	146:f64d43ff0c18	536	* Enables the Serial Communication Clock (SCK) to run continuously.
mbed_official	146:f64d43ff0c18	537	*
mbed_official	146:f64d43ff0c18	538	* Values:
mbed_official	146:f64d43ff0c18	539	* - 0 - Continuous SCK disabled.
mbed_official	146:f64d43ff0c18	540	* - 1 - Continuous SCK enabled.
mbed_official	146:f64d43ff0c18	541	*/
mbed_official	146:f64d43ff0c18	542	//@{
mbed_official	146:f64d43ff0c18	543	#define BP_SPI_MCR_CONT_SCKE (30U) //!< Bit position for SPI_MCR_CONT_SCKE.
mbed_official	146:f64d43ff0c18	544	#define BM_SPI_MCR_CONT_SCKE (0x40000000U) //!< Bit mask for SPI_MCR_CONT_SCKE.
mbed_official	146:f64d43ff0c18	545	#define BS_SPI_MCR_CONT_SCKE (1U) //!< Bit field size in bits for SPI_MCR_CONT_SCKE.
mbed_official	146:f64d43ff0c18	546
mbed_official	146:f64d43ff0c18	547	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	548	//! @brief Read current value of the SPI_MCR_CONT_SCKE field.
mbed_official	146:f64d43ff0c18	549	#define BR_SPI_MCR_CONT_SCKE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CONT_SCKE))
mbed_official	146:f64d43ff0c18	550	#endif
mbed_official	146:f64d43ff0c18	551
mbed_official	146:f64d43ff0c18	552	//! @brief Format value for bitfield SPI_MCR_CONT_SCKE.
mbed_official	146:f64d43ff0c18	553	#define BF_SPI_MCR_CONT_SCKE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_CONT_SCKE), uint32_t) & BM_SPI_MCR_CONT_SCKE)
mbed_official	146:f64d43ff0c18	554
mbed_official	146:f64d43ff0c18	555	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	556	//! @brief Set the CONT_SCKE field to a new value.
mbed_official	146:f64d43ff0c18	557	#define BW_SPI_MCR_CONT_SCKE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CONT_SCKE) = (v))
mbed_official	146:f64d43ff0c18	558	#endif
mbed_official	146:f64d43ff0c18	559	//@}
mbed_official	146:f64d43ff0c18	560
mbed_official	146:f64d43ff0c18	561	/*!
mbed_official	146:f64d43ff0c18	562	* @name Register SPI_MCR, field MSTR[31] (RW)
mbed_official	146:f64d43ff0c18	563	*
mbed_official	146:f64d43ff0c18	564	* Enables either Master mode (if supported) or Slave mode (if supported)
mbed_official	146:f64d43ff0c18	565	* operation.
mbed_official	146:f64d43ff0c18	566	*
mbed_official	146:f64d43ff0c18	567	* Values:
mbed_official	146:f64d43ff0c18	568	* - 0 - Enables Slave mode
mbed_official	146:f64d43ff0c18	569	* - 1 - Enables Master mode
mbed_official	146:f64d43ff0c18	570	*/
mbed_official	146:f64d43ff0c18	571	//@{
mbed_official	146:f64d43ff0c18	572	#define BP_SPI_MCR_MSTR (31U) //!< Bit position for SPI_MCR_MSTR.
mbed_official	146:f64d43ff0c18	573	#define BM_SPI_MCR_MSTR (0x80000000U) //!< Bit mask for SPI_MCR_MSTR.
mbed_official	146:f64d43ff0c18	574	#define BS_SPI_MCR_MSTR (1U) //!< Bit field size in bits for SPI_MCR_MSTR.
mbed_official	146:f64d43ff0c18	575
mbed_official	146:f64d43ff0c18	576	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	577	//! @brief Read current value of the SPI_MCR_MSTR field.
mbed_official	146:f64d43ff0c18	578	#define BR_SPI_MCR_MSTR(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MSTR))
mbed_official	146:f64d43ff0c18	579	#endif
mbed_official	146:f64d43ff0c18	580
mbed_official	146:f64d43ff0c18	581	//! @brief Format value for bitfield SPI_MCR_MSTR.
mbed_official	146:f64d43ff0c18	582	#define BF_SPI_MCR_MSTR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_MSTR), uint32_t) & BM_SPI_MCR_MSTR)
mbed_official	146:f64d43ff0c18	583
mbed_official	146:f64d43ff0c18	584	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	585	//! @brief Set the MSTR field to a new value.
mbed_official	146:f64d43ff0c18	586	#define BW_SPI_MCR_MSTR(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MSTR) = (v))
mbed_official	146:f64d43ff0c18	587	#endif
mbed_official	146:f64d43ff0c18	588	//@}
mbed_official	146:f64d43ff0c18	589
mbed_official	146:f64d43ff0c18	590	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	591	// HW_SPI_TCR - Transfer Count Register
mbed_official	146:f64d43ff0c18	592	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	593
mbed_official	146:f64d43ff0c18	594	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	595	/*!
mbed_official	146:f64d43ff0c18	596	* @brief HW_SPI_TCR - Transfer Count Register (RW)
mbed_official	146:f64d43ff0c18	597	*
mbed_official	146:f64d43ff0c18	598	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	599	*
mbed_official	146:f64d43ff0c18	600	* TCR contains a counter that indicates the number of SPI transfers made. The
mbed_official	146:f64d43ff0c18	601	* transfer counter is intended to assist in queue management. Do not write the
mbed_official	146:f64d43ff0c18	602	* TCR when the module is in the Running state.
mbed_official	146:f64d43ff0c18	603	*/
mbed_official	146:f64d43ff0c18	604	typedef union _hw_spi_tcr
mbed_official	146:f64d43ff0c18	605	{
mbed_official	146:f64d43ff0c18	606	uint32_t U;
mbed_official	146:f64d43ff0c18	607	struct _hw_spi_tcr_bitfields
mbed_official	146:f64d43ff0c18	608	{
mbed_official	146:f64d43ff0c18	609	uint32_t RESERVED0 : 16; //!< [15:0]
mbed_official	146:f64d43ff0c18	610	uint32_t SPI_TCNT : 16; //!< [31:16] SPI Transfer Counter
mbed_official	146:f64d43ff0c18	611	} B;
mbed_official	146:f64d43ff0c18	612	} hw_spi_tcr_t;
mbed_official	146:f64d43ff0c18	613	#endif
mbed_official	146:f64d43ff0c18	614
mbed_official	146:f64d43ff0c18	615	/*!
mbed_official	146:f64d43ff0c18	616	* @name Constants and macros for entire SPI_TCR register
mbed_official	146:f64d43ff0c18	617	*/
mbed_official	146:f64d43ff0c18	618	//@{
mbed_official	146:f64d43ff0c18	619	#define HW_SPI_TCR_ADDR(x) (REGS_SPI_BASE(x) + 0x8U)
mbed_official	146:f64d43ff0c18	620
mbed_official	146:f64d43ff0c18	621	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	622	#define HW_SPI_TCR(x) ((__IO hw_spi_tcr_t ) HW_SPI_TCR_ADDR(x))
mbed_official	146:f64d43ff0c18	623	#define HW_SPI_TCR_RD(x) (HW_SPI_TCR(x).U)
mbed_official	146:f64d43ff0c18	624	#define HW_SPI_TCR_WR(x, v) (HW_SPI_TCR(x).U = (v))
mbed_official	146:f64d43ff0c18	625	#define HW_SPI_TCR_SET(x, v) (HW_SPI_TCR_WR(x, HW_SPI_TCR_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	626	#define HW_SPI_TCR_CLR(x, v) (HW_SPI_TCR_WR(x, HW_SPI_TCR_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	627	#define HW_SPI_TCR_TOG(x, v) (HW_SPI_TCR_WR(x, HW_SPI_TCR_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	628	#endif
mbed_official	146:f64d43ff0c18	629	//@}
mbed_official	146:f64d43ff0c18	630
mbed_official	146:f64d43ff0c18	631	/*
mbed_official	146:f64d43ff0c18	632	* Constants & macros for individual SPI_TCR bitfields
mbed_official	146:f64d43ff0c18	633	*/
mbed_official	146:f64d43ff0c18	634
mbed_official	146:f64d43ff0c18	635	/*!
mbed_official	146:f64d43ff0c18	636	* @name Register SPI_TCR, field SPI_TCNT[31:16] (RW)
mbed_official	146:f64d43ff0c18	637	*
mbed_official	146:f64d43ff0c18	638	* Counts the number of SPI transfers the module makes. The SPI_TCNT field
mbed_official	146:f64d43ff0c18	639	* increments every time the last bit of an SPI frame is transmitted. A value written
mbed_official	146:f64d43ff0c18	640	* to SPI_TCNT presets the counter to that value. SPI_TCNT is reset to zero at
mbed_official	146:f64d43ff0c18	641	* the beginning of the frame when the CTCNT field is set in the executing SPI
mbed_official	146:f64d43ff0c18	642	* command. The Transfer Counter wraps around; incrementing the counter past 65535
mbed_official	146:f64d43ff0c18	643	* resets the counter to zero.
mbed_official	146:f64d43ff0c18	644	*/
mbed_official	146:f64d43ff0c18	645	//@{
mbed_official	146:f64d43ff0c18	646	#define BP_SPI_TCR_SPI_TCNT (16U) //!< Bit position for SPI_TCR_SPI_TCNT.
mbed_official	146:f64d43ff0c18	647	#define BM_SPI_TCR_SPI_TCNT (0xFFFF0000U) //!< Bit mask for SPI_TCR_SPI_TCNT.
mbed_official	146:f64d43ff0c18	648	#define BS_SPI_TCR_SPI_TCNT (16U) //!< Bit field size in bits for SPI_TCR_SPI_TCNT.
mbed_official	146:f64d43ff0c18	649
mbed_official	146:f64d43ff0c18	650	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	651	//! @brief Read current value of the SPI_TCR_SPI_TCNT field.
mbed_official	146:f64d43ff0c18	652	#define BR_SPI_TCR_SPI_TCNT(x) (HW_SPI_TCR(x).B.SPI_TCNT)
mbed_official	146:f64d43ff0c18	653	#endif
mbed_official	146:f64d43ff0c18	654
mbed_official	146:f64d43ff0c18	655	//! @brief Format value for bitfield SPI_TCR_SPI_TCNT.
mbed_official	146:f64d43ff0c18	656	#define BF_SPI_TCR_SPI_TCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_TCR_SPI_TCNT), uint32_t) & BM_SPI_TCR_SPI_TCNT)
mbed_official	146:f64d43ff0c18	657
mbed_official	146:f64d43ff0c18	658	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	659	//! @brief Set the SPI_TCNT field to a new value.
mbed_official	146:f64d43ff0c18	660	#define BW_SPI_TCR_SPI_TCNT(x, v) (HW_SPI_TCR_WR(x, (HW_SPI_TCR_RD(x) & ~BM_SPI_TCR_SPI_TCNT) \| BF_SPI_TCR_SPI_TCNT(v)))
mbed_official	146:f64d43ff0c18	661	#endif
mbed_official	146:f64d43ff0c18	662	//@}
mbed_official	146:f64d43ff0c18	663
mbed_official	146:f64d43ff0c18	664	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	665	// HW_SPI_CTARn - Clock and Transfer Attributes Register (In Master Mode)
mbed_official	146:f64d43ff0c18	666	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	667
mbed_official	146:f64d43ff0c18	668	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	669	/*!
mbed_official	146:f64d43ff0c18	670	* @brief HW_SPI_CTARn - Clock and Transfer Attributes Register (In Master Mode) (RW)
mbed_official	146:f64d43ff0c18	671	*
mbed_official	146:f64d43ff0c18	672	* Reset value: 0x78000000U
mbed_official	146:f64d43ff0c18	673	*
mbed_official	146:f64d43ff0c18	674	* CTAR registers are used to define different transfer attributes. Do not write
mbed_official	146:f64d43ff0c18	675	* to the CTAR registers while the module is in the Running state. In Master
mbed_official	146:f64d43ff0c18	676	* mode, the CTAR registers define combinations of transfer attributes such as frame
mbed_official	146:f64d43ff0c18	677	* size, clock phase and polarity, data bit ordering, baud rate, and various
mbed_official	146:f64d43ff0c18	678	* delays. In slave mode, a subset of the bitfields in CTAR0 are used to set the
mbed_official	146:f64d43ff0c18	679	* slave transfer attributes. When the module is configured as an SPI master, the
mbed_official	146:f64d43ff0c18	680	* CTAS field in the command portion of the TX FIFO entry selects which of the CTAR
mbed_official	146:f64d43ff0c18	681	* registers is used. When the module is configured as an SPI bus slave, it uses
mbed_official	146:f64d43ff0c18	682	* the CTAR0 register.
mbed_official	146:f64d43ff0c18	683	*/
mbed_official	146:f64d43ff0c18	684	typedef union _hw_spi_ctarn
mbed_official	146:f64d43ff0c18	685	{
mbed_official	146:f64d43ff0c18	686	uint32_t U;
mbed_official	146:f64d43ff0c18	687	struct _hw_spi_ctarn_bitfields
mbed_official	146:f64d43ff0c18	688	{
mbed_official	146:f64d43ff0c18	689	uint32_t BR : 4; //!< [3:0] Baud Rate Scaler
mbed_official	146:f64d43ff0c18	690	uint32_t DT : 4; //!< [7:4] Delay After Transfer Scaler
mbed_official	146:f64d43ff0c18	691	uint32_t ASC : 4; //!< [11:8] After SCK Delay Scaler
mbed_official	146:f64d43ff0c18	692	uint32_t CSSCK : 4; //!< [15:12] PCS to SCK Delay Scaler
mbed_official	146:f64d43ff0c18	693	uint32_t PBR : 2; //!< [17:16] Baud Rate Prescaler
mbed_official	146:f64d43ff0c18	694	uint32_t PDT : 2; //!< [19:18] Delay after Transfer Prescaler
mbed_official	146:f64d43ff0c18	695	uint32_t PASC : 2; //!< [21:20] After SCK Delay Prescaler
mbed_official	146:f64d43ff0c18	696	uint32_t PCSSCK : 2; //!< [23:22] PCS to SCK Delay Prescaler
mbed_official	146:f64d43ff0c18	697	uint32_t LSBFE : 1; //!< [24] LSB First
mbed_official	146:f64d43ff0c18	698	uint32_t CPHA : 1; //!< [25] Clock Phase
mbed_official	146:f64d43ff0c18	699	uint32_t CPOL : 1; //!< [26] Clock Polarity
mbed_official	146:f64d43ff0c18	700	uint32_t FMSZ : 4; //!< [30:27] Frame Size
mbed_official	146:f64d43ff0c18	701	uint32_t DBR : 1; //!< [31] Double Baud Rate
mbed_official	146:f64d43ff0c18	702	} B;
mbed_official	146:f64d43ff0c18	703	} hw_spi_ctarn_t;
mbed_official	146:f64d43ff0c18	704	#endif
mbed_official	146:f64d43ff0c18	705
mbed_official	146:f64d43ff0c18	706	/*!
mbed_official	146:f64d43ff0c18	707	* @name Constants and macros for entire SPI_CTARn register
mbed_official	146:f64d43ff0c18	708	*/
mbed_official	146:f64d43ff0c18	709	//@{
mbed_official	146:f64d43ff0c18	710	#define HW_SPI_CTARn_COUNT (2U)
mbed_official	146:f64d43ff0c18	711
mbed_official	146:f64d43ff0c18	712	#define HW_SPI_CTARn_ADDR(x, n) (REGS_SPI_BASE(x) + 0xCU + (0x4U * n))
mbed_official	146:f64d43ff0c18	713
mbed_official	146:f64d43ff0c18	714	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	715	#define HW_SPI_CTARn(x, n) ((__IO hw_spi_ctarn_t ) HW_SPI_CTARn_ADDR(x, n))
mbed_official	146:f64d43ff0c18	716	#define HW_SPI_CTARn_RD(x, n) (HW_SPI_CTARn(x, n).U)
mbed_official	146:f64d43ff0c18	717	#define HW_SPI_CTARn_WR(x, n, v) (HW_SPI_CTARn(x, n).U = (v))
mbed_official	146:f64d43ff0c18	718	#define HW_SPI_CTARn_SET(x, n, v) (HW_SPI_CTARn_WR(x, n, HW_SPI_CTARn_RD(x, n) \| (v)))
mbed_official	146:f64d43ff0c18	719	#define HW_SPI_CTARn_CLR(x, n, v) (HW_SPI_CTARn_WR(x, n, HW_SPI_CTARn_RD(x, n) & ~(v)))
mbed_official	146:f64d43ff0c18	720	#define HW_SPI_CTARn_TOG(x, n, v) (HW_SPI_CTARn_WR(x, n, HW_SPI_CTARn_RD(x, n) ^ (v)))
mbed_official	146:f64d43ff0c18	721	#endif
mbed_official	146:f64d43ff0c18	722	//@}
mbed_official	146:f64d43ff0c18	723
mbed_official	146:f64d43ff0c18	724	/*
mbed_official	146:f64d43ff0c18	725	* Constants & macros for individual SPI_CTARn bitfields
mbed_official	146:f64d43ff0c18	726	*/
mbed_official	146:f64d43ff0c18	727
mbed_official	146:f64d43ff0c18	728	/*!
mbed_official	146:f64d43ff0c18	729	* @name Register SPI_CTARn, field BR[3:0] (RW)
mbed_official	146:f64d43ff0c18	730	*
mbed_official	146:f64d43ff0c18	731	* Selects the scaler value for the baud rate. This field is used only in master
mbed_official	146:f64d43ff0c18	732	* mode. The prescaled protocol clock is divided by the Baud Rate Scaler to
mbed_official	146:f64d43ff0c18	733	* generate the frequency of the SCK. The baud rate is computed according to the
mbed_official	146:f64d43ff0c18	734	* following equation: SCK baud rate = (fP /PBR) x [(1+DBR)/BR] The following table
mbed_official	146:f64d43ff0c18	735	* lists the baud rate scaler values. Baud Rate Scaler CTARn[BR] Baud Rate Scaler
mbed_official	146:f64d43ff0c18	736	* Value 0000 2 0001 4 0010 6 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256
mbed_official	146:f64d43ff0c18	737	* 1001 512 1010 1024 1011 2048 1100 4096 1101 8192 1110 16384 1111 32768
mbed_official	146:f64d43ff0c18	738	*/
mbed_official	146:f64d43ff0c18	739	//@{
mbed_official	146:f64d43ff0c18	740	#define BP_SPI_CTARn_BR (0U) //!< Bit position for SPI_CTARn_BR.
mbed_official	146:f64d43ff0c18	741	#define BM_SPI_CTARn_BR (0x0000000FU) //!< Bit mask for SPI_CTARn_BR.
mbed_official	146:f64d43ff0c18	742	#define BS_SPI_CTARn_BR (4U) //!< Bit field size in bits for SPI_CTARn_BR.
mbed_official	146:f64d43ff0c18	743
mbed_official	146:f64d43ff0c18	744	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	745	//! @brief Read current value of the SPI_CTARn_BR field.
mbed_official	146:f64d43ff0c18	746	#define BR_SPI_CTARn_BR(x, n) (HW_SPI_CTARn(x, n).B.BR)
mbed_official	146:f64d43ff0c18	747	#endif
mbed_official	146:f64d43ff0c18	748
mbed_official	146:f64d43ff0c18	749	//! @brief Format value for bitfield SPI_CTARn_BR.
mbed_official	146:f64d43ff0c18	750	#define BF_SPI_CTARn_BR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_BR), uint32_t) & BM_SPI_CTARn_BR)
mbed_official	146:f64d43ff0c18	751
mbed_official	146:f64d43ff0c18	752	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	753	//! @brief Set the BR field to a new value.
mbed_official	146:f64d43ff0c18	754	#define BW_SPI_CTARn_BR(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_BR) \| BF_SPI_CTARn_BR(v)))
mbed_official	146:f64d43ff0c18	755	#endif
mbed_official	146:f64d43ff0c18	756	//@}
mbed_official	146:f64d43ff0c18	757
mbed_official	146:f64d43ff0c18	758	/*!
mbed_official	146:f64d43ff0c18	759	* @name Register SPI_CTARn, field DT[7:4] (RW)
mbed_official	146:f64d43ff0c18	760	*
mbed_official	146:f64d43ff0c18	761	* Selects the Delay after Transfer Scaler. This field is used only in master
mbed_official	146:f64d43ff0c18	762	* mode. The Delay after Transfer is the time between the negation of the PCS
mbed_official	146:f64d43ff0c18	763	* signal at the end of a frame and the assertion of PCS at the beginning of the next
mbed_official	146:f64d43ff0c18	764	* frame. In the Continuous Serial Communications Clock operation, the DT value
mbed_official	146:f64d43ff0c18	765	* is fixed to one SCK clock period, The Delay after Transfer is a multiple of the
mbed_official	146:f64d43ff0c18	766	* protocol clock period, and it is computed according to the following
mbed_official	146:f64d43ff0c18	767	* equation: tDT = (1/fP ) x PDT x DT See Delay Scaler Encoding table in CTARn[CSSCK] bit
mbed_official	146:f64d43ff0c18	768	* field description for scaler values.
mbed_official	146:f64d43ff0c18	769	*/
mbed_official	146:f64d43ff0c18	770	//@{
mbed_official	146:f64d43ff0c18	771	#define BP_SPI_CTARn_DT (4U) //!< Bit position for SPI_CTARn_DT.
mbed_official	146:f64d43ff0c18	772	#define BM_SPI_CTARn_DT (0x000000F0U) //!< Bit mask for SPI_CTARn_DT.
mbed_official	146:f64d43ff0c18	773	#define BS_SPI_CTARn_DT (4U) //!< Bit field size in bits for SPI_CTARn_DT.
mbed_official	146:f64d43ff0c18	774
mbed_official	146:f64d43ff0c18	775	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	776	//! @brief Read current value of the SPI_CTARn_DT field.
mbed_official	146:f64d43ff0c18	777	#define BR_SPI_CTARn_DT(x, n) (HW_SPI_CTARn(x, n).B.DT)
mbed_official	146:f64d43ff0c18	778	#endif
mbed_official	146:f64d43ff0c18	779
mbed_official	146:f64d43ff0c18	780	//! @brief Format value for bitfield SPI_CTARn_DT.
mbed_official	146:f64d43ff0c18	781	#define BF_SPI_CTARn_DT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_DT), uint32_t) & BM_SPI_CTARn_DT)
mbed_official	146:f64d43ff0c18	782
mbed_official	146:f64d43ff0c18	783	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	784	//! @brief Set the DT field to a new value.
mbed_official	146:f64d43ff0c18	785	#define BW_SPI_CTARn_DT(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_DT) \| BF_SPI_CTARn_DT(v)))
mbed_official	146:f64d43ff0c18	786	#endif
mbed_official	146:f64d43ff0c18	787	//@}
mbed_official	146:f64d43ff0c18	788
mbed_official	146:f64d43ff0c18	789	/*!
mbed_official	146:f64d43ff0c18	790	* @name Register SPI_CTARn, field ASC[11:8] (RW)
mbed_official	146:f64d43ff0c18	791	*
mbed_official	146:f64d43ff0c18	792	* Selects the scaler value for the After SCK Delay. This field is used only in
mbed_official	146:f64d43ff0c18	793	* master mode. The After SCK Delay is the delay between the last edge of SCK and
mbed_official	146:f64d43ff0c18	794	* the negation of PCS. The delay is a multiple of the protocol clock period,
mbed_official	146:f64d43ff0c18	795	* and it is computed according to the following equation: t ASC = (1/fP) x PASC x
mbed_official	146:f64d43ff0c18	796	* ASC See Delay Scaler Encoding table in CTARn[CSSCK] bit field description for
mbed_official	146:f64d43ff0c18	797	* scaler values. Refer After SCK Delay (tASC ) for more details.
mbed_official	146:f64d43ff0c18	798	*/
mbed_official	146:f64d43ff0c18	799	//@{
mbed_official	146:f64d43ff0c18	800	#define BP_SPI_CTARn_ASC (8U) //!< Bit position for SPI_CTARn_ASC.
mbed_official	146:f64d43ff0c18	801	#define BM_SPI_CTARn_ASC (0x00000F00U) //!< Bit mask for SPI_CTARn_ASC.
mbed_official	146:f64d43ff0c18	802	#define BS_SPI_CTARn_ASC (4U) //!< Bit field size in bits for SPI_CTARn_ASC.
mbed_official	146:f64d43ff0c18	803
mbed_official	146:f64d43ff0c18	804	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	805	//! @brief Read current value of the SPI_CTARn_ASC field.
mbed_official	146:f64d43ff0c18	806	#define BR_SPI_CTARn_ASC(x, n) (HW_SPI_CTARn(x, n).B.ASC)
mbed_official	146:f64d43ff0c18	807	#endif
mbed_official	146:f64d43ff0c18	808
mbed_official	146:f64d43ff0c18	809	//! @brief Format value for bitfield SPI_CTARn_ASC.
mbed_official	146:f64d43ff0c18	810	#define BF_SPI_CTARn_ASC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_ASC), uint32_t) & BM_SPI_CTARn_ASC)
mbed_official	146:f64d43ff0c18	811
mbed_official	146:f64d43ff0c18	812	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	813	//! @brief Set the ASC field to a new value.
mbed_official	146:f64d43ff0c18	814	#define BW_SPI_CTARn_ASC(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_ASC) \| BF_SPI_CTARn_ASC(v)))
mbed_official	146:f64d43ff0c18	815	#endif
mbed_official	146:f64d43ff0c18	816	//@}
mbed_official	146:f64d43ff0c18	817
mbed_official	146:f64d43ff0c18	818	/*!
mbed_official	146:f64d43ff0c18	819	* @name Register SPI_CTARn, field CSSCK[15:12] (RW)
mbed_official	146:f64d43ff0c18	820	*
mbed_official	146:f64d43ff0c18	821	* Selects the scaler value for the PCS to SCK delay. This field is used only in
mbed_official	146:f64d43ff0c18	822	* master mode. The PCS to SCK Delay is the delay between the assertion of PCS
mbed_official	146:f64d43ff0c18	823	* and the first edge of the SCK. The delay is a multiple of the protocol clock
mbed_official	146:f64d43ff0c18	824	* period, and it is computed according to the following equation: t CSC = (1/fP )
mbed_official	146:f64d43ff0c18	825	* x PCSSCK x CSSCK. The following table lists the delay scaler values. Delay
mbed_official	146:f64d43ff0c18	826	* Scaler Encoding Field Value Delay Scaler Value 0000 2 0001 4 0010 8 0011 16 0100
mbed_official	146:f64d43ff0c18	827	* 32 0101 64 0110 128 0111 256 1000 512 1001 1024 1010 2048 1011 4096 1100 8192
mbed_official	146:f64d43ff0c18	828	* 1101 16384 1110 32768 1111 65536 Refer PCS to SCK Delay (tCSC ) for more
mbed_official	146:f64d43ff0c18	829	* details.
mbed_official	146:f64d43ff0c18	830	*/
mbed_official	146:f64d43ff0c18	831	//@{
mbed_official	146:f64d43ff0c18	832	#define BP_SPI_CTARn_CSSCK (12U) //!< Bit position for SPI_CTARn_CSSCK.
mbed_official	146:f64d43ff0c18	833	#define BM_SPI_CTARn_CSSCK (0x0000F000U) //!< Bit mask for SPI_CTARn_CSSCK.
mbed_official	146:f64d43ff0c18	834	#define BS_SPI_CTARn_CSSCK (4U) //!< Bit field size in bits for SPI_CTARn_CSSCK.
mbed_official	146:f64d43ff0c18	835
mbed_official	146:f64d43ff0c18	836	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	837	//! @brief Read current value of the SPI_CTARn_CSSCK field.
mbed_official	146:f64d43ff0c18	838	#define BR_SPI_CTARn_CSSCK(x, n) (HW_SPI_CTARn(x, n).B.CSSCK)
mbed_official	146:f64d43ff0c18	839	#endif
mbed_official	146:f64d43ff0c18	840
mbed_official	146:f64d43ff0c18	841	//! @brief Format value for bitfield SPI_CTARn_CSSCK.
mbed_official	146:f64d43ff0c18	842	#define BF_SPI_CTARn_CSSCK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_CSSCK), uint32_t) & BM_SPI_CTARn_CSSCK)
mbed_official	146:f64d43ff0c18	843
mbed_official	146:f64d43ff0c18	844	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	845	//! @brief Set the CSSCK field to a new value.
mbed_official	146:f64d43ff0c18	846	#define BW_SPI_CTARn_CSSCK(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_CSSCK) \| BF_SPI_CTARn_CSSCK(v)))
mbed_official	146:f64d43ff0c18	847	#endif
mbed_official	146:f64d43ff0c18	848	//@}
mbed_official	146:f64d43ff0c18	849
mbed_official	146:f64d43ff0c18	850	/*!
mbed_official	146:f64d43ff0c18	851	* @name Register SPI_CTARn, field PBR[17:16] (RW)
mbed_official	146:f64d43ff0c18	852	*
mbed_official	146:f64d43ff0c18	853	* Selects the prescaler value for the baud rate. This field is used only in
mbed_official	146:f64d43ff0c18	854	* master mode. The baud rate is the frequency of the SCK. The protocol clock is
mbed_official	146:f64d43ff0c18	855	* divided by the prescaler value before the baud rate selection takes place. See
mbed_official	146:f64d43ff0c18	856	* the BR field description for details on how to compute the baud rate.
mbed_official	146:f64d43ff0c18	857	*
mbed_official	146:f64d43ff0c18	858	* Values:
mbed_official	146:f64d43ff0c18	859	* - 00 - Baud Rate Prescaler value is 2.
mbed_official	146:f64d43ff0c18	860	* - 01 - Baud Rate Prescaler value is 3.
mbed_official	146:f64d43ff0c18	861	* - 10 - Baud Rate Prescaler value is 5.
mbed_official	146:f64d43ff0c18	862	* - 11 - Baud Rate Prescaler value is 7.
mbed_official	146:f64d43ff0c18	863	*/
mbed_official	146:f64d43ff0c18	864	//@{
mbed_official	146:f64d43ff0c18	865	#define BP_SPI_CTARn_PBR (16U) //!< Bit position for SPI_CTARn_PBR.
mbed_official	146:f64d43ff0c18	866	#define BM_SPI_CTARn_PBR (0x00030000U) //!< Bit mask for SPI_CTARn_PBR.
mbed_official	146:f64d43ff0c18	867	#define BS_SPI_CTARn_PBR (2U) //!< Bit field size in bits for SPI_CTARn_PBR.
mbed_official	146:f64d43ff0c18	868
mbed_official	146:f64d43ff0c18	869	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	870	//! @brief Read current value of the SPI_CTARn_PBR field.
mbed_official	146:f64d43ff0c18	871	#define BR_SPI_CTARn_PBR(x, n) (HW_SPI_CTARn(x, n).B.PBR)
mbed_official	146:f64d43ff0c18	872	#endif
mbed_official	146:f64d43ff0c18	873
mbed_official	146:f64d43ff0c18	874	//! @brief Format value for bitfield SPI_CTARn_PBR.
mbed_official	146:f64d43ff0c18	875	#define BF_SPI_CTARn_PBR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_PBR), uint32_t) & BM_SPI_CTARn_PBR)
mbed_official	146:f64d43ff0c18	876
mbed_official	146:f64d43ff0c18	877	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	878	//! @brief Set the PBR field to a new value.
mbed_official	146:f64d43ff0c18	879	#define BW_SPI_CTARn_PBR(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PBR) \| BF_SPI_CTARn_PBR(v)))
mbed_official	146:f64d43ff0c18	880	#endif
mbed_official	146:f64d43ff0c18	881	//@}
mbed_official	146:f64d43ff0c18	882
mbed_official	146:f64d43ff0c18	883	/*!
mbed_official	146:f64d43ff0c18	884	* @name Register SPI_CTARn, field PDT[19:18] (RW)
mbed_official	146:f64d43ff0c18	885	*
mbed_official	146:f64d43ff0c18	886	* Selects the prescaler value for the delay between the negation of the PCS
mbed_official	146:f64d43ff0c18	887	* signal at the end of a frame and the assertion of PCS at the beginning of the
mbed_official	146:f64d43ff0c18	888	* next frame. The PDT field is only used in master mode. See the DT field
mbed_official	146:f64d43ff0c18	889	* description for details on how to compute the Delay after Transfer. Refer Delay after
mbed_official	146:f64d43ff0c18	890	* Transfer (tDT ) for more details.
mbed_official	146:f64d43ff0c18	891	*
mbed_official	146:f64d43ff0c18	892	* Values:
mbed_official	146:f64d43ff0c18	893	* - 00 - Delay after Transfer Prescaler value is 1.
mbed_official	146:f64d43ff0c18	894	* - 01 - Delay after Transfer Prescaler value is 3.
mbed_official	146:f64d43ff0c18	895	* - 10 - Delay after Transfer Prescaler value is 5.
mbed_official	146:f64d43ff0c18	896	* - 11 - Delay after Transfer Prescaler value is 7.
mbed_official	146:f64d43ff0c18	897	*/
mbed_official	146:f64d43ff0c18	898	//@{
mbed_official	146:f64d43ff0c18	899	#define BP_SPI_CTARn_PDT (18U) //!< Bit position for SPI_CTARn_PDT.
mbed_official	146:f64d43ff0c18	900	#define BM_SPI_CTARn_PDT (0x000C0000U) //!< Bit mask for SPI_CTARn_PDT.
mbed_official	146:f64d43ff0c18	901	#define BS_SPI_CTARn_PDT (2U) //!< Bit field size in bits for SPI_CTARn_PDT.
mbed_official	146:f64d43ff0c18	902
mbed_official	146:f64d43ff0c18	903	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	904	//! @brief Read current value of the SPI_CTARn_PDT field.
mbed_official	146:f64d43ff0c18	905	#define BR_SPI_CTARn_PDT(x, n) (HW_SPI_CTARn(x, n).B.PDT)
mbed_official	146:f64d43ff0c18	906	#endif
mbed_official	146:f64d43ff0c18	907
mbed_official	146:f64d43ff0c18	908	//! @brief Format value for bitfield SPI_CTARn_PDT.
mbed_official	146:f64d43ff0c18	909	#define BF_SPI_CTARn_PDT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_PDT), uint32_t) & BM_SPI_CTARn_PDT)
mbed_official	146:f64d43ff0c18	910
mbed_official	146:f64d43ff0c18	911	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	912	//! @brief Set the PDT field to a new value.
mbed_official	146:f64d43ff0c18	913	#define BW_SPI_CTARn_PDT(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PDT) \| BF_SPI_CTARn_PDT(v)))
mbed_official	146:f64d43ff0c18	914	#endif
mbed_official	146:f64d43ff0c18	915	//@}
mbed_official	146:f64d43ff0c18	916
mbed_official	146:f64d43ff0c18	917	/*!
mbed_official	146:f64d43ff0c18	918	* @name Register SPI_CTARn, field PASC[21:20] (RW)
mbed_official	146:f64d43ff0c18	919	*
mbed_official	146:f64d43ff0c18	920	* Selects the prescaler value for the delay between the last edge of SCK and
mbed_official	146:f64d43ff0c18	921	* the negation of PCS. See the ASC field description for information on how to
mbed_official	146:f64d43ff0c18	922	* compute the After SCK Delay. Refer After SCK Delay (tASC ) for more details.
mbed_official	146:f64d43ff0c18	923	*
mbed_official	146:f64d43ff0c18	924	* Values:
mbed_official	146:f64d43ff0c18	925	* - 00 - Delay after Transfer Prescaler value is 1.
mbed_official	146:f64d43ff0c18	926	* - 01 - Delay after Transfer Prescaler value is 3.
mbed_official	146:f64d43ff0c18	927	* - 10 - Delay after Transfer Prescaler value is 5.
mbed_official	146:f64d43ff0c18	928	* - 11 - Delay after Transfer Prescaler value is 7.
mbed_official	146:f64d43ff0c18	929	*/
mbed_official	146:f64d43ff0c18	930	//@{
mbed_official	146:f64d43ff0c18	931	#define BP_SPI_CTARn_PASC (20U) //!< Bit position for SPI_CTARn_PASC.
mbed_official	146:f64d43ff0c18	932	#define BM_SPI_CTARn_PASC (0x00300000U) //!< Bit mask for SPI_CTARn_PASC.
mbed_official	146:f64d43ff0c18	933	#define BS_SPI_CTARn_PASC (2U) //!< Bit field size in bits for SPI_CTARn_PASC.
mbed_official	146:f64d43ff0c18	934
mbed_official	146:f64d43ff0c18	935	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	936	//! @brief Read current value of the SPI_CTARn_PASC field.
mbed_official	146:f64d43ff0c18	937	#define BR_SPI_CTARn_PASC(x, n) (HW_SPI_CTARn(x, n).B.PASC)
mbed_official	146:f64d43ff0c18	938	#endif
mbed_official	146:f64d43ff0c18	939
mbed_official	146:f64d43ff0c18	940	//! @brief Format value for bitfield SPI_CTARn_PASC.
mbed_official	146:f64d43ff0c18	941	#define BF_SPI_CTARn_PASC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_PASC), uint32_t) & BM_SPI_CTARn_PASC)
mbed_official	146:f64d43ff0c18	942
mbed_official	146:f64d43ff0c18	943	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	944	//! @brief Set the PASC field to a new value.
mbed_official	146:f64d43ff0c18	945	#define BW_SPI_CTARn_PASC(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PASC) \| BF_SPI_CTARn_PASC(v)))
mbed_official	146:f64d43ff0c18	946	#endif
mbed_official	146:f64d43ff0c18	947	//@}
mbed_official	146:f64d43ff0c18	948
mbed_official	146:f64d43ff0c18	949	/*!
mbed_official	146:f64d43ff0c18	950	* @name Register SPI_CTARn, field PCSSCK[23:22] (RW)
mbed_official	146:f64d43ff0c18	951	*
mbed_official	146:f64d43ff0c18	952	* Selects the prescaler value for the delay between assertion of PCS and the
mbed_official	146:f64d43ff0c18	953	* first edge of the SCK. See the CSSCK field description for information on how to
mbed_official	146:f64d43ff0c18	954	* compute the PCS to SCK Delay. Refer PCS to SCK Delay (tCSC ) for more details.
mbed_official	146:f64d43ff0c18	955	*
mbed_official	146:f64d43ff0c18	956	* Values:
mbed_official	146:f64d43ff0c18	957	* - 00 - PCS to SCK Prescaler value is 1.
mbed_official	146:f64d43ff0c18	958	* - 01 - PCS to SCK Prescaler value is 3.
mbed_official	146:f64d43ff0c18	959	* - 10 - PCS to SCK Prescaler value is 5.
mbed_official	146:f64d43ff0c18	960	* - 11 - PCS to SCK Prescaler value is 7.
mbed_official	146:f64d43ff0c18	961	*/
mbed_official	146:f64d43ff0c18	962	//@{
mbed_official	146:f64d43ff0c18	963	#define BP_SPI_CTARn_PCSSCK (22U) //!< Bit position for SPI_CTARn_PCSSCK.
mbed_official	146:f64d43ff0c18	964	#define BM_SPI_CTARn_PCSSCK (0x00C00000U) //!< Bit mask for SPI_CTARn_PCSSCK.
mbed_official	146:f64d43ff0c18	965	#define BS_SPI_CTARn_PCSSCK (2U) //!< Bit field size in bits for SPI_CTARn_PCSSCK.
mbed_official	146:f64d43ff0c18	966
mbed_official	146:f64d43ff0c18	967	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	968	//! @brief Read current value of the SPI_CTARn_PCSSCK field.
mbed_official	146:f64d43ff0c18	969	#define BR_SPI_CTARn_PCSSCK(x, n) (HW_SPI_CTARn(x, n).B.PCSSCK)
mbed_official	146:f64d43ff0c18	970	#endif
mbed_official	146:f64d43ff0c18	971
mbed_official	146:f64d43ff0c18	972	//! @brief Format value for bitfield SPI_CTARn_PCSSCK.
mbed_official	146:f64d43ff0c18	973	#define BF_SPI_CTARn_PCSSCK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_PCSSCK), uint32_t) & BM_SPI_CTARn_PCSSCK)
mbed_official	146:f64d43ff0c18	974
mbed_official	146:f64d43ff0c18	975	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	976	//! @brief Set the PCSSCK field to a new value.
mbed_official	146:f64d43ff0c18	977	#define BW_SPI_CTARn_PCSSCK(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PCSSCK) \| BF_SPI_CTARn_PCSSCK(v)))
mbed_official	146:f64d43ff0c18	978	#endif
mbed_official	146:f64d43ff0c18	979	//@}
mbed_official	146:f64d43ff0c18	980
mbed_official	146:f64d43ff0c18	981	/*!
mbed_official	146:f64d43ff0c18	982	* @name Register SPI_CTARn, field LSBFE[24] (RW)
mbed_official	146:f64d43ff0c18	983	*
mbed_official	146:f64d43ff0c18	984	* Specifies whether the LSB or MSB of the frame is transferred first.
mbed_official	146:f64d43ff0c18	985	*
mbed_official	146:f64d43ff0c18	986	* Values:
mbed_official	146:f64d43ff0c18	987	* - 0 - Data is transferred MSB first.
mbed_official	146:f64d43ff0c18	988	* - 1 - Data is transferred LSB first.
mbed_official	146:f64d43ff0c18	989	*/
mbed_official	146:f64d43ff0c18	990	//@{
mbed_official	146:f64d43ff0c18	991	#define BP_SPI_CTARn_LSBFE (24U) //!< Bit position for SPI_CTARn_LSBFE.
mbed_official	146:f64d43ff0c18	992	#define BM_SPI_CTARn_LSBFE (0x01000000U) //!< Bit mask for SPI_CTARn_LSBFE.
mbed_official	146:f64d43ff0c18	993	#define BS_SPI_CTARn_LSBFE (1U) //!< Bit field size in bits for SPI_CTARn_LSBFE.
mbed_official	146:f64d43ff0c18	994
mbed_official	146:f64d43ff0c18	995	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	996	//! @brief Read current value of the SPI_CTARn_LSBFE field.
mbed_official	146:f64d43ff0c18	997	#define BR_SPI_CTARn_LSBFE(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_LSBFE))
mbed_official	146:f64d43ff0c18	998	#endif
mbed_official	146:f64d43ff0c18	999
mbed_official	146:f64d43ff0c18	1000	//! @brief Format value for bitfield SPI_CTARn_LSBFE.
mbed_official	146:f64d43ff0c18	1001	#define BF_SPI_CTARn_LSBFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_LSBFE), uint32_t) & BM_SPI_CTARn_LSBFE)
mbed_official	146:f64d43ff0c18	1002
mbed_official	146:f64d43ff0c18	1003	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1004	//! @brief Set the LSBFE field to a new value.
mbed_official	146:f64d43ff0c18	1005	#define BW_SPI_CTARn_LSBFE(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_LSBFE) = (v))
mbed_official	146:f64d43ff0c18	1006	#endif
mbed_official	146:f64d43ff0c18	1007	//@}
mbed_official	146:f64d43ff0c18	1008
mbed_official	146:f64d43ff0c18	1009	/*!
mbed_official	146:f64d43ff0c18	1010	* @name Register SPI_CTARn, field CPHA[25] (RW)
mbed_official	146:f64d43ff0c18	1011	*
mbed_official	146:f64d43ff0c18	1012	* Selects which edge of SCK causes data to change and which edge causes data to
mbed_official	146:f64d43ff0c18	1013	* be captured. This bit is used in both master and slave mode. For successful
mbed_official	146:f64d43ff0c18	1014	* communication between serial devices, the devices must have identical clock
mbed_official	146:f64d43ff0c18	1015	* phase settings. In Continuous SCK mode, the bit value is ignored and the
mbed_official	146:f64d43ff0c18	1016	* transfers are done as if the CPHA bit is set to 1.
mbed_official	146:f64d43ff0c18	1017	*
mbed_official	146:f64d43ff0c18	1018	* Values:
mbed_official	146:f64d43ff0c18	1019	* - 0 - Data is captured on the leading edge of SCK and changed on the
mbed_official	146:f64d43ff0c18	1020	* following edge.
mbed_official	146:f64d43ff0c18	1021	* - 1 - Data is changed on the leading edge of SCK and captured on the
mbed_official	146:f64d43ff0c18	1022	* following edge.
mbed_official	146:f64d43ff0c18	1023	*/
mbed_official	146:f64d43ff0c18	1024	//@{
mbed_official	146:f64d43ff0c18	1025	#define BP_SPI_CTARn_CPHA (25U) //!< Bit position for SPI_CTARn_CPHA.
mbed_official	146:f64d43ff0c18	1026	#define BM_SPI_CTARn_CPHA (0x02000000U) //!< Bit mask for SPI_CTARn_CPHA.
mbed_official	146:f64d43ff0c18	1027	#define BS_SPI_CTARn_CPHA (1U) //!< Bit field size in bits for SPI_CTARn_CPHA.
mbed_official	146:f64d43ff0c18	1028
mbed_official	146:f64d43ff0c18	1029	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1030	//! @brief Read current value of the SPI_CTARn_CPHA field.
mbed_official	146:f64d43ff0c18	1031	#define BR_SPI_CTARn_CPHA(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPHA))
mbed_official	146:f64d43ff0c18	1032	#endif
mbed_official	146:f64d43ff0c18	1033
mbed_official	146:f64d43ff0c18	1034	//! @brief Format value for bitfield SPI_CTARn_CPHA.
mbed_official	146:f64d43ff0c18	1035	#define BF_SPI_CTARn_CPHA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_CPHA), uint32_t) & BM_SPI_CTARn_CPHA)
mbed_official	146:f64d43ff0c18	1036
mbed_official	146:f64d43ff0c18	1037	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1038	//! @brief Set the CPHA field to a new value.
mbed_official	146:f64d43ff0c18	1039	#define BW_SPI_CTARn_CPHA(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPHA) = (v))
mbed_official	146:f64d43ff0c18	1040	#endif
mbed_official	146:f64d43ff0c18	1041	//@}
mbed_official	146:f64d43ff0c18	1042
mbed_official	146:f64d43ff0c18	1043	/*!
mbed_official	146:f64d43ff0c18	1044	* @name Register SPI_CTARn, field CPOL[26] (RW)
mbed_official	146:f64d43ff0c18	1045	*
mbed_official	146:f64d43ff0c18	1046	* Selects the inactive state of the Serial Communications Clock (SCK). This bit
mbed_official	146:f64d43ff0c18	1047	* is used in both master and slave mode. For successful communication between
mbed_official	146:f64d43ff0c18	1048	* serial devices, the devices must have identical clock polarities. When the
mbed_official	146:f64d43ff0c18	1049	* Continuous Selection Format is selected, switching between clock polarities
mbed_official	146:f64d43ff0c18	1050	* without stopping the module can cause errors in the transfer due to the peripheral
mbed_official	146:f64d43ff0c18	1051	* device interpreting the switch of clock polarity as a valid clock edge. In case
mbed_official	146:f64d43ff0c18	1052	* of continous sck mode, when the module goes in low power mode(disabled),
mbed_official	146:f64d43ff0c18	1053	* inactive state of sck is not guaranted.
mbed_official	146:f64d43ff0c18	1054	*
mbed_official	146:f64d43ff0c18	1055	* Values:
mbed_official	146:f64d43ff0c18	1056	* - 0 - The inactive state value of SCK is low.
mbed_official	146:f64d43ff0c18	1057	* - 1 - The inactive state value of SCK is high.
mbed_official	146:f64d43ff0c18	1058	*/
mbed_official	146:f64d43ff0c18	1059	//@{
mbed_official	146:f64d43ff0c18	1060	#define BP_SPI_CTARn_CPOL (26U) //!< Bit position for SPI_CTARn_CPOL.
mbed_official	146:f64d43ff0c18	1061	#define BM_SPI_CTARn_CPOL (0x04000000U) //!< Bit mask for SPI_CTARn_CPOL.
mbed_official	146:f64d43ff0c18	1062	#define BS_SPI_CTARn_CPOL (1U) //!< Bit field size in bits for SPI_CTARn_CPOL.
mbed_official	146:f64d43ff0c18	1063
mbed_official	146:f64d43ff0c18	1064	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1065	//! @brief Read current value of the SPI_CTARn_CPOL field.
mbed_official	146:f64d43ff0c18	1066	#define BR_SPI_CTARn_CPOL(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPOL))
mbed_official	146:f64d43ff0c18	1067	#endif
mbed_official	146:f64d43ff0c18	1068
mbed_official	146:f64d43ff0c18	1069	//! @brief Format value for bitfield SPI_CTARn_CPOL.
mbed_official	146:f64d43ff0c18	1070	#define BF_SPI_CTARn_CPOL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_CPOL), uint32_t) & BM_SPI_CTARn_CPOL)
mbed_official	146:f64d43ff0c18	1071
mbed_official	146:f64d43ff0c18	1072	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1073	//! @brief Set the CPOL field to a new value.
mbed_official	146:f64d43ff0c18	1074	#define BW_SPI_CTARn_CPOL(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPOL) = (v))
mbed_official	146:f64d43ff0c18	1075	#endif
mbed_official	146:f64d43ff0c18	1076	//@}
mbed_official	146:f64d43ff0c18	1077
mbed_official	146:f64d43ff0c18	1078	/*!
mbed_official	146:f64d43ff0c18	1079	* @name Register SPI_CTARn, field FMSZ[30:27] (RW)
mbed_official	146:f64d43ff0c18	1080	*
mbed_official	146:f64d43ff0c18	1081	* The number of bits transferred per frame is equal to the FMSZ value plus 1.
mbed_official	146:f64d43ff0c18	1082	* Regardless of the transmission mode, the minimum valid frame size value is 4.
mbed_official	146:f64d43ff0c18	1083	*/
mbed_official	146:f64d43ff0c18	1084	//@{
mbed_official	146:f64d43ff0c18	1085	#define BP_SPI_CTARn_FMSZ (27U) //!< Bit position for SPI_CTARn_FMSZ.
mbed_official	146:f64d43ff0c18	1086	#define BM_SPI_CTARn_FMSZ (0x78000000U) //!< Bit mask for SPI_CTARn_FMSZ.
mbed_official	146:f64d43ff0c18	1087	#define BS_SPI_CTARn_FMSZ (4U) //!< Bit field size in bits for SPI_CTARn_FMSZ.
mbed_official	146:f64d43ff0c18	1088
mbed_official	146:f64d43ff0c18	1089	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1090	//! @brief Read current value of the SPI_CTARn_FMSZ field.
mbed_official	146:f64d43ff0c18	1091	#define BR_SPI_CTARn_FMSZ(x, n) (HW_SPI_CTARn(x, n).B.FMSZ)
mbed_official	146:f64d43ff0c18	1092	#endif
mbed_official	146:f64d43ff0c18	1093
mbed_official	146:f64d43ff0c18	1094	//! @brief Format value for bitfield SPI_CTARn_FMSZ.
mbed_official	146:f64d43ff0c18	1095	#define BF_SPI_CTARn_FMSZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_FMSZ), uint32_t) & BM_SPI_CTARn_FMSZ)
mbed_official	146:f64d43ff0c18	1096
mbed_official	146:f64d43ff0c18	1097	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1098	//! @brief Set the FMSZ field to a new value.
mbed_official	146:f64d43ff0c18	1099	#define BW_SPI_CTARn_FMSZ(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_FMSZ) \| BF_SPI_CTARn_FMSZ(v)))
mbed_official	146:f64d43ff0c18	1100	#endif
mbed_official	146:f64d43ff0c18	1101	//@}
mbed_official	146:f64d43ff0c18	1102
mbed_official	146:f64d43ff0c18	1103	/*!
mbed_official	146:f64d43ff0c18	1104	* @name Register SPI_CTARn, field DBR[31] (RW)
mbed_official	146:f64d43ff0c18	1105	*
mbed_official	146:f64d43ff0c18	1106	* Doubles the effective baud rate of the Serial Communications Clock (SCK).
mbed_official	146:f64d43ff0c18	1107	* This field is used only in master mode. It effectively halves the Baud Rate
mbed_official	146:f64d43ff0c18	1108	* division ratio, supporting faster frequencies, and odd division ratios for the
mbed_official	146:f64d43ff0c18	1109	* Serial Communications Clock (SCK). When the DBR bit is set, the duty cycle of the
mbed_official	146:f64d43ff0c18	1110	* Serial Communications Clock (SCK) depends on the value in the Baud Rate
mbed_official	146:f64d43ff0c18	1111	* Prescaler and the Clock Phase bit as listed in the following table. See the BR field
mbed_official	146:f64d43ff0c18	1112	* description for details on how to compute the baud rate. SPI SCK Duty Cycle
mbed_official	146:f64d43ff0c18	1113	* DBR CPHA PBR SCK Duty Cycle 0 any any 50/50 1 0 00 50/50 1 0 01 33/66 1 0 10
mbed_official	146:f64d43ff0c18	1114	* 40/60 1 0 11 43/57 1 1 00 50/50 1 1 01 66/33 1 1 10 60/40 1 1 11 57/43
mbed_official	146:f64d43ff0c18	1115	*
mbed_official	146:f64d43ff0c18	1116	* Values:
mbed_official	146:f64d43ff0c18	1117	* - 0 - The baud rate is computed normally with a 50/50 duty cycle.
mbed_official	146:f64d43ff0c18	1118	* - 1 - The baud rate is doubled with the duty cycle depending on the Baud Rate
mbed_official	146:f64d43ff0c18	1119	* Prescaler.
mbed_official	146:f64d43ff0c18	1120	*/
mbed_official	146:f64d43ff0c18	1121	//@{
mbed_official	146:f64d43ff0c18	1122	#define BP_SPI_CTARn_DBR (31U) //!< Bit position for SPI_CTARn_DBR.
mbed_official	146:f64d43ff0c18	1123	#define BM_SPI_CTARn_DBR (0x80000000U) //!< Bit mask for SPI_CTARn_DBR.
mbed_official	146:f64d43ff0c18	1124	#define BS_SPI_CTARn_DBR (1U) //!< Bit field size in bits for SPI_CTARn_DBR.
mbed_official	146:f64d43ff0c18	1125
mbed_official	146:f64d43ff0c18	1126	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1127	//! @brief Read current value of the SPI_CTARn_DBR field.
mbed_official	146:f64d43ff0c18	1128	#define BR_SPI_CTARn_DBR(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_DBR))
mbed_official	146:f64d43ff0c18	1129	#endif
mbed_official	146:f64d43ff0c18	1130
mbed_official	146:f64d43ff0c18	1131	//! @brief Format value for bitfield SPI_CTARn_DBR.
mbed_official	146:f64d43ff0c18	1132	#define BF_SPI_CTARn_DBR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_DBR), uint32_t) & BM_SPI_CTARn_DBR)
mbed_official	146:f64d43ff0c18	1133
mbed_official	146:f64d43ff0c18	1134	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1135	//! @brief Set the DBR field to a new value.
mbed_official	146:f64d43ff0c18	1136	#define BW_SPI_CTARn_DBR(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_DBR) = (v))
mbed_official	146:f64d43ff0c18	1137	#endif
mbed_official	146:f64d43ff0c18	1138	//@}
mbed_official	146:f64d43ff0c18	1139	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1140	// HW_SPI_CTARn_SLAVE - Clock and Transfer Attributes Register (In Slave Mode)
mbed_official	146:f64d43ff0c18	1141	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1142
mbed_official	146:f64d43ff0c18	1143	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1144	/*!
mbed_official	146:f64d43ff0c18	1145	* @brief HW_SPI_CTARn_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) (RW)
mbed_official	146:f64d43ff0c18	1146	*
mbed_official	146:f64d43ff0c18	1147	* Reset value: 0x78000000U
mbed_official	146:f64d43ff0c18	1148	*
mbed_official	146:f64d43ff0c18	1149	* When the module is configured as an SPI bus slave, the CTAR0 register is used.
mbed_official	146:f64d43ff0c18	1150	*/
mbed_official	146:f64d43ff0c18	1151	typedef union _hw_spi_ctarn_slave
mbed_official	146:f64d43ff0c18	1152	{
mbed_official	146:f64d43ff0c18	1153	uint32_t U;
mbed_official	146:f64d43ff0c18	1154	struct _hw_spi_ctarn_slave_bitfields
mbed_official	146:f64d43ff0c18	1155	{
mbed_official	146:f64d43ff0c18	1156	uint32_t RESERVED0 : 25; //!< [24:0]
mbed_official	146:f64d43ff0c18	1157	uint32_t CPHA : 1; //!< [25] Clock Phase
mbed_official	146:f64d43ff0c18	1158	uint32_t CPOL : 1; //!< [26] Clock Polarity
mbed_official	146:f64d43ff0c18	1159	uint32_t FMSZ : 5; //!< [31:27] Frame Size
mbed_official	146:f64d43ff0c18	1160	} B;
mbed_official	146:f64d43ff0c18	1161	} hw_spi_ctarn_slave_t;
mbed_official	146:f64d43ff0c18	1162	#endif
mbed_official	146:f64d43ff0c18	1163
mbed_official	146:f64d43ff0c18	1164	/*!
mbed_official	146:f64d43ff0c18	1165	* @name Constants and macros for entire SPI_CTARn_SLAVE register
mbed_official	146:f64d43ff0c18	1166	*/
mbed_official	146:f64d43ff0c18	1167	//@{
mbed_official	146:f64d43ff0c18	1168	#define HW_SPI_CTARn_SLAVE_COUNT (1U)
mbed_official	146:f64d43ff0c18	1169
mbed_official	146:f64d43ff0c18	1170	#define HW_SPI_CTARn_SLAVE_ADDR(x, n) (REGS_SPI_BASE(x) + 0xCU + (0x4U * n))
mbed_official	146:f64d43ff0c18	1171
mbed_official	146:f64d43ff0c18	1172	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1173	#define HW_SPI_CTARn_SLAVE(x, n) ((__IO hw_spi_ctarn_slave_t ) HW_SPI_CTARn_SLAVE_ADDR(x, n))
mbed_official	146:f64d43ff0c18	1174	#define HW_SPI_CTARn_SLAVE_RD(x, n) (HW_SPI_CTARn_SLAVE(x, n).U)
mbed_official	146:f64d43ff0c18	1175	#define HW_SPI_CTARn_SLAVE_WR(x, n, v) (HW_SPI_CTARn_SLAVE(x, n).U = (v))
mbed_official	146:f64d43ff0c18	1176	#define HW_SPI_CTARn_SLAVE_SET(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, HW_SPI_CTARn_SLAVE_RD(x, n) \| (v)))
mbed_official	146:f64d43ff0c18	1177	#define HW_SPI_CTARn_SLAVE_CLR(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, HW_SPI_CTARn_SLAVE_RD(x, n) & ~(v)))
mbed_official	146:f64d43ff0c18	1178	#define HW_SPI_CTARn_SLAVE_TOG(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, HW_SPI_CTARn_SLAVE_RD(x, n) ^ (v)))
mbed_official	146:f64d43ff0c18	1179	#endif
mbed_official	146:f64d43ff0c18	1180	//@}
mbed_official	146:f64d43ff0c18	1181
mbed_official	146:f64d43ff0c18	1182	/*
mbed_official	146:f64d43ff0c18	1183	* Constants & macros for individual SPI_CTARn_SLAVE bitfields
mbed_official	146:f64d43ff0c18	1184	*/
mbed_official	146:f64d43ff0c18	1185
mbed_official	146:f64d43ff0c18	1186	/*!
mbed_official	146:f64d43ff0c18	1187	* @name Register SPI_CTARn_SLAVE, field CPHA[25] (RW)
mbed_official	146:f64d43ff0c18	1188	*
mbed_official	146:f64d43ff0c18	1189	* Selects which edge of SCK causes data to change and which edge causes data to
mbed_official	146:f64d43ff0c18	1190	* be captured. This bit is used in both master and slave mode. For successful
mbed_official	146:f64d43ff0c18	1191	* communication between serial devices, the devices must have identical clock
mbed_official	146:f64d43ff0c18	1192	* phase settings. In Continuous SCK mode, the bit value is ignored and the
mbed_official	146:f64d43ff0c18	1193	* transfers are done as if the CPHA bit is set to 1.
mbed_official	146:f64d43ff0c18	1194	*
mbed_official	146:f64d43ff0c18	1195	* Values:
mbed_official	146:f64d43ff0c18	1196	* - 0 - Data is captured on the leading edge of SCK and changed on the
mbed_official	146:f64d43ff0c18	1197	* following edge.
mbed_official	146:f64d43ff0c18	1198	* - 1 - Data is changed on the leading edge of SCK and captured on the
mbed_official	146:f64d43ff0c18	1199	* following edge.
mbed_official	146:f64d43ff0c18	1200	*/
mbed_official	146:f64d43ff0c18	1201	//@{
mbed_official	146:f64d43ff0c18	1202	#define BP_SPI_CTARn_SLAVE_CPHA (25U) //!< Bit position for SPI_CTARn_SLAVE_CPHA.
mbed_official	146:f64d43ff0c18	1203	#define BM_SPI_CTARn_SLAVE_CPHA (0x02000000U) //!< Bit mask for SPI_CTARn_SLAVE_CPHA.
mbed_official	146:f64d43ff0c18	1204	#define BS_SPI_CTARn_SLAVE_CPHA (1U) //!< Bit field size in bits for SPI_CTARn_SLAVE_CPHA.
mbed_official	146:f64d43ff0c18	1205
mbed_official	146:f64d43ff0c18	1206	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1207	//! @brief Read current value of the SPI_CTARn_SLAVE_CPHA field.
mbed_official	146:f64d43ff0c18	1208	#define BR_SPI_CTARn_SLAVE_CPHA(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPHA))
mbed_official	146:f64d43ff0c18	1209	#endif
mbed_official	146:f64d43ff0c18	1210
mbed_official	146:f64d43ff0c18	1211	//! @brief Format value for bitfield SPI_CTARn_SLAVE_CPHA.
mbed_official	146:f64d43ff0c18	1212	#define BF_SPI_CTARn_SLAVE_CPHA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_SLAVE_CPHA), uint32_t) & BM_SPI_CTARn_SLAVE_CPHA)
mbed_official	146:f64d43ff0c18	1213
mbed_official	146:f64d43ff0c18	1214	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1215	//! @brief Set the CPHA field to a new value.
mbed_official	146:f64d43ff0c18	1216	#define BW_SPI_CTARn_SLAVE_CPHA(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPHA) = (v))
mbed_official	146:f64d43ff0c18	1217	#endif
mbed_official	146:f64d43ff0c18	1218	//@}
mbed_official	146:f64d43ff0c18	1219
mbed_official	146:f64d43ff0c18	1220	/*!
mbed_official	146:f64d43ff0c18	1221	* @name Register SPI_CTARn_SLAVE, field CPOL[26] (RW)
mbed_official	146:f64d43ff0c18	1222	*
mbed_official	146:f64d43ff0c18	1223	* Selects the inactive state of the Serial Communications Clock (SCK). In case
mbed_official	146:f64d43ff0c18	1224	* of continous sck mode, when the module goes in low power mode(disabled),
mbed_official	146:f64d43ff0c18	1225	* inactive state of sck is not guaranted.
mbed_official	146:f64d43ff0c18	1226	*
mbed_official	146:f64d43ff0c18	1227	* Values:
mbed_official	146:f64d43ff0c18	1228	* - 0 - The inactive state value of SCK is low.
mbed_official	146:f64d43ff0c18	1229	* - 1 - The inactive state value of SCK is high.
mbed_official	146:f64d43ff0c18	1230	*/
mbed_official	146:f64d43ff0c18	1231	//@{
mbed_official	146:f64d43ff0c18	1232	#define BP_SPI_CTARn_SLAVE_CPOL (26U) //!< Bit position for SPI_CTARn_SLAVE_CPOL.
mbed_official	146:f64d43ff0c18	1233	#define BM_SPI_CTARn_SLAVE_CPOL (0x04000000U) //!< Bit mask for SPI_CTARn_SLAVE_CPOL.
mbed_official	146:f64d43ff0c18	1234	#define BS_SPI_CTARn_SLAVE_CPOL (1U) //!< Bit field size in bits for SPI_CTARn_SLAVE_CPOL.
mbed_official	146:f64d43ff0c18	1235
mbed_official	146:f64d43ff0c18	1236	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1237	//! @brief Read current value of the SPI_CTARn_SLAVE_CPOL field.
mbed_official	146:f64d43ff0c18	1238	#define BR_SPI_CTARn_SLAVE_CPOL(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPOL))
mbed_official	146:f64d43ff0c18	1239	#endif
mbed_official	146:f64d43ff0c18	1240
mbed_official	146:f64d43ff0c18	1241	//! @brief Format value for bitfield SPI_CTARn_SLAVE_CPOL.
mbed_official	146:f64d43ff0c18	1242	#define BF_SPI_CTARn_SLAVE_CPOL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_SLAVE_CPOL), uint32_t) & BM_SPI_CTARn_SLAVE_CPOL)
mbed_official	146:f64d43ff0c18	1243
mbed_official	146:f64d43ff0c18	1244	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1245	//! @brief Set the CPOL field to a new value.
mbed_official	146:f64d43ff0c18	1246	#define BW_SPI_CTARn_SLAVE_CPOL(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPOL) = (v))
mbed_official	146:f64d43ff0c18	1247	#endif
mbed_official	146:f64d43ff0c18	1248	//@}
mbed_official	146:f64d43ff0c18	1249
mbed_official	146:f64d43ff0c18	1250	/*!
mbed_official	146:f64d43ff0c18	1251	* @name Register SPI_CTARn_SLAVE, field FMSZ[31:27] (RW)
mbed_official	146:f64d43ff0c18	1252	*
mbed_official	146:f64d43ff0c18	1253	* The number of bits transfered per frame is equal to the FMSZ field value plus
mbed_official	146:f64d43ff0c18	1254	* 1. Note that the minimum valid value of frame size is 4.
mbed_official	146:f64d43ff0c18	1255	*/
mbed_official	146:f64d43ff0c18	1256	//@{
mbed_official	146:f64d43ff0c18	1257	#define BP_SPI_CTARn_SLAVE_FMSZ (27U) //!< Bit position for SPI_CTARn_SLAVE_FMSZ.
mbed_official	146:f64d43ff0c18	1258	#define BM_SPI_CTARn_SLAVE_FMSZ (0xF8000000U) //!< Bit mask for SPI_CTARn_SLAVE_FMSZ.
mbed_official	146:f64d43ff0c18	1259	#define BS_SPI_CTARn_SLAVE_FMSZ (5U) //!< Bit field size in bits for SPI_CTARn_SLAVE_FMSZ.
mbed_official	146:f64d43ff0c18	1260
mbed_official	146:f64d43ff0c18	1261	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1262	//! @brief Read current value of the SPI_CTARn_SLAVE_FMSZ field.
mbed_official	146:f64d43ff0c18	1263	#define BR_SPI_CTARn_SLAVE_FMSZ(x, n) (HW_SPI_CTARn_SLAVE(x, n).B.FMSZ)
mbed_official	146:f64d43ff0c18	1264	#endif
mbed_official	146:f64d43ff0c18	1265
mbed_official	146:f64d43ff0c18	1266	//! @brief Format value for bitfield SPI_CTARn_SLAVE_FMSZ.
mbed_official	146:f64d43ff0c18	1267	#define BF_SPI_CTARn_SLAVE_FMSZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_SLAVE_FMSZ), uint32_t) & BM_SPI_CTARn_SLAVE_FMSZ)
mbed_official	146:f64d43ff0c18	1268
mbed_official	146:f64d43ff0c18	1269	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1270	//! @brief Set the FMSZ field to a new value.
mbed_official	146:f64d43ff0c18	1271	#define BW_SPI_CTARn_SLAVE_FMSZ(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, (HW_SPI_CTARn_SLAVE_RD(x, n) & ~BM_SPI_CTARn_SLAVE_FMSZ) \| BF_SPI_CTARn_SLAVE_FMSZ(v)))
mbed_official	146:f64d43ff0c18	1272	#endif
mbed_official	146:f64d43ff0c18	1273	//@}
mbed_official	146:f64d43ff0c18	1274
mbed_official	146:f64d43ff0c18	1275	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1276	// HW_SPI_SR - Status Register
mbed_official	146:f64d43ff0c18	1277	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1278
mbed_official	146:f64d43ff0c18	1279	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1280	/*!
mbed_official	146:f64d43ff0c18	1281	* @brief HW_SPI_SR - Status Register (RW)
mbed_official	146:f64d43ff0c18	1282	*
mbed_official	146:f64d43ff0c18	1283	* Reset value: 0x02000000U
mbed_official	146:f64d43ff0c18	1284	*
mbed_official	146:f64d43ff0c18	1285	* SR contains status and flag bits. The bits reflect the status of the module
mbed_official	146:f64d43ff0c18	1286	* and indicate the occurrence of events that can generate interrupt or DMA
mbed_official	146:f64d43ff0c18	1287	* requests. Software can clear flag bits in the SR by writing a 1 to them. Writing a 0
mbed_official	146:f64d43ff0c18	1288	* to a flag bit has no effect. This register may not be writable in Module
mbed_official	146:f64d43ff0c18	1289	* Disable mode due to the use of power saving mechanisms.
mbed_official	146:f64d43ff0c18	1290	*/
mbed_official	146:f64d43ff0c18	1291	typedef union _hw_spi_sr
mbed_official	146:f64d43ff0c18	1292	{
mbed_official	146:f64d43ff0c18	1293	uint32_t U;
mbed_official	146:f64d43ff0c18	1294	struct _hw_spi_sr_bitfields
mbed_official	146:f64d43ff0c18	1295	{
mbed_official	146:f64d43ff0c18	1296	uint32_t POPNXTPTR : 4; //!< [3:0] Pop Next Pointer
mbed_official	146:f64d43ff0c18	1297	uint32_t RXCTR : 4; //!< [7:4] RX FIFO Counter
mbed_official	146:f64d43ff0c18	1298	uint32_t TXNXTPTR : 4; //!< [11:8] Transmit Next Pointer
mbed_official	146:f64d43ff0c18	1299	uint32_t TXCTR : 4; //!< [15:12] TX FIFO Counter
mbed_official	146:f64d43ff0c18	1300	uint32_t RESERVED0 : 1; //!< [16]
mbed_official	146:f64d43ff0c18	1301	uint32_t RFDF : 1; //!< [17] Receive FIFO Drain Flag
mbed_official	146:f64d43ff0c18	1302	uint32_t RESERVED1 : 1; //!< [18]
mbed_official	146:f64d43ff0c18	1303	uint32_t RFOF : 1; //!< [19] Receive FIFO Overflow Flag
mbed_official	146:f64d43ff0c18	1304	uint32_t RESERVED2 : 5; //!< [24:20]
mbed_official	146:f64d43ff0c18	1305	uint32_t TFFF : 1; //!< [25] Transmit FIFO Fill Flag
mbed_official	146:f64d43ff0c18	1306	uint32_t RESERVED3 : 1; //!< [26]
mbed_official	146:f64d43ff0c18	1307	uint32_t TFUF : 1; //!< [27] Transmit FIFO Underflow Flag
mbed_official	146:f64d43ff0c18	1308	uint32_t EOQF : 1; //!< [28] End of Queue Flag
mbed_official	146:f64d43ff0c18	1309	uint32_t RESERVED4 : 1; //!< [29]
mbed_official	146:f64d43ff0c18	1310	uint32_t TXRXS : 1; //!< [30] TX and RX Status
mbed_official	146:f64d43ff0c18	1311	uint32_t TCF : 1; //!< [31] Transfer Complete Flag
mbed_official	146:f64d43ff0c18	1312	} B;
mbed_official	146:f64d43ff0c18	1313	} hw_spi_sr_t;
mbed_official	146:f64d43ff0c18	1314	#endif
mbed_official	146:f64d43ff0c18	1315
mbed_official	146:f64d43ff0c18	1316	/*!
mbed_official	146:f64d43ff0c18	1317	* @name Constants and macros for entire SPI_SR register
mbed_official	146:f64d43ff0c18	1318	*/
mbed_official	146:f64d43ff0c18	1319	//@{
mbed_official	146:f64d43ff0c18	1320	#define HW_SPI_SR_ADDR(x) (REGS_SPI_BASE(x) + 0x2CU)
mbed_official	146:f64d43ff0c18	1321
mbed_official	146:f64d43ff0c18	1322	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1323	#define HW_SPI_SR(x) ((__IO hw_spi_sr_t ) HW_SPI_SR_ADDR(x))
mbed_official	146:f64d43ff0c18	1324	#define HW_SPI_SR_RD(x) (HW_SPI_SR(x).U)
mbed_official	146:f64d43ff0c18	1325	#define HW_SPI_SR_WR(x, v) (HW_SPI_SR(x).U = (v))
mbed_official	146:f64d43ff0c18	1326	#define HW_SPI_SR_SET(x, v) (HW_SPI_SR_WR(x, HW_SPI_SR_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	1327	#define HW_SPI_SR_CLR(x, v) (HW_SPI_SR_WR(x, HW_SPI_SR_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	1328	#define HW_SPI_SR_TOG(x, v) (HW_SPI_SR_WR(x, HW_SPI_SR_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	1329	#endif
mbed_official	146:f64d43ff0c18	1330	//@}
mbed_official	146:f64d43ff0c18	1331
mbed_official	146:f64d43ff0c18	1332	/*
mbed_official	146:f64d43ff0c18	1333	* Constants & macros for individual SPI_SR bitfields
mbed_official	146:f64d43ff0c18	1334	*/
mbed_official	146:f64d43ff0c18	1335
mbed_official	146:f64d43ff0c18	1336	/*!
mbed_official	146:f64d43ff0c18	1337	* @name Register SPI_SR, field POPNXTPTR[3:0] (RO)
mbed_official	146:f64d43ff0c18	1338	*
mbed_official	146:f64d43ff0c18	1339	* Contains a pointer to the RX FIFO entry to be returned when the POPR is read.
mbed_official	146:f64d43ff0c18	1340	* The POPNXTPTR is updated when the POPR is read.
mbed_official	146:f64d43ff0c18	1341	*/
mbed_official	146:f64d43ff0c18	1342	//@{
mbed_official	146:f64d43ff0c18	1343	#define BP_SPI_SR_POPNXTPTR (0U) //!< Bit position for SPI_SR_POPNXTPTR.
mbed_official	146:f64d43ff0c18	1344	#define BM_SPI_SR_POPNXTPTR (0x0000000FU) //!< Bit mask for SPI_SR_POPNXTPTR.
mbed_official	146:f64d43ff0c18	1345	#define BS_SPI_SR_POPNXTPTR (4U) //!< Bit field size in bits for SPI_SR_POPNXTPTR.
mbed_official	146:f64d43ff0c18	1346
mbed_official	146:f64d43ff0c18	1347	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1348	//! @brief Read current value of the SPI_SR_POPNXTPTR field.
mbed_official	146:f64d43ff0c18	1349	#define BR_SPI_SR_POPNXTPTR(x) (HW_SPI_SR(x).B.POPNXTPTR)
mbed_official	146:f64d43ff0c18	1350	#endif
mbed_official	146:f64d43ff0c18	1351	//@}
mbed_official	146:f64d43ff0c18	1352
mbed_official	146:f64d43ff0c18	1353	/*!
mbed_official	146:f64d43ff0c18	1354	* @name Register SPI_SR, field RXCTR[7:4] (RO)
mbed_official	146:f64d43ff0c18	1355	*
mbed_official	146:f64d43ff0c18	1356	* Indicates the number of entries in the RX FIFO. The RXCTR is decremented
mbed_official	146:f64d43ff0c18	1357	* every time the POPR is read. The RXCTR is incremented every time data is
mbed_official	146:f64d43ff0c18	1358	* transferred from the shift register to the RX FIFO.
mbed_official	146:f64d43ff0c18	1359	*/
mbed_official	146:f64d43ff0c18	1360	//@{
mbed_official	146:f64d43ff0c18	1361	#define BP_SPI_SR_RXCTR (4U) //!< Bit position for SPI_SR_RXCTR.
mbed_official	146:f64d43ff0c18	1362	#define BM_SPI_SR_RXCTR (0x000000F0U) //!< Bit mask for SPI_SR_RXCTR.
mbed_official	146:f64d43ff0c18	1363	#define BS_SPI_SR_RXCTR (4U) //!< Bit field size in bits for SPI_SR_RXCTR.
mbed_official	146:f64d43ff0c18	1364
mbed_official	146:f64d43ff0c18	1365	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1366	//! @brief Read current value of the SPI_SR_RXCTR field.
mbed_official	146:f64d43ff0c18	1367	#define BR_SPI_SR_RXCTR(x) (HW_SPI_SR(x).B.RXCTR)
mbed_official	146:f64d43ff0c18	1368	#endif
mbed_official	146:f64d43ff0c18	1369	//@}
mbed_official	146:f64d43ff0c18	1370
mbed_official	146:f64d43ff0c18	1371	/*!
mbed_official	146:f64d43ff0c18	1372	* @name Register SPI_SR, field TXNXTPTR[11:8] (RO)
mbed_official	146:f64d43ff0c18	1373	*
mbed_official	146:f64d43ff0c18	1374	* Indicates which TX FIFO entry is transmitted during the next transfer. The
mbed_official	146:f64d43ff0c18	1375	* TXNXTPTR field is updated every time SPI data is transferred from the TX FIFO to
mbed_official	146:f64d43ff0c18	1376	* the shift register.
mbed_official	146:f64d43ff0c18	1377	*/
mbed_official	146:f64d43ff0c18	1378	//@{
mbed_official	146:f64d43ff0c18	1379	#define BP_SPI_SR_TXNXTPTR (8U) //!< Bit position for SPI_SR_TXNXTPTR.
mbed_official	146:f64d43ff0c18	1380	#define BM_SPI_SR_TXNXTPTR (0x00000F00U) //!< Bit mask for SPI_SR_TXNXTPTR.
mbed_official	146:f64d43ff0c18	1381	#define BS_SPI_SR_TXNXTPTR (4U) //!< Bit field size in bits for SPI_SR_TXNXTPTR.
mbed_official	146:f64d43ff0c18	1382
mbed_official	146:f64d43ff0c18	1383	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1384	//! @brief Read current value of the SPI_SR_TXNXTPTR field.
mbed_official	146:f64d43ff0c18	1385	#define BR_SPI_SR_TXNXTPTR(x) (HW_SPI_SR(x).B.TXNXTPTR)
mbed_official	146:f64d43ff0c18	1386	#endif
mbed_official	146:f64d43ff0c18	1387	//@}
mbed_official	146:f64d43ff0c18	1388
mbed_official	146:f64d43ff0c18	1389	/*!
mbed_official	146:f64d43ff0c18	1390	* @name Register SPI_SR, field TXCTR[15:12] (RO)
mbed_official	146:f64d43ff0c18	1391	*
mbed_official	146:f64d43ff0c18	1392	* Indicates the number of valid entries in the TX FIFO. The TXCTR is
mbed_official	146:f64d43ff0c18	1393	* incremented every time the PUSHR is written. The TXCTR is decremented every time an SPI
mbed_official	146:f64d43ff0c18	1394	* command is executed and the SPI data is transferred to the shift register.
mbed_official	146:f64d43ff0c18	1395	*/
mbed_official	146:f64d43ff0c18	1396	//@{
mbed_official	146:f64d43ff0c18	1397	#define BP_SPI_SR_TXCTR (12U) //!< Bit position for SPI_SR_TXCTR.
mbed_official	146:f64d43ff0c18	1398	#define BM_SPI_SR_TXCTR (0x0000F000U) //!< Bit mask for SPI_SR_TXCTR.
mbed_official	146:f64d43ff0c18	1399	#define BS_SPI_SR_TXCTR (4U) //!< Bit field size in bits for SPI_SR_TXCTR.
mbed_official	146:f64d43ff0c18	1400
mbed_official	146:f64d43ff0c18	1401	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1402	//! @brief Read current value of the SPI_SR_TXCTR field.
mbed_official	146:f64d43ff0c18	1403	#define BR_SPI_SR_TXCTR(x) (HW_SPI_SR(x).B.TXCTR)
mbed_official	146:f64d43ff0c18	1404	#endif
mbed_official	146:f64d43ff0c18	1405	//@}
mbed_official	146:f64d43ff0c18	1406
mbed_official	146:f64d43ff0c18	1407	/*!
mbed_official	146:f64d43ff0c18	1408	* @name Register SPI_SR, field RFDF[17] (W1C)
mbed_official	146:f64d43ff0c18	1409	*
mbed_official	146:f64d43ff0c18	1410	* Provides a method for the module to request that entries be removed from the
mbed_official	146:f64d43ff0c18	1411	* RX FIFO. The bit is set while the RX FIFO is not empty. The RFDF bit can be
mbed_official	146:f64d43ff0c18	1412	* cleared by writing 1 to it or by acknowledgement from the DMA controller when
mbed_official	146:f64d43ff0c18	1413	* the RX FIFO is empty.
mbed_official	146:f64d43ff0c18	1414	*
mbed_official	146:f64d43ff0c18	1415	* Values:
mbed_official	146:f64d43ff0c18	1416	* - 0 - RX FIFO is empty.
mbed_official	146:f64d43ff0c18	1417	* - 1 - RX FIFO is not empty.
mbed_official	146:f64d43ff0c18	1418	*/
mbed_official	146:f64d43ff0c18	1419	//@{
mbed_official	146:f64d43ff0c18	1420	#define BP_SPI_SR_RFDF (17U) //!< Bit position for SPI_SR_RFDF.
mbed_official	146:f64d43ff0c18	1421	#define BM_SPI_SR_RFDF (0x00020000U) //!< Bit mask for SPI_SR_RFDF.
mbed_official	146:f64d43ff0c18	1422	#define BS_SPI_SR_RFDF (1U) //!< Bit field size in bits for SPI_SR_RFDF.
mbed_official	146:f64d43ff0c18	1423
mbed_official	146:f64d43ff0c18	1424	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1425	//! @brief Read current value of the SPI_SR_RFDF field.
mbed_official	146:f64d43ff0c18	1426	#define BR_SPI_SR_RFDF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFDF))
mbed_official	146:f64d43ff0c18	1427	#endif
mbed_official	146:f64d43ff0c18	1428
mbed_official	146:f64d43ff0c18	1429	//! @brief Format value for bitfield SPI_SR_RFDF.
mbed_official	146:f64d43ff0c18	1430	#define BF_SPI_SR_RFDF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_SR_RFDF), uint32_t) & BM_SPI_SR_RFDF)
mbed_official	146:f64d43ff0c18	1431
mbed_official	146:f64d43ff0c18	1432	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1433	//! @brief Set the RFDF field to a new value.
mbed_official	146:f64d43ff0c18	1434	#define BW_SPI_SR_RFDF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFDF) = (v))
mbed_official	146:f64d43ff0c18	1435	#endif
mbed_official	146:f64d43ff0c18	1436	//@}
mbed_official	146:f64d43ff0c18	1437
mbed_official	146:f64d43ff0c18	1438	/*!
mbed_official	146:f64d43ff0c18	1439	* @name Register SPI_SR, field RFOF[19] (W1C)
mbed_official	146:f64d43ff0c18	1440	*
mbed_official	146:f64d43ff0c18	1441	* Indicates an overflow condition in the RX FIFO. The field is set when the RX
mbed_official	146:f64d43ff0c18	1442	* FIFO and shift register are full and a transfer is initiated. The bit remains
mbed_official	146:f64d43ff0c18	1443	* set until it is cleared by writing a 1 to it.
mbed_official	146:f64d43ff0c18	1444	*
mbed_official	146:f64d43ff0c18	1445	* Values:
mbed_official	146:f64d43ff0c18	1446	* - 0 - No Rx FIFO overflow.
mbed_official	146:f64d43ff0c18	1447	* - 1 - Rx FIFO overflow has occurred.
mbed_official	146:f64d43ff0c18	1448	*/
mbed_official	146:f64d43ff0c18	1449	//@{
mbed_official	146:f64d43ff0c18	1450	#define BP_SPI_SR_RFOF (19U) //!< Bit position for SPI_SR_RFOF.
mbed_official	146:f64d43ff0c18	1451	#define BM_SPI_SR_RFOF (0x00080000U) //!< Bit mask for SPI_SR_RFOF.
mbed_official	146:f64d43ff0c18	1452	#define BS_SPI_SR_RFOF (1U) //!< Bit field size in bits for SPI_SR_RFOF.
mbed_official	146:f64d43ff0c18	1453
mbed_official	146:f64d43ff0c18	1454	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1455	//! @brief Read current value of the SPI_SR_RFOF field.
mbed_official	146:f64d43ff0c18	1456	#define BR_SPI_SR_RFOF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFOF))
mbed_official	146:f64d43ff0c18	1457	#endif
mbed_official	146:f64d43ff0c18	1458
mbed_official	146:f64d43ff0c18	1459	//! @brief Format value for bitfield SPI_SR_RFOF.
mbed_official	146:f64d43ff0c18	1460	#define BF_SPI_SR_RFOF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_SR_RFOF), uint32_t) & BM_SPI_SR_RFOF)
mbed_official	146:f64d43ff0c18	1461
mbed_official	146:f64d43ff0c18	1462	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1463	//! @brief Set the RFOF field to a new value.
mbed_official	146:f64d43ff0c18	1464	#define BW_SPI_SR_RFOF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFOF) = (v))
mbed_official	146:f64d43ff0c18	1465	#endif
mbed_official	146:f64d43ff0c18	1466	//@}
mbed_official	146:f64d43ff0c18	1467
mbed_official	146:f64d43ff0c18	1468	/*!
mbed_official	146:f64d43ff0c18	1469	* @name Register SPI_SR, field TFFF[25] (W1C)
mbed_official	146:f64d43ff0c18	1470	*
mbed_official	146:f64d43ff0c18	1471	* Provides a method for the module to request more entries to be added to the
mbed_official	146:f64d43ff0c18	1472	* TX FIFO. The TFFF bit is set while the TX FIFO is not full. The TFFF bit can be
mbed_official	146:f64d43ff0c18	1473	* cleared by writing 1 to it or by acknowledgement from the DMA controller to
mbed_official	146:f64d43ff0c18	1474	* the TX FIFO full request.
mbed_official	146:f64d43ff0c18	1475	*
mbed_official	146:f64d43ff0c18	1476	* Values:
mbed_official	146:f64d43ff0c18	1477	* - 0 - TX FIFO is full.
mbed_official	146:f64d43ff0c18	1478	* - 1 - TX FIFO is not full.
mbed_official	146:f64d43ff0c18	1479	*/
mbed_official	146:f64d43ff0c18	1480	//@{
mbed_official	146:f64d43ff0c18	1481	#define BP_SPI_SR_TFFF (25U) //!< Bit position for SPI_SR_TFFF.
mbed_official	146:f64d43ff0c18	1482	#define BM_SPI_SR_TFFF (0x02000000U) //!< Bit mask for SPI_SR_TFFF.
mbed_official	146:f64d43ff0c18	1483	#define BS_SPI_SR_TFFF (1U) //!< Bit field size in bits for SPI_SR_TFFF.
mbed_official	146:f64d43ff0c18	1484
mbed_official	146:f64d43ff0c18	1485	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1486	//! @brief Read current value of the SPI_SR_TFFF field.
mbed_official	146:f64d43ff0c18	1487	#define BR_SPI_SR_TFFF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFFF))
mbed_official	146:f64d43ff0c18	1488	#endif
mbed_official	146:f64d43ff0c18	1489
mbed_official	146:f64d43ff0c18	1490	//! @brief Format value for bitfield SPI_SR_TFFF.
mbed_official	146:f64d43ff0c18	1491	#define BF_SPI_SR_TFFF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_SR_TFFF), uint32_t) & BM_SPI_SR_TFFF)
mbed_official	146:f64d43ff0c18	1492
mbed_official	146:f64d43ff0c18	1493	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1494	//! @brief Set the TFFF field to a new value.
mbed_official	146:f64d43ff0c18	1495	#define BW_SPI_SR_TFFF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFFF) = (v))
mbed_official	146:f64d43ff0c18	1496	#endif
mbed_official	146:f64d43ff0c18	1497	//@}
mbed_official	146:f64d43ff0c18	1498
mbed_official	146:f64d43ff0c18	1499	/*!
mbed_official	146:f64d43ff0c18	1500	* @name Register SPI_SR, field TFUF[27] (W1C)
mbed_official	146:f64d43ff0c18	1501	*
mbed_official	146:f64d43ff0c18	1502	* Indicates an underflow condition in the TX FIFO. The transmit underflow
mbed_official	146:f64d43ff0c18	1503	* condition is detected only for SPI blocks operating in Slave mode and SPI
mbed_official	146:f64d43ff0c18	1504	* configuration. TFUF is set when the TX FIFO of the module operating in SPI Slave mode
mbed_official	146:f64d43ff0c18	1505	* is empty and an external SPI master initiates a transfer. The TFUF bit remains
mbed_official	146:f64d43ff0c18	1506	* set until cleared by writing 1 to it.
mbed_official	146:f64d43ff0c18	1507	*
mbed_official	146:f64d43ff0c18	1508	* Values:
mbed_official	146:f64d43ff0c18	1509	* - 0 - No TX FIFO underflow.
mbed_official	146:f64d43ff0c18	1510	* - 1 - TX FIFO underflow has occurred.
mbed_official	146:f64d43ff0c18	1511	*/
mbed_official	146:f64d43ff0c18	1512	//@{
mbed_official	146:f64d43ff0c18	1513	#define BP_SPI_SR_TFUF (27U) //!< Bit position for SPI_SR_TFUF.
mbed_official	146:f64d43ff0c18	1514	#define BM_SPI_SR_TFUF (0x08000000U) //!< Bit mask for SPI_SR_TFUF.
mbed_official	146:f64d43ff0c18	1515	#define BS_SPI_SR_TFUF (1U) //!< Bit field size in bits for SPI_SR_TFUF.
mbed_official	146:f64d43ff0c18	1516
mbed_official	146:f64d43ff0c18	1517	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1518	//! @brief Read current value of the SPI_SR_TFUF field.
mbed_official	146:f64d43ff0c18	1519	#define BR_SPI_SR_TFUF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFUF))
mbed_official	146:f64d43ff0c18	1520	#endif
mbed_official	146:f64d43ff0c18	1521
mbed_official	146:f64d43ff0c18	1522	//! @brief Format value for bitfield SPI_SR_TFUF.
mbed_official	146:f64d43ff0c18	1523	#define BF_SPI_SR_TFUF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_SR_TFUF), uint32_t) & BM_SPI_SR_TFUF)
mbed_official	146:f64d43ff0c18	1524
mbed_official	146:f64d43ff0c18	1525	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1526	//! @brief Set the TFUF field to a new value.
mbed_official	146:f64d43ff0c18	1527	#define BW_SPI_SR_TFUF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFUF) = (v))
mbed_official	146:f64d43ff0c18	1528	#endif
mbed_official	146:f64d43ff0c18	1529	//@}
mbed_official	146:f64d43ff0c18	1530
mbed_official	146:f64d43ff0c18	1531	/*!
mbed_official	146:f64d43ff0c18	1532	* @name Register SPI_SR, field EOQF[28] (W1C)
mbed_official	146:f64d43ff0c18	1533	*
mbed_official	146:f64d43ff0c18	1534	* Indicates that the last entry in a queue has been transmitted when the module
mbed_official	146:f64d43ff0c18	1535	* is in Master mode. The EOQF bit is set when the TX FIFO entry has the EOQ bit
mbed_official	146:f64d43ff0c18	1536	* set in the command halfword and the end of the transfer is reached. The EOQF
mbed_official	146:f64d43ff0c18	1537	* bit remains set until cleared by writing a 1 to it. When the EOQF bit is set,
mbed_official	146:f64d43ff0c18	1538	* the TXRXS bit is automatically cleared.
mbed_official	146:f64d43ff0c18	1539	*
mbed_official	146:f64d43ff0c18	1540	* Values:
mbed_official	146:f64d43ff0c18	1541	* - 0 - EOQ is not set in the executing command.
mbed_official	146:f64d43ff0c18	1542	* - 1 - EOQ is set in the executing SPI command.
mbed_official	146:f64d43ff0c18	1543	*/
mbed_official	146:f64d43ff0c18	1544	//@{
mbed_official	146:f64d43ff0c18	1545	#define BP_SPI_SR_EOQF (28U) //!< Bit position for SPI_SR_EOQF.
mbed_official	146:f64d43ff0c18	1546	#define BM_SPI_SR_EOQF (0x10000000U) //!< Bit mask for SPI_SR_EOQF.
mbed_official	146:f64d43ff0c18	1547	#define BS_SPI_SR_EOQF (1U) //!< Bit field size in bits for SPI_SR_EOQF.
mbed_official	146:f64d43ff0c18	1548
mbed_official	146:f64d43ff0c18	1549	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1550	//! @brief Read current value of the SPI_SR_EOQF field.
mbed_official	146:f64d43ff0c18	1551	#define BR_SPI_SR_EOQF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_EOQF))
mbed_official	146:f64d43ff0c18	1552	#endif
mbed_official	146:f64d43ff0c18	1553
mbed_official	146:f64d43ff0c18	1554	//! @brief Format value for bitfield SPI_SR_EOQF.
mbed_official	146:f64d43ff0c18	1555	#define BF_SPI_SR_EOQF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_SR_EOQF), uint32_t) & BM_SPI_SR_EOQF)
mbed_official	146:f64d43ff0c18	1556
mbed_official	146:f64d43ff0c18	1557	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1558	//! @brief Set the EOQF field to a new value.
mbed_official	146:f64d43ff0c18	1559	#define BW_SPI_SR_EOQF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_EOQF) = (v))
mbed_official	146:f64d43ff0c18	1560	#endif
mbed_official	146:f64d43ff0c18	1561	//@}
mbed_official	146:f64d43ff0c18	1562
mbed_official	146:f64d43ff0c18	1563	/*!
mbed_official	146:f64d43ff0c18	1564	* @name Register SPI_SR, field TXRXS[30] (W1C)
mbed_official	146:f64d43ff0c18	1565	*
mbed_official	146:f64d43ff0c18	1566	* Reflects the run status of the module.
mbed_official	146:f64d43ff0c18	1567	*
mbed_official	146:f64d43ff0c18	1568	* Values:
mbed_official	146:f64d43ff0c18	1569	* - 0 - Transmit and receive operations are disabled (The module is in Stopped
mbed_official	146:f64d43ff0c18	1570	* state).
mbed_official	146:f64d43ff0c18	1571	* - 1 - Transmit and receive operations are enabled (The module is in Running
mbed_official	146:f64d43ff0c18	1572	* state).
mbed_official	146:f64d43ff0c18	1573	*/
mbed_official	146:f64d43ff0c18	1574	//@{
mbed_official	146:f64d43ff0c18	1575	#define BP_SPI_SR_TXRXS (30U) //!< Bit position for SPI_SR_TXRXS.
mbed_official	146:f64d43ff0c18	1576	#define BM_SPI_SR_TXRXS (0x40000000U) //!< Bit mask for SPI_SR_TXRXS.
mbed_official	146:f64d43ff0c18	1577	#define BS_SPI_SR_TXRXS (1U) //!< Bit field size in bits for SPI_SR_TXRXS.
mbed_official	146:f64d43ff0c18	1578
mbed_official	146:f64d43ff0c18	1579	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1580	//! @brief Read current value of the SPI_SR_TXRXS field.
mbed_official	146:f64d43ff0c18	1581	#define BR_SPI_SR_TXRXS(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TXRXS))
mbed_official	146:f64d43ff0c18	1582	#endif
mbed_official	146:f64d43ff0c18	1583
mbed_official	146:f64d43ff0c18	1584	//! @brief Format value for bitfield SPI_SR_TXRXS.
mbed_official	146:f64d43ff0c18	1585	#define BF_SPI_SR_TXRXS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_SR_TXRXS), uint32_t) & BM_SPI_SR_TXRXS)
mbed_official	146:f64d43ff0c18	1586
mbed_official	146:f64d43ff0c18	1587	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1588	//! @brief Set the TXRXS field to a new value.
mbed_official	146:f64d43ff0c18	1589	#define BW_SPI_SR_TXRXS(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TXRXS) = (v))
mbed_official	146:f64d43ff0c18	1590	#endif
mbed_official	146:f64d43ff0c18	1591	//@}
mbed_official	146:f64d43ff0c18	1592
mbed_official	146:f64d43ff0c18	1593	/*!
mbed_official	146:f64d43ff0c18	1594	* @name Register SPI_SR, field TCF[31] (W1C)
mbed_official	146:f64d43ff0c18	1595	*
mbed_official	146:f64d43ff0c18	1596	* Indicates that all bits in a frame have been shifted out. TCF remains set
mbed_official	146:f64d43ff0c18	1597	* until it is cleared by writing a 1 to it.
mbed_official	146:f64d43ff0c18	1598	*
mbed_official	146:f64d43ff0c18	1599	* Values:
mbed_official	146:f64d43ff0c18	1600	* - 0 - Transfer not complete.
mbed_official	146:f64d43ff0c18	1601	* - 1 - Transfer complete.
mbed_official	146:f64d43ff0c18	1602	*/
mbed_official	146:f64d43ff0c18	1603	//@{
mbed_official	146:f64d43ff0c18	1604	#define BP_SPI_SR_TCF (31U) //!< Bit position for SPI_SR_TCF.
mbed_official	146:f64d43ff0c18	1605	#define BM_SPI_SR_TCF (0x80000000U) //!< Bit mask for SPI_SR_TCF.
mbed_official	146:f64d43ff0c18	1606	#define BS_SPI_SR_TCF (1U) //!< Bit field size in bits for SPI_SR_TCF.
mbed_official	146:f64d43ff0c18	1607
mbed_official	146:f64d43ff0c18	1608	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1609	//! @brief Read current value of the SPI_SR_TCF field.
mbed_official	146:f64d43ff0c18	1610	#define BR_SPI_SR_TCF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TCF))
mbed_official	146:f64d43ff0c18	1611	#endif
mbed_official	146:f64d43ff0c18	1612
mbed_official	146:f64d43ff0c18	1613	//! @brief Format value for bitfield SPI_SR_TCF.
mbed_official	146:f64d43ff0c18	1614	#define BF_SPI_SR_TCF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_SR_TCF), uint32_t) & BM_SPI_SR_TCF)
mbed_official	146:f64d43ff0c18	1615
mbed_official	146:f64d43ff0c18	1616	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1617	//! @brief Set the TCF field to a new value.
mbed_official	146:f64d43ff0c18	1618	#define BW_SPI_SR_TCF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TCF) = (v))
mbed_official	146:f64d43ff0c18	1619	#endif
mbed_official	146:f64d43ff0c18	1620	//@}
mbed_official	146:f64d43ff0c18	1621
mbed_official	146:f64d43ff0c18	1622	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1623	// HW_SPI_RSER - DMA/Interrupt Request Select and Enable Register
mbed_official	146:f64d43ff0c18	1624	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1625
mbed_official	146:f64d43ff0c18	1626	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1627	/*!
mbed_official	146:f64d43ff0c18	1628	* @brief HW_SPI_RSER - DMA/Interrupt Request Select and Enable Register (RW)
mbed_official	146:f64d43ff0c18	1629	*
mbed_official	146:f64d43ff0c18	1630	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	1631	*
mbed_official	146:f64d43ff0c18	1632	* RSER controls DMA and interrupt requests. Do not write to the RSER while the
mbed_official	146:f64d43ff0c18	1633	* module is in the Running state.
mbed_official	146:f64d43ff0c18	1634	*/
mbed_official	146:f64d43ff0c18	1635	typedef union _hw_spi_rser
mbed_official	146:f64d43ff0c18	1636	{
mbed_official	146:f64d43ff0c18	1637	uint32_t U;
mbed_official	146:f64d43ff0c18	1638	struct _hw_spi_rser_bitfields
mbed_official	146:f64d43ff0c18	1639	{
mbed_official	146:f64d43ff0c18	1640	uint32_t RESERVED0 : 16; //!< [15:0]
mbed_official	146:f64d43ff0c18	1641	uint32_t RFDF_DIRS : 1; //!< [16] Receive FIFO Drain DMA or Interrupt
mbed_official	146:f64d43ff0c18	1642	//! Request Select
mbed_official	146:f64d43ff0c18	1643	uint32_t RFDF_RE : 1; //!< [17] Receive FIFO Drain Request Enable
mbed_official	146:f64d43ff0c18	1644	uint32_t RESERVED1 : 1; //!< [18]
mbed_official	146:f64d43ff0c18	1645	uint32_t RFOF_RE : 1; //!< [19] Receive FIFO Overflow Request Enable
mbed_official	146:f64d43ff0c18	1646	uint32_t RESERVED2 : 4; //!< [23:20]
mbed_official	146:f64d43ff0c18	1647	uint32_t TFFF_DIRS : 1; //!< [24] Transmit FIFO Fill DMA or Interrupt
mbed_official	146:f64d43ff0c18	1648	//! Request Select
mbed_official	146:f64d43ff0c18	1649	uint32_t TFFF_RE : 1; //!< [25] Transmit FIFO Fill Request Enable
mbed_official	146:f64d43ff0c18	1650	uint32_t RESERVED3 : 1; //!< [26]
mbed_official	146:f64d43ff0c18	1651	uint32_t TFUF_RE : 1; //!< [27] Transmit FIFO Underflow Request Enable
mbed_official	146:f64d43ff0c18	1652	uint32_t EOQF_RE : 1; //!< [28] Finished Request Enable
mbed_official	146:f64d43ff0c18	1653	uint32_t RESERVED4 : 2; //!< [30:29]
mbed_official	146:f64d43ff0c18	1654	uint32_t TCF_RE : 1; //!< [31] Transmission Complete Request Enable
mbed_official	146:f64d43ff0c18	1655	} B;
mbed_official	146:f64d43ff0c18	1656	} hw_spi_rser_t;
mbed_official	146:f64d43ff0c18	1657	#endif
mbed_official	146:f64d43ff0c18	1658
mbed_official	146:f64d43ff0c18	1659	/*!
mbed_official	146:f64d43ff0c18	1660	* @name Constants and macros for entire SPI_RSER register
mbed_official	146:f64d43ff0c18	1661	*/
mbed_official	146:f64d43ff0c18	1662	//@{
mbed_official	146:f64d43ff0c18	1663	#define HW_SPI_RSER_ADDR(x) (REGS_SPI_BASE(x) + 0x30U)
mbed_official	146:f64d43ff0c18	1664
mbed_official	146:f64d43ff0c18	1665	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1666	#define HW_SPI_RSER(x) ((__IO hw_spi_rser_t ) HW_SPI_RSER_ADDR(x))
mbed_official	146:f64d43ff0c18	1667	#define HW_SPI_RSER_RD(x) (HW_SPI_RSER(x).U)
mbed_official	146:f64d43ff0c18	1668	#define HW_SPI_RSER_WR(x, v) (HW_SPI_RSER(x).U = (v))
mbed_official	146:f64d43ff0c18	1669	#define HW_SPI_RSER_SET(x, v) (HW_SPI_RSER_WR(x, HW_SPI_RSER_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	1670	#define HW_SPI_RSER_CLR(x, v) (HW_SPI_RSER_WR(x, HW_SPI_RSER_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	1671	#define HW_SPI_RSER_TOG(x, v) (HW_SPI_RSER_WR(x, HW_SPI_RSER_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	1672	#endif
mbed_official	146:f64d43ff0c18	1673	//@}
mbed_official	146:f64d43ff0c18	1674
mbed_official	146:f64d43ff0c18	1675	/*
mbed_official	146:f64d43ff0c18	1676	* Constants & macros for individual SPI_RSER bitfields
mbed_official	146:f64d43ff0c18	1677	*/
mbed_official	146:f64d43ff0c18	1678
mbed_official	146:f64d43ff0c18	1679	/*!
mbed_official	146:f64d43ff0c18	1680	* @name Register SPI_RSER, field RFDF_DIRS[16] (RW)
mbed_official	146:f64d43ff0c18	1681	*
mbed_official	146:f64d43ff0c18	1682	* Selects between generating a DMA request or an interrupt request. When the
mbed_official	146:f64d43ff0c18	1683	* RFDF flag bit in the SR is set, and the RFDF_RE bit in the RSER is set, the
mbed_official	146:f64d43ff0c18	1684	* RFDF_DIRS bit selects between generating an interrupt request or a DMA request.
mbed_official	146:f64d43ff0c18	1685	*
mbed_official	146:f64d43ff0c18	1686	* Values:
mbed_official	146:f64d43ff0c18	1687	* - 0 - Interrupt request.
mbed_official	146:f64d43ff0c18	1688	* - 1 - DMA request.
mbed_official	146:f64d43ff0c18	1689	*/
mbed_official	146:f64d43ff0c18	1690	//@{
mbed_official	146:f64d43ff0c18	1691	#define BP_SPI_RSER_RFDF_DIRS (16U) //!< Bit position for SPI_RSER_RFDF_DIRS.
mbed_official	146:f64d43ff0c18	1692	#define BM_SPI_RSER_RFDF_DIRS (0x00010000U) //!< Bit mask for SPI_RSER_RFDF_DIRS.
mbed_official	146:f64d43ff0c18	1693	#define BS_SPI_RSER_RFDF_DIRS (1U) //!< Bit field size in bits for SPI_RSER_RFDF_DIRS.
mbed_official	146:f64d43ff0c18	1694
mbed_official	146:f64d43ff0c18	1695	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1696	//! @brief Read current value of the SPI_RSER_RFDF_DIRS field.
mbed_official	146:f64d43ff0c18	1697	#define BR_SPI_RSER_RFDF_DIRS(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_DIRS))
mbed_official	146:f64d43ff0c18	1698	#endif
mbed_official	146:f64d43ff0c18	1699
mbed_official	146:f64d43ff0c18	1700	//! @brief Format value for bitfield SPI_RSER_RFDF_DIRS.
mbed_official	146:f64d43ff0c18	1701	#define BF_SPI_RSER_RFDF_DIRS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_RFDF_DIRS), uint32_t) & BM_SPI_RSER_RFDF_DIRS)
mbed_official	146:f64d43ff0c18	1702
mbed_official	146:f64d43ff0c18	1703	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1704	//! @brief Set the RFDF_DIRS field to a new value.
mbed_official	146:f64d43ff0c18	1705	#define BW_SPI_RSER_RFDF_DIRS(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_DIRS) = (v))
mbed_official	146:f64d43ff0c18	1706	#endif
mbed_official	146:f64d43ff0c18	1707	//@}
mbed_official	146:f64d43ff0c18	1708
mbed_official	146:f64d43ff0c18	1709	/*!
mbed_official	146:f64d43ff0c18	1710	* @name Register SPI_RSER, field RFDF_RE[17] (RW)
mbed_official	146:f64d43ff0c18	1711	*
mbed_official	146:f64d43ff0c18	1712	* Enables the RFDF flag in the SR to generate a request. The RFDF_DIRS bit
mbed_official	146:f64d43ff0c18	1713	* selects between generating an interrupt request or a DMA request.
mbed_official	146:f64d43ff0c18	1714	*
mbed_official	146:f64d43ff0c18	1715	* Values:
mbed_official	146:f64d43ff0c18	1716	* - 0 - RFDF interrupt or DMA requests are disabled.
mbed_official	146:f64d43ff0c18	1717	* - 1 - RFDF interrupt or DMA requests are enabled.
mbed_official	146:f64d43ff0c18	1718	*/
mbed_official	146:f64d43ff0c18	1719	//@{
mbed_official	146:f64d43ff0c18	1720	#define BP_SPI_RSER_RFDF_RE (17U) //!< Bit position for SPI_RSER_RFDF_RE.
mbed_official	146:f64d43ff0c18	1721	#define BM_SPI_RSER_RFDF_RE (0x00020000U) //!< Bit mask for SPI_RSER_RFDF_RE.
mbed_official	146:f64d43ff0c18	1722	#define BS_SPI_RSER_RFDF_RE (1U) //!< Bit field size in bits for SPI_RSER_RFDF_RE.
mbed_official	146:f64d43ff0c18	1723
mbed_official	146:f64d43ff0c18	1724	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1725	//! @brief Read current value of the SPI_RSER_RFDF_RE field.
mbed_official	146:f64d43ff0c18	1726	#define BR_SPI_RSER_RFDF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_RE))
mbed_official	146:f64d43ff0c18	1727	#endif
mbed_official	146:f64d43ff0c18	1728
mbed_official	146:f64d43ff0c18	1729	//! @brief Format value for bitfield SPI_RSER_RFDF_RE.
mbed_official	146:f64d43ff0c18	1730	#define BF_SPI_RSER_RFDF_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_RFDF_RE), uint32_t) & BM_SPI_RSER_RFDF_RE)
mbed_official	146:f64d43ff0c18	1731
mbed_official	146:f64d43ff0c18	1732	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1733	//! @brief Set the RFDF_RE field to a new value.
mbed_official	146:f64d43ff0c18	1734	#define BW_SPI_RSER_RFDF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_RE) = (v))
mbed_official	146:f64d43ff0c18	1735	#endif
mbed_official	146:f64d43ff0c18	1736	//@}
mbed_official	146:f64d43ff0c18	1737
mbed_official	146:f64d43ff0c18	1738	/*!
mbed_official	146:f64d43ff0c18	1739	* @name Register SPI_RSER, field RFOF_RE[19] (RW)
mbed_official	146:f64d43ff0c18	1740	*
mbed_official	146:f64d43ff0c18	1741	* Enables the RFOF flag in the SR to generate an interrupt request.
mbed_official	146:f64d43ff0c18	1742	*
mbed_official	146:f64d43ff0c18	1743	* Values:
mbed_official	146:f64d43ff0c18	1744	* - 0 - RFOF interrupt requests are disabled.
mbed_official	146:f64d43ff0c18	1745	* - 1 - RFOF interrupt requests are enabled.
mbed_official	146:f64d43ff0c18	1746	*/
mbed_official	146:f64d43ff0c18	1747	//@{
mbed_official	146:f64d43ff0c18	1748	#define BP_SPI_RSER_RFOF_RE (19U) //!< Bit position for SPI_RSER_RFOF_RE.
mbed_official	146:f64d43ff0c18	1749	#define BM_SPI_RSER_RFOF_RE (0x00080000U) //!< Bit mask for SPI_RSER_RFOF_RE.
mbed_official	146:f64d43ff0c18	1750	#define BS_SPI_RSER_RFOF_RE (1U) //!< Bit field size in bits for SPI_RSER_RFOF_RE.
mbed_official	146:f64d43ff0c18	1751
mbed_official	146:f64d43ff0c18	1752	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1753	//! @brief Read current value of the SPI_RSER_RFOF_RE field.
mbed_official	146:f64d43ff0c18	1754	#define BR_SPI_RSER_RFOF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFOF_RE))
mbed_official	146:f64d43ff0c18	1755	#endif
mbed_official	146:f64d43ff0c18	1756
mbed_official	146:f64d43ff0c18	1757	//! @brief Format value for bitfield SPI_RSER_RFOF_RE.
mbed_official	146:f64d43ff0c18	1758	#define BF_SPI_RSER_RFOF_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_RFOF_RE), uint32_t) & BM_SPI_RSER_RFOF_RE)
mbed_official	146:f64d43ff0c18	1759
mbed_official	146:f64d43ff0c18	1760	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1761	//! @brief Set the RFOF_RE field to a new value.
mbed_official	146:f64d43ff0c18	1762	#define BW_SPI_RSER_RFOF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFOF_RE) = (v))
mbed_official	146:f64d43ff0c18	1763	#endif
mbed_official	146:f64d43ff0c18	1764	//@}
mbed_official	146:f64d43ff0c18	1765
mbed_official	146:f64d43ff0c18	1766	/*!
mbed_official	146:f64d43ff0c18	1767	* @name Register SPI_RSER, field TFFF_DIRS[24] (RW)
mbed_official	146:f64d43ff0c18	1768	*
mbed_official	146:f64d43ff0c18	1769	* Selects between generating a DMA request or an interrupt request. When
mbed_official	146:f64d43ff0c18	1770	* SR[TFFF] and RSER[TFFF_RE] are set, this field selects between generating an
mbed_official	146:f64d43ff0c18	1771	* interrupt request or a DMA request.
mbed_official	146:f64d43ff0c18	1772	*
mbed_official	146:f64d43ff0c18	1773	* Values:
mbed_official	146:f64d43ff0c18	1774	* - 0 - TFFF flag generates interrupt requests.
mbed_official	146:f64d43ff0c18	1775	* - 1 - TFFF flag generates DMA requests.
mbed_official	146:f64d43ff0c18	1776	*/
mbed_official	146:f64d43ff0c18	1777	//@{
mbed_official	146:f64d43ff0c18	1778	#define BP_SPI_RSER_TFFF_DIRS (24U) //!< Bit position for SPI_RSER_TFFF_DIRS.
mbed_official	146:f64d43ff0c18	1779	#define BM_SPI_RSER_TFFF_DIRS (0x01000000U) //!< Bit mask for SPI_RSER_TFFF_DIRS.
mbed_official	146:f64d43ff0c18	1780	#define BS_SPI_RSER_TFFF_DIRS (1U) //!< Bit field size in bits for SPI_RSER_TFFF_DIRS.
mbed_official	146:f64d43ff0c18	1781
mbed_official	146:f64d43ff0c18	1782	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1783	//! @brief Read current value of the SPI_RSER_TFFF_DIRS field.
mbed_official	146:f64d43ff0c18	1784	#define BR_SPI_RSER_TFFF_DIRS(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_DIRS))
mbed_official	146:f64d43ff0c18	1785	#endif
mbed_official	146:f64d43ff0c18	1786
mbed_official	146:f64d43ff0c18	1787	//! @brief Format value for bitfield SPI_RSER_TFFF_DIRS.
mbed_official	146:f64d43ff0c18	1788	#define BF_SPI_RSER_TFFF_DIRS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_TFFF_DIRS), uint32_t) & BM_SPI_RSER_TFFF_DIRS)
mbed_official	146:f64d43ff0c18	1789
mbed_official	146:f64d43ff0c18	1790	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1791	//! @brief Set the TFFF_DIRS field to a new value.
mbed_official	146:f64d43ff0c18	1792	#define BW_SPI_RSER_TFFF_DIRS(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_DIRS) = (v))
mbed_official	146:f64d43ff0c18	1793	#endif
mbed_official	146:f64d43ff0c18	1794	//@}
mbed_official	146:f64d43ff0c18	1795
mbed_official	146:f64d43ff0c18	1796	/*!
mbed_official	146:f64d43ff0c18	1797	* @name Register SPI_RSER, field TFFF_RE[25] (RW)
mbed_official	146:f64d43ff0c18	1798	*
mbed_official	146:f64d43ff0c18	1799	* Enables the TFFF flag in the SR to generate a request. The TFFF_DIRS bit
mbed_official	146:f64d43ff0c18	1800	* selects between generating an interrupt request or a DMA request.
mbed_official	146:f64d43ff0c18	1801	*
mbed_official	146:f64d43ff0c18	1802	* Values:
mbed_official	146:f64d43ff0c18	1803	* - 0 - TFFF interrupts or DMA requests are disabled.
mbed_official	146:f64d43ff0c18	1804	* - 1 - TFFF interrupts or DMA requests are enabled.
mbed_official	146:f64d43ff0c18	1805	*/
mbed_official	146:f64d43ff0c18	1806	//@{
mbed_official	146:f64d43ff0c18	1807	#define BP_SPI_RSER_TFFF_RE (25U) //!< Bit position for SPI_RSER_TFFF_RE.
mbed_official	146:f64d43ff0c18	1808	#define BM_SPI_RSER_TFFF_RE (0x02000000U) //!< Bit mask for SPI_RSER_TFFF_RE.
mbed_official	146:f64d43ff0c18	1809	#define BS_SPI_RSER_TFFF_RE (1U) //!< Bit field size in bits for SPI_RSER_TFFF_RE.
mbed_official	146:f64d43ff0c18	1810
mbed_official	146:f64d43ff0c18	1811	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1812	//! @brief Read current value of the SPI_RSER_TFFF_RE field.
mbed_official	146:f64d43ff0c18	1813	#define BR_SPI_RSER_TFFF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_RE))
mbed_official	146:f64d43ff0c18	1814	#endif
mbed_official	146:f64d43ff0c18	1815
mbed_official	146:f64d43ff0c18	1816	//! @brief Format value for bitfield SPI_RSER_TFFF_RE.
mbed_official	146:f64d43ff0c18	1817	#define BF_SPI_RSER_TFFF_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_TFFF_RE), uint32_t) & BM_SPI_RSER_TFFF_RE)
mbed_official	146:f64d43ff0c18	1818
mbed_official	146:f64d43ff0c18	1819	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1820	//! @brief Set the TFFF_RE field to a new value.
mbed_official	146:f64d43ff0c18	1821	#define BW_SPI_RSER_TFFF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_RE) = (v))
mbed_official	146:f64d43ff0c18	1822	#endif
mbed_official	146:f64d43ff0c18	1823	//@}
mbed_official	146:f64d43ff0c18	1824
mbed_official	146:f64d43ff0c18	1825	/*!
mbed_official	146:f64d43ff0c18	1826	* @name Register SPI_RSER, field TFUF_RE[27] (RW)
mbed_official	146:f64d43ff0c18	1827	*
mbed_official	146:f64d43ff0c18	1828	* Enables the TFUF flag in the SR to generate an interrupt request.
mbed_official	146:f64d43ff0c18	1829	*
mbed_official	146:f64d43ff0c18	1830	* Values:
mbed_official	146:f64d43ff0c18	1831	* - 0 - TFUF interrupt requests are disabled.
mbed_official	146:f64d43ff0c18	1832	* - 1 - TFUF interrupt requests are enabled.
mbed_official	146:f64d43ff0c18	1833	*/
mbed_official	146:f64d43ff0c18	1834	//@{
mbed_official	146:f64d43ff0c18	1835	#define BP_SPI_RSER_TFUF_RE (27U) //!< Bit position for SPI_RSER_TFUF_RE.
mbed_official	146:f64d43ff0c18	1836	#define BM_SPI_RSER_TFUF_RE (0x08000000U) //!< Bit mask for SPI_RSER_TFUF_RE.
mbed_official	146:f64d43ff0c18	1837	#define BS_SPI_RSER_TFUF_RE (1U) //!< Bit field size in bits for SPI_RSER_TFUF_RE.
mbed_official	146:f64d43ff0c18	1838
mbed_official	146:f64d43ff0c18	1839	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1840	//! @brief Read current value of the SPI_RSER_TFUF_RE field.
mbed_official	146:f64d43ff0c18	1841	#define BR_SPI_RSER_TFUF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFUF_RE))
mbed_official	146:f64d43ff0c18	1842	#endif
mbed_official	146:f64d43ff0c18	1843
mbed_official	146:f64d43ff0c18	1844	//! @brief Format value for bitfield SPI_RSER_TFUF_RE.
mbed_official	146:f64d43ff0c18	1845	#define BF_SPI_RSER_TFUF_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_TFUF_RE), uint32_t) & BM_SPI_RSER_TFUF_RE)
mbed_official	146:f64d43ff0c18	1846
mbed_official	146:f64d43ff0c18	1847	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1848	//! @brief Set the TFUF_RE field to a new value.
mbed_official	146:f64d43ff0c18	1849	#define BW_SPI_RSER_TFUF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFUF_RE) = (v))
mbed_official	146:f64d43ff0c18	1850	#endif
mbed_official	146:f64d43ff0c18	1851	//@}
mbed_official	146:f64d43ff0c18	1852
mbed_official	146:f64d43ff0c18	1853	/*!
mbed_official	146:f64d43ff0c18	1854	* @name Register SPI_RSER, field EOQF_RE[28] (RW)
mbed_official	146:f64d43ff0c18	1855	*
mbed_official	146:f64d43ff0c18	1856	* Enables the EOQF flag in the SR to generate an interrupt request.
mbed_official	146:f64d43ff0c18	1857	*
mbed_official	146:f64d43ff0c18	1858	* Values:
mbed_official	146:f64d43ff0c18	1859	* - 0 - EOQF interrupt requests are disabled.
mbed_official	146:f64d43ff0c18	1860	* - 1 - EOQF interrupt requests are enabled.
mbed_official	146:f64d43ff0c18	1861	*/
mbed_official	146:f64d43ff0c18	1862	//@{
mbed_official	146:f64d43ff0c18	1863	#define BP_SPI_RSER_EOQF_RE (28U) //!< Bit position for SPI_RSER_EOQF_RE.
mbed_official	146:f64d43ff0c18	1864	#define BM_SPI_RSER_EOQF_RE (0x10000000U) //!< Bit mask for SPI_RSER_EOQF_RE.
mbed_official	146:f64d43ff0c18	1865	#define BS_SPI_RSER_EOQF_RE (1U) //!< Bit field size in bits for SPI_RSER_EOQF_RE.
mbed_official	146:f64d43ff0c18	1866
mbed_official	146:f64d43ff0c18	1867	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1868	//! @brief Read current value of the SPI_RSER_EOQF_RE field.
mbed_official	146:f64d43ff0c18	1869	#define BR_SPI_RSER_EOQF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_EOQF_RE))
mbed_official	146:f64d43ff0c18	1870	#endif
mbed_official	146:f64d43ff0c18	1871
mbed_official	146:f64d43ff0c18	1872	//! @brief Format value for bitfield SPI_RSER_EOQF_RE.
mbed_official	146:f64d43ff0c18	1873	#define BF_SPI_RSER_EOQF_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_EOQF_RE), uint32_t) & BM_SPI_RSER_EOQF_RE)
mbed_official	146:f64d43ff0c18	1874
mbed_official	146:f64d43ff0c18	1875	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1876	//! @brief Set the EOQF_RE field to a new value.
mbed_official	146:f64d43ff0c18	1877	#define BW_SPI_RSER_EOQF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_EOQF_RE) = (v))
mbed_official	146:f64d43ff0c18	1878	#endif
mbed_official	146:f64d43ff0c18	1879	//@}
mbed_official	146:f64d43ff0c18	1880
mbed_official	146:f64d43ff0c18	1881	/*!
mbed_official	146:f64d43ff0c18	1882	* @name Register SPI_RSER, field TCF_RE[31] (RW)
mbed_official	146:f64d43ff0c18	1883	*
mbed_official	146:f64d43ff0c18	1884	* Enables TCF flag in the SR to generate an interrupt request.
mbed_official	146:f64d43ff0c18	1885	*
mbed_official	146:f64d43ff0c18	1886	* Values:
mbed_official	146:f64d43ff0c18	1887	* - 0 - TCF interrupt requests are disabled.
mbed_official	146:f64d43ff0c18	1888	* - 1 - TCF interrupt requests are enabled.
mbed_official	146:f64d43ff0c18	1889	*/
mbed_official	146:f64d43ff0c18	1890	//@{
mbed_official	146:f64d43ff0c18	1891	#define BP_SPI_RSER_TCF_RE (31U) //!< Bit position for SPI_RSER_TCF_RE.
mbed_official	146:f64d43ff0c18	1892	#define BM_SPI_RSER_TCF_RE (0x80000000U) //!< Bit mask for SPI_RSER_TCF_RE.
mbed_official	146:f64d43ff0c18	1893	#define BS_SPI_RSER_TCF_RE (1U) //!< Bit field size in bits for SPI_RSER_TCF_RE.
mbed_official	146:f64d43ff0c18	1894
mbed_official	146:f64d43ff0c18	1895	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1896	//! @brief Read current value of the SPI_RSER_TCF_RE field.
mbed_official	146:f64d43ff0c18	1897	#define BR_SPI_RSER_TCF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TCF_RE))
mbed_official	146:f64d43ff0c18	1898	#endif
mbed_official	146:f64d43ff0c18	1899
mbed_official	146:f64d43ff0c18	1900	//! @brief Format value for bitfield SPI_RSER_TCF_RE.
mbed_official	146:f64d43ff0c18	1901	#define BF_SPI_RSER_TCF_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_TCF_RE), uint32_t) & BM_SPI_RSER_TCF_RE)
mbed_official	146:f64d43ff0c18	1902
mbed_official	146:f64d43ff0c18	1903	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1904	//! @brief Set the TCF_RE field to a new value.
mbed_official	146:f64d43ff0c18	1905	#define BW_SPI_RSER_TCF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TCF_RE) = (v))
mbed_official	146:f64d43ff0c18	1906	#endif
mbed_official	146:f64d43ff0c18	1907	//@}
mbed_official	146:f64d43ff0c18	1908
mbed_official	146:f64d43ff0c18	1909	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1910	// HW_SPI_PUSHR - PUSH TX FIFO Register In Master Mode
mbed_official	146:f64d43ff0c18	1911	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1912
mbed_official	146:f64d43ff0c18	1913	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1914	/*!
mbed_official	146:f64d43ff0c18	1915	* @brief HW_SPI_PUSHR - PUSH TX FIFO Register In Master Mode (RW)
mbed_official	146:f64d43ff0c18	1916	*
mbed_official	146:f64d43ff0c18	1917	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	1918	*
mbed_official	146:f64d43ff0c18	1919	* Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access
mbed_official	146:f64d43ff0c18	1920	* transfers all 32 bits to the TX FIFO. In Master mode, the register transfers
mbed_official	146:f64d43ff0c18	1921	* 16 bits of data and 16 bits of command information. In Slave mode, all 32 bits
mbed_official	146:f64d43ff0c18	1922	* can be used as data, supporting up to 32-bit frame operation. A read access
mbed_official	146:f64d43ff0c18	1923	* of PUSHR returns the topmost TX FIFO entry. When the module is disabled,
mbed_official	146:f64d43ff0c18	1924	* writing to this register does not update the FIFO. Therefore, any reads performed
mbed_official	146:f64d43ff0c18	1925	* while the module is disabled return the last PUSHR write performed while the
mbed_official	146:f64d43ff0c18	1926	* module was still enabled.
mbed_official	146:f64d43ff0c18	1927	*/
mbed_official	146:f64d43ff0c18	1928	typedef union _hw_spi_pushr
mbed_official	146:f64d43ff0c18	1929	{
mbed_official	146:f64d43ff0c18	1930	uint32_t U;
mbed_official	146:f64d43ff0c18	1931	struct _hw_spi_pushr_bitfields
mbed_official	146:f64d43ff0c18	1932	{
mbed_official	146:f64d43ff0c18	1933	uint32_t TXDATA : 16; //!< [15:0] Transmit Data
mbed_official	146:f64d43ff0c18	1934	uint32_t PCS : 6; //!< [21:16]
mbed_official	146:f64d43ff0c18	1935	uint32_t RESERVED0 : 4; //!< [25:22]
mbed_official	146:f64d43ff0c18	1936	uint32_t CTCNT : 1; //!< [26] Clear Transfer Counter
mbed_official	146:f64d43ff0c18	1937	uint32_t EOQ : 1; //!< [27] End Of Queue
mbed_official	146:f64d43ff0c18	1938	uint32_t CTAS : 3; //!< [30:28] Clock and Transfer Attributes Select
mbed_official	146:f64d43ff0c18	1939	uint32_t CONT : 1; //!< [31] Continuous Peripheral Chip Select Enable
mbed_official	146:f64d43ff0c18	1940	} B;
mbed_official	146:f64d43ff0c18	1941	} hw_spi_pushr_t;
mbed_official	146:f64d43ff0c18	1942	#endif
mbed_official	146:f64d43ff0c18	1943
mbed_official	146:f64d43ff0c18	1944	/*!
mbed_official	146:f64d43ff0c18	1945	* @name Constants and macros for entire SPI_PUSHR register
mbed_official	146:f64d43ff0c18	1946	*/
mbed_official	146:f64d43ff0c18	1947	//@{
mbed_official	146:f64d43ff0c18	1948	#define HW_SPI_PUSHR_ADDR(x) (REGS_SPI_BASE(x) + 0x34U)
mbed_official	146:f64d43ff0c18	1949
mbed_official	146:f64d43ff0c18	1950	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1951	#define HW_SPI_PUSHR(x) ((__IO hw_spi_pushr_t ) HW_SPI_PUSHR_ADDR(x))
mbed_official	146:f64d43ff0c18	1952	#define HW_SPI_PUSHR_RD(x) (HW_SPI_PUSHR(x).U)
mbed_official	146:f64d43ff0c18	1953	#define HW_SPI_PUSHR_WR(x, v) (HW_SPI_PUSHR(x).U = (v))
mbed_official	146:f64d43ff0c18	1954	#define HW_SPI_PUSHR_SET(x, v) (HW_SPI_PUSHR_WR(x, HW_SPI_PUSHR_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	1955	#define HW_SPI_PUSHR_CLR(x, v) (HW_SPI_PUSHR_WR(x, HW_SPI_PUSHR_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	1956	#define HW_SPI_PUSHR_TOG(x, v) (HW_SPI_PUSHR_WR(x, HW_SPI_PUSHR_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	1957	#endif
mbed_official	146:f64d43ff0c18	1958	//@}
mbed_official	146:f64d43ff0c18	1959
mbed_official	146:f64d43ff0c18	1960	/*
mbed_official	146:f64d43ff0c18	1961	* Constants & macros for individual SPI_PUSHR bitfields
mbed_official	146:f64d43ff0c18	1962	*/
mbed_official	146:f64d43ff0c18	1963
mbed_official	146:f64d43ff0c18	1964	/*!
mbed_official	146:f64d43ff0c18	1965	* @name Register SPI_PUSHR, field TXDATA[15:0] (RW)
mbed_official	146:f64d43ff0c18	1966	*
mbed_official	146:f64d43ff0c18	1967	* Holds SPI data to be transferred according to the associated SPI command.
mbed_official	146:f64d43ff0c18	1968	*/
mbed_official	146:f64d43ff0c18	1969	//@{
mbed_official	146:f64d43ff0c18	1970	#define BP_SPI_PUSHR_TXDATA (0U) //!< Bit position for SPI_PUSHR_TXDATA.
mbed_official	146:f64d43ff0c18	1971	#define BM_SPI_PUSHR_TXDATA (0x0000FFFFU) //!< Bit mask for SPI_PUSHR_TXDATA.
mbed_official	146:f64d43ff0c18	1972	#define BS_SPI_PUSHR_TXDATA (16U) //!< Bit field size in bits for SPI_PUSHR_TXDATA.
mbed_official	146:f64d43ff0c18	1973
mbed_official	146:f64d43ff0c18	1974	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1975	//! @brief Read current value of the SPI_PUSHR_TXDATA field.
mbed_official	146:f64d43ff0c18	1976	#define BR_SPI_PUSHR_TXDATA(x) (HW_SPI_PUSHR(x).B.TXDATA)
mbed_official	146:f64d43ff0c18	1977	#endif
mbed_official	146:f64d43ff0c18	1978
mbed_official	146:f64d43ff0c18	1979	//! @brief Format value for bitfield SPI_PUSHR_TXDATA.
mbed_official	146:f64d43ff0c18	1980	#define BF_SPI_PUSHR_TXDATA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_PUSHR_TXDATA), uint32_t) & BM_SPI_PUSHR_TXDATA)
mbed_official	146:f64d43ff0c18	1981
mbed_official	146:f64d43ff0c18	1982	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1983	//! @brief Set the TXDATA field to a new value.
mbed_official	146:f64d43ff0c18	1984	#define BW_SPI_PUSHR_TXDATA(x, v) (HW_SPI_PUSHR_WR(x, (HW_SPI_PUSHR_RD(x) & ~BM_SPI_PUSHR_TXDATA) \| BF_SPI_PUSHR_TXDATA(v)))
mbed_official	146:f64d43ff0c18	1985	#endif
mbed_official	146:f64d43ff0c18	1986	//@}
mbed_official	146:f64d43ff0c18	1987
mbed_official	146:f64d43ff0c18	1988	/*!
mbed_official	146:f64d43ff0c18	1989	* @name Register SPI_PUSHR, field PCS[21:16] (RW)
mbed_official	146:f64d43ff0c18	1990	*
mbed_official	146:f64d43ff0c18	1991	* Select which PCS signals are to be asserted for the transfer. Refer to the
mbed_official	146:f64d43ff0c18	1992	* chip configuration details for the number of PCS signals used in this MCU.
mbed_official	146:f64d43ff0c18	1993	*
mbed_official	146:f64d43ff0c18	1994	* Values:
mbed_official	146:f64d43ff0c18	1995	* - 0 - Negate the PCS[x] signal.
mbed_official	146:f64d43ff0c18	1996	* - 1 - Assert the PCS[x] signal.
mbed_official	146:f64d43ff0c18	1997	*/
mbed_official	146:f64d43ff0c18	1998	//@{
mbed_official	146:f64d43ff0c18	1999	#define BP_SPI_PUSHR_PCS (16U) //!< Bit position for SPI_PUSHR_PCS.
mbed_official	146:f64d43ff0c18	2000	#define BM_SPI_PUSHR_PCS (0x003F0000U) //!< Bit mask for SPI_PUSHR_PCS.
mbed_official	146:f64d43ff0c18	2001	#define BS_SPI_PUSHR_PCS (6U) //!< Bit field size in bits for SPI_PUSHR_PCS.
mbed_official	146:f64d43ff0c18	2002
mbed_official	146:f64d43ff0c18	2003	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2004	//! @brief Read current value of the SPI_PUSHR_PCS field.
mbed_official	146:f64d43ff0c18	2005	#define BR_SPI_PUSHR_PCS(x) (HW_SPI_PUSHR(x).B.PCS)
mbed_official	146:f64d43ff0c18	2006	#endif
mbed_official	146:f64d43ff0c18	2007
mbed_official	146:f64d43ff0c18	2008	//! @brief Format value for bitfield SPI_PUSHR_PCS.
mbed_official	146:f64d43ff0c18	2009	#define BF_SPI_PUSHR_PCS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_PUSHR_PCS), uint32_t) & BM_SPI_PUSHR_PCS)
mbed_official	146:f64d43ff0c18	2010
mbed_official	146:f64d43ff0c18	2011	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2012	//! @brief Set the PCS field to a new value.
mbed_official	146:f64d43ff0c18	2013	#define BW_SPI_PUSHR_PCS(x, v) (HW_SPI_PUSHR_WR(x, (HW_SPI_PUSHR_RD(x) & ~BM_SPI_PUSHR_PCS) \| BF_SPI_PUSHR_PCS(v)))
mbed_official	146:f64d43ff0c18	2014	#endif
mbed_official	146:f64d43ff0c18	2015	//@}
mbed_official	146:f64d43ff0c18	2016
mbed_official	146:f64d43ff0c18	2017	/*!
mbed_official	146:f64d43ff0c18	2018	* @name Register SPI_PUSHR, field CTCNT[26] (RW)
mbed_official	146:f64d43ff0c18	2019	*
mbed_official	146:f64d43ff0c18	2020	* Clears the TCNT field in the TCR register. The TCNT field is cleared before
mbed_official	146:f64d43ff0c18	2021	* the module starts transmitting the current SPI frame.
mbed_official	146:f64d43ff0c18	2022	*
mbed_official	146:f64d43ff0c18	2023	* Values:
mbed_official	146:f64d43ff0c18	2024	* - 0 - Do not clear the TCR[TCNT] field.
mbed_official	146:f64d43ff0c18	2025	* - 1 - Clear the TCR[TCNT] field.
mbed_official	146:f64d43ff0c18	2026	*/
mbed_official	146:f64d43ff0c18	2027	//@{
mbed_official	146:f64d43ff0c18	2028	#define BP_SPI_PUSHR_CTCNT (26U) //!< Bit position for SPI_PUSHR_CTCNT.
mbed_official	146:f64d43ff0c18	2029	#define BM_SPI_PUSHR_CTCNT (0x04000000U) //!< Bit mask for SPI_PUSHR_CTCNT.
mbed_official	146:f64d43ff0c18	2030	#define BS_SPI_PUSHR_CTCNT (1U) //!< Bit field size in bits for SPI_PUSHR_CTCNT.
mbed_official	146:f64d43ff0c18	2031
mbed_official	146:f64d43ff0c18	2032	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2033	//! @brief Read current value of the SPI_PUSHR_CTCNT field.
mbed_official	146:f64d43ff0c18	2034	#define BR_SPI_PUSHR_CTCNT(x) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CTCNT))
mbed_official	146:f64d43ff0c18	2035	#endif
mbed_official	146:f64d43ff0c18	2036
mbed_official	146:f64d43ff0c18	2037	//! @brief Format value for bitfield SPI_PUSHR_CTCNT.
mbed_official	146:f64d43ff0c18	2038	#define BF_SPI_PUSHR_CTCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_PUSHR_CTCNT), uint32_t) & BM_SPI_PUSHR_CTCNT)
mbed_official	146:f64d43ff0c18	2039
mbed_official	146:f64d43ff0c18	2040	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2041	//! @brief Set the CTCNT field to a new value.
mbed_official	146:f64d43ff0c18	2042	#define BW_SPI_PUSHR_CTCNT(x, v) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CTCNT) = (v))
mbed_official	146:f64d43ff0c18	2043	#endif
mbed_official	146:f64d43ff0c18	2044	//@}
mbed_official	146:f64d43ff0c18	2045
mbed_official	146:f64d43ff0c18	2046	/*!
mbed_official	146:f64d43ff0c18	2047	* @name Register SPI_PUSHR, field EOQ[27] (RW)
mbed_official	146:f64d43ff0c18	2048	*
mbed_official	146:f64d43ff0c18	2049	* Host software uses this bit to signal to the module that the current SPI
mbed_official	146:f64d43ff0c18	2050	* transfer is the last in a queue. At the end of the transfer, the EOQF bit in the
mbed_official	146:f64d43ff0c18	2051	* SR is set.
mbed_official	146:f64d43ff0c18	2052	*
mbed_official	146:f64d43ff0c18	2053	* Values:
mbed_official	146:f64d43ff0c18	2054	* - 0 - The SPI data is not the last data to transfer.
mbed_official	146:f64d43ff0c18	2055	* - 1 - The SPI data is the last data to transfer.
mbed_official	146:f64d43ff0c18	2056	*/
mbed_official	146:f64d43ff0c18	2057	//@{
mbed_official	146:f64d43ff0c18	2058	#define BP_SPI_PUSHR_EOQ (27U) //!< Bit position for SPI_PUSHR_EOQ.
mbed_official	146:f64d43ff0c18	2059	#define BM_SPI_PUSHR_EOQ (0x08000000U) //!< Bit mask for SPI_PUSHR_EOQ.
mbed_official	146:f64d43ff0c18	2060	#define BS_SPI_PUSHR_EOQ (1U) //!< Bit field size in bits for SPI_PUSHR_EOQ.
mbed_official	146:f64d43ff0c18	2061
mbed_official	146:f64d43ff0c18	2062	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2063	//! @brief Read current value of the SPI_PUSHR_EOQ field.
mbed_official	146:f64d43ff0c18	2064	#define BR_SPI_PUSHR_EOQ(x) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_EOQ))
mbed_official	146:f64d43ff0c18	2065	#endif
mbed_official	146:f64d43ff0c18	2066
mbed_official	146:f64d43ff0c18	2067	//! @brief Format value for bitfield SPI_PUSHR_EOQ.
mbed_official	146:f64d43ff0c18	2068	#define BF_SPI_PUSHR_EOQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_PUSHR_EOQ), uint32_t) & BM_SPI_PUSHR_EOQ)
mbed_official	146:f64d43ff0c18	2069
mbed_official	146:f64d43ff0c18	2070	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2071	//! @brief Set the EOQ field to a new value.
mbed_official	146:f64d43ff0c18	2072	#define BW_SPI_PUSHR_EOQ(x, v) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_EOQ) = (v))
mbed_official	146:f64d43ff0c18	2073	#endif
mbed_official	146:f64d43ff0c18	2074	//@}
mbed_official	146:f64d43ff0c18	2075
mbed_official	146:f64d43ff0c18	2076	/*!
mbed_official	146:f64d43ff0c18	2077	* @name Register SPI_PUSHR, field CTAS[30:28] (RW)
mbed_official	146:f64d43ff0c18	2078	*
mbed_official	146:f64d43ff0c18	2079	* Selects which CTAR to use in master mode to specify the transfer attributes
mbed_official	146:f64d43ff0c18	2080	* for the associated SPI frame. In SPI Slave mode, CTAR0 is used. See the chip
mbed_official	146:f64d43ff0c18	2081	* configuration details to determine how many CTARs this device has. You should
mbed_official	146:f64d43ff0c18	2082	* not program a value in this field for a register that is not present.
mbed_official	146:f64d43ff0c18	2083	*
mbed_official	146:f64d43ff0c18	2084	* Values:
mbed_official	146:f64d43ff0c18	2085	* - 000 - CTAR0
mbed_official	146:f64d43ff0c18	2086	* - 001 - CTAR1
mbed_official	146:f64d43ff0c18	2087	* - 010 - Reserved
mbed_official	146:f64d43ff0c18	2088	* - 011 - Reserved
mbed_official	146:f64d43ff0c18	2089	* - 100 - Reserved
mbed_official	146:f64d43ff0c18	2090	* - 101 - Reserved
mbed_official	146:f64d43ff0c18	2091	* - 110 - Reserved
mbed_official	146:f64d43ff0c18	2092	* - 111 - Reserved
mbed_official	146:f64d43ff0c18	2093	*/
mbed_official	146:f64d43ff0c18	2094	//@{
mbed_official	146:f64d43ff0c18	2095	#define BP_SPI_PUSHR_CTAS (28U) //!< Bit position for SPI_PUSHR_CTAS.
mbed_official	146:f64d43ff0c18	2096	#define BM_SPI_PUSHR_CTAS (0x70000000U) //!< Bit mask for SPI_PUSHR_CTAS.
mbed_official	146:f64d43ff0c18	2097	#define BS_SPI_PUSHR_CTAS (3U) //!< Bit field size in bits for SPI_PUSHR_CTAS.
mbed_official	146:f64d43ff0c18	2098
mbed_official	146:f64d43ff0c18	2099	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2100	//! @brief Read current value of the SPI_PUSHR_CTAS field.
mbed_official	146:f64d43ff0c18	2101	#define BR_SPI_PUSHR_CTAS(x) (HW_SPI_PUSHR(x).B.CTAS)
mbed_official	146:f64d43ff0c18	2102	#endif
mbed_official	146:f64d43ff0c18	2103
mbed_official	146:f64d43ff0c18	2104	//! @brief Format value for bitfield SPI_PUSHR_CTAS.
mbed_official	146:f64d43ff0c18	2105	#define BF_SPI_PUSHR_CTAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_PUSHR_CTAS), uint32_t) & BM_SPI_PUSHR_CTAS)
mbed_official	146:f64d43ff0c18	2106
mbed_official	146:f64d43ff0c18	2107	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2108	//! @brief Set the CTAS field to a new value.
mbed_official	146:f64d43ff0c18	2109	#define BW_SPI_PUSHR_CTAS(x, v) (HW_SPI_PUSHR_WR(x, (HW_SPI_PUSHR_RD(x) & ~BM_SPI_PUSHR_CTAS) \| BF_SPI_PUSHR_CTAS(v)))
mbed_official	146:f64d43ff0c18	2110	#endif
mbed_official	146:f64d43ff0c18	2111	//@}
mbed_official	146:f64d43ff0c18	2112
mbed_official	146:f64d43ff0c18	2113	/*!
mbed_official	146:f64d43ff0c18	2114	* @name Register SPI_PUSHR, field CONT[31] (RW)
mbed_official	146:f64d43ff0c18	2115	*
mbed_official	146:f64d43ff0c18	2116	* Selects a continuous selection format. The bit is used in SPI Master mode.
mbed_official	146:f64d43ff0c18	2117	* The bit enables the selected PCS signals to remain asserted between transfers.
mbed_official	146:f64d43ff0c18	2118	*
mbed_official	146:f64d43ff0c18	2119	* Values:
mbed_official	146:f64d43ff0c18	2120	* - 0 - Return PCSn signals to their inactive state between transfers.
mbed_official	146:f64d43ff0c18	2121	* - 1 - Keep PCSn signals asserted between transfers.
mbed_official	146:f64d43ff0c18	2122	*/
mbed_official	146:f64d43ff0c18	2123	//@{
mbed_official	146:f64d43ff0c18	2124	#define BP_SPI_PUSHR_CONT (31U) //!< Bit position for SPI_PUSHR_CONT.
mbed_official	146:f64d43ff0c18	2125	#define BM_SPI_PUSHR_CONT (0x80000000U) //!< Bit mask for SPI_PUSHR_CONT.
mbed_official	146:f64d43ff0c18	2126	#define BS_SPI_PUSHR_CONT (1U) //!< Bit field size in bits for SPI_PUSHR_CONT.
mbed_official	146:f64d43ff0c18	2127
mbed_official	146:f64d43ff0c18	2128	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2129	//! @brief Read current value of the SPI_PUSHR_CONT field.
mbed_official	146:f64d43ff0c18	2130	#define BR_SPI_PUSHR_CONT(x) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CONT))
mbed_official	146:f64d43ff0c18	2131	#endif
mbed_official	146:f64d43ff0c18	2132
mbed_official	146:f64d43ff0c18	2133	//! @brief Format value for bitfield SPI_PUSHR_CONT.
mbed_official	146:f64d43ff0c18	2134	#define BF_SPI_PUSHR_CONT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_PUSHR_CONT), uint32_t) & BM_SPI_PUSHR_CONT)
mbed_official	146:f64d43ff0c18	2135
mbed_official	146:f64d43ff0c18	2136	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2137	//! @brief Set the CONT field to a new value.
mbed_official	146:f64d43ff0c18	2138	#define BW_SPI_PUSHR_CONT(x, v) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CONT) = (v))
mbed_official	146:f64d43ff0c18	2139	#endif
mbed_official	146:f64d43ff0c18	2140	//@}
mbed_official	146:f64d43ff0c18	2141	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	2142	// HW_SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode
mbed_official	146:f64d43ff0c18	2143	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	2144
mbed_official	146:f64d43ff0c18	2145	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2146	/*!
mbed_official	146:f64d43ff0c18	2147	* @brief HW_SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode (RW)
mbed_official	146:f64d43ff0c18	2148	*
mbed_official	146:f64d43ff0c18	2149	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	2150	*
mbed_official	146:f64d43ff0c18	2151	* Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access
mbed_official	146:f64d43ff0c18	2152	* to PUSHR transfers all 32 bits to the TX FIFO. In master mode, the register
mbed_official	146:f64d43ff0c18	2153	* transfers 16 bits of data and 16 bits of command information to the TX FIFO. In
mbed_official	146:f64d43ff0c18	2154	* slave mode, all 32 register bits can be used as data, supporting up to 32-bit
mbed_official	146:f64d43ff0c18	2155	* SPI Frame operation.
mbed_official	146:f64d43ff0c18	2156	*/
mbed_official	146:f64d43ff0c18	2157	typedef union _hw_spi_pushr_slave
mbed_official	146:f64d43ff0c18	2158	{
mbed_official	146:f64d43ff0c18	2159	uint32_t U;
mbed_official	146:f64d43ff0c18	2160	struct _hw_spi_pushr_slave_bitfields
mbed_official	146:f64d43ff0c18	2161	{
mbed_official	146:f64d43ff0c18	2162	uint32_t TXDATA : 32; //!< [31:0] Transmit Data
mbed_official	146:f64d43ff0c18	2163	} B;
mbed_official	146:f64d43ff0c18	2164	} hw_spi_pushr_slave_t;
mbed_official	146:f64d43ff0c18	2165	#endif
mbed_official	146:f64d43ff0c18	2166
mbed_official	146:f64d43ff0c18	2167	/*!
mbed_official	146:f64d43ff0c18	2168	* @name Constants and macros for entire SPI_PUSHR_SLAVE register
mbed_official	146:f64d43ff0c18	2169	*/
mbed_official	146:f64d43ff0c18	2170	//@{
mbed_official	146:f64d43ff0c18	2171	#define HW_SPI_PUSHR_SLAVE_ADDR(x) (REGS_SPI_BASE(x) + 0x34U)
mbed_official	146:f64d43ff0c18	2172
mbed_official	146:f64d43ff0c18	2173	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2174	#define HW_SPI_PUSHR_SLAVE(x) ((__IO hw_spi_pushr_slave_t ) HW_SPI_PUSHR_SLAVE_ADDR(x))
mbed_official	146:f64d43ff0c18	2175	#define HW_SPI_PUSHR_SLAVE_RD(x) (HW_SPI_PUSHR_SLAVE(x).U)
mbed_official	146:f64d43ff0c18	2176	#define HW_SPI_PUSHR_SLAVE_WR(x, v) (HW_SPI_PUSHR_SLAVE(x).U = (v))
mbed_official	146:f64d43ff0c18	2177	#define HW_SPI_PUSHR_SLAVE_SET(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, HW_SPI_PUSHR_SLAVE_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	2178	#define HW_SPI_PUSHR_SLAVE_CLR(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, HW_SPI_PUSHR_SLAVE_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	2179	#define HW_SPI_PUSHR_SLAVE_TOG(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, HW_SPI_PUSHR_SLAVE_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	2180	#endif
mbed_official	146:f64d43ff0c18	2181	//@}
mbed_official	146:f64d43ff0c18	2182
mbed_official	146:f64d43ff0c18	2183	/*
mbed_official	146:f64d43ff0c18	2184	* Constants & macros for individual SPI_PUSHR_SLAVE bitfields
mbed_official	146:f64d43ff0c18	2185	*/
mbed_official	146:f64d43ff0c18	2186
mbed_official	146:f64d43ff0c18	2187	/*!
mbed_official	146:f64d43ff0c18	2188	* @name Register SPI_PUSHR_SLAVE, field TXDATA[31:0] (RW)
mbed_official	146:f64d43ff0c18	2189	*
mbed_official	146:f64d43ff0c18	2190	* Holds SPI data to be transferred according to the associated SPI command.
mbed_official	146:f64d43ff0c18	2191	*/
mbed_official	146:f64d43ff0c18	2192	//@{
mbed_official	146:f64d43ff0c18	2193	#define BP_SPI_PUSHR_SLAVE_TXDATA (0U) //!< Bit position for SPI_PUSHR_SLAVE_TXDATA.
mbed_official	146:f64d43ff0c18	2194	#define BM_SPI_PUSHR_SLAVE_TXDATA (0xFFFFFFFFU) //!< Bit mask for SPI_PUSHR_SLAVE_TXDATA.
mbed_official	146:f64d43ff0c18	2195	#define BS_SPI_PUSHR_SLAVE_TXDATA (32U) //!< Bit field size in bits for SPI_PUSHR_SLAVE_TXDATA.
mbed_official	146:f64d43ff0c18	2196
mbed_official	146:f64d43ff0c18	2197	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2198	//! @brief Read current value of the SPI_PUSHR_SLAVE_TXDATA field.
mbed_official	146:f64d43ff0c18	2199	#define BR_SPI_PUSHR_SLAVE_TXDATA(x) (HW_SPI_PUSHR_SLAVE(x).U)
mbed_official	146:f64d43ff0c18	2200	#endif
mbed_official	146:f64d43ff0c18	2201
mbed_official	146:f64d43ff0c18	2202	//! @brief Format value for bitfield SPI_PUSHR_SLAVE_TXDATA.
mbed_official	146:f64d43ff0c18	2203	#define BF_SPI_PUSHR_SLAVE_TXDATA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_PUSHR_SLAVE_TXDATA), uint32_t) & BM_SPI_PUSHR_SLAVE_TXDATA)
mbed_official	146:f64d43ff0c18	2204
mbed_official	146:f64d43ff0c18	2205	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2206	//! @brief Set the TXDATA field to a new value.
mbed_official	146:f64d43ff0c18	2207	#define BW_SPI_PUSHR_SLAVE_TXDATA(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, v))
mbed_official	146:f64d43ff0c18	2208	#endif
mbed_official	146:f64d43ff0c18	2209	//@}
mbed_official	146:f64d43ff0c18	2210
mbed_official	146:f64d43ff0c18	2211	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	2212	// HW_SPI_POPR - POP RX FIFO Register
mbed_official	146:f64d43ff0c18	2213	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	2214
mbed_official	146:f64d43ff0c18	2215	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2216	/*!
mbed_official	146:f64d43ff0c18	2217	* @brief HW_SPI_POPR - POP RX FIFO Register (RO)
mbed_official	146:f64d43ff0c18	2218	*
mbed_official	146:f64d43ff0c18	2219	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	2220	*
mbed_official	146:f64d43ff0c18	2221	* POPR is used to read the RX FIFO. Eight- or sixteen-bit read accesses to the
mbed_official	146:f64d43ff0c18	2222	* POPR have the same effect on the RX FIFO as 32-bit read accesses. A write to
mbed_official	146:f64d43ff0c18	2223	* this register will generate a Transfer Error.
mbed_official	146:f64d43ff0c18	2224	*/
mbed_official	146:f64d43ff0c18	2225	typedef union _hw_spi_popr
mbed_official	146:f64d43ff0c18	2226	{
mbed_official	146:f64d43ff0c18	2227	uint32_t U;
mbed_official	146:f64d43ff0c18	2228	struct _hw_spi_popr_bitfields
mbed_official	146:f64d43ff0c18	2229	{
mbed_official	146:f64d43ff0c18	2230	uint32_t RXDATA : 32; //!< [31:0] Received Data
mbed_official	146:f64d43ff0c18	2231	} B;
mbed_official	146:f64d43ff0c18	2232	} hw_spi_popr_t;
mbed_official	146:f64d43ff0c18	2233	#endif
mbed_official	146:f64d43ff0c18	2234
mbed_official	146:f64d43ff0c18	2235	/*!
mbed_official	146:f64d43ff0c18	2236	* @name Constants and macros for entire SPI_POPR register
mbed_official	146:f64d43ff0c18	2237	*/
mbed_official	146:f64d43ff0c18	2238	//@{
mbed_official	146:f64d43ff0c18	2239	#define HW_SPI_POPR_ADDR(x) (REGS_SPI_BASE(x) + 0x38U)
mbed_official	146:f64d43ff0c18	2240
mbed_official	146:f64d43ff0c18	2241	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2242	#define HW_SPI_POPR(x) ((__I hw_spi_popr_t ) HW_SPI_POPR_ADDR(x))
mbed_official	146:f64d43ff0c18	2243	#define HW_SPI_POPR_RD(x) (HW_SPI_POPR(x).U)
mbed_official	146:f64d43ff0c18	2244	#endif
mbed_official	146:f64d43ff0c18	2245	//@}
mbed_official	146:f64d43ff0c18	2246
mbed_official	146:f64d43ff0c18	2247	/*
mbed_official	146:f64d43ff0c18	2248	* Constants & macros for individual SPI_POPR bitfields
mbed_official	146:f64d43ff0c18	2249	*/
mbed_official	146:f64d43ff0c18	2250
mbed_official	146:f64d43ff0c18	2251	/*!
mbed_official	146:f64d43ff0c18	2252	* @name Register SPI_POPR, field RXDATA[31:0] (RO)
mbed_official	146:f64d43ff0c18	2253	*
mbed_official	146:f64d43ff0c18	2254	* Contains the SPI data from the RX FIFO entry to which the Pop Next Data
mbed_official	146:f64d43ff0c18	2255	* Pointer points.
mbed_official	146:f64d43ff0c18	2256	*/
mbed_official	146:f64d43ff0c18	2257	//@{
mbed_official	146:f64d43ff0c18	2258	#define BP_SPI_POPR_RXDATA (0U) //!< Bit position for SPI_POPR_RXDATA.
mbed_official	146:f64d43ff0c18	2259	#define BM_SPI_POPR_RXDATA (0xFFFFFFFFU) //!< Bit mask for SPI_POPR_RXDATA.
mbed_official	146:f64d43ff0c18	2260	#define BS_SPI_POPR_RXDATA (32U) //!< Bit field size in bits for SPI_POPR_RXDATA.
mbed_official	146:f64d43ff0c18	2261
mbed_official	146:f64d43ff0c18	2262	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2263	//! @brief Read current value of the SPI_POPR_RXDATA field.
mbed_official	146:f64d43ff0c18	2264	#define BR_SPI_POPR_RXDATA(x) (HW_SPI_POPR(x).U)
mbed_official	146:f64d43ff0c18	2265	#endif
mbed_official	146:f64d43ff0c18	2266	//@}
mbed_official	146:f64d43ff0c18	2267
mbed_official	146:f64d43ff0c18	2268	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	2269	// HW_SPI_TXFRn - Transmit FIFO Registers
mbed_official	146:f64d43ff0c18	2270	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	2271
mbed_official	146:f64d43ff0c18	2272	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2273	/*!
mbed_official	146:f64d43ff0c18	2274	* @brief HW_SPI_TXFRn - Transmit FIFO Registers (RO)
mbed_official	146:f64d43ff0c18	2275	*
mbed_official	146:f64d43ff0c18	2276	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	2277	*
mbed_official	146:f64d43ff0c18	2278	* TXFRn registers provide visibility into the TX FIFO for debugging purposes.
mbed_official	146:f64d43ff0c18	2279	* Each register is an entry in the TX FIFO. The registers are read-only and
mbed_official	146:f64d43ff0c18	2280	* cannot be modified. Reading the TXFRx registers does not alter the state of the TX
mbed_official	146:f64d43ff0c18	2281	* FIFO.
mbed_official	146:f64d43ff0c18	2282	*/
mbed_official	146:f64d43ff0c18	2283	typedef union _hw_spi_txfrn
mbed_official	146:f64d43ff0c18	2284	{
mbed_official	146:f64d43ff0c18	2285	uint32_t U;
mbed_official	146:f64d43ff0c18	2286	struct _hw_spi_txfrn_bitfields
mbed_official	146:f64d43ff0c18	2287	{
mbed_official	146:f64d43ff0c18	2288	uint32_t TXDATA : 16; //!< [15:0] Transmit Data
mbed_official	146:f64d43ff0c18	2289	uint32_t TXCMD_TXDATA : 16; //!< [31:16] Transmit Command or Transmit
mbed_official	146:f64d43ff0c18	2290	//! Data
mbed_official	146:f64d43ff0c18	2291	} B;
mbed_official	146:f64d43ff0c18	2292	} hw_spi_txfrn_t;
mbed_official	146:f64d43ff0c18	2293	#endif
mbed_official	146:f64d43ff0c18	2294
mbed_official	146:f64d43ff0c18	2295	/*!
mbed_official	146:f64d43ff0c18	2296	* @name Constants and macros for entire SPI_TXFRn register
mbed_official	146:f64d43ff0c18	2297	*/
mbed_official	146:f64d43ff0c18	2298	//@{
mbed_official	146:f64d43ff0c18	2299	#define HW_SPI_TXFRn_COUNT (4U)
mbed_official	146:f64d43ff0c18	2300
mbed_official	146:f64d43ff0c18	2301	#define HW_SPI_TXFRn_ADDR(x, n) (REGS_SPI_BASE(x) + 0x3CU + (0x4U * n))
mbed_official	146:f64d43ff0c18	2302
mbed_official	146:f64d43ff0c18	2303	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2304	#define HW_SPI_TXFRn(x, n) ((__I hw_spi_txfrn_t ) HW_SPI_TXFRn_ADDR(x, n))
mbed_official	146:f64d43ff0c18	2305	#define HW_SPI_TXFRn_RD(x, n) (HW_SPI_TXFRn(x, n).U)
mbed_official	146:f64d43ff0c18	2306	#endif
mbed_official	146:f64d43ff0c18	2307	//@}
mbed_official	146:f64d43ff0c18	2308
mbed_official	146:f64d43ff0c18	2309	/*
mbed_official	146:f64d43ff0c18	2310	* Constants & macros for individual SPI_TXFRn bitfields
mbed_official	146:f64d43ff0c18	2311	*/
mbed_official	146:f64d43ff0c18	2312
mbed_official	146:f64d43ff0c18	2313	/*!
mbed_official	146:f64d43ff0c18	2314	* @name Register SPI_TXFRn, field TXDATA[15:0] (RO)
mbed_official	146:f64d43ff0c18	2315	*
mbed_official	146:f64d43ff0c18	2316	* Contains the SPI data to be shifted out.
mbed_official	146:f64d43ff0c18	2317	*/
mbed_official	146:f64d43ff0c18	2318	//@{
mbed_official	146:f64d43ff0c18	2319	#define BP_SPI_TXFRn_TXDATA (0U) //!< Bit position for SPI_TXFRn_TXDATA.
mbed_official	146:f64d43ff0c18	2320	#define BM_SPI_TXFRn_TXDATA (0x0000FFFFU) //!< Bit mask for SPI_TXFRn_TXDATA.
mbed_official	146:f64d43ff0c18	2321	#define BS_SPI_TXFRn_TXDATA (16U) //!< Bit field size in bits for SPI_TXFRn_TXDATA.
mbed_official	146:f64d43ff0c18	2322
mbed_official	146:f64d43ff0c18	2323	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2324	//! @brief Read current value of the SPI_TXFRn_TXDATA field.
mbed_official	146:f64d43ff0c18	2325	#define BR_SPI_TXFRn_TXDATA(x, n) (HW_SPI_TXFRn(x, n).B.TXDATA)
mbed_official	146:f64d43ff0c18	2326	#endif
mbed_official	146:f64d43ff0c18	2327	//@}
mbed_official	146:f64d43ff0c18	2328
mbed_official	146:f64d43ff0c18	2329	/*!
mbed_official	146:f64d43ff0c18	2330	* @name Register SPI_TXFRn, field TXCMD_TXDATA[31:16] (RO)
mbed_official	146:f64d43ff0c18	2331	*
mbed_official	146:f64d43ff0c18	2332	* In Master mode the TXCMD field contains the command that sets the transfer
mbed_official	146:f64d43ff0c18	2333	* attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
mbed_official	146:f64d43ff0c18	2334	* the SPI data to be shifted out.
mbed_official	146:f64d43ff0c18	2335	*/
mbed_official	146:f64d43ff0c18	2336	//@{
mbed_official	146:f64d43ff0c18	2337	#define BP_SPI_TXFRn_TXCMD_TXDATA (16U) //!< Bit position for SPI_TXFRn_TXCMD_TXDATA.
mbed_official	146:f64d43ff0c18	2338	#define BM_SPI_TXFRn_TXCMD_TXDATA (0xFFFF0000U) //!< Bit mask for SPI_TXFRn_TXCMD_TXDATA.
mbed_official	146:f64d43ff0c18	2339	#define BS_SPI_TXFRn_TXCMD_TXDATA (16U) //!< Bit field size in bits for SPI_TXFRn_TXCMD_TXDATA.
mbed_official	146:f64d43ff0c18	2340
mbed_official	146:f64d43ff0c18	2341	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2342	//! @brief Read current value of the SPI_TXFRn_TXCMD_TXDATA field.
mbed_official	146:f64d43ff0c18	2343	#define BR_SPI_TXFRn_TXCMD_TXDATA(x, n) (HW_SPI_TXFRn(x, n).B.TXCMD_TXDATA)
mbed_official	146:f64d43ff0c18	2344	#endif
mbed_official	146:f64d43ff0c18	2345	//@}
mbed_official	146:f64d43ff0c18	2346
mbed_official	146:f64d43ff0c18	2347	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	2348	// HW_SPI_RXFRn - Receive FIFO Registers
mbed_official	146:f64d43ff0c18	2349	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	2350
mbed_official	146:f64d43ff0c18	2351	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2352	/*!
mbed_official	146:f64d43ff0c18	2353	* @brief HW_SPI_RXFRn - Receive FIFO Registers (RO)
mbed_official	146:f64d43ff0c18	2354	*
mbed_official	146:f64d43ff0c18	2355	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	2356	*
mbed_official	146:f64d43ff0c18	2357	* RXFRn provide visibility into the RX FIFO for debugging purposes. Each
mbed_official	146:f64d43ff0c18	2358	* register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
mbed_official	146:f64d43ff0c18	2359	* RXFRx registers does not alter the state of the RX FIFO.
mbed_official	146:f64d43ff0c18	2360	*/
mbed_official	146:f64d43ff0c18	2361	typedef union _hw_spi_rxfrn
mbed_official	146:f64d43ff0c18	2362	{
mbed_official	146:f64d43ff0c18	2363	uint32_t U;
mbed_official	146:f64d43ff0c18	2364	struct _hw_spi_rxfrn_bitfields
mbed_official	146:f64d43ff0c18	2365	{
mbed_official	146:f64d43ff0c18	2366	uint32_t RXDATA : 32; //!< [31:0] Receive Data
mbed_official	146:f64d43ff0c18	2367	} B;
mbed_official	146:f64d43ff0c18	2368	} hw_spi_rxfrn_t;
mbed_official	146:f64d43ff0c18	2369	#endif
mbed_official	146:f64d43ff0c18	2370
mbed_official	146:f64d43ff0c18	2371	/*!
mbed_official	146:f64d43ff0c18	2372	* @name Constants and macros for entire SPI_RXFRn register
mbed_official	146:f64d43ff0c18	2373	*/
mbed_official	146:f64d43ff0c18	2374	//@{
mbed_official	146:f64d43ff0c18	2375	#define HW_SPI_RXFRn_COUNT (4U)
mbed_official	146:f64d43ff0c18	2376
mbed_official	146:f64d43ff0c18	2377	#define HW_SPI_RXFRn_ADDR(x, n) (REGS_SPI_BASE(x) + 0x7CU + (0x4U * n))
mbed_official	146:f64d43ff0c18	2378
mbed_official	146:f64d43ff0c18	2379	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2380	#define HW_SPI_RXFRn(x, n) ((__I hw_spi_rxfrn_t ) HW_SPI_RXFRn_ADDR(x, n))
mbed_official	146:f64d43ff0c18	2381	#define HW_SPI_RXFRn_RD(x, n) (HW_SPI_RXFRn(x, n).U)
mbed_official	146:f64d43ff0c18	2382	#endif
mbed_official	146:f64d43ff0c18	2383	//@}
mbed_official	146:f64d43ff0c18	2384
mbed_official	146:f64d43ff0c18	2385	/*
mbed_official	146:f64d43ff0c18	2386	* Constants & macros for individual SPI_RXFRn bitfields
mbed_official	146:f64d43ff0c18	2387	*/
mbed_official	146:f64d43ff0c18	2388
mbed_official	146:f64d43ff0c18	2389	/*!
mbed_official	146:f64d43ff0c18	2390	* @name Register SPI_RXFRn, field RXDATA[31:0] (RO)
mbed_official	146:f64d43ff0c18	2391	*
mbed_official	146:f64d43ff0c18	2392	* Contains the received SPI data.
mbed_official	146:f64d43ff0c18	2393	*/
mbed_official	146:f64d43ff0c18	2394	//@{
mbed_official	146:f64d43ff0c18	2395	#define BP_SPI_RXFRn_RXDATA (0U) //!< Bit position for SPI_RXFRn_RXDATA.
mbed_official	146:f64d43ff0c18	2396	#define BM_SPI_RXFRn_RXDATA (0xFFFFFFFFU) //!< Bit mask for SPI_RXFRn_RXDATA.
mbed_official	146:f64d43ff0c18	2397	#define BS_SPI_RXFRn_RXDATA (32U) //!< Bit field size in bits for SPI_RXFRn_RXDATA.
mbed_official	146:f64d43ff0c18	2398
mbed_official	146:f64d43ff0c18	2399	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2400	//! @brief Read current value of the SPI_RXFRn_RXDATA field.
mbed_official	146:f64d43ff0c18	2401	#define BR_SPI_RXFRn_RXDATA(x, n) (HW_SPI_RXFRn(x, n).U)
mbed_official	146:f64d43ff0c18	2402	#endif
mbed_official	146:f64d43ff0c18	2403	//@}
mbed_official	146:f64d43ff0c18	2404
mbed_official	146:f64d43ff0c18	2405	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	2406	// hw_spi_t - module struct
mbed_official	146:f64d43ff0c18	2407	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	2408	/*!
mbed_official	146:f64d43ff0c18	2409	* @brief All SPI module registers.
mbed_official	146:f64d43ff0c18	2410	*/
mbed_official	146:f64d43ff0c18	2411	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2412	#pragma pack(1)
mbed_official	146:f64d43ff0c18	2413	typedef struct _hw_spi
mbed_official	146:f64d43ff0c18	2414	{
mbed_official	146:f64d43ff0c18	2415	__IO hw_spi_mcr_t MCR; //!< [0x0] Module Configuration Register
mbed_official	146:f64d43ff0c18	2416	uint8_t _reserved0[4];
mbed_official	146:f64d43ff0c18	2417	__IO hw_spi_tcr_t TCR; //!< [0x8] Transfer Count Register
mbed_official	146:f64d43ff0c18	2418	union {
mbed_official	146:f64d43ff0c18	2419	__IO hw_spi_ctarn_t CTARn[2]; //!< [0xC] Clock and Transfer Attributes Register (In Master Mode)
mbed_official	146:f64d43ff0c18	2420	__IO hw_spi_ctarn_slave_t CTARn_SLAVE[1]; //!< [0xC] Clock and Transfer Attributes Register (In Slave Mode)
mbed_official	146:f64d43ff0c18	2421	};
mbed_official	146:f64d43ff0c18	2422	uint8_t _reserved1[24];
mbed_official	146:f64d43ff0c18	2423	__IO hw_spi_sr_t SR; //!< [0x2C] Status Register
mbed_official	146:f64d43ff0c18	2424	__IO hw_spi_rser_t RSER; //!< [0x30] DMA/Interrupt Request Select and Enable Register
mbed_official	146:f64d43ff0c18	2425	union {
mbed_official	146:f64d43ff0c18	2426	__IO hw_spi_pushr_t PUSHR; //!< [0x34] PUSH TX FIFO Register In Master Mode
mbed_official	146:f64d43ff0c18	2427	__IO hw_spi_pushr_slave_t PUSHR_SLAVE; //!< [0x34] PUSH TX FIFO Register In Slave Mode
mbed_official	146:f64d43ff0c18	2428	};
mbed_official	146:f64d43ff0c18	2429	__I hw_spi_popr_t POPR; //!< [0x38] POP RX FIFO Register
mbed_official	146:f64d43ff0c18	2430	__I hw_spi_txfrn_t TXFRn[4]; //!< [0x3C] Transmit FIFO Registers
mbed_official	146:f64d43ff0c18	2431	uint8_t _reserved2[48];
mbed_official	146:f64d43ff0c18	2432	__I hw_spi_rxfrn_t RXFRn[4]; //!< [0x7C] Receive FIFO Registers
mbed_official	146:f64d43ff0c18	2433	} hw_spi_t;
mbed_official	146:f64d43ff0c18	2434	#pragma pack()
mbed_official	146:f64d43ff0c18	2435
mbed_official	146:f64d43ff0c18	2436	//! @brief Macro to access all SPI registers.
mbed_official	146:f64d43ff0c18	2437	//! @param x SPI instance number.
mbed_official	146:f64d43ff0c18	2438	//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official	146:f64d43ff0c18	2439	//! use the '&' operator, like <code>&HW_SPI(0)</code>.
mbed_official	146:f64d43ff0c18	2440	#define HW_SPI(x) ((hw_spi_t ) REGS_SPI_BASE(x))
mbed_official	146:f64d43ff0c18	2441	#endif
mbed_official	146:f64d43ff0c18	2442
mbed_official	146:f64d43ff0c18	2443	#endif // __HW_SPI_REGISTERS_H__
mbed_official	146:f64d43ff0c18	2444	// v22/130726/0.9
mbed_official	146:f64d43ff0c18	2445	// EOF