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Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_sim.h@149:1fb5f62b92bd, 2014-04-03 (annotated)

Committer:
mbed_official
Date:
Thu Apr 03 11:45:06 2014 +0100
Revision:
149:1fb5f62b92bd
Parent:
targets/hal/TARGET_Freescale/TARGET_KSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_sim.h@146:f64d43ff0c18 
Synchronized with git revision 220c0bb39ceee40016e1e86350c058963d01ed42



Full URL: https://github.com/mbedmicro/mbed/commit/220c0bb39ceee40016e1e86350c058963d01ed42/

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /*
mbed_official 146:f64d43ff0c18 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
mbed_official 146:f64d43ff0c18 3 * All rights reserved.
mbed_official 146:f64d43ff0c18 4 *
mbed_official 146:f64d43ff0c18 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official 146:f64d43ff0c18 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official 146:f64d43ff0c18 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
mbed_official 146:f64d43ff0c18 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
mbed_official 146:f64d43ff0c18 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
mbed_official 146:f64d43ff0c18 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 146:f64d43ff0c18 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 146:f64d43ff0c18 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
mbed_official 146:f64d43ff0c18 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
mbed_official 146:f64d43ff0c18 14 * OF SUCH DAMAGE.
mbed_official 146:f64d43ff0c18 15 */
mbed_official 146:f64d43ff0c18 16 /*
mbed_official 146:f64d43ff0c18 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 146:f64d43ff0c18 18 *
mbed_official 146:f64d43ff0c18 19 * This file was generated automatically and any changes may be lost.
mbed_official 146:f64d43ff0c18 20 */
mbed_official 146:f64d43ff0c18 21 #ifndef __HW_SIM_REGISTERS_H__
mbed_official 146:f64d43ff0c18 22 #define __HW_SIM_REGISTERS_H__
mbed_official 146:f64d43ff0c18 23
mbed_official 146:f64d43ff0c18 24 #include "regs.h"
mbed_official 146:f64d43ff0c18 25
mbed_official 146:f64d43ff0c18 26 /*
mbed_official 146:f64d43ff0c18 27 * MK64F12 SIM
mbed_official 146:f64d43ff0c18 28 *
mbed_official 146:f64d43ff0c18 29 * System Integration Module
mbed_official 146:f64d43ff0c18 30 *
mbed_official 146:f64d43ff0c18 31 * Registers defined in this header file:
mbed_official 146:f64d43ff0c18 32 * - HW_SIM_SOPT1 - System Options Register 1
mbed_official 146:f64d43ff0c18 33 * - HW_SIM_SOPT1CFG - SOPT1 Configuration Register
mbed_official 146:f64d43ff0c18 34 * - HW_SIM_SOPT2 - System Options Register 2
mbed_official 146:f64d43ff0c18 35 * - HW_SIM_SOPT4 - System Options Register 4
mbed_official 146:f64d43ff0c18 36 * - HW_SIM_SOPT5 - System Options Register 5
mbed_official 146:f64d43ff0c18 37 * - HW_SIM_SOPT7 - System Options Register 7
mbed_official 146:f64d43ff0c18 38 * - HW_SIM_SDID - System Device Identification Register
mbed_official 146:f64d43ff0c18 39 * - HW_SIM_SCGC1 - System Clock Gating Control Register 1
mbed_official 146:f64d43ff0c18 40 * - HW_SIM_SCGC2 - System Clock Gating Control Register 2
mbed_official 146:f64d43ff0c18 41 * - HW_SIM_SCGC3 - System Clock Gating Control Register 3
mbed_official 146:f64d43ff0c18 42 * - HW_SIM_SCGC4 - System Clock Gating Control Register 4
mbed_official 146:f64d43ff0c18 43 * - HW_SIM_SCGC5 - System Clock Gating Control Register 5
mbed_official 146:f64d43ff0c18 44 * - HW_SIM_SCGC6 - System Clock Gating Control Register 6
mbed_official 146:f64d43ff0c18 45 * - HW_SIM_SCGC7 - System Clock Gating Control Register 7
mbed_official 146:f64d43ff0c18 46 * - HW_SIM_CLKDIV1 - System Clock Divider Register 1
mbed_official 146:f64d43ff0c18 47 * - HW_SIM_CLKDIV2 - System Clock Divider Register 2
mbed_official 146:f64d43ff0c18 48 * - HW_SIM_FCFG1 - Flash Configuration Register 1
mbed_official 146:f64d43ff0c18 49 * - HW_SIM_FCFG2 - Flash Configuration Register 2
mbed_official 146:f64d43ff0c18 50 * - HW_SIM_UIDH - Unique Identification Register High
mbed_official 146:f64d43ff0c18 51 * - HW_SIM_UIDMH - Unique Identification Register Mid-High
mbed_official 146:f64d43ff0c18 52 * - HW_SIM_UIDML - Unique Identification Register Mid Low
mbed_official 146:f64d43ff0c18 53 * - HW_SIM_UIDL - Unique Identification Register Low
mbed_official 146:f64d43ff0c18 54 *
mbed_official 146:f64d43ff0c18 55 * - hw_sim_t - Struct containing all module registers.
mbed_official 146:f64d43ff0c18 56 */
mbed_official 146:f64d43ff0c18 57
mbed_official 146:f64d43ff0c18 58 //! @name Module base addresses
mbed_official 146:f64d43ff0c18 59 //@{
mbed_official 146:f64d43ff0c18 60 #ifndef REGS_SIM_BASE
mbed_official 146:f64d43ff0c18 61 #define HW_SIM_INSTANCE_COUNT (1U) //!< Number of instances of the SIM module.
mbed_official 146:f64d43ff0c18 62 #define REGS_SIM_BASE (0x40047000U) //!< Base address for SIM.
mbed_official 146:f64d43ff0c18 63 #endif
mbed_official 146:f64d43ff0c18 64 //@}
mbed_official 146:f64d43ff0c18 65
mbed_official 146:f64d43ff0c18 66 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 67 // HW_SIM_SOPT1 - System Options Register 1
mbed_official 146:f64d43ff0c18 68 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 69
mbed_official 146:f64d43ff0c18 70 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 71 /*!
mbed_official 146:f64d43ff0c18 72 * @brief HW_SIM_SOPT1 - System Options Register 1 (RW)
mbed_official 146:f64d43ff0c18 73 *
mbed_official 146:f64d43ff0c18 74 * Reset value: 0x80000000U
mbed_official 146:f64d43ff0c18 75 *
mbed_official 146:f64d43ff0c18 76 * The SOPT1 register is only reset on POR or LVD.
mbed_official 146:f64d43ff0c18 77 */
mbed_official 146:f64d43ff0c18 78 typedef union _hw_sim_sopt1
mbed_official 146:f64d43ff0c18 79 {
mbed_official 146:f64d43ff0c18 80 uint32_t U;
mbed_official 146:f64d43ff0c18 81 struct _hw_sim_sopt1_bitfields
mbed_official 146:f64d43ff0c18 82 {
mbed_official 146:f64d43ff0c18 83 uint32_t RESERVED0 : 12; //!< [11:0]
mbed_official 146:f64d43ff0c18 84 uint32_t RAMSIZE : 4; //!< [15:12] RAM size
mbed_official 146:f64d43ff0c18 85 uint32_t RESERVED1 : 2; //!< [17:16]
mbed_official 146:f64d43ff0c18 86 uint32_t OSC32KSEL : 2; //!< [19:18] 32K oscillator clock select
mbed_official 146:f64d43ff0c18 87 uint32_t RESERVED2 : 9; //!< [28:20]
mbed_official 146:f64d43ff0c18 88 uint32_t USBVSTBY : 1; //!< [29] USB voltage regulator in standby
mbed_official 146:f64d43ff0c18 89 //! mode during VLPR and VLPW modes
mbed_official 146:f64d43ff0c18 90 uint32_t USBSSTBY : 1; //!< [30] USB voltage regulator in standby
mbed_official 146:f64d43ff0c18 91 //! mode during Stop, VLPS, LLS and VLLS modes.
mbed_official 146:f64d43ff0c18 92 uint32_t USBREGEN : 1; //!< [31] USB voltage regulator enable
mbed_official 146:f64d43ff0c18 93 } B;
mbed_official 146:f64d43ff0c18 94 } hw_sim_sopt1_t;
mbed_official 146:f64d43ff0c18 95 #endif
mbed_official 146:f64d43ff0c18 96
mbed_official 146:f64d43ff0c18 97 /*!
mbed_official 146:f64d43ff0c18 98 * @name Constants and macros for entire SIM_SOPT1 register
mbed_official 146:f64d43ff0c18 99 */
mbed_official 146:f64d43ff0c18 100 //@{
mbed_official 146:f64d43ff0c18 101 #define HW_SIM_SOPT1_ADDR (REGS_SIM_BASE + 0x0U)
mbed_official 146:f64d43ff0c18 102
mbed_official 146:f64d43ff0c18 103 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 104 #define HW_SIM_SOPT1 (*(__IO hw_sim_sopt1_t *) HW_SIM_SOPT1_ADDR)
mbed_official 146:f64d43ff0c18 105 #define HW_SIM_SOPT1_RD() (HW_SIM_SOPT1.U)
mbed_official 146:f64d43ff0c18 106 #define HW_SIM_SOPT1_WR(v) (HW_SIM_SOPT1.U = (v))
mbed_official 146:f64d43ff0c18 107 #define HW_SIM_SOPT1_SET(v) (HW_SIM_SOPT1_WR(HW_SIM_SOPT1_RD() | (v)))
mbed_official 146:f64d43ff0c18 108 #define HW_SIM_SOPT1_CLR(v) (HW_SIM_SOPT1_WR(HW_SIM_SOPT1_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 109 #define HW_SIM_SOPT1_TOG(v) (HW_SIM_SOPT1_WR(HW_SIM_SOPT1_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 110 #endif
mbed_official 146:f64d43ff0c18 111 //@}
mbed_official 146:f64d43ff0c18 112
mbed_official 146:f64d43ff0c18 113 /*
mbed_official 146:f64d43ff0c18 114 * Constants & macros for individual SIM_SOPT1 bitfields
mbed_official 146:f64d43ff0c18 115 */
mbed_official 146:f64d43ff0c18 116
mbed_official 146:f64d43ff0c18 117 /*!
mbed_official 146:f64d43ff0c18 118 * @name Register SIM_SOPT1, field RAMSIZE[15:12] (RO)
mbed_official 146:f64d43ff0c18 119 *
mbed_official 146:f64d43ff0c18 120 * This field specifies the amount of system RAM available on the device.
mbed_official 146:f64d43ff0c18 121 *
mbed_official 146:f64d43ff0c18 122 * Values:
mbed_official 146:f64d43ff0c18 123 * - 0001 - 8 KB
mbed_official 146:f64d43ff0c18 124 * - 0011 - 16 KB
mbed_official 146:f64d43ff0c18 125 * - 0100 - 24 KB
mbed_official 146:f64d43ff0c18 126 * - 0101 - 32 KB
mbed_official 146:f64d43ff0c18 127 * - 0110 - 48 KB
mbed_official 146:f64d43ff0c18 128 * - 0111 - 64 KB
mbed_official 146:f64d43ff0c18 129 * - 1000 - 96 KB
mbed_official 146:f64d43ff0c18 130 * - 1001 - 128 KB
mbed_official 146:f64d43ff0c18 131 * - 1011 - 256 KB
mbed_official 146:f64d43ff0c18 132 */
mbed_official 146:f64d43ff0c18 133 //@{
mbed_official 146:f64d43ff0c18 134 #define BP_SIM_SOPT1_RAMSIZE (12U) //!< Bit position for SIM_SOPT1_RAMSIZE.
mbed_official 146:f64d43ff0c18 135 #define BM_SIM_SOPT1_RAMSIZE (0x0000F000U) //!< Bit mask for SIM_SOPT1_RAMSIZE.
mbed_official 146:f64d43ff0c18 136 #define BS_SIM_SOPT1_RAMSIZE (4U) //!< Bit field size in bits for SIM_SOPT1_RAMSIZE.
mbed_official 146:f64d43ff0c18 137
mbed_official 146:f64d43ff0c18 138 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 139 //! @brief Read current value of the SIM_SOPT1_RAMSIZE field.
mbed_official 146:f64d43ff0c18 140 #define BR_SIM_SOPT1_RAMSIZE (HW_SIM_SOPT1.B.RAMSIZE)
mbed_official 146:f64d43ff0c18 141 #endif
mbed_official 146:f64d43ff0c18 142 //@}
mbed_official 146:f64d43ff0c18 143
mbed_official 146:f64d43ff0c18 144 /*!
mbed_official 146:f64d43ff0c18 145 * @name Register SIM_SOPT1, field OSC32KSEL[19:18] (RW)
mbed_official 146:f64d43ff0c18 146 *
mbed_official 146:f64d43ff0c18 147 * Selects the 32 kHz clock source (ERCLK32K) for LPTMR. This field is reset
mbed_official 146:f64d43ff0c18 148 * only on POR/LVD.
mbed_official 146:f64d43ff0c18 149 *
mbed_official 146:f64d43ff0c18 150 * Values:
mbed_official 146:f64d43ff0c18 151 * - 00 - System oscillator (OSC32KCLK)
mbed_official 146:f64d43ff0c18 152 * - 01 - Reserved
mbed_official 146:f64d43ff0c18 153 * - 10 - RTC 32.768kHz oscillator
mbed_official 146:f64d43ff0c18 154 * - 11 - LPO 1 kHz
mbed_official 146:f64d43ff0c18 155 */
mbed_official 146:f64d43ff0c18 156 //@{
mbed_official 146:f64d43ff0c18 157 #define BP_SIM_SOPT1_OSC32KSEL (18U) //!< Bit position for SIM_SOPT1_OSC32KSEL.
mbed_official 146:f64d43ff0c18 158 #define BM_SIM_SOPT1_OSC32KSEL (0x000C0000U) //!< Bit mask for SIM_SOPT1_OSC32KSEL.
mbed_official 146:f64d43ff0c18 159 #define BS_SIM_SOPT1_OSC32KSEL (2U) //!< Bit field size in bits for SIM_SOPT1_OSC32KSEL.
mbed_official 146:f64d43ff0c18 160
mbed_official 146:f64d43ff0c18 161 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 162 //! @brief Read current value of the SIM_SOPT1_OSC32KSEL field.
mbed_official 146:f64d43ff0c18 163 #define BR_SIM_SOPT1_OSC32KSEL (HW_SIM_SOPT1.B.OSC32KSEL)
mbed_official 146:f64d43ff0c18 164 #endif
mbed_official 146:f64d43ff0c18 165
mbed_official 146:f64d43ff0c18 166 //! @brief Format value for bitfield SIM_SOPT1_OSC32KSEL.
mbed_official 146:f64d43ff0c18 167 #define BF_SIM_SOPT1_OSC32KSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT1_OSC32KSEL), uint32_t) & BM_SIM_SOPT1_OSC32KSEL)
mbed_official 146:f64d43ff0c18 168
mbed_official 146:f64d43ff0c18 169 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 170 //! @brief Set the OSC32KSEL field to a new value.
mbed_official 146:f64d43ff0c18 171 #define BW_SIM_SOPT1_OSC32KSEL(v) (HW_SIM_SOPT1_WR((HW_SIM_SOPT1_RD() & ~BM_SIM_SOPT1_OSC32KSEL) | BF_SIM_SOPT1_OSC32KSEL(v)))
mbed_official 146:f64d43ff0c18 172 #endif
mbed_official 146:f64d43ff0c18 173 //@}
mbed_official 146:f64d43ff0c18 174
mbed_official 146:f64d43ff0c18 175 /*!
mbed_official 146:f64d43ff0c18 176 * @name Register SIM_SOPT1, field USBVSTBY[29] (RW)
mbed_official 146:f64d43ff0c18 177 *
mbed_official 146:f64d43ff0c18 178 * Controls whether the USB voltage regulator is placed in standby mode during
mbed_official 146:f64d43ff0c18 179 * VLPR and VLPW modes.
mbed_official 146:f64d43ff0c18 180 *
mbed_official 146:f64d43ff0c18 181 * Values:
mbed_official 146:f64d43ff0c18 182 * - 0 - USB voltage regulator not in standby during VLPR and VLPW modes.
mbed_official 146:f64d43ff0c18 183 * - 1 - USB voltage regulator in standby during VLPR and VLPW modes.
mbed_official 146:f64d43ff0c18 184 */
mbed_official 146:f64d43ff0c18 185 //@{
mbed_official 146:f64d43ff0c18 186 #define BP_SIM_SOPT1_USBVSTBY (29U) //!< Bit position for SIM_SOPT1_USBVSTBY.
mbed_official 146:f64d43ff0c18 187 #define BM_SIM_SOPT1_USBVSTBY (0x20000000U) //!< Bit mask for SIM_SOPT1_USBVSTBY.
mbed_official 146:f64d43ff0c18 188 #define BS_SIM_SOPT1_USBVSTBY (1U) //!< Bit field size in bits for SIM_SOPT1_USBVSTBY.
mbed_official 146:f64d43ff0c18 189
mbed_official 146:f64d43ff0c18 190 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 191 //! @brief Read current value of the SIM_SOPT1_USBVSTBY field.
mbed_official 146:f64d43ff0c18 192 #define BR_SIM_SOPT1_USBVSTBY (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR, BP_SIM_SOPT1_USBVSTBY))
mbed_official 146:f64d43ff0c18 193 #endif
mbed_official 146:f64d43ff0c18 194
mbed_official 146:f64d43ff0c18 195 //! @brief Format value for bitfield SIM_SOPT1_USBVSTBY.
mbed_official 146:f64d43ff0c18 196 #define BF_SIM_SOPT1_USBVSTBY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT1_USBVSTBY), uint32_t) & BM_SIM_SOPT1_USBVSTBY)
mbed_official 146:f64d43ff0c18 197
mbed_official 146:f64d43ff0c18 198 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 199 //! @brief Set the USBVSTBY field to a new value.
mbed_official 146:f64d43ff0c18 200 #define BW_SIM_SOPT1_USBVSTBY(v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR, BP_SIM_SOPT1_USBVSTBY) = (v))
mbed_official 146:f64d43ff0c18 201 #endif
mbed_official 146:f64d43ff0c18 202 //@}
mbed_official 146:f64d43ff0c18 203
mbed_official 146:f64d43ff0c18 204 /*!
mbed_official 146:f64d43ff0c18 205 * @name Register SIM_SOPT1, field USBSSTBY[30] (RW)
mbed_official 146:f64d43ff0c18 206 *
mbed_official 146:f64d43ff0c18 207 * Controls whether the USB voltage regulator is placed in standby mode during
mbed_official 146:f64d43ff0c18 208 * Stop, VLPS, LLS and VLLS modes.
mbed_official 146:f64d43ff0c18 209 *
mbed_official 146:f64d43ff0c18 210 * Values:
mbed_official 146:f64d43ff0c18 211 * - 0 - USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS
mbed_official 146:f64d43ff0c18 212 * modes.
mbed_official 146:f64d43ff0c18 213 * - 1 - USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes.
mbed_official 146:f64d43ff0c18 214 */
mbed_official 146:f64d43ff0c18 215 //@{
mbed_official 146:f64d43ff0c18 216 #define BP_SIM_SOPT1_USBSSTBY (30U) //!< Bit position for SIM_SOPT1_USBSSTBY.
mbed_official 146:f64d43ff0c18 217 #define BM_SIM_SOPT1_USBSSTBY (0x40000000U) //!< Bit mask for SIM_SOPT1_USBSSTBY.
mbed_official 146:f64d43ff0c18 218 #define BS_SIM_SOPT1_USBSSTBY (1U) //!< Bit field size in bits for SIM_SOPT1_USBSSTBY.
mbed_official 146:f64d43ff0c18 219
mbed_official 146:f64d43ff0c18 220 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 221 //! @brief Read current value of the SIM_SOPT1_USBSSTBY field.
mbed_official 146:f64d43ff0c18 222 #define BR_SIM_SOPT1_USBSSTBY (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR, BP_SIM_SOPT1_USBSSTBY))
mbed_official 146:f64d43ff0c18 223 #endif
mbed_official 146:f64d43ff0c18 224
mbed_official 146:f64d43ff0c18 225 //! @brief Format value for bitfield SIM_SOPT1_USBSSTBY.
mbed_official 146:f64d43ff0c18 226 #define BF_SIM_SOPT1_USBSSTBY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT1_USBSSTBY), uint32_t) & BM_SIM_SOPT1_USBSSTBY)
mbed_official 146:f64d43ff0c18 227
mbed_official 146:f64d43ff0c18 228 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 229 //! @brief Set the USBSSTBY field to a new value.
mbed_official 146:f64d43ff0c18 230 #define BW_SIM_SOPT1_USBSSTBY(v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR, BP_SIM_SOPT1_USBSSTBY) = (v))
mbed_official 146:f64d43ff0c18 231 #endif
mbed_official 146:f64d43ff0c18 232 //@}
mbed_official 146:f64d43ff0c18 233
mbed_official 146:f64d43ff0c18 234 /*!
mbed_official 146:f64d43ff0c18 235 * @name Register SIM_SOPT1, field USBREGEN[31] (RW)
mbed_official 146:f64d43ff0c18 236 *
mbed_official 146:f64d43ff0c18 237 * Controls whether the USB voltage regulator is enabled.
mbed_official 146:f64d43ff0c18 238 *
mbed_official 146:f64d43ff0c18 239 * Values:
mbed_official 146:f64d43ff0c18 240 * - 0 - USB voltage regulator is disabled.
mbed_official 146:f64d43ff0c18 241 * - 1 - USB voltage regulator is enabled.
mbed_official 146:f64d43ff0c18 242 */
mbed_official 146:f64d43ff0c18 243 //@{
mbed_official 146:f64d43ff0c18 244 #define BP_SIM_SOPT1_USBREGEN (31U) //!< Bit position for SIM_SOPT1_USBREGEN.
mbed_official 146:f64d43ff0c18 245 #define BM_SIM_SOPT1_USBREGEN (0x80000000U) //!< Bit mask for SIM_SOPT1_USBREGEN.
mbed_official 146:f64d43ff0c18 246 #define BS_SIM_SOPT1_USBREGEN (1U) //!< Bit field size in bits for SIM_SOPT1_USBREGEN.
mbed_official 146:f64d43ff0c18 247
mbed_official 146:f64d43ff0c18 248 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 249 //! @brief Read current value of the SIM_SOPT1_USBREGEN field.
mbed_official 146:f64d43ff0c18 250 #define BR_SIM_SOPT1_USBREGEN (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR, BP_SIM_SOPT1_USBREGEN))
mbed_official 146:f64d43ff0c18 251 #endif
mbed_official 146:f64d43ff0c18 252
mbed_official 146:f64d43ff0c18 253 //! @brief Format value for bitfield SIM_SOPT1_USBREGEN.
mbed_official 146:f64d43ff0c18 254 #define BF_SIM_SOPT1_USBREGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT1_USBREGEN), uint32_t) & BM_SIM_SOPT1_USBREGEN)
mbed_official 146:f64d43ff0c18 255
mbed_official 146:f64d43ff0c18 256 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 257 //! @brief Set the USBREGEN field to a new value.
mbed_official 146:f64d43ff0c18 258 #define BW_SIM_SOPT1_USBREGEN(v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR, BP_SIM_SOPT1_USBREGEN) = (v))
mbed_official 146:f64d43ff0c18 259 #endif
mbed_official 146:f64d43ff0c18 260 //@}
mbed_official 146:f64d43ff0c18 261
mbed_official 146:f64d43ff0c18 262 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 263 // HW_SIM_SOPT1CFG - SOPT1 Configuration Register
mbed_official 146:f64d43ff0c18 264 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 265
mbed_official 146:f64d43ff0c18 266 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 267 /*!
mbed_official 146:f64d43ff0c18 268 * @brief HW_SIM_SOPT1CFG - SOPT1 Configuration Register (RW)
mbed_official 146:f64d43ff0c18 269 *
mbed_official 146:f64d43ff0c18 270 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 271 *
mbed_official 146:f64d43ff0c18 272 * The SOPT1CFG register is reset on System Reset not VLLS.
mbed_official 146:f64d43ff0c18 273 */
mbed_official 146:f64d43ff0c18 274 typedef union _hw_sim_sopt1cfg
mbed_official 146:f64d43ff0c18 275 {
mbed_official 146:f64d43ff0c18 276 uint32_t U;
mbed_official 146:f64d43ff0c18 277 struct _hw_sim_sopt1cfg_bitfields
mbed_official 146:f64d43ff0c18 278 {
mbed_official 146:f64d43ff0c18 279 uint32_t RESERVED0 : 24; //!< [23:0]
mbed_official 146:f64d43ff0c18 280 uint32_t URWE : 1; //!< [24] USB voltage regulator enable write enable
mbed_official 146:f64d43ff0c18 281 uint32_t UVSWE : 1; //!< [25] USB voltage regulator VLP standby write
mbed_official 146:f64d43ff0c18 282 //! enable
mbed_official 146:f64d43ff0c18 283 uint32_t USSWE : 1; //!< [26] USB voltage regulator stop standby
mbed_official 146:f64d43ff0c18 284 //! write enable
mbed_official 146:f64d43ff0c18 285 uint32_t RESERVED1 : 5; //!< [31:27]
mbed_official 146:f64d43ff0c18 286 } B;
mbed_official 146:f64d43ff0c18 287 } hw_sim_sopt1cfg_t;
mbed_official 146:f64d43ff0c18 288 #endif
mbed_official 146:f64d43ff0c18 289
mbed_official 146:f64d43ff0c18 290 /*!
mbed_official 146:f64d43ff0c18 291 * @name Constants and macros for entire SIM_SOPT1CFG register
mbed_official 146:f64d43ff0c18 292 */
mbed_official 146:f64d43ff0c18 293 //@{
mbed_official 146:f64d43ff0c18 294 #define HW_SIM_SOPT1CFG_ADDR (REGS_SIM_BASE + 0x4U)
mbed_official 146:f64d43ff0c18 295
mbed_official 146:f64d43ff0c18 296 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 297 #define HW_SIM_SOPT1CFG (*(__IO hw_sim_sopt1cfg_t *) HW_SIM_SOPT1CFG_ADDR)
mbed_official 146:f64d43ff0c18 298 #define HW_SIM_SOPT1CFG_RD() (HW_SIM_SOPT1CFG.U)
mbed_official 146:f64d43ff0c18 299 #define HW_SIM_SOPT1CFG_WR(v) (HW_SIM_SOPT1CFG.U = (v))
mbed_official 146:f64d43ff0c18 300 #define HW_SIM_SOPT1CFG_SET(v) (HW_SIM_SOPT1CFG_WR(HW_SIM_SOPT1CFG_RD() | (v)))
mbed_official 146:f64d43ff0c18 301 #define HW_SIM_SOPT1CFG_CLR(v) (HW_SIM_SOPT1CFG_WR(HW_SIM_SOPT1CFG_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 302 #define HW_SIM_SOPT1CFG_TOG(v) (HW_SIM_SOPT1CFG_WR(HW_SIM_SOPT1CFG_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 303 #endif
mbed_official 146:f64d43ff0c18 304 //@}
mbed_official 146:f64d43ff0c18 305
mbed_official 146:f64d43ff0c18 306 /*
mbed_official 146:f64d43ff0c18 307 * Constants & macros for individual SIM_SOPT1CFG bitfields
mbed_official 146:f64d43ff0c18 308 */
mbed_official 146:f64d43ff0c18 309
mbed_official 146:f64d43ff0c18 310 /*!
mbed_official 146:f64d43ff0c18 311 * @name Register SIM_SOPT1CFG, field URWE[24] (RW)
mbed_official 146:f64d43ff0c18 312 *
mbed_official 146:f64d43ff0c18 313 * Writing one to the URWE bit allows the SOPT1 USBREGEN bit to be written. This
mbed_official 146:f64d43ff0c18 314 * register bit clears after a write to USBREGEN.
mbed_official 146:f64d43ff0c18 315 *
mbed_official 146:f64d43ff0c18 316 * Values:
mbed_official 146:f64d43ff0c18 317 * - 0 - SOPT1 USBREGEN cannot be written.
mbed_official 146:f64d43ff0c18 318 * - 1 - SOPT1 USBREGEN can be written.
mbed_official 146:f64d43ff0c18 319 */
mbed_official 146:f64d43ff0c18 320 //@{
mbed_official 146:f64d43ff0c18 321 #define BP_SIM_SOPT1CFG_URWE (24U) //!< Bit position for SIM_SOPT1CFG_URWE.
mbed_official 146:f64d43ff0c18 322 #define BM_SIM_SOPT1CFG_URWE (0x01000000U) //!< Bit mask for SIM_SOPT1CFG_URWE.
mbed_official 146:f64d43ff0c18 323 #define BS_SIM_SOPT1CFG_URWE (1U) //!< Bit field size in bits for SIM_SOPT1CFG_URWE.
mbed_official 146:f64d43ff0c18 324
mbed_official 146:f64d43ff0c18 325 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 326 //! @brief Read current value of the SIM_SOPT1CFG_URWE field.
mbed_official 146:f64d43ff0c18 327 #define BR_SIM_SOPT1CFG_URWE (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR, BP_SIM_SOPT1CFG_URWE))
mbed_official 146:f64d43ff0c18 328 #endif
mbed_official 146:f64d43ff0c18 329
mbed_official 146:f64d43ff0c18 330 //! @brief Format value for bitfield SIM_SOPT1CFG_URWE.
mbed_official 146:f64d43ff0c18 331 #define BF_SIM_SOPT1CFG_URWE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT1CFG_URWE), uint32_t) & BM_SIM_SOPT1CFG_URWE)
mbed_official 146:f64d43ff0c18 332
mbed_official 146:f64d43ff0c18 333 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 334 //! @brief Set the URWE field to a new value.
mbed_official 146:f64d43ff0c18 335 #define BW_SIM_SOPT1CFG_URWE(v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR, BP_SIM_SOPT1CFG_URWE) = (v))
mbed_official 146:f64d43ff0c18 336 #endif
mbed_official 146:f64d43ff0c18 337 //@}
mbed_official 146:f64d43ff0c18 338
mbed_official 146:f64d43ff0c18 339 /*!
mbed_official 146:f64d43ff0c18 340 * @name Register SIM_SOPT1CFG, field UVSWE[25] (RW)
mbed_official 146:f64d43ff0c18 341 *
mbed_official 146:f64d43ff0c18 342 * Writing one to the UVSWE bit allows the SOPT1 USBVSTBY bit to be written.
mbed_official 146:f64d43ff0c18 343 * This register bit clears after a write to USBVSTBY.
mbed_official 146:f64d43ff0c18 344 *
mbed_official 146:f64d43ff0c18 345 * Values:
mbed_official 146:f64d43ff0c18 346 * - 0 - SOPT1 USBVSTBY cannot be written.
mbed_official 146:f64d43ff0c18 347 * - 1 - SOPT1 USBVSTBY can be written.
mbed_official 146:f64d43ff0c18 348 */
mbed_official 146:f64d43ff0c18 349 //@{
mbed_official 146:f64d43ff0c18 350 #define BP_SIM_SOPT1CFG_UVSWE (25U) //!< Bit position for SIM_SOPT1CFG_UVSWE.
mbed_official 146:f64d43ff0c18 351 #define BM_SIM_SOPT1CFG_UVSWE (0x02000000U) //!< Bit mask for SIM_SOPT1CFG_UVSWE.
mbed_official 146:f64d43ff0c18 352 #define BS_SIM_SOPT1CFG_UVSWE (1U) //!< Bit field size in bits for SIM_SOPT1CFG_UVSWE.
mbed_official 146:f64d43ff0c18 353
mbed_official 146:f64d43ff0c18 354 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 355 //! @brief Read current value of the SIM_SOPT1CFG_UVSWE field.
mbed_official 146:f64d43ff0c18 356 #define BR_SIM_SOPT1CFG_UVSWE (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR, BP_SIM_SOPT1CFG_UVSWE))
mbed_official 146:f64d43ff0c18 357 #endif
mbed_official 146:f64d43ff0c18 358
mbed_official 146:f64d43ff0c18 359 //! @brief Format value for bitfield SIM_SOPT1CFG_UVSWE.
mbed_official 146:f64d43ff0c18 360 #define BF_SIM_SOPT1CFG_UVSWE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT1CFG_UVSWE), uint32_t) & BM_SIM_SOPT1CFG_UVSWE)
mbed_official 146:f64d43ff0c18 361
mbed_official 146:f64d43ff0c18 362 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 363 //! @brief Set the UVSWE field to a new value.
mbed_official 146:f64d43ff0c18 364 #define BW_SIM_SOPT1CFG_UVSWE(v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR, BP_SIM_SOPT1CFG_UVSWE) = (v))
mbed_official 146:f64d43ff0c18 365 #endif
mbed_official 146:f64d43ff0c18 366 //@}
mbed_official 146:f64d43ff0c18 367
mbed_official 146:f64d43ff0c18 368 /*!
mbed_official 146:f64d43ff0c18 369 * @name Register SIM_SOPT1CFG, field USSWE[26] (RW)
mbed_official 146:f64d43ff0c18 370 *
mbed_official 146:f64d43ff0c18 371 * Writing one to the USSWE bit allows the SOPT1 USBSSTBY bit to be written.
mbed_official 146:f64d43ff0c18 372 * This register bit clears after a write to USBSSTBY.
mbed_official 146:f64d43ff0c18 373 *
mbed_official 146:f64d43ff0c18 374 * Values:
mbed_official 146:f64d43ff0c18 375 * - 0 - SOPT1 USBSSTBY cannot be written.
mbed_official 146:f64d43ff0c18 376 * - 1 - SOPT1 USBSSTBY can be written.
mbed_official 146:f64d43ff0c18 377 */
mbed_official 146:f64d43ff0c18 378 //@{
mbed_official 146:f64d43ff0c18 379 #define BP_SIM_SOPT1CFG_USSWE (26U) //!< Bit position for SIM_SOPT1CFG_USSWE.
mbed_official 146:f64d43ff0c18 380 #define BM_SIM_SOPT1CFG_USSWE (0x04000000U) //!< Bit mask for SIM_SOPT1CFG_USSWE.
mbed_official 146:f64d43ff0c18 381 #define BS_SIM_SOPT1CFG_USSWE (1U) //!< Bit field size in bits for SIM_SOPT1CFG_USSWE.
mbed_official 146:f64d43ff0c18 382
mbed_official 146:f64d43ff0c18 383 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 384 //! @brief Read current value of the SIM_SOPT1CFG_USSWE field.
mbed_official 146:f64d43ff0c18 385 #define BR_SIM_SOPT1CFG_USSWE (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR, BP_SIM_SOPT1CFG_USSWE))
mbed_official 146:f64d43ff0c18 386 #endif
mbed_official 146:f64d43ff0c18 387
mbed_official 146:f64d43ff0c18 388 //! @brief Format value for bitfield SIM_SOPT1CFG_USSWE.
mbed_official 146:f64d43ff0c18 389 #define BF_SIM_SOPT1CFG_USSWE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT1CFG_USSWE), uint32_t) & BM_SIM_SOPT1CFG_USSWE)
mbed_official 146:f64d43ff0c18 390
mbed_official 146:f64d43ff0c18 391 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 392 //! @brief Set the USSWE field to a new value.
mbed_official 146:f64d43ff0c18 393 #define BW_SIM_SOPT1CFG_USSWE(v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR, BP_SIM_SOPT1CFG_USSWE) = (v))
mbed_official 146:f64d43ff0c18 394 #endif
mbed_official 146:f64d43ff0c18 395 //@}
mbed_official 146:f64d43ff0c18 396
mbed_official 146:f64d43ff0c18 397 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 398 // HW_SIM_SOPT2 - System Options Register 2
mbed_official 146:f64d43ff0c18 399 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 400
mbed_official 146:f64d43ff0c18 401 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 402 /*!
mbed_official 146:f64d43ff0c18 403 * @brief HW_SIM_SOPT2 - System Options Register 2 (RW)
mbed_official 146:f64d43ff0c18 404 *
mbed_official 146:f64d43ff0c18 405 * Reset value: 0x00001000U
mbed_official 146:f64d43ff0c18 406 *
mbed_official 146:f64d43ff0c18 407 * SOPT2 contains the controls for selecting many of the module clock source
mbed_official 146:f64d43ff0c18 408 * options on this device. See the Clock Distribution chapter for more information
mbed_official 146:f64d43ff0c18 409 * including clocking diagrams and definitions of device clocks.
mbed_official 146:f64d43ff0c18 410 */
mbed_official 146:f64d43ff0c18 411 typedef union _hw_sim_sopt2
mbed_official 146:f64d43ff0c18 412 {
mbed_official 146:f64d43ff0c18 413 uint32_t U;
mbed_official 146:f64d43ff0c18 414 struct _hw_sim_sopt2_bitfields
mbed_official 146:f64d43ff0c18 415 {
mbed_official 146:f64d43ff0c18 416 uint32_t RESERVED0 : 4; //!< [3:0]
mbed_official 146:f64d43ff0c18 417 uint32_t RTCCLKOUTSEL : 1; //!< [4] RTC clock out select
mbed_official 146:f64d43ff0c18 418 uint32_t CLKOUTSEL : 3; //!< [7:5] CLKOUT select
mbed_official 146:f64d43ff0c18 419 uint32_t FBSL : 2; //!< [9:8] FlexBus security level
mbed_official 146:f64d43ff0c18 420 uint32_t RESERVED1 : 1; //!< [10]
mbed_official 146:f64d43ff0c18 421 uint32_t PTD7PAD : 1; //!< [11] PTD7 pad drive strength
mbed_official 146:f64d43ff0c18 422 uint32_t TRACECLKSEL : 1; //!< [12] Debug trace clock select
mbed_official 146:f64d43ff0c18 423 uint32_t RESERVED2 : 3; //!< [15:13]
mbed_official 146:f64d43ff0c18 424 uint32_t PLLFLLSEL : 2; //!< [17:16] PLL/FLL clock select
mbed_official 146:f64d43ff0c18 425 uint32_t USBSRC : 1; //!< [18] USB clock source select
mbed_official 146:f64d43ff0c18 426 uint32_t RMIISRC : 1; //!< [19] RMII clock source select
mbed_official 146:f64d43ff0c18 427 uint32_t TIMESRC : 2; //!< [21:20] IEEE 1588 timestamp clock source
mbed_official 146:f64d43ff0c18 428 //! select
mbed_official 146:f64d43ff0c18 429 uint32_t RESERVED3 : 6; //!< [27:22]
mbed_official 146:f64d43ff0c18 430 uint32_t SDHCSRC : 2; //!< [29:28] SDHC clock source select
mbed_official 146:f64d43ff0c18 431 uint32_t RESERVED4 : 2; //!< [31:30]
mbed_official 146:f64d43ff0c18 432 } B;
mbed_official 146:f64d43ff0c18 433 } hw_sim_sopt2_t;
mbed_official 146:f64d43ff0c18 434 #endif
mbed_official 146:f64d43ff0c18 435
mbed_official 146:f64d43ff0c18 436 /*!
mbed_official 146:f64d43ff0c18 437 * @name Constants and macros for entire SIM_SOPT2 register
mbed_official 146:f64d43ff0c18 438 */
mbed_official 146:f64d43ff0c18 439 //@{
mbed_official 146:f64d43ff0c18 440 #define HW_SIM_SOPT2_ADDR (REGS_SIM_BASE + 0x1004U)
mbed_official 146:f64d43ff0c18 441
mbed_official 146:f64d43ff0c18 442 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 443 #define HW_SIM_SOPT2 (*(__IO hw_sim_sopt2_t *) HW_SIM_SOPT2_ADDR)
mbed_official 146:f64d43ff0c18 444 #define HW_SIM_SOPT2_RD() (HW_SIM_SOPT2.U)
mbed_official 146:f64d43ff0c18 445 #define HW_SIM_SOPT2_WR(v) (HW_SIM_SOPT2.U = (v))
mbed_official 146:f64d43ff0c18 446 #define HW_SIM_SOPT2_SET(v) (HW_SIM_SOPT2_WR(HW_SIM_SOPT2_RD() | (v)))
mbed_official 146:f64d43ff0c18 447 #define HW_SIM_SOPT2_CLR(v) (HW_SIM_SOPT2_WR(HW_SIM_SOPT2_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 448 #define HW_SIM_SOPT2_TOG(v) (HW_SIM_SOPT2_WR(HW_SIM_SOPT2_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 449 #endif
mbed_official 146:f64d43ff0c18 450 //@}
mbed_official 146:f64d43ff0c18 451
mbed_official 146:f64d43ff0c18 452 /*
mbed_official 146:f64d43ff0c18 453 * Constants & macros for individual SIM_SOPT2 bitfields
mbed_official 146:f64d43ff0c18 454 */
mbed_official 146:f64d43ff0c18 455
mbed_official 146:f64d43ff0c18 456 /*!
mbed_official 146:f64d43ff0c18 457 * @name Register SIM_SOPT2, field RTCCLKOUTSEL[4] (RW)
mbed_official 146:f64d43ff0c18 458 *
mbed_official 146:f64d43ff0c18 459 * Selects either the RTC 1 Hz clock or the 32.768kHz clock to be output on the
mbed_official 146:f64d43ff0c18 460 * RTC_CLKOUT pin.
mbed_official 146:f64d43ff0c18 461 *
mbed_official 146:f64d43ff0c18 462 * Values:
mbed_official 146:f64d43ff0c18 463 * - 0 - RTC 1 Hz clock is output on the RTC_CLKOUT pin.
mbed_official 146:f64d43ff0c18 464 * - 1 - RTC 32.768kHz clock is output on the RTC_CLKOUT pin.
mbed_official 146:f64d43ff0c18 465 */
mbed_official 146:f64d43ff0c18 466 //@{
mbed_official 146:f64d43ff0c18 467 #define BP_SIM_SOPT2_RTCCLKOUTSEL (4U) //!< Bit position for SIM_SOPT2_RTCCLKOUTSEL.
mbed_official 146:f64d43ff0c18 468 #define BM_SIM_SOPT2_RTCCLKOUTSEL (0x00000010U) //!< Bit mask for SIM_SOPT2_RTCCLKOUTSEL.
mbed_official 146:f64d43ff0c18 469 #define BS_SIM_SOPT2_RTCCLKOUTSEL (1U) //!< Bit field size in bits for SIM_SOPT2_RTCCLKOUTSEL.
mbed_official 146:f64d43ff0c18 470
mbed_official 146:f64d43ff0c18 471 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 472 //! @brief Read current value of the SIM_SOPT2_RTCCLKOUTSEL field.
mbed_official 146:f64d43ff0c18 473 #define BR_SIM_SOPT2_RTCCLKOUTSEL (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_RTCCLKOUTSEL))
mbed_official 146:f64d43ff0c18 474 #endif
mbed_official 146:f64d43ff0c18 475
mbed_official 146:f64d43ff0c18 476 //! @brief Format value for bitfield SIM_SOPT2_RTCCLKOUTSEL.
mbed_official 146:f64d43ff0c18 477 #define BF_SIM_SOPT2_RTCCLKOUTSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_RTCCLKOUTSEL), uint32_t) & BM_SIM_SOPT2_RTCCLKOUTSEL)
mbed_official 146:f64d43ff0c18 478
mbed_official 146:f64d43ff0c18 479 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 480 //! @brief Set the RTCCLKOUTSEL field to a new value.
mbed_official 146:f64d43ff0c18 481 #define BW_SIM_SOPT2_RTCCLKOUTSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_RTCCLKOUTSEL) = (v))
mbed_official 146:f64d43ff0c18 482 #endif
mbed_official 146:f64d43ff0c18 483 //@}
mbed_official 146:f64d43ff0c18 484
mbed_official 146:f64d43ff0c18 485 /*!
mbed_official 146:f64d43ff0c18 486 * @name Register SIM_SOPT2, field CLKOUTSEL[7:5] (RW)
mbed_official 146:f64d43ff0c18 487 *
mbed_official 146:f64d43ff0c18 488 * Selects the clock to output on the CLKOUT pin.
mbed_official 146:f64d43ff0c18 489 *
mbed_official 146:f64d43ff0c18 490 * Values:
mbed_official 146:f64d43ff0c18 491 * - 000 - FlexBus CLKOUT
mbed_official 146:f64d43ff0c18 492 * - 001 - Reserved
mbed_official 146:f64d43ff0c18 493 * - 010 - Flash clock
mbed_official 146:f64d43ff0c18 494 * - 011 - LPO clock (1 kHz)
mbed_official 146:f64d43ff0c18 495 * - 100 - MCGIRCLK
mbed_official 146:f64d43ff0c18 496 * - 101 - RTC 32.768kHz clock
mbed_official 146:f64d43ff0c18 497 * - 110 - OSCERCLK0
mbed_official 146:f64d43ff0c18 498 * - 111 - IRC 48 MHz clock
mbed_official 146:f64d43ff0c18 499 */
mbed_official 146:f64d43ff0c18 500 //@{
mbed_official 146:f64d43ff0c18 501 #define BP_SIM_SOPT2_CLKOUTSEL (5U) //!< Bit position for SIM_SOPT2_CLKOUTSEL.
mbed_official 146:f64d43ff0c18 502 #define BM_SIM_SOPT2_CLKOUTSEL (0x000000E0U) //!< Bit mask for SIM_SOPT2_CLKOUTSEL.
mbed_official 146:f64d43ff0c18 503 #define BS_SIM_SOPT2_CLKOUTSEL (3U) //!< Bit field size in bits for SIM_SOPT2_CLKOUTSEL.
mbed_official 146:f64d43ff0c18 504
mbed_official 146:f64d43ff0c18 505 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 506 //! @brief Read current value of the SIM_SOPT2_CLKOUTSEL field.
mbed_official 146:f64d43ff0c18 507 #define BR_SIM_SOPT2_CLKOUTSEL (HW_SIM_SOPT2.B.CLKOUTSEL)
mbed_official 146:f64d43ff0c18 508 #endif
mbed_official 146:f64d43ff0c18 509
mbed_official 146:f64d43ff0c18 510 //! @brief Format value for bitfield SIM_SOPT2_CLKOUTSEL.
mbed_official 146:f64d43ff0c18 511 #define BF_SIM_SOPT2_CLKOUTSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_CLKOUTSEL), uint32_t) & BM_SIM_SOPT2_CLKOUTSEL)
mbed_official 146:f64d43ff0c18 512
mbed_official 146:f64d43ff0c18 513 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 514 //! @brief Set the CLKOUTSEL field to a new value.
mbed_official 146:f64d43ff0c18 515 #define BW_SIM_SOPT2_CLKOUTSEL(v) (HW_SIM_SOPT2_WR((HW_SIM_SOPT2_RD() & ~BM_SIM_SOPT2_CLKOUTSEL) | BF_SIM_SOPT2_CLKOUTSEL(v)))
mbed_official 146:f64d43ff0c18 516 #endif
mbed_official 146:f64d43ff0c18 517 //@}
mbed_official 146:f64d43ff0c18 518
mbed_official 146:f64d43ff0c18 519 /*!
mbed_official 146:f64d43ff0c18 520 * @name Register SIM_SOPT2, field FBSL[9:8] (RW)
mbed_official 146:f64d43ff0c18 521 *
mbed_official 146:f64d43ff0c18 522 * If flash security is enabled, then this field affects what CPU operations can
mbed_official 146:f64d43ff0c18 523 * access off-chip via the FlexBus interface. This field has no effect if flash
mbed_official 146:f64d43ff0c18 524 * security is not enabled.
mbed_official 146:f64d43ff0c18 525 *
mbed_official 146:f64d43ff0c18 526 * Values:
mbed_official 146:f64d43ff0c18 527 * - 00 - All off-chip accesses (instruction and data) via the FlexBus are
mbed_official 146:f64d43ff0c18 528 * disallowed.
mbed_official 146:f64d43ff0c18 529 * - 01 - All off-chip accesses (instruction and data) via the FlexBus are
mbed_official 146:f64d43ff0c18 530 * disallowed.
mbed_official 146:f64d43ff0c18 531 * - 10 - Off-chip instruction accesses are disallowed. Data accesses are
mbed_official 146:f64d43ff0c18 532 * allowed.
mbed_official 146:f64d43ff0c18 533 * - 11 - Off-chip instruction accesses and data accesses are allowed.
mbed_official 146:f64d43ff0c18 534 */
mbed_official 146:f64d43ff0c18 535 //@{
mbed_official 146:f64d43ff0c18 536 #define BP_SIM_SOPT2_FBSL (8U) //!< Bit position for SIM_SOPT2_FBSL.
mbed_official 146:f64d43ff0c18 537 #define BM_SIM_SOPT2_FBSL (0x00000300U) //!< Bit mask for SIM_SOPT2_FBSL.
mbed_official 146:f64d43ff0c18 538 #define BS_SIM_SOPT2_FBSL (2U) //!< Bit field size in bits for SIM_SOPT2_FBSL.
mbed_official 146:f64d43ff0c18 539
mbed_official 146:f64d43ff0c18 540 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 541 //! @brief Read current value of the SIM_SOPT2_FBSL field.
mbed_official 146:f64d43ff0c18 542 #define BR_SIM_SOPT2_FBSL (HW_SIM_SOPT2.B.FBSL)
mbed_official 146:f64d43ff0c18 543 #endif
mbed_official 146:f64d43ff0c18 544
mbed_official 146:f64d43ff0c18 545 //! @brief Format value for bitfield SIM_SOPT2_FBSL.
mbed_official 146:f64d43ff0c18 546 #define BF_SIM_SOPT2_FBSL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_FBSL), uint32_t) & BM_SIM_SOPT2_FBSL)
mbed_official 146:f64d43ff0c18 547
mbed_official 146:f64d43ff0c18 548 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 549 //! @brief Set the FBSL field to a new value.
mbed_official 146:f64d43ff0c18 550 #define BW_SIM_SOPT2_FBSL(v) (HW_SIM_SOPT2_WR((HW_SIM_SOPT2_RD() & ~BM_SIM_SOPT2_FBSL) | BF_SIM_SOPT2_FBSL(v)))
mbed_official 146:f64d43ff0c18 551 #endif
mbed_official 146:f64d43ff0c18 552 //@}
mbed_official 146:f64d43ff0c18 553
mbed_official 146:f64d43ff0c18 554 /*!
mbed_official 146:f64d43ff0c18 555 * @name Register SIM_SOPT2, field PTD7PAD[11] (RW)
mbed_official 146:f64d43ff0c18 556 *
mbed_official 146:f64d43ff0c18 557 * Controls the output drive strength of the PTD7 pin by selecting either one or
mbed_official 146:f64d43ff0c18 558 * two pads to drive it.
mbed_official 146:f64d43ff0c18 559 *
mbed_official 146:f64d43ff0c18 560 * Values:
mbed_official 146:f64d43ff0c18 561 * - 0 - Single-pad drive strength for PTD7.
mbed_official 146:f64d43ff0c18 562 * - 1 - Double pad drive strength for PTD7.
mbed_official 146:f64d43ff0c18 563 */
mbed_official 146:f64d43ff0c18 564 //@{
mbed_official 146:f64d43ff0c18 565 #define BP_SIM_SOPT2_PTD7PAD (11U) //!< Bit position for SIM_SOPT2_PTD7PAD.
mbed_official 146:f64d43ff0c18 566 #define BM_SIM_SOPT2_PTD7PAD (0x00000800U) //!< Bit mask for SIM_SOPT2_PTD7PAD.
mbed_official 146:f64d43ff0c18 567 #define BS_SIM_SOPT2_PTD7PAD (1U) //!< Bit field size in bits for SIM_SOPT2_PTD7PAD.
mbed_official 146:f64d43ff0c18 568
mbed_official 146:f64d43ff0c18 569 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 570 //! @brief Read current value of the SIM_SOPT2_PTD7PAD field.
mbed_official 146:f64d43ff0c18 571 #define BR_SIM_SOPT2_PTD7PAD (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_PTD7PAD))
mbed_official 146:f64d43ff0c18 572 #endif
mbed_official 146:f64d43ff0c18 573
mbed_official 146:f64d43ff0c18 574 //! @brief Format value for bitfield SIM_SOPT2_PTD7PAD.
mbed_official 146:f64d43ff0c18 575 #define BF_SIM_SOPT2_PTD7PAD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_PTD7PAD), uint32_t) & BM_SIM_SOPT2_PTD7PAD)
mbed_official 146:f64d43ff0c18 576
mbed_official 146:f64d43ff0c18 577 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 578 //! @brief Set the PTD7PAD field to a new value.
mbed_official 146:f64d43ff0c18 579 #define BW_SIM_SOPT2_PTD7PAD(v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_PTD7PAD) = (v))
mbed_official 146:f64d43ff0c18 580 #endif
mbed_official 146:f64d43ff0c18 581 //@}
mbed_official 146:f64d43ff0c18 582
mbed_official 146:f64d43ff0c18 583 /*!
mbed_official 146:f64d43ff0c18 584 * @name Register SIM_SOPT2, field TRACECLKSEL[12] (RW)
mbed_official 146:f64d43ff0c18 585 *
mbed_official 146:f64d43ff0c18 586 * Selects the core/system clock or MCG output clock (MCGOUTCLK) as the trace
mbed_official 146:f64d43ff0c18 587 * clock source.
mbed_official 146:f64d43ff0c18 588 *
mbed_official 146:f64d43ff0c18 589 * Values:
mbed_official 146:f64d43ff0c18 590 * - 0 - MCGOUTCLK
mbed_official 146:f64d43ff0c18 591 * - 1 - Core/system clock
mbed_official 146:f64d43ff0c18 592 */
mbed_official 146:f64d43ff0c18 593 //@{
mbed_official 146:f64d43ff0c18 594 #define BP_SIM_SOPT2_TRACECLKSEL (12U) //!< Bit position for SIM_SOPT2_TRACECLKSEL.
mbed_official 146:f64d43ff0c18 595 #define BM_SIM_SOPT2_TRACECLKSEL (0x00001000U) //!< Bit mask for SIM_SOPT2_TRACECLKSEL.
mbed_official 146:f64d43ff0c18 596 #define BS_SIM_SOPT2_TRACECLKSEL (1U) //!< Bit field size in bits for SIM_SOPT2_TRACECLKSEL.
mbed_official 146:f64d43ff0c18 597
mbed_official 146:f64d43ff0c18 598 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 599 //! @brief Read current value of the SIM_SOPT2_TRACECLKSEL field.
mbed_official 146:f64d43ff0c18 600 #define BR_SIM_SOPT2_TRACECLKSEL (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_TRACECLKSEL))
mbed_official 146:f64d43ff0c18 601 #endif
mbed_official 146:f64d43ff0c18 602
mbed_official 146:f64d43ff0c18 603 //! @brief Format value for bitfield SIM_SOPT2_TRACECLKSEL.
mbed_official 146:f64d43ff0c18 604 #define BF_SIM_SOPT2_TRACECLKSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_TRACECLKSEL), uint32_t) & BM_SIM_SOPT2_TRACECLKSEL)
mbed_official 146:f64d43ff0c18 605
mbed_official 146:f64d43ff0c18 606 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 607 //! @brief Set the TRACECLKSEL field to a new value.
mbed_official 146:f64d43ff0c18 608 #define BW_SIM_SOPT2_TRACECLKSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_TRACECLKSEL) = (v))
mbed_official 146:f64d43ff0c18 609 #endif
mbed_official 146:f64d43ff0c18 610 //@}
mbed_official 146:f64d43ff0c18 611
mbed_official 146:f64d43ff0c18 612 /*!
mbed_official 146:f64d43ff0c18 613 * @name Register SIM_SOPT2, field PLLFLLSEL[17:16] (RW)
mbed_official 146:f64d43ff0c18 614 *
mbed_official 146:f64d43ff0c18 615 * Selects the high frequency clock for various peripheral clocking options.
mbed_official 146:f64d43ff0c18 616 *
mbed_official 146:f64d43ff0c18 617 * Values:
mbed_official 146:f64d43ff0c18 618 * - 00 - MCGFLLCLK clock
mbed_official 146:f64d43ff0c18 619 * - 01 - MCGPLLCLK clock
mbed_official 146:f64d43ff0c18 620 * - 10 - Reserved
mbed_official 146:f64d43ff0c18 621 * - 11 - IRC48 MHz clock
mbed_official 146:f64d43ff0c18 622 */
mbed_official 146:f64d43ff0c18 623 //@{
mbed_official 146:f64d43ff0c18 624 #define BP_SIM_SOPT2_PLLFLLSEL (16U) //!< Bit position for SIM_SOPT2_PLLFLLSEL.
mbed_official 146:f64d43ff0c18 625 #define BM_SIM_SOPT2_PLLFLLSEL (0x00030000U) //!< Bit mask for SIM_SOPT2_PLLFLLSEL.
mbed_official 146:f64d43ff0c18 626 #define BS_SIM_SOPT2_PLLFLLSEL (2U) //!< Bit field size in bits for SIM_SOPT2_PLLFLLSEL.
mbed_official 146:f64d43ff0c18 627
mbed_official 146:f64d43ff0c18 628 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 629 //! @brief Read current value of the SIM_SOPT2_PLLFLLSEL field.
mbed_official 146:f64d43ff0c18 630 #define BR_SIM_SOPT2_PLLFLLSEL (HW_SIM_SOPT2.B.PLLFLLSEL)
mbed_official 146:f64d43ff0c18 631 #endif
mbed_official 146:f64d43ff0c18 632
mbed_official 146:f64d43ff0c18 633 //! @brief Format value for bitfield SIM_SOPT2_PLLFLLSEL.
mbed_official 146:f64d43ff0c18 634 #define BF_SIM_SOPT2_PLLFLLSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_PLLFLLSEL), uint32_t) & BM_SIM_SOPT2_PLLFLLSEL)
mbed_official 146:f64d43ff0c18 635
mbed_official 146:f64d43ff0c18 636 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 637 //! @brief Set the PLLFLLSEL field to a new value.
mbed_official 146:f64d43ff0c18 638 #define BW_SIM_SOPT2_PLLFLLSEL(v) (HW_SIM_SOPT2_WR((HW_SIM_SOPT2_RD() & ~BM_SIM_SOPT2_PLLFLLSEL) | BF_SIM_SOPT2_PLLFLLSEL(v)))
mbed_official 146:f64d43ff0c18 639 #endif
mbed_official 146:f64d43ff0c18 640 //@}
mbed_official 146:f64d43ff0c18 641
mbed_official 146:f64d43ff0c18 642 /*!
mbed_official 146:f64d43ff0c18 643 * @name Register SIM_SOPT2, field USBSRC[18] (RW)
mbed_official 146:f64d43ff0c18 644 *
mbed_official 146:f64d43ff0c18 645 * Selects the clock source for the USB 48 MHz clock.
mbed_official 146:f64d43ff0c18 646 *
mbed_official 146:f64d43ff0c18 647 * Values:
mbed_official 146:f64d43ff0c18 648 * - 0 - External bypass clock (USB_CLKIN).
mbed_official 146:f64d43ff0c18 649 * - 1 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by
mbed_official 146:f64d43ff0c18 650 * SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by
mbed_official 146:f64d43ff0c18 651 * SIM_CLKDIV2[USBFRAC, USBDIV].
mbed_official 146:f64d43ff0c18 652 */
mbed_official 146:f64d43ff0c18 653 //@{
mbed_official 146:f64d43ff0c18 654 #define BP_SIM_SOPT2_USBSRC (18U) //!< Bit position for SIM_SOPT2_USBSRC.
mbed_official 146:f64d43ff0c18 655 #define BM_SIM_SOPT2_USBSRC (0x00040000U) //!< Bit mask for SIM_SOPT2_USBSRC.
mbed_official 146:f64d43ff0c18 656 #define BS_SIM_SOPT2_USBSRC (1U) //!< Bit field size in bits for SIM_SOPT2_USBSRC.
mbed_official 146:f64d43ff0c18 657
mbed_official 146:f64d43ff0c18 658 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 659 //! @brief Read current value of the SIM_SOPT2_USBSRC field.
mbed_official 146:f64d43ff0c18 660 #define BR_SIM_SOPT2_USBSRC (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_USBSRC))
mbed_official 146:f64d43ff0c18 661 #endif
mbed_official 146:f64d43ff0c18 662
mbed_official 146:f64d43ff0c18 663 //! @brief Format value for bitfield SIM_SOPT2_USBSRC.
mbed_official 146:f64d43ff0c18 664 #define BF_SIM_SOPT2_USBSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_USBSRC), uint32_t) & BM_SIM_SOPT2_USBSRC)
mbed_official 146:f64d43ff0c18 665
mbed_official 146:f64d43ff0c18 666 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 667 //! @brief Set the USBSRC field to a new value.
mbed_official 146:f64d43ff0c18 668 #define BW_SIM_SOPT2_USBSRC(v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_USBSRC) = (v))
mbed_official 146:f64d43ff0c18 669 #endif
mbed_official 146:f64d43ff0c18 670 //@}
mbed_official 146:f64d43ff0c18 671
mbed_official 146:f64d43ff0c18 672 /*!
mbed_official 146:f64d43ff0c18 673 * @name Register SIM_SOPT2, field RMIISRC[19] (RW)
mbed_official 146:f64d43ff0c18 674 *
mbed_official 146:f64d43ff0c18 675 * Selects the clock source for the Ethernet RMII interface
mbed_official 146:f64d43ff0c18 676 *
mbed_official 146:f64d43ff0c18 677 * Values:
mbed_official 146:f64d43ff0c18 678 * - 0 - EXTAL clock
mbed_official 146:f64d43ff0c18 679 * - 1 - External bypass clock (ENET_1588_CLKIN).
mbed_official 146:f64d43ff0c18 680 */
mbed_official 146:f64d43ff0c18 681 //@{
mbed_official 146:f64d43ff0c18 682 #define BP_SIM_SOPT2_RMIISRC (19U) //!< Bit position for SIM_SOPT2_RMIISRC.
mbed_official 146:f64d43ff0c18 683 #define BM_SIM_SOPT2_RMIISRC (0x00080000U) //!< Bit mask for SIM_SOPT2_RMIISRC.
mbed_official 146:f64d43ff0c18 684 #define BS_SIM_SOPT2_RMIISRC (1U) //!< Bit field size in bits for SIM_SOPT2_RMIISRC.
mbed_official 146:f64d43ff0c18 685
mbed_official 146:f64d43ff0c18 686 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 687 //! @brief Read current value of the SIM_SOPT2_RMIISRC field.
mbed_official 146:f64d43ff0c18 688 #define BR_SIM_SOPT2_RMIISRC (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_RMIISRC))
mbed_official 146:f64d43ff0c18 689 #endif
mbed_official 146:f64d43ff0c18 690
mbed_official 146:f64d43ff0c18 691 //! @brief Format value for bitfield SIM_SOPT2_RMIISRC.
mbed_official 146:f64d43ff0c18 692 #define BF_SIM_SOPT2_RMIISRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_RMIISRC), uint32_t) & BM_SIM_SOPT2_RMIISRC)
mbed_official 146:f64d43ff0c18 693
mbed_official 146:f64d43ff0c18 694 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 695 //! @brief Set the RMIISRC field to a new value.
mbed_official 146:f64d43ff0c18 696 #define BW_SIM_SOPT2_RMIISRC(v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_RMIISRC) = (v))
mbed_official 146:f64d43ff0c18 697 #endif
mbed_official 146:f64d43ff0c18 698 //@}
mbed_official 146:f64d43ff0c18 699
mbed_official 146:f64d43ff0c18 700 /*!
mbed_official 146:f64d43ff0c18 701 * @name Register SIM_SOPT2, field TIMESRC[21:20] (RW)
mbed_official 146:f64d43ff0c18 702 *
mbed_official 146:f64d43ff0c18 703 * Selects the clock source for the Ethernet timestamp clock.
mbed_official 146:f64d43ff0c18 704 *
mbed_official 146:f64d43ff0c18 705 * Values:
mbed_official 146:f64d43ff0c18 706 * - 00 - Core/system clock.
mbed_official 146:f64d43ff0c18 707 * - 01 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by
mbed_official 146:f64d43ff0c18 708 * SOPT2[PLLFLLSEL].
mbed_official 146:f64d43ff0c18 709 * - 10 - OSCERCLK clock
mbed_official 146:f64d43ff0c18 710 * - 11 - External bypass clock (ENET_1588_CLKIN).
mbed_official 146:f64d43ff0c18 711 */
mbed_official 146:f64d43ff0c18 712 //@{
mbed_official 146:f64d43ff0c18 713 #define BP_SIM_SOPT2_TIMESRC (20U) //!< Bit position for SIM_SOPT2_TIMESRC.
mbed_official 146:f64d43ff0c18 714 #define BM_SIM_SOPT2_TIMESRC (0x00300000U) //!< Bit mask for SIM_SOPT2_TIMESRC.
mbed_official 146:f64d43ff0c18 715 #define BS_SIM_SOPT2_TIMESRC (2U) //!< Bit field size in bits for SIM_SOPT2_TIMESRC.
mbed_official 146:f64d43ff0c18 716
mbed_official 146:f64d43ff0c18 717 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 718 //! @brief Read current value of the SIM_SOPT2_TIMESRC field.
mbed_official 146:f64d43ff0c18 719 #define BR_SIM_SOPT2_TIMESRC (HW_SIM_SOPT2.B.TIMESRC)
mbed_official 146:f64d43ff0c18 720 #endif
mbed_official 146:f64d43ff0c18 721
mbed_official 146:f64d43ff0c18 722 //! @brief Format value for bitfield SIM_SOPT2_TIMESRC.
mbed_official 146:f64d43ff0c18 723 #define BF_SIM_SOPT2_TIMESRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_TIMESRC), uint32_t) & BM_SIM_SOPT2_TIMESRC)
mbed_official 146:f64d43ff0c18 724
mbed_official 146:f64d43ff0c18 725 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 726 //! @brief Set the TIMESRC field to a new value.
mbed_official 146:f64d43ff0c18 727 #define BW_SIM_SOPT2_TIMESRC(v) (HW_SIM_SOPT2_WR((HW_SIM_SOPT2_RD() & ~BM_SIM_SOPT2_TIMESRC) | BF_SIM_SOPT2_TIMESRC(v)))
mbed_official 146:f64d43ff0c18 728 #endif
mbed_official 146:f64d43ff0c18 729 //@}
mbed_official 146:f64d43ff0c18 730
mbed_official 146:f64d43ff0c18 731 /*!
mbed_official 146:f64d43ff0c18 732 * @name Register SIM_SOPT2, field SDHCSRC[29:28] (RW)
mbed_official 146:f64d43ff0c18 733 *
mbed_official 146:f64d43ff0c18 734 * Selects the clock source for the SDHC clock .
mbed_official 146:f64d43ff0c18 735 *
mbed_official 146:f64d43ff0c18 736 * Values:
mbed_official 146:f64d43ff0c18 737 * - 00 - Core/system clock.
mbed_official 146:f64d43ff0c18 738 * - 01 - MCGFLLCLK, or MCGPLLCLK , or IRC48M clock as selected by
mbed_official 146:f64d43ff0c18 739 * SOPT2[PLLFLLSEL].
mbed_official 146:f64d43ff0c18 740 * - 10 - OSCERCLK clock
mbed_official 146:f64d43ff0c18 741 * - 11 - External bypass clock (SDHC0_CLKIN)
mbed_official 146:f64d43ff0c18 742 */
mbed_official 146:f64d43ff0c18 743 //@{
mbed_official 146:f64d43ff0c18 744 #define BP_SIM_SOPT2_SDHCSRC (28U) //!< Bit position for SIM_SOPT2_SDHCSRC.
mbed_official 146:f64d43ff0c18 745 #define BM_SIM_SOPT2_SDHCSRC (0x30000000U) //!< Bit mask for SIM_SOPT2_SDHCSRC.
mbed_official 146:f64d43ff0c18 746 #define BS_SIM_SOPT2_SDHCSRC (2U) //!< Bit field size in bits for SIM_SOPT2_SDHCSRC.
mbed_official 146:f64d43ff0c18 747
mbed_official 146:f64d43ff0c18 748 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 749 //! @brief Read current value of the SIM_SOPT2_SDHCSRC field.
mbed_official 146:f64d43ff0c18 750 #define BR_SIM_SOPT2_SDHCSRC (HW_SIM_SOPT2.B.SDHCSRC)
mbed_official 146:f64d43ff0c18 751 #endif
mbed_official 146:f64d43ff0c18 752
mbed_official 146:f64d43ff0c18 753 //! @brief Format value for bitfield SIM_SOPT2_SDHCSRC.
mbed_official 146:f64d43ff0c18 754 #define BF_SIM_SOPT2_SDHCSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_SDHCSRC), uint32_t) & BM_SIM_SOPT2_SDHCSRC)
mbed_official 146:f64d43ff0c18 755
mbed_official 146:f64d43ff0c18 756 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 757 //! @brief Set the SDHCSRC field to a new value.
mbed_official 146:f64d43ff0c18 758 #define BW_SIM_SOPT2_SDHCSRC(v) (HW_SIM_SOPT2_WR((HW_SIM_SOPT2_RD() & ~BM_SIM_SOPT2_SDHCSRC) | BF_SIM_SOPT2_SDHCSRC(v)))
mbed_official 146:f64d43ff0c18 759 #endif
mbed_official 146:f64d43ff0c18 760 //@}
mbed_official 146:f64d43ff0c18 761
mbed_official 146:f64d43ff0c18 762 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 763 // HW_SIM_SOPT4 - System Options Register 4
mbed_official 146:f64d43ff0c18 764 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 765
mbed_official 146:f64d43ff0c18 766 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 767 /*!
mbed_official 146:f64d43ff0c18 768 * @brief HW_SIM_SOPT4 - System Options Register 4 (RW)
mbed_official 146:f64d43ff0c18 769 *
mbed_official 146:f64d43ff0c18 770 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 771 */
mbed_official 146:f64d43ff0c18 772 typedef union _hw_sim_sopt4
mbed_official 146:f64d43ff0c18 773 {
mbed_official 146:f64d43ff0c18 774 uint32_t U;
mbed_official 146:f64d43ff0c18 775 struct _hw_sim_sopt4_bitfields
mbed_official 146:f64d43ff0c18 776 {
mbed_official 146:f64d43ff0c18 777 uint32_t FTM0FLT0 : 1; //!< [0] FTM0 Fault 0 Select
mbed_official 146:f64d43ff0c18 778 uint32_t FTM0FLT1 : 1; //!< [1] FTM0 Fault 1 Select
mbed_official 146:f64d43ff0c18 779 uint32_t FTM0FLT2 : 1; //!< [2] FTM0 Fault 2 Select
mbed_official 146:f64d43ff0c18 780 uint32_t RESERVED0 : 1; //!< [3]
mbed_official 146:f64d43ff0c18 781 uint32_t FTM1FLT0 : 1; //!< [4] FTM1 Fault 0 Select
mbed_official 146:f64d43ff0c18 782 uint32_t RESERVED1 : 3; //!< [7:5]
mbed_official 146:f64d43ff0c18 783 uint32_t FTM2FLT0 : 1; //!< [8] FTM2 Fault 0 Select
mbed_official 146:f64d43ff0c18 784 uint32_t RESERVED2 : 3; //!< [11:9]
mbed_official 146:f64d43ff0c18 785 uint32_t FTM3FLT0 : 1; //!< [12] FTM3 Fault 0 Select
mbed_official 146:f64d43ff0c18 786 uint32_t RESERVED3 : 5; //!< [17:13]
mbed_official 146:f64d43ff0c18 787 uint32_t FTM1CH0SRC : 2; //!< [19:18] FTM1 channel 0 input capture
mbed_official 146:f64d43ff0c18 788 //! source select
mbed_official 146:f64d43ff0c18 789 uint32_t FTM2CH0SRC : 2; //!< [21:20] FTM2 channel 0 input capture
mbed_official 146:f64d43ff0c18 790 //! source select
mbed_official 146:f64d43ff0c18 791 uint32_t RESERVED4 : 2; //!< [23:22]
mbed_official 146:f64d43ff0c18 792 uint32_t FTM0CLKSEL : 1; //!< [24] FlexTimer 0 External Clock Pin
mbed_official 146:f64d43ff0c18 793 //! Select
mbed_official 146:f64d43ff0c18 794 uint32_t FTM1CLKSEL : 1; //!< [25] FTM1 External Clock Pin Select
mbed_official 146:f64d43ff0c18 795 uint32_t FTM2CLKSEL : 1; //!< [26] FlexTimer 2 External Clock Pin
mbed_official 146:f64d43ff0c18 796 //! Select
mbed_official 146:f64d43ff0c18 797 uint32_t FTM3CLKSEL : 1; //!< [27] FlexTimer 3 External Clock Pin
mbed_official 146:f64d43ff0c18 798 //! Select
mbed_official 146:f64d43ff0c18 799 uint32_t FTM0TRG0SRC : 1; //!< [28] FlexTimer 0 Hardware Trigger 0
mbed_official 146:f64d43ff0c18 800 //! Source Select
mbed_official 146:f64d43ff0c18 801 uint32_t FTM0TRG1SRC : 1; //!< [29] FlexTimer 0 Hardware Trigger 1
mbed_official 146:f64d43ff0c18 802 //! Source Select
mbed_official 146:f64d43ff0c18 803 uint32_t FTM3TRG0SRC : 1; //!< [30] FlexTimer 3 Hardware Trigger 0
mbed_official 146:f64d43ff0c18 804 //! Source Select
mbed_official 146:f64d43ff0c18 805 uint32_t FTM3TRG1SRC : 1; //!< [31] FlexTimer 3 Hardware Trigger 1
mbed_official 146:f64d43ff0c18 806 //! Source Select
mbed_official 146:f64d43ff0c18 807 } B;
mbed_official 146:f64d43ff0c18 808 } hw_sim_sopt4_t;
mbed_official 146:f64d43ff0c18 809 #endif
mbed_official 146:f64d43ff0c18 810
mbed_official 146:f64d43ff0c18 811 /*!
mbed_official 146:f64d43ff0c18 812 * @name Constants and macros for entire SIM_SOPT4 register
mbed_official 146:f64d43ff0c18 813 */
mbed_official 146:f64d43ff0c18 814 //@{
mbed_official 146:f64d43ff0c18 815 #define HW_SIM_SOPT4_ADDR (REGS_SIM_BASE + 0x100CU)
mbed_official 146:f64d43ff0c18 816
mbed_official 146:f64d43ff0c18 817 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 818 #define HW_SIM_SOPT4 (*(__IO hw_sim_sopt4_t *) HW_SIM_SOPT4_ADDR)
mbed_official 146:f64d43ff0c18 819 #define HW_SIM_SOPT4_RD() (HW_SIM_SOPT4.U)
mbed_official 146:f64d43ff0c18 820 #define HW_SIM_SOPT4_WR(v) (HW_SIM_SOPT4.U = (v))
mbed_official 146:f64d43ff0c18 821 #define HW_SIM_SOPT4_SET(v) (HW_SIM_SOPT4_WR(HW_SIM_SOPT4_RD() | (v)))
mbed_official 146:f64d43ff0c18 822 #define HW_SIM_SOPT4_CLR(v) (HW_SIM_SOPT4_WR(HW_SIM_SOPT4_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 823 #define HW_SIM_SOPT4_TOG(v) (HW_SIM_SOPT4_WR(HW_SIM_SOPT4_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 824 #endif
mbed_official 146:f64d43ff0c18 825 //@}
mbed_official 146:f64d43ff0c18 826
mbed_official 146:f64d43ff0c18 827 /*
mbed_official 146:f64d43ff0c18 828 * Constants & macros for individual SIM_SOPT4 bitfields
mbed_official 146:f64d43ff0c18 829 */
mbed_official 146:f64d43ff0c18 830
mbed_official 146:f64d43ff0c18 831 /*!
mbed_official 146:f64d43ff0c18 832 * @name Register SIM_SOPT4, field FTM0FLT0[0] (RW)
mbed_official 146:f64d43ff0c18 833 *
mbed_official 146:f64d43ff0c18 834 * Selects the source of FTM0 fault 0. The pin source for fault 0 must be
mbed_official 146:f64d43ff0c18 835 * configured for the FTM module fault function through the appropriate pin control
mbed_official 146:f64d43ff0c18 836 * register in the port control module.
mbed_official 146:f64d43ff0c18 837 *
mbed_official 146:f64d43ff0c18 838 * Values:
mbed_official 146:f64d43ff0c18 839 * - 0 - FTM0_FLT0 pin
mbed_official 146:f64d43ff0c18 840 * - 1 - CMP0 out
mbed_official 146:f64d43ff0c18 841 */
mbed_official 146:f64d43ff0c18 842 //@{
mbed_official 146:f64d43ff0c18 843 #define BP_SIM_SOPT4_FTM0FLT0 (0U) //!< Bit position for SIM_SOPT4_FTM0FLT0.
mbed_official 146:f64d43ff0c18 844 #define BM_SIM_SOPT4_FTM0FLT0 (0x00000001U) //!< Bit mask for SIM_SOPT4_FTM0FLT0.
mbed_official 146:f64d43ff0c18 845 #define BS_SIM_SOPT4_FTM0FLT0 (1U) //!< Bit field size in bits for SIM_SOPT4_FTM0FLT0.
mbed_official 146:f64d43ff0c18 846
mbed_official 146:f64d43ff0c18 847 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 848 //! @brief Read current value of the SIM_SOPT4_FTM0FLT0 field.
mbed_official 146:f64d43ff0c18 849 #define BR_SIM_SOPT4_FTM0FLT0 (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0FLT0))
mbed_official 146:f64d43ff0c18 850 #endif
mbed_official 146:f64d43ff0c18 851
mbed_official 146:f64d43ff0c18 852 //! @brief Format value for bitfield SIM_SOPT4_FTM0FLT0.
mbed_official 146:f64d43ff0c18 853 #define BF_SIM_SOPT4_FTM0FLT0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM0FLT0), uint32_t) & BM_SIM_SOPT4_FTM0FLT0)
mbed_official 146:f64d43ff0c18 854
mbed_official 146:f64d43ff0c18 855 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 856 //! @brief Set the FTM0FLT0 field to a new value.
mbed_official 146:f64d43ff0c18 857 #define BW_SIM_SOPT4_FTM0FLT0(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0FLT0) = (v))
mbed_official 146:f64d43ff0c18 858 #endif
mbed_official 146:f64d43ff0c18 859 //@}
mbed_official 146:f64d43ff0c18 860
mbed_official 146:f64d43ff0c18 861 /*!
mbed_official 146:f64d43ff0c18 862 * @name Register SIM_SOPT4, field FTM0FLT1[1] (RW)
mbed_official 146:f64d43ff0c18 863 *
mbed_official 146:f64d43ff0c18 864 * Selects the source of FTM0 fault 1. The pin source for fault 1 must be
mbed_official 146:f64d43ff0c18 865 * configured for the FTM module fault function through the appropriate pin control
mbed_official 146:f64d43ff0c18 866 * register in the port control module.
mbed_official 146:f64d43ff0c18 867 *
mbed_official 146:f64d43ff0c18 868 * Values:
mbed_official 146:f64d43ff0c18 869 * - 0 - FTM0_FLT1 pin
mbed_official 146:f64d43ff0c18 870 * - 1 - CMP1 out
mbed_official 146:f64d43ff0c18 871 */
mbed_official 146:f64d43ff0c18 872 //@{
mbed_official 146:f64d43ff0c18 873 #define BP_SIM_SOPT4_FTM0FLT1 (1U) //!< Bit position for SIM_SOPT4_FTM0FLT1.
mbed_official 146:f64d43ff0c18 874 #define BM_SIM_SOPT4_FTM0FLT1 (0x00000002U) //!< Bit mask for SIM_SOPT4_FTM0FLT1.
mbed_official 146:f64d43ff0c18 875 #define BS_SIM_SOPT4_FTM0FLT1 (1U) //!< Bit field size in bits for SIM_SOPT4_FTM0FLT1.
mbed_official 146:f64d43ff0c18 876
mbed_official 146:f64d43ff0c18 877 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 878 //! @brief Read current value of the SIM_SOPT4_FTM0FLT1 field.
mbed_official 146:f64d43ff0c18 879 #define BR_SIM_SOPT4_FTM0FLT1 (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0FLT1))
mbed_official 146:f64d43ff0c18 880 #endif
mbed_official 146:f64d43ff0c18 881
mbed_official 146:f64d43ff0c18 882 //! @brief Format value for bitfield SIM_SOPT4_FTM0FLT1.
mbed_official 146:f64d43ff0c18 883 #define BF_SIM_SOPT4_FTM0FLT1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM0FLT1), uint32_t) & BM_SIM_SOPT4_FTM0FLT1)
mbed_official 146:f64d43ff0c18 884
mbed_official 146:f64d43ff0c18 885 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 886 //! @brief Set the FTM0FLT1 field to a new value.
mbed_official 146:f64d43ff0c18 887 #define BW_SIM_SOPT4_FTM0FLT1(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0FLT1) = (v))
mbed_official 146:f64d43ff0c18 888 #endif
mbed_official 146:f64d43ff0c18 889 //@}
mbed_official 146:f64d43ff0c18 890
mbed_official 146:f64d43ff0c18 891 /*!
mbed_official 146:f64d43ff0c18 892 * @name Register SIM_SOPT4, field FTM0FLT2[2] (RW)
mbed_official 146:f64d43ff0c18 893 *
mbed_official 146:f64d43ff0c18 894 * Selects the source of FTM0 fault 2. The pin source for fault 2 must be
mbed_official 146:f64d43ff0c18 895 * configured for the FTM module fault function through the appropriate pin control
mbed_official 146:f64d43ff0c18 896 * register in the port control module.
mbed_official 146:f64d43ff0c18 897 *
mbed_official 146:f64d43ff0c18 898 * Values:
mbed_official 146:f64d43ff0c18 899 * - 0 - FTM0_FLT2 pin
mbed_official 146:f64d43ff0c18 900 * - 1 - CMP2 out
mbed_official 146:f64d43ff0c18 901 */
mbed_official 146:f64d43ff0c18 902 //@{
mbed_official 146:f64d43ff0c18 903 #define BP_SIM_SOPT4_FTM0FLT2 (2U) //!< Bit position for SIM_SOPT4_FTM0FLT2.
mbed_official 146:f64d43ff0c18 904 #define BM_SIM_SOPT4_FTM0FLT2 (0x00000004U) //!< Bit mask for SIM_SOPT4_FTM0FLT2.
mbed_official 146:f64d43ff0c18 905 #define BS_SIM_SOPT4_FTM0FLT2 (1U) //!< Bit field size in bits for SIM_SOPT4_FTM0FLT2.
mbed_official 146:f64d43ff0c18 906
mbed_official 146:f64d43ff0c18 907 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 908 //! @brief Read current value of the SIM_SOPT4_FTM0FLT2 field.
mbed_official 146:f64d43ff0c18 909 #define BR_SIM_SOPT4_FTM0FLT2 (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0FLT2))
mbed_official 146:f64d43ff0c18 910 #endif
mbed_official 146:f64d43ff0c18 911
mbed_official 146:f64d43ff0c18 912 //! @brief Format value for bitfield SIM_SOPT4_FTM0FLT2.
mbed_official 146:f64d43ff0c18 913 #define BF_SIM_SOPT4_FTM0FLT2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM0FLT2), uint32_t) & BM_SIM_SOPT4_FTM0FLT2)
mbed_official 146:f64d43ff0c18 914
mbed_official 146:f64d43ff0c18 915 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 916 //! @brief Set the FTM0FLT2 field to a new value.
mbed_official 146:f64d43ff0c18 917 #define BW_SIM_SOPT4_FTM0FLT2(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0FLT2) = (v))
mbed_official 146:f64d43ff0c18 918 #endif
mbed_official 146:f64d43ff0c18 919 //@}
mbed_official 146:f64d43ff0c18 920
mbed_official 146:f64d43ff0c18 921 /*!
mbed_official 146:f64d43ff0c18 922 * @name Register SIM_SOPT4, field FTM1FLT0[4] (RW)
mbed_official 146:f64d43ff0c18 923 *
mbed_official 146:f64d43ff0c18 924 * Selects the source of FTM1 fault 0. The pin source for fault 0 must be
mbed_official 146:f64d43ff0c18 925 * configured for the FTM module fault function through the appropriate pin control
mbed_official 146:f64d43ff0c18 926 * register in the port control module.
mbed_official 146:f64d43ff0c18 927 *
mbed_official 146:f64d43ff0c18 928 * Values:
mbed_official 146:f64d43ff0c18 929 * - 0 - FTM1_FLT0 pin
mbed_official 146:f64d43ff0c18 930 * - 1 - CMP0 out
mbed_official 146:f64d43ff0c18 931 */
mbed_official 146:f64d43ff0c18 932 //@{
mbed_official 146:f64d43ff0c18 933 #define BP_SIM_SOPT4_FTM1FLT0 (4U) //!< Bit position for SIM_SOPT4_FTM1FLT0.
mbed_official 146:f64d43ff0c18 934 #define BM_SIM_SOPT4_FTM1FLT0 (0x00000010U) //!< Bit mask for SIM_SOPT4_FTM1FLT0.
mbed_official 146:f64d43ff0c18 935 #define BS_SIM_SOPT4_FTM1FLT0 (1U) //!< Bit field size in bits for SIM_SOPT4_FTM1FLT0.
mbed_official 146:f64d43ff0c18 936
mbed_official 146:f64d43ff0c18 937 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 938 //! @brief Read current value of the SIM_SOPT4_FTM1FLT0 field.
mbed_official 146:f64d43ff0c18 939 #define BR_SIM_SOPT4_FTM1FLT0 (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM1FLT0))
mbed_official 146:f64d43ff0c18 940 #endif
mbed_official 146:f64d43ff0c18 941
mbed_official 146:f64d43ff0c18 942 //! @brief Format value for bitfield SIM_SOPT4_FTM1FLT0.
mbed_official 146:f64d43ff0c18 943 #define BF_SIM_SOPT4_FTM1FLT0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM1FLT0), uint32_t) & BM_SIM_SOPT4_FTM1FLT0)
mbed_official 146:f64d43ff0c18 944
mbed_official 146:f64d43ff0c18 945 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 946 //! @brief Set the FTM1FLT0 field to a new value.
mbed_official 146:f64d43ff0c18 947 #define BW_SIM_SOPT4_FTM1FLT0(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM1FLT0) = (v))
mbed_official 146:f64d43ff0c18 948 #endif
mbed_official 146:f64d43ff0c18 949 //@}
mbed_official 146:f64d43ff0c18 950
mbed_official 146:f64d43ff0c18 951 /*!
mbed_official 146:f64d43ff0c18 952 * @name Register SIM_SOPT4, field FTM2FLT0[8] (RW)
mbed_official 146:f64d43ff0c18 953 *
mbed_official 146:f64d43ff0c18 954 * Selects the source of FTM2 fault 0. The pin source for fault 0 must be
mbed_official 146:f64d43ff0c18 955 * configured for the FTM module fault function through the appropriate PORTx pin
mbed_official 146:f64d43ff0c18 956 * control register.
mbed_official 146:f64d43ff0c18 957 *
mbed_official 146:f64d43ff0c18 958 * Values:
mbed_official 146:f64d43ff0c18 959 * - 0 - FTM2_FLT0 pin
mbed_official 146:f64d43ff0c18 960 * - 1 - CMP0 out
mbed_official 146:f64d43ff0c18 961 */
mbed_official 146:f64d43ff0c18 962 //@{
mbed_official 146:f64d43ff0c18 963 #define BP_SIM_SOPT4_FTM2FLT0 (8U) //!< Bit position for SIM_SOPT4_FTM2FLT0.
mbed_official 146:f64d43ff0c18 964 #define BM_SIM_SOPT4_FTM2FLT0 (0x00000100U) //!< Bit mask for SIM_SOPT4_FTM2FLT0.
mbed_official 146:f64d43ff0c18 965 #define BS_SIM_SOPT4_FTM2FLT0 (1U) //!< Bit field size in bits for SIM_SOPT4_FTM2FLT0.
mbed_official 146:f64d43ff0c18 966
mbed_official 146:f64d43ff0c18 967 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 968 //! @brief Read current value of the SIM_SOPT4_FTM2FLT0 field.
mbed_official 146:f64d43ff0c18 969 #define BR_SIM_SOPT4_FTM2FLT0 (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM2FLT0))
mbed_official 146:f64d43ff0c18 970 #endif
mbed_official 146:f64d43ff0c18 971
mbed_official 146:f64d43ff0c18 972 //! @brief Format value for bitfield SIM_SOPT4_FTM2FLT0.
mbed_official 146:f64d43ff0c18 973 #define BF_SIM_SOPT4_FTM2FLT0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM2FLT0), uint32_t) & BM_SIM_SOPT4_FTM2FLT0)
mbed_official 146:f64d43ff0c18 974
mbed_official 146:f64d43ff0c18 975 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 976 //! @brief Set the FTM2FLT0 field to a new value.
mbed_official 146:f64d43ff0c18 977 #define BW_SIM_SOPT4_FTM2FLT0(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM2FLT0) = (v))
mbed_official 146:f64d43ff0c18 978 #endif
mbed_official 146:f64d43ff0c18 979 //@}
mbed_official 146:f64d43ff0c18 980
mbed_official 146:f64d43ff0c18 981 /*!
mbed_official 146:f64d43ff0c18 982 * @name Register SIM_SOPT4, field FTM3FLT0[12] (RW)
mbed_official 146:f64d43ff0c18 983 *
mbed_official 146:f64d43ff0c18 984 * Selects the source of FTM3 fault 0. The pin source for fault 0 must be
mbed_official 146:f64d43ff0c18 985 * configured for the FTM module fault function through the appropriate PORTx pin
mbed_official 146:f64d43ff0c18 986 * control register.
mbed_official 146:f64d43ff0c18 987 *
mbed_official 146:f64d43ff0c18 988 * Values:
mbed_official 146:f64d43ff0c18 989 * - 0 - FTM3_FLT0 pin
mbed_official 146:f64d43ff0c18 990 * - 1 - CMP0 out
mbed_official 146:f64d43ff0c18 991 */
mbed_official 146:f64d43ff0c18 992 //@{
mbed_official 146:f64d43ff0c18 993 #define BP_SIM_SOPT4_FTM3FLT0 (12U) //!< Bit position for SIM_SOPT4_FTM3FLT0.
mbed_official 146:f64d43ff0c18 994 #define BM_SIM_SOPT4_FTM3FLT0 (0x00001000U) //!< Bit mask for SIM_SOPT4_FTM3FLT0.
mbed_official 146:f64d43ff0c18 995 #define BS_SIM_SOPT4_FTM3FLT0 (1U) //!< Bit field size in bits for SIM_SOPT4_FTM3FLT0.
mbed_official 146:f64d43ff0c18 996
mbed_official 146:f64d43ff0c18 997 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 998 //! @brief Read current value of the SIM_SOPT4_FTM3FLT0 field.
mbed_official 146:f64d43ff0c18 999 #define BR_SIM_SOPT4_FTM3FLT0 (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3FLT0))
mbed_official 146:f64d43ff0c18 1000 #endif
mbed_official 146:f64d43ff0c18 1001
mbed_official 146:f64d43ff0c18 1002 //! @brief Format value for bitfield SIM_SOPT4_FTM3FLT0.
mbed_official 146:f64d43ff0c18 1003 #define BF_SIM_SOPT4_FTM3FLT0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM3FLT0), uint32_t) & BM_SIM_SOPT4_FTM3FLT0)
mbed_official 146:f64d43ff0c18 1004
mbed_official 146:f64d43ff0c18 1005 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1006 //! @brief Set the FTM3FLT0 field to a new value.
mbed_official 146:f64d43ff0c18 1007 #define BW_SIM_SOPT4_FTM3FLT0(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3FLT0) = (v))
mbed_official 146:f64d43ff0c18 1008 #endif
mbed_official 146:f64d43ff0c18 1009 //@}
mbed_official 146:f64d43ff0c18 1010
mbed_official 146:f64d43ff0c18 1011 /*!
mbed_official 146:f64d43ff0c18 1012 * @name Register SIM_SOPT4, field FTM1CH0SRC[19:18] (RW)
mbed_official 146:f64d43ff0c18 1013 *
mbed_official 146:f64d43ff0c18 1014 * Selects the source for FTM1 channel 0 input capture. When the FTM is not in
mbed_official 146:f64d43ff0c18 1015 * input capture mode, clear this field.
mbed_official 146:f64d43ff0c18 1016 *
mbed_official 146:f64d43ff0c18 1017 * Values:
mbed_official 146:f64d43ff0c18 1018 * - 00 - FTM1_CH0 signal
mbed_official 146:f64d43ff0c18 1019 * - 01 - CMP0 output
mbed_official 146:f64d43ff0c18 1020 * - 10 - CMP1 output
mbed_official 146:f64d43ff0c18 1021 * - 11 - USB start of frame pulse
mbed_official 146:f64d43ff0c18 1022 */
mbed_official 146:f64d43ff0c18 1023 //@{
mbed_official 146:f64d43ff0c18 1024 #define BP_SIM_SOPT4_FTM1CH0SRC (18U) //!< Bit position for SIM_SOPT4_FTM1CH0SRC.
mbed_official 146:f64d43ff0c18 1025 #define BM_SIM_SOPT4_FTM1CH0SRC (0x000C0000U) //!< Bit mask for SIM_SOPT4_FTM1CH0SRC.
mbed_official 146:f64d43ff0c18 1026 #define BS_SIM_SOPT4_FTM1CH0SRC (2U) //!< Bit field size in bits for SIM_SOPT4_FTM1CH0SRC.
mbed_official 146:f64d43ff0c18 1027
mbed_official 146:f64d43ff0c18 1028 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1029 //! @brief Read current value of the SIM_SOPT4_FTM1CH0SRC field.
mbed_official 146:f64d43ff0c18 1030 #define BR_SIM_SOPT4_FTM1CH0SRC (HW_SIM_SOPT4.B.FTM1CH0SRC)
mbed_official 146:f64d43ff0c18 1031 #endif
mbed_official 146:f64d43ff0c18 1032
mbed_official 146:f64d43ff0c18 1033 //! @brief Format value for bitfield SIM_SOPT4_FTM1CH0SRC.
mbed_official 146:f64d43ff0c18 1034 #define BF_SIM_SOPT4_FTM1CH0SRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM1CH0SRC), uint32_t) & BM_SIM_SOPT4_FTM1CH0SRC)
mbed_official 146:f64d43ff0c18 1035
mbed_official 146:f64d43ff0c18 1036 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1037 //! @brief Set the FTM1CH0SRC field to a new value.
mbed_official 146:f64d43ff0c18 1038 #define BW_SIM_SOPT4_FTM1CH0SRC(v) (HW_SIM_SOPT4_WR((HW_SIM_SOPT4_RD() & ~BM_SIM_SOPT4_FTM1CH0SRC) | BF_SIM_SOPT4_FTM1CH0SRC(v)))
mbed_official 146:f64d43ff0c18 1039 #endif
mbed_official 146:f64d43ff0c18 1040 //@}
mbed_official 146:f64d43ff0c18 1041
mbed_official 146:f64d43ff0c18 1042 /*!
mbed_official 146:f64d43ff0c18 1043 * @name Register SIM_SOPT4, field FTM2CH0SRC[21:20] (RW)
mbed_official 146:f64d43ff0c18 1044 *
mbed_official 146:f64d43ff0c18 1045 * Selects the source for FTM2 channel 0 input capture. When the FTM is not in
mbed_official 146:f64d43ff0c18 1046 * input capture mode, clear this field.
mbed_official 146:f64d43ff0c18 1047 *
mbed_official 146:f64d43ff0c18 1048 * Values:
mbed_official 146:f64d43ff0c18 1049 * - 00 - FTM2_CH0 signal
mbed_official 146:f64d43ff0c18 1050 * - 01 - CMP0 output
mbed_official 146:f64d43ff0c18 1051 * - 10 - CMP1 output
mbed_official 146:f64d43ff0c18 1052 * - 11 - Reserved
mbed_official 146:f64d43ff0c18 1053 */
mbed_official 146:f64d43ff0c18 1054 //@{
mbed_official 146:f64d43ff0c18 1055 #define BP_SIM_SOPT4_FTM2CH0SRC (20U) //!< Bit position for SIM_SOPT4_FTM2CH0SRC.
mbed_official 146:f64d43ff0c18 1056 #define BM_SIM_SOPT4_FTM2CH0SRC (0x00300000U) //!< Bit mask for SIM_SOPT4_FTM2CH0SRC.
mbed_official 146:f64d43ff0c18 1057 #define BS_SIM_SOPT4_FTM2CH0SRC (2U) //!< Bit field size in bits for SIM_SOPT4_FTM2CH0SRC.
mbed_official 146:f64d43ff0c18 1058
mbed_official 146:f64d43ff0c18 1059 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1060 //! @brief Read current value of the SIM_SOPT4_FTM2CH0SRC field.
mbed_official 146:f64d43ff0c18 1061 #define BR_SIM_SOPT4_FTM2CH0SRC (HW_SIM_SOPT4.B.FTM2CH0SRC)
mbed_official 146:f64d43ff0c18 1062 #endif
mbed_official 146:f64d43ff0c18 1063
mbed_official 146:f64d43ff0c18 1064 //! @brief Format value for bitfield SIM_SOPT4_FTM2CH0SRC.
mbed_official 146:f64d43ff0c18 1065 #define BF_SIM_SOPT4_FTM2CH0SRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM2CH0SRC), uint32_t) & BM_SIM_SOPT4_FTM2CH0SRC)
mbed_official 146:f64d43ff0c18 1066
mbed_official 146:f64d43ff0c18 1067 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1068 //! @brief Set the FTM2CH0SRC field to a new value.
mbed_official 146:f64d43ff0c18 1069 #define BW_SIM_SOPT4_FTM2CH0SRC(v) (HW_SIM_SOPT4_WR((HW_SIM_SOPT4_RD() & ~BM_SIM_SOPT4_FTM2CH0SRC) | BF_SIM_SOPT4_FTM2CH0SRC(v)))
mbed_official 146:f64d43ff0c18 1070 #endif
mbed_official 146:f64d43ff0c18 1071 //@}
mbed_official 146:f64d43ff0c18 1072
mbed_official 146:f64d43ff0c18 1073 /*!
mbed_official 146:f64d43ff0c18 1074 * @name Register SIM_SOPT4, field FTM0CLKSEL[24] (RW)
mbed_official 146:f64d43ff0c18 1075 *
mbed_official 146:f64d43ff0c18 1076 * Selects the external pin used to drive the clock to the FTM0 module. The
mbed_official 146:f64d43ff0c18 1077 * selected pin must also be configured for the FTM external clock function through
mbed_official 146:f64d43ff0c18 1078 * the appropriate pin control register in the port control module.
mbed_official 146:f64d43ff0c18 1079 *
mbed_official 146:f64d43ff0c18 1080 * Values:
mbed_official 146:f64d43ff0c18 1081 * - 0 - FTM_CLK0 pin
mbed_official 146:f64d43ff0c18 1082 * - 1 - FTM_CLK1 pin
mbed_official 146:f64d43ff0c18 1083 */
mbed_official 146:f64d43ff0c18 1084 //@{
mbed_official 146:f64d43ff0c18 1085 #define BP_SIM_SOPT4_FTM0CLKSEL (24U) //!< Bit position for SIM_SOPT4_FTM0CLKSEL.
mbed_official 146:f64d43ff0c18 1086 #define BM_SIM_SOPT4_FTM0CLKSEL (0x01000000U) //!< Bit mask for SIM_SOPT4_FTM0CLKSEL.
mbed_official 146:f64d43ff0c18 1087 #define BS_SIM_SOPT4_FTM0CLKSEL (1U) //!< Bit field size in bits for SIM_SOPT4_FTM0CLKSEL.
mbed_official 146:f64d43ff0c18 1088
mbed_official 146:f64d43ff0c18 1089 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1090 //! @brief Read current value of the SIM_SOPT4_FTM0CLKSEL field.
mbed_official 146:f64d43ff0c18 1091 #define BR_SIM_SOPT4_FTM0CLKSEL (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0CLKSEL))
mbed_official 146:f64d43ff0c18 1092 #endif
mbed_official 146:f64d43ff0c18 1093
mbed_official 146:f64d43ff0c18 1094 //! @brief Format value for bitfield SIM_SOPT4_FTM0CLKSEL.
mbed_official 146:f64d43ff0c18 1095 #define BF_SIM_SOPT4_FTM0CLKSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM0CLKSEL), uint32_t) & BM_SIM_SOPT4_FTM0CLKSEL)
mbed_official 146:f64d43ff0c18 1096
mbed_official 146:f64d43ff0c18 1097 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1098 //! @brief Set the FTM0CLKSEL field to a new value.
mbed_official 146:f64d43ff0c18 1099 #define BW_SIM_SOPT4_FTM0CLKSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0CLKSEL) = (v))
mbed_official 146:f64d43ff0c18 1100 #endif
mbed_official 146:f64d43ff0c18 1101 //@}
mbed_official 146:f64d43ff0c18 1102
mbed_official 146:f64d43ff0c18 1103 /*!
mbed_official 146:f64d43ff0c18 1104 * @name Register SIM_SOPT4, field FTM1CLKSEL[25] (RW)
mbed_official 146:f64d43ff0c18 1105 *
mbed_official 146:f64d43ff0c18 1106 * Selects the external pin used to drive the clock to the FTM1 module. The
mbed_official 146:f64d43ff0c18 1107 * selected pin must also be configured for the FTM external clock function through
mbed_official 146:f64d43ff0c18 1108 * the appropriate pin control register in the port control module.
mbed_official 146:f64d43ff0c18 1109 *
mbed_official 146:f64d43ff0c18 1110 * Values:
mbed_official 146:f64d43ff0c18 1111 * - 0 - FTM_CLK0 pin
mbed_official 146:f64d43ff0c18 1112 * - 1 - FTM_CLK1 pin
mbed_official 146:f64d43ff0c18 1113 */
mbed_official 146:f64d43ff0c18 1114 //@{
mbed_official 146:f64d43ff0c18 1115 #define BP_SIM_SOPT4_FTM1CLKSEL (25U) //!< Bit position for SIM_SOPT4_FTM1CLKSEL.
mbed_official 146:f64d43ff0c18 1116 #define BM_SIM_SOPT4_FTM1CLKSEL (0x02000000U) //!< Bit mask for SIM_SOPT4_FTM1CLKSEL.
mbed_official 146:f64d43ff0c18 1117 #define BS_SIM_SOPT4_FTM1CLKSEL (1U) //!< Bit field size in bits for SIM_SOPT4_FTM1CLKSEL.
mbed_official 146:f64d43ff0c18 1118
mbed_official 146:f64d43ff0c18 1119 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1120 //! @brief Read current value of the SIM_SOPT4_FTM1CLKSEL field.
mbed_official 146:f64d43ff0c18 1121 #define BR_SIM_SOPT4_FTM1CLKSEL (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM1CLKSEL))
mbed_official 146:f64d43ff0c18 1122 #endif
mbed_official 146:f64d43ff0c18 1123
mbed_official 146:f64d43ff0c18 1124 //! @brief Format value for bitfield SIM_SOPT4_FTM1CLKSEL.
mbed_official 146:f64d43ff0c18 1125 #define BF_SIM_SOPT4_FTM1CLKSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM1CLKSEL), uint32_t) & BM_SIM_SOPT4_FTM1CLKSEL)
mbed_official 146:f64d43ff0c18 1126
mbed_official 146:f64d43ff0c18 1127 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1128 //! @brief Set the FTM1CLKSEL field to a new value.
mbed_official 146:f64d43ff0c18 1129 #define BW_SIM_SOPT4_FTM1CLKSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM1CLKSEL) = (v))
mbed_official 146:f64d43ff0c18 1130 #endif
mbed_official 146:f64d43ff0c18 1131 //@}
mbed_official 146:f64d43ff0c18 1132
mbed_official 146:f64d43ff0c18 1133 /*!
mbed_official 146:f64d43ff0c18 1134 * @name Register SIM_SOPT4, field FTM2CLKSEL[26] (RW)
mbed_official 146:f64d43ff0c18 1135 *
mbed_official 146:f64d43ff0c18 1136 * Selects the external pin used to drive the clock to the FTM2 module. The
mbed_official 146:f64d43ff0c18 1137 * selected pin must also be configured for the FTM2 module external clock function
mbed_official 146:f64d43ff0c18 1138 * through the appropriate pin control register in the port control module.
mbed_official 146:f64d43ff0c18 1139 *
mbed_official 146:f64d43ff0c18 1140 * Values:
mbed_official 146:f64d43ff0c18 1141 * - 0 - FTM2 external clock driven by FTM_CLK0 pin.
mbed_official 146:f64d43ff0c18 1142 * - 1 - FTM2 external clock driven by FTM_CLK1 pin.
mbed_official 146:f64d43ff0c18 1143 */
mbed_official 146:f64d43ff0c18 1144 //@{
mbed_official 146:f64d43ff0c18 1145 #define BP_SIM_SOPT4_FTM2CLKSEL (26U) //!< Bit position for SIM_SOPT4_FTM2CLKSEL.
mbed_official 146:f64d43ff0c18 1146 #define BM_SIM_SOPT4_FTM2CLKSEL (0x04000000U) //!< Bit mask for SIM_SOPT4_FTM2CLKSEL.
mbed_official 146:f64d43ff0c18 1147 #define BS_SIM_SOPT4_FTM2CLKSEL (1U) //!< Bit field size in bits for SIM_SOPT4_FTM2CLKSEL.
mbed_official 146:f64d43ff0c18 1148
mbed_official 146:f64d43ff0c18 1149 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1150 //! @brief Read current value of the SIM_SOPT4_FTM2CLKSEL field.
mbed_official 146:f64d43ff0c18 1151 #define BR_SIM_SOPT4_FTM2CLKSEL (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM2CLKSEL))
mbed_official 146:f64d43ff0c18 1152 #endif
mbed_official 146:f64d43ff0c18 1153
mbed_official 146:f64d43ff0c18 1154 //! @brief Format value for bitfield SIM_SOPT4_FTM2CLKSEL.
mbed_official 146:f64d43ff0c18 1155 #define BF_SIM_SOPT4_FTM2CLKSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM2CLKSEL), uint32_t) & BM_SIM_SOPT4_FTM2CLKSEL)
mbed_official 146:f64d43ff0c18 1156
mbed_official 146:f64d43ff0c18 1157 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1158 //! @brief Set the FTM2CLKSEL field to a new value.
mbed_official 146:f64d43ff0c18 1159 #define BW_SIM_SOPT4_FTM2CLKSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM2CLKSEL) = (v))
mbed_official 146:f64d43ff0c18 1160 #endif
mbed_official 146:f64d43ff0c18 1161 //@}
mbed_official 146:f64d43ff0c18 1162
mbed_official 146:f64d43ff0c18 1163 /*!
mbed_official 146:f64d43ff0c18 1164 * @name Register SIM_SOPT4, field FTM3CLKSEL[27] (RW)
mbed_official 146:f64d43ff0c18 1165 *
mbed_official 146:f64d43ff0c18 1166 * Selects the external pin used to drive the clock to the FTM3 module. The
mbed_official 146:f64d43ff0c18 1167 * selected pin must also be configured for the FTM3 module external clock function
mbed_official 146:f64d43ff0c18 1168 * through the appropriate pin control register in the port control module.
mbed_official 146:f64d43ff0c18 1169 *
mbed_official 146:f64d43ff0c18 1170 * Values:
mbed_official 146:f64d43ff0c18 1171 * - 0 - FTM3 external clock driven by FTM_CLK0 pin.
mbed_official 146:f64d43ff0c18 1172 * - 1 - FTM3 external clock driven by FTM_CLK1 pin.
mbed_official 146:f64d43ff0c18 1173 */
mbed_official 146:f64d43ff0c18 1174 //@{
mbed_official 146:f64d43ff0c18 1175 #define BP_SIM_SOPT4_FTM3CLKSEL (27U) //!< Bit position for SIM_SOPT4_FTM3CLKSEL.
mbed_official 146:f64d43ff0c18 1176 #define BM_SIM_SOPT4_FTM3CLKSEL (0x08000000U) //!< Bit mask for SIM_SOPT4_FTM3CLKSEL.
mbed_official 146:f64d43ff0c18 1177 #define BS_SIM_SOPT4_FTM3CLKSEL (1U) //!< Bit field size in bits for SIM_SOPT4_FTM3CLKSEL.
mbed_official 146:f64d43ff0c18 1178
mbed_official 146:f64d43ff0c18 1179 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1180 //! @brief Read current value of the SIM_SOPT4_FTM3CLKSEL field.
mbed_official 146:f64d43ff0c18 1181 #define BR_SIM_SOPT4_FTM3CLKSEL (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3CLKSEL))
mbed_official 146:f64d43ff0c18 1182 #endif
mbed_official 146:f64d43ff0c18 1183
mbed_official 146:f64d43ff0c18 1184 //! @brief Format value for bitfield SIM_SOPT4_FTM3CLKSEL.
mbed_official 146:f64d43ff0c18 1185 #define BF_SIM_SOPT4_FTM3CLKSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM3CLKSEL), uint32_t) & BM_SIM_SOPT4_FTM3CLKSEL)
mbed_official 146:f64d43ff0c18 1186
mbed_official 146:f64d43ff0c18 1187 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1188 //! @brief Set the FTM3CLKSEL field to a new value.
mbed_official 146:f64d43ff0c18 1189 #define BW_SIM_SOPT4_FTM3CLKSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3CLKSEL) = (v))
mbed_official 146:f64d43ff0c18 1190 #endif
mbed_official 146:f64d43ff0c18 1191 //@}
mbed_official 146:f64d43ff0c18 1192
mbed_official 146:f64d43ff0c18 1193 /*!
mbed_official 146:f64d43ff0c18 1194 * @name Register SIM_SOPT4, field FTM0TRG0SRC[28] (RW)
mbed_official 146:f64d43ff0c18 1195 *
mbed_official 146:f64d43ff0c18 1196 * Selects the source of FTM0 hardware trigger 0.
mbed_official 146:f64d43ff0c18 1197 *
mbed_official 146:f64d43ff0c18 1198 * Values:
mbed_official 146:f64d43ff0c18 1199 * - 0 - HSCMP0 output drives FTM0 hardware trigger 0
mbed_official 146:f64d43ff0c18 1200 * - 1 - FTM1 channel match drives FTM0 hardware trigger 0
mbed_official 146:f64d43ff0c18 1201 */
mbed_official 146:f64d43ff0c18 1202 //@{
mbed_official 146:f64d43ff0c18 1203 #define BP_SIM_SOPT4_FTM0TRG0SRC (28U) //!< Bit position for SIM_SOPT4_FTM0TRG0SRC.
mbed_official 146:f64d43ff0c18 1204 #define BM_SIM_SOPT4_FTM0TRG0SRC (0x10000000U) //!< Bit mask for SIM_SOPT4_FTM0TRG0SRC.
mbed_official 146:f64d43ff0c18 1205 #define BS_SIM_SOPT4_FTM0TRG0SRC (1U) //!< Bit field size in bits for SIM_SOPT4_FTM0TRG0SRC.
mbed_official 146:f64d43ff0c18 1206
mbed_official 146:f64d43ff0c18 1207 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1208 //! @brief Read current value of the SIM_SOPT4_FTM0TRG0SRC field.
mbed_official 146:f64d43ff0c18 1209 #define BR_SIM_SOPT4_FTM0TRG0SRC (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0TRG0SRC))
mbed_official 146:f64d43ff0c18 1210 #endif
mbed_official 146:f64d43ff0c18 1211
mbed_official 146:f64d43ff0c18 1212 //! @brief Format value for bitfield SIM_SOPT4_FTM0TRG0SRC.
mbed_official 146:f64d43ff0c18 1213 #define BF_SIM_SOPT4_FTM0TRG0SRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM0TRG0SRC), uint32_t) & BM_SIM_SOPT4_FTM0TRG0SRC)
mbed_official 146:f64d43ff0c18 1214
mbed_official 146:f64d43ff0c18 1215 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1216 //! @brief Set the FTM0TRG0SRC field to a new value.
mbed_official 146:f64d43ff0c18 1217 #define BW_SIM_SOPT4_FTM0TRG0SRC(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0TRG0SRC) = (v))
mbed_official 146:f64d43ff0c18 1218 #endif
mbed_official 146:f64d43ff0c18 1219 //@}
mbed_official 146:f64d43ff0c18 1220
mbed_official 146:f64d43ff0c18 1221 /*!
mbed_official 146:f64d43ff0c18 1222 * @name Register SIM_SOPT4, field FTM0TRG1SRC[29] (RW)
mbed_official 146:f64d43ff0c18 1223 *
mbed_official 146:f64d43ff0c18 1224 * Selects the source of FTM0 hardware trigger 1.
mbed_official 146:f64d43ff0c18 1225 *
mbed_official 146:f64d43ff0c18 1226 * Values:
mbed_official 146:f64d43ff0c18 1227 * - 0 - PDB output trigger 1 drives FTM0 hardware trigger 1
mbed_official 146:f64d43ff0c18 1228 * - 1 - FTM2 channel match drives FTM0 hardware trigger 1
mbed_official 146:f64d43ff0c18 1229 */
mbed_official 146:f64d43ff0c18 1230 //@{
mbed_official 146:f64d43ff0c18 1231 #define BP_SIM_SOPT4_FTM0TRG1SRC (29U) //!< Bit position for SIM_SOPT4_FTM0TRG1SRC.
mbed_official 146:f64d43ff0c18 1232 #define BM_SIM_SOPT4_FTM0TRG1SRC (0x20000000U) //!< Bit mask for SIM_SOPT4_FTM0TRG1SRC.
mbed_official 146:f64d43ff0c18 1233 #define BS_SIM_SOPT4_FTM0TRG1SRC (1U) //!< Bit field size in bits for SIM_SOPT4_FTM0TRG1SRC.
mbed_official 146:f64d43ff0c18 1234
mbed_official 146:f64d43ff0c18 1235 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1236 //! @brief Read current value of the SIM_SOPT4_FTM0TRG1SRC field.
mbed_official 146:f64d43ff0c18 1237 #define BR_SIM_SOPT4_FTM0TRG1SRC (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0TRG1SRC))
mbed_official 146:f64d43ff0c18 1238 #endif
mbed_official 146:f64d43ff0c18 1239
mbed_official 146:f64d43ff0c18 1240 //! @brief Format value for bitfield SIM_SOPT4_FTM0TRG1SRC.
mbed_official 146:f64d43ff0c18 1241 #define BF_SIM_SOPT4_FTM0TRG1SRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM0TRG1SRC), uint32_t) & BM_SIM_SOPT4_FTM0TRG1SRC)
mbed_official 146:f64d43ff0c18 1242
mbed_official 146:f64d43ff0c18 1243 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1244 //! @brief Set the FTM0TRG1SRC field to a new value.
mbed_official 146:f64d43ff0c18 1245 #define BW_SIM_SOPT4_FTM0TRG1SRC(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0TRG1SRC) = (v))
mbed_official 146:f64d43ff0c18 1246 #endif
mbed_official 146:f64d43ff0c18 1247 //@}
mbed_official 146:f64d43ff0c18 1248
mbed_official 146:f64d43ff0c18 1249 /*!
mbed_official 146:f64d43ff0c18 1250 * @name Register SIM_SOPT4, field FTM3TRG0SRC[30] (RW)
mbed_official 146:f64d43ff0c18 1251 *
mbed_official 146:f64d43ff0c18 1252 * Selects the source of FTM3 hardware trigger 0.
mbed_official 146:f64d43ff0c18 1253 *
mbed_official 146:f64d43ff0c18 1254 * Values:
mbed_official 146:f64d43ff0c18 1255 * - 0 - Reserved
mbed_official 146:f64d43ff0c18 1256 * - 1 - FTM1 channel match drives FTM3 hardware trigger 0
mbed_official 146:f64d43ff0c18 1257 */
mbed_official 146:f64d43ff0c18 1258 //@{
mbed_official 146:f64d43ff0c18 1259 #define BP_SIM_SOPT4_FTM3TRG0SRC (30U) //!< Bit position for SIM_SOPT4_FTM3TRG0SRC.
mbed_official 146:f64d43ff0c18 1260 #define BM_SIM_SOPT4_FTM3TRG0SRC (0x40000000U) //!< Bit mask for SIM_SOPT4_FTM3TRG0SRC.
mbed_official 146:f64d43ff0c18 1261 #define BS_SIM_SOPT4_FTM3TRG0SRC (1U) //!< Bit field size in bits for SIM_SOPT4_FTM3TRG0SRC.
mbed_official 146:f64d43ff0c18 1262
mbed_official 146:f64d43ff0c18 1263 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1264 //! @brief Read current value of the SIM_SOPT4_FTM3TRG0SRC field.
mbed_official 146:f64d43ff0c18 1265 #define BR_SIM_SOPT4_FTM3TRG0SRC (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3TRG0SRC))
mbed_official 146:f64d43ff0c18 1266 #endif
mbed_official 146:f64d43ff0c18 1267
mbed_official 146:f64d43ff0c18 1268 //! @brief Format value for bitfield SIM_SOPT4_FTM3TRG0SRC.
mbed_official 146:f64d43ff0c18 1269 #define BF_SIM_SOPT4_FTM3TRG0SRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM3TRG0SRC), uint32_t) & BM_SIM_SOPT4_FTM3TRG0SRC)
mbed_official 146:f64d43ff0c18 1270
mbed_official 146:f64d43ff0c18 1271 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1272 //! @brief Set the FTM3TRG0SRC field to a new value.
mbed_official 146:f64d43ff0c18 1273 #define BW_SIM_SOPT4_FTM3TRG0SRC(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3TRG0SRC) = (v))
mbed_official 146:f64d43ff0c18 1274 #endif
mbed_official 146:f64d43ff0c18 1275 //@}
mbed_official 146:f64d43ff0c18 1276
mbed_official 146:f64d43ff0c18 1277 /*!
mbed_official 146:f64d43ff0c18 1278 * @name Register SIM_SOPT4, field FTM3TRG1SRC[31] (RW)
mbed_official 146:f64d43ff0c18 1279 *
mbed_official 146:f64d43ff0c18 1280 * Selects the source of FTM3 hardware trigger 1.
mbed_official 146:f64d43ff0c18 1281 *
mbed_official 146:f64d43ff0c18 1282 * Values:
mbed_official 146:f64d43ff0c18 1283 * - 0 - Reserved
mbed_official 146:f64d43ff0c18 1284 * - 1 - FTM2 channel match drives FTM3 hardware trigger 1
mbed_official 146:f64d43ff0c18 1285 */
mbed_official 146:f64d43ff0c18 1286 //@{
mbed_official 146:f64d43ff0c18 1287 #define BP_SIM_SOPT4_FTM3TRG1SRC (31U) //!< Bit position for SIM_SOPT4_FTM3TRG1SRC.
mbed_official 146:f64d43ff0c18 1288 #define BM_SIM_SOPT4_FTM3TRG1SRC (0x80000000U) //!< Bit mask for SIM_SOPT4_FTM3TRG1SRC.
mbed_official 146:f64d43ff0c18 1289 #define BS_SIM_SOPT4_FTM3TRG1SRC (1U) //!< Bit field size in bits for SIM_SOPT4_FTM3TRG1SRC.
mbed_official 146:f64d43ff0c18 1290
mbed_official 146:f64d43ff0c18 1291 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1292 //! @brief Read current value of the SIM_SOPT4_FTM3TRG1SRC field.
mbed_official 146:f64d43ff0c18 1293 #define BR_SIM_SOPT4_FTM3TRG1SRC (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3TRG1SRC))
mbed_official 146:f64d43ff0c18 1294 #endif
mbed_official 146:f64d43ff0c18 1295
mbed_official 146:f64d43ff0c18 1296 //! @brief Format value for bitfield SIM_SOPT4_FTM3TRG1SRC.
mbed_official 146:f64d43ff0c18 1297 #define BF_SIM_SOPT4_FTM3TRG1SRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM3TRG1SRC), uint32_t) & BM_SIM_SOPT4_FTM3TRG1SRC)
mbed_official 146:f64d43ff0c18 1298
mbed_official 146:f64d43ff0c18 1299 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1300 //! @brief Set the FTM3TRG1SRC field to a new value.
mbed_official 146:f64d43ff0c18 1301 #define BW_SIM_SOPT4_FTM3TRG1SRC(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3TRG1SRC) = (v))
mbed_official 146:f64d43ff0c18 1302 #endif
mbed_official 146:f64d43ff0c18 1303 //@}
mbed_official 146:f64d43ff0c18 1304
mbed_official 146:f64d43ff0c18 1305 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1306 // HW_SIM_SOPT5 - System Options Register 5
mbed_official 146:f64d43ff0c18 1307 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1308
mbed_official 146:f64d43ff0c18 1309 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1310 /*!
mbed_official 146:f64d43ff0c18 1311 * @brief HW_SIM_SOPT5 - System Options Register 5 (RW)
mbed_official 146:f64d43ff0c18 1312 *
mbed_official 146:f64d43ff0c18 1313 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 1314 */
mbed_official 146:f64d43ff0c18 1315 typedef union _hw_sim_sopt5
mbed_official 146:f64d43ff0c18 1316 {
mbed_official 146:f64d43ff0c18 1317 uint32_t U;
mbed_official 146:f64d43ff0c18 1318 struct _hw_sim_sopt5_bitfields
mbed_official 146:f64d43ff0c18 1319 {
mbed_official 146:f64d43ff0c18 1320 uint32_t UART0TXSRC : 2; //!< [1:0] UART 0 transmit data source select
mbed_official 146:f64d43ff0c18 1321 uint32_t UART0RXSRC : 2; //!< [3:2] UART 0 receive data source select
mbed_official 146:f64d43ff0c18 1322 uint32_t UART1TXSRC : 2; //!< [5:4] UART 1 transmit data source select
mbed_official 146:f64d43ff0c18 1323 uint32_t UART1RXSRC : 2; //!< [7:6] UART 1 receive data source select
mbed_official 146:f64d43ff0c18 1324 uint32_t RESERVED0 : 24; //!< [31:8]
mbed_official 146:f64d43ff0c18 1325 } B;
mbed_official 146:f64d43ff0c18 1326 } hw_sim_sopt5_t;
mbed_official 146:f64d43ff0c18 1327 #endif
mbed_official 146:f64d43ff0c18 1328
mbed_official 146:f64d43ff0c18 1329 /*!
mbed_official 146:f64d43ff0c18 1330 * @name Constants and macros for entire SIM_SOPT5 register
mbed_official 146:f64d43ff0c18 1331 */
mbed_official 146:f64d43ff0c18 1332 //@{
mbed_official 146:f64d43ff0c18 1333 #define HW_SIM_SOPT5_ADDR (REGS_SIM_BASE + 0x1010U)
mbed_official 146:f64d43ff0c18 1334
mbed_official 146:f64d43ff0c18 1335 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1336 #define HW_SIM_SOPT5 (*(__IO hw_sim_sopt5_t *) HW_SIM_SOPT5_ADDR)
mbed_official 146:f64d43ff0c18 1337 #define HW_SIM_SOPT5_RD() (HW_SIM_SOPT5.U)
mbed_official 146:f64d43ff0c18 1338 #define HW_SIM_SOPT5_WR(v) (HW_SIM_SOPT5.U = (v))
mbed_official 146:f64d43ff0c18 1339 #define HW_SIM_SOPT5_SET(v) (HW_SIM_SOPT5_WR(HW_SIM_SOPT5_RD() | (v)))
mbed_official 146:f64d43ff0c18 1340 #define HW_SIM_SOPT5_CLR(v) (HW_SIM_SOPT5_WR(HW_SIM_SOPT5_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 1341 #define HW_SIM_SOPT5_TOG(v) (HW_SIM_SOPT5_WR(HW_SIM_SOPT5_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 1342 #endif
mbed_official 146:f64d43ff0c18 1343 //@}
mbed_official 146:f64d43ff0c18 1344
mbed_official 146:f64d43ff0c18 1345 /*
mbed_official 146:f64d43ff0c18 1346 * Constants & macros for individual SIM_SOPT5 bitfields
mbed_official 146:f64d43ff0c18 1347 */
mbed_official 146:f64d43ff0c18 1348
mbed_official 146:f64d43ff0c18 1349 /*!
mbed_official 146:f64d43ff0c18 1350 * @name Register SIM_SOPT5, field UART0TXSRC[1:0] (RW)
mbed_official 146:f64d43ff0c18 1351 *
mbed_official 146:f64d43ff0c18 1352 * Selects the source for the UART 0 transmit data.
mbed_official 146:f64d43ff0c18 1353 *
mbed_official 146:f64d43ff0c18 1354 * Values:
mbed_official 146:f64d43ff0c18 1355 * - 00 - UART0_TX pin
mbed_official 146:f64d43ff0c18 1356 * - 01 - UART0_TX pin modulated with FTM1 channel 0 output
mbed_official 146:f64d43ff0c18 1357 * - 10 - UART0_TX pin modulated with FTM2 channel 0 output
mbed_official 146:f64d43ff0c18 1358 * - 11 - Reserved
mbed_official 146:f64d43ff0c18 1359 */
mbed_official 146:f64d43ff0c18 1360 //@{
mbed_official 146:f64d43ff0c18 1361 #define BP_SIM_SOPT5_UART0TXSRC (0U) //!< Bit position for SIM_SOPT5_UART0TXSRC.
mbed_official 146:f64d43ff0c18 1362 #define BM_SIM_SOPT5_UART0TXSRC (0x00000003U) //!< Bit mask for SIM_SOPT5_UART0TXSRC.
mbed_official 146:f64d43ff0c18 1363 #define BS_SIM_SOPT5_UART0TXSRC (2U) //!< Bit field size in bits for SIM_SOPT5_UART0TXSRC.
mbed_official 146:f64d43ff0c18 1364
mbed_official 146:f64d43ff0c18 1365 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1366 //! @brief Read current value of the SIM_SOPT5_UART0TXSRC field.
mbed_official 146:f64d43ff0c18 1367 #define BR_SIM_SOPT5_UART0TXSRC (HW_SIM_SOPT5.B.UART0TXSRC)
mbed_official 146:f64d43ff0c18 1368 #endif
mbed_official 146:f64d43ff0c18 1369
mbed_official 146:f64d43ff0c18 1370 //! @brief Format value for bitfield SIM_SOPT5_UART0TXSRC.
mbed_official 146:f64d43ff0c18 1371 #define BF_SIM_SOPT5_UART0TXSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT5_UART0TXSRC), uint32_t) & BM_SIM_SOPT5_UART0TXSRC)
mbed_official 146:f64d43ff0c18 1372
mbed_official 146:f64d43ff0c18 1373 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1374 //! @brief Set the UART0TXSRC field to a new value.
mbed_official 146:f64d43ff0c18 1375 #define BW_SIM_SOPT5_UART0TXSRC(v) (HW_SIM_SOPT5_WR((HW_SIM_SOPT5_RD() & ~BM_SIM_SOPT5_UART0TXSRC) | BF_SIM_SOPT5_UART0TXSRC(v)))
mbed_official 146:f64d43ff0c18 1376 #endif
mbed_official 146:f64d43ff0c18 1377 //@}
mbed_official 146:f64d43ff0c18 1378
mbed_official 146:f64d43ff0c18 1379 /*!
mbed_official 146:f64d43ff0c18 1380 * @name Register SIM_SOPT5, field UART0RXSRC[3:2] (RW)
mbed_official 146:f64d43ff0c18 1381 *
mbed_official 146:f64d43ff0c18 1382 * Selects the source for the UART 0 receive data.
mbed_official 146:f64d43ff0c18 1383 *
mbed_official 146:f64d43ff0c18 1384 * Values:
mbed_official 146:f64d43ff0c18 1385 * - 00 - UART0_RX pin
mbed_official 146:f64d43ff0c18 1386 * - 01 - CMP0
mbed_official 146:f64d43ff0c18 1387 * - 10 - CMP1
mbed_official 146:f64d43ff0c18 1388 * - 11 - Reserved
mbed_official 146:f64d43ff0c18 1389 */
mbed_official 146:f64d43ff0c18 1390 //@{
mbed_official 146:f64d43ff0c18 1391 #define BP_SIM_SOPT5_UART0RXSRC (2U) //!< Bit position for SIM_SOPT5_UART0RXSRC.
mbed_official 146:f64d43ff0c18 1392 #define BM_SIM_SOPT5_UART0RXSRC (0x0000000CU) //!< Bit mask for SIM_SOPT5_UART0RXSRC.
mbed_official 146:f64d43ff0c18 1393 #define BS_SIM_SOPT5_UART0RXSRC (2U) //!< Bit field size in bits for SIM_SOPT5_UART0RXSRC.
mbed_official 146:f64d43ff0c18 1394
mbed_official 146:f64d43ff0c18 1395 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1396 //! @brief Read current value of the SIM_SOPT5_UART0RXSRC field.
mbed_official 146:f64d43ff0c18 1397 #define BR_SIM_SOPT5_UART0RXSRC (HW_SIM_SOPT5.B.UART0RXSRC)
mbed_official 146:f64d43ff0c18 1398 #endif
mbed_official 146:f64d43ff0c18 1399
mbed_official 146:f64d43ff0c18 1400 //! @brief Format value for bitfield SIM_SOPT5_UART0RXSRC.
mbed_official 146:f64d43ff0c18 1401 #define BF_SIM_SOPT5_UART0RXSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT5_UART0RXSRC), uint32_t) & BM_SIM_SOPT5_UART0RXSRC)
mbed_official 146:f64d43ff0c18 1402
mbed_official 146:f64d43ff0c18 1403 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1404 //! @brief Set the UART0RXSRC field to a new value.
mbed_official 146:f64d43ff0c18 1405 #define BW_SIM_SOPT5_UART0RXSRC(v) (HW_SIM_SOPT5_WR((HW_SIM_SOPT5_RD() & ~BM_SIM_SOPT5_UART0RXSRC) | BF_SIM_SOPT5_UART0RXSRC(v)))
mbed_official 146:f64d43ff0c18 1406 #endif
mbed_official 146:f64d43ff0c18 1407 //@}
mbed_official 146:f64d43ff0c18 1408
mbed_official 146:f64d43ff0c18 1409 /*!
mbed_official 146:f64d43ff0c18 1410 * @name Register SIM_SOPT5, field UART1TXSRC[5:4] (RW)
mbed_official 146:f64d43ff0c18 1411 *
mbed_official 146:f64d43ff0c18 1412 * Selects the source for the UART 1 transmit data.
mbed_official 146:f64d43ff0c18 1413 *
mbed_official 146:f64d43ff0c18 1414 * Values:
mbed_official 146:f64d43ff0c18 1415 * - 00 - UART1_TX pin
mbed_official 146:f64d43ff0c18 1416 * - 01 - UART1_TX pin modulated with FTM1 channel 0 output
mbed_official 146:f64d43ff0c18 1417 * - 10 - UART1_TX pin modulated with FTM2 channel 0 output
mbed_official 146:f64d43ff0c18 1418 * - 11 - Reserved
mbed_official 146:f64d43ff0c18 1419 */
mbed_official 146:f64d43ff0c18 1420 //@{
mbed_official 146:f64d43ff0c18 1421 #define BP_SIM_SOPT5_UART1TXSRC (4U) //!< Bit position for SIM_SOPT5_UART1TXSRC.
mbed_official 146:f64d43ff0c18 1422 #define BM_SIM_SOPT5_UART1TXSRC (0x00000030U) //!< Bit mask for SIM_SOPT5_UART1TXSRC.
mbed_official 146:f64d43ff0c18 1423 #define BS_SIM_SOPT5_UART1TXSRC (2U) //!< Bit field size in bits for SIM_SOPT5_UART1TXSRC.
mbed_official 146:f64d43ff0c18 1424
mbed_official 146:f64d43ff0c18 1425 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1426 //! @brief Read current value of the SIM_SOPT5_UART1TXSRC field.
mbed_official 146:f64d43ff0c18 1427 #define BR_SIM_SOPT5_UART1TXSRC (HW_SIM_SOPT5.B.UART1TXSRC)
mbed_official 146:f64d43ff0c18 1428 #endif
mbed_official 146:f64d43ff0c18 1429
mbed_official 146:f64d43ff0c18 1430 //! @brief Format value for bitfield SIM_SOPT5_UART1TXSRC.
mbed_official 146:f64d43ff0c18 1431 #define BF_SIM_SOPT5_UART1TXSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT5_UART1TXSRC), uint32_t) & BM_SIM_SOPT5_UART1TXSRC)
mbed_official 146:f64d43ff0c18 1432
mbed_official 146:f64d43ff0c18 1433 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1434 //! @brief Set the UART1TXSRC field to a new value.
mbed_official 146:f64d43ff0c18 1435 #define BW_SIM_SOPT5_UART1TXSRC(v) (HW_SIM_SOPT5_WR((HW_SIM_SOPT5_RD() & ~BM_SIM_SOPT5_UART1TXSRC) | BF_SIM_SOPT5_UART1TXSRC(v)))
mbed_official 146:f64d43ff0c18 1436 #endif
mbed_official 146:f64d43ff0c18 1437 //@}
mbed_official 146:f64d43ff0c18 1438
mbed_official 146:f64d43ff0c18 1439 /*!
mbed_official 146:f64d43ff0c18 1440 * @name Register SIM_SOPT5, field UART1RXSRC[7:6] (RW)
mbed_official 146:f64d43ff0c18 1441 *
mbed_official 146:f64d43ff0c18 1442 * Selects the source for the UART 1 receive data.
mbed_official 146:f64d43ff0c18 1443 *
mbed_official 146:f64d43ff0c18 1444 * Values:
mbed_official 146:f64d43ff0c18 1445 * - 00 - UART1_RX pin
mbed_official 146:f64d43ff0c18 1446 * - 01 - CMP0
mbed_official 146:f64d43ff0c18 1447 * - 10 - CMP1
mbed_official 146:f64d43ff0c18 1448 * - 11 - Reserved
mbed_official 146:f64d43ff0c18 1449 */
mbed_official 146:f64d43ff0c18 1450 //@{
mbed_official 146:f64d43ff0c18 1451 #define BP_SIM_SOPT5_UART1RXSRC (6U) //!< Bit position for SIM_SOPT5_UART1RXSRC.
mbed_official 146:f64d43ff0c18 1452 #define BM_SIM_SOPT5_UART1RXSRC (0x000000C0U) //!< Bit mask for SIM_SOPT5_UART1RXSRC.
mbed_official 146:f64d43ff0c18 1453 #define BS_SIM_SOPT5_UART1RXSRC (2U) //!< Bit field size in bits for SIM_SOPT5_UART1RXSRC.
mbed_official 146:f64d43ff0c18 1454
mbed_official 146:f64d43ff0c18 1455 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1456 //! @brief Read current value of the SIM_SOPT5_UART1RXSRC field.
mbed_official 146:f64d43ff0c18 1457 #define BR_SIM_SOPT5_UART1RXSRC (HW_SIM_SOPT5.B.UART1RXSRC)
mbed_official 146:f64d43ff0c18 1458 #endif
mbed_official 146:f64d43ff0c18 1459
mbed_official 146:f64d43ff0c18 1460 //! @brief Format value for bitfield SIM_SOPT5_UART1RXSRC.
mbed_official 146:f64d43ff0c18 1461 #define BF_SIM_SOPT5_UART1RXSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT5_UART1RXSRC), uint32_t) & BM_SIM_SOPT5_UART1RXSRC)
mbed_official 146:f64d43ff0c18 1462
mbed_official 146:f64d43ff0c18 1463 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1464 //! @brief Set the UART1RXSRC field to a new value.
mbed_official 146:f64d43ff0c18 1465 #define BW_SIM_SOPT5_UART1RXSRC(v) (HW_SIM_SOPT5_WR((HW_SIM_SOPT5_RD() & ~BM_SIM_SOPT5_UART1RXSRC) | BF_SIM_SOPT5_UART1RXSRC(v)))
mbed_official 146:f64d43ff0c18 1466 #endif
mbed_official 146:f64d43ff0c18 1467 //@}
mbed_official 146:f64d43ff0c18 1468
mbed_official 146:f64d43ff0c18 1469 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1470 // HW_SIM_SOPT7 - System Options Register 7
mbed_official 146:f64d43ff0c18 1471 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1472
mbed_official 146:f64d43ff0c18 1473 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1474 /*!
mbed_official 146:f64d43ff0c18 1475 * @brief HW_SIM_SOPT7 - System Options Register 7 (RW)
mbed_official 146:f64d43ff0c18 1476 *
mbed_official 146:f64d43ff0c18 1477 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 1478 */
mbed_official 146:f64d43ff0c18 1479 typedef union _hw_sim_sopt7
mbed_official 146:f64d43ff0c18 1480 {
mbed_official 146:f64d43ff0c18 1481 uint32_t U;
mbed_official 146:f64d43ff0c18 1482 struct _hw_sim_sopt7_bitfields
mbed_official 146:f64d43ff0c18 1483 {
mbed_official 146:f64d43ff0c18 1484 uint32_t ADC0TRGSEL : 4; //!< [3:0] ADC0 trigger select
mbed_official 146:f64d43ff0c18 1485 uint32_t ADC0PRETRGSEL : 1; //!< [4] ADC0 pretrigger select
mbed_official 146:f64d43ff0c18 1486 uint32_t RESERVED0 : 2; //!< [6:5]
mbed_official 146:f64d43ff0c18 1487 uint32_t ADC0ALTTRGEN : 1; //!< [7] ADC0 alternate trigger enable
mbed_official 146:f64d43ff0c18 1488 uint32_t ADC1TRGSEL : 4; //!< [11:8] ADC1 trigger select
mbed_official 146:f64d43ff0c18 1489 uint32_t ADC1PRETRGSEL : 1; //!< [12] ADC1 pre-trigger select
mbed_official 146:f64d43ff0c18 1490 uint32_t RESERVED1 : 2; //!< [14:13]
mbed_official 146:f64d43ff0c18 1491 uint32_t ADC1ALTTRGEN : 1; //!< [15] ADC1 alternate trigger enable
mbed_official 146:f64d43ff0c18 1492 uint32_t RESERVED2 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 1493 } B;
mbed_official 146:f64d43ff0c18 1494 } hw_sim_sopt7_t;
mbed_official 146:f64d43ff0c18 1495 #endif
mbed_official 146:f64d43ff0c18 1496
mbed_official 146:f64d43ff0c18 1497 /*!
mbed_official 146:f64d43ff0c18 1498 * @name Constants and macros for entire SIM_SOPT7 register
mbed_official 146:f64d43ff0c18 1499 */
mbed_official 146:f64d43ff0c18 1500 //@{
mbed_official 146:f64d43ff0c18 1501 #define HW_SIM_SOPT7_ADDR (REGS_SIM_BASE + 0x1018U)
mbed_official 146:f64d43ff0c18 1502
mbed_official 146:f64d43ff0c18 1503 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1504 #define HW_SIM_SOPT7 (*(__IO hw_sim_sopt7_t *) HW_SIM_SOPT7_ADDR)
mbed_official 146:f64d43ff0c18 1505 #define HW_SIM_SOPT7_RD() (HW_SIM_SOPT7.U)
mbed_official 146:f64d43ff0c18 1506 #define HW_SIM_SOPT7_WR(v) (HW_SIM_SOPT7.U = (v))
mbed_official 146:f64d43ff0c18 1507 #define HW_SIM_SOPT7_SET(v) (HW_SIM_SOPT7_WR(HW_SIM_SOPT7_RD() | (v)))
mbed_official 146:f64d43ff0c18 1508 #define HW_SIM_SOPT7_CLR(v) (HW_SIM_SOPT7_WR(HW_SIM_SOPT7_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 1509 #define HW_SIM_SOPT7_TOG(v) (HW_SIM_SOPT7_WR(HW_SIM_SOPT7_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 1510 #endif
mbed_official 146:f64d43ff0c18 1511 //@}
mbed_official 146:f64d43ff0c18 1512
mbed_official 146:f64d43ff0c18 1513 /*
mbed_official 146:f64d43ff0c18 1514 * Constants & macros for individual SIM_SOPT7 bitfields
mbed_official 146:f64d43ff0c18 1515 */
mbed_official 146:f64d43ff0c18 1516
mbed_official 146:f64d43ff0c18 1517 /*!
mbed_official 146:f64d43ff0c18 1518 * @name Register SIM_SOPT7, field ADC0TRGSEL[3:0] (RW)
mbed_official 146:f64d43ff0c18 1519 *
mbed_official 146:f64d43ff0c18 1520 * Selects the ADC0 trigger source when alternative triggers are functional in
mbed_official 146:f64d43ff0c18 1521 * stop and VLPS modes. .
mbed_official 146:f64d43ff0c18 1522 *
mbed_official 146:f64d43ff0c18 1523 * Values:
mbed_official 146:f64d43ff0c18 1524 * - 0000 - PDB external trigger pin input (PDB0_EXTRG)
mbed_official 146:f64d43ff0c18 1525 * - 0001 - High speed comparator 0 output
mbed_official 146:f64d43ff0c18 1526 * - 0010 - High speed comparator 1 output
mbed_official 146:f64d43ff0c18 1527 * - 0011 - High speed comparator 2 output
mbed_official 146:f64d43ff0c18 1528 * - 0100 - PIT trigger 0
mbed_official 146:f64d43ff0c18 1529 * - 0101 - PIT trigger 1
mbed_official 146:f64d43ff0c18 1530 * - 0110 - PIT trigger 2
mbed_official 146:f64d43ff0c18 1531 * - 0111 - PIT trigger 3
mbed_official 146:f64d43ff0c18 1532 * - 1000 - FTM0 trigger
mbed_official 146:f64d43ff0c18 1533 * - 1001 - FTM1 trigger
mbed_official 146:f64d43ff0c18 1534 * - 1010 - FTM2 trigger
mbed_official 146:f64d43ff0c18 1535 * - 1011 - FTM3 trigger
mbed_official 146:f64d43ff0c18 1536 * - 1100 - RTC alarm
mbed_official 146:f64d43ff0c18 1537 * - 1101 - RTC seconds
mbed_official 146:f64d43ff0c18 1538 * - 1110 - Low-power timer (LPTMR) trigger
mbed_official 146:f64d43ff0c18 1539 * - 1111 - Reserved
mbed_official 146:f64d43ff0c18 1540 */
mbed_official 146:f64d43ff0c18 1541 //@{
mbed_official 146:f64d43ff0c18 1542 #define BP_SIM_SOPT7_ADC0TRGSEL (0U) //!< Bit position for SIM_SOPT7_ADC0TRGSEL.
mbed_official 146:f64d43ff0c18 1543 #define BM_SIM_SOPT7_ADC0TRGSEL (0x0000000FU) //!< Bit mask for SIM_SOPT7_ADC0TRGSEL.
mbed_official 146:f64d43ff0c18 1544 #define BS_SIM_SOPT7_ADC0TRGSEL (4U) //!< Bit field size in bits for SIM_SOPT7_ADC0TRGSEL.
mbed_official 146:f64d43ff0c18 1545
mbed_official 146:f64d43ff0c18 1546 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1547 //! @brief Read current value of the SIM_SOPT7_ADC0TRGSEL field.
mbed_official 146:f64d43ff0c18 1548 #define BR_SIM_SOPT7_ADC0TRGSEL (HW_SIM_SOPT7.B.ADC0TRGSEL)
mbed_official 146:f64d43ff0c18 1549 #endif
mbed_official 146:f64d43ff0c18 1550
mbed_official 146:f64d43ff0c18 1551 //! @brief Format value for bitfield SIM_SOPT7_ADC0TRGSEL.
mbed_official 146:f64d43ff0c18 1552 #define BF_SIM_SOPT7_ADC0TRGSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT7_ADC0TRGSEL), uint32_t) & BM_SIM_SOPT7_ADC0TRGSEL)
mbed_official 146:f64d43ff0c18 1553
mbed_official 146:f64d43ff0c18 1554 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1555 //! @brief Set the ADC0TRGSEL field to a new value.
mbed_official 146:f64d43ff0c18 1556 #define BW_SIM_SOPT7_ADC0TRGSEL(v) (HW_SIM_SOPT7_WR((HW_SIM_SOPT7_RD() & ~BM_SIM_SOPT7_ADC0TRGSEL) | BF_SIM_SOPT7_ADC0TRGSEL(v)))
mbed_official 146:f64d43ff0c18 1557 #endif
mbed_official 146:f64d43ff0c18 1558 //@}
mbed_official 146:f64d43ff0c18 1559
mbed_official 146:f64d43ff0c18 1560 /*!
mbed_official 146:f64d43ff0c18 1561 * @name Register SIM_SOPT7, field ADC0PRETRGSEL[4] (RW)
mbed_official 146:f64d43ff0c18 1562 *
mbed_official 146:f64d43ff0c18 1563 * Selects the ADC0 pre-trigger source when alternative triggers are enabled
mbed_official 146:f64d43ff0c18 1564 * through ADC0ALTTRGEN.
mbed_official 146:f64d43ff0c18 1565 *
mbed_official 146:f64d43ff0c18 1566 * Values:
mbed_official 146:f64d43ff0c18 1567 * - 0 - Pre-trigger A
mbed_official 146:f64d43ff0c18 1568 * - 1 - Pre-trigger B
mbed_official 146:f64d43ff0c18 1569 */
mbed_official 146:f64d43ff0c18 1570 //@{
mbed_official 146:f64d43ff0c18 1571 #define BP_SIM_SOPT7_ADC0PRETRGSEL (4U) //!< Bit position for SIM_SOPT7_ADC0PRETRGSEL.
mbed_official 146:f64d43ff0c18 1572 #define BM_SIM_SOPT7_ADC0PRETRGSEL (0x00000010U) //!< Bit mask for SIM_SOPT7_ADC0PRETRGSEL.
mbed_official 146:f64d43ff0c18 1573 #define BS_SIM_SOPT7_ADC0PRETRGSEL (1U) //!< Bit field size in bits for SIM_SOPT7_ADC0PRETRGSEL.
mbed_official 146:f64d43ff0c18 1574
mbed_official 146:f64d43ff0c18 1575 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1576 //! @brief Read current value of the SIM_SOPT7_ADC0PRETRGSEL field.
mbed_official 146:f64d43ff0c18 1577 #define BR_SIM_SOPT7_ADC0PRETRGSEL (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC0PRETRGSEL))
mbed_official 146:f64d43ff0c18 1578 #endif
mbed_official 146:f64d43ff0c18 1579
mbed_official 146:f64d43ff0c18 1580 //! @brief Format value for bitfield SIM_SOPT7_ADC0PRETRGSEL.
mbed_official 146:f64d43ff0c18 1581 #define BF_SIM_SOPT7_ADC0PRETRGSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT7_ADC0PRETRGSEL), uint32_t) & BM_SIM_SOPT7_ADC0PRETRGSEL)
mbed_official 146:f64d43ff0c18 1582
mbed_official 146:f64d43ff0c18 1583 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1584 //! @brief Set the ADC0PRETRGSEL field to a new value.
mbed_official 146:f64d43ff0c18 1585 #define BW_SIM_SOPT7_ADC0PRETRGSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC0PRETRGSEL) = (v))
mbed_official 146:f64d43ff0c18 1586 #endif
mbed_official 146:f64d43ff0c18 1587 //@}
mbed_official 146:f64d43ff0c18 1588
mbed_official 146:f64d43ff0c18 1589 /*!
mbed_official 146:f64d43ff0c18 1590 * @name Register SIM_SOPT7, field ADC0ALTTRGEN[7] (RW)
mbed_official 146:f64d43ff0c18 1591 *
mbed_official 146:f64d43ff0c18 1592 * Enable alternative conversion triggers for ADC0.
mbed_official 146:f64d43ff0c18 1593 *
mbed_official 146:f64d43ff0c18 1594 * Values:
mbed_official 146:f64d43ff0c18 1595 * - 0 - PDB trigger selected for ADC0.
mbed_official 146:f64d43ff0c18 1596 * - 1 - Alternate trigger selected for ADC0.
mbed_official 146:f64d43ff0c18 1597 */
mbed_official 146:f64d43ff0c18 1598 //@{
mbed_official 146:f64d43ff0c18 1599 #define BP_SIM_SOPT7_ADC0ALTTRGEN (7U) //!< Bit position for SIM_SOPT7_ADC0ALTTRGEN.
mbed_official 146:f64d43ff0c18 1600 #define BM_SIM_SOPT7_ADC0ALTTRGEN (0x00000080U) //!< Bit mask for SIM_SOPT7_ADC0ALTTRGEN.
mbed_official 146:f64d43ff0c18 1601 #define BS_SIM_SOPT7_ADC0ALTTRGEN (1U) //!< Bit field size in bits for SIM_SOPT7_ADC0ALTTRGEN.
mbed_official 146:f64d43ff0c18 1602
mbed_official 146:f64d43ff0c18 1603 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1604 //! @brief Read current value of the SIM_SOPT7_ADC0ALTTRGEN field.
mbed_official 146:f64d43ff0c18 1605 #define BR_SIM_SOPT7_ADC0ALTTRGEN (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC0ALTTRGEN))
mbed_official 146:f64d43ff0c18 1606 #endif
mbed_official 146:f64d43ff0c18 1607
mbed_official 146:f64d43ff0c18 1608 //! @brief Format value for bitfield SIM_SOPT7_ADC0ALTTRGEN.
mbed_official 146:f64d43ff0c18 1609 #define BF_SIM_SOPT7_ADC0ALTTRGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT7_ADC0ALTTRGEN), uint32_t) & BM_SIM_SOPT7_ADC0ALTTRGEN)
mbed_official 146:f64d43ff0c18 1610
mbed_official 146:f64d43ff0c18 1611 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1612 //! @brief Set the ADC0ALTTRGEN field to a new value.
mbed_official 146:f64d43ff0c18 1613 #define BW_SIM_SOPT7_ADC0ALTTRGEN(v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC0ALTTRGEN) = (v))
mbed_official 146:f64d43ff0c18 1614 #endif
mbed_official 146:f64d43ff0c18 1615 //@}
mbed_official 146:f64d43ff0c18 1616
mbed_official 146:f64d43ff0c18 1617 /*!
mbed_official 146:f64d43ff0c18 1618 * @name Register SIM_SOPT7, field ADC1TRGSEL[11:8] (RW)
mbed_official 146:f64d43ff0c18 1619 *
mbed_official 146:f64d43ff0c18 1620 * Selects the ADC1 trigger source when alternative triggers are functional in
mbed_official 146:f64d43ff0c18 1621 * stop and VLPS modes.
mbed_official 146:f64d43ff0c18 1622 *
mbed_official 146:f64d43ff0c18 1623 * Values:
mbed_official 146:f64d43ff0c18 1624 * - 0000 - PDB external trigger pin input (PDB0_EXTRG)
mbed_official 146:f64d43ff0c18 1625 * - 0001 - High speed comparator 0 output
mbed_official 146:f64d43ff0c18 1626 * - 0010 - High speed comparator 1 output
mbed_official 146:f64d43ff0c18 1627 * - 0011 - High speed comparator 2 output
mbed_official 146:f64d43ff0c18 1628 * - 0100 - PIT trigger 0
mbed_official 146:f64d43ff0c18 1629 * - 0101 - PIT trigger 1
mbed_official 146:f64d43ff0c18 1630 * - 0110 - PIT trigger 2
mbed_official 146:f64d43ff0c18 1631 * - 0111 - PIT trigger 3
mbed_official 146:f64d43ff0c18 1632 * - 1000 - FTM0 trigger
mbed_official 146:f64d43ff0c18 1633 * - 1001 - FTM1 trigger
mbed_official 146:f64d43ff0c18 1634 * - 1010 - FTM2 trigger
mbed_official 146:f64d43ff0c18 1635 * - 1011 - FTM3 trigger
mbed_official 146:f64d43ff0c18 1636 * - 1100 - RTC alarm
mbed_official 146:f64d43ff0c18 1637 * - 1101 - RTC seconds
mbed_official 146:f64d43ff0c18 1638 * - 1110 - Low-power timer (LPTMR) trigger
mbed_official 146:f64d43ff0c18 1639 * - 1111 - Reserved
mbed_official 146:f64d43ff0c18 1640 */
mbed_official 146:f64d43ff0c18 1641 //@{
mbed_official 146:f64d43ff0c18 1642 #define BP_SIM_SOPT7_ADC1TRGSEL (8U) //!< Bit position for SIM_SOPT7_ADC1TRGSEL.
mbed_official 146:f64d43ff0c18 1643 #define BM_SIM_SOPT7_ADC1TRGSEL (0x00000F00U) //!< Bit mask for SIM_SOPT7_ADC1TRGSEL.
mbed_official 146:f64d43ff0c18 1644 #define BS_SIM_SOPT7_ADC1TRGSEL (4U) //!< Bit field size in bits for SIM_SOPT7_ADC1TRGSEL.
mbed_official 146:f64d43ff0c18 1645
mbed_official 146:f64d43ff0c18 1646 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1647 //! @brief Read current value of the SIM_SOPT7_ADC1TRGSEL field.
mbed_official 146:f64d43ff0c18 1648 #define BR_SIM_SOPT7_ADC1TRGSEL (HW_SIM_SOPT7.B.ADC1TRGSEL)
mbed_official 146:f64d43ff0c18 1649 #endif
mbed_official 146:f64d43ff0c18 1650
mbed_official 146:f64d43ff0c18 1651 //! @brief Format value for bitfield SIM_SOPT7_ADC1TRGSEL.
mbed_official 146:f64d43ff0c18 1652 #define BF_SIM_SOPT7_ADC1TRGSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT7_ADC1TRGSEL), uint32_t) & BM_SIM_SOPT7_ADC1TRGSEL)
mbed_official 146:f64d43ff0c18 1653
mbed_official 146:f64d43ff0c18 1654 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1655 //! @brief Set the ADC1TRGSEL field to a new value.
mbed_official 146:f64d43ff0c18 1656 #define BW_SIM_SOPT7_ADC1TRGSEL(v) (HW_SIM_SOPT7_WR((HW_SIM_SOPT7_RD() & ~BM_SIM_SOPT7_ADC1TRGSEL) | BF_SIM_SOPT7_ADC1TRGSEL(v)))
mbed_official 146:f64d43ff0c18 1657 #endif
mbed_official 146:f64d43ff0c18 1658 //@}
mbed_official 146:f64d43ff0c18 1659
mbed_official 146:f64d43ff0c18 1660 /*!
mbed_official 146:f64d43ff0c18 1661 * @name Register SIM_SOPT7, field ADC1PRETRGSEL[12] (RW)
mbed_official 146:f64d43ff0c18 1662 *
mbed_official 146:f64d43ff0c18 1663 * Selects the ADC1 pre-trigger source when alternative triggers are enabled
mbed_official 146:f64d43ff0c18 1664 * through ADC1ALTTRGEN.
mbed_official 146:f64d43ff0c18 1665 *
mbed_official 146:f64d43ff0c18 1666 * Values:
mbed_official 146:f64d43ff0c18 1667 * - 0 - Pre-trigger A selected for ADC1.
mbed_official 146:f64d43ff0c18 1668 * - 1 - Pre-trigger B selected for ADC1.
mbed_official 146:f64d43ff0c18 1669 */
mbed_official 146:f64d43ff0c18 1670 //@{
mbed_official 146:f64d43ff0c18 1671 #define BP_SIM_SOPT7_ADC1PRETRGSEL (12U) //!< Bit position for SIM_SOPT7_ADC1PRETRGSEL.
mbed_official 146:f64d43ff0c18 1672 #define BM_SIM_SOPT7_ADC1PRETRGSEL (0x00001000U) //!< Bit mask for SIM_SOPT7_ADC1PRETRGSEL.
mbed_official 146:f64d43ff0c18 1673 #define BS_SIM_SOPT7_ADC1PRETRGSEL (1U) //!< Bit field size in bits for SIM_SOPT7_ADC1PRETRGSEL.
mbed_official 146:f64d43ff0c18 1674
mbed_official 146:f64d43ff0c18 1675 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1676 //! @brief Read current value of the SIM_SOPT7_ADC1PRETRGSEL field.
mbed_official 146:f64d43ff0c18 1677 #define BR_SIM_SOPT7_ADC1PRETRGSEL (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC1PRETRGSEL))
mbed_official 146:f64d43ff0c18 1678 #endif
mbed_official 146:f64d43ff0c18 1679
mbed_official 146:f64d43ff0c18 1680 //! @brief Format value for bitfield SIM_SOPT7_ADC1PRETRGSEL.
mbed_official 146:f64d43ff0c18 1681 #define BF_SIM_SOPT7_ADC1PRETRGSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT7_ADC1PRETRGSEL), uint32_t) & BM_SIM_SOPT7_ADC1PRETRGSEL)
mbed_official 146:f64d43ff0c18 1682
mbed_official 146:f64d43ff0c18 1683 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1684 //! @brief Set the ADC1PRETRGSEL field to a new value.
mbed_official 146:f64d43ff0c18 1685 #define BW_SIM_SOPT7_ADC1PRETRGSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC1PRETRGSEL) = (v))
mbed_official 146:f64d43ff0c18 1686 #endif
mbed_official 146:f64d43ff0c18 1687 //@}
mbed_official 146:f64d43ff0c18 1688
mbed_official 146:f64d43ff0c18 1689 /*!
mbed_official 146:f64d43ff0c18 1690 * @name Register SIM_SOPT7, field ADC1ALTTRGEN[15] (RW)
mbed_official 146:f64d43ff0c18 1691 *
mbed_official 146:f64d43ff0c18 1692 * Enable alternative conversion triggers for ADC1.
mbed_official 146:f64d43ff0c18 1693 *
mbed_official 146:f64d43ff0c18 1694 * Values:
mbed_official 146:f64d43ff0c18 1695 * - 0 - PDB trigger selected for ADC1
mbed_official 146:f64d43ff0c18 1696 * - 1 - Alternate trigger selected for ADC1 as defined by ADC1TRGSEL.
mbed_official 146:f64d43ff0c18 1697 */
mbed_official 146:f64d43ff0c18 1698 //@{
mbed_official 146:f64d43ff0c18 1699 #define BP_SIM_SOPT7_ADC1ALTTRGEN (15U) //!< Bit position for SIM_SOPT7_ADC1ALTTRGEN.
mbed_official 146:f64d43ff0c18 1700 #define BM_SIM_SOPT7_ADC1ALTTRGEN (0x00008000U) //!< Bit mask for SIM_SOPT7_ADC1ALTTRGEN.
mbed_official 146:f64d43ff0c18 1701 #define BS_SIM_SOPT7_ADC1ALTTRGEN (1U) //!< Bit field size in bits for SIM_SOPT7_ADC1ALTTRGEN.
mbed_official 146:f64d43ff0c18 1702
mbed_official 146:f64d43ff0c18 1703 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1704 //! @brief Read current value of the SIM_SOPT7_ADC1ALTTRGEN field.
mbed_official 146:f64d43ff0c18 1705 #define BR_SIM_SOPT7_ADC1ALTTRGEN (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC1ALTTRGEN))
mbed_official 146:f64d43ff0c18 1706 #endif
mbed_official 146:f64d43ff0c18 1707
mbed_official 146:f64d43ff0c18 1708 //! @brief Format value for bitfield SIM_SOPT7_ADC1ALTTRGEN.
mbed_official 146:f64d43ff0c18 1709 #define BF_SIM_SOPT7_ADC1ALTTRGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT7_ADC1ALTTRGEN), uint32_t) & BM_SIM_SOPT7_ADC1ALTTRGEN)
mbed_official 146:f64d43ff0c18 1710
mbed_official 146:f64d43ff0c18 1711 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1712 //! @brief Set the ADC1ALTTRGEN field to a new value.
mbed_official 146:f64d43ff0c18 1713 #define BW_SIM_SOPT7_ADC1ALTTRGEN(v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC1ALTTRGEN) = (v))
mbed_official 146:f64d43ff0c18 1714 #endif
mbed_official 146:f64d43ff0c18 1715 //@}
mbed_official 146:f64d43ff0c18 1716
mbed_official 146:f64d43ff0c18 1717 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1718 // HW_SIM_SDID - System Device Identification Register
mbed_official 146:f64d43ff0c18 1719 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1720
mbed_official 146:f64d43ff0c18 1721 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1722 /*!
mbed_official 146:f64d43ff0c18 1723 * @brief HW_SIM_SDID - System Device Identification Register (RO)
mbed_official 146:f64d43ff0c18 1724 *
mbed_official 146:f64d43ff0c18 1725 * Reset value: 0x00000380U
mbed_official 146:f64d43ff0c18 1726 */
mbed_official 146:f64d43ff0c18 1727 typedef union _hw_sim_sdid
mbed_official 146:f64d43ff0c18 1728 {
mbed_official 146:f64d43ff0c18 1729 uint32_t U;
mbed_official 146:f64d43ff0c18 1730 struct _hw_sim_sdid_bitfields
mbed_official 146:f64d43ff0c18 1731 {
mbed_official 146:f64d43ff0c18 1732 uint32_t PINID : 4; //!< [3:0] Pincount identification
mbed_official 146:f64d43ff0c18 1733 uint32_t FAMID : 3; //!< [6:4] Kinetis family identification
mbed_official 146:f64d43ff0c18 1734 uint32_t DIEID : 5; //!< [11:7] Device Die ID
mbed_official 146:f64d43ff0c18 1735 uint32_t REVID : 4; //!< [15:12] Device revision number
mbed_official 146:f64d43ff0c18 1736 uint32_t RESERVED0 : 4; //!< [19:16]
mbed_official 146:f64d43ff0c18 1737 uint32_t SERIESID : 4; //!< [23:20] Kinetis Series ID
mbed_official 146:f64d43ff0c18 1738 uint32_t SUBFAMID : 4; //!< [27:24] Kinetis Sub-Family ID
mbed_official 146:f64d43ff0c18 1739 uint32_t FAMILYID : 4; //!< [31:28] Kinetis Family ID
mbed_official 146:f64d43ff0c18 1740 } B;
mbed_official 146:f64d43ff0c18 1741 } hw_sim_sdid_t;
mbed_official 146:f64d43ff0c18 1742 #endif
mbed_official 146:f64d43ff0c18 1743
mbed_official 146:f64d43ff0c18 1744 /*!
mbed_official 146:f64d43ff0c18 1745 * @name Constants and macros for entire SIM_SDID register
mbed_official 146:f64d43ff0c18 1746 */
mbed_official 146:f64d43ff0c18 1747 //@{
mbed_official 146:f64d43ff0c18 1748 #define HW_SIM_SDID_ADDR (REGS_SIM_BASE + 0x1024U)
mbed_official 146:f64d43ff0c18 1749
mbed_official 146:f64d43ff0c18 1750 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1751 #define HW_SIM_SDID (*(__I hw_sim_sdid_t *) HW_SIM_SDID_ADDR)
mbed_official 146:f64d43ff0c18 1752 #define HW_SIM_SDID_RD() (HW_SIM_SDID.U)
mbed_official 146:f64d43ff0c18 1753 #endif
mbed_official 146:f64d43ff0c18 1754 //@}
mbed_official 146:f64d43ff0c18 1755
mbed_official 146:f64d43ff0c18 1756 /*
mbed_official 146:f64d43ff0c18 1757 * Constants & macros for individual SIM_SDID bitfields
mbed_official 146:f64d43ff0c18 1758 */
mbed_official 146:f64d43ff0c18 1759
mbed_official 146:f64d43ff0c18 1760 /*!
mbed_official 146:f64d43ff0c18 1761 * @name Register SIM_SDID, field PINID[3:0] (RO)
mbed_official 146:f64d43ff0c18 1762 *
mbed_official 146:f64d43ff0c18 1763 * Specifies the pincount of the device.
mbed_official 146:f64d43ff0c18 1764 *
mbed_official 146:f64d43ff0c18 1765 * Values:
mbed_official 146:f64d43ff0c18 1766 * - 0000 - Reserved
mbed_official 146:f64d43ff0c18 1767 * - 0001 - Reserved
mbed_official 146:f64d43ff0c18 1768 * - 0010 - 32-pin
mbed_official 146:f64d43ff0c18 1769 * - 0011 - Reserved
mbed_official 146:f64d43ff0c18 1770 * - 0100 - 48-pin
mbed_official 146:f64d43ff0c18 1771 * - 0101 - 64-pin
mbed_official 146:f64d43ff0c18 1772 * - 0110 - 80-pin
mbed_official 146:f64d43ff0c18 1773 * - 0111 - 81-pin or 121-pin
mbed_official 146:f64d43ff0c18 1774 * - 1000 - 100-pin
mbed_official 146:f64d43ff0c18 1775 * - 1001 - 121-pin
mbed_official 146:f64d43ff0c18 1776 * - 1010 - 144-pin
mbed_official 146:f64d43ff0c18 1777 * - 1011 - Custom pinout (WLCSP)
mbed_official 146:f64d43ff0c18 1778 * - 1100 - 169-pin
mbed_official 146:f64d43ff0c18 1779 * - 1101 - Reserved
mbed_official 146:f64d43ff0c18 1780 * - 1110 - 256-pin
mbed_official 146:f64d43ff0c18 1781 * - 1111 - Reserved
mbed_official 146:f64d43ff0c18 1782 */
mbed_official 146:f64d43ff0c18 1783 //@{
mbed_official 146:f64d43ff0c18 1784 #define BP_SIM_SDID_PINID (0U) //!< Bit position for SIM_SDID_PINID.
mbed_official 146:f64d43ff0c18 1785 #define BM_SIM_SDID_PINID (0x0000000FU) //!< Bit mask for SIM_SDID_PINID.
mbed_official 146:f64d43ff0c18 1786 #define BS_SIM_SDID_PINID (4U) //!< Bit field size in bits for SIM_SDID_PINID.
mbed_official 146:f64d43ff0c18 1787
mbed_official 146:f64d43ff0c18 1788 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1789 //! @brief Read current value of the SIM_SDID_PINID field.
mbed_official 146:f64d43ff0c18 1790 #define BR_SIM_SDID_PINID (HW_SIM_SDID.B.PINID)
mbed_official 146:f64d43ff0c18 1791 #endif
mbed_official 146:f64d43ff0c18 1792 //@}
mbed_official 146:f64d43ff0c18 1793
mbed_official 146:f64d43ff0c18 1794 /*!
mbed_official 146:f64d43ff0c18 1795 * @name Register SIM_SDID, field FAMID[6:4] (RO)
mbed_official 146:f64d43ff0c18 1796 *
mbed_official 146:f64d43ff0c18 1797 * This field is maintained for compatibility only, but has been superceded by
mbed_official 146:f64d43ff0c18 1798 * the SERIESID, FAMILYID and SUBFAMID fields in this register.
mbed_official 146:f64d43ff0c18 1799 *
mbed_official 146:f64d43ff0c18 1800 * Values:
mbed_official 146:f64d43ff0c18 1801 * - 000 - K1x Family (without tamper)
mbed_official 146:f64d43ff0c18 1802 * - 001 - K2x Family (without tamper)
mbed_official 146:f64d43ff0c18 1803 * - 010 - K3x Family or K1x/K6x Family (with tamper)
mbed_official 146:f64d43ff0c18 1804 * - 011 - K4x Family or K2x Family (with tamper)
mbed_official 146:f64d43ff0c18 1805 * - 100 - K6x Family (without tamper)
mbed_official 146:f64d43ff0c18 1806 * - 101 - K7x Family
mbed_official 146:f64d43ff0c18 1807 * - 110 - Reserved
mbed_official 146:f64d43ff0c18 1808 * - 111 - Reserved
mbed_official 146:f64d43ff0c18 1809 */
mbed_official 146:f64d43ff0c18 1810 //@{
mbed_official 146:f64d43ff0c18 1811 #define BP_SIM_SDID_FAMID (4U) //!< Bit position for SIM_SDID_FAMID.
mbed_official 146:f64d43ff0c18 1812 #define BM_SIM_SDID_FAMID (0x00000070U) //!< Bit mask for SIM_SDID_FAMID.
mbed_official 146:f64d43ff0c18 1813 #define BS_SIM_SDID_FAMID (3U) //!< Bit field size in bits for SIM_SDID_FAMID.
mbed_official 146:f64d43ff0c18 1814
mbed_official 146:f64d43ff0c18 1815 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1816 //! @brief Read current value of the SIM_SDID_FAMID field.
mbed_official 146:f64d43ff0c18 1817 #define BR_SIM_SDID_FAMID (HW_SIM_SDID.B.FAMID)
mbed_official 146:f64d43ff0c18 1818 #endif
mbed_official 146:f64d43ff0c18 1819 //@}
mbed_official 146:f64d43ff0c18 1820
mbed_official 146:f64d43ff0c18 1821 /*!
mbed_official 146:f64d43ff0c18 1822 * @name Register SIM_SDID, field DIEID[11:7] (RO)
mbed_official 146:f64d43ff0c18 1823 *
mbed_official 146:f64d43ff0c18 1824 * Specifies the silicon feature set identication number for the device.
mbed_official 146:f64d43ff0c18 1825 */
mbed_official 146:f64d43ff0c18 1826 //@{
mbed_official 146:f64d43ff0c18 1827 #define BP_SIM_SDID_DIEID (7U) //!< Bit position for SIM_SDID_DIEID.
mbed_official 146:f64d43ff0c18 1828 #define BM_SIM_SDID_DIEID (0x00000F80U) //!< Bit mask for SIM_SDID_DIEID.
mbed_official 146:f64d43ff0c18 1829 #define BS_SIM_SDID_DIEID (5U) //!< Bit field size in bits for SIM_SDID_DIEID.
mbed_official 146:f64d43ff0c18 1830
mbed_official 146:f64d43ff0c18 1831 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1832 //! @brief Read current value of the SIM_SDID_DIEID field.
mbed_official 146:f64d43ff0c18 1833 #define BR_SIM_SDID_DIEID (HW_SIM_SDID.B.DIEID)
mbed_official 146:f64d43ff0c18 1834 #endif
mbed_official 146:f64d43ff0c18 1835 //@}
mbed_official 146:f64d43ff0c18 1836
mbed_official 146:f64d43ff0c18 1837 /*!
mbed_official 146:f64d43ff0c18 1838 * @name Register SIM_SDID, field REVID[15:12] (RO)
mbed_official 146:f64d43ff0c18 1839 *
mbed_official 146:f64d43ff0c18 1840 * Specifies the silicon implementation number for the device.
mbed_official 146:f64d43ff0c18 1841 */
mbed_official 146:f64d43ff0c18 1842 //@{
mbed_official 146:f64d43ff0c18 1843 #define BP_SIM_SDID_REVID (12U) //!< Bit position for SIM_SDID_REVID.
mbed_official 146:f64d43ff0c18 1844 #define BM_SIM_SDID_REVID (0x0000F000U) //!< Bit mask for SIM_SDID_REVID.
mbed_official 146:f64d43ff0c18 1845 #define BS_SIM_SDID_REVID (4U) //!< Bit field size in bits for SIM_SDID_REVID.
mbed_official 146:f64d43ff0c18 1846
mbed_official 146:f64d43ff0c18 1847 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1848 //! @brief Read current value of the SIM_SDID_REVID field.
mbed_official 146:f64d43ff0c18 1849 #define BR_SIM_SDID_REVID (HW_SIM_SDID.B.REVID)
mbed_official 146:f64d43ff0c18 1850 #endif
mbed_official 146:f64d43ff0c18 1851 //@}
mbed_official 146:f64d43ff0c18 1852
mbed_official 146:f64d43ff0c18 1853 /*!
mbed_official 146:f64d43ff0c18 1854 * @name Register SIM_SDID, field SERIESID[23:20] (RO)
mbed_official 146:f64d43ff0c18 1855 *
mbed_official 146:f64d43ff0c18 1856 * Specifies the Kinetis series of the device.
mbed_official 146:f64d43ff0c18 1857 *
mbed_official 146:f64d43ff0c18 1858 * Values:
mbed_official 146:f64d43ff0c18 1859 * - 0000 - Kinetis K series
mbed_official 146:f64d43ff0c18 1860 * - 0001 - Kinetis L series
mbed_official 146:f64d43ff0c18 1861 * - 0101 - Kinetis W series
mbed_official 146:f64d43ff0c18 1862 * - 0110 - Kinetis V series
mbed_official 146:f64d43ff0c18 1863 */
mbed_official 146:f64d43ff0c18 1864 //@{
mbed_official 146:f64d43ff0c18 1865 #define BP_SIM_SDID_SERIESID (20U) //!< Bit position for SIM_SDID_SERIESID.
mbed_official 146:f64d43ff0c18 1866 #define BM_SIM_SDID_SERIESID (0x00F00000U) //!< Bit mask for SIM_SDID_SERIESID.
mbed_official 146:f64d43ff0c18 1867 #define BS_SIM_SDID_SERIESID (4U) //!< Bit field size in bits for SIM_SDID_SERIESID.
mbed_official 146:f64d43ff0c18 1868
mbed_official 146:f64d43ff0c18 1869 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1870 //! @brief Read current value of the SIM_SDID_SERIESID field.
mbed_official 146:f64d43ff0c18 1871 #define BR_SIM_SDID_SERIESID (HW_SIM_SDID.B.SERIESID)
mbed_official 146:f64d43ff0c18 1872 #endif
mbed_official 146:f64d43ff0c18 1873 //@}
mbed_official 146:f64d43ff0c18 1874
mbed_official 146:f64d43ff0c18 1875 /*!
mbed_official 146:f64d43ff0c18 1876 * @name Register SIM_SDID, field SUBFAMID[27:24] (RO)
mbed_official 146:f64d43ff0c18 1877 *
mbed_official 146:f64d43ff0c18 1878 * Specifies the Kinetis sub-family of the device.
mbed_official 146:f64d43ff0c18 1879 *
mbed_official 146:f64d43ff0c18 1880 * Values:
mbed_official 146:f64d43ff0c18 1881 * - 0000 - Kx0 Subfamily
mbed_official 146:f64d43ff0c18 1882 * - 0001 - Kx1 Subfamily (tamper detect)
mbed_official 146:f64d43ff0c18 1883 * - 0010 - Kx2 Subfamily
mbed_official 146:f64d43ff0c18 1884 * - 0011 - Kx3 Subfamily (tamper detect)
mbed_official 146:f64d43ff0c18 1885 * - 0100 - Kx4 Subfamily
mbed_official 146:f64d43ff0c18 1886 * - 0101 - Kx5 Subfamily (tamper detect)
mbed_official 146:f64d43ff0c18 1887 * - 0110 - Kx6 Subfamily
mbed_official 146:f64d43ff0c18 1888 */
mbed_official 146:f64d43ff0c18 1889 //@{
mbed_official 146:f64d43ff0c18 1890 #define BP_SIM_SDID_SUBFAMID (24U) //!< Bit position for SIM_SDID_SUBFAMID.
mbed_official 146:f64d43ff0c18 1891 #define BM_SIM_SDID_SUBFAMID (0x0F000000U) //!< Bit mask for SIM_SDID_SUBFAMID.
mbed_official 146:f64d43ff0c18 1892 #define BS_SIM_SDID_SUBFAMID (4U) //!< Bit field size in bits for SIM_SDID_SUBFAMID.
mbed_official 146:f64d43ff0c18 1893
mbed_official 146:f64d43ff0c18 1894 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1895 //! @brief Read current value of the SIM_SDID_SUBFAMID field.
mbed_official 146:f64d43ff0c18 1896 #define BR_SIM_SDID_SUBFAMID (HW_SIM_SDID.B.SUBFAMID)
mbed_official 146:f64d43ff0c18 1897 #endif
mbed_official 146:f64d43ff0c18 1898 //@}
mbed_official 146:f64d43ff0c18 1899
mbed_official 146:f64d43ff0c18 1900 /*!
mbed_official 146:f64d43ff0c18 1901 * @name Register SIM_SDID, field FAMILYID[31:28] (RO)
mbed_official 146:f64d43ff0c18 1902 *
mbed_official 146:f64d43ff0c18 1903 * Specifies the Kinetis family of the device.
mbed_official 146:f64d43ff0c18 1904 *
mbed_official 146:f64d43ff0c18 1905 * Values:
mbed_official 146:f64d43ff0c18 1906 * - 0001 - K1x Family
mbed_official 146:f64d43ff0c18 1907 * - 0010 - K2x Family
mbed_official 146:f64d43ff0c18 1908 * - 0011 - K3x Family
mbed_official 146:f64d43ff0c18 1909 * - 0100 - K4x Family
mbed_official 146:f64d43ff0c18 1910 * - 0110 - K6x Family
mbed_official 146:f64d43ff0c18 1911 * - 0111 - K7x Family
mbed_official 146:f64d43ff0c18 1912 */
mbed_official 146:f64d43ff0c18 1913 //@{
mbed_official 146:f64d43ff0c18 1914 #define BP_SIM_SDID_FAMILYID (28U) //!< Bit position for SIM_SDID_FAMILYID.
mbed_official 146:f64d43ff0c18 1915 #define BM_SIM_SDID_FAMILYID (0xF0000000U) //!< Bit mask for SIM_SDID_FAMILYID.
mbed_official 146:f64d43ff0c18 1916 #define BS_SIM_SDID_FAMILYID (4U) //!< Bit field size in bits for SIM_SDID_FAMILYID.
mbed_official 146:f64d43ff0c18 1917
mbed_official 146:f64d43ff0c18 1918 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1919 //! @brief Read current value of the SIM_SDID_FAMILYID field.
mbed_official 146:f64d43ff0c18 1920 #define BR_SIM_SDID_FAMILYID (HW_SIM_SDID.B.FAMILYID)
mbed_official 146:f64d43ff0c18 1921 #endif
mbed_official 146:f64d43ff0c18 1922 //@}
mbed_official 146:f64d43ff0c18 1923
mbed_official 146:f64d43ff0c18 1924 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1925 // HW_SIM_SCGC1 - System Clock Gating Control Register 1
mbed_official 146:f64d43ff0c18 1926 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1927
mbed_official 146:f64d43ff0c18 1928 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1929 /*!
mbed_official 146:f64d43ff0c18 1930 * @brief HW_SIM_SCGC1 - System Clock Gating Control Register 1 (RW)
mbed_official 146:f64d43ff0c18 1931 *
mbed_official 146:f64d43ff0c18 1932 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 1933 */
mbed_official 146:f64d43ff0c18 1934 typedef union _hw_sim_scgc1
mbed_official 146:f64d43ff0c18 1935 {
mbed_official 146:f64d43ff0c18 1936 uint32_t U;
mbed_official 146:f64d43ff0c18 1937 struct _hw_sim_scgc1_bitfields
mbed_official 146:f64d43ff0c18 1938 {
mbed_official 146:f64d43ff0c18 1939 uint32_t RESERVED0 : 6; //!< [5:0]
mbed_official 146:f64d43ff0c18 1940 uint32_t I2C2b : 1; //!< [6] I2C2 Clock Gate Control
mbed_official 146:f64d43ff0c18 1941 uint32_t RESERVED1 : 3; //!< [9:7]
mbed_official 146:f64d43ff0c18 1942 uint32_t UART4b : 1; //!< [10] UART4 Clock Gate Control
mbed_official 146:f64d43ff0c18 1943 uint32_t UART5b : 1; //!< [11] UART5 Clock Gate Control
mbed_official 146:f64d43ff0c18 1944 uint32_t RESERVED2 : 20; //!< [31:12]
mbed_official 146:f64d43ff0c18 1945 } B;
mbed_official 146:f64d43ff0c18 1946 } hw_sim_scgc1_t;
mbed_official 146:f64d43ff0c18 1947 #endif
mbed_official 146:f64d43ff0c18 1948
mbed_official 146:f64d43ff0c18 1949 /*!
mbed_official 146:f64d43ff0c18 1950 * @name Constants and macros for entire SIM_SCGC1 register
mbed_official 146:f64d43ff0c18 1951 */
mbed_official 146:f64d43ff0c18 1952 //@{
mbed_official 146:f64d43ff0c18 1953 #define HW_SIM_SCGC1_ADDR (REGS_SIM_BASE + 0x1028U)
mbed_official 146:f64d43ff0c18 1954
mbed_official 146:f64d43ff0c18 1955 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1956 #define HW_SIM_SCGC1 (*(__IO hw_sim_scgc1_t *) HW_SIM_SCGC1_ADDR)
mbed_official 146:f64d43ff0c18 1957 #define HW_SIM_SCGC1_RD() (HW_SIM_SCGC1.U)
mbed_official 146:f64d43ff0c18 1958 #define HW_SIM_SCGC1_WR(v) (HW_SIM_SCGC1.U = (v))
mbed_official 146:f64d43ff0c18 1959 #define HW_SIM_SCGC1_SET(v) (HW_SIM_SCGC1_WR(HW_SIM_SCGC1_RD() | (v)))
mbed_official 146:f64d43ff0c18 1960 #define HW_SIM_SCGC1_CLR(v) (HW_SIM_SCGC1_WR(HW_SIM_SCGC1_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 1961 #define HW_SIM_SCGC1_TOG(v) (HW_SIM_SCGC1_WR(HW_SIM_SCGC1_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 1962 #endif
mbed_official 146:f64d43ff0c18 1963 //@}
mbed_official 146:f64d43ff0c18 1964
mbed_official 146:f64d43ff0c18 1965 /*
mbed_official 146:f64d43ff0c18 1966 * Constants & macros for individual SIM_SCGC1 bitfields
mbed_official 146:f64d43ff0c18 1967 */
mbed_official 146:f64d43ff0c18 1968
mbed_official 146:f64d43ff0c18 1969 /*!
mbed_official 146:f64d43ff0c18 1970 * @name Register SIM_SCGC1, field I2C2[6] (RW)
mbed_official 146:f64d43ff0c18 1971 *
mbed_official 146:f64d43ff0c18 1972 * This bit controls the clock gate to the I2C2 module.
mbed_official 146:f64d43ff0c18 1973 *
mbed_official 146:f64d43ff0c18 1974 * Values:
mbed_official 146:f64d43ff0c18 1975 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 1976 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 1977 */
mbed_official 146:f64d43ff0c18 1978 //@{
mbed_official 146:f64d43ff0c18 1979 #define BP_SIM_SCGC1_I2C2 (6U) //!< Bit position for SIM_SCGC1_I2C2.
mbed_official 146:f64d43ff0c18 1980 #define BM_SIM_SCGC1_I2C2 (0x00000040U) //!< Bit mask for SIM_SCGC1_I2C2.
mbed_official 146:f64d43ff0c18 1981 #define BS_SIM_SCGC1_I2C2 (1U) //!< Bit field size in bits for SIM_SCGC1_I2C2.
mbed_official 146:f64d43ff0c18 1982
mbed_official 146:f64d43ff0c18 1983 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1984 //! @brief Read current value of the SIM_SCGC1_I2C2 field.
mbed_official 146:f64d43ff0c18 1985 #define BR_SIM_SCGC1_I2C2 (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR, BP_SIM_SCGC1_I2C2))
mbed_official 146:f64d43ff0c18 1986 #endif
mbed_official 146:f64d43ff0c18 1987
mbed_official 146:f64d43ff0c18 1988 //! @brief Format value for bitfield SIM_SCGC1_I2C2.
mbed_official 146:f64d43ff0c18 1989 #define BF_SIM_SCGC1_I2C2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC1_I2C2), uint32_t) & BM_SIM_SCGC1_I2C2)
mbed_official 146:f64d43ff0c18 1990
mbed_official 146:f64d43ff0c18 1991 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1992 //! @brief Set the I2C2 field to a new value.
mbed_official 146:f64d43ff0c18 1993 #define BW_SIM_SCGC1_I2C2(v) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR, BP_SIM_SCGC1_I2C2) = (v))
mbed_official 146:f64d43ff0c18 1994 #endif
mbed_official 146:f64d43ff0c18 1995 //@}
mbed_official 146:f64d43ff0c18 1996
mbed_official 146:f64d43ff0c18 1997 /*!
mbed_official 146:f64d43ff0c18 1998 * @name Register SIM_SCGC1, field UART4[10] (RW)
mbed_official 146:f64d43ff0c18 1999 *
mbed_official 146:f64d43ff0c18 2000 * This bit controls the clock gate to the UART4 module.
mbed_official 146:f64d43ff0c18 2001 *
mbed_official 146:f64d43ff0c18 2002 * Values:
mbed_official 146:f64d43ff0c18 2003 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 2004 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 2005 */
mbed_official 146:f64d43ff0c18 2006 //@{
mbed_official 146:f64d43ff0c18 2007 #define BP_SIM_SCGC1_UART4 (10U) //!< Bit position for SIM_SCGC1_UART4.
mbed_official 146:f64d43ff0c18 2008 #define BM_SIM_SCGC1_UART4 (0x00000400U) //!< Bit mask for SIM_SCGC1_UART4.
mbed_official 146:f64d43ff0c18 2009 #define BS_SIM_SCGC1_UART4 (1U) //!< Bit field size in bits for SIM_SCGC1_UART4.
mbed_official 146:f64d43ff0c18 2010
mbed_official 146:f64d43ff0c18 2011 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2012 //! @brief Read current value of the SIM_SCGC1_UART4 field.
mbed_official 146:f64d43ff0c18 2013 #define BR_SIM_SCGC1_UART4 (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR, BP_SIM_SCGC1_UART4))
mbed_official 146:f64d43ff0c18 2014 #endif
mbed_official 146:f64d43ff0c18 2015
mbed_official 146:f64d43ff0c18 2016 //! @brief Format value for bitfield SIM_SCGC1_UART4.
mbed_official 146:f64d43ff0c18 2017 #define BF_SIM_SCGC1_UART4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC1_UART4), uint32_t) & BM_SIM_SCGC1_UART4)
mbed_official 146:f64d43ff0c18 2018
mbed_official 146:f64d43ff0c18 2019 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2020 //! @brief Set the UART4 field to a new value.
mbed_official 146:f64d43ff0c18 2021 #define BW_SIM_SCGC1_UART4(v) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR, BP_SIM_SCGC1_UART4) = (v))
mbed_official 146:f64d43ff0c18 2022 #endif
mbed_official 146:f64d43ff0c18 2023 //@}
mbed_official 146:f64d43ff0c18 2024
mbed_official 146:f64d43ff0c18 2025 /*!
mbed_official 146:f64d43ff0c18 2026 * @name Register SIM_SCGC1, field UART5[11] (RW)
mbed_official 146:f64d43ff0c18 2027 *
mbed_official 146:f64d43ff0c18 2028 * This bit controls the clock gate to the UART5 module.
mbed_official 146:f64d43ff0c18 2029 *
mbed_official 146:f64d43ff0c18 2030 * Values:
mbed_official 146:f64d43ff0c18 2031 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 2032 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 2033 */
mbed_official 146:f64d43ff0c18 2034 //@{
mbed_official 146:f64d43ff0c18 2035 #define BP_SIM_SCGC1_UART5 (11U) //!< Bit position for SIM_SCGC1_UART5.
mbed_official 146:f64d43ff0c18 2036 #define BM_SIM_SCGC1_UART5 (0x00000800U) //!< Bit mask for SIM_SCGC1_UART5.
mbed_official 146:f64d43ff0c18 2037 #define BS_SIM_SCGC1_UART5 (1U) //!< Bit field size in bits for SIM_SCGC1_UART5.
mbed_official 146:f64d43ff0c18 2038
mbed_official 146:f64d43ff0c18 2039 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2040 //! @brief Read current value of the SIM_SCGC1_UART5 field.
mbed_official 146:f64d43ff0c18 2041 #define BR_SIM_SCGC1_UART5 (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR, BP_SIM_SCGC1_UART5))
mbed_official 146:f64d43ff0c18 2042 #endif
mbed_official 146:f64d43ff0c18 2043
mbed_official 146:f64d43ff0c18 2044 //! @brief Format value for bitfield SIM_SCGC1_UART5.
mbed_official 146:f64d43ff0c18 2045 #define BF_SIM_SCGC1_UART5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC1_UART5), uint32_t) & BM_SIM_SCGC1_UART5)
mbed_official 146:f64d43ff0c18 2046
mbed_official 146:f64d43ff0c18 2047 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2048 //! @brief Set the UART5 field to a new value.
mbed_official 146:f64d43ff0c18 2049 #define BW_SIM_SCGC1_UART5(v) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR, BP_SIM_SCGC1_UART5) = (v))
mbed_official 146:f64d43ff0c18 2050 #endif
mbed_official 146:f64d43ff0c18 2051 //@}
mbed_official 146:f64d43ff0c18 2052
mbed_official 146:f64d43ff0c18 2053 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2054 // HW_SIM_SCGC2 - System Clock Gating Control Register 2
mbed_official 146:f64d43ff0c18 2055 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2056
mbed_official 146:f64d43ff0c18 2057 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2058 /*!
mbed_official 146:f64d43ff0c18 2059 * @brief HW_SIM_SCGC2 - System Clock Gating Control Register 2 (RW)
mbed_official 146:f64d43ff0c18 2060 *
mbed_official 146:f64d43ff0c18 2061 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 2062 *
mbed_official 146:f64d43ff0c18 2063 * DAC0 can be accessed through both AIPS0 and AIPS1. When accessing through
mbed_official 146:f64d43ff0c18 2064 * AIPS1, define the clock gate control bits in the SCGC2. When accessing through
mbed_official 146:f64d43ff0c18 2065 * AIPS0, define the clock gate control bits in SCGC6.
mbed_official 146:f64d43ff0c18 2066 */
mbed_official 146:f64d43ff0c18 2067 typedef union _hw_sim_scgc2
mbed_official 146:f64d43ff0c18 2068 {
mbed_official 146:f64d43ff0c18 2069 uint32_t U;
mbed_official 146:f64d43ff0c18 2070 struct _hw_sim_scgc2_bitfields
mbed_official 146:f64d43ff0c18 2071 {
mbed_official 146:f64d43ff0c18 2072 uint32_t ENETb : 1; //!< [0] ENET Clock Gate Control
mbed_official 146:f64d43ff0c18 2073 uint32_t RESERVED0 : 11; //!< [11:1]
mbed_official 146:f64d43ff0c18 2074 uint32_t DAC0b : 1; //!< [12] DAC0 Clock Gate Control
mbed_official 146:f64d43ff0c18 2075 uint32_t DAC1b : 1; //!< [13] DAC1 Clock Gate Control
mbed_official 146:f64d43ff0c18 2076 uint32_t RESERVED1 : 18; //!< [31:14]
mbed_official 146:f64d43ff0c18 2077 } B;
mbed_official 146:f64d43ff0c18 2078 } hw_sim_scgc2_t;
mbed_official 146:f64d43ff0c18 2079 #endif
mbed_official 146:f64d43ff0c18 2080
mbed_official 146:f64d43ff0c18 2081 /*!
mbed_official 146:f64d43ff0c18 2082 * @name Constants and macros for entire SIM_SCGC2 register
mbed_official 146:f64d43ff0c18 2083 */
mbed_official 146:f64d43ff0c18 2084 //@{
mbed_official 146:f64d43ff0c18 2085 #define HW_SIM_SCGC2_ADDR (REGS_SIM_BASE + 0x102CU)
mbed_official 146:f64d43ff0c18 2086
mbed_official 146:f64d43ff0c18 2087 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2088 #define HW_SIM_SCGC2 (*(__IO hw_sim_scgc2_t *) HW_SIM_SCGC2_ADDR)
mbed_official 146:f64d43ff0c18 2089 #define HW_SIM_SCGC2_RD() (HW_SIM_SCGC2.U)
mbed_official 146:f64d43ff0c18 2090 #define HW_SIM_SCGC2_WR(v) (HW_SIM_SCGC2.U = (v))
mbed_official 146:f64d43ff0c18 2091 #define HW_SIM_SCGC2_SET(v) (HW_SIM_SCGC2_WR(HW_SIM_SCGC2_RD() | (v)))
mbed_official 146:f64d43ff0c18 2092 #define HW_SIM_SCGC2_CLR(v) (HW_SIM_SCGC2_WR(HW_SIM_SCGC2_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 2093 #define HW_SIM_SCGC2_TOG(v) (HW_SIM_SCGC2_WR(HW_SIM_SCGC2_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 2094 #endif
mbed_official 146:f64d43ff0c18 2095 //@}
mbed_official 146:f64d43ff0c18 2096
mbed_official 146:f64d43ff0c18 2097 /*
mbed_official 146:f64d43ff0c18 2098 * Constants & macros for individual SIM_SCGC2 bitfields
mbed_official 146:f64d43ff0c18 2099 */
mbed_official 146:f64d43ff0c18 2100
mbed_official 146:f64d43ff0c18 2101 /*!
mbed_official 146:f64d43ff0c18 2102 * @name Register SIM_SCGC2, field ENET[0] (RW)
mbed_official 146:f64d43ff0c18 2103 *
mbed_official 146:f64d43ff0c18 2104 * This bit controls the clock gate to the ENET module.
mbed_official 146:f64d43ff0c18 2105 *
mbed_official 146:f64d43ff0c18 2106 * Values:
mbed_official 146:f64d43ff0c18 2107 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 2108 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 2109 */
mbed_official 146:f64d43ff0c18 2110 //@{
mbed_official 146:f64d43ff0c18 2111 #define BP_SIM_SCGC2_ENET (0U) //!< Bit position for SIM_SCGC2_ENET.
mbed_official 146:f64d43ff0c18 2112 #define BM_SIM_SCGC2_ENET (0x00000001U) //!< Bit mask for SIM_SCGC2_ENET.
mbed_official 146:f64d43ff0c18 2113 #define BS_SIM_SCGC2_ENET (1U) //!< Bit field size in bits for SIM_SCGC2_ENET.
mbed_official 146:f64d43ff0c18 2114
mbed_official 146:f64d43ff0c18 2115 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2116 //! @brief Read current value of the SIM_SCGC2_ENET field.
mbed_official 146:f64d43ff0c18 2117 #define BR_SIM_SCGC2_ENET (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR, BP_SIM_SCGC2_ENET))
mbed_official 146:f64d43ff0c18 2118 #endif
mbed_official 146:f64d43ff0c18 2119
mbed_official 146:f64d43ff0c18 2120 //! @brief Format value for bitfield SIM_SCGC2_ENET.
mbed_official 146:f64d43ff0c18 2121 #define BF_SIM_SCGC2_ENET(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC2_ENET), uint32_t) & BM_SIM_SCGC2_ENET)
mbed_official 146:f64d43ff0c18 2122
mbed_official 146:f64d43ff0c18 2123 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2124 //! @brief Set the ENET field to a new value.
mbed_official 146:f64d43ff0c18 2125 #define BW_SIM_SCGC2_ENET(v) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR, BP_SIM_SCGC2_ENET) = (v))
mbed_official 146:f64d43ff0c18 2126 #endif
mbed_official 146:f64d43ff0c18 2127 //@}
mbed_official 146:f64d43ff0c18 2128
mbed_official 146:f64d43ff0c18 2129 /*!
mbed_official 146:f64d43ff0c18 2130 * @name Register SIM_SCGC2, field DAC0[12] (RW)
mbed_official 146:f64d43ff0c18 2131 *
mbed_official 146:f64d43ff0c18 2132 * This bit controls the clock gate to the DAC0 module.
mbed_official 146:f64d43ff0c18 2133 *
mbed_official 146:f64d43ff0c18 2134 * Values:
mbed_official 146:f64d43ff0c18 2135 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 2136 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 2137 */
mbed_official 146:f64d43ff0c18 2138 //@{
mbed_official 146:f64d43ff0c18 2139 #define BP_SIM_SCGC2_DAC0 (12U) //!< Bit position for SIM_SCGC2_DAC0.
mbed_official 146:f64d43ff0c18 2140 #define BM_SIM_SCGC2_DAC0 (0x00001000U) //!< Bit mask for SIM_SCGC2_DAC0.
mbed_official 146:f64d43ff0c18 2141 #define BS_SIM_SCGC2_DAC0 (1U) //!< Bit field size in bits for SIM_SCGC2_DAC0.
mbed_official 146:f64d43ff0c18 2142
mbed_official 146:f64d43ff0c18 2143 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2144 //! @brief Read current value of the SIM_SCGC2_DAC0 field.
mbed_official 146:f64d43ff0c18 2145 #define BR_SIM_SCGC2_DAC0 (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR, BP_SIM_SCGC2_DAC0))
mbed_official 146:f64d43ff0c18 2146 #endif
mbed_official 146:f64d43ff0c18 2147
mbed_official 146:f64d43ff0c18 2148 //! @brief Format value for bitfield SIM_SCGC2_DAC0.
mbed_official 146:f64d43ff0c18 2149 #define BF_SIM_SCGC2_DAC0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC2_DAC0), uint32_t) & BM_SIM_SCGC2_DAC0)
mbed_official 146:f64d43ff0c18 2150
mbed_official 146:f64d43ff0c18 2151 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2152 //! @brief Set the DAC0 field to a new value.
mbed_official 146:f64d43ff0c18 2153 #define BW_SIM_SCGC2_DAC0(v) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR, BP_SIM_SCGC2_DAC0) = (v))
mbed_official 146:f64d43ff0c18 2154 #endif
mbed_official 146:f64d43ff0c18 2155 //@}
mbed_official 146:f64d43ff0c18 2156
mbed_official 146:f64d43ff0c18 2157 /*!
mbed_official 146:f64d43ff0c18 2158 * @name Register SIM_SCGC2, field DAC1[13] (RW)
mbed_official 146:f64d43ff0c18 2159 *
mbed_official 146:f64d43ff0c18 2160 * This bit controls the clock gate to the DAC1 module.
mbed_official 146:f64d43ff0c18 2161 *
mbed_official 146:f64d43ff0c18 2162 * Values:
mbed_official 146:f64d43ff0c18 2163 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 2164 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 2165 */
mbed_official 146:f64d43ff0c18 2166 //@{
mbed_official 146:f64d43ff0c18 2167 #define BP_SIM_SCGC2_DAC1 (13U) //!< Bit position for SIM_SCGC2_DAC1.
mbed_official 146:f64d43ff0c18 2168 #define BM_SIM_SCGC2_DAC1 (0x00002000U) //!< Bit mask for SIM_SCGC2_DAC1.
mbed_official 146:f64d43ff0c18 2169 #define BS_SIM_SCGC2_DAC1 (1U) //!< Bit field size in bits for SIM_SCGC2_DAC1.
mbed_official 146:f64d43ff0c18 2170
mbed_official 146:f64d43ff0c18 2171 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2172 //! @brief Read current value of the SIM_SCGC2_DAC1 field.
mbed_official 146:f64d43ff0c18 2173 #define BR_SIM_SCGC2_DAC1 (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR, BP_SIM_SCGC2_DAC1))
mbed_official 146:f64d43ff0c18 2174 #endif
mbed_official 146:f64d43ff0c18 2175
mbed_official 146:f64d43ff0c18 2176 //! @brief Format value for bitfield SIM_SCGC2_DAC1.
mbed_official 146:f64d43ff0c18 2177 #define BF_SIM_SCGC2_DAC1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC2_DAC1), uint32_t) & BM_SIM_SCGC2_DAC1)
mbed_official 146:f64d43ff0c18 2178
mbed_official 146:f64d43ff0c18 2179 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2180 //! @brief Set the DAC1 field to a new value.
mbed_official 146:f64d43ff0c18 2181 #define BW_SIM_SCGC2_DAC1(v) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR, BP_SIM_SCGC2_DAC1) = (v))
mbed_official 146:f64d43ff0c18 2182 #endif
mbed_official 146:f64d43ff0c18 2183 //@}
mbed_official 146:f64d43ff0c18 2184
mbed_official 146:f64d43ff0c18 2185 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2186 // HW_SIM_SCGC3 - System Clock Gating Control Register 3
mbed_official 146:f64d43ff0c18 2187 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2188
mbed_official 146:f64d43ff0c18 2189 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2190 /*!
mbed_official 146:f64d43ff0c18 2191 * @brief HW_SIM_SCGC3 - System Clock Gating Control Register 3 (RW)
mbed_official 146:f64d43ff0c18 2192 *
mbed_official 146:f64d43ff0c18 2193 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 2194 *
mbed_official 146:f64d43ff0c18 2195 * FTM2 and RNGA can be accessed through both AIPS0 and AIPS1. When accessing
mbed_official 146:f64d43ff0c18 2196 * through AIPS1, define the clock gate control bits in the SCGC3. When accessing
mbed_official 146:f64d43ff0c18 2197 * through AIPS0, define the clock gate control bits in SCGC6.
mbed_official 146:f64d43ff0c18 2198 */
mbed_official 146:f64d43ff0c18 2199 typedef union _hw_sim_scgc3
mbed_official 146:f64d43ff0c18 2200 {
mbed_official 146:f64d43ff0c18 2201 uint32_t U;
mbed_official 146:f64d43ff0c18 2202 struct _hw_sim_scgc3_bitfields
mbed_official 146:f64d43ff0c18 2203 {
mbed_official 146:f64d43ff0c18 2204 uint32_t RNGA : 1; //!< [0] RNGA Clock Gate Control
mbed_official 146:f64d43ff0c18 2205 uint32_t RESERVED0 : 11; //!< [11:1]
mbed_official 146:f64d43ff0c18 2206 uint32_t SPI2b : 1; //!< [12] SPI2 Clock Gate Control
mbed_official 146:f64d43ff0c18 2207 uint32_t RESERVED1 : 4; //!< [16:13]
mbed_official 146:f64d43ff0c18 2208 uint32_t SDHCb : 1; //!< [17] SDHC Clock Gate Control
mbed_official 146:f64d43ff0c18 2209 uint32_t RESERVED2 : 6; //!< [23:18]
mbed_official 146:f64d43ff0c18 2210 uint32_t FTM2b : 1; //!< [24] FTM2 Clock Gate Control
mbed_official 146:f64d43ff0c18 2211 uint32_t FTM3b : 1; //!< [25] FTM3 Clock Gate Control
mbed_official 146:f64d43ff0c18 2212 uint32_t RESERVED3 : 1; //!< [26]
mbed_official 146:f64d43ff0c18 2213 uint32_t ADC1b : 1; //!< [27] ADC1 Clock Gate Control
mbed_official 146:f64d43ff0c18 2214 uint32_t RESERVED4 : 4; //!< [31:28]
mbed_official 146:f64d43ff0c18 2215 } B;
mbed_official 146:f64d43ff0c18 2216 } hw_sim_scgc3_t;
mbed_official 146:f64d43ff0c18 2217 #endif
mbed_official 146:f64d43ff0c18 2218
mbed_official 146:f64d43ff0c18 2219 /*!
mbed_official 146:f64d43ff0c18 2220 * @name Constants and macros for entire SIM_SCGC3 register
mbed_official 146:f64d43ff0c18 2221 */
mbed_official 146:f64d43ff0c18 2222 //@{
mbed_official 146:f64d43ff0c18 2223 #define HW_SIM_SCGC3_ADDR (REGS_SIM_BASE + 0x1030U)
mbed_official 146:f64d43ff0c18 2224
mbed_official 146:f64d43ff0c18 2225 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2226 #define HW_SIM_SCGC3 (*(__IO hw_sim_scgc3_t *) HW_SIM_SCGC3_ADDR)
mbed_official 146:f64d43ff0c18 2227 #define HW_SIM_SCGC3_RD() (HW_SIM_SCGC3.U)
mbed_official 146:f64d43ff0c18 2228 #define HW_SIM_SCGC3_WR(v) (HW_SIM_SCGC3.U = (v))
mbed_official 146:f64d43ff0c18 2229 #define HW_SIM_SCGC3_SET(v) (HW_SIM_SCGC3_WR(HW_SIM_SCGC3_RD() | (v)))
mbed_official 146:f64d43ff0c18 2230 #define HW_SIM_SCGC3_CLR(v) (HW_SIM_SCGC3_WR(HW_SIM_SCGC3_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 2231 #define HW_SIM_SCGC3_TOG(v) (HW_SIM_SCGC3_WR(HW_SIM_SCGC3_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 2232 #endif
mbed_official 146:f64d43ff0c18 2233 //@}
mbed_official 146:f64d43ff0c18 2234
mbed_official 146:f64d43ff0c18 2235 /*
mbed_official 146:f64d43ff0c18 2236 * Constants & macros for individual SIM_SCGC3 bitfields
mbed_official 146:f64d43ff0c18 2237 */
mbed_official 146:f64d43ff0c18 2238
mbed_official 146:f64d43ff0c18 2239 /*!
mbed_official 146:f64d43ff0c18 2240 * @name Register SIM_SCGC3, field RNGA[0] (RW)
mbed_official 146:f64d43ff0c18 2241 *
mbed_official 146:f64d43ff0c18 2242 * This bit controls the clock gate to the RNGA module.
mbed_official 146:f64d43ff0c18 2243 *
mbed_official 146:f64d43ff0c18 2244 * Values:
mbed_official 146:f64d43ff0c18 2245 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 2246 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 2247 */
mbed_official 146:f64d43ff0c18 2248 //@{
mbed_official 146:f64d43ff0c18 2249 #define BP_SIM_SCGC3_RNGA (0U) //!< Bit position for SIM_SCGC3_RNGA.
mbed_official 146:f64d43ff0c18 2250 #define BM_SIM_SCGC3_RNGA (0x00000001U) //!< Bit mask for SIM_SCGC3_RNGA.
mbed_official 146:f64d43ff0c18 2251 #define BS_SIM_SCGC3_RNGA (1U) //!< Bit field size in bits for SIM_SCGC3_RNGA.
mbed_official 146:f64d43ff0c18 2252
mbed_official 146:f64d43ff0c18 2253 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2254 //! @brief Read current value of the SIM_SCGC3_RNGA field.
mbed_official 146:f64d43ff0c18 2255 #define BR_SIM_SCGC3_RNGA (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_RNGA))
mbed_official 146:f64d43ff0c18 2256 #endif
mbed_official 146:f64d43ff0c18 2257
mbed_official 146:f64d43ff0c18 2258 //! @brief Format value for bitfield SIM_SCGC3_RNGA.
mbed_official 146:f64d43ff0c18 2259 #define BF_SIM_SCGC3_RNGA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC3_RNGA), uint32_t) & BM_SIM_SCGC3_RNGA)
mbed_official 146:f64d43ff0c18 2260
mbed_official 146:f64d43ff0c18 2261 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2262 //! @brief Set the RNGA field to a new value.
mbed_official 146:f64d43ff0c18 2263 #define BW_SIM_SCGC3_RNGA(v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_RNGA) = (v))
mbed_official 146:f64d43ff0c18 2264 #endif
mbed_official 146:f64d43ff0c18 2265 //@}
mbed_official 146:f64d43ff0c18 2266
mbed_official 146:f64d43ff0c18 2267 /*!
mbed_official 146:f64d43ff0c18 2268 * @name Register SIM_SCGC3, field SPI2[12] (RW)
mbed_official 146:f64d43ff0c18 2269 *
mbed_official 146:f64d43ff0c18 2270 * This bit controls the clock gate to the SPI2 module.
mbed_official 146:f64d43ff0c18 2271 *
mbed_official 146:f64d43ff0c18 2272 * Values:
mbed_official 146:f64d43ff0c18 2273 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 2274 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 2275 */
mbed_official 146:f64d43ff0c18 2276 //@{
mbed_official 146:f64d43ff0c18 2277 #define BP_SIM_SCGC3_SPI2 (12U) //!< Bit position for SIM_SCGC3_SPI2.
mbed_official 146:f64d43ff0c18 2278 #define BM_SIM_SCGC3_SPI2 (0x00001000U) //!< Bit mask for SIM_SCGC3_SPI2.
mbed_official 146:f64d43ff0c18 2279 #define BS_SIM_SCGC3_SPI2 (1U) //!< Bit field size in bits for SIM_SCGC3_SPI2.
mbed_official 146:f64d43ff0c18 2280
mbed_official 146:f64d43ff0c18 2281 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2282 //! @brief Read current value of the SIM_SCGC3_SPI2 field.
mbed_official 146:f64d43ff0c18 2283 #define BR_SIM_SCGC3_SPI2 (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_SPI2))
mbed_official 146:f64d43ff0c18 2284 #endif
mbed_official 146:f64d43ff0c18 2285
mbed_official 146:f64d43ff0c18 2286 //! @brief Format value for bitfield SIM_SCGC3_SPI2.
mbed_official 146:f64d43ff0c18 2287 #define BF_SIM_SCGC3_SPI2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC3_SPI2), uint32_t) & BM_SIM_SCGC3_SPI2)
mbed_official 146:f64d43ff0c18 2288
mbed_official 146:f64d43ff0c18 2289 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2290 //! @brief Set the SPI2 field to a new value.
mbed_official 146:f64d43ff0c18 2291 #define BW_SIM_SCGC3_SPI2(v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_SPI2) = (v))
mbed_official 146:f64d43ff0c18 2292 #endif
mbed_official 146:f64d43ff0c18 2293 //@}
mbed_official 146:f64d43ff0c18 2294
mbed_official 146:f64d43ff0c18 2295 /*!
mbed_official 146:f64d43ff0c18 2296 * @name Register SIM_SCGC3, field SDHC[17] (RW)
mbed_official 146:f64d43ff0c18 2297 *
mbed_official 146:f64d43ff0c18 2298 * This bit controls the clock gate to the SDHC module.
mbed_official 146:f64d43ff0c18 2299 *
mbed_official 146:f64d43ff0c18 2300 * Values:
mbed_official 146:f64d43ff0c18 2301 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 2302 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 2303 */
mbed_official 146:f64d43ff0c18 2304 //@{
mbed_official 146:f64d43ff0c18 2305 #define BP_SIM_SCGC3_SDHC (17U) //!< Bit position for SIM_SCGC3_SDHC.
mbed_official 146:f64d43ff0c18 2306 #define BM_SIM_SCGC3_SDHC (0x00020000U) //!< Bit mask for SIM_SCGC3_SDHC.
mbed_official 146:f64d43ff0c18 2307 #define BS_SIM_SCGC3_SDHC (1U) //!< Bit field size in bits for SIM_SCGC3_SDHC.
mbed_official 146:f64d43ff0c18 2308
mbed_official 146:f64d43ff0c18 2309 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2310 //! @brief Read current value of the SIM_SCGC3_SDHC field.
mbed_official 146:f64d43ff0c18 2311 #define BR_SIM_SCGC3_SDHC (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_SDHC))
mbed_official 146:f64d43ff0c18 2312 #endif
mbed_official 146:f64d43ff0c18 2313
mbed_official 146:f64d43ff0c18 2314 //! @brief Format value for bitfield SIM_SCGC3_SDHC.
mbed_official 146:f64d43ff0c18 2315 #define BF_SIM_SCGC3_SDHC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC3_SDHC), uint32_t) & BM_SIM_SCGC3_SDHC)
mbed_official 146:f64d43ff0c18 2316
mbed_official 146:f64d43ff0c18 2317 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2318 //! @brief Set the SDHC field to a new value.
mbed_official 146:f64d43ff0c18 2319 #define BW_SIM_SCGC3_SDHC(v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_SDHC) = (v))
mbed_official 146:f64d43ff0c18 2320 #endif
mbed_official 146:f64d43ff0c18 2321 //@}
mbed_official 146:f64d43ff0c18 2322
mbed_official 146:f64d43ff0c18 2323 /*!
mbed_official 146:f64d43ff0c18 2324 * @name Register SIM_SCGC3, field FTM2[24] (RW)
mbed_official 146:f64d43ff0c18 2325 *
mbed_official 146:f64d43ff0c18 2326 * This bit controls the clock gate to the FTM2 module.
mbed_official 146:f64d43ff0c18 2327 *
mbed_official 146:f64d43ff0c18 2328 * Values:
mbed_official 146:f64d43ff0c18 2329 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 2330 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 2331 */
mbed_official 146:f64d43ff0c18 2332 //@{
mbed_official 146:f64d43ff0c18 2333 #define BP_SIM_SCGC3_FTM2 (24U) //!< Bit position for SIM_SCGC3_FTM2.
mbed_official 146:f64d43ff0c18 2334 #define BM_SIM_SCGC3_FTM2 (0x01000000U) //!< Bit mask for SIM_SCGC3_FTM2.
mbed_official 146:f64d43ff0c18 2335 #define BS_SIM_SCGC3_FTM2 (1U) //!< Bit field size in bits for SIM_SCGC3_FTM2.
mbed_official 146:f64d43ff0c18 2336
mbed_official 146:f64d43ff0c18 2337 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2338 //! @brief Read current value of the SIM_SCGC3_FTM2 field.
mbed_official 146:f64d43ff0c18 2339 #define BR_SIM_SCGC3_FTM2 (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_FTM2))
mbed_official 146:f64d43ff0c18 2340 #endif
mbed_official 146:f64d43ff0c18 2341
mbed_official 146:f64d43ff0c18 2342 //! @brief Format value for bitfield SIM_SCGC3_FTM2.
mbed_official 146:f64d43ff0c18 2343 #define BF_SIM_SCGC3_FTM2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC3_FTM2), uint32_t) & BM_SIM_SCGC3_FTM2)
mbed_official 146:f64d43ff0c18 2344
mbed_official 146:f64d43ff0c18 2345 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2346 //! @brief Set the FTM2 field to a new value.
mbed_official 146:f64d43ff0c18 2347 #define BW_SIM_SCGC3_FTM2(v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_FTM2) = (v))
mbed_official 146:f64d43ff0c18 2348 #endif
mbed_official 146:f64d43ff0c18 2349 //@}
mbed_official 146:f64d43ff0c18 2350
mbed_official 146:f64d43ff0c18 2351 /*!
mbed_official 146:f64d43ff0c18 2352 * @name Register SIM_SCGC3, field FTM3[25] (RW)
mbed_official 146:f64d43ff0c18 2353 *
mbed_official 146:f64d43ff0c18 2354 * This bit controls the clock gate to the FTM3 module.
mbed_official 146:f64d43ff0c18 2355 *
mbed_official 146:f64d43ff0c18 2356 * Values:
mbed_official 146:f64d43ff0c18 2357 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 2358 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 2359 */
mbed_official 146:f64d43ff0c18 2360 //@{
mbed_official 146:f64d43ff0c18 2361 #define BP_SIM_SCGC3_FTM3 (25U) //!< Bit position for SIM_SCGC3_FTM3.
mbed_official 146:f64d43ff0c18 2362 #define BM_SIM_SCGC3_FTM3 (0x02000000U) //!< Bit mask for SIM_SCGC3_FTM3.
mbed_official 146:f64d43ff0c18 2363 #define BS_SIM_SCGC3_FTM3 (1U) //!< Bit field size in bits for SIM_SCGC3_FTM3.
mbed_official 146:f64d43ff0c18 2364
mbed_official 146:f64d43ff0c18 2365 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2366 //! @brief Read current value of the SIM_SCGC3_FTM3 field.
mbed_official 146:f64d43ff0c18 2367 #define BR_SIM_SCGC3_FTM3 (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_FTM3))
mbed_official 146:f64d43ff0c18 2368 #endif
mbed_official 146:f64d43ff0c18 2369
mbed_official 146:f64d43ff0c18 2370 //! @brief Format value for bitfield SIM_SCGC3_FTM3.
mbed_official 146:f64d43ff0c18 2371 #define BF_SIM_SCGC3_FTM3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC3_FTM3), uint32_t) & BM_SIM_SCGC3_FTM3)
mbed_official 146:f64d43ff0c18 2372
mbed_official 146:f64d43ff0c18 2373 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2374 //! @brief Set the FTM3 field to a new value.
mbed_official 146:f64d43ff0c18 2375 #define BW_SIM_SCGC3_FTM3(v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_FTM3) = (v))
mbed_official 146:f64d43ff0c18 2376 #endif
mbed_official 146:f64d43ff0c18 2377 //@}
mbed_official 146:f64d43ff0c18 2378
mbed_official 146:f64d43ff0c18 2379 /*!
mbed_official 146:f64d43ff0c18 2380 * @name Register SIM_SCGC3, field ADC1[27] (RW)
mbed_official 146:f64d43ff0c18 2381 *
mbed_official 146:f64d43ff0c18 2382 * This bit controls the clock gate to the ADC1 module.
mbed_official 146:f64d43ff0c18 2383 *
mbed_official 146:f64d43ff0c18 2384 * Values:
mbed_official 146:f64d43ff0c18 2385 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 2386 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 2387 */
mbed_official 146:f64d43ff0c18 2388 //@{
mbed_official 146:f64d43ff0c18 2389 #define BP_SIM_SCGC3_ADC1 (27U) //!< Bit position for SIM_SCGC3_ADC1.
mbed_official 146:f64d43ff0c18 2390 #define BM_SIM_SCGC3_ADC1 (0x08000000U) //!< Bit mask for SIM_SCGC3_ADC1.
mbed_official 146:f64d43ff0c18 2391 #define BS_SIM_SCGC3_ADC1 (1U) //!< Bit field size in bits for SIM_SCGC3_ADC1.
mbed_official 146:f64d43ff0c18 2392
mbed_official 146:f64d43ff0c18 2393 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2394 //! @brief Read current value of the SIM_SCGC3_ADC1 field.
mbed_official 146:f64d43ff0c18 2395 #define BR_SIM_SCGC3_ADC1 (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_ADC1))
mbed_official 146:f64d43ff0c18 2396 #endif
mbed_official 146:f64d43ff0c18 2397
mbed_official 146:f64d43ff0c18 2398 //! @brief Format value for bitfield SIM_SCGC3_ADC1.
mbed_official 146:f64d43ff0c18 2399 #define BF_SIM_SCGC3_ADC1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC3_ADC1), uint32_t) & BM_SIM_SCGC3_ADC1)
mbed_official 146:f64d43ff0c18 2400
mbed_official 146:f64d43ff0c18 2401 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2402 //! @brief Set the ADC1 field to a new value.
mbed_official 146:f64d43ff0c18 2403 #define BW_SIM_SCGC3_ADC1(v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_ADC1) = (v))
mbed_official 146:f64d43ff0c18 2404 #endif
mbed_official 146:f64d43ff0c18 2405 //@}
mbed_official 146:f64d43ff0c18 2406
mbed_official 146:f64d43ff0c18 2407 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2408 // HW_SIM_SCGC4 - System Clock Gating Control Register 4
mbed_official 146:f64d43ff0c18 2409 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2410
mbed_official 146:f64d43ff0c18 2411 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2412 /*!
mbed_official 146:f64d43ff0c18 2413 * @brief HW_SIM_SCGC4 - System Clock Gating Control Register 4 (RW)
mbed_official 146:f64d43ff0c18 2414 *
mbed_official 146:f64d43ff0c18 2415 * Reset value: 0xF0100030U
mbed_official 146:f64d43ff0c18 2416 */
mbed_official 146:f64d43ff0c18 2417 typedef union _hw_sim_scgc4
mbed_official 146:f64d43ff0c18 2418 {
mbed_official 146:f64d43ff0c18 2419 uint32_t U;
mbed_official 146:f64d43ff0c18 2420 struct _hw_sim_scgc4_bitfields
mbed_official 146:f64d43ff0c18 2421 {
mbed_official 146:f64d43ff0c18 2422 uint32_t RESERVED0 : 1; //!< [0]
mbed_official 146:f64d43ff0c18 2423 uint32_t EWMb : 1; //!< [1] EWM Clock Gate Control
mbed_official 146:f64d43ff0c18 2424 uint32_t CMTb : 1; //!< [2] CMT Clock Gate Control
mbed_official 146:f64d43ff0c18 2425 uint32_t RESERVED1 : 3; //!< [5:3]
mbed_official 146:f64d43ff0c18 2426 uint32_t I2C0b : 1; //!< [6] I2C0 Clock Gate Control
mbed_official 146:f64d43ff0c18 2427 uint32_t I2C1b : 1; //!< [7] I2C1 Clock Gate Control
mbed_official 146:f64d43ff0c18 2428 uint32_t RESERVED2 : 2; //!< [9:8]
mbed_official 146:f64d43ff0c18 2429 uint32_t UART0b : 1; //!< [10] UART0 Clock Gate Control
mbed_official 146:f64d43ff0c18 2430 uint32_t UART1b : 1; //!< [11] UART1 Clock Gate Control
mbed_official 146:f64d43ff0c18 2431 uint32_t UART2b : 1; //!< [12] UART2 Clock Gate Control
mbed_official 146:f64d43ff0c18 2432 uint32_t UART3b : 1; //!< [13] UART3 Clock Gate Control
mbed_official 146:f64d43ff0c18 2433 uint32_t RESERVED3 : 4; //!< [17:14]
mbed_official 146:f64d43ff0c18 2434 uint32_t USBOTG : 1; //!< [18] USB Clock Gate Control
mbed_official 146:f64d43ff0c18 2435 uint32_t CMP : 1; //!< [19] Comparator Clock Gate Control
mbed_official 146:f64d43ff0c18 2436 uint32_t VREFb : 1; //!< [20] VREF Clock Gate Control
mbed_official 146:f64d43ff0c18 2437 uint32_t RESERVED4 : 11; //!< [31:21]
mbed_official 146:f64d43ff0c18 2438 } B;
mbed_official 146:f64d43ff0c18 2439 } hw_sim_scgc4_t;
mbed_official 146:f64d43ff0c18 2440 #endif
mbed_official 146:f64d43ff0c18 2441
mbed_official 146:f64d43ff0c18 2442 /*!
mbed_official 146:f64d43ff0c18 2443 * @name Constants and macros for entire SIM_SCGC4 register
mbed_official 146:f64d43ff0c18 2444 */
mbed_official 146:f64d43ff0c18 2445 //@{
mbed_official 146:f64d43ff0c18 2446 #define HW_SIM_SCGC4_ADDR (REGS_SIM_BASE + 0x1034U)
mbed_official 146:f64d43ff0c18 2447
mbed_official 146:f64d43ff0c18 2448 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2449 #define HW_SIM_SCGC4 (*(__IO hw_sim_scgc4_t *) HW_SIM_SCGC4_ADDR)
mbed_official 146:f64d43ff0c18 2450 #define HW_SIM_SCGC4_RD() (HW_SIM_SCGC4.U)
mbed_official 146:f64d43ff0c18 2451 #define HW_SIM_SCGC4_WR(v) (HW_SIM_SCGC4.U = (v))
mbed_official 146:f64d43ff0c18 2452 #define HW_SIM_SCGC4_SET(v) (HW_SIM_SCGC4_WR(HW_SIM_SCGC4_RD() | (v)))
mbed_official 146:f64d43ff0c18 2453 #define HW_SIM_SCGC4_CLR(v) (HW_SIM_SCGC4_WR(HW_SIM_SCGC4_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 2454 #define HW_SIM_SCGC4_TOG(v) (HW_SIM_SCGC4_WR(HW_SIM_SCGC4_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 2455 #endif
mbed_official 146:f64d43ff0c18 2456 //@}
mbed_official 146:f64d43ff0c18 2457
mbed_official 146:f64d43ff0c18 2458 /*
mbed_official 146:f64d43ff0c18 2459 * Constants & macros for individual SIM_SCGC4 bitfields
mbed_official 146:f64d43ff0c18 2460 */
mbed_official 146:f64d43ff0c18 2461
mbed_official 146:f64d43ff0c18 2462 /*!
mbed_official 146:f64d43ff0c18 2463 * @name Register SIM_SCGC4, field EWM[1] (RW)
mbed_official 146:f64d43ff0c18 2464 *
mbed_official 146:f64d43ff0c18 2465 * This bit controls the clock gate to the EWM module.
mbed_official 146:f64d43ff0c18 2466 *
mbed_official 146:f64d43ff0c18 2467 * Values:
mbed_official 146:f64d43ff0c18 2468 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 2469 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 2470 */
mbed_official 146:f64d43ff0c18 2471 //@{
mbed_official 146:f64d43ff0c18 2472 #define BP_SIM_SCGC4_EWM (1U) //!< Bit position for SIM_SCGC4_EWM.
mbed_official 146:f64d43ff0c18 2473 #define BM_SIM_SCGC4_EWM (0x00000002U) //!< Bit mask for SIM_SCGC4_EWM.
mbed_official 146:f64d43ff0c18 2474 #define BS_SIM_SCGC4_EWM (1U) //!< Bit field size in bits for SIM_SCGC4_EWM.
mbed_official 146:f64d43ff0c18 2475
mbed_official 146:f64d43ff0c18 2476 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2477 //! @brief Read current value of the SIM_SCGC4_EWM field.
mbed_official 146:f64d43ff0c18 2478 #define BR_SIM_SCGC4_EWM (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_EWM))
mbed_official 146:f64d43ff0c18 2479 #endif
mbed_official 146:f64d43ff0c18 2480
mbed_official 146:f64d43ff0c18 2481 //! @brief Format value for bitfield SIM_SCGC4_EWM.
mbed_official 146:f64d43ff0c18 2482 #define BF_SIM_SCGC4_EWM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_EWM), uint32_t) & BM_SIM_SCGC4_EWM)
mbed_official 146:f64d43ff0c18 2483
mbed_official 146:f64d43ff0c18 2484 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2485 //! @brief Set the EWM field to a new value.
mbed_official 146:f64d43ff0c18 2486 #define BW_SIM_SCGC4_EWM(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_EWM) = (v))
mbed_official 146:f64d43ff0c18 2487 #endif
mbed_official 146:f64d43ff0c18 2488 //@}
mbed_official 146:f64d43ff0c18 2489
mbed_official 146:f64d43ff0c18 2490 /*!
mbed_official 146:f64d43ff0c18 2491 * @name Register SIM_SCGC4, field CMT[2] (RW)
mbed_official 146:f64d43ff0c18 2492 *
mbed_official 146:f64d43ff0c18 2493 * This bit controls the clock gate to the CMT module.
mbed_official 146:f64d43ff0c18 2494 *
mbed_official 146:f64d43ff0c18 2495 * Values:
mbed_official 146:f64d43ff0c18 2496 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 2497 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 2498 */
mbed_official 146:f64d43ff0c18 2499 //@{
mbed_official 146:f64d43ff0c18 2500 #define BP_SIM_SCGC4_CMT (2U) //!< Bit position for SIM_SCGC4_CMT.
mbed_official 146:f64d43ff0c18 2501 #define BM_SIM_SCGC4_CMT (0x00000004U) //!< Bit mask for SIM_SCGC4_CMT.
mbed_official 146:f64d43ff0c18 2502 #define BS_SIM_SCGC4_CMT (1U) //!< Bit field size in bits for SIM_SCGC4_CMT.
mbed_official 146:f64d43ff0c18 2503
mbed_official 146:f64d43ff0c18 2504 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2505 //! @brief Read current value of the SIM_SCGC4_CMT field.
mbed_official 146:f64d43ff0c18 2506 #define BR_SIM_SCGC4_CMT (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_CMT))
mbed_official 146:f64d43ff0c18 2507 #endif
mbed_official 146:f64d43ff0c18 2508
mbed_official 146:f64d43ff0c18 2509 //! @brief Format value for bitfield SIM_SCGC4_CMT.
mbed_official 146:f64d43ff0c18 2510 #define BF_SIM_SCGC4_CMT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_CMT), uint32_t) & BM_SIM_SCGC4_CMT)
mbed_official 146:f64d43ff0c18 2511
mbed_official 146:f64d43ff0c18 2512 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2513 //! @brief Set the CMT field to a new value.
mbed_official 146:f64d43ff0c18 2514 #define BW_SIM_SCGC4_CMT(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_CMT) = (v))
mbed_official 146:f64d43ff0c18 2515 #endif
mbed_official 146:f64d43ff0c18 2516 //@}
mbed_official 146:f64d43ff0c18 2517
mbed_official 146:f64d43ff0c18 2518 /*!
mbed_official 146:f64d43ff0c18 2519 * @name Register SIM_SCGC4, field I2C0[6] (RW)
mbed_official 146:f64d43ff0c18 2520 *
mbed_official 146:f64d43ff0c18 2521 * This bit controls the clock gate to the I 2 C0 module.
mbed_official 146:f64d43ff0c18 2522 *
mbed_official 146:f64d43ff0c18 2523 * Values:
mbed_official 146:f64d43ff0c18 2524 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 2525 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 2526 */
mbed_official 146:f64d43ff0c18 2527 //@{
mbed_official 146:f64d43ff0c18 2528 #define BP_SIM_SCGC4_I2C0 (6U) //!< Bit position for SIM_SCGC4_I2C0.
mbed_official 146:f64d43ff0c18 2529 #define BM_SIM_SCGC4_I2C0 (0x00000040U) //!< Bit mask for SIM_SCGC4_I2C0.
mbed_official 146:f64d43ff0c18 2530 #define BS_SIM_SCGC4_I2C0 (1U) //!< Bit field size in bits for SIM_SCGC4_I2C0.
mbed_official 146:f64d43ff0c18 2531
mbed_official 146:f64d43ff0c18 2532 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2533 //! @brief Read current value of the SIM_SCGC4_I2C0 field.
mbed_official 146:f64d43ff0c18 2534 #define BR_SIM_SCGC4_I2C0 (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_I2C0))
mbed_official 146:f64d43ff0c18 2535 #endif
mbed_official 146:f64d43ff0c18 2536
mbed_official 146:f64d43ff0c18 2537 //! @brief Format value for bitfield SIM_SCGC4_I2C0.
mbed_official 146:f64d43ff0c18 2538 #define BF_SIM_SCGC4_I2C0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_I2C0), uint32_t) & BM_SIM_SCGC4_I2C0)
mbed_official 146:f64d43ff0c18 2539
mbed_official 146:f64d43ff0c18 2540 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2541 //! @brief Set the I2C0 field to a new value.
mbed_official 146:f64d43ff0c18 2542 #define BW_SIM_SCGC4_I2C0(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_I2C0) = (v))
mbed_official 146:f64d43ff0c18 2543 #endif
mbed_official 146:f64d43ff0c18 2544 //@}
mbed_official 146:f64d43ff0c18 2545
mbed_official 146:f64d43ff0c18 2546 /*!
mbed_official 146:f64d43ff0c18 2547 * @name Register SIM_SCGC4, field I2C1[7] (RW)
mbed_official 146:f64d43ff0c18 2548 *
mbed_official 146:f64d43ff0c18 2549 * This bit controls the clock gate to the I 2 C1 module.
mbed_official 146:f64d43ff0c18 2550 *
mbed_official 146:f64d43ff0c18 2551 * Values:
mbed_official 146:f64d43ff0c18 2552 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 2553 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 2554 */
mbed_official 146:f64d43ff0c18 2555 //@{
mbed_official 146:f64d43ff0c18 2556 #define BP_SIM_SCGC4_I2C1 (7U) //!< Bit position for SIM_SCGC4_I2C1.
mbed_official 146:f64d43ff0c18 2557 #define BM_SIM_SCGC4_I2C1 (0x00000080U) //!< Bit mask for SIM_SCGC4_I2C1.
mbed_official 146:f64d43ff0c18 2558 #define BS_SIM_SCGC4_I2C1 (1U) //!< Bit field size in bits for SIM_SCGC4_I2C1.
mbed_official 146:f64d43ff0c18 2559
mbed_official 146:f64d43ff0c18 2560 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2561 //! @brief Read current value of the SIM_SCGC4_I2C1 field.
mbed_official 146:f64d43ff0c18 2562 #define BR_SIM_SCGC4_I2C1 (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_I2C1))
mbed_official 146:f64d43ff0c18 2563 #endif
mbed_official 146:f64d43ff0c18 2564
mbed_official 146:f64d43ff0c18 2565 //! @brief Format value for bitfield SIM_SCGC4_I2C1.
mbed_official 146:f64d43ff0c18 2566 #define BF_SIM_SCGC4_I2C1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_I2C1), uint32_t) & BM_SIM_SCGC4_I2C1)
mbed_official 146:f64d43ff0c18 2567
mbed_official 146:f64d43ff0c18 2568 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2569 //! @brief Set the I2C1 field to a new value.
mbed_official 146:f64d43ff0c18 2570 #define BW_SIM_SCGC4_I2C1(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_I2C1) = (v))
mbed_official 146:f64d43ff0c18 2571 #endif
mbed_official 146:f64d43ff0c18 2572 //@}
mbed_official 146:f64d43ff0c18 2573
mbed_official 146:f64d43ff0c18 2574 /*!
mbed_official 146:f64d43ff0c18 2575 * @name Register SIM_SCGC4, field UART0[10] (RW)
mbed_official 146:f64d43ff0c18 2576 *
mbed_official 146:f64d43ff0c18 2577 * This bit controls the clock gate to the UART0 module.
mbed_official 146:f64d43ff0c18 2578 *
mbed_official 146:f64d43ff0c18 2579 * Values:
mbed_official 146:f64d43ff0c18 2580 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 2581 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 2582 */
mbed_official 146:f64d43ff0c18 2583 //@{
mbed_official 146:f64d43ff0c18 2584 #define BP_SIM_SCGC4_UART0 (10U) //!< Bit position for SIM_SCGC4_UART0.
mbed_official 146:f64d43ff0c18 2585 #define BM_SIM_SCGC4_UART0 (0x00000400U) //!< Bit mask for SIM_SCGC4_UART0.
mbed_official 146:f64d43ff0c18 2586 #define BS_SIM_SCGC4_UART0 (1U) //!< Bit field size in bits for SIM_SCGC4_UART0.
mbed_official 146:f64d43ff0c18 2587
mbed_official 146:f64d43ff0c18 2588 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2589 //! @brief Read current value of the SIM_SCGC4_UART0 field.
mbed_official 146:f64d43ff0c18 2590 #define BR_SIM_SCGC4_UART0 (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART0))
mbed_official 146:f64d43ff0c18 2591 #endif
mbed_official 146:f64d43ff0c18 2592
mbed_official 146:f64d43ff0c18 2593 //! @brief Format value for bitfield SIM_SCGC4_UART0.
mbed_official 146:f64d43ff0c18 2594 #define BF_SIM_SCGC4_UART0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_UART0), uint32_t) & BM_SIM_SCGC4_UART0)
mbed_official 146:f64d43ff0c18 2595
mbed_official 146:f64d43ff0c18 2596 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2597 //! @brief Set the UART0 field to a new value.
mbed_official 146:f64d43ff0c18 2598 #define BW_SIM_SCGC4_UART0(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART0) = (v))
mbed_official 146:f64d43ff0c18 2599 #endif
mbed_official 146:f64d43ff0c18 2600 //@}
mbed_official 146:f64d43ff0c18 2601
mbed_official 146:f64d43ff0c18 2602 /*!
mbed_official 146:f64d43ff0c18 2603 * @name Register SIM_SCGC4, field UART1[11] (RW)
mbed_official 146:f64d43ff0c18 2604 *
mbed_official 146:f64d43ff0c18 2605 * This bit controls the clock gate to the UART1 module.
mbed_official 146:f64d43ff0c18 2606 *
mbed_official 146:f64d43ff0c18 2607 * Values:
mbed_official 146:f64d43ff0c18 2608 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 2609 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 2610 */
mbed_official 146:f64d43ff0c18 2611 //@{
mbed_official 146:f64d43ff0c18 2612 #define BP_SIM_SCGC4_UART1 (11U) //!< Bit position for SIM_SCGC4_UART1.
mbed_official 146:f64d43ff0c18 2613 #define BM_SIM_SCGC4_UART1 (0x00000800U) //!< Bit mask for SIM_SCGC4_UART1.
mbed_official 146:f64d43ff0c18 2614 #define BS_SIM_SCGC4_UART1 (1U) //!< Bit field size in bits for SIM_SCGC4_UART1.
mbed_official 146:f64d43ff0c18 2615
mbed_official 146:f64d43ff0c18 2616 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2617 //! @brief Read current value of the SIM_SCGC4_UART1 field.
mbed_official 146:f64d43ff0c18 2618 #define BR_SIM_SCGC4_UART1 (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART1))
mbed_official 146:f64d43ff0c18 2619 #endif
mbed_official 146:f64d43ff0c18 2620
mbed_official 146:f64d43ff0c18 2621 //! @brief Format value for bitfield SIM_SCGC4_UART1.
mbed_official 146:f64d43ff0c18 2622 #define BF_SIM_SCGC4_UART1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_UART1), uint32_t) & BM_SIM_SCGC4_UART1)
mbed_official 146:f64d43ff0c18 2623
mbed_official 146:f64d43ff0c18 2624 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2625 //! @brief Set the UART1 field to a new value.
mbed_official 146:f64d43ff0c18 2626 #define BW_SIM_SCGC4_UART1(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART1) = (v))
mbed_official 146:f64d43ff0c18 2627 #endif
mbed_official 146:f64d43ff0c18 2628 //@}
mbed_official 146:f64d43ff0c18 2629
mbed_official 146:f64d43ff0c18 2630 /*!
mbed_official 146:f64d43ff0c18 2631 * @name Register SIM_SCGC4, field UART2[12] (RW)
mbed_official 146:f64d43ff0c18 2632 *
mbed_official 146:f64d43ff0c18 2633 * This bit controls the clock gate to the UART2 module.
mbed_official 146:f64d43ff0c18 2634 *
mbed_official 146:f64d43ff0c18 2635 * Values:
mbed_official 146:f64d43ff0c18 2636 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 2637 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 2638 */
mbed_official 146:f64d43ff0c18 2639 //@{
mbed_official 146:f64d43ff0c18 2640 #define BP_SIM_SCGC4_UART2 (12U) //!< Bit position for SIM_SCGC4_UART2.
mbed_official 146:f64d43ff0c18 2641 #define BM_SIM_SCGC4_UART2 (0x00001000U) //!< Bit mask for SIM_SCGC4_UART2.
mbed_official 146:f64d43ff0c18 2642 #define BS_SIM_SCGC4_UART2 (1U) //!< Bit field size in bits for SIM_SCGC4_UART2.
mbed_official 146:f64d43ff0c18 2643
mbed_official 146:f64d43ff0c18 2644 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2645 //! @brief Read current value of the SIM_SCGC4_UART2 field.
mbed_official 146:f64d43ff0c18 2646 #define BR_SIM_SCGC4_UART2 (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART2))
mbed_official 146:f64d43ff0c18 2647 #endif
mbed_official 146:f64d43ff0c18 2648
mbed_official 146:f64d43ff0c18 2649 //! @brief Format value for bitfield SIM_SCGC4_UART2.
mbed_official 146:f64d43ff0c18 2650 #define BF_SIM_SCGC4_UART2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_UART2), uint32_t) & BM_SIM_SCGC4_UART2)
mbed_official 146:f64d43ff0c18 2651
mbed_official 146:f64d43ff0c18 2652 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2653 //! @brief Set the UART2 field to a new value.
mbed_official 146:f64d43ff0c18 2654 #define BW_SIM_SCGC4_UART2(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART2) = (v))
mbed_official 146:f64d43ff0c18 2655 #endif
mbed_official 146:f64d43ff0c18 2656 //@}
mbed_official 146:f64d43ff0c18 2657
mbed_official 146:f64d43ff0c18 2658 /*!
mbed_official 146:f64d43ff0c18 2659 * @name Register SIM_SCGC4, field UART3[13] (RW)
mbed_official 146:f64d43ff0c18 2660 *
mbed_official 146:f64d43ff0c18 2661 * This bit controls the clock gate to the UART3 module.
mbed_official 146:f64d43ff0c18 2662 *
mbed_official 146:f64d43ff0c18 2663 * Values:
mbed_official 146:f64d43ff0c18 2664 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 2665 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 2666 */
mbed_official 146:f64d43ff0c18 2667 //@{
mbed_official 146:f64d43ff0c18 2668 #define BP_SIM_SCGC4_UART3 (13U) //!< Bit position for SIM_SCGC4_UART3.
mbed_official 146:f64d43ff0c18 2669 #define BM_SIM_SCGC4_UART3 (0x00002000U) //!< Bit mask for SIM_SCGC4_UART3.
mbed_official 146:f64d43ff0c18 2670 #define BS_SIM_SCGC4_UART3 (1U) //!< Bit field size in bits for SIM_SCGC4_UART3.
mbed_official 146:f64d43ff0c18 2671
mbed_official 146:f64d43ff0c18 2672 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2673 //! @brief Read current value of the SIM_SCGC4_UART3 field.
mbed_official 146:f64d43ff0c18 2674 #define BR_SIM_SCGC4_UART3 (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART3))
mbed_official 146:f64d43ff0c18 2675 #endif
mbed_official 146:f64d43ff0c18 2676
mbed_official 146:f64d43ff0c18 2677 //! @brief Format value for bitfield SIM_SCGC4_UART3.
mbed_official 146:f64d43ff0c18 2678 #define BF_SIM_SCGC4_UART3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_UART3), uint32_t) & BM_SIM_SCGC4_UART3)
mbed_official 146:f64d43ff0c18 2679
mbed_official 146:f64d43ff0c18 2680 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2681 //! @brief Set the UART3 field to a new value.
mbed_official 146:f64d43ff0c18 2682 #define BW_SIM_SCGC4_UART3(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART3) = (v))
mbed_official 146:f64d43ff0c18 2683 #endif
mbed_official 146:f64d43ff0c18 2684 //@}
mbed_official 146:f64d43ff0c18 2685
mbed_official 146:f64d43ff0c18 2686 /*!
mbed_official 146:f64d43ff0c18 2687 * @name Register SIM_SCGC4, field USBOTG[18] (RW)
mbed_official 146:f64d43ff0c18 2688 *
mbed_official 146:f64d43ff0c18 2689 * This bit controls the clock gate to the USB module.
mbed_official 146:f64d43ff0c18 2690 *
mbed_official 146:f64d43ff0c18 2691 * Values:
mbed_official 146:f64d43ff0c18 2692 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 2693 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 2694 */
mbed_official 146:f64d43ff0c18 2695 //@{
mbed_official 146:f64d43ff0c18 2696 #define BP_SIM_SCGC4_USBOTG (18U) //!< Bit position for SIM_SCGC4_USBOTG.
mbed_official 146:f64d43ff0c18 2697 #define BM_SIM_SCGC4_USBOTG (0x00040000U) //!< Bit mask for SIM_SCGC4_USBOTG.
mbed_official 146:f64d43ff0c18 2698 #define BS_SIM_SCGC4_USBOTG (1U) //!< Bit field size in bits for SIM_SCGC4_USBOTG.
mbed_official 146:f64d43ff0c18 2699
mbed_official 146:f64d43ff0c18 2700 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2701 //! @brief Read current value of the SIM_SCGC4_USBOTG field.
mbed_official 146:f64d43ff0c18 2702 #define BR_SIM_SCGC4_USBOTG (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_USBOTG))
mbed_official 146:f64d43ff0c18 2703 #endif
mbed_official 146:f64d43ff0c18 2704
mbed_official 146:f64d43ff0c18 2705 //! @brief Format value for bitfield SIM_SCGC4_USBOTG.
mbed_official 146:f64d43ff0c18 2706 #define BF_SIM_SCGC4_USBOTG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_USBOTG), uint32_t) & BM_SIM_SCGC4_USBOTG)
mbed_official 146:f64d43ff0c18 2707
mbed_official 146:f64d43ff0c18 2708 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2709 //! @brief Set the USBOTG field to a new value.
mbed_official 146:f64d43ff0c18 2710 #define BW_SIM_SCGC4_USBOTG(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_USBOTG) = (v))
mbed_official 146:f64d43ff0c18 2711 #endif
mbed_official 146:f64d43ff0c18 2712 //@}
mbed_official 146:f64d43ff0c18 2713
mbed_official 146:f64d43ff0c18 2714 /*!
mbed_official 146:f64d43ff0c18 2715 * @name Register SIM_SCGC4, field CMP[19] (RW)
mbed_official 146:f64d43ff0c18 2716 *
mbed_official 146:f64d43ff0c18 2717 * This bit controls the clock gate to the comparator module.
mbed_official 146:f64d43ff0c18 2718 *
mbed_official 146:f64d43ff0c18 2719 * Values:
mbed_official 146:f64d43ff0c18 2720 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 2721 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 2722 */
mbed_official 146:f64d43ff0c18 2723 //@{
mbed_official 146:f64d43ff0c18 2724 #define BP_SIM_SCGC4_CMP (19U) //!< Bit position for SIM_SCGC4_CMP.
mbed_official 146:f64d43ff0c18 2725 #define BM_SIM_SCGC4_CMP (0x00080000U) //!< Bit mask for SIM_SCGC4_CMP.
mbed_official 146:f64d43ff0c18 2726 #define BS_SIM_SCGC4_CMP (1U) //!< Bit field size in bits for SIM_SCGC4_CMP.
mbed_official 146:f64d43ff0c18 2727
mbed_official 146:f64d43ff0c18 2728 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2729 //! @brief Read current value of the SIM_SCGC4_CMP field.
mbed_official 146:f64d43ff0c18 2730 #define BR_SIM_SCGC4_CMP (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_CMP))
mbed_official 146:f64d43ff0c18 2731 #endif
mbed_official 146:f64d43ff0c18 2732
mbed_official 146:f64d43ff0c18 2733 //! @brief Format value for bitfield SIM_SCGC4_CMP.
mbed_official 146:f64d43ff0c18 2734 #define BF_SIM_SCGC4_CMP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_CMP), uint32_t) & BM_SIM_SCGC4_CMP)
mbed_official 146:f64d43ff0c18 2735
mbed_official 146:f64d43ff0c18 2736 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2737 //! @brief Set the CMP field to a new value.
mbed_official 146:f64d43ff0c18 2738 #define BW_SIM_SCGC4_CMP(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_CMP) = (v))
mbed_official 146:f64d43ff0c18 2739 #endif
mbed_official 146:f64d43ff0c18 2740 //@}
mbed_official 146:f64d43ff0c18 2741
mbed_official 146:f64d43ff0c18 2742 /*!
mbed_official 146:f64d43ff0c18 2743 * @name Register SIM_SCGC4, field VREF[20] (RW)
mbed_official 146:f64d43ff0c18 2744 *
mbed_official 146:f64d43ff0c18 2745 * This bit controls the clock gate to the VREF module.
mbed_official 146:f64d43ff0c18 2746 *
mbed_official 146:f64d43ff0c18 2747 * Values:
mbed_official 146:f64d43ff0c18 2748 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 2749 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 2750 */
mbed_official 146:f64d43ff0c18 2751 //@{
mbed_official 146:f64d43ff0c18 2752 #define BP_SIM_SCGC4_VREF (20U) //!< Bit position for SIM_SCGC4_VREF.
mbed_official 146:f64d43ff0c18 2753 #define BM_SIM_SCGC4_VREF (0x00100000U) //!< Bit mask for SIM_SCGC4_VREF.
mbed_official 146:f64d43ff0c18 2754 #define BS_SIM_SCGC4_VREF (1U) //!< Bit field size in bits for SIM_SCGC4_VREF.
mbed_official 146:f64d43ff0c18 2755
mbed_official 146:f64d43ff0c18 2756 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2757 //! @brief Read current value of the SIM_SCGC4_VREF field.
mbed_official 146:f64d43ff0c18 2758 #define BR_SIM_SCGC4_VREF (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_VREF))
mbed_official 146:f64d43ff0c18 2759 #endif
mbed_official 146:f64d43ff0c18 2760
mbed_official 146:f64d43ff0c18 2761 //! @brief Format value for bitfield SIM_SCGC4_VREF.
mbed_official 146:f64d43ff0c18 2762 #define BF_SIM_SCGC4_VREF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_VREF), uint32_t) & BM_SIM_SCGC4_VREF)
mbed_official 146:f64d43ff0c18 2763
mbed_official 146:f64d43ff0c18 2764 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2765 //! @brief Set the VREF field to a new value.
mbed_official 146:f64d43ff0c18 2766 #define BW_SIM_SCGC4_VREF(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_VREF) = (v))
mbed_official 146:f64d43ff0c18 2767 #endif
mbed_official 146:f64d43ff0c18 2768 //@}
mbed_official 146:f64d43ff0c18 2769
mbed_official 146:f64d43ff0c18 2770 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2771 // HW_SIM_SCGC5 - System Clock Gating Control Register 5
mbed_official 146:f64d43ff0c18 2772 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2773
mbed_official 146:f64d43ff0c18 2774 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2775 /*!
mbed_official 146:f64d43ff0c18 2776 * @brief HW_SIM_SCGC5 - System Clock Gating Control Register 5 (RW)
mbed_official 146:f64d43ff0c18 2777 *
mbed_official 146:f64d43ff0c18 2778 * Reset value: 0x00040182U
mbed_official 146:f64d43ff0c18 2779 */
mbed_official 146:f64d43ff0c18 2780 typedef union _hw_sim_scgc5
mbed_official 146:f64d43ff0c18 2781 {
mbed_official 146:f64d43ff0c18 2782 uint32_t U;
mbed_official 146:f64d43ff0c18 2783 struct _hw_sim_scgc5_bitfields
mbed_official 146:f64d43ff0c18 2784 {
mbed_official 146:f64d43ff0c18 2785 uint32_t LPTMR : 1; //!< [0] Low Power Timer Access Control
mbed_official 146:f64d43ff0c18 2786 uint32_t RESERVED0 : 8; //!< [8:1]
mbed_official 146:f64d43ff0c18 2787 uint32_t PORTAb : 1; //!< [9] Port A Clock Gate Control
mbed_official 146:f64d43ff0c18 2788 uint32_t PORTBb : 1; //!< [10] Port B Clock Gate Control
mbed_official 146:f64d43ff0c18 2789 uint32_t PORTCb : 1; //!< [11] Port C Clock Gate Control
mbed_official 146:f64d43ff0c18 2790 uint32_t PORTDb : 1; //!< [12] Port D Clock Gate Control
mbed_official 146:f64d43ff0c18 2791 uint32_t PORTEb : 1; //!< [13] Port E Clock Gate Control
mbed_official 146:f64d43ff0c18 2792 uint32_t RESERVED1 : 18; //!< [31:14]
mbed_official 146:f64d43ff0c18 2793 } B;
mbed_official 146:f64d43ff0c18 2794 } hw_sim_scgc5_t;
mbed_official 146:f64d43ff0c18 2795 #endif
mbed_official 146:f64d43ff0c18 2796
mbed_official 146:f64d43ff0c18 2797 /*!
mbed_official 146:f64d43ff0c18 2798 * @name Constants and macros for entire SIM_SCGC5 register
mbed_official 146:f64d43ff0c18 2799 */
mbed_official 146:f64d43ff0c18 2800 //@{
mbed_official 146:f64d43ff0c18 2801 #define HW_SIM_SCGC5_ADDR (REGS_SIM_BASE + 0x1038U)
mbed_official 146:f64d43ff0c18 2802
mbed_official 146:f64d43ff0c18 2803 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2804 #define HW_SIM_SCGC5 (*(__IO hw_sim_scgc5_t *) HW_SIM_SCGC5_ADDR)
mbed_official 146:f64d43ff0c18 2805 #define HW_SIM_SCGC5_RD() (HW_SIM_SCGC5.U)
mbed_official 146:f64d43ff0c18 2806 #define HW_SIM_SCGC5_WR(v) (HW_SIM_SCGC5.U = (v))
mbed_official 146:f64d43ff0c18 2807 #define HW_SIM_SCGC5_SET(v) (HW_SIM_SCGC5_WR(HW_SIM_SCGC5_RD() | (v)))
mbed_official 146:f64d43ff0c18 2808 #define HW_SIM_SCGC5_CLR(v) (HW_SIM_SCGC5_WR(HW_SIM_SCGC5_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 2809 #define HW_SIM_SCGC5_TOG(v) (HW_SIM_SCGC5_WR(HW_SIM_SCGC5_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 2810 #endif
mbed_official 146:f64d43ff0c18 2811 //@}
mbed_official 146:f64d43ff0c18 2812
mbed_official 146:f64d43ff0c18 2813 /*
mbed_official 146:f64d43ff0c18 2814 * Constants & macros for individual SIM_SCGC5 bitfields
mbed_official 146:f64d43ff0c18 2815 */
mbed_official 146:f64d43ff0c18 2816
mbed_official 146:f64d43ff0c18 2817 /*!
mbed_official 146:f64d43ff0c18 2818 * @name Register SIM_SCGC5, field LPTMR[0] (RW)
mbed_official 146:f64d43ff0c18 2819 *
mbed_official 146:f64d43ff0c18 2820 * This bit controls software access to the Low Power Timer module.
mbed_official 146:f64d43ff0c18 2821 *
mbed_official 146:f64d43ff0c18 2822 * Values:
mbed_official 146:f64d43ff0c18 2823 * - 0 - Access disabled
mbed_official 146:f64d43ff0c18 2824 * - 1 - Access enabled
mbed_official 146:f64d43ff0c18 2825 */
mbed_official 146:f64d43ff0c18 2826 //@{
mbed_official 146:f64d43ff0c18 2827 #define BP_SIM_SCGC5_LPTMR (0U) //!< Bit position for SIM_SCGC5_LPTMR.
mbed_official 146:f64d43ff0c18 2828 #define BM_SIM_SCGC5_LPTMR (0x00000001U) //!< Bit mask for SIM_SCGC5_LPTMR.
mbed_official 146:f64d43ff0c18 2829 #define BS_SIM_SCGC5_LPTMR (1U) //!< Bit field size in bits for SIM_SCGC5_LPTMR.
mbed_official 146:f64d43ff0c18 2830
mbed_official 146:f64d43ff0c18 2831 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2832 //! @brief Read current value of the SIM_SCGC5_LPTMR field.
mbed_official 146:f64d43ff0c18 2833 #define BR_SIM_SCGC5_LPTMR (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_LPTMR))
mbed_official 146:f64d43ff0c18 2834 #endif
mbed_official 146:f64d43ff0c18 2835
mbed_official 146:f64d43ff0c18 2836 //! @brief Format value for bitfield SIM_SCGC5_LPTMR.
mbed_official 146:f64d43ff0c18 2837 #define BF_SIM_SCGC5_LPTMR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC5_LPTMR), uint32_t) & BM_SIM_SCGC5_LPTMR)
mbed_official 146:f64d43ff0c18 2838
mbed_official 146:f64d43ff0c18 2839 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2840 //! @brief Set the LPTMR field to a new value.
mbed_official 146:f64d43ff0c18 2841 #define BW_SIM_SCGC5_LPTMR(v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_LPTMR) = (v))
mbed_official 146:f64d43ff0c18 2842 #endif
mbed_official 146:f64d43ff0c18 2843 //@}
mbed_official 146:f64d43ff0c18 2844
mbed_official 146:f64d43ff0c18 2845 /*!
mbed_official 146:f64d43ff0c18 2846 * @name Register SIM_SCGC5, field PORTA[9] (RW)
mbed_official 146:f64d43ff0c18 2847 *
mbed_official 146:f64d43ff0c18 2848 * This bit controls the clock gate to the Port A module.
mbed_official 146:f64d43ff0c18 2849 *
mbed_official 146:f64d43ff0c18 2850 * Values:
mbed_official 146:f64d43ff0c18 2851 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 2852 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 2853 */
mbed_official 146:f64d43ff0c18 2854 //@{
mbed_official 146:f64d43ff0c18 2855 #define BP_SIM_SCGC5_PORTA (9U) //!< Bit position for SIM_SCGC5_PORTA.
mbed_official 146:f64d43ff0c18 2856 #define BM_SIM_SCGC5_PORTA (0x00000200U) //!< Bit mask for SIM_SCGC5_PORTA.
mbed_official 146:f64d43ff0c18 2857 #define BS_SIM_SCGC5_PORTA (1U) //!< Bit field size in bits for SIM_SCGC5_PORTA.
mbed_official 146:f64d43ff0c18 2858
mbed_official 146:f64d43ff0c18 2859 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2860 //! @brief Read current value of the SIM_SCGC5_PORTA field.
mbed_official 146:f64d43ff0c18 2861 #define BR_SIM_SCGC5_PORTA (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTA))
mbed_official 146:f64d43ff0c18 2862 #endif
mbed_official 146:f64d43ff0c18 2863
mbed_official 146:f64d43ff0c18 2864 //! @brief Format value for bitfield SIM_SCGC5_PORTA.
mbed_official 146:f64d43ff0c18 2865 #define BF_SIM_SCGC5_PORTA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC5_PORTA), uint32_t) & BM_SIM_SCGC5_PORTA)
mbed_official 146:f64d43ff0c18 2866
mbed_official 146:f64d43ff0c18 2867 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2868 //! @brief Set the PORTA field to a new value.
mbed_official 146:f64d43ff0c18 2869 #define BW_SIM_SCGC5_PORTA(v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTA) = (v))
mbed_official 146:f64d43ff0c18 2870 #endif
mbed_official 146:f64d43ff0c18 2871 //@}
mbed_official 146:f64d43ff0c18 2872
mbed_official 146:f64d43ff0c18 2873 /*!
mbed_official 146:f64d43ff0c18 2874 * @name Register SIM_SCGC5, field PORTB[10] (RW)
mbed_official 146:f64d43ff0c18 2875 *
mbed_official 146:f64d43ff0c18 2876 * This bit controls the clock gate to the Port B module.
mbed_official 146:f64d43ff0c18 2877 *
mbed_official 146:f64d43ff0c18 2878 * Values:
mbed_official 146:f64d43ff0c18 2879 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 2880 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 2881 */
mbed_official 146:f64d43ff0c18 2882 //@{
mbed_official 146:f64d43ff0c18 2883 #define BP_SIM_SCGC5_PORTB (10U) //!< Bit position for SIM_SCGC5_PORTB.
mbed_official 146:f64d43ff0c18 2884 #define BM_SIM_SCGC5_PORTB (0x00000400U) //!< Bit mask for SIM_SCGC5_PORTB.
mbed_official 146:f64d43ff0c18 2885 #define BS_SIM_SCGC5_PORTB (1U) //!< Bit field size in bits for SIM_SCGC5_PORTB.
mbed_official 146:f64d43ff0c18 2886
mbed_official 146:f64d43ff0c18 2887 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2888 //! @brief Read current value of the SIM_SCGC5_PORTB field.
mbed_official 146:f64d43ff0c18 2889 #define BR_SIM_SCGC5_PORTB (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTB))
mbed_official 146:f64d43ff0c18 2890 #endif
mbed_official 146:f64d43ff0c18 2891
mbed_official 146:f64d43ff0c18 2892 //! @brief Format value for bitfield SIM_SCGC5_PORTB.
mbed_official 146:f64d43ff0c18 2893 #define BF_SIM_SCGC5_PORTB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC5_PORTB), uint32_t) & BM_SIM_SCGC5_PORTB)
mbed_official 146:f64d43ff0c18 2894
mbed_official 146:f64d43ff0c18 2895 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2896 //! @brief Set the PORTB field to a new value.
mbed_official 146:f64d43ff0c18 2897 #define BW_SIM_SCGC5_PORTB(v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTB) = (v))
mbed_official 146:f64d43ff0c18 2898 #endif
mbed_official 146:f64d43ff0c18 2899 //@}
mbed_official 146:f64d43ff0c18 2900
mbed_official 146:f64d43ff0c18 2901 /*!
mbed_official 146:f64d43ff0c18 2902 * @name Register SIM_SCGC5, field PORTC[11] (RW)
mbed_official 146:f64d43ff0c18 2903 *
mbed_official 146:f64d43ff0c18 2904 * This bit controls the clock gate to the Port C module.
mbed_official 146:f64d43ff0c18 2905 *
mbed_official 146:f64d43ff0c18 2906 * Values:
mbed_official 146:f64d43ff0c18 2907 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 2908 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 2909 */
mbed_official 146:f64d43ff0c18 2910 //@{
mbed_official 146:f64d43ff0c18 2911 #define BP_SIM_SCGC5_PORTC (11U) //!< Bit position for SIM_SCGC5_PORTC.
mbed_official 146:f64d43ff0c18 2912 #define BM_SIM_SCGC5_PORTC (0x00000800U) //!< Bit mask for SIM_SCGC5_PORTC.
mbed_official 146:f64d43ff0c18 2913 #define BS_SIM_SCGC5_PORTC (1U) //!< Bit field size in bits for SIM_SCGC5_PORTC.
mbed_official 146:f64d43ff0c18 2914
mbed_official 146:f64d43ff0c18 2915 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2916 //! @brief Read current value of the SIM_SCGC5_PORTC field.
mbed_official 146:f64d43ff0c18 2917 #define BR_SIM_SCGC5_PORTC (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTC))
mbed_official 146:f64d43ff0c18 2918 #endif
mbed_official 146:f64d43ff0c18 2919
mbed_official 146:f64d43ff0c18 2920 //! @brief Format value for bitfield SIM_SCGC5_PORTC.
mbed_official 146:f64d43ff0c18 2921 #define BF_SIM_SCGC5_PORTC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC5_PORTC), uint32_t) & BM_SIM_SCGC5_PORTC)
mbed_official 146:f64d43ff0c18 2922
mbed_official 146:f64d43ff0c18 2923 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2924 //! @brief Set the PORTC field to a new value.
mbed_official 146:f64d43ff0c18 2925 #define BW_SIM_SCGC5_PORTC(v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTC) = (v))
mbed_official 146:f64d43ff0c18 2926 #endif
mbed_official 146:f64d43ff0c18 2927 //@}
mbed_official 146:f64d43ff0c18 2928
mbed_official 146:f64d43ff0c18 2929 /*!
mbed_official 146:f64d43ff0c18 2930 * @name Register SIM_SCGC5, field PORTD[12] (RW)
mbed_official 146:f64d43ff0c18 2931 *
mbed_official 146:f64d43ff0c18 2932 * This bit controls the clock gate to the Port D module.
mbed_official 146:f64d43ff0c18 2933 *
mbed_official 146:f64d43ff0c18 2934 * Values:
mbed_official 146:f64d43ff0c18 2935 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 2936 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 2937 */
mbed_official 146:f64d43ff0c18 2938 //@{
mbed_official 146:f64d43ff0c18 2939 #define BP_SIM_SCGC5_PORTD (12U) //!< Bit position for SIM_SCGC5_PORTD.
mbed_official 146:f64d43ff0c18 2940 #define BM_SIM_SCGC5_PORTD (0x00001000U) //!< Bit mask for SIM_SCGC5_PORTD.
mbed_official 146:f64d43ff0c18 2941 #define BS_SIM_SCGC5_PORTD (1U) //!< Bit field size in bits for SIM_SCGC5_PORTD.
mbed_official 146:f64d43ff0c18 2942
mbed_official 146:f64d43ff0c18 2943 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2944 //! @brief Read current value of the SIM_SCGC5_PORTD field.
mbed_official 146:f64d43ff0c18 2945 #define BR_SIM_SCGC5_PORTD (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTD))
mbed_official 146:f64d43ff0c18 2946 #endif
mbed_official 146:f64d43ff0c18 2947
mbed_official 146:f64d43ff0c18 2948 //! @brief Format value for bitfield SIM_SCGC5_PORTD.
mbed_official 146:f64d43ff0c18 2949 #define BF_SIM_SCGC5_PORTD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC5_PORTD), uint32_t) & BM_SIM_SCGC5_PORTD)
mbed_official 146:f64d43ff0c18 2950
mbed_official 146:f64d43ff0c18 2951 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2952 //! @brief Set the PORTD field to a new value.
mbed_official 146:f64d43ff0c18 2953 #define BW_SIM_SCGC5_PORTD(v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTD) = (v))
mbed_official 146:f64d43ff0c18 2954 #endif
mbed_official 146:f64d43ff0c18 2955 //@}
mbed_official 146:f64d43ff0c18 2956
mbed_official 146:f64d43ff0c18 2957 /*!
mbed_official 146:f64d43ff0c18 2958 * @name Register SIM_SCGC5, field PORTE[13] (RW)
mbed_official 146:f64d43ff0c18 2959 *
mbed_official 146:f64d43ff0c18 2960 * This bit controls the clock gate to the Port E module.
mbed_official 146:f64d43ff0c18 2961 *
mbed_official 146:f64d43ff0c18 2962 * Values:
mbed_official 146:f64d43ff0c18 2963 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 2964 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 2965 */
mbed_official 146:f64d43ff0c18 2966 //@{
mbed_official 146:f64d43ff0c18 2967 #define BP_SIM_SCGC5_PORTE (13U) //!< Bit position for SIM_SCGC5_PORTE.
mbed_official 146:f64d43ff0c18 2968 #define BM_SIM_SCGC5_PORTE (0x00002000U) //!< Bit mask for SIM_SCGC5_PORTE.
mbed_official 146:f64d43ff0c18 2969 #define BS_SIM_SCGC5_PORTE (1U) //!< Bit field size in bits for SIM_SCGC5_PORTE.
mbed_official 146:f64d43ff0c18 2970
mbed_official 146:f64d43ff0c18 2971 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2972 //! @brief Read current value of the SIM_SCGC5_PORTE field.
mbed_official 146:f64d43ff0c18 2973 #define BR_SIM_SCGC5_PORTE (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTE))
mbed_official 146:f64d43ff0c18 2974 #endif
mbed_official 146:f64d43ff0c18 2975
mbed_official 146:f64d43ff0c18 2976 //! @brief Format value for bitfield SIM_SCGC5_PORTE.
mbed_official 146:f64d43ff0c18 2977 #define BF_SIM_SCGC5_PORTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC5_PORTE), uint32_t) & BM_SIM_SCGC5_PORTE)
mbed_official 146:f64d43ff0c18 2978
mbed_official 146:f64d43ff0c18 2979 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2980 //! @brief Set the PORTE field to a new value.
mbed_official 146:f64d43ff0c18 2981 #define BW_SIM_SCGC5_PORTE(v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTE) = (v))
mbed_official 146:f64d43ff0c18 2982 #endif
mbed_official 146:f64d43ff0c18 2983 //@}
mbed_official 146:f64d43ff0c18 2984
mbed_official 146:f64d43ff0c18 2985 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2986 // HW_SIM_SCGC6 - System Clock Gating Control Register 6
mbed_official 146:f64d43ff0c18 2987 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2988
mbed_official 146:f64d43ff0c18 2989 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2990 /*!
mbed_official 146:f64d43ff0c18 2991 * @brief HW_SIM_SCGC6 - System Clock Gating Control Register 6 (RW)
mbed_official 146:f64d43ff0c18 2992 *
mbed_official 146:f64d43ff0c18 2993 * Reset value: 0x40000001U
mbed_official 146:f64d43ff0c18 2994 *
mbed_official 146:f64d43ff0c18 2995 * DAC0, FTM2, and RNGA can be accessed through both AIPS0 and AIPS1. When
mbed_official 146:f64d43ff0c18 2996 * accessing through AIPS1, define the clock gate control bits in the SCGC2 and SCGC3.
mbed_official 146:f64d43ff0c18 2997 * When accessing through AIPS0, define the clock gate control bits in SCGC6.
mbed_official 146:f64d43ff0c18 2998 */
mbed_official 146:f64d43ff0c18 2999 typedef union _hw_sim_scgc6
mbed_official 146:f64d43ff0c18 3000 {
mbed_official 146:f64d43ff0c18 3001 uint32_t U;
mbed_official 146:f64d43ff0c18 3002 struct _hw_sim_scgc6_bitfields
mbed_official 146:f64d43ff0c18 3003 {
mbed_official 146:f64d43ff0c18 3004 uint32_t FTF : 1; //!< [0] Flash Memory Clock Gate Control
mbed_official 146:f64d43ff0c18 3005 uint32_t DMAMUXb : 1; //!< [1] DMA Mux Clock Gate Control
mbed_official 146:f64d43ff0c18 3006 uint32_t RESERVED0 : 2; //!< [3:2]
mbed_official 146:f64d43ff0c18 3007 uint32_t FLEXCAN0 : 1; //!< [4] FlexCAN0 Clock Gate Control
mbed_official 146:f64d43ff0c18 3008 uint32_t RESERVED1 : 4; //!< [8:5]
mbed_official 146:f64d43ff0c18 3009 uint32_t RNGA : 1; //!< [9] RNGA Clock Gate Control
mbed_official 146:f64d43ff0c18 3010 uint32_t RESERVED2 : 2; //!< [11:10]
mbed_official 146:f64d43ff0c18 3011 uint32_t SPI0b : 1; //!< [12] SPI0 Clock Gate Control
mbed_official 146:f64d43ff0c18 3012 uint32_t SPI1b : 1; //!< [13] SPI1 Clock Gate Control
mbed_official 146:f64d43ff0c18 3013 uint32_t RESERVED3 : 1; //!< [14]
mbed_official 146:f64d43ff0c18 3014 uint32_t I2S : 1; //!< [15] I2S Clock Gate Control
mbed_official 146:f64d43ff0c18 3015 uint32_t RESERVED4 : 2; //!< [17:16]
mbed_official 146:f64d43ff0c18 3016 uint32_t CRCb : 1; //!< [18] CRC Clock Gate Control
mbed_official 146:f64d43ff0c18 3017 uint32_t RESERVED5 : 2; //!< [20:19]
mbed_official 146:f64d43ff0c18 3018 uint32_t USBDCDb : 1; //!< [21] USB DCD Clock Gate Control
mbed_official 146:f64d43ff0c18 3019 uint32_t PDB : 1; //!< [22] PDB Clock Gate Control
mbed_official 146:f64d43ff0c18 3020 uint32_t PITb : 1; //!< [23] PIT Clock Gate Control
mbed_official 146:f64d43ff0c18 3021 uint32_t FTM0b : 1; //!< [24] FTM0 Clock Gate Control
mbed_official 146:f64d43ff0c18 3022 uint32_t FTM1b : 1; //!< [25] FTM1 Clock Gate Control
mbed_official 146:f64d43ff0c18 3023 uint32_t FTM2b : 1; //!< [26] FTM2 Clock Gate Control
mbed_official 146:f64d43ff0c18 3024 uint32_t ADC0b : 1; //!< [27] ADC0 Clock Gate Control
mbed_official 146:f64d43ff0c18 3025 uint32_t RESERVED6 : 1; //!< [28]
mbed_official 146:f64d43ff0c18 3026 uint32_t RTCb : 1; //!< [29] RTC Access Control
mbed_official 146:f64d43ff0c18 3027 uint32_t RESERVED7 : 1; //!< [30]
mbed_official 146:f64d43ff0c18 3028 uint32_t DAC0b : 1; //!< [31] DAC0 Clock Gate Control
mbed_official 146:f64d43ff0c18 3029 } B;
mbed_official 146:f64d43ff0c18 3030 } hw_sim_scgc6_t;
mbed_official 146:f64d43ff0c18 3031 #endif
mbed_official 146:f64d43ff0c18 3032
mbed_official 146:f64d43ff0c18 3033 /*!
mbed_official 146:f64d43ff0c18 3034 * @name Constants and macros for entire SIM_SCGC6 register
mbed_official 146:f64d43ff0c18 3035 */
mbed_official 146:f64d43ff0c18 3036 //@{
mbed_official 146:f64d43ff0c18 3037 #define HW_SIM_SCGC6_ADDR (REGS_SIM_BASE + 0x103CU)
mbed_official 146:f64d43ff0c18 3038
mbed_official 146:f64d43ff0c18 3039 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3040 #define HW_SIM_SCGC6 (*(__IO hw_sim_scgc6_t *) HW_SIM_SCGC6_ADDR)
mbed_official 146:f64d43ff0c18 3041 #define HW_SIM_SCGC6_RD() (HW_SIM_SCGC6.U)
mbed_official 146:f64d43ff0c18 3042 #define HW_SIM_SCGC6_WR(v) (HW_SIM_SCGC6.U = (v))
mbed_official 146:f64d43ff0c18 3043 #define HW_SIM_SCGC6_SET(v) (HW_SIM_SCGC6_WR(HW_SIM_SCGC6_RD() | (v)))
mbed_official 146:f64d43ff0c18 3044 #define HW_SIM_SCGC6_CLR(v) (HW_SIM_SCGC6_WR(HW_SIM_SCGC6_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 3045 #define HW_SIM_SCGC6_TOG(v) (HW_SIM_SCGC6_WR(HW_SIM_SCGC6_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 3046 #endif
mbed_official 146:f64d43ff0c18 3047 //@}
mbed_official 146:f64d43ff0c18 3048
mbed_official 146:f64d43ff0c18 3049 /*
mbed_official 146:f64d43ff0c18 3050 * Constants & macros for individual SIM_SCGC6 bitfields
mbed_official 146:f64d43ff0c18 3051 */
mbed_official 146:f64d43ff0c18 3052
mbed_official 146:f64d43ff0c18 3053 /*!
mbed_official 146:f64d43ff0c18 3054 * @name Register SIM_SCGC6, field FTF[0] (RW)
mbed_official 146:f64d43ff0c18 3055 *
mbed_official 146:f64d43ff0c18 3056 * This bit controls the clock gate to the flash memory. Flash reads are still
mbed_official 146:f64d43ff0c18 3057 * supported while the flash memory is clock gated, but entry into low power modes
mbed_official 146:f64d43ff0c18 3058 * is blocked.
mbed_official 146:f64d43ff0c18 3059 *
mbed_official 146:f64d43ff0c18 3060 * Values:
mbed_official 146:f64d43ff0c18 3061 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 3062 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 3063 */
mbed_official 146:f64d43ff0c18 3064 //@{
mbed_official 146:f64d43ff0c18 3065 #define BP_SIM_SCGC6_FTF (0U) //!< Bit position for SIM_SCGC6_FTF.
mbed_official 146:f64d43ff0c18 3066 #define BM_SIM_SCGC6_FTF (0x00000001U) //!< Bit mask for SIM_SCGC6_FTF.
mbed_official 146:f64d43ff0c18 3067 #define BS_SIM_SCGC6_FTF (1U) //!< Bit field size in bits for SIM_SCGC6_FTF.
mbed_official 146:f64d43ff0c18 3068
mbed_official 146:f64d43ff0c18 3069 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3070 //! @brief Read current value of the SIM_SCGC6_FTF field.
mbed_official 146:f64d43ff0c18 3071 #define BR_SIM_SCGC6_FTF (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTF))
mbed_official 146:f64d43ff0c18 3072 #endif
mbed_official 146:f64d43ff0c18 3073
mbed_official 146:f64d43ff0c18 3074 //! @brief Format value for bitfield SIM_SCGC6_FTF.
mbed_official 146:f64d43ff0c18 3075 #define BF_SIM_SCGC6_FTF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_FTF), uint32_t) & BM_SIM_SCGC6_FTF)
mbed_official 146:f64d43ff0c18 3076
mbed_official 146:f64d43ff0c18 3077 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3078 //! @brief Set the FTF field to a new value.
mbed_official 146:f64d43ff0c18 3079 #define BW_SIM_SCGC6_FTF(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTF) = (v))
mbed_official 146:f64d43ff0c18 3080 #endif
mbed_official 146:f64d43ff0c18 3081 //@}
mbed_official 146:f64d43ff0c18 3082
mbed_official 146:f64d43ff0c18 3083 /*!
mbed_official 146:f64d43ff0c18 3084 * @name Register SIM_SCGC6, field DMAMUX[1] (RW)
mbed_official 146:f64d43ff0c18 3085 *
mbed_official 146:f64d43ff0c18 3086 * This bit controls the clock gate to the DMA Mux module.
mbed_official 146:f64d43ff0c18 3087 *
mbed_official 146:f64d43ff0c18 3088 * Values:
mbed_official 146:f64d43ff0c18 3089 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 3090 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 3091 */
mbed_official 146:f64d43ff0c18 3092 //@{
mbed_official 146:f64d43ff0c18 3093 #define BP_SIM_SCGC6_DMAMUX (1U) //!< Bit position for SIM_SCGC6_DMAMUX.
mbed_official 146:f64d43ff0c18 3094 #define BM_SIM_SCGC6_DMAMUX (0x00000002U) //!< Bit mask for SIM_SCGC6_DMAMUX.
mbed_official 146:f64d43ff0c18 3095 #define BS_SIM_SCGC6_DMAMUX (1U) //!< Bit field size in bits for SIM_SCGC6_DMAMUX.
mbed_official 146:f64d43ff0c18 3096
mbed_official 146:f64d43ff0c18 3097 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3098 //! @brief Read current value of the SIM_SCGC6_DMAMUX field.
mbed_official 146:f64d43ff0c18 3099 #define BR_SIM_SCGC6_DMAMUX (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_DMAMUX))
mbed_official 146:f64d43ff0c18 3100 #endif
mbed_official 146:f64d43ff0c18 3101
mbed_official 146:f64d43ff0c18 3102 //! @brief Format value for bitfield SIM_SCGC6_DMAMUX.
mbed_official 146:f64d43ff0c18 3103 #define BF_SIM_SCGC6_DMAMUX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_DMAMUX), uint32_t) & BM_SIM_SCGC6_DMAMUX)
mbed_official 146:f64d43ff0c18 3104
mbed_official 146:f64d43ff0c18 3105 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3106 //! @brief Set the DMAMUX field to a new value.
mbed_official 146:f64d43ff0c18 3107 #define BW_SIM_SCGC6_DMAMUX(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_DMAMUX) = (v))
mbed_official 146:f64d43ff0c18 3108 #endif
mbed_official 146:f64d43ff0c18 3109 //@}
mbed_official 146:f64d43ff0c18 3110
mbed_official 146:f64d43ff0c18 3111 /*!
mbed_official 146:f64d43ff0c18 3112 * @name Register SIM_SCGC6, field FLEXCAN0[4] (RW)
mbed_official 146:f64d43ff0c18 3113 *
mbed_official 146:f64d43ff0c18 3114 * This bit controls the clock gate to the FlexCAN0 module.
mbed_official 146:f64d43ff0c18 3115 *
mbed_official 146:f64d43ff0c18 3116 * Values:
mbed_official 146:f64d43ff0c18 3117 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 3118 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 3119 */
mbed_official 146:f64d43ff0c18 3120 //@{
mbed_official 146:f64d43ff0c18 3121 #define BP_SIM_SCGC6_FLEXCAN0 (4U) //!< Bit position for SIM_SCGC6_FLEXCAN0.
mbed_official 146:f64d43ff0c18 3122 #define BM_SIM_SCGC6_FLEXCAN0 (0x00000010U) //!< Bit mask for SIM_SCGC6_FLEXCAN0.
mbed_official 146:f64d43ff0c18 3123 #define BS_SIM_SCGC6_FLEXCAN0 (1U) //!< Bit field size in bits for SIM_SCGC6_FLEXCAN0.
mbed_official 146:f64d43ff0c18 3124
mbed_official 146:f64d43ff0c18 3125 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3126 //! @brief Read current value of the SIM_SCGC6_FLEXCAN0 field.
mbed_official 146:f64d43ff0c18 3127 #define BR_SIM_SCGC6_FLEXCAN0 (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FLEXCAN0))
mbed_official 146:f64d43ff0c18 3128 #endif
mbed_official 146:f64d43ff0c18 3129
mbed_official 146:f64d43ff0c18 3130 //! @brief Format value for bitfield SIM_SCGC6_FLEXCAN0.
mbed_official 146:f64d43ff0c18 3131 #define BF_SIM_SCGC6_FLEXCAN0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_FLEXCAN0), uint32_t) & BM_SIM_SCGC6_FLEXCAN0)
mbed_official 146:f64d43ff0c18 3132
mbed_official 146:f64d43ff0c18 3133 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3134 //! @brief Set the FLEXCAN0 field to a new value.
mbed_official 146:f64d43ff0c18 3135 #define BW_SIM_SCGC6_FLEXCAN0(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FLEXCAN0) = (v))
mbed_official 146:f64d43ff0c18 3136 #endif
mbed_official 146:f64d43ff0c18 3137 //@}
mbed_official 146:f64d43ff0c18 3138
mbed_official 146:f64d43ff0c18 3139 /*!
mbed_official 146:f64d43ff0c18 3140 * @name Register SIM_SCGC6, field RNGA[9] (RW)
mbed_official 146:f64d43ff0c18 3141 *
mbed_official 146:f64d43ff0c18 3142 * This bit controls the clock gate to the RNGA module.
mbed_official 146:f64d43ff0c18 3143 */
mbed_official 146:f64d43ff0c18 3144 //@{
mbed_official 146:f64d43ff0c18 3145 #define BP_SIM_SCGC6_RNGA (9U) //!< Bit position for SIM_SCGC6_RNGA.
mbed_official 146:f64d43ff0c18 3146 #define BM_SIM_SCGC6_RNGA (0x00000200U) //!< Bit mask for SIM_SCGC6_RNGA.
mbed_official 146:f64d43ff0c18 3147 #define BS_SIM_SCGC6_RNGA (1U) //!< Bit field size in bits for SIM_SCGC6_RNGA.
mbed_official 146:f64d43ff0c18 3148
mbed_official 146:f64d43ff0c18 3149 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3150 //! @brief Read current value of the SIM_SCGC6_RNGA field.
mbed_official 146:f64d43ff0c18 3151 #define BR_SIM_SCGC6_RNGA (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_RNGA))
mbed_official 146:f64d43ff0c18 3152 #endif
mbed_official 146:f64d43ff0c18 3153
mbed_official 146:f64d43ff0c18 3154 //! @brief Format value for bitfield SIM_SCGC6_RNGA.
mbed_official 146:f64d43ff0c18 3155 #define BF_SIM_SCGC6_RNGA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_RNGA), uint32_t) & BM_SIM_SCGC6_RNGA)
mbed_official 146:f64d43ff0c18 3156
mbed_official 146:f64d43ff0c18 3157 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3158 //! @brief Set the RNGA field to a new value.
mbed_official 146:f64d43ff0c18 3159 #define BW_SIM_SCGC6_RNGA(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_RNGA) = (v))
mbed_official 146:f64d43ff0c18 3160 #endif
mbed_official 146:f64d43ff0c18 3161 //@}
mbed_official 146:f64d43ff0c18 3162
mbed_official 146:f64d43ff0c18 3163 /*!
mbed_official 146:f64d43ff0c18 3164 * @name Register SIM_SCGC6, field SPI0[12] (RW)
mbed_official 146:f64d43ff0c18 3165 *
mbed_official 146:f64d43ff0c18 3166 * This bit controls the clock gate to the SPI0 module.
mbed_official 146:f64d43ff0c18 3167 *
mbed_official 146:f64d43ff0c18 3168 * Values:
mbed_official 146:f64d43ff0c18 3169 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 3170 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 3171 */
mbed_official 146:f64d43ff0c18 3172 //@{
mbed_official 146:f64d43ff0c18 3173 #define BP_SIM_SCGC6_SPI0 (12U) //!< Bit position for SIM_SCGC6_SPI0.
mbed_official 146:f64d43ff0c18 3174 #define BM_SIM_SCGC6_SPI0 (0x00001000U) //!< Bit mask for SIM_SCGC6_SPI0.
mbed_official 146:f64d43ff0c18 3175 #define BS_SIM_SCGC6_SPI0 (1U) //!< Bit field size in bits for SIM_SCGC6_SPI0.
mbed_official 146:f64d43ff0c18 3176
mbed_official 146:f64d43ff0c18 3177 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3178 //! @brief Read current value of the SIM_SCGC6_SPI0 field.
mbed_official 146:f64d43ff0c18 3179 #define BR_SIM_SCGC6_SPI0 (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_SPI0))
mbed_official 146:f64d43ff0c18 3180 #endif
mbed_official 146:f64d43ff0c18 3181
mbed_official 146:f64d43ff0c18 3182 //! @brief Format value for bitfield SIM_SCGC6_SPI0.
mbed_official 146:f64d43ff0c18 3183 #define BF_SIM_SCGC6_SPI0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_SPI0), uint32_t) & BM_SIM_SCGC6_SPI0)
mbed_official 146:f64d43ff0c18 3184
mbed_official 146:f64d43ff0c18 3185 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3186 //! @brief Set the SPI0 field to a new value.
mbed_official 146:f64d43ff0c18 3187 #define BW_SIM_SCGC6_SPI0(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_SPI0) = (v))
mbed_official 146:f64d43ff0c18 3188 #endif
mbed_official 146:f64d43ff0c18 3189 //@}
mbed_official 146:f64d43ff0c18 3190
mbed_official 146:f64d43ff0c18 3191 /*!
mbed_official 146:f64d43ff0c18 3192 * @name Register SIM_SCGC6, field SPI1[13] (RW)
mbed_official 146:f64d43ff0c18 3193 *
mbed_official 146:f64d43ff0c18 3194 * This bit controls the clock gate to the SPI1 module.
mbed_official 146:f64d43ff0c18 3195 *
mbed_official 146:f64d43ff0c18 3196 * Values:
mbed_official 146:f64d43ff0c18 3197 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 3198 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 3199 */
mbed_official 146:f64d43ff0c18 3200 //@{
mbed_official 146:f64d43ff0c18 3201 #define BP_SIM_SCGC6_SPI1 (13U) //!< Bit position for SIM_SCGC6_SPI1.
mbed_official 146:f64d43ff0c18 3202 #define BM_SIM_SCGC6_SPI1 (0x00002000U) //!< Bit mask for SIM_SCGC6_SPI1.
mbed_official 146:f64d43ff0c18 3203 #define BS_SIM_SCGC6_SPI1 (1U) //!< Bit field size in bits for SIM_SCGC6_SPI1.
mbed_official 146:f64d43ff0c18 3204
mbed_official 146:f64d43ff0c18 3205 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3206 //! @brief Read current value of the SIM_SCGC6_SPI1 field.
mbed_official 146:f64d43ff0c18 3207 #define BR_SIM_SCGC6_SPI1 (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_SPI1))
mbed_official 146:f64d43ff0c18 3208 #endif
mbed_official 146:f64d43ff0c18 3209
mbed_official 146:f64d43ff0c18 3210 //! @brief Format value for bitfield SIM_SCGC6_SPI1.
mbed_official 146:f64d43ff0c18 3211 #define BF_SIM_SCGC6_SPI1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_SPI1), uint32_t) & BM_SIM_SCGC6_SPI1)
mbed_official 146:f64d43ff0c18 3212
mbed_official 146:f64d43ff0c18 3213 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3214 //! @brief Set the SPI1 field to a new value.
mbed_official 146:f64d43ff0c18 3215 #define BW_SIM_SCGC6_SPI1(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_SPI1) = (v))
mbed_official 146:f64d43ff0c18 3216 #endif
mbed_official 146:f64d43ff0c18 3217 //@}
mbed_official 146:f64d43ff0c18 3218
mbed_official 146:f64d43ff0c18 3219 /*!
mbed_official 146:f64d43ff0c18 3220 * @name Register SIM_SCGC6, field I2S[15] (RW)
mbed_official 146:f64d43ff0c18 3221 *
mbed_official 146:f64d43ff0c18 3222 * This bit controls the clock gate to the I 2 S module.
mbed_official 146:f64d43ff0c18 3223 *
mbed_official 146:f64d43ff0c18 3224 * Values:
mbed_official 146:f64d43ff0c18 3225 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 3226 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 3227 */
mbed_official 146:f64d43ff0c18 3228 //@{
mbed_official 146:f64d43ff0c18 3229 #define BP_SIM_SCGC6_I2S (15U) //!< Bit position for SIM_SCGC6_I2S.
mbed_official 146:f64d43ff0c18 3230 #define BM_SIM_SCGC6_I2S (0x00008000U) //!< Bit mask for SIM_SCGC6_I2S.
mbed_official 146:f64d43ff0c18 3231 #define BS_SIM_SCGC6_I2S (1U) //!< Bit field size in bits for SIM_SCGC6_I2S.
mbed_official 146:f64d43ff0c18 3232
mbed_official 146:f64d43ff0c18 3233 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3234 //! @brief Read current value of the SIM_SCGC6_I2S field.
mbed_official 146:f64d43ff0c18 3235 #define BR_SIM_SCGC6_I2S (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_I2S))
mbed_official 146:f64d43ff0c18 3236 #endif
mbed_official 146:f64d43ff0c18 3237
mbed_official 146:f64d43ff0c18 3238 //! @brief Format value for bitfield SIM_SCGC6_I2S.
mbed_official 146:f64d43ff0c18 3239 #define BF_SIM_SCGC6_I2S(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_I2S), uint32_t) & BM_SIM_SCGC6_I2S)
mbed_official 146:f64d43ff0c18 3240
mbed_official 146:f64d43ff0c18 3241 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3242 //! @brief Set the I2S field to a new value.
mbed_official 146:f64d43ff0c18 3243 #define BW_SIM_SCGC6_I2S(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_I2S) = (v))
mbed_official 146:f64d43ff0c18 3244 #endif
mbed_official 146:f64d43ff0c18 3245 //@}
mbed_official 146:f64d43ff0c18 3246
mbed_official 146:f64d43ff0c18 3247 /*!
mbed_official 146:f64d43ff0c18 3248 * @name Register SIM_SCGC6, field CRC[18] (RW)
mbed_official 146:f64d43ff0c18 3249 *
mbed_official 146:f64d43ff0c18 3250 * This bit controls the clock gate to the CRC module.
mbed_official 146:f64d43ff0c18 3251 *
mbed_official 146:f64d43ff0c18 3252 * Values:
mbed_official 146:f64d43ff0c18 3253 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 3254 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 3255 */
mbed_official 146:f64d43ff0c18 3256 //@{
mbed_official 146:f64d43ff0c18 3257 #define BP_SIM_SCGC6_CRC (18U) //!< Bit position for SIM_SCGC6_CRC.
mbed_official 146:f64d43ff0c18 3258 #define BM_SIM_SCGC6_CRC (0x00040000U) //!< Bit mask for SIM_SCGC6_CRC.
mbed_official 146:f64d43ff0c18 3259 #define BS_SIM_SCGC6_CRC (1U) //!< Bit field size in bits for SIM_SCGC6_CRC.
mbed_official 146:f64d43ff0c18 3260
mbed_official 146:f64d43ff0c18 3261 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3262 //! @brief Read current value of the SIM_SCGC6_CRC field.
mbed_official 146:f64d43ff0c18 3263 #define BR_SIM_SCGC6_CRC (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_CRC))
mbed_official 146:f64d43ff0c18 3264 #endif
mbed_official 146:f64d43ff0c18 3265
mbed_official 146:f64d43ff0c18 3266 //! @brief Format value for bitfield SIM_SCGC6_CRC.
mbed_official 146:f64d43ff0c18 3267 #define BF_SIM_SCGC6_CRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_CRC), uint32_t) & BM_SIM_SCGC6_CRC)
mbed_official 146:f64d43ff0c18 3268
mbed_official 146:f64d43ff0c18 3269 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3270 //! @brief Set the CRC field to a new value.
mbed_official 146:f64d43ff0c18 3271 #define BW_SIM_SCGC6_CRC(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_CRC) = (v))
mbed_official 146:f64d43ff0c18 3272 #endif
mbed_official 146:f64d43ff0c18 3273 //@}
mbed_official 146:f64d43ff0c18 3274
mbed_official 146:f64d43ff0c18 3275 /*!
mbed_official 146:f64d43ff0c18 3276 * @name Register SIM_SCGC6, field USBDCD[21] (RW)
mbed_official 146:f64d43ff0c18 3277 *
mbed_official 146:f64d43ff0c18 3278 * This bit controls the clock gate to the USB DCD module.
mbed_official 146:f64d43ff0c18 3279 *
mbed_official 146:f64d43ff0c18 3280 * Values:
mbed_official 146:f64d43ff0c18 3281 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 3282 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 3283 */
mbed_official 146:f64d43ff0c18 3284 //@{
mbed_official 146:f64d43ff0c18 3285 #define BP_SIM_SCGC6_USBDCD (21U) //!< Bit position for SIM_SCGC6_USBDCD.
mbed_official 146:f64d43ff0c18 3286 #define BM_SIM_SCGC6_USBDCD (0x00200000U) //!< Bit mask for SIM_SCGC6_USBDCD.
mbed_official 146:f64d43ff0c18 3287 #define BS_SIM_SCGC6_USBDCD (1U) //!< Bit field size in bits for SIM_SCGC6_USBDCD.
mbed_official 146:f64d43ff0c18 3288
mbed_official 146:f64d43ff0c18 3289 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3290 //! @brief Read current value of the SIM_SCGC6_USBDCD field.
mbed_official 146:f64d43ff0c18 3291 #define BR_SIM_SCGC6_USBDCD (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_USBDCD))
mbed_official 146:f64d43ff0c18 3292 #endif
mbed_official 146:f64d43ff0c18 3293
mbed_official 146:f64d43ff0c18 3294 //! @brief Format value for bitfield SIM_SCGC6_USBDCD.
mbed_official 146:f64d43ff0c18 3295 #define BF_SIM_SCGC6_USBDCD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_USBDCD), uint32_t) & BM_SIM_SCGC6_USBDCD)
mbed_official 146:f64d43ff0c18 3296
mbed_official 146:f64d43ff0c18 3297 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3298 //! @brief Set the USBDCD field to a new value.
mbed_official 146:f64d43ff0c18 3299 #define BW_SIM_SCGC6_USBDCD(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_USBDCD) = (v))
mbed_official 146:f64d43ff0c18 3300 #endif
mbed_official 146:f64d43ff0c18 3301 //@}
mbed_official 146:f64d43ff0c18 3302
mbed_official 146:f64d43ff0c18 3303 /*!
mbed_official 146:f64d43ff0c18 3304 * @name Register SIM_SCGC6, field PDB[22] (RW)
mbed_official 146:f64d43ff0c18 3305 *
mbed_official 146:f64d43ff0c18 3306 * This bit controls the clock gate to the PDB module.
mbed_official 146:f64d43ff0c18 3307 *
mbed_official 146:f64d43ff0c18 3308 * Values:
mbed_official 146:f64d43ff0c18 3309 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 3310 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 3311 */
mbed_official 146:f64d43ff0c18 3312 //@{
mbed_official 146:f64d43ff0c18 3313 #define BP_SIM_SCGC6_PDB (22U) //!< Bit position for SIM_SCGC6_PDB.
mbed_official 146:f64d43ff0c18 3314 #define BM_SIM_SCGC6_PDB (0x00400000U) //!< Bit mask for SIM_SCGC6_PDB.
mbed_official 146:f64d43ff0c18 3315 #define BS_SIM_SCGC6_PDB (1U) //!< Bit field size in bits for SIM_SCGC6_PDB.
mbed_official 146:f64d43ff0c18 3316
mbed_official 146:f64d43ff0c18 3317 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3318 //! @brief Read current value of the SIM_SCGC6_PDB field.
mbed_official 146:f64d43ff0c18 3319 #define BR_SIM_SCGC6_PDB (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_PDB))
mbed_official 146:f64d43ff0c18 3320 #endif
mbed_official 146:f64d43ff0c18 3321
mbed_official 146:f64d43ff0c18 3322 //! @brief Format value for bitfield SIM_SCGC6_PDB.
mbed_official 146:f64d43ff0c18 3323 #define BF_SIM_SCGC6_PDB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_PDB), uint32_t) & BM_SIM_SCGC6_PDB)
mbed_official 146:f64d43ff0c18 3324
mbed_official 146:f64d43ff0c18 3325 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3326 //! @brief Set the PDB field to a new value.
mbed_official 146:f64d43ff0c18 3327 #define BW_SIM_SCGC6_PDB(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_PDB) = (v))
mbed_official 146:f64d43ff0c18 3328 #endif
mbed_official 146:f64d43ff0c18 3329 //@}
mbed_official 146:f64d43ff0c18 3330
mbed_official 146:f64d43ff0c18 3331 /*!
mbed_official 146:f64d43ff0c18 3332 * @name Register SIM_SCGC6, field PIT[23] (RW)
mbed_official 146:f64d43ff0c18 3333 *
mbed_official 146:f64d43ff0c18 3334 * This bit controls the clock gate to the PIT module.
mbed_official 146:f64d43ff0c18 3335 *
mbed_official 146:f64d43ff0c18 3336 * Values:
mbed_official 146:f64d43ff0c18 3337 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 3338 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 3339 */
mbed_official 146:f64d43ff0c18 3340 //@{
mbed_official 146:f64d43ff0c18 3341 #define BP_SIM_SCGC6_PIT (23U) //!< Bit position for SIM_SCGC6_PIT.
mbed_official 146:f64d43ff0c18 3342 #define BM_SIM_SCGC6_PIT (0x00800000U) //!< Bit mask for SIM_SCGC6_PIT.
mbed_official 146:f64d43ff0c18 3343 #define BS_SIM_SCGC6_PIT (1U) //!< Bit field size in bits for SIM_SCGC6_PIT.
mbed_official 146:f64d43ff0c18 3344
mbed_official 146:f64d43ff0c18 3345 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3346 //! @brief Read current value of the SIM_SCGC6_PIT field.
mbed_official 146:f64d43ff0c18 3347 #define BR_SIM_SCGC6_PIT (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_PIT))
mbed_official 146:f64d43ff0c18 3348 #endif
mbed_official 146:f64d43ff0c18 3349
mbed_official 146:f64d43ff0c18 3350 //! @brief Format value for bitfield SIM_SCGC6_PIT.
mbed_official 146:f64d43ff0c18 3351 #define BF_SIM_SCGC6_PIT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_PIT), uint32_t) & BM_SIM_SCGC6_PIT)
mbed_official 146:f64d43ff0c18 3352
mbed_official 146:f64d43ff0c18 3353 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3354 //! @brief Set the PIT field to a new value.
mbed_official 146:f64d43ff0c18 3355 #define BW_SIM_SCGC6_PIT(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_PIT) = (v))
mbed_official 146:f64d43ff0c18 3356 #endif
mbed_official 146:f64d43ff0c18 3357 //@}
mbed_official 146:f64d43ff0c18 3358
mbed_official 146:f64d43ff0c18 3359 /*!
mbed_official 146:f64d43ff0c18 3360 * @name Register SIM_SCGC6, field FTM0[24] (RW)
mbed_official 146:f64d43ff0c18 3361 *
mbed_official 146:f64d43ff0c18 3362 * This bit controls the clock gate to the FTM0 module.
mbed_official 146:f64d43ff0c18 3363 *
mbed_official 146:f64d43ff0c18 3364 * Values:
mbed_official 146:f64d43ff0c18 3365 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 3366 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 3367 */
mbed_official 146:f64d43ff0c18 3368 //@{
mbed_official 146:f64d43ff0c18 3369 #define BP_SIM_SCGC6_FTM0 (24U) //!< Bit position for SIM_SCGC6_FTM0.
mbed_official 146:f64d43ff0c18 3370 #define BM_SIM_SCGC6_FTM0 (0x01000000U) //!< Bit mask for SIM_SCGC6_FTM0.
mbed_official 146:f64d43ff0c18 3371 #define BS_SIM_SCGC6_FTM0 (1U) //!< Bit field size in bits for SIM_SCGC6_FTM0.
mbed_official 146:f64d43ff0c18 3372
mbed_official 146:f64d43ff0c18 3373 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3374 //! @brief Read current value of the SIM_SCGC6_FTM0 field.
mbed_official 146:f64d43ff0c18 3375 #define BR_SIM_SCGC6_FTM0 (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTM0))
mbed_official 146:f64d43ff0c18 3376 #endif
mbed_official 146:f64d43ff0c18 3377
mbed_official 146:f64d43ff0c18 3378 //! @brief Format value for bitfield SIM_SCGC6_FTM0.
mbed_official 146:f64d43ff0c18 3379 #define BF_SIM_SCGC6_FTM0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_FTM0), uint32_t) & BM_SIM_SCGC6_FTM0)
mbed_official 146:f64d43ff0c18 3380
mbed_official 146:f64d43ff0c18 3381 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3382 //! @brief Set the FTM0 field to a new value.
mbed_official 146:f64d43ff0c18 3383 #define BW_SIM_SCGC6_FTM0(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTM0) = (v))
mbed_official 146:f64d43ff0c18 3384 #endif
mbed_official 146:f64d43ff0c18 3385 //@}
mbed_official 146:f64d43ff0c18 3386
mbed_official 146:f64d43ff0c18 3387 /*!
mbed_official 146:f64d43ff0c18 3388 * @name Register SIM_SCGC6, field FTM1[25] (RW)
mbed_official 146:f64d43ff0c18 3389 *
mbed_official 146:f64d43ff0c18 3390 * This bit controls the clock gate to the FTM1 module.
mbed_official 146:f64d43ff0c18 3391 *
mbed_official 146:f64d43ff0c18 3392 * Values:
mbed_official 146:f64d43ff0c18 3393 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 3394 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 3395 */
mbed_official 146:f64d43ff0c18 3396 //@{
mbed_official 146:f64d43ff0c18 3397 #define BP_SIM_SCGC6_FTM1 (25U) //!< Bit position for SIM_SCGC6_FTM1.
mbed_official 146:f64d43ff0c18 3398 #define BM_SIM_SCGC6_FTM1 (0x02000000U) //!< Bit mask for SIM_SCGC6_FTM1.
mbed_official 146:f64d43ff0c18 3399 #define BS_SIM_SCGC6_FTM1 (1U) //!< Bit field size in bits for SIM_SCGC6_FTM1.
mbed_official 146:f64d43ff0c18 3400
mbed_official 146:f64d43ff0c18 3401 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3402 //! @brief Read current value of the SIM_SCGC6_FTM1 field.
mbed_official 146:f64d43ff0c18 3403 #define BR_SIM_SCGC6_FTM1 (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTM1))
mbed_official 146:f64d43ff0c18 3404 #endif
mbed_official 146:f64d43ff0c18 3405
mbed_official 146:f64d43ff0c18 3406 //! @brief Format value for bitfield SIM_SCGC6_FTM1.
mbed_official 146:f64d43ff0c18 3407 #define BF_SIM_SCGC6_FTM1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_FTM1), uint32_t) & BM_SIM_SCGC6_FTM1)
mbed_official 146:f64d43ff0c18 3408
mbed_official 146:f64d43ff0c18 3409 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3410 //! @brief Set the FTM1 field to a new value.
mbed_official 146:f64d43ff0c18 3411 #define BW_SIM_SCGC6_FTM1(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTM1) = (v))
mbed_official 146:f64d43ff0c18 3412 #endif
mbed_official 146:f64d43ff0c18 3413 //@}
mbed_official 146:f64d43ff0c18 3414
mbed_official 146:f64d43ff0c18 3415 /*!
mbed_official 146:f64d43ff0c18 3416 * @name Register SIM_SCGC6, field FTM2[26] (RW)
mbed_official 146:f64d43ff0c18 3417 *
mbed_official 146:f64d43ff0c18 3418 * This bit controls the clock gate to the FTM2 module.
mbed_official 146:f64d43ff0c18 3419 *
mbed_official 146:f64d43ff0c18 3420 * Values:
mbed_official 146:f64d43ff0c18 3421 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 3422 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 3423 */
mbed_official 146:f64d43ff0c18 3424 //@{
mbed_official 146:f64d43ff0c18 3425 #define BP_SIM_SCGC6_FTM2 (26U) //!< Bit position for SIM_SCGC6_FTM2.
mbed_official 146:f64d43ff0c18 3426 #define BM_SIM_SCGC6_FTM2 (0x04000000U) //!< Bit mask for SIM_SCGC6_FTM2.
mbed_official 146:f64d43ff0c18 3427 #define BS_SIM_SCGC6_FTM2 (1U) //!< Bit field size in bits for SIM_SCGC6_FTM2.
mbed_official 146:f64d43ff0c18 3428
mbed_official 146:f64d43ff0c18 3429 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3430 //! @brief Read current value of the SIM_SCGC6_FTM2 field.
mbed_official 146:f64d43ff0c18 3431 #define BR_SIM_SCGC6_FTM2 (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTM2))
mbed_official 146:f64d43ff0c18 3432 #endif
mbed_official 146:f64d43ff0c18 3433
mbed_official 146:f64d43ff0c18 3434 //! @brief Format value for bitfield SIM_SCGC6_FTM2.
mbed_official 146:f64d43ff0c18 3435 #define BF_SIM_SCGC6_FTM2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_FTM2), uint32_t) & BM_SIM_SCGC6_FTM2)
mbed_official 146:f64d43ff0c18 3436
mbed_official 146:f64d43ff0c18 3437 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3438 //! @brief Set the FTM2 field to a new value.
mbed_official 146:f64d43ff0c18 3439 #define BW_SIM_SCGC6_FTM2(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTM2) = (v))
mbed_official 146:f64d43ff0c18 3440 #endif
mbed_official 146:f64d43ff0c18 3441 //@}
mbed_official 146:f64d43ff0c18 3442
mbed_official 146:f64d43ff0c18 3443 /*!
mbed_official 146:f64d43ff0c18 3444 * @name Register SIM_SCGC6, field ADC0[27] (RW)
mbed_official 146:f64d43ff0c18 3445 *
mbed_official 146:f64d43ff0c18 3446 * This bit controls the clock gate to the ADC0 module.
mbed_official 146:f64d43ff0c18 3447 *
mbed_official 146:f64d43ff0c18 3448 * Values:
mbed_official 146:f64d43ff0c18 3449 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 3450 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 3451 */
mbed_official 146:f64d43ff0c18 3452 //@{
mbed_official 146:f64d43ff0c18 3453 #define BP_SIM_SCGC6_ADC0 (27U) //!< Bit position for SIM_SCGC6_ADC0.
mbed_official 146:f64d43ff0c18 3454 #define BM_SIM_SCGC6_ADC0 (0x08000000U) //!< Bit mask for SIM_SCGC6_ADC0.
mbed_official 146:f64d43ff0c18 3455 #define BS_SIM_SCGC6_ADC0 (1U) //!< Bit field size in bits for SIM_SCGC6_ADC0.
mbed_official 146:f64d43ff0c18 3456
mbed_official 146:f64d43ff0c18 3457 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3458 //! @brief Read current value of the SIM_SCGC6_ADC0 field.
mbed_official 146:f64d43ff0c18 3459 #define BR_SIM_SCGC6_ADC0 (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_ADC0))
mbed_official 146:f64d43ff0c18 3460 #endif
mbed_official 146:f64d43ff0c18 3461
mbed_official 146:f64d43ff0c18 3462 //! @brief Format value for bitfield SIM_SCGC6_ADC0.
mbed_official 146:f64d43ff0c18 3463 #define BF_SIM_SCGC6_ADC0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_ADC0), uint32_t) & BM_SIM_SCGC6_ADC0)
mbed_official 146:f64d43ff0c18 3464
mbed_official 146:f64d43ff0c18 3465 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3466 //! @brief Set the ADC0 field to a new value.
mbed_official 146:f64d43ff0c18 3467 #define BW_SIM_SCGC6_ADC0(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_ADC0) = (v))
mbed_official 146:f64d43ff0c18 3468 #endif
mbed_official 146:f64d43ff0c18 3469 //@}
mbed_official 146:f64d43ff0c18 3470
mbed_official 146:f64d43ff0c18 3471 /*!
mbed_official 146:f64d43ff0c18 3472 * @name Register SIM_SCGC6, field RTC[29] (RW)
mbed_official 146:f64d43ff0c18 3473 *
mbed_official 146:f64d43ff0c18 3474 * This bit controls software access and interrupts to the RTC module.
mbed_official 146:f64d43ff0c18 3475 *
mbed_official 146:f64d43ff0c18 3476 * Values:
mbed_official 146:f64d43ff0c18 3477 * - 0 - Access and interrupts disabled
mbed_official 146:f64d43ff0c18 3478 * - 1 - Access and interrupts enabled
mbed_official 146:f64d43ff0c18 3479 */
mbed_official 146:f64d43ff0c18 3480 //@{
mbed_official 146:f64d43ff0c18 3481 #define BP_SIM_SCGC6_RTC (29U) //!< Bit position for SIM_SCGC6_RTC.
mbed_official 146:f64d43ff0c18 3482 #define BM_SIM_SCGC6_RTC (0x20000000U) //!< Bit mask for SIM_SCGC6_RTC.
mbed_official 146:f64d43ff0c18 3483 #define BS_SIM_SCGC6_RTC (1U) //!< Bit field size in bits for SIM_SCGC6_RTC.
mbed_official 146:f64d43ff0c18 3484
mbed_official 146:f64d43ff0c18 3485 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3486 //! @brief Read current value of the SIM_SCGC6_RTC field.
mbed_official 146:f64d43ff0c18 3487 #define BR_SIM_SCGC6_RTC (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_RTC))
mbed_official 146:f64d43ff0c18 3488 #endif
mbed_official 146:f64d43ff0c18 3489
mbed_official 146:f64d43ff0c18 3490 //! @brief Format value for bitfield SIM_SCGC6_RTC.
mbed_official 146:f64d43ff0c18 3491 #define BF_SIM_SCGC6_RTC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_RTC), uint32_t) & BM_SIM_SCGC6_RTC)
mbed_official 146:f64d43ff0c18 3492
mbed_official 146:f64d43ff0c18 3493 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3494 //! @brief Set the RTC field to a new value.
mbed_official 146:f64d43ff0c18 3495 #define BW_SIM_SCGC6_RTC(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_RTC) = (v))
mbed_official 146:f64d43ff0c18 3496 #endif
mbed_official 146:f64d43ff0c18 3497 //@}
mbed_official 146:f64d43ff0c18 3498
mbed_official 146:f64d43ff0c18 3499 /*!
mbed_official 146:f64d43ff0c18 3500 * @name Register SIM_SCGC6, field DAC0[31] (RW)
mbed_official 146:f64d43ff0c18 3501 *
mbed_official 146:f64d43ff0c18 3502 * This bit controls the clock gate to the DAC0 module.
mbed_official 146:f64d43ff0c18 3503 *
mbed_official 146:f64d43ff0c18 3504 * Values:
mbed_official 146:f64d43ff0c18 3505 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 3506 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 3507 */
mbed_official 146:f64d43ff0c18 3508 //@{
mbed_official 146:f64d43ff0c18 3509 #define BP_SIM_SCGC6_DAC0 (31U) //!< Bit position for SIM_SCGC6_DAC0.
mbed_official 146:f64d43ff0c18 3510 #define BM_SIM_SCGC6_DAC0 (0x80000000U) //!< Bit mask for SIM_SCGC6_DAC0.
mbed_official 146:f64d43ff0c18 3511 #define BS_SIM_SCGC6_DAC0 (1U) //!< Bit field size in bits for SIM_SCGC6_DAC0.
mbed_official 146:f64d43ff0c18 3512
mbed_official 146:f64d43ff0c18 3513 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3514 //! @brief Read current value of the SIM_SCGC6_DAC0 field.
mbed_official 146:f64d43ff0c18 3515 #define BR_SIM_SCGC6_DAC0 (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_DAC0))
mbed_official 146:f64d43ff0c18 3516 #endif
mbed_official 146:f64d43ff0c18 3517
mbed_official 146:f64d43ff0c18 3518 //! @brief Format value for bitfield SIM_SCGC6_DAC0.
mbed_official 146:f64d43ff0c18 3519 #define BF_SIM_SCGC6_DAC0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_DAC0), uint32_t) & BM_SIM_SCGC6_DAC0)
mbed_official 146:f64d43ff0c18 3520
mbed_official 146:f64d43ff0c18 3521 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3522 //! @brief Set the DAC0 field to a new value.
mbed_official 146:f64d43ff0c18 3523 #define BW_SIM_SCGC6_DAC0(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_DAC0) = (v))
mbed_official 146:f64d43ff0c18 3524 #endif
mbed_official 146:f64d43ff0c18 3525 //@}
mbed_official 146:f64d43ff0c18 3526
mbed_official 146:f64d43ff0c18 3527 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3528 // HW_SIM_SCGC7 - System Clock Gating Control Register 7
mbed_official 146:f64d43ff0c18 3529 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3530
mbed_official 146:f64d43ff0c18 3531 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3532 /*!
mbed_official 146:f64d43ff0c18 3533 * @brief HW_SIM_SCGC7 - System Clock Gating Control Register 7 (RW)
mbed_official 146:f64d43ff0c18 3534 *
mbed_official 146:f64d43ff0c18 3535 * Reset value: 0x00000006U
mbed_official 146:f64d43ff0c18 3536 */
mbed_official 146:f64d43ff0c18 3537 typedef union _hw_sim_scgc7
mbed_official 146:f64d43ff0c18 3538 {
mbed_official 146:f64d43ff0c18 3539 uint32_t U;
mbed_official 146:f64d43ff0c18 3540 struct _hw_sim_scgc7_bitfields
mbed_official 146:f64d43ff0c18 3541 {
mbed_official 146:f64d43ff0c18 3542 uint32_t FLEXBUS : 1; //!< [0] FlexBus Clock Gate Control
mbed_official 146:f64d43ff0c18 3543 uint32_t DMAb : 1; //!< [1] DMA Clock Gate Control
mbed_official 146:f64d43ff0c18 3544 uint32_t MPUb : 1; //!< [2] MPU Clock Gate Control
mbed_official 146:f64d43ff0c18 3545 uint32_t RESERVED0 : 29; //!< [31:3]
mbed_official 146:f64d43ff0c18 3546 } B;
mbed_official 146:f64d43ff0c18 3547 } hw_sim_scgc7_t;
mbed_official 146:f64d43ff0c18 3548 #endif
mbed_official 146:f64d43ff0c18 3549
mbed_official 146:f64d43ff0c18 3550 /*!
mbed_official 146:f64d43ff0c18 3551 * @name Constants and macros for entire SIM_SCGC7 register
mbed_official 146:f64d43ff0c18 3552 */
mbed_official 146:f64d43ff0c18 3553 //@{
mbed_official 146:f64d43ff0c18 3554 #define HW_SIM_SCGC7_ADDR (REGS_SIM_BASE + 0x1040U)
mbed_official 146:f64d43ff0c18 3555
mbed_official 146:f64d43ff0c18 3556 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3557 #define HW_SIM_SCGC7 (*(__IO hw_sim_scgc7_t *) HW_SIM_SCGC7_ADDR)
mbed_official 146:f64d43ff0c18 3558 #define HW_SIM_SCGC7_RD() (HW_SIM_SCGC7.U)
mbed_official 146:f64d43ff0c18 3559 #define HW_SIM_SCGC7_WR(v) (HW_SIM_SCGC7.U = (v))
mbed_official 146:f64d43ff0c18 3560 #define HW_SIM_SCGC7_SET(v) (HW_SIM_SCGC7_WR(HW_SIM_SCGC7_RD() | (v)))
mbed_official 146:f64d43ff0c18 3561 #define HW_SIM_SCGC7_CLR(v) (HW_SIM_SCGC7_WR(HW_SIM_SCGC7_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 3562 #define HW_SIM_SCGC7_TOG(v) (HW_SIM_SCGC7_WR(HW_SIM_SCGC7_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 3563 #endif
mbed_official 146:f64d43ff0c18 3564 //@}
mbed_official 146:f64d43ff0c18 3565
mbed_official 146:f64d43ff0c18 3566 /*
mbed_official 146:f64d43ff0c18 3567 * Constants & macros for individual SIM_SCGC7 bitfields
mbed_official 146:f64d43ff0c18 3568 */
mbed_official 146:f64d43ff0c18 3569
mbed_official 146:f64d43ff0c18 3570 /*!
mbed_official 146:f64d43ff0c18 3571 * @name Register SIM_SCGC7, field FLEXBUS[0] (RW)
mbed_official 146:f64d43ff0c18 3572 *
mbed_official 146:f64d43ff0c18 3573 * This bit controls the clock gate to the FlexBus module.
mbed_official 146:f64d43ff0c18 3574 *
mbed_official 146:f64d43ff0c18 3575 * Values:
mbed_official 146:f64d43ff0c18 3576 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 3577 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 3578 */
mbed_official 146:f64d43ff0c18 3579 //@{
mbed_official 146:f64d43ff0c18 3580 #define BP_SIM_SCGC7_FLEXBUS (0U) //!< Bit position for SIM_SCGC7_FLEXBUS.
mbed_official 146:f64d43ff0c18 3581 #define BM_SIM_SCGC7_FLEXBUS (0x00000001U) //!< Bit mask for SIM_SCGC7_FLEXBUS.
mbed_official 146:f64d43ff0c18 3582 #define BS_SIM_SCGC7_FLEXBUS (1U) //!< Bit field size in bits for SIM_SCGC7_FLEXBUS.
mbed_official 146:f64d43ff0c18 3583
mbed_official 146:f64d43ff0c18 3584 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3585 //! @brief Read current value of the SIM_SCGC7_FLEXBUS field.
mbed_official 146:f64d43ff0c18 3586 #define BR_SIM_SCGC7_FLEXBUS (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR, BP_SIM_SCGC7_FLEXBUS))
mbed_official 146:f64d43ff0c18 3587 #endif
mbed_official 146:f64d43ff0c18 3588
mbed_official 146:f64d43ff0c18 3589 //! @brief Format value for bitfield SIM_SCGC7_FLEXBUS.
mbed_official 146:f64d43ff0c18 3590 #define BF_SIM_SCGC7_FLEXBUS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC7_FLEXBUS), uint32_t) & BM_SIM_SCGC7_FLEXBUS)
mbed_official 146:f64d43ff0c18 3591
mbed_official 146:f64d43ff0c18 3592 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3593 //! @brief Set the FLEXBUS field to a new value.
mbed_official 146:f64d43ff0c18 3594 #define BW_SIM_SCGC7_FLEXBUS(v) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR, BP_SIM_SCGC7_FLEXBUS) = (v))
mbed_official 146:f64d43ff0c18 3595 #endif
mbed_official 146:f64d43ff0c18 3596 //@}
mbed_official 146:f64d43ff0c18 3597
mbed_official 146:f64d43ff0c18 3598 /*!
mbed_official 146:f64d43ff0c18 3599 * @name Register SIM_SCGC7, field DMA[1] (RW)
mbed_official 146:f64d43ff0c18 3600 *
mbed_official 146:f64d43ff0c18 3601 * This bit controls the clock gate to the DMA module.
mbed_official 146:f64d43ff0c18 3602 *
mbed_official 146:f64d43ff0c18 3603 * Values:
mbed_official 146:f64d43ff0c18 3604 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 3605 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 3606 */
mbed_official 146:f64d43ff0c18 3607 //@{
mbed_official 146:f64d43ff0c18 3608 #define BP_SIM_SCGC7_DMA (1U) //!< Bit position for SIM_SCGC7_DMA.
mbed_official 146:f64d43ff0c18 3609 #define BM_SIM_SCGC7_DMA (0x00000002U) //!< Bit mask for SIM_SCGC7_DMA.
mbed_official 146:f64d43ff0c18 3610 #define BS_SIM_SCGC7_DMA (1U) //!< Bit field size in bits for SIM_SCGC7_DMA.
mbed_official 146:f64d43ff0c18 3611
mbed_official 146:f64d43ff0c18 3612 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3613 //! @brief Read current value of the SIM_SCGC7_DMA field.
mbed_official 146:f64d43ff0c18 3614 #define BR_SIM_SCGC7_DMA (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR, BP_SIM_SCGC7_DMA))
mbed_official 146:f64d43ff0c18 3615 #endif
mbed_official 146:f64d43ff0c18 3616
mbed_official 146:f64d43ff0c18 3617 //! @brief Format value for bitfield SIM_SCGC7_DMA.
mbed_official 146:f64d43ff0c18 3618 #define BF_SIM_SCGC7_DMA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC7_DMA), uint32_t) & BM_SIM_SCGC7_DMA)
mbed_official 146:f64d43ff0c18 3619
mbed_official 146:f64d43ff0c18 3620 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3621 //! @brief Set the DMA field to a new value.
mbed_official 146:f64d43ff0c18 3622 #define BW_SIM_SCGC7_DMA(v) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR, BP_SIM_SCGC7_DMA) = (v))
mbed_official 146:f64d43ff0c18 3623 #endif
mbed_official 146:f64d43ff0c18 3624 //@}
mbed_official 146:f64d43ff0c18 3625
mbed_official 146:f64d43ff0c18 3626 /*!
mbed_official 146:f64d43ff0c18 3627 * @name Register SIM_SCGC7, field MPU[2] (RW)
mbed_official 146:f64d43ff0c18 3628 *
mbed_official 146:f64d43ff0c18 3629 * This bit controls the clock gate to the MPU module.
mbed_official 146:f64d43ff0c18 3630 *
mbed_official 146:f64d43ff0c18 3631 * Values:
mbed_official 146:f64d43ff0c18 3632 * - 0 - Clock disabled
mbed_official 146:f64d43ff0c18 3633 * - 1 - Clock enabled
mbed_official 146:f64d43ff0c18 3634 */
mbed_official 146:f64d43ff0c18 3635 //@{
mbed_official 146:f64d43ff0c18 3636 #define BP_SIM_SCGC7_MPU (2U) //!< Bit position for SIM_SCGC7_MPU.
mbed_official 146:f64d43ff0c18 3637 #define BM_SIM_SCGC7_MPU (0x00000004U) //!< Bit mask for SIM_SCGC7_MPU.
mbed_official 146:f64d43ff0c18 3638 #define BS_SIM_SCGC7_MPU (1U) //!< Bit field size in bits for SIM_SCGC7_MPU.
mbed_official 146:f64d43ff0c18 3639
mbed_official 146:f64d43ff0c18 3640 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3641 //! @brief Read current value of the SIM_SCGC7_MPU field.
mbed_official 146:f64d43ff0c18 3642 #define BR_SIM_SCGC7_MPU (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR, BP_SIM_SCGC7_MPU))
mbed_official 146:f64d43ff0c18 3643 #endif
mbed_official 146:f64d43ff0c18 3644
mbed_official 146:f64d43ff0c18 3645 //! @brief Format value for bitfield SIM_SCGC7_MPU.
mbed_official 146:f64d43ff0c18 3646 #define BF_SIM_SCGC7_MPU(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC7_MPU), uint32_t) & BM_SIM_SCGC7_MPU)
mbed_official 146:f64d43ff0c18 3647
mbed_official 146:f64d43ff0c18 3648 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3649 //! @brief Set the MPU field to a new value.
mbed_official 146:f64d43ff0c18 3650 #define BW_SIM_SCGC7_MPU(v) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR, BP_SIM_SCGC7_MPU) = (v))
mbed_official 146:f64d43ff0c18 3651 #endif
mbed_official 146:f64d43ff0c18 3652 //@}
mbed_official 146:f64d43ff0c18 3653
mbed_official 146:f64d43ff0c18 3654 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3655 // HW_SIM_CLKDIV1 - System Clock Divider Register 1
mbed_official 146:f64d43ff0c18 3656 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3657
mbed_official 146:f64d43ff0c18 3658 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3659 /*!
mbed_official 146:f64d43ff0c18 3660 * @brief HW_SIM_CLKDIV1 - System Clock Divider Register 1 (RW)
mbed_official 146:f64d43ff0c18 3661 *
mbed_official 146:f64d43ff0c18 3662 * Reset value: 0x00010000U
mbed_official 146:f64d43ff0c18 3663 *
mbed_official 146:f64d43ff0c18 3664 * When updating CLKDIV1, update all fields using the one write command.
mbed_official 146:f64d43ff0c18 3665 * Attempting to write an invalid clock ratio to the CLKDIV1 register will cause the
mbed_official 146:f64d43ff0c18 3666 * write to be ignored. The maximum divide ratio that can be programmed between
mbed_official 146:f64d43ff0c18 3667 * core/system clock and the other divided clocks is divide by 8. When OUTDIV1 equals
mbed_official 146:f64d43ff0c18 3668 * 0000 (divide by 1), the other dividers cannot be set higher than 0111 (divide
mbed_official 146:f64d43ff0c18 3669 * by 8). The CLKDIV1 register cannot be written to when the device is in VLPR
mbed_official 146:f64d43ff0c18 3670 * mode.
mbed_official 146:f64d43ff0c18 3671 */
mbed_official 146:f64d43ff0c18 3672 typedef union _hw_sim_clkdiv1
mbed_official 146:f64d43ff0c18 3673 {
mbed_official 146:f64d43ff0c18 3674 uint32_t U;
mbed_official 146:f64d43ff0c18 3675 struct _hw_sim_clkdiv1_bitfields
mbed_official 146:f64d43ff0c18 3676 {
mbed_official 146:f64d43ff0c18 3677 uint32_t RESERVED0 : 16; //!< [15:0]
mbed_official 146:f64d43ff0c18 3678 uint32_t OUTDIV4 : 4; //!< [19:16] Clock 4 output divider value
mbed_official 146:f64d43ff0c18 3679 uint32_t OUTDIV3 : 4; //!< [23:20] Clock 3 output divider value
mbed_official 146:f64d43ff0c18 3680 uint32_t OUTDIV2 : 4; //!< [27:24] Clock 2 output divider value
mbed_official 146:f64d43ff0c18 3681 uint32_t OUTDIV1 : 4; //!< [31:28] Clock 1 output divider value
mbed_official 146:f64d43ff0c18 3682 } B;
mbed_official 146:f64d43ff0c18 3683 } hw_sim_clkdiv1_t;
mbed_official 146:f64d43ff0c18 3684 #endif
mbed_official 146:f64d43ff0c18 3685
mbed_official 146:f64d43ff0c18 3686 /*!
mbed_official 146:f64d43ff0c18 3687 * @name Constants and macros for entire SIM_CLKDIV1 register
mbed_official 146:f64d43ff0c18 3688 */
mbed_official 146:f64d43ff0c18 3689 //@{
mbed_official 146:f64d43ff0c18 3690 #define HW_SIM_CLKDIV1_ADDR (REGS_SIM_BASE + 0x1044U)
mbed_official 146:f64d43ff0c18 3691
mbed_official 146:f64d43ff0c18 3692 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3693 #define HW_SIM_CLKDIV1 (*(__IO hw_sim_clkdiv1_t *) HW_SIM_CLKDIV1_ADDR)
mbed_official 146:f64d43ff0c18 3694 #define HW_SIM_CLKDIV1_RD() (HW_SIM_CLKDIV1.U)
mbed_official 146:f64d43ff0c18 3695 #define HW_SIM_CLKDIV1_WR(v) (HW_SIM_CLKDIV1.U = (v))
mbed_official 146:f64d43ff0c18 3696 #define HW_SIM_CLKDIV1_SET(v) (HW_SIM_CLKDIV1_WR(HW_SIM_CLKDIV1_RD() | (v)))
mbed_official 146:f64d43ff0c18 3697 #define HW_SIM_CLKDIV1_CLR(v) (HW_SIM_CLKDIV1_WR(HW_SIM_CLKDIV1_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 3698 #define HW_SIM_CLKDIV1_TOG(v) (HW_SIM_CLKDIV1_WR(HW_SIM_CLKDIV1_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 3699 #endif
mbed_official 146:f64d43ff0c18 3700 //@}
mbed_official 146:f64d43ff0c18 3701
mbed_official 146:f64d43ff0c18 3702 /*
mbed_official 146:f64d43ff0c18 3703 * Constants & macros for individual SIM_CLKDIV1 bitfields
mbed_official 146:f64d43ff0c18 3704 */
mbed_official 146:f64d43ff0c18 3705
mbed_official 146:f64d43ff0c18 3706 /*!
mbed_official 146:f64d43ff0c18 3707 * @name Register SIM_CLKDIV1, field OUTDIV4[19:16] (RW)
mbed_official 146:f64d43ff0c18 3708 *
mbed_official 146:f64d43ff0c18 3709 * This field sets the divide value for the flash clock from MCGOUTCLK. At the
mbed_official 146:f64d43ff0c18 3710 * end of reset, it is loaded with either 0001 or 1111 depending on
mbed_official 146:f64d43ff0c18 3711 * FTF_FOPT[LPBOOT]. The flash clock frequency must be an integer divide of the system clock
mbed_official 146:f64d43ff0c18 3712 * frequency.
mbed_official 146:f64d43ff0c18 3713 *
mbed_official 146:f64d43ff0c18 3714 * Values:
mbed_official 146:f64d43ff0c18 3715 * - 0000 - Divide-by-1.
mbed_official 146:f64d43ff0c18 3716 * - 0001 - Divide-by-2.
mbed_official 146:f64d43ff0c18 3717 * - 0010 - Divide-by-3.
mbed_official 146:f64d43ff0c18 3718 * - 0011 - Divide-by-4.
mbed_official 146:f64d43ff0c18 3719 * - 0100 - Divide-by-5.
mbed_official 146:f64d43ff0c18 3720 * - 0101 - Divide-by-6.
mbed_official 146:f64d43ff0c18 3721 * - 0110 - Divide-by-7.
mbed_official 146:f64d43ff0c18 3722 * - 0111 - Divide-by-8.
mbed_official 146:f64d43ff0c18 3723 * - 1000 - Divide-by-9.
mbed_official 146:f64d43ff0c18 3724 * - 1001 - Divide-by-10.
mbed_official 146:f64d43ff0c18 3725 * - 1010 - Divide-by-11.
mbed_official 146:f64d43ff0c18 3726 * - 1011 - Divide-by-12.
mbed_official 146:f64d43ff0c18 3727 * - 1100 - Divide-by-13.
mbed_official 146:f64d43ff0c18 3728 * - 1101 - Divide-by-14.
mbed_official 146:f64d43ff0c18 3729 * - 1110 - Divide-by-15.
mbed_official 146:f64d43ff0c18 3730 * - 1111 - Divide-by-16.
mbed_official 146:f64d43ff0c18 3731 */
mbed_official 146:f64d43ff0c18 3732 //@{
mbed_official 146:f64d43ff0c18 3733 #define BP_SIM_CLKDIV1_OUTDIV4 (16U) //!< Bit position for SIM_CLKDIV1_OUTDIV4.
mbed_official 146:f64d43ff0c18 3734 #define BM_SIM_CLKDIV1_OUTDIV4 (0x000F0000U) //!< Bit mask for SIM_CLKDIV1_OUTDIV4.
mbed_official 146:f64d43ff0c18 3735 #define BS_SIM_CLKDIV1_OUTDIV4 (4U) //!< Bit field size in bits for SIM_CLKDIV1_OUTDIV4.
mbed_official 146:f64d43ff0c18 3736
mbed_official 146:f64d43ff0c18 3737 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3738 //! @brief Read current value of the SIM_CLKDIV1_OUTDIV4 field.
mbed_official 146:f64d43ff0c18 3739 #define BR_SIM_CLKDIV1_OUTDIV4 (HW_SIM_CLKDIV1.B.OUTDIV4)
mbed_official 146:f64d43ff0c18 3740 #endif
mbed_official 146:f64d43ff0c18 3741
mbed_official 146:f64d43ff0c18 3742 //! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV4.
mbed_official 146:f64d43ff0c18 3743 #define BF_SIM_CLKDIV1_OUTDIV4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_CLKDIV1_OUTDIV4), uint32_t) & BM_SIM_CLKDIV1_OUTDIV4)
mbed_official 146:f64d43ff0c18 3744
mbed_official 146:f64d43ff0c18 3745 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3746 //! @brief Set the OUTDIV4 field to a new value.
mbed_official 146:f64d43ff0c18 3747 #define BW_SIM_CLKDIV1_OUTDIV4(v) (HW_SIM_CLKDIV1_WR((HW_SIM_CLKDIV1_RD() & ~BM_SIM_CLKDIV1_OUTDIV4) | BF_SIM_CLKDIV1_OUTDIV4(v)))
mbed_official 146:f64d43ff0c18 3748 #endif
mbed_official 146:f64d43ff0c18 3749 //@}
mbed_official 146:f64d43ff0c18 3750
mbed_official 146:f64d43ff0c18 3751 /*!
mbed_official 146:f64d43ff0c18 3752 * @name Register SIM_CLKDIV1, field OUTDIV3[23:20] (RW)
mbed_official 146:f64d43ff0c18 3753 *
mbed_official 146:f64d43ff0c18 3754 * This field sets the divide value for the FlexBus clock (external pin FB_CLK)
mbed_official 146:f64d43ff0c18 3755 * from MCGOUTCLK. At the end of reset, it is loaded with either 0001 or 1111
mbed_official 146:f64d43ff0c18 3756 * depending on FTF_FOPT[LPBOOT]. The FlexBus clock frequency must be an integer
mbed_official 146:f64d43ff0c18 3757 * divide of the system clock frequency.
mbed_official 146:f64d43ff0c18 3758 *
mbed_official 146:f64d43ff0c18 3759 * Values:
mbed_official 146:f64d43ff0c18 3760 * - 0000 - Divide-by-1.
mbed_official 146:f64d43ff0c18 3761 * - 0001 - Divide-by-2.
mbed_official 146:f64d43ff0c18 3762 * - 0010 - Divide-by-3.
mbed_official 146:f64d43ff0c18 3763 * - 0011 - Divide-by-4.
mbed_official 146:f64d43ff0c18 3764 * - 0100 - Divide-by-5.
mbed_official 146:f64d43ff0c18 3765 * - 0101 - Divide-by-6.
mbed_official 146:f64d43ff0c18 3766 * - 0110 - Divide-by-7.
mbed_official 146:f64d43ff0c18 3767 * - 0111 - Divide-by-8.
mbed_official 146:f64d43ff0c18 3768 * - 1000 - Divide-by-9.
mbed_official 146:f64d43ff0c18 3769 * - 1001 - Divide-by-10.
mbed_official 146:f64d43ff0c18 3770 * - 1010 - Divide-by-11.
mbed_official 146:f64d43ff0c18 3771 * - 1011 - Divide-by-12.
mbed_official 146:f64d43ff0c18 3772 * - 1100 - Divide-by-13.
mbed_official 146:f64d43ff0c18 3773 * - 1101 - Divide-by-14.
mbed_official 146:f64d43ff0c18 3774 * - 1110 - Divide-by-15.
mbed_official 146:f64d43ff0c18 3775 * - 1111 - Divide-by-16.
mbed_official 146:f64d43ff0c18 3776 */
mbed_official 146:f64d43ff0c18 3777 //@{
mbed_official 146:f64d43ff0c18 3778 #define BP_SIM_CLKDIV1_OUTDIV3 (20U) //!< Bit position for SIM_CLKDIV1_OUTDIV3.
mbed_official 146:f64d43ff0c18 3779 #define BM_SIM_CLKDIV1_OUTDIV3 (0x00F00000U) //!< Bit mask for SIM_CLKDIV1_OUTDIV3.
mbed_official 146:f64d43ff0c18 3780 #define BS_SIM_CLKDIV1_OUTDIV3 (4U) //!< Bit field size in bits for SIM_CLKDIV1_OUTDIV3.
mbed_official 146:f64d43ff0c18 3781
mbed_official 146:f64d43ff0c18 3782 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3783 //! @brief Read current value of the SIM_CLKDIV1_OUTDIV3 field.
mbed_official 146:f64d43ff0c18 3784 #define BR_SIM_CLKDIV1_OUTDIV3 (HW_SIM_CLKDIV1.B.OUTDIV3)
mbed_official 146:f64d43ff0c18 3785 #endif
mbed_official 146:f64d43ff0c18 3786
mbed_official 146:f64d43ff0c18 3787 //! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV3.
mbed_official 146:f64d43ff0c18 3788 #define BF_SIM_CLKDIV1_OUTDIV3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_CLKDIV1_OUTDIV3), uint32_t) & BM_SIM_CLKDIV1_OUTDIV3)
mbed_official 146:f64d43ff0c18 3789
mbed_official 146:f64d43ff0c18 3790 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3791 //! @brief Set the OUTDIV3 field to a new value.
mbed_official 146:f64d43ff0c18 3792 #define BW_SIM_CLKDIV1_OUTDIV3(v) (HW_SIM_CLKDIV1_WR((HW_SIM_CLKDIV1_RD() & ~BM_SIM_CLKDIV1_OUTDIV3) | BF_SIM_CLKDIV1_OUTDIV3(v)))
mbed_official 146:f64d43ff0c18 3793 #endif
mbed_official 146:f64d43ff0c18 3794 //@}
mbed_official 146:f64d43ff0c18 3795
mbed_official 146:f64d43ff0c18 3796 /*!
mbed_official 146:f64d43ff0c18 3797 * @name Register SIM_CLKDIV1, field OUTDIV2[27:24] (RW)
mbed_official 146:f64d43ff0c18 3798 *
mbed_official 146:f64d43ff0c18 3799 * This field sets the divide value for the bus clock from MCGOUTCLK. At the end
mbed_official 146:f64d43ff0c18 3800 * of reset, it is loaded with either 0000 or 0111 depending on
mbed_official 146:f64d43ff0c18 3801 * FTF_FOPT[LPBOOT]. The bus clock frequency must be an integer divide of the core/system clock
mbed_official 146:f64d43ff0c18 3802 * frequency.
mbed_official 146:f64d43ff0c18 3803 *
mbed_official 146:f64d43ff0c18 3804 * Values:
mbed_official 146:f64d43ff0c18 3805 * - 0000 - Divide-by-1.
mbed_official 146:f64d43ff0c18 3806 * - 0001 - Divide-by-2.
mbed_official 146:f64d43ff0c18 3807 * - 0010 - Divide-by-3.
mbed_official 146:f64d43ff0c18 3808 * - 0011 - Divide-by-4.
mbed_official 146:f64d43ff0c18 3809 * - 0100 - Divide-by-5.
mbed_official 146:f64d43ff0c18 3810 * - 0101 - Divide-by-6.
mbed_official 146:f64d43ff0c18 3811 * - 0110 - Divide-by-7.
mbed_official 146:f64d43ff0c18 3812 * - 0111 - Divide-by-8.
mbed_official 146:f64d43ff0c18 3813 * - 1000 - Divide-by-9.
mbed_official 146:f64d43ff0c18 3814 * - 1001 - Divide-by-10.
mbed_official 146:f64d43ff0c18 3815 * - 1010 - Divide-by-11.
mbed_official 146:f64d43ff0c18 3816 * - 1011 - Divide-by-12.
mbed_official 146:f64d43ff0c18 3817 * - 1100 - Divide-by-13.
mbed_official 146:f64d43ff0c18 3818 * - 1101 - Divide-by-14.
mbed_official 146:f64d43ff0c18 3819 * - 1110 - Divide-by-15.
mbed_official 146:f64d43ff0c18 3820 * - 1111 - Divide-by-16.
mbed_official 146:f64d43ff0c18 3821 */
mbed_official 146:f64d43ff0c18 3822 //@{
mbed_official 146:f64d43ff0c18 3823 #define BP_SIM_CLKDIV1_OUTDIV2 (24U) //!< Bit position for SIM_CLKDIV1_OUTDIV2.
mbed_official 146:f64d43ff0c18 3824 #define BM_SIM_CLKDIV1_OUTDIV2 (0x0F000000U) //!< Bit mask for SIM_CLKDIV1_OUTDIV2.
mbed_official 146:f64d43ff0c18 3825 #define BS_SIM_CLKDIV1_OUTDIV2 (4U) //!< Bit field size in bits for SIM_CLKDIV1_OUTDIV2.
mbed_official 146:f64d43ff0c18 3826
mbed_official 146:f64d43ff0c18 3827 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3828 //! @brief Read current value of the SIM_CLKDIV1_OUTDIV2 field.
mbed_official 146:f64d43ff0c18 3829 #define BR_SIM_CLKDIV1_OUTDIV2 (HW_SIM_CLKDIV1.B.OUTDIV2)
mbed_official 146:f64d43ff0c18 3830 #endif
mbed_official 146:f64d43ff0c18 3831
mbed_official 146:f64d43ff0c18 3832 //! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV2.
mbed_official 146:f64d43ff0c18 3833 #define BF_SIM_CLKDIV1_OUTDIV2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_CLKDIV1_OUTDIV2), uint32_t) & BM_SIM_CLKDIV1_OUTDIV2)
mbed_official 146:f64d43ff0c18 3834
mbed_official 146:f64d43ff0c18 3835 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3836 //! @brief Set the OUTDIV2 field to a new value.
mbed_official 146:f64d43ff0c18 3837 #define BW_SIM_CLKDIV1_OUTDIV2(v) (HW_SIM_CLKDIV1_WR((HW_SIM_CLKDIV1_RD() & ~BM_SIM_CLKDIV1_OUTDIV2) | BF_SIM_CLKDIV1_OUTDIV2(v)))
mbed_official 146:f64d43ff0c18 3838 #endif
mbed_official 146:f64d43ff0c18 3839 //@}
mbed_official 146:f64d43ff0c18 3840
mbed_official 146:f64d43ff0c18 3841 /*!
mbed_official 146:f64d43ff0c18 3842 * @name Register SIM_CLKDIV1, field OUTDIV1[31:28] (RW)
mbed_official 146:f64d43ff0c18 3843 *
mbed_official 146:f64d43ff0c18 3844 * This field sets the divide value for the core/system clock from MCGOUTCLK. At
mbed_official 146:f64d43ff0c18 3845 * the end of reset, it is loaded with either 0000 or 0111 depending on
mbed_official 146:f64d43ff0c18 3846 * FTF_FOPT[LPBOOT].
mbed_official 146:f64d43ff0c18 3847 *
mbed_official 146:f64d43ff0c18 3848 * Values:
mbed_official 146:f64d43ff0c18 3849 * - 0000 - Divide-by-1.
mbed_official 146:f64d43ff0c18 3850 * - 0001 - Divide-by-2.
mbed_official 146:f64d43ff0c18 3851 * - 0010 - Divide-by-3.
mbed_official 146:f64d43ff0c18 3852 * - 0011 - Divide-by-4.
mbed_official 146:f64d43ff0c18 3853 * - 0100 - Divide-by-5.
mbed_official 146:f64d43ff0c18 3854 * - 0101 - Divide-by-6.
mbed_official 146:f64d43ff0c18 3855 * - 0110 - Divide-by-7.
mbed_official 146:f64d43ff0c18 3856 * - 0111 - Divide-by-8.
mbed_official 146:f64d43ff0c18 3857 * - 1000 - Divide-by-9.
mbed_official 146:f64d43ff0c18 3858 * - 1001 - Divide-by-10.
mbed_official 146:f64d43ff0c18 3859 * - 1010 - Divide-by-11.
mbed_official 146:f64d43ff0c18 3860 * - 1011 - Divide-by-12.
mbed_official 146:f64d43ff0c18 3861 * - 1100 - Divide-by-13.
mbed_official 146:f64d43ff0c18 3862 * - 1101 - Divide-by-14.
mbed_official 146:f64d43ff0c18 3863 * - 1110 - Divide-by-15.
mbed_official 146:f64d43ff0c18 3864 * - 1111 - Divide-by-16.
mbed_official 146:f64d43ff0c18 3865 */
mbed_official 146:f64d43ff0c18 3866 //@{
mbed_official 146:f64d43ff0c18 3867 #define BP_SIM_CLKDIV1_OUTDIV1 (28U) //!< Bit position for SIM_CLKDIV1_OUTDIV1.
mbed_official 146:f64d43ff0c18 3868 #define BM_SIM_CLKDIV1_OUTDIV1 (0xF0000000U) //!< Bit mask for SIM_CLKDIV1_OUTDIV1.
mbed_official 146:f64d43ff0c18 3869 #define BS_SIM_CLKDIV1_OUTDIV1 (4U) //!< Bit field size in bits for SIM_CLKDIV1_OUTDIV1.
mbed_official 146:f64d43ff0c18 3870
mbed_official 146:f64d43ff0c18 3871 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3872 //! @brief Read current value of the SIM_CLKDIV1_OUTDIV1 field.
mbed_official 146:f64d43ff0c18 3873 #define BR_SIM_CLKDIV1_OUTDIV1 (HW_SIM_CLKDIV1.B.OUTDIV1)
mbed_official 146:f64d43ff0c18 3874 #endif
mbed_official 146:f64d43ff0c18 3875
mbed_official 146:f64d43ff0c18 3876 //! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV1.
mbed_official 146:f64d43ff0c18 3877 #define BF_SIM_CLKDIV1_OUTDIV1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_CLKDIV1_OUTDIV1), uint32_t) & BM_SIM_CLKDIV1_OUTDIV1)
mbed_official 146:f64d43ff0c18 3878
mbed_official 146:f64d43ff0c18 3879 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3880 //! @brief Set the OUTDIV1 field to a new value.
mbed_official 146:f64d43ff0c18 3881 #define BW_SIM_CLKDIV1_OUTDIV1(v) (HW_SIM_CLKDIV1_WR((HW_SIM_CLKDIV1_RD() & ~BM_SIM_CLKDIV1_OUTDIV1) | BF_SIM_CLKDIV1_OUTDIV1(v)))
mbed_official 146:f64d43ff0c18 3882 #endif
mbed_official 146:f64d43ff0c18 3883 //@}
mbed_official 146:f64d43ff0c18 3884
mbed_official 146:f64d43ff0c18 3885 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3886 // HW_SIM_CLKDIV2 - System Clock Divider Register 2
mbed_official 146:f64d43ff0c18 3887 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3888
mbed_official 146:f64d43ff0c18 3889 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3890 /*!
mbed_official 146:f64d43ff0c18 3891 * @brief HW_SIM_CLKDIV2 - System Clock Divider Register 2 (RW)
mbed_official 146:f64d43ff0c18 3892 *
mbed_official 146:f64d43ff0c18 3893 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 3894 */
mbed_official 146:f64d43ff0c18 3895 typedef union _hw_sim_clkdiv2
mbed_official 146:f64d43ff0c18 3896 {
mbed_official 146:f64d43ff0c18 3897 uint32_t U;
mbed_official 146:f64d43ff0c18 3898 struct _hw_sim_clkdiv2_bitfields
mbed_official 146:f64d43ff0c18 3899 {
mbed_official 146:f64d43ff0c18 3900 uint32_t USBFRAC : 1; //!< [0] USB clock divider fraction
mbed_official 146:f64d43ff0c18 3901 uint32_t USBDIV : 3; //!< [3:1] USB clock divider divisor
mbed_official 146:f64d43ff0c18 3902 uint32_t RESERVED0 : 28; //!< [31:4]
mbed_official 146:f64d43ff0c18 3903 } B;
mbed_official 146:f64d43ff0c18 3904 } hw_sim_clkdiv2_t;
mbed_official 146:f64d43ff0c18 3905 #endif
mbed_official 146:f64d43ff0c18 3906
mbed_official 146:f64d43ff0c18 3907 /*!
mbed_official 146:f64d43ff0c18 3908 * @name Constants and macros for entire SIM_CLKDIV2 register
mbed_official 146:f64d43ff0c18 3909 */
mbed_official 146:f64d43ff0c18 3910 //@{
mbed_official 146:f64d43ff0c18 3911 #define HW_SIM_CLKDIV2_ADDR (REGS_SIM_BASE + 0x1048U)
mbed_official 146:f64d43ff0c18 3912
mbed_official 146:f64d43ff0c18 3913 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3914 #define HW_SIM_CLKDIV2 (*(__IO hw_sim_clkdiv2_t *) HW_SIM_CLKDIV2_ADDR)
mbed_official 146:f64d43ff0c18 3915 #define HW_SIM_CLKDIV2_RD() (HW_SIM_CLKDIV2.U)
mbed_official 146:f64d43ff0c18 3916 #define HW_SIM_CLKDIV2_WR(v) (HW_SIM_CLKDIV2.U = (v))
mbed_official 146:f64d43ff0c18 3917 #define HW_SIM_CLKDIV2_SET(v) (HW_SIM_CLKDIV2_WR(HW_SIM_CLKDIV2_RD() | (v)))
mbed_official 146:f64d43ff0c18 3918 #define HW_SIM_CLKDIV2_CLR(v) (HW_SIM_CLKDIV2_WR(HW_SIM_CLKDIV2_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 3919 #define HW_SIM_CLKDIV2_TOG(v) (HW_SIM_CLKDIV2_WR(HW_SIM_CLKDIV2_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 3920 #endif
mbed_official 146:f64d43ff0c18 3921 //@}
mbed_official 146:f64d43ff0c18 3922
mbed_official 146:f64d43ff0c18 3923 /*
mbed_official 146:f64d43ff0c18 3924 * Constants & macros for individual SIM_CLKDIV2 bitfields
mbed_official 146:f64d43ff0c18 3925 */
mbed_official 146:f64d43ff0c18 3926
mbed_official 146:f64d43ff0c18 3927 /*!
mbed_official 146:f64d43ff0c18 3928 * @name Register SIM_CLKDIV2, field USBFRAC[0] (RW)
mbed_official 146:f64d43ff0c18 3929 *
mbed_official 146:f64d43ff0c18 3930 * This field sets the fraction multiply value for the fractional clock divider
mbed_official 146:f64d43ff0c18 3931 * when the MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] =
mbed_official 146:f64d43ff0c18 3932 * 1). Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
mbed_official 146:f64d43ff0c18 3933 */
mbed_official 146:f64d43ff0c18 3934 //@{
mbed_official 146:f64d43ff0c18 3935 #define BP_SIM_CLKDIV2_USBFRAC (0U) //!< Bit position for SIM_CLKDIV2_USBFRAC.
mbed_official 146:f64d43ff0c18 3936 #define BM_SIM_CLKDIV2_USBFRAC (0x00000001U) //!< Bit mask for SIM_CLKDIV2_USBFRAC.
mbed_official 146:f64d43ff0c18 3937 #define BS_SIM_CLKDIV2_USBFRAC (1U) //!< Bit field size in bits for SIM_CLKDIV2_USBFRAC.
mbed_official 146:f64d43ff0c18 3938
mbed_official 146:f64d43ff0c18 3939 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3940 //! @brief Read current value of the SIM_CLKDIV2_USBFRAC field.
mbed_official 146:f64d43ff0c18 3941 #define BR_SIM_CLKDIV2_USBFRAC (BITBAND_ACCESS32(HW_SIM_CLKDIV2_ADDR, BP_SIM_CLKDIV2_USBFRAC))
mbed_official 146:f64d43ff0c18 3942 #endif
mbed_official 146:f64d43ff0c18 3943
mbed_official 146:f64d43ff0c18 3944 //! @brief Format value for bitfield SIM_CLKDIV2_USBFRAC.
mbed_official 146:f64d43ff0c18 3945 #define BF_SIM_CLKDIV2_USBFRAC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_CLKDIV2_USBFRAC), uint32_t) & BM_SIM_CLKDIV2_USBFRAC)
mbed_official 146:f64d43ff0c18 3946
mbed_official 146:f64d43ff0c18 3947 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3948 //! @brief Set the USBFRAC field to a new value.
mbed_official 146:f64d43ff0c18 3949 #define BW_SIM_CLKDIV2_USBFRAC(v) (BITBAND_ACCESS32(HW_SIM_CLKDIV2_ADDR, BP_SIM_CLKDIV2_USBFRAC) = (v))
mbed_official 146:f64d43ff0c18 3950 #endif
mbed_official 146:f64d43ff0c18 3951 //@}
mbed_official 146:f64d43ff0c18 3952
mbed_official 146:f64d43ff0c18 3953 /*!
mbed_official 146:f64d43ff0c18 3954 * @name Register SIM_CLKDIV2, field USBDIV[3:1] (RW)
mbed_official 146:f64d43ff0c18 3955 *
mbed_official 146:f64d43ff0c18 3956 * This field sets the divide value for the fractional clock divider when the
mbed_official 146:f64d43ff0c18 3957 * MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] = 1). Divider
mbed_official 146:f64d43ff0c18 3958 * output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
mbed_official 146:f64d43ff0c18 3959 */
mbed_official 146:f64d43ff0c18 3960 //@{
mbed_official 146:f64d43ff0c18 3961 #define BP_SIM_CLKDIV2_USBDIV (1U) //!< Bit position for SIM_CLKDIV2_USBDIV.
mbed_official 146:f64d43ff0c18 3962 #define BM_SIM_CLKDIV2_USBDIV (0x0000000EU) //!< Bit mask for SIM_CLKDIV2_USBDIV.
mbed_official 146:f64d43ff0c18 3963 #define BS_SIM_CLKDIV2_USBDIV (3U) //!< Bit field size in bits for SIM_CLKDIV2_USBDIV.
mbed_official 146:f64d43ff0c18 3964
mbed_official 146:f64d43ff0c18 3965 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3966 //! @brief Read current value of the SIM_CLKDIV2_USBDIV field.
mbed_official 146:f64d43ff0c18 3967 #define BR_SIM_CLKDIV2_USBDIV (HW_SIM_CLKDIV2.B.USBDIV)
mbed_official 146:f64d43ff0c18 3968 #endif
mbed_official 146:f64d43ff0c18 3969
mbed_official 146:f64d43ff0c18 3970 //! @brief Format value for bitfield SIM_CLKDIV2_USBDIV.
mbed_official 146:f64d43ff0c18 3971 #define BF_SIM_CLKDIV2_USBDIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_CLKDIV2_USBDIV), uint32_t) & BM_SIM_CLKDIV2_USBDIV)
mbed_official 146:f64d43ff0c18 3972
mbed_official 146:f64d43ff0c18 3973 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3974 //! @brief Set the USBDIV field to a new value.
mbed_official 146:f64d43ff0c18 3975 #define BW_SIM_CLKDIV2_USBDIV(v) (HW_SIM_CLKDIV2_WR((HW_SIM_CLKDIV2_RD() & ~BM_SIM_CLKDIV2_USBDIV) | BF_SIM_CLKDIV2_USBDIV(v)))
mbed_official 146:f64d43ff0c18 3976 #endif
mbed_official 146:f64d43ff0c18 3977 //@}
mbed_official 146:f64d43ff0c18 3978
mbed_official 146:f64d43ff0c18 3979 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3980 // HW_SIM_FCFG1 - Flash Configuration Register 1
mbed_official 146:f64d43ff0c18 3981 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3982
mbed_official 146:f64d43ff0c18 3983 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3984 /*!
mbed_official 146:f64d43ff0c18 3985 * @brief HW_SIM_FCFG1 - Flash Configuration Register 1 (RW)
mbed_official 146:f64d43ff0c18 3986 *
mbed_official 146:f64d43ff0c18 3987 * Reset value: 0xFF0F0F00U
mbed_official 146:f64d43ff0c18 3988 *
mbed_official 146:f64d43ff0c18 3989 * For devices with FlexNVM: The reset value of EESIZE and DEPART are based on
mbed_official 146:f64d43ff0c18 3990 * user programming in user IFR via the PGMPART flash command. For devices with
mbed_official 146:f64d43ff0c18 3991 * program flash only:
mbed_official 146:f64d43ff0c18 3992 */
mbed_official 146:f64d43ff0c18 3993 typedef union _hw_sim_fcfg1
mbed_official 146:f64d43ff0c18 3994 {
mbed_official 146:f64d43ff0c18 3995 uint32_t U;
mbed_official 146:f64d43ff0c18 3996 struct _hw_sim_fcfg1_bitfields
mbed_official 146:f64d43ff0c18 3997 {
mbed_official 146:f64d43ff0c18 3998 uint32_t FLASHDIS : 1; //!< [0] Flash Disable
mbed_official 146:f64d43ff0c18 3999 uint32_t FLASHDOZE : 1; //!< [1] Flash Doze
mbed_official 146:f64d43ff0c18 4000 uint32_t RESERVED0 : 6; //!< [7:2]
mbed_official 146:f64d43ff0c18 4001 uint32_t DEPART : 4; //!< [11:8] FlexNVM partition
mbed_official 146:f64d43ff0c18 4002 uint32_t RESERVED1 : 4; //!< [15:12]
mbed_official 146:f64d43ff0c18 4003 uint32_t EESIZE : 4; //!< [19:16] EEPROM size
mbed_official 146:f64d43ff0c18 4004 uint32_t RESERVED2 : 4; //!< [23:20]
mbed_official 146:f64d43ff0c18 4005 uint32_t PFSIZE : 4; //!< [27:24] Program flash size
mbed_official 146:f64d43ff0c18 4006 uint32_t NVMSIZE : 4; //!< [31:28] FlexNVM size
mbed_official 146:f64d43ff0c18 4007 } B;
mbed_official 146:f64d43ff0c18 4008 } hw_sim_fcfg1_t;
mbed_official 146:f64d43ff0c18 4009 #endif
mbed_official 146:f64d43ff0c18 4010
mbed_official 146:f64d43ff0c18 4011 /*!
mbed_official 146:f64d43ff0c18 4012 * @name Constants and macros for entire SIM_FCFG1 register
mbed_official 146:f64d43ff0c18 4013 */
mbed_official 146:f64d43ff0c18 4014 //@{
mbed_official 146:f64d43ff0c18 4015 #define HW_SIM_FCFG1_ADDR (REGS_SIM_BASE + 0x104CU)
mbed_official 146:f64d43ff0c18 4016
mbed_official 146:f64d43ff0c18 4017 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4018 #define HW_SIM_FCFG1 (*(__IO hw_sim_fcfg1_t *) HW_SIM_FCFG1_ADDR)
mbed_official 146:f64d43ff0c18 4019 #define HW_SIM_FCFG1_RD() (HW_SIM_FCFG1.U)
mbed_official 146:f64d43ff0c18 4020 #define HW_SIM_FCFG1_WR(v) (HW_SIM_FCFG1.U = (v))
mbed_official 146:f64d43ff0c18 4021 #define HW_SIM_FCFG1_SET(v) (HW_SIM_FCFG1_WR(HW_SIM_FCFG1_RD() | (v)))
mbed_official 146:f64d43ff0c18 4022 #define HW_SIM_FCFG1_CLR(v) (HW_SIM_FCFG1_WR(HW_SIM_FCFG1_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 4023 #define HW_SIM_FCFG1_TOG(v) (HW_SIM_FCFG1_WR(HW_SIM_FCFG1_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 4024 #endif
mbed_official 146:f64d43ff0c18 4025 //@}
mbed_official 146:f64d43ff0c18 4026
mbed_official 146:f64d43ff0c18 4027 /*
mbed_official 146:f64d43ff0c18 4028 * Constants & macros for individual SIM_FCFG1 bitfields
mbed_official 146:f64d43ff0c18 4029 */
mbed_official 146:f64d43ff0c18 4030
mbed_official 146:f64d43ff0c18 4031 /*!
mbed_official 146:f64d43ff0c18 4032 * @name Register SIM_FCFG1, field FLASHDIS[0] (RW)
mbed_official 146:f64d43ff0c18 4033 *
mbed_official 146:f64d43ff0c18 4034 * Flash accesses are disabled (and generate a bus error) and the Flash memory
mbed_official 146:f64d43ff0c18 4035 * is placed in a low power state. This bit should not be changed during VLP
mbed_official 146:f64d43ff0c18 4036 * modes. Relocate the interrupt vectors out of Flash memory before disabling the
mbed_official 146:f64d43ff0c18 4037 * Flash.
mbed_official 146:f64d43ff0c18 4038 *
mbed_official 146:f64d43ff0c18 4039 * Values:
mbed_official 146:f64d43ff0c18 4040 * - 0 - Flash is enabled
mbed_official 146:f64d43ff0c18 4041 * - 1 - Flash is disabled
mbed_official 146:f64d43ff0c18 4042 */
mbed_official 146:f64d43ff0c18 4043 //@{
mbed_official 146:f64d43ff0c18 4044 #define BP_SIM_FCFG1_FLASHDIS (0U) //!< Bit position for SIM_FCFG1_FLASHDIS.
mbed_official 146:f64d43ff0c18 4045 #define BM_SIM_FCFG1_FLASHDIS (0x00000001U) //!< Bit mask for SIM_FCFG1_FLASHDIS.
mbed_official 146:f64d43ff0c18 4046 #define BS_SIM_FCFG1_FLASHDIS (1U) //!< Bit field size in bits for SIM_FCFG1_FLASHDIS.
mbed_official 146:f64d43ff0c18 4047
mbed_official 146:f64d43ff0c18 4048 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4049 //! @brief Read current value of the SIM_FCFG1_FLASHDIS field.
mbed_official 146:f64d43ff0c18 4050 #define BR_SIM_FCFG1_FLASHDIS (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR, BP_SIM_FCFG1_FLASHDIS))
mbed_official 146:f64d43ff0c18 4051 #endif
mbed_official 146:f64d43ff0c18 4052
mbed_official 146:f64d43ff0c18 4053 //! @brief Format value for bitfield SIM_FCFG1_FLASHDIS.
mbed_official 146:f64d43ff0c18 4054 #define BF_SIM_FCFG1_FLASHDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_FCFG1_FLASHDIS), uint32_t) & BM_SIM_FCFG1_FLASHDIS)
mbed_official 146:f64d43ff0c18 4055
mbed_official 146:f64d43ff0c18 4056 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4057 //! @brief Set the FLASHDIS field to a new value.
mbed_official 146:f64d43ff0c18 4058 #define BW_SIM_FCFG1_FLASHDIS(v) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR, BP_SIM_FCFG1_FLASHDIS) = (v))
mbed_official 146:f64d43ff0c18 4059 #endif
mbed_official 146:f64d43ff0c18 4060 //@}
mbed_official 146:f64d43ff0c18 4061
mbed_official 146:f64d43ff0c18 4062 /*!
mbed_official 146:f64d43ff0c18 4063 * @name Register SIM_FCFG1, field FLASHDOZE[1] (RW)
mbed_official 146:f64d43ff0c18 4064 *
mbed_official 146:f64d43ff0c18 4065 * When set, Flash memory is disabled for the duration of Wait mode. An attempt
mbed_official 146:f64d43ff0c18 4066 * by the DMA or other bus master to access the Flash when the Flash is disabled
mbed_official 146:f64d43ff0c18 4067 * will result in a bus error. This bit should be clear during VLP modes. The
mbed_official 146:f64d43ff0c18 4068 * Flash will be automatically enabled again at the end of Wait mode so interrupt
mbed_official 146:f64d43ff0c18 4069 * vectors do not need to be relocated out of Flash memory. The wakeup time from
mbed_official 146:f64d43ff0c18 4070 * Wait mode is extended when this bit is set.
mbed_official 146:f64d43ff0c18 4071 *
mbed_official 146:f64d43ff0c18 4072 * Values:
mbed_official 146:f64d43ff0c18 4073 * - 0 - Flash remains enabled during Wait mode
mbed_official 146:f64d43ff0c18 4074 * - 1 - Flash is disabled for the duration of Wait mode
mbed_official 146:f64d43ff0c18 4075 */
mbed_official 146:f64d43ff0c18 4076 //@{
mbed_official 146:f64d43ff0c18 4077 #define BP_SIM_FCFG1_FLASHDOZE (1U) //!< Bit position for SIM_FCFG1_FLASHDOZE.
mbed_official 146:f64d43ff0c18 4078 #define BM_SIM_FCFG1_FLASHDOZE (0x00000002U) //!< Bit mask for SIM_FCFG1_FLASHDOZE.
mbed_official 146:f64d43ff0c18 4079 #define BS_SIM_FCFG1_FLASHDOZE (1U) //!< Bit field size in bits for SIM_FCFG1_FLASHDOZE.
mbed_official 146:f64d43ff0c18 4080
mbed_official 146:f64d43ff0c18 4081 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4082 //! @brief Read current value of the SIM_FCFG1_FLASHDOZE field.
mbed_official 146:f64d43ff0c18 4083 #define BR_SIM_FCFG1_FLASHDOZE (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR, BP_SIM_FCFG1_FLASHDOZE))
mbed_official 146:f64d43ff0c18 4084 #endif
mbed_official 146:f64d43ff0c18 4085
mbed_official 146:f64d43ff0c18 4086 //! @brief Format value for bitfield SIM_FCFG1_FLASHDOZE.
mbed_official 146:f64d43ff0c18 4087 #define BF_SIM_FCFG1_FLASHDOZE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_FCFG1_FLASHDOZE), uint32_t) & BM_SIM_FCFG1_FLASHDOZE)
mbed_official 146:f64d43ff0c18 4088
mbed_official 146:f64d43ff0c18 4089 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4090 //! @brief Set the FLASHDOZE field to a new value.
mbed_official 146:f64d43ff0c18 4091 #define BW_SIM_FCFG1_FLASHDOZE(v) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR, BP_SIM_FCFG1_FLASHDOZE) = (v))
mbed_official 146:f64d43ff0c18 4092 #endif
mbed_official 146:f64d43ff0c18 4093 //@}
mbed_official 146:f64d43ff0c18 4094
mbed_official 146:f64d43ff0c18 4095 /*!
mbed_official 146:f64d43ff0c18 4096 * @name Register SIM_FCFG1, field DEPART[11:8] (RO)
mbed_official 146:f64d43ff0c18 4097 *
mbed_official 146:f64d43ff0c18 4098 * For devices with FlexNVM: Data flash / EEPROM backup split . See DEPART bit
mbed_official 146:f64d43ff0c18 4099 * description in FTFE chapter. For devices without FlexNVM: Reserved
mbed_official 146:f64d43ff0c18 4100 */
mbed_official 146:f64d43ff0c18 4101 //@{
mbed_official 146:f64d43ff0c18 4102 #define BP_SIM_FCFG1_DEPART (8U) //!< Bit position for SIM_FCFG1_DEPART.
mbed_official 146:f64d43ff0c18 4103 #define BM_SIM_FCFG1_DEPART (0x00000F00U) //!< Bit mask for SIM_FCFG1_DEPART.
mbed_official 146:f64d43ff0c18 4104 #define BS_SIM_FCFG1_DEPART (4U) //!< Bit field size in bits for SIM_FCFG1_DEPART.
mbed_official 146:f64d43ff0c18 4105
mbed_official 146:f64d43ff0c18 4106 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4107 //! @brief Read current value of the SIM_FCFG1_DEPART field.
mbed_official 146:f64d43ff0c18 4108 #define BR_SIM_FCFG1_DEPART (HW_SIM_FCFG1.B.DEPART)
mbed_official 146:f64d43ff0c18 4109 #endif
mbed_official 146:f64d43ff0c18 4110 //@}
mbed_official 146:f64d43ff0c18 4111
mbed_official 146:f64d43ff0c18 4112 /*!
mbed_official 146:f64d43ff0c18 4113 * @name Register SIM_FCFG1, field EESIZE[19:16] (RO)
mbed_official 146:f64d43ff0c18 4114 *
mbed_official 146:f64d43ff0c18 4115 * EEPROM data size .
mbed_official 146:f64d43ff0c18 4116 *
mbed_official 146:f64d43ff0c18 4117 * Values:
mbed_official 146:f64d43ff0c18 4118 * - 0000 - 16 KB
mbed_official 146:f64d43ff0c18 4119 * - 0001 - 8 KB
mbed_official 146:f64d43ff0c18 4120 * - 0010 - 4 KB
mbed_official 146:f64d43ff0c18 4121 * - 0011 - 2 KB
mbed_official 146:f64d43ff0c18 4122 * - 0100 - 1 KB
mbed_official 146:f64d43ff0c18 4123 * - 0101 - 512 Bytes
mbed_official 146:f64d43ff0c18 4124 * - 0110 - 256 Bytes
mbed_official 146:f64d43ff0c18 4125 * - 0111 - 128 Bytes
mbed_official 146:f64d43ff0c18 4126 * - 1000 - 64 Bytes
mbed_official 146:f64d43ff0c18 4127 * - 1001 - 32 Bytes
mbed_official 146:f64d43ff0c18 4128 * - 1111 - 0 Bytes
mbed_official 146:f64d43ff0c18 4129 */
mbed_official 146:f64d43ff0c18 4130 //@{
mbed_official 146:f64d43ff0c18 4131 #define BP_SIM_FCFG1_EESIZE (16U) //!< Bit position for SIM_FCFG1_EESIZE.
mbed_official 146:f64d43ff0c18 4132 #define BM_SIM_FCFG1_EESIZE (0x000F0000U) //!< Bit mask for SIM_FCFG1_EESIZE.
mbed_official 146:f64d43ff0c18 4133 #define BS_SIM_FCFG1_EESIZE (4U) //!< Bit field size in bits for SIM_FCFG1_EESIZE.
mbed_official 146:f64d43ff0c18 4134
mbed_official 146:f64d43ff0c18 4135 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4136 //! @brief Read current value of the SIM_FCFG1_EESIZE field.
mbed_official 146:f64d43ff0c18 4137 #define BR_SIM_FCFG1_EESIZE (HW_SIM_FCFG1.B.EESIZE)
mbed_official 146:f64d43ff0c18 4138 #endif
mbed_official 146:f64d43ff0c18 4139 //@}
mbed_official 146:f64d43ff0c18 4140
mbed_official 146:f64d43ff0c18 4141 /*!
mbed_official 146:f64d43ff0c18 4142 * @name Register SIM_FCFG1, field PFSIZE[27:24] (RO)
mbed_official 146:f64d43ff0c18 4143 *
mbed_official 146:f64d43ff0c18 4144 * This field specifies the amount of program flash memory available on the
mbed_official 146:f64d43ff0c18 4145 * device . Undefined values are reserved.
mbed_official 146:f64d43ff0c18 4146 *
mbed_official 146:f64d43ff0c18 4147 * Values:
mbed_official 146:f64d43ff0c18 4148 * - 0011 - 32 KB of program flash memory
mbed_official 146:f64d43ff0c18 4149 * - 0101 - 64 KB of program flash memory
mbed_official 146:f64d43ff0c18 4150 * - 0111 - 128 KB of program flash memory
mbed_official 146:f64d43ff0c18 4151 * - 1001 - 256 KB of program flash memory
mbed_official 146:f64d43ff0c18 4152 * - 1011 - 512 KB of program flash memory
mbed_official 146:f64d43ff0c18 4153 * - 1101 - 1024 KB of program flash memory
mbed_official 146:f64d43ff0c18 4154 * - 1111 - 1024 KB of program flash memory
mbed_official 146:f64d43ff0c18 4155 */
mbed_official 146:f64d43ff0c18 4156 //@{
mbed_official 146:f64d43ff0c18 4157 #define BP_SIM_FCFG1_PFSIZE (24U) //!< Bit position for SIM_FCFG1_PFSIZE.
mbed_official 146:f64d43ff0c18 4158 #define BM_SIM_FCFG1_PFSIZE (0x0F000000U) //!< Bit mask for SIM_FCFG1_PFSIZE.
mbed_official 146:f64d43ff0c18 4159 #define BS_SIM_FCFG1_PFSIZE (4U) //!< Bit field size in bits for SIM_FCFG1_PFSIZE.
mbed_official 146:f64d43ff0c18 4160
mbed_official 146:f64d43ff0c18 4161 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4162 //! @brief Read current value of the SIM_FCFG1_PFSIZE field.
mbed_official 146:f64d43ff0c18 4163 #define BR_SIM_FCFG1_PFSIZE (HW_SIM_FCFG1.B.PFSIZE)
mbed_official 146:f64d43ff0c18 4164 #endif
mbed_official 146:f64d43ff0c18 4165 //@}
mbed_official 146:f64d43ff0c18 4166
mbed_official 146:f64d43ff0c18 4167 /*!
mbed_official 146:f64d43ff0c18 4168 * @name Register SIM_FCFG1, field NVMSIZE[31:28] (RO)
mbed_official 146:f64d43ff0c18 4169 *
mbed_official 146:f64d43ff0c18 4170 * This field specifies the amount of FlexNVM memory available on the device .
mbed_official 146:f64d43ff0c18 4171 * Undefined values are reserved.
mbed_official 146:f64d43ff0c18 4172 *
mbed_official 146:f64d43ff0c18 4173 * Values:
mbed_official 146:f64d43ff0c18 4174 * - 0000 - 0 KB of FlexNVM
mbed_official 146:f64d43ff0c18 4175 * - 0011 - 32 KB of FlexNVM
mbed_official 146:f64d43ff0c18 4176 * - 0101 - 64 KB of FlexNVM
mbed_official 146:f64d43ff0c18 4177 * - 0111 - 128 KB of FlexNVM
mbed_official 146:f64d43ff0c18 4178 * - 1001 - 256 KB of FlexNVM
mbed_official 146:f64d43ff0c18 4179 * - 1011 - 512 KB of FlexNVM
mbed_official 146:f64d43ff0c18 4180 * - 1111 - 512 KB of FlexNVM
mbed_official 146:f64d43ff0c18 4181 */
mbed_official 146:f64d43ff0c18 4182 //@{
mbed_official 146:f64d43ff0c18 4183 #define BP_SIM_FCFG1_NVMSIZE (28U) //!< Bit position for SIM_FCFG1_NVMSIZE.
mbed_official 146:f64d43ff0c18 4184 #define BM_SIM_FCFG1_NVMSIZE (0xF0000000U) //!< Bit mask for SIM_FCFG1_NVMSIZE.
mbed_official 146:f64d43ff0c18 4185 #define BS_SIM_FCFG1_NVMSIZE (4U) //!< Bit field size in bits for SIM_FCFG1_NVMSIZE.
mbed_official 146:f64d43ff0c18 4186
mbed_official 146:f64d43ff0c18 4187 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4188 //! @brief Read current value of the SIM_FCFG1_NVMSIZE field.
mbed_official 146:f64d43ff0c18 4189 #define BR_SIM_FCFG1_NVMSIZE (HW_SIM_FCFG1.B.NVMSIZE)
mbed_official 146:f64d43ff0c18 4190 #endif
mbed_official 146:f64d43ff0c18 4191 //@}
mbed_official 146:f64d43ff0c18 4192
mbed_official 146:f64d43ff0c18 4193 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4194 // HW_SIM_FCFG2 - Flash Configuration Register 2
mbed_official 146:f64d43ff0c18 4195 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4196
mbed_official 146:f64d43ff0c18 4197 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4198 /*!
mbed_official 146:f64d43ff0c18 4199 * @brief HW_SIM_FCFG2 - Flash Configuration Register 2 (RO)
mbed_official 146:f64d43ff0c18 4200 *
mbed_official 146:f64d43ff0c18 4201 * Reset value: 0x7F7F0000U
mbed_official 146:f64d43ff0c18 4202 */
mbed_official 146:f64d43ff0c18 4203 typedef union _hw_sim_fcfg2
mbed_official 146:f64d43ff0c18 4204 {
mbed_official 146:f64d43ff0c18 4205 uint32_t U;
mbed_official 146:f64d43ff0c18 4206 struct _hw_sim_fcfg2_bitfields
mbed_official 146:f64d43ff0c18 4207 {
mbed_official 146:f64d43ff0c18 4208 uint32_t RESERVED0 : 16; //!< [15:0]
mbed_official 146:f64d43ff0c18 4209 uint32_t MAXADDR1 : 7; //!< [22:16] Max address block 1
mbed_official 146:f64d43ff0c18 4210 uint32_t PFLSH : 1; //!< [23] Program flash only
mbed_official 146:f64d43ff0c18 4211 uint32_t MAXADDR0 : 7; //!< [30:24] Max address block 0
mbed_official 146:f64d43ff0c18 4212 uint32_t RESERVED1 : 1; //!< [31]
mbed_official 146:f64d43ff0c18 4213 } B;
mbed_official 146:f64d43ff0c18 4214 } hw_sim_fcfg2_t;
mbed_official 146:f64d43ff0c18 4215 #endif
mbed_official 146:f64d43ff0c18 4216
mbed_official 146:f64d43ff0c18 4217 /*!
mbed_official 146:f64d43ff0c18 4218 * @name Constants and macros for entire SIM_FCFG2 register
mbed_official 146:f64d43ff0c18 4219 */
mbed_official 146:f64d43ff0c18 4220 //@{
mbed_official 146:f64d43ff0c18 4221 #define HW_SIM_FCFG2_ADDR (REGS_SIM_BASE + 0x1050U)
mbed_official 146:f64d43ff0c18 4222
mbed_official 146:f64d43ff0c18 4223 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4224 #define HW_SIM_FCFG2 (*(__I hw_sim_fcfg2_t *) HW_SIM_FCFG2_ADDR)
mbed_official 146:f64d43ff0c18 4225 #define HW_SIM_FCFG2_RD() (HW_SIM_FCFG2.U)
mbed_official 146:f64d43ff0c18 4226 #endif
mbed_official 146:f64d43ff0c18 4227 //@}
mbed_official 146:f64d43ff0c18 4228
mbed_official 146:f64d43ff0c18 4229 /*
mbed_official 146:f64d43ff0c18 4230 * Constants & macros for individual SIM_FCFG2 bitfields
mbed_official 146:f64d43ff0c18 4231 */
mbed_official 146:f64d43ff0c18 4232
mbed_official 146:f64d43ff0c18 4233 /*!
mbed_official 146:f64d43ff0c18 4234 * @name Register SIM_FCFG2, field MAXADDR1[22:16] (RO)
mbed_official 146:f64d43ff0c18 4235 *
mbed_official 146:f64d43ff0c18 4236 * For devices with FlexNVM: This field concatenated with 13 trailing zeros plus
mbed_official 146:f64d43ff0c18 4237 * the FlexNVM base address indicates the first invalid address of the FlexNVM
mbed_official 146:f64d43ff0c18 4238 * flash block. For example, if MAXADDR1 = 0x20 the first invalid address of
mbed_official 146:f64d43ff0c18 4239 * FlexNVM flash block is 0x4_0000 + 0x1000_0000 . This would be the MAXADDR1 value
mbed_official 146:f64d43ff0c18 4240 * for a device with 256 KB FlexNVM. For devices with program flash only: This
mbed_official 146:f64d43ff0c18 4241 * field equals zero if there is only one program flash block, otherwise it equals
mbed_official 146:f64d43ff0c18 4242 * the value of the MAXADDR0 field. For example, with MAXADDR0 = MAXADDR1 = 0x20
mbed_official 146:f64d43ff0c18 4243 * the first invalid address of flash block 1 is 0x4_0000 + 0x4_0000. This would be
mbed_official 146:f64d43ff0c18 4244 * the MAXADDR1 value for a device with 512 KB program flash memory across two
mbed_official 146:f64d43ff0c18 4245 * flash blocks and no FlexNVM.
mbed_official 146:f64d43ff0c18 4246 */
mbed_official 146:f64d43ff0c18 4247 //@{
mbed_official 146:f64d43ff0c18 4248 #define BP_SIM_FCFG2_MAXADDR1 (16U) //!< Bit position for SIM_FCFG2_MAXADDR1.
mbed_official 146:f64d43ff0c18 4249 #define BM_SIM_FCFG2_MAXADDR1 (0x007F0000U) //!< Bit mask for SIM_FCFG2_MAXADDR1.
mbed_official 146:f64d43ff0c18 4250 #define BS_SIM_FCFG2_MAXADDR1 (7U) //!< Bit field size in bits for SIM_FCFG2_MAXADDR1.
mbed_official 146:f64d43ff0c18 4251
mbed_official 146:f64d43ff0c18 4252 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4253 //! @brief Read current value of the SIM_FCFG2_MAXADDR1 field.
mbed_official 146:f64d43ff0c18 4254 #define BR_SIM_FCFG2_MAXADDR1 (HW_SIM_FCFG2.B.MAXADDR1)
mbed_official 146:f64d43ff0c18 4255 #endif
mbed_official 146:f64d43ff0c18 4256 //@}
mbed_official 146:f64d43ff0c18 4257
mbed_official 146:f64d43ff0c18 4258 /*!
mbed_official 146:f64d43ff0c18 4259 * @name Register SIM_FCFG2, field PFLSH[23] (RO)
mbed_official 146:f64d43ff0c18 4260 *
mbed_official 146:f64d43ff0c18 4261 * For devices with FlexNVM, this bit is always clear. For devices without
mbed_official 146:f64d43ff0c18 4262 * FlexNVM, this bit is always set.
mbed_official 146:f64d43ff0c18 4263 *
mbed_official 146:f64d43ff0c18 4264 * Values:
mbed_official 146:f64d43ff0c18 4265 * - 0 - Device supports FlexNVM
mbed_official 146:f64d43ff0c18 4266 * - 1 - Program Flash only, device does not support FlexNVM
mbed_official 146:f64d43ff0c18 4267 */
mbed_official 146:f64d43ff0c18 4268 //@{
mbed_official 146:f64d43ff0c18 4269 #define BP_SIM_FCFG2_PFLSH (23U) //!< Bit position for SIM_FCFG2_PFLSH.
mbed_official 146:f64d43ff0c18 4270 #define BM_SIM_FCFG2_PFLSH (0x00800000U) //!< Bit mask for SIM_FCFG2_PFLSH.
mbed_official 146:f64d43ff0c18 4271 #define BS_SIM_FCFG2_PFLSH (1U) //!< Bit field size in bits for SIM_FCFG2_PFLSH.
mbed_official 146:f64d43ff0c18 4272
mbed_official 146:f64d43ff0c18 4273 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4274 //! @brief Read current value of the SIM_FCFG2_PFLSH field.
mbed_official 146:f64d43ff0c18 4275 #define BR_SIM_FCFG2_PFLSH (BITBAND_ACCESS32(HW_SIM_FCFG2_ADDR, BP_SIM_FCFG2_PFLSH))
mbed_official 146:f64d43ff0c18 4276 #endif
mbed_official 146:f64d43ff0c18 4277 //@}
mbed_official 146:f64d43ff0c18 4278
mbed_official 146:f64d43ff0c18 4279 /*!
mbed_official 146:f64d43ff0c18 4280 * @name Register SIM_FCFG2, field MAXADDR0[30:24] (RO)
mbed_official 146:f64d43ff0c18 4281 *
mbed_official 146:f64d43ff0c18 4282 * This field concatenated with 13 trailing zeros indicates the first invalid
mbed_official 146:f64d43ff0c18 4283 * address of each program flash block. For example, if MAXADDR0 = 0x20 the first
mbed_official 146:f64d43ff0c18 4284 * invalid address of flash block 0 is 0x0004_0000. This would be the MAXADDR0
mbed_official 146:f64d43ff0c18 4285 * value for a device with 256 KB program flash in flash block 0.
mbed_official 146:f64d43ff0c18 4286 */
mbed_official 146:f64d43ff0c18 4287 //@{
mbed_official 146:f64d43ff0c18 4288 #define BP_SIM_FCFG2_MAXADDR0 (24U) //!< Bit position for SIM_FCFG2_MAXADDR0.
mbed_official 146:f64d43ff0c18 4289 #define BM_SIM_FCFG2_MAXADDR0 (0x7F000000U) //!< Bit mask for SIM_FCFG2_MAXADDR0.
mbed_official 146:f64d43ff0c18 4290 #define BS_SIM_FCFG2_MAXADDR0 (7U) //!< Bit field size in bits for SIM_FCFG2_MAXADDR0.
mbed_official 146:f64d43ff0c18 4291
mbed_official 146:f64d43ff0c18 4292 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4293 //! @brief Read current value of the SIM_FCFG2_MAXADDR0 field.
mbed_official 146:f64d43ff0c18 4294 #define BR_SIM_FCFG2_MAXADDR0 (HW_SIM_FCFG2.B.MAXADDR0)
mbed_official 146:f64d43ff0c18 4295 #endif
mbed_official 146:f64d43ff0c18 4296 //@}
mbed_official 146:f64d43ff0c18 4297
mbed_official 146:f64d43ff0c18 4298 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4299 // HW_SIM_UIDH - Unique Identification Register High
mbed_official 146:f64d43ff0c18 4300 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4301
mbed_official 146:f64d43ff0c18 4302 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4303 /*!
mbed_official 146:f64d43ff0c18 4304 * @brief HW_SIM_UIDH - Unique Identification Register High (RO)
mbed_official 146:f64d43ff0c18 4305 *
mbed_official 146:f64d43ff0c18 4306 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 4307 */
mbed_official 146:f64d43ff0c18 4308 typedef union _hw_sim_uidh
mbed_official 146:f64d43ff0c18 4309 {
mbed_official 146:f64d43ff0c18 4310 uint32_t U;
mbed_official 146:f64d43ff0c18 4311 struct _hw_sim_uidh_bitfields
mbed_official 146:f64d43ff0c18 4312 {
mbed_official 146:f64d43ff0c18 4313 uint32_t UID : 32; //!< [31:0] Unique Identification
mbed_official 146:f64d43ff0c18 4314 } B;
mbed_official 146:f64d43ff0c18 4315 } hw_sim_uidh_t;
mbed_official 146:f64d43ff0c18 4316 #endif
mbed_official 146:f64d43ff0c18 4317
mbed_official 146:f64d43ff0c18 4318 /*!
mbed_official 146:f64d43ff0c18 4319 * @name Constants and macros for entire SIM_UIDH register
mbed_official 146:f64d43ff0c18 4320 */
mbed_official 146:f64d43ff0c18 4321 //@{
mbed_official 146:f64d43ff0c18 4322 #define HW_SIM_UIDH_ADDR (REGS_SIM_BASE + 0x1054U)
mbed_official 146:f64d43ff0c18 4323
mbed_official 146:f64d43ff0c18 4324 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4325 #define HW_SIM_UIDH (*(__I hw_sim_uidh_t *) HW_SIM_UIDH_ADDR)
mbed_official 146:f64d43ff0c18 4326 #define HW_SIM_UIDH_RD() (HW_SIM_UIDH.U)
mbed_official 146:f64d43ff0c18 4327 #endif
mbed_official 146:f64d43ff0c18 4328 //@}
mbed_official 146:f64d43ff0c18 4329
mbed_official 146:f64d43ff0c18 4330 /*
mbed_official 146:f64d43ff0c18 4331 * Constants & macros for individual SIM_UIDH bitfields
mbed_official 146:f64d43ff0c18 4332 */
mbed_official 146:f64d43ff0c18 4333
mbed_official 146:f64d43ff0c18 4334 /*!
mbed_official 146:f64d43ff0c18 4335 * @name Register SIM_UIDH, field UID[31:0] (RO)
mbed_official 146:f64d43ff0c18 4336 *
mbed_official 146:f64d43ff0c18 4337 * Unique identification for the device.
mbed_official 146:f64d43ff0c18 4338 */
mbed_official 146:f64d43ff0c18 4339 //@{
mbed_official 146:f64d43ff0c18 4340 #define BP_SIM_UIDH_UID (0U) //!< Bit position for SIM_UIDH_UID.
mbed_official 146:f64d43ff0c18 4341 #define BM_SIM_UIDH_UID (0xFFFFFFFFU) //!< Bit mask for SIM_UIDH_UID.
mbed_official 146:f64d43ff0c18 4342 #define BS_SIM_UIDH_UID (32U) //!< Bit field size in bits for SIM_UIDH_UID.
mbed_official 146:f64d43ff0c18 4343
mbed_official 146:f64d43ff0c18 4344 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4345 //! @brief Read current value of the SIM_UIDH_UID field.
mbed_official 146:f64d43ff0c18 4346 #define BR_SIM_UIDH_UID (HW_SIM_UIDH.U)
mbed_official 146:f64d43ff0c18 4347 #endif
mbed_official 146:f64d43ff0c18 4348 //@}
mbed_official 146:f64d43ff0c18 4349
mbed_official 146:f64d43ff0c18 4350 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4351 // HW_SIM_UIDMH - Unique Identification Register Mid-High
mbed_official 146:f64d43ff0c18 4352 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4353
mbed_official 146:f64d43ff0c18 4354 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4355 /*!
mbed_official 146:f64d43ff0c18 4356 * @brief HW_SIM_UIDMH - Unique Identification Register Mid-High (RO)
mbed_official 146:f64d43ff0c18 4357 *
mbed_official 146:f64d43ff0c18 4358 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 4359 */
mbed_official 146:f64d43ff0c18 4360 typedef union _hw_sim_uidmh
mbed_official 146:f64d43ff0c18 4361 {
mbed_official 146:f64d43ff0c18 4362 uint32_t U;
mbed_official 146:f64d43ff0c18 4363 struct _hw_sim_uidmh_bitfields
mbed_official 146:f64d43ff0c18 4364 {
mbed_official 146:f64d43ff0c18 4365 uint32_t UID : 32; //!< [31:0] Unique Identification
mbed_official 146:f64d43ff0c18 4366 } B;
mbed_official 146:f64d43ff0c18 4367 } hw_sim_uidmh_t;
mbed_official 146:f64d43ff0c18 4368 #endif
mbed_official 146:f64d43ff0c18 4369
mbed_official 146:f64d43ff0c18 4370 /*!
mbed_official 146:f64d43ff0c18 4371 * @name Constants and macros for entire SIM_UIDMH register
mbed_official 146:f64d43ff0c18 4372 */
mbed_official 146:f64d43ff0c18 4373 //@{
mbed_official 146:f64d43ff0c18 4374 #define HW_SIM_UIDMH_ADDR (REGS_SIM_BASE + 0x1058U)
mbed_official 146:f64d43ff0c18 4375
mbed_official 146:f64d43ff0c18 4376 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4377 #define HW_SIM_UIDMH (*(__I hw_sim_uidmh_t *) HW_SIM_UIDMH_ADDR)
mbed_official 146:f64d43ff0c18 4378 #define HW_SIM_UIDMH_RD() (HW_SIM_UIDMH.U)
mbed_official 146:f64d43ff0c18 4379 #endif
mbed_official 146:f64d43ff0c18 4380 //@}
mbed_official 146:f64d43ff0c18 4381
mbed_official 146:f64d43ff0c18 4382 /*
mbed_official 146:f64d43ff0c18 4383 * Constants & macros for individual SIM_UIDMH bitfields
mbed_official 146:f64d43ff0c18 4384 */
mbed_official 146:f64d43ff0c18 4385
mbed_official 146:f64d43ff0c18 4386 /*!
mbed_official 146:f64d43ff0c18 4387 * @name Register SIM_UIDMH, field UID[31:0] (RO)
mbed_official 146:f64d43ff0c18 4388 *
mbed_official 146:f64d43ff0c18 4389 * Unique identification for the device.
mbed_official 146:f64d43ff0c18 4390 */
mbed_official 146:f64d43ff0c18 4391 //@{
mbed_official 146:f64d43ff0c18 4392 #define BP_SIM_UIDMH_UID (0U) //!< Bit position for SIM_UIDMH_UID.
mbed_official 146:f64d43ff0c18 4393 #define BM_SIM_UIDMH_UID (0xFFFFFFFFU) //!< Bit mask for SIM_UIDMH_UID.
mbed_official 146:f64d43ff0c18 4394 #define BS_SIM_UIDMH_UID (32U) //!< Bit field size in bits for SIM_UIDMH_UID.
mbed_official 146:f64d43ff0c18 4395
mbed_official 146:f64d43ff0c18 4396 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4397 //! @brief Read current value of the SIM_UIDMH_UID field.
mbed_official 146:f64d43ff0c18 4398 #define BR_SIM_UIDMH_UID (HW_SIM_UIDMH.U)
mbed_official 146:f64d43ff0c18 4399 #endif
mbed_official 146:f64d43ff0c18 4400 //@}
mbed_official 146:f64d43ff0c18 4401
mbed_official 146:f64d43ff0c18 4402 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4403 // HW_SIM_UIDML - Unique Identification Register Mid Low
mbed_official 146:f64d43ff0c18 4404 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4405
mbed_official 146:f64d43ff0c18 4406 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4407 /*!
mbed_official 146:f64d43ff0c18 4408 * @brief HW_SIM_UIDML - Unique Identification Register Mid Low (RO)
mbed_official 146:f64d43ff0c18 4409 *
mbed_official 146:f64d43ff0c18 4410 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 4411 */
mbed_official 146:f64d43ff0c18 4412 typedef union _hw_sim_uidml
mbed_official 146:f64d43ff0c18 4413 {
mbed_official 146:f64d43ff0c18 4414 uint32_t U;
mbed_official 146:f64d43ff0c18 4415 struct _hw_sim_uidml_bitfields
mbed_official 146:f64d43ff0c18 4416 {
mbed_official 146:f64d43ff0c18 4417 uint32_t UID : 32; //!< [31:0] Unique Identification
mbed_official 146:f64d43ff0c18 4418 } B;
mbed_official 146:f64d43ff0c18 4419 } hw_sim_uidml_t;
mbed_official 146:f64d43ff0c18 4420 #endif
mbed_official 146:f64d43ff0c18 4421
mbed_official 146:f64d43ff0c18 4422 /*!
mbed_official 146:f64d43ff0c18 4423 * @name Constants and macros for entire SIM_UIDML register
mbed_official 146:f64d43ff0c18 4424 */
mbed_official 146:f64d43ff0c18 4425 //@{
mbed_official 146:f64d43ff0c18 4426 #define HW_SIM_UIDML_ADDR (REGS_SIM_BASE + 0x105CU)
mbed_official 146:f64d43ff0c18 4427
mbed_official 146:f64d43ff0c18 4428 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4429 #define HW_SIM_UIDML (*(__I hw_sim_uidml_t *) HW_SIM_UIDML_ADDR)
mbed_official 146:f64d43ff0c18 4430 #define HW_SIM_UIDML_RD() (HW_SIM_UIDML.U)
mbed_official 146:f64d43ff0c18 4431 #endif
mbed_official 146:f64d43ff0c18 4432 //@}
mbed_official 146:f64d43ff0c18 4433
mbed_official 146:f64d43ff0c18 4434 /*
mbed_official 146:f64d43ff0c18 4435 * Constants & macros for individual SIM_UIDML bitfields
mbed_official 146:f64d43ff0c18 4436 */
mbed_official 146:f64d43ff0c18 4437
mbed_official 146:f64d43ff0c18 4438 /*!
mbed_official 146:f64d43ff0c18 4439 * @name Register SIM_UIDML, field UID[31:0] (RO)
mbed_official 146:f64d43ff0c18 4440 *
mbed_official 146:f64d43ff0c18 4441 * Unique identification for the device.
mbed_official 146:f64d43ff0c18 4442 */
mbed_official 146:f64d43ff0c18 4443 //@{
mbed_official 146:f64d43ff0c18 4444 #define BP_SIM_UIDML_UID (0U) //!< Bit position for SIM_UIDML_UID.
mbed_official 146:f64d43ff0c18 4445 #define BM_SIM_UIDML_UID (0xFFFFFFFFU) //!< Bit mask for SIM_UIDML_UID.
mbed_official 146:f64d43ff0c18 4446 #define BS_SIM_UIDML_UID (32U) //!< Bit field size in bits for SIM_UIDML_UID.
mbed_official 146:f64d43ff0c18 4447
mbed_official 146:f64d43ff0c18 4448 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4449 //! @brief Read current value of the SIM_UIDML_UID field.
mbed_official 146:f64d43ff0c18 4450 #define BR_SIM_UIDML_UID (HW_SIM_UIDML.U)
mbed_official 146:f64d43ff0c18 4451 #endif
mbed_official 146:f64d43ff0c18 4452 //@}
mbed_official 146:f64d43ff0c18 4453
mbed_official 146:f64d43ff0c18 4454 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4455 // HW_SIM_UIDL - Unique Identification Register Low
mbed_official 146:f64d43ff0c18 4456 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4457
mbed_official 146:f64d43ff0c18 4458 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4459 /*!
mbed_official 146:f64d43ff0c18 4460 * @brief HW_SIM_UIDL - Unique Identification Register Low (RO)
mbed_official 146:f64d43ff0c18 4461 *
mbed_official 146:f64d43ff0c18 4462 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 4463 */
mbed_official 146:f64d43ff0c18 4464 typedef union _hw_sim_uidl
mbed_official 146:f64d43ff0c18 4465 {
mbed_official 146:f64d43ff0c18 4466 uint32_t U;
mbed_official 146:f64d43ff0c18 4467 struct _hw_sim_uidl_bitfields
mbed_official 146:f64d43ff0c18 4468 {
mbed_official 146:f64d43ff0c18 4469 uint32_t UID : 32; //!< [31:0] Unique Identification
mbed_official 146:f64d43ff0c18 4470 } B;
mbed_official 146:f64d43ff0c18 4471 } hw_sim_uidl_t;
mbed_official 146:f64d43ff0c18 4472 #endif
mbed_official 146:f64d43ff0c18 4473
mbed_official 146:f64d43ff0c18 4474 /*!
mbed_official 146:f64d43ff0c18 4475 * @name Constants and macros for entire SIM_UIDL register
mbed_official 146:f64d43ff0c18 4476 */
mbed_official 146:f64d43ff0c18 4477 //@{
mbed_official 146:f64d43ff0c18 4478 #define HW_SIM_UIDL_ADDR (REGS_SIM_BASE + 0x1060U)
mbed_official 146:f64d43ff0c18 4479
mbed_official 146:f64d43ff0c18 4480 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4481 #define HW_SIM_UIDL (*(__I hw_sim_uidl_t *) HW_SIM_UIDL_ADDR)
mbed_official 146:f64d43ff0c18 4482 #define HW_SIM_UIDL_RD() (HW_SIM_UIDL.U)
mbed_official 146:f64d43ff0c18 4483 #endif
mbed_official 146:f64d43ff0c18 4484 //@}
mbed_official 146:f64d43ff0c18 4485
mbed_official 146:f64d43ff0c18 4486 /*
mbed_official 146:f64d43ff0c18 4487 * Constants & macros for individual SIM_UIDL bitfields
mbed_official 146:f64d43ff0c18 4488 */
mbed_official 146:f64d43ff0c18 4489
mbed_official 146:f64d43ff0c18 4490 /*!
mbed_official 146:f64d43ff0c18 4491 * @name Register SIM_UIDL, field UID[31:0] (RO)
mbed_official 146:f64d43ff0c18 4492 *
mbed_official 146:f64d43ff0c18 4493 * Unique identification for the device.
mbed_official 146:f64d43ff0c18 4494 */
mbed_official 146:f64d43ff0c18 4495 //@{
mbed_official 146:f64d43ff0c18 4496 #define BP_SIM_UIDL_UID (0U) //!< Bit position for SIM_UIDL_UID.
mbed_official 146:f64d43ff0c18 4497 #define BM_SIM_UIDL_UID (0xFFFFFFFFU) //!< Bit mask for SIM_UIDL_UID.
mbed_official 146:f64d43ff0c18 4498 #define BS_SIM_UIDL_UID (32U) //!< Bit field size in bits for SIM_UIDL_UID.
mbed_official 146:f64d43ff0c18 4499
mbed_official 146:f64d43ff0c18 4500 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4501 //! @brief Read current value of the SIM_UIDL_UID field.
mbed_official 146:f64d43ff0c18 4502 #define BR_SIM_UIDL_UID (HW_SIM_UIDL.U)
mbed_official 146:f64d43ff0c18 4503 #endif
mbed_official 146:f64d43ff0c18 4504 //@}
mbed_official 146:f64d43ff0c18 4505
mbed_official 146:f64d43ff0c18 4506 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4507 // hw_sim_t - module struct
mbed_official 146:f64d43ff0c18 4508 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4509 /*!
mbed_official 146:f64d43ff0c18 4510 * @brief All SIM module registers.
mbed_official 146:f64d43ff0c18 4511 */
mbed_official 146:f64d43ff0c18 4512 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4513 #pragma pack(1)
mbed_official 146:f64d43ff0c18 4514 typedef struct _hw_sim
mbed_official 146:f64d43ff0c18 4515 {
mbed_official 146:f64d43ff0c18 4516 __IO hw_sim_sopt1_t SOPT1; //!< [0x0] System Options Register 1
mbed_official 146:f64d43ff0c18 4517 __IO hw_sim_sopt1cfg_t SOPT1CFG; //!< [0x4] SOPT1 Configuration Register
mbed_official 146:f64d43ff0c18 4518 uint8_t _reserved0[4092];
mbed_official 146:f64d43ff0c18 4519 __IO hw_sim_sopt2_t SOPT2; //!< [0x1004] System Options Register 2
mbed_official 146:f64d43ff0c18 4520 uint8_t _reserved1[4];
mbed_official 146:f64d43ff0c18 4521 __IO hw_sim_sopt4_t SOPT4; //!< [0x100C] System Options Register 4
mbed_official 146:f64d43ff0c18 4522 __IO hw_sim_sopt5_t SOPT5; //!< [0x1010] System Options Register 5
mbed_official 146:f64d43ff0c18 4523 uint8_t _reserved2[4];
mbed_official 146:f64d43ff0c18 4524 __IO hw_sim_sopt7_t SOPT7; //!< [0x1018] System Options Register 7
mbed_official 146:f64d43ff0c18 4525 uint8_t _reserved3[8];
mbed_official 146:f64d43ff0c18 4526 __I hw_sim_sdid_t SDID; //!< [0x1024] System Device Identification Register
mbed_official 146:f64d43ff0c18 4527 __IO hw_sim_scgc1_t SCGC1; //!< [0x1028] System Clock Gating Control Register 1
mbed_official 146:f64d43ff0c18 4528 __IO hw_sim_scgc2_t SCGC2; //!< [0x102C] System Clock Gating Control Register 2
mbed_official 146:f64d43ff0c18 4529 __IO hw_sim_scgc3_t SCGC3; //!< [0x1030] System Clock Gating Control Register 3
mbed_official 146:f64d43ff0c18 4530 __IO hw_sim_scgc4_t SCGC4; //!< [0x1034] System Clock Gating Control Register 4
mbed_official 146:f64d43ff0c18 4531 __IO hw_sim_scgc5_t SCGC5; //!< [0x1038] System Clock Gating Control Register 5
mbed_official 146:f64d43ff0c18 4532 __IO hw_sim_scgc6_t SCGC6; //!< [0x103C] System Clock Gating Control Register 6
mbed_official 146:f64d43ff0c18 4533 __IO hw_sim_scgc7_t SCGC7; //!< [0x1040] System Clock Gating Control Register 7
mbed_official 146:f64d43ff0c18 4534 __IO hw_sim_clkdiv1_t CLKDIV1; //!< [0x1044] System Clock Divider Register 1
mbed_official 146:f64d43ff0c18 4535 __IO hw_sim_clkdiv2_t CLKDIV2; //!< [0x1048] System Clock Divider Register 2
mbed_official 146:f64d43ff0c18 4536 __IO hw_sim_fcfg1_t FCFG1; //!< [0x104C] Flash Configuration Register 1
mbed_official 146:f64d43ff0c18 4537 __I hw_sim_fcfg2_t FCFG2; //!< [0x1050] Flash Configuration Register 2
mbed_official 146:f64d43ff0c18 4538 __I hw_sim_uidh_t UIDH; //!< [0x1054] Unique Identification Register High
mbed_official 146:f64d43ff0c18 4539 __I hw_sim_uidmh_t UIDMH; //!< [0x1058] Unique Identification Register Mid-High
mbed_official 146:f64d43ff0c18 4540 __I hw_sim_uidml_t UIDML; //!< [0x105C] Unique Identification Register Mid Low
mbed_official 146:f64d43ff0c18 4541 __I hw_sim_uidl_t UIDL; //!< [0x1060] Unique Identification Register Low
mbed_official 146:f64d43ff0c18 4542 } hw_sim_t;
mbed_official 146:f64d43ff0c18 4543 #pragma pack()
mbed_official 146:f64d43ff0c18 4544
mbed_official 146:f64d43ff0c18 4545 //! @brief Macro to access all SIM registers.
mbed_official 146:f64d43ff0c18 4546 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 146:f64d43ff0c18 4547 //! use the '&' operator, like <code>&HW_SIM</code>.
mbed_official 146:f64d43ff0c18 4548 #define HW_SIM (*(hw_sim_t *) REGS_SIM_BASE)
mbed_official 146:f64d43ff0c18 4549 #endif
mbed_official 146:f64d43ff0c18 4550
mbed_official 146:f64d43ff0c18 4551 #endif // __HW_SIM_REGISTERS_H__
mbed_official 146:f64d43ff0c18 4552 // v22/130726/0.9
mbed_official 146:f64d43ff0c18 4553 // EOF