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Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_port.h@149:1fb5f62b92bd, 2014-04-03 (annotated)

Committer:
mbed_official
Date:
Thu Apr 03 11:45:06 2014 +0100
Revision:
149:1fb5f62b92bd
Parent:
targets/hal/TARGET_Freescale/TARGET_KSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_port.h@146:f64d43ff0c18 
Synchronized with git revision 220c0bb39ceee40016e1e86350c058963d01ed42



Full URL: https://github.com/mbedmicro/mbed/commit/220c0bb39ceee40016e1e86350c058963d01ed42/

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /*
mbed_official 146:f64d43ff0c18 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
mbed_official 146:f64d43ff0c18 3 * All rights reserved.
mbed_official 146:f64d43ff0c18 4 *
mbed_official 146:f64d43ff0c18 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official 146:f64d43ff0c18 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official 146:f64d43ff0c18 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
mbed_official 146:f64d43ff0c18 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
mbed_official 146:f64d43ff0c18 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
mbed_official 146:f64d43ff0c18 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 146:f64d43ff0c18 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 146:f64d43ff0c18 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
mbed_official 146:f64d43ff0c18 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
mbed_official 146:f64d43ff0c18 14 * OF SUCH DAMAGE.
mbed_official 146:f64d43ff0c18 15 */
mbed_official 146:f64d43ff0c18 16 /*
mbed_official 146:f64d43ff0c18 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 146:f64d43ff0c18 18 *
mbed_official 146:f64d43ff0c18 19 * This file was generated automatically and any changes may be lost.
mbed_official 146:f64d43ff0c18 20 */
mbed_official 146:f64d43ff0c18 21 #ifndef __HW_PORT_REGISTERS_H__
mbed_official 146:f64d43ff0c18 22 #define __HW_PORT_REGISTERS_H__
mbed_official 146:f64d43ff0c18 23
mbed_official 146:f64d43ff0c18 24 #include "regs.h"
mbed_official 146:f64d43ff0c18 25
mbed_official 146:f64d43ff0c18 26 /*
mbed_official 146:f64d43ff0c18 27 * MK64F12 PORT
mbed_official 146:f64d43ff0c18 28 *
mbed_official 146:f64d43ff0c18 29 * Pin Control and Interrupts
mbed_official 146:f64d43ff0c18 30 *
mbed_official 146:f64d43ff0c18 31 * Registers defined in this header file:
mbed_official 146:f64d43ff0c18 32 * - HW_PORT_PCRn - Pin Control Register n
mbed_official 146:f64d43ff0c18 33 * - HW_PORT_GPCLR - Global Pin Control Low Register
mbed_official 146:f64d43ff0c18 34 * - HW_PORT_GPCHR - Global Pin Control High Register
mbed_official 146:f64d43ff0c18 35 * - HW_PORT_ISFR - Interrupt Status Flag Register
mbed_official 146:f64d43ff0c18 36 * - HW_PORT_DFER - Digital Filter Enable Register
mbed_official 146:f64d43ff0c18 37 * - HW_PORT_DFCR - Digital Filter Clock Register
mbed_official 146:f64d43ff0c18 38 * - HW_PORT_DFWR - Digital Filter Width Register
mbed_official 146:f64d43ff0c18 39 *
mbed_official 146:f64d43ff0c18 40 * - hw_port_t - Struct containing all module registers.
mbed_official 146:f64d43ff0c18 41 */
mbed_official 146:f64d43ff0c18 42
mbed_official 146:f64d43ff0c18 43 //! @name Module base addresses
mbed_official 146:f64d43ff0c18 44 //@{
mbed_official 146:f64d43ff0c18 45 #ifndef REGS_PORT_BASE
mbed_official 146:f64d43ff0c18 46 #define HW_PORT_INSTANCE_COUNT (5U) //!< Number of instances of the PORT module.
mbed_official 146:f64d43ff0c18 47 #define HW_PORTA (0U) //!< Instance number for PORTA.
mbed_official 146:f64d43ff0c18 48 #define HW_PORTB (1U) //!< Instance number for PORTB.
mbed_official 146:f64d43ff0c18 49 #define HW_PORTC (2U) //!< Instance number for PORTC.
mbed_official 146:f64d43ff0c18 50 #define HW_PORTD (3U) //!< Instance number for PORTD.
mbed_official 146:f64d43ff0c18 51 #define HW_PORTE (4U) //!< Instance number for PORTE.
mbed_official 146:f64d43ff0c18 52 #define REGS_PORTA_BASE (0x40049000U) //!< Base address for PORTA.
mbed_official 146:f64d43ff0c18 53 #define REGS_PORTB_BASE (0x4004A000U) //!< Base address for PORTB.
mbed_official 146:f64d43ff0c18 54 #define REGS_PORTC_BASE (0x4004B000U) //!< Base address for PORTC.
mbed_official 146:f64d43ff0c18 55 #define REGS_PORTD_BASE (0x4004C000U) //!< Base address for PORTD.
mbed_official 146:f64d43ff0c18 56 #define REGS_PORTE_BASE (0x4004D000U) //!< Base address for PORTE.
mbed_official 146:f64d43ff0c18 57
mbed_official 146:f64d43ff0c18 58 //! @brief Table of base addresses for PORT instances.
mbed_official 146:f64d43ff0c18 59 static const uint32_t __g_regs_PORT_base_addresses[] = {
mbed_official 146:f64d43ff0c18 60 REGS_PORTA_BASE,
mbed_official 146:f64d43ff0c18 61 REGS_PORTB_BASE,
mbed_official 146:f64d43ff0c18 62 REGS_PORTC_BASE,
mbed_official 146:f64d43ff0c18 63 REGS_PORTD_BASE,
mbed_official 146:f64d43ff0c18 64 REGS_PORTE_BASE,
mbed_official 146:f64d43ff0c18 65 };
mbed_official 146:f64d43ff0c18 66
mbed_official 146:f64d43ff0c18 67 //! @brief Get the base address of PORT by instance number.
mbed_official 146:f64d43ff0c18 68 //! @param x PORT instance number, from 0 through 4.
mbed_official 146:f64d43ff0c18 69 #define REGS_PORT_BASE(x) (__g_regs_PORT_base_addresses[(x)])
mbed_official 146:f64d43ff0c18 70
mbed_official 146:f64d43ff0c18 71 //! @brief Get the instance number given a base address.
mbed_official 146:f64d43ff0c18 72 //! @param b Base address for an instance of PORT.
mbed_official 146:f64d43ff0c18 73 #define REGS_PORT_INSTANCE(b) ((b) == REGS_PORTA_BASE ? HW_PORTA : (b) == REGS_PORTB_BASE ? HW_PORTB : (b) == REGS_PORTC_BASE ? HW_PORTC : (b) == REGS_PORTD_BASE ? HW_PORTD : (b) == REGS_PORTE_BASE ? HW_PORTE : 0)
mbed_official 146:f64d43ff0c18 74 #endif
mbed_official 146:f64d43ff0c18 75 //@}
mbed_official 146:f64d43ff0c18 76
mbed_official 146:f64d43ff0c18 77 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 78 // HW_PORT_PCRn - Pin Control Register n
mbed_official 146:f64d43ff0c18 79 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 80
mbed_official 146:f64d43ff0c18 81 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 82 /*!
mbed_official 146:f64d43ff0c18 83 * @brief HW_PORT_PCRn - Pin Control Register n (RW)
mbed_official 146:f64d43ff0c18 84 *
mbed_official 146:f64d43ff0c18 85 * Reset value: 0x00000742U
mbed_official 146:f64d43ff0c18 86 *
mbed_official 146:f64d43ff0c18 87 * See the Signal Multiplexing and Pin Assignment chapter for the reset value of
mbed_official 146:f64d43ff0c18 88 * this device. See the GPIO Configuration section for details on the available
mbed_official 146:f64d43ff0c18 89 * functions for each pin. Do not modify pin configuration registers associated
mbed_official 146:f64d43ff0c18 90 * with pins not available in your selected package. All unbonded pins not
mbed_official 146:f64d43ff0c18 91 * available in your package will default to DISABLE state for lowest power consumption.
mbed_official 146:f64d43ff0c18 92 */
mbed_official 146:f64d43ff0c18 93 typedef union _hw_port_pcrn
mbed_official 146:f64d43ff0c18 94 {
mbed_official 146:f64d43ff0c18 95 uint32_t U;
mbed_official 146:f64d43ff0c18 96 struct _hw_port_pcrn_bitfields
mbed_official 146:f64d43ff0c18 97 {
mbed_official 146:f64d43ff0c18 98 uint32_t PS : 1; //!< [0] Pull Select
mbed_official 146:f64d43ff0c18 99 uint32_t PE : 1; //!< [1] Pull Enable
mbed_official 146:f64d43ff0c18 100 uint32_t SRE : 1; //!< [2] Slew Rate Enable
mbed_official 146:f64d43ff0c18 101 uint32_t RESERVED0 : 1; //!< [3]
mbed_official 146:f64d43ff0c18 102 uint32_t PFE : 1; //!< [4] Passive Filter Enable
mbed_official 146:f64d43ff0c18 103 uint32_t ODE : 1; //!< [5] Open Drain Enable
mbed_official 146:f64d43ff0c18 104 uint32_t DSE : 1; //!< [6] Drive Strength Enable
mbed_official 146:f64d43ff0c18 105 uint32_t RESERVED1 : 1; //!< [7]
mbed_official 146:f64d43ff0c18 106 uint32_t MUX : 3; //!< [10:8] Pin Mux Control
mbed_official 146:f64d43ff0c18 107 uint32_t RESERVED2 : 4; //!< [14:11]
mbed_official 146:f64d43ff0c18 108 uint32_t LK : 1; //!< [15] Lock Register
mbed_official 146:f64d43ff0c18 109 uint32_t IRQC : 4; //!< [19:16] Interrupt Configuration
mbed_official 146:f64d43ff0c18 110 uint32_t RESERVED3 : 4; //!< [23:20]
mbed_official 146:f64d43ff0c18 111 uint32_t ISF : 1; //!< [24] Interrupt Status Flag
mbed_official 146:f64d43ff0c18 112 uint32_t RESERVED4 : 7; //!< [31:25]
mbed_official 146:f64d43ff0c18 113 } B;
mbed_official 146:f64d43ff0c18 114 } hw_port_pcrn_t;
mbed_official 146:f64d43ff0c18 115 #endif
mbed_official 146:f64d43ff0c18 116
mbed_official 146:f64d43ff0c18 117 /*!
mbed_official 146:f64d43ff0c18 118 * @name Constants and macros for entire PORT_PCRn register
mbed_official 146:f64d43ff0c18 119 */
mbed_official 146:f64d43ff0c18 120 //@{
mbed_official 146:f64d43ff0c18 121 #define HW_PORT_PCRn_COUNT (32U)
mbed_official 146:f64d43ff0c18 122
mbed_official 146:f64d43ff0c18 123 #define HW_PORT_PCRn_ADDR(x, n) (REGS_PORT_BASE(x) + 0x0U + (0x4U * n))
mbed_official 146:f64d43ff0c18 124
mbed_official 146:f64d43ff0c18 125 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 126 #define HW_PORT_PCRn(x, n) (*(__IO hw_port_pcrn_t *) HW_PORT_PCRn_ADDR(x, n))
mbed_official 146:f64d43ff0c18 127 #define HW_PORT_PCRn_RD(x, n) (HW_PORT_PCRn(x, n).U)
mbed_official 146:f64d43ff0c18 128 #define HW_PORT_PCRn_WR(x, n, v) (HW_PORT_PCRn(x, n).U = (v))
mbed_official 146:f64d43ff0c18 129 #define HW_PORT_PCRn_SET(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) | (v)))
mbed_official 146:f64d43ff0c18 130 #define HW_PORT_PCRn_CLR(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) & ~(v)))
mbed_official 146:f64d43ff0c18 131 #define HW_PORT_PCRn_TOG(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) ^ (v)))
mbed_official 146:f64d43ff0c18 132 #endif
mbed_official 146:f64d43ff0c18 133 //@}
mbed_official 146:f64d43ff0c18 134
mbed_official 146:f64d43ff0c18 135 /*
mbed_official 146:f64d43ff0c18 136 * Constants & macros for individual PORT_PCRn bitfields
mbed_official 146:f64d43ff0c18 137 */
mbed_official 146:f64d43ff0c18 138
mbed_official 146:f64d43ff0c18 139 /*!
mbed_official 146:f64d43ff0c18 140 * @name Register PORT_PCRn, field PS[0] (RW)
mbed_official 146:f64d43ff0c18 141 *
mbed_official 146:f64d43ff0c18 142 * Pull configuration is valid in all digital pin muxing modes.
mbed_official 146:f64d43ff0c18 143 *
mbed_official 146:f64d43ff0c18 144 * Values:
mbed_official 146:f64d43ff0c18 145 * - 0 - Internal pulldown resistor is enabled on the corresponding pin, if the
mbed_official 146:f64d43ff0c18 146 * corresponding PE field is set.
mbed_official 146:f64d43ff0c18 147 * - 1 - Internal pullup resistor is enabled on the corresponding pin, if the
mbed_official 146:f64d43ff0c18 148 * corresponding PE field is set.
mbed_official 146:f64d43ff0c18 149 */
mbed_official 146:f64d43ff0c18 150 //@{
mbed_official 146:f64d43ff0c18 151 #define BP_PORT_PCRn_PS (0U) //!< Bit position for PORT_PCRn_PS.
mbed_official 146:f64d43ff0c18 152 #define BM_PORT_PCRn_PS (0x00000001U) //!< Bit mask for PORT_PCRn_PS.
mbed_official 146:f64d43ff0c18 153 #define BS_PORT_PCRn_PS (1U) //!< Bit field size in bits for PORT_PCRn_PS.
mbed_official 146:f64d43ff0c18 154
mbed_official 146:f64d43ff0c18 155 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 156 //! @brief Read current value of the PORT_PCRn_PS field.
mbed_official 146:f64d43ff0c18 157 #define BR_PORT_PCRn_PS(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PS))
mbed_official 146:f64d43ff0c18 158 #endif
mbed_official 146:f64d43ff0c18 159
mbed_official 146:f64d43ff0c18 160 //! @brief Format value for bitfield PORT_PCRn_PS.
mbed_official 146:f64d43ff0c18 161 #define BF_PORT_PCRn_PS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_PS), uint32_t) & BM_PORT_PCRn_PS)
mbed_official 146:f64d43ff0c18 162
mbed_official 146:f64d43ff0c18 163 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 164 //! @brief Set the PS field to a new value.
mbed_official 146:f64d43ff0c18 165 #define BW_PORT_PCRn_PS(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PS) = (v))
mbed_official 146:f64d43ff0c18 166 #endif
mbed_official 146:f64d43ff0c18 167 //@}
mbed_official 146:f64d43ff0c18 168
mbed_official 146:f64d43ff0c18 169 /*!
mbed_official 146:f64d43ff0c18 170 * @name Register PORT_PCRn, field PE[1] (RW)
mbed_official 146:f64d43ff0c18 171 *
mbed_official 146:f64d43ff0c18 172 * Pull configuration is valid in all digital pin muxing modes.
mbed_official 146:f64d43ff0c18 173 *
mbed_official 146:f64d43ff0c18 174 * Values:
mbed_official 146:f64d43ff0c18 175 * - 0 - Internal pullup or pulldown resistor is not enabled on the
mbed_official 146:f64d43ff0c18 176 * corresponding pin.
mbed_official 146:f64d43ff0c18 177 * - 1 - Internal pullup or pulldown resistor is enabled on the corresponding
mbed_official 146:f64d43ff0c18 178 * pin, if the pin is configured as a digital input.
mbed_official 146:f64d43ff0c18 179 */
mbed_official 146:f64d43ff0c18 180 //@{
mbed_official 146:f64d43ff0c18 181 #define BP_PORT_PCRn_PE (1U) //!< Bit position for PORT_PCRn_PE.
mbed_official 146:f64d43ff0c18 182 #define BM_PORT_PCRn_PE (0x00000002U) //!< Bit mask for PORT_PCRn_PE.
mbed_official 146:f64d43ff0c18 183 #define BS_PORT_PCRn_PE (1U) //!< Bit field size in bits for PORT_PCRn_PE.
mbed_official 146:f64d43ff0c18 184
mbed_official 146:f64d43ff0c18 185 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 186 //! @brief Read current value of the PORT_PCRn_PE field.
mbed_official 146:f64d43ff0c18 187 #define BR_PORT_PCRn_PE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PE))
mbed_official 146:f64d43ff0c18 188 #endif
mbed_official 146:f64d43ff0c18 189
mbed_official 146:f64d43ff0c18 190 //! @brief Format value for bitfield PORT_PCRn_PE.
mbed_official 146:f64d43ff0c18 191 #define BF_PORT_PCRn_PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_PE), uint32_t) & BM_PORT_PCRn_PE)
mbed_official 146:f64d43ff0c18 192
mbed_official 146:f64d43ff0c18 193 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 194 //! @brief Set the PE field to a new value.
mbed_official 146:f64d43ff0c18 195 #define BW_PORT_PCRn_PE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PE) = (v))
mbed_official 146:f64d43ff0c18 196 #endif
mbed_official 146:f64d43ff0c18 197 //@}
mbed_official 146:f64d43ff0c18 198
mbed_official 146:f64d43ff0c18 199 /*!
mbed_official 146:f64d43ff0c18 200 * @name Register PORT_PCRn, field SRE[2] (RW)
mbed_official 146:f64d43ff0c18 201 *
mbed_official 146:f64d43ff0c18 202 * Slew rate configuration is valid in all digital pin muxing modes.
mbed_official 146:f64d43ff0c18 203 *
mbed_official 146:f64d43ff0c18 204 * Values:
mbed_official 146:f64d43ff0c18 205 * - 0 - Fast slew rate is configured on the corresponding pin, if the pin is
mbed_official 146:f64d43ff0c18 206 * configured as a digital output.
mbed_official 146:f64d43ff0c18 207 * - 1 - Slow slew rate is configured on the corresponding pin, if the pin is
mbed_official 146:f64d43ff0c18 208 * configured as a digital output.
mbed_official 146:f64d43ff0c18 209 */
mbed_official 146:f64d43ff0c18 210 //@{
mbed_official 146:f64d43ff0c18 211 #define BP_PORT_PCRn_SRE (2U) //!< Bit position for PORT_PCRn_SRE.
mbed_official 146:f64d43ff0c18 212 #define BM_PORT_PCRn_SRE (0x00000004U) //!< Bit mask for PORT_PCRn_SRE.
mbed_official 146:f64d43ff0c18 213 #define BS_PORT_PCRn_SRE (1U) //!< Bit field size in bits for PORT_PCRn_SRE.
mbed_official 146:f64d43ff0c18 214
mbed_official 146:f64d43ff0c18 215 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 216 //! @brief Read current value of the PORT_PCRn_SRE field.
mbed_official 146:f64d43ff0c18 217 #define BR_PORT_PCRn_SRE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_SRE))
mbed_official 146:f64d43ff0c18 218 #endif
mbed_official 146:f64d43ff0c18 219
mbed_official 146:f64d43ff0c18 220 //! @brief Format value for bitfield PORT_PCRn_SRE.
mbed_official 146:f64d43ff0c18 221 #define BF_PORT_PCRn_SRE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_SRE), uint32_t) & BM_PORT_PCRn_SRE)
mbed_official 146:f64d43ff0c18 222
mbed_official 146:f64d43ff0c18 223 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 224 //! @brief Set the SRE field to a new value.
mbed_official 146:f64d43ff0c18 225 #define BW_PORT_PCRn_SRE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_SRE) = (v))
mbed_official 146:f64d43ff0c18 226 #endif
mbed_official 146:f64d43ff0c18 227 //@}
mbed_official 146:f64d43ff0c18 228
mbed_official 146:f64d43ff0c18 229 /*!
mbed_official 146:f64d43ff0c18 230 * @name Register PORT_PCRn, field PFE[4] (RW)
mbed_official 146:f64d43ff0c18 231 *
mbed_official 146:f64d43ff0c18 232 * Passive filter configuration is valid in all digital pin muxing modes.
mbed_official 146:f64d43ff0c18 233 *
mbed_official 146:f64d43ff0c18 234 * Values:
mbed_official 146:f64d43ff0c18 235 * - 0 - Passive input filter is disabled on the corresponding pin.
mbed_official 146:f64d43ff0c18 236 * - 1 - Passive input filter is enabled on the corresponding pin, if the pin is
mbed_official 146:f64d43ff0c18 237 * configured as a digital input. Refer to the device data sheet for filter
mbed_official 146:f64d43ff0c18 238 * characteristics.
mbed_official 146:f64d43ff0c18 239 */
mbed_official 146:f64d43ff0c18 240 //@{
mbed_official 146:f64d43ff0c18 241 #define BP_PORT_PCRn_PFE (4U) //!< Bit position for PORT_PCRn_PFE.
mbed_official 146:f64d43ff0c18 242 #define BM_PORT_PCRn_PFE (0x00000010U) //!< Bit mask for PORT_PCRn_PFE.
mbed_official 146:f64d43ff0c18 243 #define BS_PORT_PCRn_PFE (1U) //!< Bit field size in bits for PORT_PCRn_PFE.
mbed_official 146:f64d43ff0c18 244
mbed_official 146:f64d43ff0c18 245 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 246 //! @brief Read current value of the PORT_PCRn_PFE field.
mbed_official 146:f64d43ff0c18 247 #define BR_PORT_PCRn_PFE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PFE))
mbed_official 146:f64d43ff0c18 248 #endif
mbed_official 146:f64d43ff0c18 249
mbed_official 146:f64d43ff0c18 250 //! @brief Format value for bitfield PORT_PCRn_PFE.
mbed_official 146:f64d43ff0c18 251 #define BF_PORT_PCRn_PFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_PFE), uint32_t) & BM_PORT_PCRn_PFE)
mbed_official 146:f64d43ff0c18 252
mbed_official 146:f64d43ff0c18 253 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 254 //! @brief Set the PFE field to a new value.
mbed_official 146:f64d43ff0c18 255 #define BW_PORT_PCRn_PFE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PFE) = (v))
mbed_official 146:f64d43ff0c18 256 #endif
mbed_official 146:f64d43ff0c18 257 //@}
mbed_official 146:f64d43ff0c18 258
mbed_official 146:f64d43ff0c18 259 /*!
mbed_official 146:f64d43ff0c18 260 * @name Register PORT_PCRn, field ODE[5] (RW)
mbed_official 146:f64d43ff0c18 261 *
mbed_official 146:f64d43ff0c18 262 * Open drain configuration is valid in all digital pin muxing modes.
mbed_official 146:f64d43ff0c18 263 *
mbed_official 146:f64d43ff0c18 264 * Values:
mbed_official 146:f64d43ff0c18 265 * - 0 - Open drain output is disabled on the corresponding pin.
mbed_official 146:f64d43ff0c18 266 * - 1 - Open drain output is enabled on the corresponding pin, if the pin is
mbed_official 146:f64d43ff0c18 267 * configured as a digital output.
mbed_official 146:f64d43ff0c18 268 */
mbed_official 146:f64d43ff0c18 269 //@{
mbed_official 146:f64d43ff0c18 270 #define BP_PORT_PCRn_ODE (5U) //!< Bit position for PORT_PCRn_ODE.
mbed_official 146:f64d43ff0c18 271 #define BM_PORT_PCRn_ODE (0x00000020U) //!< Bit mask for PORT_PCRn_ODE.
mbed_official 146:f64d43ff0c18 272 #define BS_PORT_PCRn_ODE (1U) //!< Bit field size in bits for PORT_PCRn_ODE.
mbed_official 146:f64d43ff0c18 273
mbed_official 146:f64d43ff0c18 274 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 275 //! @brief Read current value of the PORT_PCRn_ODE field.
mbed_official 146:f64d43ff0c18 276 #define BR_PORT_PCRn_ODE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ODE))
mbed_official 146:f64d43ff0c18 277 #endif
mbed_official 146:f64d43ff0c18 278
mbed_official 146:f64d43ff0c18 279 //! @brief Format value for bitfield PORT_PCRn_ODE.
mbed_official 146:f64d43ff0c18 280 #define BF_PORT_PCRn_ODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_ODE), uint32_t) & BM_PORT_PCRn_ODE)
mbed_official 146:f64d43ff0c18 281
mbed_official 146:f64d43ff0c18 282 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 283 //! @brief Set the ODE field to a new value.
mbed_official 146:f64d43ff0c18 284 #define BW_PORT_PCRn_ODE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ODE) = (v))
mbed_official 146:f64d43ff0c18 285 #endif
mbed_official 146:f64d43ff0c18 286 //@}
mbed_official 146:f64d43ff0c18 287
mbed_official 146:f64d43ff0c18 288 /*!
mbed_official 146:f64d43ff0c18 289 * @name Register PORT_PCRn, field DSE[6] (RW)
mbed_official 146:f64d43ff0c18 290 *
mbed_official 146:f64d43ff0c18 291 * Drive strength configuration is valid in all digital pin muxing modes.
mbed_official 146:f64d43ff0c18 292 *
mbed_official 146:f64d43ff0c18 293 * Values:
mbed_official 146:f64d43ff0c18 294 * - 0 - Low drive strength is configured on the corresponding pin, if pin is
mbed_official 146:f64d43ff0c18 295 * configured as a digital output.
mbed_official 146:f64d43ff0c18 296 * - 1 - High drive strength is configured on the corresponding pin, if pin is
mbed_official 146:f64d43ff0c18 297 * configured as a digital output.
mbed_official 146:f64d43ff0c18 298 */
mbed_official 146:f64d43ff0c18 299 //@{
mbed_official 146:f64d43ff0c18 300 #define BP_PORT_PCRn_DSE (6U) //!< Bit position for PORT_PCRn_DSE.
mbed_official 146:f64d43ff0c18 301 #define BM_PORT_PCRn_DSE (0x00000040U) //!< Bit mask for PORT_PCRn_DSE.
mbed_official 146:f64d43ff0c18 302 #define BS_PORT_PCRn_DSE (1U) //!< Bit field size in bits for PORT_PCRn_DSE.
mbed_official 146:f64d43ff0c18 303
mbed_official 146:f64d43ff0c18 304 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 305 //! @brief Read current value of the PORT_PCRn_DSE field.
mbed_official 146:f64d43ff0c18 306 #define BR_PORT_PCRn_DSE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_DSE))
mbed_official 146:f64d43ff0c18 307 #endif
mbed_official 146:f64d43ff0c18 308
mbed_official 146:f64d43ff0c18 309 //! @brief Format value for bitfield PORT_PCRn_DSE.
mbed_official 146:f64d43ff0c18 310 #define BF_PORT_PCRn_DSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_DSE), uint32_t) & BM_PORT_PCRn_DSE)
mbed_official 146:f64d43ff0c18 311
mbed_official 146:f64d43ff0c18 312 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 313 //! @brief Set the DSE field to a new value.
mbed_official 146:f64d43ff0c18 314 #define BW_PORT_PCRn_DSE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_DSE) = (v))
mbed_official 146:f64d43ff0c18 315 #endif
mbed_official 146:f64d43ff0c18 316 //@}
mbed_official 146:f64d43ff0c18 317
mbed_official 146:f64d43ff0c18 318 /*!
mbed_official 146:f64d43ff0c18 319 * @name Register PORT_PCRn, field MUX[10:8] (RW)
mbed_official 146:f64d43ff0c18 320 *
mbed_official 146:f64d43ff0c18 321 * Not all pins support all pin muxing slots. Unimplemented pin muxing slots are
mbed_official 146:f64d43ff0c18 322 * reserved and may result in configuring the pin for a different pin muxing
mbed_official 146:f64d43ff0c18 323 * slot. The corresponding pin is configured in the following pin muxing slot as
mbed_official 146:f64d43ff0c18 324 * follows:
mbed_official 146:f64d43ff0c18 325 *
mbed_official 146:f64d43ff0c18 326 * Values:
mbed_official 146:f64d43ff0c18 327 * - 000 - Pin disabled (analog).
mbed_official 146:f64d43ff0c18 328 * - 001 - Alternative 1 (GPIO).
mbed_official 146:f64d43ff0c18 329 * - 010 - Alternative 2 (chip-specific).
mbed_official 146:f64d43ff0c18 330 * - 011 - Alternative 3 (chip-specific).
mbed_official 146:f64d43ff0c18 331 * - 100 - Alternative 4 (chip-specific).
mbed_official 146:f64d43ff0c18 332 * - 101 - Alternative 5 (chip-specific).
mbed_official 146:f64d43ff0c18 333 * - 110 - Alternative 6 (chip-specific).
mbed_official 146:f64d43ff0c18 334 * - 111 - Alternative 7 (chip-specific).
mbed_official 146:f64d43ff0c18 335 */
mbed_official 146:f64d43ff0c18 336 //@{
mbed_official 146:f64d43ff0c18 337 #define BP_PORT_PCRn_MUX (8U) //!< Bit position for PORT_PCRn_MUX.
mbed_official 146:f64d43ff0c18 338 #define BM_PORT_PCRn_MUX (0x00000700U) //!< Bit mask for PORT_PCRn_MUX.
mbed_official 146:f64d43ff0c18 339 #define BS_PORT_PCRn_MUX (3U) //!< Bit field size in bits for PORT_PCRn_MUX.
mbed_official 146:f64d43ff0c18 340
mbed_official 146:f64d43ff0c18 341 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 342 //! @brief Read current value of the PORT_PCRn_MUX field.
mbed_official 146:f64d43ff0c18 343 #define BR_PORT_PCRn_MUX(x, n) (HW_PORT_PCRn(x, n).B.MUX)
mbed_official 146:f64d43ff0c18 344 #endif
mbed_official 146:f64d43ff0c18 345
mbed_official 146:f64d43ff0c18 346 //! @brief Format value for bitfield PORT_PCRn_MUX.
mbed_official 146:f64d43ff0c18 347 #define BF_PORT_PCRn_MUX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_MUX), uint32_t) & BM_PORT_PCRn_MUX)
mbed_official 146:f64d43ff0c18 348
mbed_official 146:f64d43ff0c18 349 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 350 //! @brief Set the MUX field to a new value.
mbed_official 146:f64d43ff0c18 351 #define BW_PORT_PCRn_MUX(x, n, v) (HW_PORT_PCRn_WR(x, n, (HW_PORT_PCRn_RD(x, n) & ~BM_PORT_PCRn_MUX) | BF_PORT_PCRn_MUX(v)))
mbed_official 146:f64d43ff0c18 352 #endif
mbed_official 146:f64d43ff0c18 353 //@}
mbed_official 146:f64d43ff0c18 354
mbed_official 146:f64d43ff0c18 355 /*!
mbed_official 146:f64d43ff0c18 356 * @name Register PORT_PCRn, field LK[15] (RW)
mbed_official 146:f64d43ff0c18 357 *
mbed_official 146:f64d43ff0c18 358 * Values:
mbed_official 146:f64d43ff0c18 359 * - 0 - Pin Control Register fields [15:0] are not locked.
mbed_official 146:f64d43ff0c18 360 * - 1 - Pin Control Register fields [15:0] are locked and cannot be updated
mbed_official 146:f64d43ff0c18 361 * until the next system reset.
mbed_official 146:f64d43ff0c18 362 */
mbed_official 146:f64d43ff0c18 363 //@{
mbed_official 146:f64d43ff0c18 364 #define BP_PORT_PCRn_LK (15U) //!< Bit position for PORT_PCRn_LK.
mbed_official 146:f64d43ff0c18 365 #define BM_PORT_PCRn_LK (0x00008000U) //!< Bit mask for PORT_PCRn_LK.
mbed_official 146:f64d43ff0c18 366 #define BS_PORT_PCRn_LK (1U) //!< Bit field size in bits for PORT_PCRn_LK.
mbed_official 146:f64d43ff0c18 367
mbed_official 146:f64d43ff0c18 368 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 369 //! @brief Read current value of the PORT_PCRn_LK field.
mbed_official 146:f64d43ff0c18 370 #define BR_PORT_PCRn_LK(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_LK))
mbed_official 146:f64d43ff0c18 371 #endif
mbed_official 146:f64d43ff0c18 372
mbed_official 146:f64d43ff0c18 373 //! @brief Format value for bitfield PORT_PCRn_LK.
mbed_official 146:f64d43ff0c18 374 #define BF_PORT_PCRn_LK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_LK), uint32_t) & BM_PORT_PCRn_LK)
mbed_official 146:f64d43ff0c18 375
mbed_official 146:f64d43ff0c18 376 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 377 //! @brief Set the LK field to a new value.
mbed_official 146:f64d43ff0c18 378 #define BW_PORT_PCRn_LK(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_LK) = (v))
mbed_official 146:f64d43ff0c18 379 #endif
mbed_official 146:f64d43ff0c18 380 //@}
mbed_official 146:f64d43ff0c18 381
mbed_official 146:f64d43ff0c18 382 /*!
mbed_official 146:f64d43ff0c18 383 * @name Register PORT_PCRn, field IRQC[19:16] (RW)
mbed_official 146:f64d43ff0c18 384 *
mbed_official 146:f64d43ff0c18 385 * The pin interrupt configuration is valid in all digital pin muxing modes. The
mbed_official 146:f64d43ff0c18 386 * corresponding pin is configured to generate interrupt/DMA request as follows:
mbed_official 146:f64d43ff0c18 387 *
mbed_official 146:f64d43ff0c18 388 * Values:
mbed_official 146:f64d43ff0c18 389 * - 0000 - Interrupt/DMA request disabled.
mbed_official 146:f64d43ff0c18 390 * - 0001 - DMA request on rising edge.
mbed_official 146:f64d43ff0c18 391 * - 0010 - DMA request on falling edge.
mbed_official 146:f64d43ff0c18 392 * - 0011 - DMA request on either edge.
mbed_official 146:f64d43ff0c18 393 * - 1000 - Interrupt when logic 0.
mbed_official 146:f64d43ff0c18 394 * - 1001 - Interrupt on rising-edge.
mbed_official 146:f64d43ff0c18 395 * - 1010 - Interrupt on falling-edge.
mbed_official 146:f64d43ff0c18 396 * - 1011 - Interrupt on either edge.
mbed_official 146:f64d43ff0c18 397 * - 1100 - Interrupt when logic 1.
mbed_official 146:f64d43ff0c18 398 */
mbed_official 146:f64d43ff0c18 399 //@{
mbed_official 146:f64d43ff0c18 400 #define BP_PORT_PCRn_IRQC (16U) //!< Bit position for PORT_PCRn_IRQC.
mbed_official 146:f64d43ff0c18 401 #define BM_PORT_PCRn_IRQC (0x000F0000U) //!< Bit mask for PORT_PCRn_IRQC.
mbed_official 146:f64d43ff0c18 402 #define BS_PORT_PCRn_IRQC (4U) //!< Bit field size in bits for PORT_PCRn_IRQC.
mbed_official 146:f64d43ff0c18 403
mbed_official 146:f64d43ff0c18 404 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 405 //! @brief Read current value of the PORT_PCRn_IRQC field.
mbed_official 146:f64d43ff0c18 406 #define BR_PORT_PCRn_IRQC(x, n) (HW_PORT_PCRn(x, n).B.IRQC)
mbed_official 146:f64d43ff0c18 407 #endif
mbed_official 146:f64d43ff0c18 408
mbed_official 146:f64d43ff0c18 409 //! @brief Format value for bitfield PORT_PCRn_IRQC.
mbed_official 146:f64d43ff0c18 410 #define BF_PORT_PCRn_IRQC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_IRQC), uint32_t) & BM_PORT_PCRn_IRQC)
mbed_official 146:f64d43ff0c18 411
mbed_official 146:f64d43ff0c18 412 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 413 //! @brief Set the IRQC field to a new value.
mbed_official 146:f64d43ff0c18 414 #define BW_PORT_PCRn_IRQC(x, n, v) (HW_PORT_PCRn_WR(x, n, (HW_PORT_PCRn_RD(x, n) & ~BM_PORT_PCRn_IRQC) | BF_PORT_PCRn_IRQC(v)))
mbed_official 146:f64d43ff0c18 415 #endif
mbed_official 146:f64d43ff0c18 416 //@}
mbed_official 146:f64d43ff0c18 417
mbed_official 146:f64d43ff0c18 418 /*!
mbed_official 146:f64d43ff0c18 419 * @name Register PORT_PCRn, field ISF[24] (W1C)
mbed_official 146:f64d43ff0c18 420 *
mbed_official 146:f64d43ff0c18 421 * The pin interrupt configuration is valid in all digital pin muxing modes.
mbed_official 146:f64d43ff0c18 422 *
mbed_official 146:f64d43ff0c18 423 * Values:
mbed_official 146:f64d43ff0c18 424 * - 0 - Configured interrupt is not detected.
mbed_official 146:f64d43ff0c18 425 * - 1 - Configured interrupt is detected. If the pin is configured to generate
mbed_official 146:f64d43ff0c18 426 * a DMA request, then the corresponding flag will be cleared automatically
mbed_official 146:f64d43ff0c18 427 * at the completion of the requested DMA transfer. Otherwise, the flag
mbed_official 146:f64d43ff0c18 428 * remains set until a logic 1 is written to the flag. If the pin is configured for
mbed_official 146:f64d43ff0c18 429 * a level sensitive interrupt and the pin remains asserted, then the flag
mbed_official 146:f64d43ff0c18 430 * is set again immediately after it is cleared.
mbed_official 146:f64d43ff0c18 431 */
mbed_official 146:f64d43ff0c18 432 //@{
mbed_official 146:f64d43ff0c18 433 #define BP_PORT_PCRn_ISF (24U) //!< Bit position for PORT_PCRn_ISF.
mbed_official 146:f64d43ff0c18 434 #define BM_PORT_PCRn_ISF (0x01000000U) //!< Bit mask for PORT_PCRn_ISF.
mbed_official 146:f64d43ff0c18 435 #define BS_PORT_PCRn_ISF (1U) //!< Bit field size in bits for PORT_PCRn_ISF.
mbed_official 146:f64d43ff0c18 436
mbed_official 146:f64d43ff0c18 437 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 438 //! @brief Read current value of the PORT_PCRn_ISF field.
mbed_official 146:f64d43ff0c18 439 #define BR_PORT_PCRn_ISF(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ISF))
mbed_official 146:f64d43ff0c18 440 #endif
mbed_official 146:f64d43ff0c18 441
mbed_official 146:f64d43ff0c18 442 //! @brief Format value for bitfield PORT_PCRn_ISF.
mbed_official 146:f64d43ff0c18 443 #define BF_PORT_PCRn_ISF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_ISF), uint32_t) & BM_PORT_PCRn_ISF)
mbed_official 146:f64d43ff0c18 444
mbed_official 146:f64d43ff0c18 445 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 446 //! @brief Set the ISF field to a new value.
mbed_official 146:f64d43ff0c18 447 #define BW_PORT_PCRn_ISF(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ISF) = (v))
mbed_official 146:f64d43ff0c18 448 #endif
mbed_official 146:f64d43ff0c18 449 //@}
mbed_official 146:f64d43ff0c18 450
mbed_official 146:f64d43ff0c18 451 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 452 // HW_PORT_GPCLR - Global Pin Control Low Register
mbed_official 146:f64d43ff0c18 453 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 454
mbed_official 146:f64d43ff0c18 455 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 456 /*!
mbed_official 146:f64d43ff0c18 457 * @brief HW_PORT_GPCLR - Global Pin Control Low Register (WORZ)
mbed_official 146:f64d43ff0c18 458 *
mbed_official 146:f64d43ff0c18 459 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 460 *
mbed_official 146:f64d43ff0c18 461 * Only 32-bit writes are supported to this register.
mbed_official 146:f64d43ff0c18 462 */
mbed_official 146:f64d43ff0c18 463 typedef union _hw_port_gpclr
mbed_official 146:f64d43ff0c18 464 {
mbed_official 146:f64d43ff0c18 465 uint32_t U;
mbed_official 146:f64d43ff0c18 466 struct _hw_port_gpclr_bitfields
mbed_official 146:f64d43ff0c18 467 {
mbed_official 146:f64d43ff0c18 468 uint32_t GPWD : 16; //!< [15:0] Global Pin Write Data
mbed_official 146:f64d43ff0c18 469 uint32_t GPWE : 16; //!< [31:16] Global Pin Write Enable
mbed_official 146:f64d43ff0c18 470 } B;
mbed_official 146:f64d43ff0c18 471 } hw_port_gpclr_t;
mbed_official 146:f64d43ff0c18 472 #endif
mbed_official 146:f64d43ff0c18 473
mbed_official 146:f64d43ff0c18 474 /*!
mbed_official 146:f64d43ff0c18 475 * @name Constants and macros for entire PORT_GPCLR register
mbed_official 146:f64d43ff0c18 476 */
mbed_official 146:f64d43ff0c18 477 //@{
mbed_official 146:f64d43ff0c18 478 #define HW_PORT_GPCLR_ADDR(x) (REGS_PORT_BASE(x) + 0x80U)
mbed_official 146:f64d43ff0c18 479
mbed_official 146:f64d43ff0c18 480 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 481 #define HW_PORT_GPCLR(x) (*(__O hw_port_gpclr_t *) HW_PORT_GPCLR_ADDR(x))
mbed_official 146:f64d43ff0c18 482 #define HW_PORT_GPCLR_RD(x) (HW_PORT_GPCLR(x).U)
mbed_official 146:f64d43ff0c18 483 #define HW_PORT_GPCLR_WR(x, v) (HW_PORT_GPCLR(x).U = (v))
mbed_official 146:f64d43ff0c18 484 #endif
mbed_official 146:f64d43ff0c18 485 //@}
mbed_official 146:f64d43ff0c18 486
mbed_official 146:f64d43ff0c18 487 /*
mbed_official 146:f64d43ff0c18 488 * Constants & macros for individual PORT_GPCLR bitfields
mbed_official 146:f64d43ff0c18 489 */
mbed_official 146:f64d43ff0c18 490
mbed_official 146:f64d43ff0c18 491 /*!
mbed_official 146:f64d43ff0c18 492 * @name Register PORT_GPCLR, field GPWD[15:0] (WORZ)
mbed_official 146:f64d43ff0c18 493 *
mbed_official 146:f64d43ff0c18 494 * Write value that is written to all Pin Control Registers bits [15:0] that are
mbed_official 146:f64d43ff0c18 495 * selected by GPWE.
mbed_official 146:f64d43ff0c18 496 */
mbed_official 146:f64d43ff0c18 497 //@{
mbed_official 146:f64d43ff0c18 498 #define BP_PORT_GPCLR_GPWD (0U) //!< Bit position for PORT_GPCLR_GPWD.
mbed_official 146:f64d43ff0c18 499 #define BM_PORT_GPCLR_GPWD (0x0000FFFFU) //!< Bit mask for PORT_GPCLR_GPWD.
mbed_official 146:f64d43ff0c18 500 #define BS_PORT_GPCLR_GPWD (16U) //!< Bit field size in bits for PORT_GPCLR_GPWD.
mbed_official 146:f64d43ff0c18 501
mbed_official 146:f64d43ff0c18 502 //! @brief Format value for bitfield PORT_GPCLR_GPWD.
mbed_official 146:f64d43ff0c18 503 #define BF_PORT_GPCLR_GPWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_GPCLR_GPWD), uint32_t) & BM_PORT_GPCLR_GPWD)
mbed_official 146:f64d43ff0c18 504
mbed_official 146:f64d43ff0c18 505 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 506 //! @brief Set the GPWD field to a new value.
mbed_official 146:f64d43ff0c18 507 #define BW_PORT_GPCLR_GPWD(x, v) (HW_PORT_GPCLR_WR(x, (HW_PORT_GPCLR_RD(x) & ~BM_PORT_GPCLR_GPWD) | BF_PORT_GPCLR_GPWD(v)))
mbed_official 146:f64d43ff0c18 508 #endif
mbed_official 146:f64d43ff0c18 509 //@}
mbed_official 146:f64d43ff0c18 510
mbed_official 146:f64d43ff0c18 511 /*!
mbed_official 146:f64d43ff0c18 512 * @name Register PORT_GPCLR, field GPWE[31:16] (WORZ)
mbed_official 146:f64d43ff0c18 513 *
mbed_official 146:f64d43ff0c18 514 * Selects which Pin Control Registers (15 through 0) bits [15:0] update with
mbed_official 146:f64d43ff0c18 515 * the value in GPWD. If a selected Pin Control Register is locked then the write
mbed_official 146:f64d43ff0c18 516 * to that register is ignored.
mbed_official 146:f64d43ff0c18 517 *
mbed_official 146:f64d43ff0c18 518 * Values:
mbed_official 146:f64d43ff0c18 519 * - 0 - Corresponding Pin Control Register is not updated with the value in
mbed_official 146:f64d43ff0c18 520 * GPWD.
mbed_official 146:f64d43ff0c18 521 * - 1 - Corresponding Pin Control Register is updated with the value in GPWD.
mbed_official 146:f64d43ff0c18 522 */
mbed_official 146:f64d43ff0c18 523 //@{
mbed_official 146:f64d43ff0c18 524 #define BP_PORT_GPCLR_GPWE (16U) //!< Bit position for PORT_GPCLR_GPWE.
mbed_official 146:f64d43ff0c18 525 #define BM_PORT_GPCLR_GPWE (0xFFFF0000U) //!< Bit mask for PORT_GPCLR_GPWE.
mbed_official 146:f64d43ff0c18 526 #define BS_PORT_GPCLR_GPWE (16U) //!< Bit field size in bits for PORT_GPCLR_GPWE.
mbed_official 146:f64d43ff0c18 527
mbed_official 146:f64d43ff0c18 528 //! @brief Format value for bitfield PORT_GPCLR_GPWE.
mbed_official 146:f64d43ff0c18 529 #define BF_PORT_GPCLR_GPWE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_GPCLR_GPWE), uint32_t) & BM_PORT_GPCLR_GPWE)
mbed_official 146:f64d43ff0c18 530
mbed_official 146:f64d43ff0c18 531 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 532 //! @brief Set the GPWE field to a new value.
mbed_official 146:f64d43ff0c18 533 #define BW_PORT_GPCLR_GPWE(x, v) (HW_PORT_GPCLR_WR(x, (HW_PORT_GPCLR_RD(x) & ~BM_PORT_GPCLR_GPWE) | BF_PORT_GPCLR_GPWE(v)))
mbed_official 146:f64d43ff0c18 534 #endif
mbed_official 146:f64d43ff0c18 535 //@}
mbed_official 146:f64d43ff0c18 536
mbed_official 146:f64d43ff0c18 537 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 538 // HW_PORT_GPCHR - Global Pin Control High Register
mbed_official 146:f64d43ff0c18 539 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 540
mbed_official 146:f64d43ff0c18 541 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 542 /*!
mbed_official 146:f64d43ff0c18 543 * @brief HW_PORT_GPCHR - Global Pin Control High Register (WORZ)
mbed_official 146:f64d43ff0c18 544 *
mbed_official 146:f64d43ff0c18 545 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 546 *
mbed_official 146:f64d43ff0c18 547 * Only 32-bit writes are supported to this register.
mbed_official 146:f64d43ff0c18 548 */
mbed_official 146:f64d43ff0c18 549 typedef union _hw_port_gpchr
mbed_official 146:f64d43ff0c18 550 {
mbed_official 146:f64d43ff0c18 551 uint32_t U;
mbed_official 146:f64d43ff0c18 552 struct _hw_port_gpchr_bitfields
mbed_official 146:f64d43ff0c18 553 {
mbed_official 146:f64d43ff0c18 554 uint32_t GPWD : 16; //!< [15:0] Global Pin Write Data
mbed_official 146:f64d43ff0c18 555 uint32_t GPWE : 16; //!< [31:16] Global Pin Write Enable
mbed_official 146:f64d43ff0c18 556 } B;
mbed_official 146:f64d43ff0c18 557 } hw_port_gpchr_t;
mbed_official 146:f64d43ff0c18 558 #endif
mbed_official 146:f64d43ff0c18 559
mbed_official 146:f64d43ff0c18 560 /*!
mbed_official 146:f64d43ff0c18 561 * @name Constants and macros for entire PORT_GPCHR register
mbed_official 146:f64d43ff0c18 562 */
mbed_official 146:f64d43ff0c18 563 //@{
mbed_official 146:f64d43ff0c18 564 #define HW_PORT_GPCHR_ADDR(x) (REGS_PORT_BASE(x) + 0x84U)
mbed_official 146:f64d43ff0c18 565
mbed_official 146:f64d43ff0c18 566 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 567 #define HW_PORT_GPCHR(x) (*(__O hw_port_gpchr_t *) HW_PORT_GPCHR_ADDR(x))
mbed_official 146:f64d43ff0c18 568 #define HW_PORT_GPCHR_RD(x) (HW_PORT_GPCHR(x).U)
mbed_official 146:f64d43ff0c18 569 #define HW_PORT_GPCHR_WR(x, v) (HW_PORT_GPCHR(x).U = (v))
mbed_official 146:f64d43ff0c18 570 #endif
mbed_official 146:f64d43ff0c18 571 //@}
mbed_official 146:f64d43ff0c18 572
mbed_official 146:f64d43ff0c18 573 /*
mbed_official 146:f64d43ff0c18 574 * Constants & macros for individual PORT_GPCHR bitfields
mbed_official 146:f64d43ff0c18 575 */
mbed_official 146:f64d43ff0c18 576
mbed_official 146:f64d43ff0c18 577 /*!
mbed_official 146:f64d43ff0c18 578 * @name Register PORT_GPCHR, field GPWD[15:0] (WORZ)
mbed_official 146:f64d43ff0c18 579 *
mbed_official 146:f64d43ff0c18 580 * Write value that is written to all Pin Control Registers bits [15:0] that are
mbed_official 146:f64d43ff0c18 581 * selected by GPWE.
mbed_official 146:f64d43ff0c18 582 */
mbed_official 146:f64d43ff0c18 583 //@{
mbed_official 146:f64d43ff0c18 584 #define BP_PORT_GPCHR_GPWD (0U) //!< Bit position for PORT_GPCHR_GPWD.
mbed_official 146:f64d43ff0c18 585 #define BM_PORT_GPCHR_GPWD (0x0000FFFFU) //!< Bit mask for PORT_GPCHR_GPWD.
mbed_official 146:f64d43ff0c18 586 #define BS_PORT_GPCHR_GPWD (16U) //!< Bit field size in bits for PORT_GPCHR_GPWD.
mbed_official 146:f64d43ff0c18 587
mbed_official 146:f64d43ff0c18 588 //! @brief Format value for bitfield PORT_GPCHR_GPWD.
mbed_official 146:f64d43ff0c18 589 #define BF_PORT_GPCHR_GPWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_GPCHR_GPWD), uint32_t) & BM_PORT_GPCHR_GPWD)
mbed_official 146:f64d43ff0c18 590
mbed_official 146:f64d43ff0c18 591 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 592 //! @brief Set the GPWD field to a new value.
mbed_official 146:f64d43ff0c18 593 #define BW_PORT_GPCHR_GPWD(x, v) (HW_PORT_GPCHR_WR(x, (HW_PORT_GPCHR_RD(x) & ~BM_PORT_GPCHR_GPWD) | BF_PORT_GPCHR_GPWD(v)))
mbed_official 146:f64d43ff0c18 594 #endif
mbed_official 146:f64d43ff0c18 595 //@}
mbed_official 146:f64d43ff0c18 596
mbed_official 146:f64d43ff0c18 597 /*!
mbed_official 146:f64d43ff0c18 598 * @name Register PORT_GPCHR, field GPWE[31:16] (WORZ)
mbed_official 146:f64d43ff0c18 599 *
mbed_official 146:f64d43ff0c18 600 * Selects which Pin Control Registers (31 through 16) bits [15:0] update with
mbed_official 146:f64d43ff0c18 601 * the value in GPWD. If a selected Pin Control Register is locked then the write
mbed_official 146:f64d43ff0c18 602 * to that register is ignored.
mbed_official 146:f64d43ff0c18 603 *
mbed_official 146:f64d43ff0c18 604 * Values:
mbed_official 146:f64d43ff0c18 605 * - 0 - Corresponding Pin Control Register is not updated with the value in
mbed_official 146:f64d43ff0c18 606 * GPWD.
mbed_official 146:f64d43ff0c18 607 * - 1 - Corresponding Pin Control Register is updated with the value in GPWD.
mbed_official 146:f64d43ff0c18 608 */
mbed_official 146:f64d43ff0c18 609 //@{
mbed_official 146:f64d43ff0c18 610 #define BP_PORT_GPCHR_GPWE (16U) //!< Bit position for PORT_GPCHR_GPWE.
mbed_official 146:f64d43ff0c18 611 #define BM_PORT_GPCHR_GPWE (0xFFFF0000U) //!< Bit mask for PORT_GPCHR_GPWE.
mbed_official 146:f64d43ff0c18 612 #define BS_PORT_GPCHR_GPWE (16U) //!< Bit field size in bits for PORT_GPCHR_GPWE.
mbed_official 146:f64d43ff0c18 613
mbed_official 146:f64d43ff0c18 614 //! @brief Format value for bitfield PORT_GPCHR_GPWE.
mbed_official 146:f64d43ff0c18 615 #define BF_PORT_GPCHR_GPWE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_GPCHR_GPWE), uint32_t) & BM_PORT_GPCHR_GPWE)
mbed_official 146:f64d43ff0c18 616
mbed_official 146:f64d43ff0c18 617 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 618 //! @brief Set the GPWE field to a new value.
mbed_official 146:f64d43ff0c18 619 #define BW_PORT_GPCHR_GPWE(x, v) (HW_PORT_GPCHR_WR(x, (HW_PORT_GPCHR_RD(x) & ~BM_PORT_GPCHR_GPWE) | BF_PORT_GPCHR_GPWE(v)))
mbed_official 146:f64d43ff0c18 620 #endif
mbed_official 146:f64d43ff0c18 621 //@}
mbed_official 146:f64d43ff0c18 622
mbed_official 146:f64d43ff0c18 623 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 624 // HW_PORT_ISFR - Interrupt Status Flag Register
mbed_official 146:f64d43ff0c18 625 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 626
mbed_official 146:f64d43ff0c18 627 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 628 /*!
mbed_official 146:f64d43ff0c18 629 * @brief HW_PORT_ISFR - Interrupt Status Flag Register (W1C)
mbed_official 146:f64d43ff0c18 630 *
mbed_official 146:f64d43ff0c18 631 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 632 *
mbed_official 146:f64d43ff0c18 633 * The pin interrupt configuration is valid in all digital pin muxing modes. The
mbed_official 146:f64d43ff0c18 634 * Interrupt Status Flag for each pin is also visible in the corresponding Pin
mbed_official 146:f64d43ff0c18 635 * Control Register, and each flag can be cleared in either location.
mbed_official 146:f64d43ff0c18 636 */
mbed_official 146:f64d43ff0c18 637 typedef union _hw_port_isfr
mbed_official 146:f64d43ff0c18 638 {
mbed_official 146:f64d43ff0c18 639 uint32_t U;
mbed_official 146:f64d43ff0c18 640 struct _hw_port_isfr_bitfields
mbed_official 146:f64d43ff0c18 641 {
mbed_official 146:f64d43ff0c18 642 uint32_t ISF : 32; //!< [31:0] Interrupt Status Flag
mbed_official 146:f64d43ff0c18 643 } B;
mbed_official 146:f64d43ff0c18 644 } hw_port_isfr_t;
mbed_official 146:f64d43ff0c18 645 #endif
mbed_official 146:f64d43ff0c18 646
mbed_official 146:f64d43ff0c18 647 /*!
mbed_official 146:f64d43ff0c18 648 * @name Constants and macros for entire PORT_ISFR register
mbed_official 146:f64d43ff0c18 649 */
mbed_official 146:f64d43ff0c18 650 //@{
mbed_official 146:f64d43ff0c18 651 #define HW_PORT_ISFR_ADDR(x) (REGS_PORT_BASE(x) + 0xA0U)
mbed_official 146:f64d43ff0c18 652
mbed_official 146:f64d43ff0c18 653 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 654 #define HW_PORT_ISFR(x) (*(__IO hw_port_isfr_t *) HW_PORT_ISFR_ADDR(x))
mbed_official 146:f64d43ff0c18 655 #define HW_PORT_ISFR_RD(x) (HW_PORT_ISFR(x).U)
mbed_official 146:f64d43ff0c18 656 #define HW_PORT_ISFR_WR(x, v) (HW_PORT_ISFR(x).U = (v))
mbed_official 146:f64d43ff0c18 657 #define HW_PORT_ISFR_SET(x, v) (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 658 #define HW_PORT_ISFR_CLR(x, v) (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 659 #define HW_PORT_ISFR_TOG(x, v) (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 660 #endif
mbed_official 146:f64d43ff0c18 661 //@}
mbed_official 146:f64d43ff0c18 662
mbed_official 146:f64d43ff0c18 663 /*
mbed_official 146:f64d43ff0c18 664 * Constants & macros for individual PORT_ISFR bitfields
mbed_official 146:f64d43ff0c18 665 */
mbed_official 146:f64d43ff0c18 666
mbed_official 146:f64d43ff0c18 667 /*!
mbed_official 146:f64d43ff0c18 668 * @name Register PORT_ISFR, field ISF[31:0] (W1C)
mbed_official 146:f64d43ff0c18 669 *
mbed_official 146:f64d43ff0c18 670 * Each bit in the field indicates the detection of the configured interrupt of
mbed_official 146:f64d43ff0c18 671 * the same number as the field.
mbed_official 146:f64d43ff0c18 672 *
mbed_official 146:f64d43ff0c18 673 * Values:
mbed_official 146:f64d43ff0c18 674 * - 0 - Configured interrupt is not detected.
mbed_official 146:f64d43ff0c18 675 * - 1 - Configured interrupt is detected. If the pin is configured to generate
mbed_official 146:f64d43ff0c18 676 * a DMA request, then the corresponding flag will be cleared automatically
mbed_official 146:f64d43ff0c18 677 * at the completion of the requested DMA transfer. Otherwise, the flag
mbed_official 146:f64d43ff0c18 678 * remains set until a logic 1 is written to the flag. If the pin is configured for
mbed_official 146:f64d43ff0c18 679 * a level sensitive interrupt and the pin remains asserted, then the flag
mbed_official 146:f64d43ff0c18 680 * is set again immediately after it is cleared.
mbed_official 146:f64d43ff0c18 681 */
mbed_official 146:f64d43ff0c18 682 //@{
mbed_official 146:f64d43ff0c18 683 #define BP_PORT_ISFR_ISF (0U) //!< Bit position for PORT_ISFR_ISF.
mbed_official 146:f64d43ff0c18 684 #define BM_PORT_ISFR_ISF (0xFFFFFFFFU) //!< Bit mask for PORT_ISFR_ISF.
mbed_official 146:f64d43ff0c18 685 #define BS_PORT_ISFR_ISF (32U) //!< Bit field size in bits for PORT_ISFR_ISF.
mbed_official 146:f64d43ff0c18 686
mbed_official 146:f64d43ff0c18 687 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 688 //! @brief Read current value of the PORT_ISFR_ISF field.
mbed_official 146:f64d43ff0c18 689 #define BR_PORT_ISFR_ISF(x) (HW_PORT_ISFR(x).U)
mbed_official 146:f64d43ff0c18 690 #endif
mbed_official 146:f64d43ff0c18 691
mbed_official 146:f64d43ff0c18 692 //! @brief Format value for bitfield PORT_ISFR_ISF.
mbed_official 146:f64d43ff0c18 693 #define BF_PORT_ISFR_ISF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_ISFR_ISF), uint32_t) & BM_PORT_ISFR_ISF)
mbed_official 146:f64d43ff0c18 694
mbed_official 146:f64d43ff0c18 695 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 696 //! @brief Set the ISF field to a new value.
mbed_official 146:f64d43ff0c18 697 #define BW_PORT_ISFR_ISF(x, v) (HW_PORT_ISFR_WR(x, v))
mbed_official 146:f64d43ff0c18 698 #endif
mbed_official 146:f64d43ff0c18 699 //@}
mbed_official 146:f64d43ff0c18 700
mbed_official 146:f64d43ff0c18 701 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 702 // HW_PORT_DFER - Digital Filter Enable Register
mbed_official 146:f64d43ff0c18 703 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 704
mbed_official 146:f64d43ff0c18 705 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 706 /*!
mbed_official 146:f64d43ff0c18 707 * @brief HW_PORT_DFER - Digital Filter Enable Register (RW)
mbed_official 146:f64d43ff0c18 708 *
mbed_official 146:f64d43ff0c18 709 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 710 *
mbed_official 146:f64d43ff0c18 711 * The corresponding bit is read only for pins that do not support a digital
mbed_official 146:f64d43ff0c18 712 * filter. Refer to the Chapter of Signal Multiplexing and Signal Descriptions for
mbed_official 146:f64d43ff0c18 713 * the pins that support digital filter. The digital filter configuration is valid
mbed_official 146:f64d43ff0c18 714 * in all digital pin muxing modes.
mbed_official 146:f64d43ff0c18 715 */
mbed_official 146:f64d43ff0c18 716 typedef union _hw_port_dfer
mbed_official 146:f64d43ff0c18 717 {
mbed_official 146:f64d43ff0c18 718 uint32_t U;
mbed_official 146:f64d43ff0c18 719 struct _hw_port_dfer_bitfields
mbed_official 146:f64d43ff0c18 720 {
mbed_official 146:f64d43ff0c18 721 uint32_t DFE : 32; //!< [31:0] Digital Filter Enable
mbed_official 146:f64d43ff0c18 722 } B;
mbed_official 146:f64d43ff0c18 723 } hw_port_dfer_t;
mbed_official 146:f64d43ff0c18 724 #endif
mbed_official 146:f64d43ff0c18 725
mbed_official 146:f64d43ff0c18 726 /*!
mbed_official 146:f64d43ff0c18 727 * @name Constants and macros for entire PORT_DFER register
mbed_official 146:f64d43ff0c18 728 */
mbed_official 146:f64d43ff0c18 729 //@{
mbed_official 146:f64d43ff0c18 730 #define HW_PORT_DFER_ADDR(x) (REGS_PORT_BASE(x) + 0xC0U)
mbed_official 146:f64d43ff0c18 731
mbed_official 146:f64d43ff0c18 732 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 733 #define HW_PORT_DFER(x) (*(__IO hw_port_dfer_t *) HW_PORT_DFER_ADDR(x))
mbed_official 146:f64d43ff0c18 734 #define HW_PORT_DFER_RD(x) (HW_PORT_DFER(x).U)
mbed_official 146:f64d43ff0c18 735 #define HW_PORT_DFER_WR(x, v) (HW_PORT_DFER(x).U = (v))
mbed_official 146:f64d43ff0c18 736 #define HW_PORT_DFER_SET(x, v) (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 737 #define HW_PORT_DFER_CLR(x, v) (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 738 #define HW_PORT_DFER_TOG(x, v) (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 739 #endif
mbed_official 146:f64d43ff0c18 740 //@}
mbed_official 146:f64d43ff0c18 741
mbed_official 146:f64d43ff0c18 742 /*
mbed_official 146:f64d43ff0c18 743 * Constants & macros for individual PORT_DFER bitfields
mbed_official 146:f64d43ff0c18 744 */
mbed_official 146:f64d43ff0c18 745
mbed_official 146:f64d43ff0c18 746 /*!
mbed_official 146:f64d43ff0c18 747 * @name Register PORT_DFER, field DFE[31:0] (RW)
mbed_official 146:f64d43ff0c18 748 *
mbed_official 146:f64d43ff0c18 749 * The digital filter configuration is valid in all digital pin muxing modes.
mbed_official 146:f64d43ff0c18 750 * The output of each digital filter is reset to zero at system reset and whenever
mbed_official 146:f64d43ff0c18 751 * the digital filter is disabled. Each bit in the field enables the digital
mbed_official 146:f64d43ff0c18 752 * filter of the same number as the field.
mbed_official 146:f64d43ff0c18 753 *
mbed_official 146:f64d43ff0c18 754 * Values:
mbed_official 146:f64d43ff0c18 755 * - 0 - Digital filter is disabled on the corresponding pin and output of the
mbed_official 146:f64d43ff0c18 756 * digital filter is reset to zero.
mbed_official 146:f64d43ff0c18 757 * - 1 - Digital filter is enabled on the corresponding pin, if the pin is
mbed_official 146:f64d43ff0c18 758 * configured as a digital input.
mbed_official 146:f64d43ff0c18 759 */
mbed_official 146:f64d43ff0c18 760 //@{
mbed_official 146:f64d43ff0c18 761 #define BP_PORT_DFER_DFE (0U) //!< Bit position for PORT_DFER_DFE.
mbed_official 146:f64d43ff0c18 762 #define BM_PORT_DFER_DFE (0xFFFFFFFFU) //!< Bit mask for PORT_DFER_DFE.
mbed_official 146:f64d43ff0c18 763 #define BS_PORT_DFER_DFE (32U) //!< Bit field size in bits for PORT_DFER_DFE.
mbed_official 146:f64d43ff0c18 764
mbed_official 146:f64d43ff0c18 765 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 766 //! @brief Read current value of the PORT_DFER_DFE field.
mbed_official 146:f64d43ff0c18 767 #define BR_PORT_DFER_DFE(x) (HW_PORT_DFER(x).U)
mbed_official 146:f64d43ff0c18 768 #endif
mbed_official 146:f64d43ff0c18 769
mbed_official 146:f64d43ff0c18 770 //! @brief Format value for bitfield PORT_DFER_DFE.
mbed_official 146:f64d43ff0c18 771 #define BF_PORT_DFER_DFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_DFER_DFE), uint32_t) & BM_PORT_DFER_DFE)
mbed_official 146:f64d43ff0c18 772
mbed_official 146:f64d43ff0c18 773 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 774 //! @brief Set the DFE field to a new value.
mbed_official 146:f64d43ff0c18 775 #define BW_PORT_DFER_DFE(x, v) (HW_PORT_DFER_WR(x, v))
mbed_official 146:f64d43ff0c18 776 #endif
mbed_official 146:f64d43ff0c18 777 //@}
mbed_official 146:f64d43ff0c18 778
mbed_official 146:f64d43ff0c18 779 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 780 // HW_PORT_DFCR - Digital Filter Clock Register
mbed_official 146:f64d43ff0c18 781 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 782
mbed_official 146:f64d43ff0c18 783 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 784 /*!
mbed_official 146:f64d43ff0c18 785 * @brief HW_PORT_DFCR - Digital Filter Clock Register (RW)
mbed_official 146:f64d43ff0c18 786 *
mbed_official 146:f64d43ff0c18 787 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 788 *
mbed_official 146:f64d43ff0c18 789 * This register is read only for ports that do not support a digital filter.
mbed_official 146:f64d43ff0c18 790 * The digital filter configuration is valid in all digital pin muxing modes.
mbed_official 146:f64d43ff0c18 791 */
mbed_official 146:f64d43ff0c18 792 typedef union _hw_port_dfcr
mbed_official 146:f64d43ff0c18 793 {
mbed_official 146:f64d43ff0c18 794 uint32_t U;
mbed_official 146:f64d43ff0c18 795 struct _hw_port_dfcr_bitfields
mbed_official 146:f64d43ff0c18 796 {
mbed_official 146:f64d43ff0c18 797 uint32_t CS : 1; //!< [0] Clock Source
mbed_official 146:f64d43ff0c18 798 uint32_t RESERVED0 : 31; //!< [31:1]
mbed_official 146:f64d43ff0c18 799 } B;
mbed_official 146:f64d43ff0c18 800 } hw_port_dfcr_t;
mbed_official 146:f64d43ff0c18 801 #endif
mbed_official 146:f64d43ff0c18 802
mbed_official 146:f64d43ff0c18 803 /*!
mbed_official 146:f64d43ff0c18 804 * @name Constants and macros for entire PORT_DFCR register
mbed_official 146:f64d43ff0c18 805 */
mbed_official 146:f64d43ff0c18 806 //@{
mbed_official 146:f64d43ff0c18 807 #define HW_PORT_DFCR_ADDR(x) (REGS_PORT_BASE(x) + 0xC4U)
mbed_official 146:f64d43ff0c18 808
mbed_official 146:f64d43ff0c18 809 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 810 #define HW_PORT_DFCR(x) (*(__IO hw_port_dfcr_t *) HW_PORT_DFCR_ADDR(x))
mbed_official 146:f64d43ff0c18 811 #define HW_PORT_DFCR_RD(x) (HW_PORT_DFCR(x).U)
mbed_official 146:f64d43ff0c18 812 #define HW_PORT_DFCR_WR(x, v) (HW_PORT_DFCR(x).U = (v))
mbed_official 146:f64d43ff0c18 813 #define HW_PORT_DFCR_SET(x, v) (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 814 #define HW_PORT_DFCR_CLR(x, v) (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 815 #define HW_PORT_DFCR_TOG(x, v) (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 816 #endif
mbed_official 146:f64d43ff0c18 817 //@}
mbed_official 146:f64d43ff0c18 818
mbed_official 146:f64d43ff0c18 819 /*
mbed_official 146:f64d43ff0c18 820 * Constants & macros for individual PORT_DFCR bitfields
mbed_official 146:f64d43ff0c18 821 */
mbed_official 146:f64d43ff0c18 822
mbed_official 146:f64d43ff0c18 823 /*!
mbed_official 146:f64d43ff0c18 824 * @name Register PORT_DFCR, field CS[0] (RW)
mbed_official 146:f64d43ff0c18 825 *
mbed_official 146:f64d43ff0c18 826 * The digital filter configuration is valid in all digital pin muxing modes.
mbed_official 146:f64d43ff0c18 827 * Configures the clock source for the digital input filters. Changing the filter
mbed_official 146:f64d43ff0c18 828 * clock source must be done only when all digital filters are disabled.
mbed_official 146:f64d43ff0c18 829 *
mbed_official 146:f64d43ff0c18 830 * Values:
mbed_official 146:f64d43ff0c18 831 * - 0 - Digital filters are clocked by the bus clock.
mbed_official 146:f64d43ff0c18 832 * - 1 - Digital filters are clocked by the 1 kHz LPO clock.
mbed_official 146:f64d43ff0c18 833 */
mbed_official 146:f64d43ff0c18 834 //@{
mbed_official 146:f64d43ff0c18 835 #define BP_PORT_DFCR_CS (0U) //!< Bit position for PORT_DFCR_CS.
mbed_official 146:f64d43ff0c18 836 #define BM_PORT_DFCR_CS (0x00000001U) //!< Bit mask for PORT_DFCR_CS.
mbed_official 146:f64d43ff0c18 837 #define BS_PORT_DFCR_CS (1U) //!< Bit field size in bits for PORT_DFCR_CS.
mbed_official 146:f64d43ff0c18 838
mbed_official 146:f64d43ff0c18 839 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 840 //! @brief Read current value of the PORT_DFCR_CS field.
mbed_official 146:f64d43ff0c18 841 #define BR_PORT_DFCR_CS(x) (BITBAND_ACCESS32(HW_PORT_DFCR_ADDR(x), BP_PORT_DFCR_CS))
mbed_official 146:f64d43ff0c18 842 #endif
mbed_official 146:f64d43ff0c18 843
mbed_official 146:f64d43ff0c18 844 //! @brief Format value for bitfield PORT_DFCR_CS.
mbed_official 146:f64d43ff0c18 845 #define BF_PORT_DFCR_CS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_DFCR_CS), uint32_t) & BM_PORT_DFCR_CS)
mbed_official 146:f64d43ff0c18 846
mbed_official 146:f64d43ff0c18 847 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 848 //! @brief Set the CS field to a new value.
mbed_official 146:f64d43ff0c18 849 #define BW_PORT_DFCR_CS(x, v) (BITBAND_ACCESS32(HW_PORT_DFCR_ADDR(x), BP_PORT_DFCR_CS) = (v))
mbed_official 146:f64d43ff0c18 850 #endif
mbed_official 146:f64d43ff0c18 851 //@}
mbed_official 146:f64d43ff0c18 852
mbed_official 146:f64d43ff0c18 853 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 854 // HW_PORT_DFWR - Digital Filter Width Register
mbed_official 146:f64d43ff0c18 855 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 856
mbed_official 146:f64d43ff0c18 857 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 858 /*!
mbed_official 146:f64d43ff0c18 859 * @brief HW_PORT_DFWR - Digital Filter Width Register (RW)
mbed_official 146:f64d43ff0c18 860 *
mbed_official 146:f64d43ff0c18 861 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 862 *
mbed_official 146:f64d43ff0c18 863 * This register is read only for ports that do not support a digital filter.
mbed_official 146:f64d43ff0c18 864 * The digital filter configuration is valid in all digital pin muxing modes.
mbed_official 146:f64d43ff0c18 865 */
mbed_official 146:f64d43ff0c18 866 typedef union _hw_port_dfwr
mbed_official 146:f64d43ff0c18 867 {
mbed_official 146:f64d43ff0c18 868 uint32_t U;
mbed_official 146:f64d43ff0c18 869 struct _hw_port_dfwr_bitfields
mbed_official 146:f64d43ff0c18 870 {
mbed_official 146:f64d43ff0c18 871 uint32_t FILT : 5; //!< [4:0] Filter Length
mbed_official 146:f64d43ff0c18 872 uint32_t RESERVED0 : 27; //!< [31:5]
mbed_official 146:f64d43ff0c18 873 } B;
mbed_official 146:f64d43ff0c18 874 } hw_port_dfwr_t;
mbed_official 146:f64d43ff0c18 875 #endif
mbed_official 146:f64d43ff0c18 876
mbed_official 146:f64d43ff0c18 877 /*!
mbed_official 146:f64d43ff0c18 878 * @name Constants and macros for entire PORT_DFWR register
mbed_official 146:f64d43ff0c18 879 */
mbed_official 146:f64d43ff0c18 880 //@{
mbed_official 146:f64d43ff0c18 881 #define HW_PORT_DFWR_ADDR(x) (REGS_PORT_BASE(x) + 0xC8U)
mbed_official 146:f64d43ff0c18 882
mbed_official 146:f64d43ff0c18 883 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 884 #define HW_PORT_DFWR(x) (*(__IO hw_port_dfwr_t *) HW_PORT_DFWR_ADDR(x))
mbed_official 146:f64d43ff0c18 885 #define HW_PORT_DFWR_RD(x) (HW_PORT_DFWR(x).U)
mbed_official 146:f64d43ff0c18 886 #define HW_PORT_DFWR_WR(x, v) (HW_PORT_DFWR(x).U = (v))
mbed_official 146:f64d43ff0c18 887 #define HW_PORT_DFWR_SET(x, v) (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 888 #define HW_PORT_DFWR_CLR(x, v) (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 889 #define HW_PORT_DFWR_TOG(x, v) (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 890 #endif
mbed_official 146:f64d43ff0c18 891 //@}
mbed_official 146:f64d43ff0c18 892
mbed_official 146:f64d43ff0c18 893 /*
mbed_official 146:f64d43ff0c18 894 * Constants & macros for individual PORT_DFWR bitfields
mbed_official 146:f64d43ff0c18 895 */
mbed_official 146:f64d43ff0c18 896
mbed_official 146:f64d43ff0c18 897 /*!
mbed_official 146:f64d43ff0c18 898 * @name Register PORT_DFWR, field FILT[4:0] (RW)
mbed_official 146:f64d43ff0c18 899 *
mbed_official 146:f64d43ff0c18 900 * The digital filter configuration is valid in all digital pin muxing modes.
mbed_official 146:f64d43ff0c18 901 * Configures the maximum size of the glitches, in clock cycles, that the digital
mbed_official 146:f64d43ff0c18 902 * filter absorbs for the enabled digital filters. Glitches that are longer than
mbed_official 146:f64d43ff0c18 903 * this register setting will pass through the digital filter, and glitches that
mbed_official 146:f64d43ff0c18 904 * are equal to or less than this register setting are filtered. Changing the
mbed_official 146:f64d43ff0c18 905 * filter length must be done only after all filters are disabled.
mbed_official 146:f64d43ff0c18 906 */
mbed_official 146:f64d43ff0c18 907 //@{
mbed_official 146:f64d43ff0c18 908 #define BP_PORT_DFWR_FILT (0U) //!< Bit position for PORT_DFWR_FILT.
mbed_official 146:f64d43ff0c18 909 #define BM_PORT_DFWR_FILT (0x0000001FU) //!< Bit mask for PORT_DFWR_FILT.
mbed_official 146:f64d43ff0c18 910 #define BS_PORT_DFWR_FILT (5U) //!< Bit field size in bits for PORT_DFWR_FILT.
mbed_official 146:f64d43ff0c18 911
mbed_official 146:f64d43ff0c18 912 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 913 //! @brief Read current value of the PORT_DFWR_FILT field.
mbed_official 146:f64d43ff0c18 914 #define BR_PORT_DFWR_FILT(x) (HW_PORT_DFWR(x).B.FILT)
mbed_official 146:f64d43ff0c18 915 #endif
mbed_official 146:f64d43ff0c18 916
mbed_official 146:f64d43ff0c18 917 //! @brief Format value for bitfield PORT_DFWR_FILT.
mbed_official 146:f64d43ff0c18 918 #define BF_PORT_DFWR_FILT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_DFWR_FILT), uint32_t) & BM_PORT_DFWR_FILT)
mbed_official 146:f64d43ff0c18 919
mbed_official 146:f64d43ff0c18 920 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 921 //! @brief Set the FILT field to a new value.
mbed_official 146:f64d43ff0c18 922 #define BW_PORT_DFWR_FILT(x, v) (HW_PORT_DFWR_WR(x, (HW_PORT_DFWR_RD(x) & ~BM_PORT_DFWR_FILT) | BF_PORT_DFWR_FILT(v)))
mbed_official 146:f64d43ff0c18 923 #endif
mbed_official 146:f64d43ff0c18 924 //@}
mbed_official 146:f64d43ff0c18 925
mbed_official 146:f64d43ff0c18 926 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 927 // hw_port_t - module struct
mbed_official 146:f64d43ff0c18 928 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 929 /*!
mbed_official 146:f64d43ff0c18 930 * @brief All PORT module registers.
mbed_official 146:f64d43ff0c18 931 */
mbed_official 146:f64d43ff0c18 932 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 933 #pragma pack(1)
mbed_official 146:f64d43ff0c18 934 typedef struct _hw_port
mbed_official 146:f64d43ff0c18 935 {
mbed_official 146:f64d43ff0c18 936 __IO hw_port_pcrn_t PCRn[32]; //!< [0x0] Pin Control Register n
mbed_official 146:f64d43ff0c18 937 __O hw_port_gpclr_t GPCLR; //!< [0x80] Global Pin Control Low Register
mbed_official 146:f64d43ff0c18 938 __O hw_port_gpchr_t GPCHR; //!< [0x84] Global Pin Control High Register
mbed_official 146:f64d43ff0c18 939 uint8_t _reserved0[24];
mbed_official 146:f64d43ff0c18 940 __IO hw_port_isfr_t ISFR; //!< [0xA0] Interrupt Status Flag Register
mbed_official 146:f64d43ff0c18 941 uint8_t _reserved1[28];
mbed_official 146:f64d43ff0c18 942 __IO hw_port_dfer_t DFER; //!< [0xC0] Digital Filter Enable Register
mbed_official 146:f64d43ff0c18 943 __IO hw_port_dfcr_t DFCR; //!< [0xC4] Digital Filter Clock Register
mbed_official 146:f64d43ff0c18 944 __IO hw_port_dfwr_t DFWR; //!< [0xC8] Digital Filter Width Register
mbed_official 146:f64d43ff0c18 945 } hw_port_t;
mbed_official 146:f64d43ff0c18 946 #pragma pack()
mbed_official 146:f64d43ff0c18 947
mbed_official 146:f64d43ff0c18 948 //! @brief Macro to access all PORT registers.
mbed_official 146:f64d43ff0c18 949 //! @param x PORT instance number.
mbed_official 146:f64d43ff0c18 950 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 146:f64d43ff0c18 951 //! use the '&' operator, like <code>&HW_PORT(0)</code>.
mbed_official 146:f64d43ff0c18 952 #define HW_PORT(x) (*(hw_port_t *) REGS_PORT_BASE(x))
mbed_official 146:f64d43ff0c18 953 #endif
mbed_official 146:f64d43ff0c18 954
mbed_official 146:f64d43ff0c18 955 #endif // __HW_PORT_REGISTERS_H__
mbed_official 146:f64d43ff0c18 956 // v22/130726/0.9
mbed_official 146:f64d43ff0c18 957 // EOF