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Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_mcm.h@149:1fb5f62b92bd, 2014-04-03 (annotated)

Committer:
mbed_official
Date:
Thu Apr 03 11:45:06 2014 +0100
Revision:
149:1fb5f62b92bd
Parent:
targets/hal/TARGET_Freescale/TARGET_KSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_mcm.h@146:f64d43ff0c18 
Synchronized with git revision 220c0bb39ceee40016e1e86350c058963d01ed42



Full URL: https://github.com/mbedmicro/mbed/commit/220c0bb39ceee40016e1e86350c058963d01ed42/

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /*
mbed_official 146:f64d43ff0c18 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
mbed_official 146:f64d43ff0c18 3 * All rights reserved.
mbed_official 146:f64d43ff0c18 4 *
mbed_official 146:f64d43ff0c18 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official 146:f64d43ff0c18 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official 146:f64d43ff0c18 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
mbed_official 146:f64d43ff0c18 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
mbed_official 146:f64d43ff0c18 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
mbed_official 146:f64d43ff0c18 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 146:f64d43ff0c18 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 146:f64d43ff0c18 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
mbed_official 146:f64d43ff0c18 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
mbed_official 146:f64d43ff0c18 14 * OF SUCH DAMAGE.
mbed_official 146:f64d43ff0c18 15 */
mbed_official 146:f64d43ff0c18 16 /*
mbed_official 146:f64d43ff0c18 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 146:f64d43ff0c18 18 *
mbed_official 146:f64d43ff0c18 19 * This file was generated automatically and any changes may be lost.
mbed_official 146:f64d43ff0c18 20 */
mbed_official 146:f64d43ff0c18 21 #ifndef __HW_MCM_REGISTERS_H__
mbed_official 146:f64d43ff0c18 22 #define __HW_MCM_REGISTERS_H__
mbed_official 146:f64d43ff0c18 23
mbed_official 146:f64d43ff0c18 24 #include "regs.h"
mbed_official 146:f64d43ff0c18 25
mbed_official 146:f64d43ff0c18 26 /*
mbed_official 146:f64d43ff0c18 27 * MK64F12 MCM
mbed_official 146:f64d43ff0c18 28 *
mbed_official 146:f64d43ff0c18 29 * Core Platform Miscellaneous Control Module
mbed_official 146:f64d43ff0c18 30 *
mbed_official 146:f64d43ff0c18 31 * Registers defined in this header file:
mbed_official 146:f64d43ff0c18 32 * - HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
mbed_official 146:f64d43ff0c18 33 * - HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
mbed_official 146:f64d43ff0c18 34 * - HW_MCM_CR - Control Register
mbed_official 146:f64d43ff0c18 35 * - HW_MCM_ISR - Interrupt Status Register
mbed_official 146:f64d43ff0c18 36 * - HW_MCM_ETBCC - ETB Counter Control register
mbed_official 146:f64d43ff0c18 37 * - HW_MCM_ETBRL - ETB Reload register
mbed_official 146:f64d43ff0c18 38 * - HW_MCM_ETBCNT - ETB Counter Value register
mbed_official 146:f64d43ff0c18 39 * - HW_MCM_PID - Process ID register
mbed_official 146:f64d43ff0c18 40 *
mbed_official 146:f64d43ff0c18 41 * - hw_mcm_t - Struct containing all module registers.
mbed_official 146:f64d43ff0c18 42 */
mbed_official 146:f64d43ff0c18 43
mbed_official 146:f64d43ff0c18 44 //! @name Module base addresses
mbed_official 146:f64d43ff0c18 45 //@{
mbed_official 146:f64d43ff0c18 46 #ifndef REGS_MCM_BASE
mbed_official 146:f64d43ff0c18 47 #define HW_MCM_INSTANCE_COUNT (1U) //!< Number of instances of the MCM module.
mbed_official 146:f64d43ff0c18 48 #define REGS_MCM_BASE (0xE0080000U) //!< Base address for MCM.
mbed_official 146:f64d43ff0c18 49 #endif
mbed_official 146:f64d43ff0c18 50 //@}
mbed_official 146:f64d43ff0c18 51
mbed_official 146:f64d43ff0c18 52 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 53 // HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
mbed_official 146:f64d43ff0c18 54 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 55
mbed_official 146:f64d43ff0c18 56 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 57 /*!
mbed_official 146:f64d43ff0c18 58 * @brief HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration (RO)
mbed_official 146:f64d43ff0c18 59 *
mbed_official 146:f64d43ff0c18 60 * Reset value: 0x001FU
mbed_official 146:f64d43ff0c18 61 *
mbed_official 146:f64d43ff0c18 62 * PLASC is a 16-bit read-only register identifying the presence/absence of bus
mbed_official 146:f64d43ff0c18 63 * slave connections to the device's crossbar switch.
mbed_official 146:f64d43ff0c18 64 */
mbed_official 146:f64d43ff0c18 65 typedef union _hw_mcm_plasc
mbed_official 146:f64d43ff0c18 66 {
mbed_official 146:f64d43ff0c18 67 uint16_t U;
mbed_official 146:f64d43ff0c18 68 struct _hw_mcm_plasc_bitfields
mbed_official 146:f64d43ff0c18 69 {
mbed_official 146:f64d43ff0c18 70 uint16_t ASC : 8; //!< [7:0] Each bit in the ASC field indicates
mbed_official 146:f64d43ff0c18 71 //! whether there is a corresponding connection to the crossbar switch's slave
mbed_official 146:f64d43ff0c18 72 //! input port.
mbed_official 146:f64d43ff0c18 73 uint16_t RESERVED0 : 8; //!< [15:8]
mbed_official 146:f64d43ff0c18 74 } B;
mbed_official 146:f64d43ff0c18 75 } hw_mcm_plasc_t;
mbed_official 146:f64d43ff0c18 76 #endif
mbed_official 146:f64d43ff0c18 77
mbed_official 146:f64d43ff0c18 78 /*!
mbed_official 146:f64d43ff0c18 79 * @name Constants and macros for entire MCM_PLASC register
mbed_official 146:f64d43ff0c18 80 */
mbed_official 146:f64d43ff0c18 81 //@{
mbed_official 146:f64d43ff0c18 82 #define HW_MCM_PLASC_ADDR (REGS_MCM_BASE + 0x8U)
mbed_official 146:f64d43ff0c18 83
mbed_official 146:f64d43ff0c18 84 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 85 #define HW_MCM_PLASC (*(__I hw_mcm_plasc_t *) HW_MCM_PLASC_ADDR)
mbed_official 146:f64d43ff0c18 86 #define HW_MCM_PLASC_RD() (HW_MCM_PLASC.U)
mbed_official 146:f64d43ff0c18 87 #endif
mbed_official 146:f64d43ff0c18 88 //@}
mbed_official 146:f64d43ff0c18 89
mbed_official 146:f64d43ff0c18 90 /*
mbed_official 146:f64d43ff0c18 91 * Constants & macros for individual MCM_PLASC bitfields
mbed_official 146:f64d43ff0c18 92 */
mbed_official 146:f64d43ff0c18 93
mbed_official 146:f64d43ff0c18 94 /*!
mbed_official 146:f64d43ff0c18 95 * @name Register MCM_PLASC, field ASC[7:0] (RO)
mbed_official 146:f64d43ff0c18 96 *
mbed_official 146:f64d43ff0c18 97 * Values:
mbed_official 146:f64d43ff0c18 98 * - 0 - A bus slave connection to AXBS input port n is absent
mbed_official 146:f64d43ff0c18 99 * - 1 - A bus slave connection to AXBS input port n is present
mbed_official 146:f64d43ff0c18 100 */
mbed_official 146:f64d43ff0c18 101 //@{
mbed_official 146:f64d43ff0c18 102 #define BP_MCM_PLASC_ASC (0U) //!< Bit position for MCM_PLASC_ASC.
mbed_official 146:f64d43ff0c18 103 #define BM_MCM_PLASC_ASC (0x00FFU) //!< Bit mask for MCM_PLASC_ASC.
mbed_official 146:f64d43ff0c18 104 #define BS_MCM_PLASC_ASC (8U) //!< Bit field size in bits for MCM_PLASC_ASC.
mbed_official 146:f64d43ff0c18 105
mbed_official 146:f64d43ff0c18 106 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 107 //! @brief Read current value of the MCM_PLASC_ASC field.
mbed_official 146:f64d43ff0c18 108 #define BR_MCM_PLASC_ASC (HW_MCM_PLASC.B.ASC)
mbed_official 146:f64d43ff0c18 109 #endif
mbed_official 146:f64d43ff0c18 110 //@}
mbed_official 146:f64d43ff0c18 111
mbed_official 146:f64d43ff0c18 112 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 113 // HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
mbed_official 146:f64d43ff0c18 114 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 115
mbed_official 146:f64d43ff0c18 116 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 117 /*!
mbed_official 146:f64d43ff0c18 118 * @brief HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration (RO)
mbed_official 146:f64d43ff0c18 119 *
mbed_official 146:f64d43ff0c18 120 * Reset value: 0x0037U
mbed_official 146:f64d43ff0c18 121 *
mbed_official 146:f64d43ff0c18 122 * PLAMC is a 16-bit read-only register identifying the presence/absence of bus
mbed_official 146:f64d43ff0c18 123 * master connections to the device's crossbar switch.
mbed_official 146:f64d43ff0c18 124 */
mbed_official 146:f64d43ff0c18 125 typedef union _hw_mcm_plamc
mbed_official 146:f64d43ff0c18 126 {
mbed_official 146:f64d43ff0c18 127 uint16_t U;
mbed_official 146:f64d43ff0c18 128 struct _hw_mcm_plamc_bitfields
mbed_official 146:f64d43ff0c18 129 {
mbed_official 146:f64d43ff0c18 130 uint16_t AMC : 8; //!< [7:0] Each bit in the AMC field indicates
mbed_official 146:f64d43ff0c18 131 //! whether there is a corresponding connection to the AXBS master input port.
mbed_official 146:f64d43ff0c18 132 uint16_t RESERVED0 : 8; //!< [15:8]
mbed_official 146:f64d43ff0c18 133 } B;
mbed_official 146:f64d43ff0c18 134 } hw_mcm_plamc_t;
mbed_official 146:f64d43ff0c18 135 #endif
mbed_official 146:f64d43ff0c18 136
mbed_official 146:f64d43ff0c18 137 /*!
mbed_official 146:f64d43ff0c18 138 * @name Constants and macros for entire MCM_PLAMC register
mbed_official 146:f64d43ff0c18 139 */
mbed_official 146:f64d43ff0c18 140 //@{
mbed_official 146:f64d43ff0c18 141 #define HW_MCM_PLAMC_ADDR (REGS_MCM_BASE + 0xAU)
mbed_official 146:f64d43ff0c18 142
mbed_official 146:f64d43ff0c18 143 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 144 #define HW_MCM_PLAMC (*(__I hw_mcm_plamc_t *) HW_MCM_PLAMC_ADDR)
mbed_official 146:f64d43ff0c18 145 #define HW_MCM_PLAMC_RD() (HW_MCM_PLAMC.U)
mbed_official 146:f64d43ff0c18 146 #endif
mbed_official 146:f64d43ff0c18 147 //@}
mbed_official 146:f64d43ff0c18 148
mbed_official 146:f64d43ff0c18 149 /*
mbed_official 146:f64d43ff0c18 150 * Constants & macros for individual MCM_PLAMC bitfields
mbed_official 146:f64d43ff0c18 151 */
mbed_official 146:f64d43ff0c18 152
mbed_official 146:f64d43ff0c18 153 /*!
mbed_official 146:f64d43ff0c18 154 * @name Register MCM_PLAMC, field AMC[7:0] (RO)
mbed_official 146:f64d43ff0c18 155 *
mbed_official 146:f64d43ff0c18 156 * Values:
mbed_official 146:f64d43ff0c18 157 * - 0 - A bus master connection to AXBS input port n is absent
mbed_official 146:f64d43ff0c18 158 * - 1 - A bus master connection to AXBS input port n is present
mbed_official 146:f64d43ff0c18 159 */
mbed_official 146:f64d43ff0c18 160 //@{
mbed_official 146:f64d43ff0c18 161 #define BP_MCM_PLAMC_AMC (0U) //!< Bit position for MCM_PLAMC_AMC.
mbed_official 146:f64d43ff0c18 162 #define BM_MCM_PLAMC_AMC (0x00FFU) //!< Bit mask for MCM_PLAMC_AMC.
mbed_official 146:f64d43ff0c18 163 #define BS_MCM_PLAMC_AMC (8U) //!< Bit field size in bits for MCM_PLAMC_AMC.
mbed_official 146:f64d43ff0c18 164
mbed_official 146:f64d43ff0c18 165 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 166 //! @brief Read current value of the MCM_PLAMC_AMC field.
mbed_official 146:f64d43ff0c18 167 #define BR_MCM_PLAMC_AMC (HW_MCM_PLAMC.B.AMC)
mbed_official 146:f64d43ff0c18 168 #endif
mbed_official 146:f64d43ff0c18 169 //@}
mbed_official 146:f64d43ff0c18 170
mbed_official 146:f64d43ff0c18 171 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 172 // HW_MCM_CR - Control Register
mbed_official 146:f64d43ff0c18 173 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 174
mbed_official 146:f64d43ff0c18 175 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 176 /*!
mbed_official 146:f64d43ff0c18 177 * @brief HW_MCM_CR - Control Register (RW)
mbed_official 146:f64d43ff0c18 178 *
mbed_official 146:f64d43ff0c18 179 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 180 *
mbed_official 146:f64d43ff0c18 181 * CR defines the arbitration and protection schemes for the two system RAM
mbed_official 146:f64d43ff0c18 182 * arrays.
mbed_official 146:f64d43ff0c18 183 */
mbed_official 146:f64d43ff0c18 184 typedef union _hw_mcm_cr
mbed_official 146:f64d43ff0c18 185 {
mbed_official 146:f64d43ff0c18 186 uint32_t U;
mbed_official 146:f64d43ff0c18 187 struct _hw_mcm_cr_bitfields
mbed_official 146:f64d43ff0c18 188 {
mbed_official 146:f64d43ff0c18 189 uint32_t RESERVED0 : 24; //!< [23:0]
mbed_official 146:f64d43ff0c18 190 uint32_t SRAMUAP : 2; //!< [25:24] SRAM_U arbitration priority
mbed_official 146:f64d43ff0c18 191 uint32_t SRAMUWP : 1; //!< [26] SRAM_U write protect
mbed_official 146:f64d43ff0c18 192 uint32_t RESERVED1 : 1; //!< [27]
mbed_official 146:f64d43ff0c18 193 uint32_t SRAMLAP : 2; //!< [29:28] SRAM_L arbitration priority
mbed_official 146:f64d43ff0c18 194 uint32_t SRAMLWP : 1; //!< [30] SRAM_L Write Protect
mbed_official 146:f64d43ff0c18 195 uint32_t RESERVED2 : 1; //!< [31]
mbed_official 146:f64d43ff0c18 196 } B;
mbed_official 146:f64d43ff0c18 197 } hw_mcm_cr_t;
mbed_official 146:f64d43ff0c18 198 #endif
mbed_official 146:f64d43ff0c18 199
mbed_official 146:f64d43ff0c18 200 /*!
mbed_official 146:f64d43ff0c18 201 * @name Constants and macros for entire MCM_CR register
mbed_official 146:f64d43ff0c18 202 */
mbed_official 146:f64d43ff0c18 203 //@{
mbed_official 146:f64d43ff0c18 204 #define HW_MCM_CR_ADDR (REGS_MCM_BASE + 0xCU)
mbed_official 146:f64d43ff0c18 205
mbed_official 146:f64d43ff0c18 206 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 207 #define HW_MCM_CR (*(__IO hw_mcm_cr_t *) HW_MCM_CR_ADDR)
mbed_official 146:f64d43ff0c18 208 #define HW_MCM_CR_RD() (HW_MCM_CR.U)
mbed_official 146:f64d43ff0c18 209 #define HW_MCM_CR_WR(v) (HW_MCM_CR.U = (v))
mbed_official 146:f64d43ff0c18 210 #define HW_MCM_CR_SET(v) (HW_MCM_CR_WR(HW_MCM_CR_RD() | (v)))
mbed_official 146:f64d43ff0c18 211 #define HW_MCM_CR_CLR(v) (HW_MCM_CR_WR(HW_MCM_CR_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 212 #define HW_MCM_CR_TOG(v) (HW_MCM_CR_WR(HW_MCM_CR_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 213 #endif
mbed_official 146:f64d43ff0c18 214 //@}
mbed_official 146:f64d43ff0c18 215
mbed_official 146:f64d43ff0c18 216 /*
mbed_official 146:f64d43ff0c18 217 * Constants & macros for individual MCM_CR bitfields
mbed_official 146:f64d43ff0c18 218 */
mbed_official 146:f64d43ff0c18 219
mbed_official 146:f64d43ff0c18 220 /*!
mbed_official 146:f64d43ff0c18 221 * @name Register MCM_CR, field SRAMUAP[25:24] (RW)
mbed_official 146:f64d43ff0c18 222 *
mbed_official 146:f64d43ff0c18 223 * Defines the arbitration scheme and priority for the processor and SRAM
mbed_official 146:f64d43ff0c18 224 * backdoor accesses to the SRAM_U array.
mbed_official 146:f64d43ff0c18 225 *
mbed_official 146:f64d43ff0c18 226 * Values:
mbed_official 146:f64d43ff0c18 227 * - 00 - Round robin
mbed_official 146:f64d43ff0c18 228 * - 01 - Special round robin (favors SRAM backoor accesses over the processor)
mbed_official 146:f64d43ff0c18 229 * - 10 - Fixed priority. Processor has highest, backdoor has lowest
mbed_official 146:f64d43ff0c18 230 * - 11 - Fixed priority. Backdoor has highest, processor has lowest
mbed_official 146:f64d43ff0c18 231 */
mbed_official 146:f64d43ff0c18 232 //@{
mbed_official 146:f64d43ff0c18 233 #define BP_MCM_CR_SRAMUAP (24U) //!< Bit position for MCM_CR_SRAMUAP.
mbed_official 146:f64d43ff0c18 234 #define BM_MCM_CR_SRAMUAP (0x03000000U) //!< Bit mask for MCM_CR_SRAMUAP.
mbed_official 146:f64d43ff0c18 235 #define BS_MCM_CR_SRAMUAP (2U) //!< Bit field size in bits for MCM_CR_SRAMUAP.
mbed_official 146:f64d43ff0c18 236
mbed_official 146:f64d43ff0c18 237 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 238 //! @brief Read current value of the MCM_CR_SRAMUAP field.
mbed_official 146:f64d43ff0c18 239 #define BR_MCM_CR_SRAMUAP (HW_MCM_CR.B.SRAMUAP)
mbed_official 146:f64d43ff0c18 240 #endif
mbed_official 146:f64d43ff0c18 241
mbed_official 146:f64d43ff0c18 242 //! @brief Format value for bitfield MCM_CR_SRAMUAP.
mbed_official 146:f64d43ff0c18 243 #define BF_MCM_CR_SRAMUAP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_CR_SRAMUAP), uint32_t) & BM_MCM_CR_SRAMUAP)
mbed_official 146:f64d43ff0c18 244
mbed_official 146:f64d43ff0c18 245 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 246 //! @brief Set the SRAMUAP field to a new value.
mbed_official 146:f64d43ff0c18 247 #define BW_MCM_CR_SRAMUAP(v) (HW_MCM_CR_WR((HW_MCM_CR_RD() & ~BM_MCM_CR_SRAMUAP) | BF_MCM_CR_SRAMUAP(v)))
mbed_official 146:f64d43ff0c18 248 #endif
mbed_official 146:f64d43ff0c18 249 //@}
mbed_official 146:f64d43ff0c18 250
mbed_official 146:f64d43ff0c18 251 /*!
mbed_official 146:f64d43ff0c18 252 * @name Register MCM_CR, field SRAMUWP[26] (RW)
mbed_official 146:f64d43ff0c18 253 *
mbed_official 146:f64d43ff0c18 254 * When this bit is set, writes to SRAM_U array generates a bus error.
mbed_official 146:f64d43ff0c18 255 */
mbed_official 146:f64d43ff0c18 256 //@{
mbed_official 146:f64d43ff0c18 257 #define BP_MCM_CR_SRAMUWP (26U) //!< Bit position for MCM_CR_SRAMUWP.
mbed_official 146:f64d43ff0c18 258 #define BM_MCM_CR_SRAMUWP (0x04000000U) //!< Bit mask for MCM_CR_SRAMUWP.
mbed_official 146:f64d43ff0c18 259 #define BS_MCM_CR_SRAMUWP (1U) //!< Bit field size in bits for MCM_CR_SRAMUWP.
mbed_official 146:f64d43ff0c18 260
mbed_official 146:f64d43ff0c18 261 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 262 //! @brief Read current value of the MCM_CR_SRAMUWP field.
mbed_official 146:f64d43ff0c18 263 #define BR_MCM_CR_SRAMUWP (BITBAND_ACCESS32(HW_MCM_CR_ADDR, BP_MCM_CR_SRAMUWP))
mbed_official 146:f64d43ff0c18 264 #endif
mbed_official 146:f64d43ff0c18 265
mbed_official 146:f64d43ff0c18 266 //! @brief Format value for bitfield MCM_CR_SRAMUWP.
mbed_official 146:f64d43ff0c18 267 #define BF_MCM_CR_SRAMUWP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_CR_SRAMUWP), uint32_t) & BM_MCM_CR_SRAMUWP)
mbed_official 146:f64d43ff0c18 268
mbed_official 146:f64d43ff0c18 269 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 270 //! @brief Set the SRAMUWP field to a new value.
mbed_official 146:f64d43ff0c18 271 #define BW_MCM_CR_SRAMUWP(v) (BITBAND_ACCESS32(HW_MCM_CR_ADDR, BP_MCM_CR_SRAMUWP) = (v))
mbed_official 146:f64d43ff0c18 272 #endif
mbed_official 146:f64d43ff0c18 273 //@}
mbed_official 146:f64d43ff0c18 274
mbed_official 146:f64d43ff0c18 275 /*!
mbed_official 146:f64d43ff0c18 276 * @name Register MCM_CR, field SRAMLAP[29:28] (RW)
mbed_official 146:f64d43ff0c18 277 *
mbed_official 146:f64d43ff0c18 278 * Defines the arbitration scheme and priority for the processor and SRAM
mbed_official 146:f64d43ff0c18 279 * backdoor accesses to the SRAM_L array.
mbed_official 146:f64d43ff0c18 280 *
mbed_official 146:f64d43ff0c18 281 * Values:
mbed_official 146:f64d43ff0c18 282 * - 00 - Round robin
mbed_official 146:f64d43ff0c18 283 * - 01 - Special round robin (favors SRAM backoor accesses over the processor)
mbed_official 146:f64d43ff0c18 284 * - 10 - Fixed priority. Processor has highest, backdoor has lowest
mbed_official 146:f64d43ff0c18 285 * - 11 - Fixed priority. Backdoor has highest, processor has lowest
mbed_official 146:f64d43ff0c18 286 */
mbed_official 146:f64d43ff0c18 287 //@{
mbed_official 146:f64d43ff0c18 288 #define BP_MCM_CR_SRAMLAP (28U) //!< Bit position for MCM_CR_SRAMLAP.
mbed_official 146:f64d43ff0c18 289 #define BM_MCM_CR_SRAMLAP (0x30000000U) //!< Bit mask for MCM_CR_SRAMLAP.
mbed_official 146:f64d43ff0c18 290 #define BS_MCM_CR_SRAMLAP (2U) //!< Bit field size in bits for MCM_CR_SRAMLAP.
mbed_official 146:f64d43ff0c18 291
mbed_official 146:f64d43ff0c18 292 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 293 //! @brief Read current value of the MCM_CR_SRAMLAP field.
mbed_official 146:f64d43ff0c18 294 #define BR_MCM_CR_SRAMLAP (HW_MCM_CR.B.SRAMLAP)
mbed_official 146:f64d43ff0c18 295 #endif
mbed_official 146:f64d43ff0c18 296
mbed_official 146:f64d43ff0c18 297 //! @brief Format value for bitfield MCM_CR_SRAMLAP.
mbed_official 146:f64d43ff0c18 298 #define BF_MCM_CR_SRAMLAP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_CR_SRAMLAP), uint32_t) & BM_MCM_CR_SRAMLAP)
mbed_official 146:f64d43ff0c18 299
mbed_official 146:f64d43ff0c18 300 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 301 //! @brief Set the SRAMLAP field to a new value.
mbed_official 146:f64d43ff0c18 302 #define BW_MCM_CR_SRAMLAP(v) (HW_MCM_CR_WR((HW_MCM_CR_RD() & ~BM_MCM_CR_SRAMLAP) | BF_MCM_CR_SRAMLAP(v)))
mbed_official 146:f64d43ff0c18 303 #endif
mbed_official 146:f64d43ff0c18 304 //@}
mbed_official 146:f64d43ff0c18 305
mbed_official 146:f64d43ff0c18 306 /*!
mbed_official 146:f64d43ff0c18 307 * @name Register MCM_CR, field SRAMLWP[30] (RW)
mbed_official 146:f64d43ff0c18 308 *
mbed_official 146:f64d43ff0c18 309 * When this bit is set, writes to SRAM_L array generates a bus error.
mbed_official 146:f64d43ff0c18 310 */
mbed_official 146:f64d43ff0c18 311 //@{
mbed_official 146:f64d43ff0c18 312 #define BP_MCM_CR_SRAMLWP (30U) //!< Bit position for MCM_CR_SRAMLWP.
mbed_official 146:f64d43ff0c18 313 #define BM_MCM_CR_SRAMLWP (0x40000000U) //!< Bit mask for MCM_CR_SRAMLWP.
mbed_official 146:f64d43ff0c18 314 #define BS_MCM_CR_SRAMLWP (1U) //!< Bit field size in bits for MCM_CR_SRAMLWP.
mbed_official 146:f64d43ff0c18 315
mbed_official 146:f64d43ff0c18 316 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 317 //! @brief Read current value of the MCM_CR_SRAMLWP field.
mbed_official 146:f64d43ff0c18 318 #define BR_MCM_CR_SRAMLWP (BITBAND_ACCESS32(HW_MCM_CR_ADDR, BP_MCM_CR_SRAMLWP))
mbed_official 146:f64d43ff0c18 319 #endif
mbed_official 146:f64d43ff0c18 320
mbed_official 146:f64d43ff0c18 321 //! @brief Format value for bitfield MCM_CR_SRAMLWP.
mbed_official 146:f64d43ff0c18 322 #define BF_MCM_CR_SRAMLWP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_CR_SRAMLWP), uint32_t) & BM_MCM_CR_SRAMLWP)
mbed_official 146:f64d43ff0c18 323
mbed_official 146:f64d43ff0c18 324 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 325 //! @brief Set the SRAMLWP field to a new value.
mbed_official 146:f64d43ff0c18 326 #define BW_MCM_CR_SRAMLWP(v) (BITBAND_ACCESS32(HW_MCM_CR_ADDR, BP_MCM_CR_SRAMLWP) = (v))
mbed_official 146:f64d43ff0c18 327 #endif
mbed_official 146:f64d43ff0c18 328 //@}
mbed_official 146:f64d43ff0c18 329
mbed_official 146:f64d43ff0c18 330 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 331 // HW_MCM_ISR - Interrupt Status Register
mbed_official 146:f64d43ff0c18 332 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 333
mbed_official 146:f64d43ff0c18 334 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 335 /*!
mbed_official 146:f64d43ff0c18 336 * @brief HW_MCM_ISR - Interrupt Status Register (RW)
mbed_official 146:f64d43ff0c18 337 *
mbed_official 146:f64d43ff0c18 338 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 339 */
mbed_official 146:f64d43ff0c18 340 typedef union _hw_mcm_isr
mbed_official 146:f64d43ff0c18 341 {
mbed_official 146:f64d43ff0c18 342 uint32_t U;
mbed_official 146:f64d43ff0c18 343 struct _hw_mcm_isr_bitfields
mbed_official 146:f64d43ff0c18 344 {
mbed_official 146:f64d43ff0c18 345 uint32_t RESERVED0 : 1; //!< [0]
mbed_official 146:f64d43ff0c18 346 uint32_t IRQ : 1; //!< [1] Normal Interrupt Pending
mbed_official 146:f64d43ff0c18 347 uint32_t NMI : 1; //!< [2] Non-maskable Interrupt Pending
mbed_official 146:f64d43ff0c18 348 uint32_t DHREQ : 1; //!< [3] Debug Halt Request Indicator
mbed_official 146:f64d43ff0c18 349 uint32_t RESERVED1 : 4; //!< [7:4]
mbed_official 146:f64d43ff0c18 350 uint32_t FIOC : 1; //!< [8] FPU invalid operation interrupt status
mbed_official 146:f64d43ff0c18 351 uint32_t FDZC : 1; //!< [9] FPU divide-by-zero interrupt status
mbed_official 146:f64d43ff0c18 352 uint32_t FOFC : 1; //!< [10] FPU overflow interrupt status
mbed_official 146:f64d43ff0c18 353 uint32_t FUFC : 1; //!< [11] FPU underflow interrupt status
mbed_official 146:f64d43ff0c18 354 uint32_t FIXC : 1; //!< [12] FPU inexact interrupt status
mbed_official 146:f64d43ff0c18 355 uint32_t RESERVED2 : 2; //!< [14:13]
mbed_official 146:f64d43ff0c18 356 uint32_t FIDC : 1; //!< [15] FPU input denormal interrupt status
mbed_official 146:f64d43ff0c18 357 uint32_t RESERVED3 : 8; //!< [23:16]
mbed_official 146:f64d43ff0c18 358 uint32_t FIOCE : 1; //!< [24] FPU invalid operation interrupt enable
mbed_official 146:f64d43ff0c18 359 uint32_t FDZCE : 1; //!< [25] FPU divide-by-zero interrupt enable
mbed_official 146:f64d43ff0c18 360 uint32_t FOFCE : 1; //!< [26] FPU overflow interrupt enable
mbed_official 146:f64d43ff0c18 361 uint32_t FUFCE : 1; //!< [27] FPU underflow interrupt enable
mbed_official 146:f64d43ff0c18 362 uint32_t FIXCE : 1; //!< [28] FPU inexact interrupt enable
mbed_official 146:f64d43ff0c18 363 uint32_t RESERVED4 : 2; //!< [30:29]
mbed_official 146:f64d43ff0c18 364 uint32_t FIDCE : 1; //!< [31] FPU input denormal interrupt enable
mbed_official 146:f64d43ff0c18 365 } B;
mbed_official 146:f64d43ff0c18 366 } hw_mcm_isr_t;
mbed_official 146:f64d43ff0c18 367 #endif
mbed_official 146:f64d43ff0c18 368
mbed_official 146:f64d43ff0c18 369 /*!
mbed_official 146:f64d43ff0c18 370 * @name Constants and macros for entire MCM_ISR register
mbed_official 146:f64d43ff0c18 371 */
mbed_official 146:f64d43ff0c18 372 //@{
mbed_official 146:f64d43ff0c18 373 #define HW_MCM_ISR_ADDR (REGS_MCM_BASE + 0x10U)
mbed_official 146:f64d43ff0c18 374
mbed_official 146:f64d43ff0c18 375 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 376 #define HW_MCM_ISR (*(__IO hw_mcm_isr_t *) HW_MCM_ISR_ADDR)
mbed_official 146:f64d43ff0c18 377 #define HW_MCM_ISR_RD() (HW_MCM_ISR.U)
mbed_official 146:f64d43ff0c18 378 #define HW_MCM_ISR_WR(v) (HW_MCM_ISR.U = (v))
mbed_official 146:f64d43ff0c18 379 #define HW_MCM_ISR_SET(v) (HW_MCM_ISR_WR(HW_MCM_ISR_RD() | (v)))
mbed_official 146:f64d43ff0c18 380 #define HW_MCM_ISR_CLR(v) (HW_MCM_ISR_WR(HW_MCM_ISR_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 381 #define HW_MCM_ISR_TOG(v) (HW_MCM_ISR_WR(HW_MCM_ISR_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 382 #endif
mbed_official 146:f64d43ff0c18 383 //@}
mbed_official 146:f64d43ff0c18 384
mbed_official 146:f64d43ff0c18 385 /*
mbed_official 146:f64d43ff0c18 386 * Constants & macros for individual MCM_ISR bitfields
mbed_official 146:f64d43ff0c18 387 */
mbed_official 146:f64d43ff0c18 388
mbed_official 146:f64d43ff0c18 389 /*!
mbed_official 146:f64d43ff0c18 390 * @name Register MCM_ISR, field IRQ[1] (W1C)
mbed_official 146:f64d43ff0c18 391 *
mbed_official 146:f64d43ff0c18 392 * If ETBCC[RSPT] is set to 01b, this bit is set when the ETB counter expires.
mbed_official 146:f64d43ff0c18 393 *
mbed_official 146:f64d43ff0c18 394 * Values:
mbed_official 146:f64d43ff0c18 395 * - 0 - No pending interrupt
mbed_official 146:f64d43ff0c18 396 * - 1 - Due to the ETB counter expiring, a normal interrupt is pending
mbed_official 146:f64d43ff0c18 397 */
mbed_official 146:f64d43ff0c18 398 //@{
mbed_official 146:f64d43ff0c18 399 #define BP_MCM_ISR_IRQ (1U) //!< Bit position for MCM_ISR_IRQ.
mbed_official 146:f64d43ff0c18 400 #define BM_MCM_ISR_IRQ (0x00000002U) //!< Bit mask for MCM_ISR_IRQ.
mbed_official 146:f64d43ff0c18 401 #define BS_MCM_ISR_IRQ (1U) //!< Bit field size in bits for MCM_ISR_IRQ.
mbed_official 146:f64d43ff0c18 402
mbed_official 146:f64d43ff0c18 403 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 404 //! @brief Read current value of the MCM_ISR_IRQ field.
mbed_official 146:f64d43ff0c18 405 #define BR_MCM_ISR_IRQ (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_IRQ))
mbed_official 146:f64d43ff0c18 406 #endif
mbed_official 146:f64d43ff0c18 407
mbed_official 146:f64d43ff0c18 408 //! @brief Format value for bitfield MCM_ISR_IRQ.
mbed_official 146:f64d43ff0c18 409 #define BF_MCM_ISR_IRQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_IRQ), uint32_t) & BM_MCM_ISR_IRQ)
mbed_official 146:f64d43ff0c18 410
mbed_official 146:f64d43ff0c18 411 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 412 //! @brief Set the IRQ field to a new value.
mbed_official 146:f64d43ff0c18 413 #define BW_MCM_ISR_IRQ(v) (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_IRQ) = (v))
mbed_official 146:f64d43ff0c18 414 #endif
mbed_official 146:f64d43ff0c18 415 //@}
mbed_official 146:f64d43ff0c18 416
mbed_official 146:f64d43ff0c18 417 /*!
mbed_official 146:f64d43ff0c18 418 * @name Register MCM_ISR, field NMI[2] (W1C)
mbed_official 146:f64d43ff0c18 419 *
mbed_official 146:f64d43ff0c18 420 * If ETBCC[RSPT] is set to 10b, this bit is set when the ETB counter expires.
mbed_official 146:f64d43ff0c18 421 *
mbed_official 146:f64d43ff0c18 422 * Values:
mbed_official 146:f64d43ff0c18 423 * - 0 - No pending NMI
mbed_official 146:f64d43ff0c18 424 * - 1 - Due to the ETB counter expiring, an NMI is pending
mbed_official 146:f64d43ff0c18 425 */
mbed_official 146:f64d43ff0c18 426 //@{
mbed_official 146:f64d43ff0c18 427 #define BP_MCM_ISR_NMI (2U) //!< Bit position for MCM_ISR_NMI.
mbed_official 146:f64d43ff0c18 428 #define BM_MCM_ISR_NMI (0x00000004U) //!< Bit mask for MCM_ISR_NMI.
mbed_official 146:f64d43ff0c18 429 #define BS_MCM_ISR_NMI (1U) //!< Bit field size in bits for MCM_ISR_NMI.
mbed_official 146:f64d43ff0c18 430
mbed_official 146:f64d43ff0c18 431 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 432 //! @brief Read current value of the MCM_ISR_NMI field.
mbed_official 146:f64d43ff0c18 433 #define BR_MCM_ISR_NMI (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_NMI))
mbed_official 146:f64d43ff0c18 434 #endif
mbed_official 146:f64d43ff0c18 435
mbed_official 146:f64d43ff0c18 436 //! @brief Format value for bitfield MCM_ISR_NMI.
mbed_official 146:f64d43ff0c18 437 #define BF_MCM_ISR_NMI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_NMI), uint32_t) & BM_MCM_ISR_NMI)
mbed_official 146:f64d43ff0c18 438
mbed_official 146:f64d43ff0c18 439 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 440 //! @brief Set the NMI field to a new value.
mbed_official 146:f64d43ff0c18 441 #define BW_MCM_ISR_NMI(v) (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_NMI) = (v))
mbed_official 146:f64d43ff0c18 442 #endif
mbed_official 146:f64d43ff0c18 443 //@}
mbed_official 146:f64d43ff0c18 444
mbed_official 146:f64d43ff0c18 445 /*!
mbed_official 146:f64d43ff0c18 446 * @name Register MCM_ISR, field DHREQ[3] (RO)
mbed_official 146:f64d43ff0c18 447 *
mbed_official 146:f64d43ff0c18 448 * Indicates that a debug halt request is initiated due to a ETB counter
mbed_official 146:f64d43ff0c18 449 * expiration, ETBCC[2:0] = 3b111 & ETBCV[10:0] = 11h0. This bit is cleared when the
mbed_official 146:f64d43ff0c18 450 * counter is disabled or when the ETB counter is reloaded.
mbed_official 146:f64d43ff0c18 451 *
mbed_official 146:f64d43ff0c18 452 * Values:
mbed_official 146:f64d43ff0c18 453 * - 0 - No debug halt request
mbed_official 146:f64d43ff0c18 454 * - 1 - Debug halt request initiated
mbed_official 146:f64d43ff0c18 455 */
mbed_official 146:f64d43ff0c18 456 //@{
mbed_official 146:f64d43ff0c18 457 #define BP_MCM_ISR_DHREQ (3U) //!< Bit position for MCM_ISR_DHREQ.
mbed_official 146:f64d43ff0c18 458 #define BM_MCM_ISR_DHREQ (0x00000008U) //!< Bit mask for MCM_ISR_DHREQ.
mbed_official 146:f64d43ff0c18 459 #define BS_MCM_ISR_DHREQ (1U) //!< Bit field size in bits for MCM_ISR_DHREQ.
mbed_official 146:f64d43ff0c18 460
mbed_official 146:f64d43ff0c18 461 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 462 //! @brief Read current value of the MCM_ISR_DHREQ field.
mbed_official 146:f64d43ff0c18 463 #define BR_MCM_ISR_DHREQ (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_DHREQ))
mbed_official 146:f64d43ff0c18 464 #endif
mbed_official 146:f64d43ff0c18 465 //@}
mbed_official 146:f64d43ff0c18 466
mbed_official 146:f64d43ff0c18 467 /*!
mbed_official 146:f64d43ff0c18 468 * @name Register MCM_ISR, field FIOC[8] (RO)
mbed_official 146:f64d43ff0c18 469 *
mbed_official 146:f64d43ff0c18 470 * This read-only bit is a copy of the core's FPSCR[IOC] bit and signals an
mbed_official 146:f64d43ff0c18 471 * illegal operation has been detected in the processor's FPU. Once set, this bit
mbed_official 146:f64d43ff0c18 472 * remains set until software clears the FPSCR[IOC] bit.
mbed_official 146:f64d43ff0c18 473 *
mbed_official 146:f64d43ff0c18 474 * Values:
mbed_official 146:f64d43ff0c18 475 * - 0 - No interrupt
mbed_official 146:f64d43ff0c18 476 * - 1 - Interrupt occurred
mbed_official 146:f64d43ff0c18 477 */
mbed_official 146:f64d43ff0c18 478 //@{
mbed_official 146:f64d43ff0c18 479 #define BP_MCM_ISR_FIOC (8U) //!< Bit position for MCM_ISR_FIOC.
mbed_official 146:f64d43ff0c18 480 #define BM_MCM_ISR_FIOC (0x00000100U) //!< Bit mask for MCM_ISR_FIOC.
mbed_official 146:f64d43ff0c18 481 #define BS_MCM_ISR_FIOC (1U) //!< Bit field size in bits for MCM_ISR_FIOC.
mbed_official 146:f64d43ff0c18 482
mbed_official 146:f64d43ff0c18 483 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 484 //! @brief Read current value of the MCM_ISR_FIOC field.
mbed_official 146:f64d43ff0c18 485 #define BR_MCM_ISR_FIOC (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIOC))
mbed_official 146:f64d43ff0c18 486 #endif
mbed_official 146:f64d43ff0c18 487 //@}
mbed_official 146:f64d43ff0c18 488
mbed_official 146:f64d43ff0c18 489 /*!
mbed_official 146:f64d43ff0c18 490 * @name Register MCM_ISR, field FDZC[9] (RO)
mbed_official 146:f64d43ff0c18 491 *
mbed_official 146:f64d43ff0c18 492 * This read-only bit is a copy of the core's FPSCR[DZC] bit and signals a
mbed_official 146:f64d43ff0c18 493 * divide by zero has been detected in the processor's FPU. Once set, this bit remains
mbed_official 146:f64d43ff0c18 494 * set until software clears the FPSCR[DZC] bit.
mbed_official 146:f64d43ff0c18 495 *
mbed_official 146:f64d43ff0c18 496 * Values:
mbed_official 146:f64d43ff0c18 497 * - 0 - No interrupt
mbed_official 146:f64d43ff0c18 498 * - 1 - Interrupt occurred
mbed_official 146:f64d43ff0c18 499 */
mbed_official 146:f64d43ff0c18 500 //@{
mbed_official 146:f64d43ff0c18 501 #define BP_MCM_ISR_FDZC (9U) //!< Bit position for MCM_ISR_FDZC.
mbed_official 146:f64d43ff0c18 502 #define BM_MCM_ISR_FDZC (0x00000200U) //!< Bit mask for MCM_ISR_FDZC.
mbed_official 146:f64d43ff0c18 503 #define BS_MCM_ISR_FDZC (1U) //!< Bit field size in bits for MCM_ISR_FDZC.
mbed_official 146:f64d43ff0c18 504
mbed_official 146:f64d43ff0c18 505 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 506 //! @brief Read current value of the MCM_ISR_FDZC field.
mbed_official 146:f64d43ff0c18 507 #define BR_MCM_ISR_FDZC (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FDZC))
mbed_official 146:f64d43ff0c18 508 #endif
mbed_official 146:f64d43ff0c18 509 //@}
mbed_official 146:f64d43ff0c18 510
mbed_official 146:f64d43ff0c18 511 /*!
mbed_official 146:f64d43ff0c18 512 * @name Register MCM_ISR, field FOFC[10] (RO)
mbed_official 146:f64d43ff0c18 513 *
mbed_official 146:f64d43ff0c18 514 * This read-only bit is a copy of the core's FPSCR[OFC] bit and signals an
mbed_official 146:f64d43ff0c18 515 * overflow has been detected in the processor's FPU. Once set, this bit remains set
mbed_official 146:f64d43ff0c18 516 * until software clears the FPSCR[OFC] bit.
mbed_official 146:f64d43ff0c18 517 *
mbed_official 146:f64d43ff0c18 518 * Values:
mbed_official 146:f64d43ff0c18 519 * - 0 - No interrupt
mbed_official 146:f64d43ff0c18 520 * - 1 - Interrupt occurred
mbed_official 146:f64d43ff0c18 521 */
mbed_official 146:f64d43ff0c18 522 //@{
mbed_official 146:f64d43ff0c18 523 #define BP_MCM_ISR_FOFC (10U) //!< Bit position for MCM_ISR_FOFC.
mbed_official 146:f64d43ff0c18 524 #define BM_MCM_ISR_FOFC (0x00000400U) //!< Bit mask for MCM_ISR_FOFC.
mbed_official 146:f64d43ff0c18 525 #define BS_MCM_ISR_FOFC (1U) //!< Bit field size in bits for MCM_ISR_FOFC.
mbed_official 146:f64d43ff0c18 526
mbed_official 146:f64d43ff0c18 527 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 528 //! @brief Read current value of the MCM_ISR_FOFC field.
mbed_official 146:f64d43ff0c18 529 #define BR_MCM_ISR_FOFC (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FOFC))
mbed_official 146:f64d43ff0c18 530 #endif
mbed_official 146:f64d43ff0c18 531 //@}
mbed_official 146:f64d43ff0c18 532
mbed_official 146:f64d43ff0c18 533 /*!
mbed_official 146:f64d43ff0c18 534 * @name Register MCM_ISR, field FUFC[11] (RO)
mbed_official 146:f64d43ff0c18 535 *
mbed_official 146:f64d43ff0c18 536 * This read-only bit is a copy of the core's FPSCR[UFC] bit and signals an
mbed_official 146:f64d43ff0c18 537 * underflow has been detected in the processor's FPU. Once set, this bit remains set
mbed_official 146:f64d43ff0c18 538 * until software clears the FPSCR[UFC] bit.
mbed_official 146:f64d43ff0c18 539 *
mbed_official 146:f64d43ff0c18 540 * Values:
mbed_official 146:f64d43ff0c18 541 * - 0 - No interrupt
mbed_official 146:f64d43ff0c18 542 * - 1 - Interrupt occurred
mbed_official 146:f64d43ff0c18 543 */
mbed_official 146:f64d43ff0c18 544 //@{
mbed_official 146:f64d43ff0c18 545 #define BP_MCM_ISR_FUFC (11U) //!< Bit position for MCM_ISR_FUFC.
mbed_official 146:f64d43ff0c18 546 #define BM_MCM_ISR_FUFC (0x00000800U) //!< Bit mask for MCM_ISR_FUFC.
mbed_official 146:f64d43ff0c18 547 #define BS_MCM_ISR_FUFC (1U) //!< Bit field size in bits for MCM_ISR_FUFC.
mbed_official 146:f64d43ff0c18 548
mbed_official 146:f64d43ff0c18 549 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 550 //! @brief Read current value of the MCM_ISR_FUFC field.
mbed_official 146:f64d43ff0c18 551 #define BR_MCM_ISR_FUFC (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FUFC))
mbed_official 146:f64d43ff0c18 552 #endif
mbed_official 146:f64d43ff0c18 553 //@}
mbed_official 146:f64d43ff0c18 554
mbed_official 146:f64d43ff0c18 555 /*!
mbed_official 146:f64d43ff0c18 556 * @name Register MCM_ISR, field FIXC[12] (RO)
mbed_official 146:f64d43ff0c18 557 *
mbed_official 146:f64d43ff0c18 558 * This read-only bit is a copy of the core's FPSCR[IXC] bit and signals an
mbed_official 146:f64d43ff0c18 559 * inexact number has been detected in the processor's FPU. Once set, this bit
mbed_official 146:f64d43ff0c18 560 * remains set until software clears the FPSCR[IXC] bit.
mbed_official 146:f64d43ff0c18 561 *
mbed_official 146:f64d43ff0c18 562 * Values:
mbed_official 146:f64d43ff0c18 563 * - 0 - No interrupt
mbed_official 146:f64d43ff0c18 564 * - 1 - Interrupt occurred
mbed_official 146:f64d43ff0c18 565 */
mbed_official 146:f64d43ff0c18 566 //@{
mbed_official 146:f64d43ff0c18 567 #define BP_MCM_ISR_FIXC (12U) //!< Bit position for MCM_ISR_FIXC.
mbed_official 146:f64d43ff0c18 568 #define BM_MCM_ISR_FIXC (0x00001000U) //!< Bit mask for MCM_ISR_FIXC.
mbed_official 146:f64d43ff0c18 569 #define BS_MCM_ISR_FIXC (1U) //!< Bit field size in bits for MCM_ISR_FIXC.
mbed_official 146:f64d43ff0c18 570
mbed_official 146:f64d43ff0c18 571 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 572 //! @brief Read current value of the MCM_ISR_FIXC field.
mbed_official 146:f64d43ff0c18 573 #define BR_MCM_ISR_FIXC (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIXC))
mbed_official 146:f64d43ff0c18 574 #endif
mbed_official 146:f64d43ff0c18 575 //@}
mbed_official 146:f64d43ff0c18 576
mbed_official 146:f64d43ff0c18 577 /*!
mbed_official 146:f64d43ff0c18 578 * @name Register MCM_ISR, field FIDC[15] (RO)
mbed_official 146:f64d43ff0c18 579 *
mbed_official 146:f64d43ff0c18 580 * This read-only bit is a copy of the core's FPSCR[IDC] bit and signals input
mbed_official 146:f64d43ff0c18 581 * denormalized number has been detected in the processor's FPU. Once set, this
mbed_official 146:f64d43ff0c18 582 * bit remains set until software clears the FPSCR[IDC] bit.
mbed_official 146:f64d43ff0c18 583 *
mbed_official 146:f64d43ff0c18 584 * Values:
mbed_official 146:f64d43ff0c18 585 * - 0 - No interrupt
mbed_official 146:f64d43ff0c18 586 * - 1 - Interrupt occurred
mbed_official 146:f64d43ff0c18 587 */
mbed_official 146:f64d43ff0c18 588 //@{
mbed_official 146:f64d43ff0c18 589 #define BP_MCM_ISR_FIDC (15U) //!< Bit position for MCM_ISR_FIDC.
mbed_official 146:f64d43ff0c18 590 #define BM_MCM_ISR_FIDC (0x00008000U) //!< Bit mask for MCM_ISR_FIDC.
mbed_official 146:f64d43ff0c18 591 #define BS_MCM_ISR_FIDC (1U) //!< Bit field size in bits for MCM_ISR_FIDC.
mbed_official 146:f64d43ff0c18 592
mbed_official 146:f64d43ff0c18 593 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 594 //! @brief Read current value of the MCM_ISR_FIDC field.
mbed_official 146:f64d43ff0c18 595 #define BR_MCM_ISR_FIDC (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIDC))
mbed_official 146:f64d43ff0c18 596 #endif
mbed_official 146:f64d43ff0c18 597 //@}
mbed_official 146:f64d43ff0c18 598
mbed_official 146:f64d43ff0c18 599 /*!
mbed_official 146:f64d43ff0c18 600 * @name Register MCM_ISR, field FIOCE[24] (RW)
mbed_official 146:f64d43ff0c18 601 *
mbed_official 146:f64d43ff0c18 602 * Values:
mbed_official 146:f64d43ff0c18 603 * - 0 - Disable interrupt
mbed_official 146:f64d43ff0c18 604 * - 1 - Enable interrupt
mbed_official 146:f64d43ff0c18 605 */
mbed_official 146:f64d43ff0c18 606 //@{
mbed_official 146:f64d43ff0c18 607 #define BP_MCM_ISR_FIOCE (24U) //!< Bit position for MCM_ISR_FIOCE.
mbed_official 146:f64d43ff0c18 608 #define BM_MCM_ISR_FIOCE (0x01000000U) //!< Bit mask for MCM_ISR_FIOCE.
mbed_official 146:f64d43ff0c18 609 #define BS_MCM_ISR_FIOCE (1U) //!< Bit field size in bits for MCM_ISR_FIOCE.
mbed_official 146:f64d43ff0c18 610
mbed_official 146:f64d43ff0c18 611 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 612 //! @brief Read current value of the MCM_ISR_FIOCE field.
mbed_official 146:f64d43ff0c18 613 #define BR_MCM_ISR_FIOCE (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIOCE))
mbed_official 146:f64d43ff0c18 614 #endif
mbed_official 146:f64d43ff0c18 615
mbed_official 146:f64d43ff0c18 616 //! @brief Format value for bitfield MCM_ISR_FIOCE.
mbed_official 146:f64d43ff0c18 617 #define BF_MCM_ISR_FIOCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_FIOCE), uint32_t) & BM_MCM_ISR_FIOCE)
mbed_official 146:f64d43ff0c18 618
mbed_official 146:f64d43ff0c18 619 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 620 //! @brief Set the FIOCE field to a new value.
mbed_official 146:f64d43ff0c18 621 #define BW_MCM_ISR_FIOCE(v) (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIOCE) = (v))
mbed_official 146:f64d43ff0c18 622 #endif
mbed_official 146:f64d43ff0c18 623 //@}
mbed_official 146:f64d43ff0c18 624
mbed_official 146:f64d43ff0c18 625 /*!
mbed_official 146:f64d43ff0c18 626 * @name Register MCM_ISR, field FDZCE[25] (RW)
mbed_official 146:f64d43ff0c18 627 *
mbed_official 146:f64d43ff0c18 628 * Values:
mbed_official 146:f64d43ff0c18 629 * - 0 - Disable interrupt
mbed_official 146:f64d43ff0c18 630 * - 1 - Enable interrupt
mbed_official 146:f64d43ff0c18 631 */
mbed_official 146:f64d43ff0c18 632 //@{
mbed_official 146:f64d43ff0c18 633 #define BP_MCM_ISR_FDZCE (25U) //!< Bit position for MCM_ISR_FDZCE.
mbed_official 146:f64d43ff0c18 634 #define BM_MCM_ISR_FDZCE (0x02000000U) //!< Bit mask for MCM_ISR_FDZCE.
mbed_official 146:f64d43ff0c18 635 #define BS_MCM_ISR_FDZCE (1U) //!< Bit field size in bits for MCM_ISR_FDZCE.
mbed_official 146:f64d43ff0c18 636
mbed_official 146:f64d43ff0c18 637 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 638 //! @brief Read current value of the MCM_ISR_FDZCE field.
mbed_official 146:f64d43ff0c18 639 #define BR_MCM_ISR_FDZCE (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FDZCE))
mbed_official 146:f64d43ff0c18 640 #endif
mbed_official 146:f64d43ff0c18 641
mbed_official 146:f64d43ff0c18 642 //! @brief Format value for bitfield MCM_ISR_FDZCE.
mbed_official 146:f64d43ff0c18 643 #define BF_MCM_ISR_FDZCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_FDZCE), uint32_t) & BM_MCM_ISR_FDZCE)
mbed_official 146:f64d43ff0c18 644
mbed_official 146:f64d43ff0c18 645 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 646 //! @brief Set the FDZCE field to a new value.
mbed_official 146:f64d43ff0c18 647 #define BW_MCM_ISR_FDZCE(v) (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FDZCE) = (v))
mbed_official 146:f64d43ff0c18 648 #endif
mbed_official 146:f64d43ff0c18 649 //@}
mbed_official 146:f64d43ff0c18 650
mbed_official 146:f64d43ff0c18 651 /*!
mbed_official 146:f64d43ff0c18 652 * @name Register MCM_ISR, field FOFCE[26] (RW)
mbed_official 146:f64d43ff0c18 653 *
mbed_official 146:f64d43ff0c18 654 * Values:
mbed_official 146:f64d43ff0c18 655 * - 0 - Disable interrupt
mbed_official 146:f64d43ff0c18 656 * - 1 - Enable interrupt
mbed_official 146:f64d43ff0c18 657 */
mbed_official 146:f64d43ff0c18 658 //@{
mbed_official 146:f64d43ff0c18 659 #define BP_MCM_ISR_FOFCE (26U) //!< Bit position for MCM_ISR_FOFCE.
mbed_official 146:f64d43ff0c18 660 #define BM_MCM_ISR_FOFCE (0x04000000U) //!< Bit mask for MCM_ISR_FOFCE.
mbed_official 146:f64d43ff0c18 661 #define BS_MCM_ISR_FOFCE (1U) //!< Bit field size in bits for MCM_ISR_FOFCE.
mbed_official 146:f64d43ff0c18 662
mbed_official 146:f64d43ff0c18 663 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 664 //! @brief Read current value of the MCM_ISR_FOFCE field.
mbed_official 146:f64d43ff0c18 665 #define BR_MCM_ISR_FOFCE (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FOFCE))
mbed_official 146:f64d43ff0c18 666 #endif
mbed_official 146:f64d43ff0c18 667
mbed_official 146:f64d43ff0c18 668 //! @brief Format value for bitfield MCM_ISR_FOFCE.
mbed_official 146:f64d43ff0c18 669 #define BF_MCM_ISR_FOFCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_FOFCE), uint32_t) & BM_MCM_ISR_FOFCE)
mbed_official 146:f64d43ff0c18 670
mbed_official 146:f64d43ff0c18 671 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 672 //! @brief Set the FOFCE field to a new value.
mbed_official 146:f64d43ff0c18 673 #define BW_MCM_ISR_FOFCE(v) (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FOFCE) = (v))
mbed_official 146:f64d43ff0c18 674 #endif
mbed_official 146:f64d43ff0c18 675 //@}
mbed_official 146:f64d43ff0c18 676
mbed_official 146:f64d43ff0c18 677 /*!
mbed_official 146:f64d43ff0c18 678 * @name Register MCM_ISR, field FUFCE[27] (RW)
mbed_official 146:f64d43ff0c18 679 *
mbed_official 146:f64d43ff0c18 680 * Values:
mbed_official 146:f64d43ff0c18 681 * - 0 - Disable interrupt
mbed_official 146:f64d43ff0c18 682 * - 1 - Enable interrupt
mbed_official 146:f64d43ff0c18 683 */
mbed_official 146:f64d43ff0c18 684 //@{
mbed_official 146:f64d43ff0c18 685 #define BP_MCM_ISR_FUFCE (27U) //!< Bit position for MCM_ISR_FUFCE.
mbed_official 146:f64d43ff0c18 686 #define BM_MCM_ISR_FUFCE (0x08000000U) //!< Bit mask for MCM_ISR_FUFCE.
mbed_official 146:f64d43ff0c18 687 #define BS_MCM_ISR_FUFCE (1U) //!< Bit field size in bits for MCM_ISR_FUFCE.
mbed_official 146:f64d43ff0c18 688
mbed_official 146:f64d43ff0c18 689 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 690 //! @brief Read current value of the MCM_ISR_FUFCE field.
mbed_official 146:f64d43ff0c18 691 #define BR_MCM_ISR_FUFCE (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FUFCE))
mbed_official 146:f64d43ff0c18 692 #endif
mbed_official 146:f64d43ff0c18 693
mbed_official 146:f64d43ff0c18 694 //! @brief Format value for bitfield MCM_ISR_FUFCE.
mbed_official 146:f64d43ff0c18 695 #define BF_MCM_ISR_FUFCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_FUFCE), uint32_t) & BM_MCM_ISR_FUFCE)
mbed_official 146:f64d43ff0c18 696
mbed_official 146:f64d43ff0c18 697 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 698 //! @brief Set the FUFCE field to a new value.
mbed_official 146:f64d43ff0c18 699 #define BW_MCM_ISR_FUFCE(v) (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FUFCE) = (v))
mbed_official 146:f64d43ff0c18 700 #endif
mbed_official 146:f64d43ff0c18 701 //@}
mbed_official 146:f64d43ff0c18 702
mbed_official 146:f64d43ff0c18 703 /*!
mbed_official 146:f64d43ff0c18 704 * @name Register MCM_ISR, field FIXCE[28] (RW)
mbed_official 146:f64d43ff0c18 705 *
mbed_official 146:f64d43ff0c18 706 * Values:
mbed_official 146:f64d43ff0c18 707 * - 0 - Disable interrupt
mbed_official 146:f64d43ff0c18 708 * - 1 - Enable interrupt
mbed_official 146:f64d43ff0c18 709 */
mbed_official 146:f64d43ff0c18 710 //@{
mbed_official 146:f64d43ff0c18 711 #define BP_MCM_ISR_FIXCE (28U) //!< Bit position for MCM_ISR_FIXCE.
mbed_official 146:f64d43ff0c18 712 #define BM_MCM_ISR_FIXCE (0x10000000U) //!< Bit mask for MCM_ISR_FIXCE.
mbed_official 146:f64d43ff0c18 713 #define BS_MCM_ISR_FIXCE (1U) //!< Bit field size in bits for MCM_ISR_FIXCE.
mbed_official 146:f64d43ff0c18 714
mbed_official 146:f64d43ff0c18 715 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 716 //! @brief Read current value of the MCM_ISR_FIXCE field.
mbed_official 146:f64d43ff0c18 717 #define BR_MCM_ISR_FIXCE (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIXCE))
mbed_official 146:f64d43ff0c18 718 #endif
mbed_official 146:f64d43ff0c18 719
mbed_official 146:f64d43ff0c18 720 //! @brief Format value for bitfield MCM_ISR_FIXCE.
mbed_official 146:f64d43ff0c18 721 #define BF_MCM_ISR_FIXCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_FIXCE), uint32_t) & BM_MCM_ISR_FIXCE)
mbed_official 146:f64d43ff0c18 722
mbed_official 146:f64d43ff0c18 723 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 724 //! @brief Set the FIXCE field to a new value.
mbed_official 146:f64d43ff0c18 725 #define BW_MCM_ISR_FIXCE(v) (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIXCE) = (v))
mbed_official 146:f64d43ff0c18 726 #endif
mbed_official 146:f64d43ff0c18 727 //@}
mbed_official 146:f64d43ff0c18 728
mbed_official 146:f64d43ff0c18 729 /*!
mbed_official 146:f64d43ff0c18 730 * @name Register MCM_ISR, field FIDCE[31] (RW)
mbed_official 146:f64d43ff0c18 731 *
mbed_official 146:f64d43ff0c18 732 * Values:
mbed_official 146:f64d43ff0c18 733 * - 0 - Disable interrupt
mbed_official 146:f64d43ff0c18 734 * - 1 - Enable interrupt
mbed_official 146:f64d43ff0c18 735 */
mbed_official 146:f64d43ff0c18 736 //@{
mbed_official 146:f64d43ff0c18 737 #define BP_MCM_ISR_FIDCE (31U) //!< Bit position for MCM_ISR_FIDCE.
mbed_official 146:f64d43ff0c18 738 #define BM_MCM_ISR_FIDCE (0x80000000U) //!< Bit mask for MCM_ISR_FIDCE.
mbed_official 146:f64d43ff0c18 739 #define BS_MCM_ISR_FIDCE (1U) //!< Bit field size in bits for MCM_ISR_FIDCE.
mbed_official 146:f64d43ff0c18 740
mbed_official 146:f64d43ff0c18 741 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 742 //! @brief Read current value of the MCM_ISR_FIDCE field.
mbed_official 146:f64d43ff0c18 743 #define BR_MCM_ISR_FIDCE (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIDCE))
mbed_official 146:f64d43ff0c18 744 #endif
mbed_official 146:f64d43ff0c18 745
mbed_official 146:f64d43ff0c18 746 //! @brief Format value for bitfield MCM_ISR_FIDCE.
mbed_official 146:f64d43ff0c18 747 #define BF_MCM_ISR_FIDCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_FIDCE), uint32_t) & BM_MCM_ISR_FIDCE)
mbed_official 146:f64d43ff0c18 748
mbed_official 146:f64d43ff0c18 749 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 750 //! @brief Set the FIDCE field to a new value.
mbed_official 146:f64d43ff0c18 751 #define BW_MCM_ISR_FIDCE(v) (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIDCE) = (v))
mbed_official 146:f64d43ff0c18 752 #endif
mbed_official 146:f64d43ff0c18 753 //@}
mbed_official 146:f64d43ff0c18 754
mbed_official 146:f64d43ff0c18 755 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 756 // HW_MCM_ETBCC - ETB Counter Control register
mbed_official 146:f64d43ff0c18 757 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 758
mbed_official 146:f64d43ff0c18 759 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 760 /*!
mbed_official 146:f64d43ff0c18 761 * @brief HW_MCM_ETBCC - ETB Counter Control register (RW)
mbed_official 146:f64d43ff0c18 762 *
mbed_official 146:f64d43ff0c18 763 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 764 */
mbed_official 146:f64d43ff0c18 765 typedef union _hw_mcm_etbcc
mbed_official 146:f64d43ff0c18 766 {
mbed_official 146:f64d43ff0c18 767 uint32_t U;
mbed_official 146:f64d43ff0c18 768 struct _hw_mcm_etbcc_bitfields
mbed_official 146:f64d43ff0c18 769 {
mbed_official 146:f64d43ff0c18 770 uint32_t CNTEN : 1; //!< [0] Counter Enable
mbed_official 146:f64d43ff0c18 771 uint32_t RSPT : 2; //!< [2:1] Response Type
mbed_official 146:f64d43ff0c18 772 uint32_t RLRQ : 1; //!< [3] Reload Request
mbed_official 146:f64d43ff0c18 773 uint32_t ETDIS : 1; //!< [4] ETM-To-TPIU Disable
mbed_official 146:f64d43ff0c18 774 uint32_t ITDIS : 1; //!< [5] ITM-To-TPIU Disable
mbed_official 146:f64d43ff0c18 775 uint32_t RESERVED0 : 26; //!< [31:6]
mbed_official 146:f64d43ff0c18 776 } B;
mbed_official 146:f64d43ff0c18 777 } hw_mcm_etbcc_t;
mbed_official 146:f64d43ff0c18 778 #endif
mbed_official 146:f64d43ff0c18 779
mbed_official 146:f64d43ff0c18 780 /*!
mbed_official 146:f64d43ff0c18 781 * @name Constants and macros for entire MCM_ETBCC register
mbed_official 146:f64d43ff0c18 782 */
mbed_official 146:f64d43ff0c18 783 //@{
mbed_official 146:f64d43ff0c18 784 #define HW_MCM_ETBCC_ADDR (REGS_MCM_BASE + 0x14U)
mbed_official 146:f64d43ff0c18 785
mbed_official 146:f64d43ff0c18 786 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 787 #define HW_MCM_ETBCC (*(__IO hw_mcm_etbcc_t *) HW_MCM_ETBCC_ADDR)
mbed_official 146:f64d43ff0c18 788 #define HW_MCM_ETBCC_RD() (HW_MCM_ETBCC.U)
mbed_official 146:f64d43ff0c18 789 #define HW_MCM_ETBCC_WR(v) (HW_MCM_ETBCC.U = (v))
mbed_official 146:f64d43ff0c18 790 #define HW_MCM_ETBCC_SET(v) (HW_MCM_ETBCC_WR(HW_MCM_ETBCC_RD() | (v)))
mbed_official 146:f64d43ff0c18 791 #define HW_MCM_ETBCC_CLR(v) (HW_MCM_ETBCC_WR(HW_MCM_ETBCC_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 792 #define HW_MCM_ETBCC_TOG(v) (HW_MCM_ETBCC_WR(HW_MCM_ETBCC_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 793 #endif
mbed_official 146:f64d43ff0c18 794 //@}
mbed_official 146:f64d43ff0c18 795
mbed_official 146:f64d43ff0c18 796 /*
mbed_official 146:f64d43ff0c18 797 * Constants & macros for individual MCM_ETBCC bitfields
mbed_official 146:f64d43ff0c18 798 */
mbed_official 146:f64d43ff0c18 799
mbed_official 146:f64d43ff0c18 800 /*!
mbed_official 146:f64d43ff0c18 801 * @name Register MCM_ETBCC, field CNTEN[0] (RW)
mbed_official 146:f64d43ff0c18 802 *
mbed_official 146:f64d43ff0c18 803 * Enables the ETB counter.
mbed_official 146:f64d43ff0c18 804 *
mbed_official 146:f64d43ff0c18 805 * Values:
mbed_official 146:f64d43ff0c18 806 * - 0 - ETB counter disabled
mbed_official 146:f64d43ff0c18 807 * - 1 - ETB counter enabled
mbed_official 146:f64d43ff0c18 808 */
mbed_official 146:f64d43ff0c18 809 //@{
mbed_official 146:f64d43ff0c18 810 #define BP_MCM_ETBCC_CNTEN (0U) //!< Bit position for MCM_ETBCC_CNTEN.
mbed_official 146:f64d43ff0c18 811 #define BM_MCM_ETBCC_CNTEN (0x00000001U) //!< Bit mask for MCM_ETBCC_CNTEN.
mbed_official 146:f64d43ff0c18 812 #define BS_MCM_ETBCC_CNTEN (1U) //!< Bit field size in bits for MCM_ETBCC_CNTEN.
mbed_official 146:f64d43ff0c18 813
mbed_official 146:f64d43ff0c18 814 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 815 //! @brief Read current value of the MCM_ETBCC_CNTEN field.
mbed_official 146:f64d43ff0c18 816 #define BR_MCM_ETBCC_CNTEN (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_CNTEN))
mbed_official 146:f64d43ff0c18 817 #endif
mbed_official 146:f64d43ff0c18 818
mbed_official 146:f64d43ff0c18 819 //! @brief Format value for bitfield MCM_ETBCC_CNTEN.
mbed_official 146:f64d43ff0c18 820 #define BF_MCM_ETBCC_CNTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ETBCC_CNTEN), uint32_t) & BM_MCM_ETBCC_CNTEN)
mbed_official 146:f64d43ff0c18 821
mbed_official 146:f64d43ff0c18 822 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 823 //! @brief Set the CNTEN field to a new value.
mbed_official 146:f64d43ff0c18 824 #define BW_MCM_ETBCC_CNTEN(v) (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_CNTEN) = (v))
mbed_official 146:f64d43ff0c18 825 #endif
mbed_official 146:f64d43ff0c18 826 //@}
mbed_official 146:f64d43ff0c18 827
mbed_official 146:f64d43ff0c18 828 /*!
mbed_official 146:f64d43ff0c18 829 * @name Register MCM_ETBCC, field RSPT[2:1] (RW)
mbed_official 146:f64d43ff0c18 830 *
mbed_official 146:f64d43ff0c18 831 * Values:
mbed_official 146:f64d43ff0c18 832 * - 00 - No response when the ETB count expires
mbed_official 146:f64d43ff0c18 833 * - 01 - Generate a normal interrupt when the ETB count expires
mbed_official 146:f64d43ff0c18 834 * - 10 - Generate an NMI when the ETB count expires
mbed_official 146:f64d43ff0c18 835 * - 11 - Generate a debug halt when the ETB count expires
mbed_official 146:f64d43ff0c18 836 */
mbed_official 146:f64d43ff0c18 837 //@{
mbed_official 146:f64d43ff0c18 838 #define BP_MCM_ETBCC_RSPT (1U) //!< Bit position for MCM_ETBCC_RSPT.
mbed_official 146:f64d43ff0c18 839 #define BM_MCM_ETBCC_RSPT (0x00000006U) //!< Bit mask for MCM_ETBCC_RSPT.
mbed_official 146:f64d43ff0c18 840 #define BS_MCM_ETBCC_RSPT (2U) //!< Bit field size in bits for MCM_ETBCC_RSPT.
mbed_official 146:f64d43ff0c18 841
mbed_official 146:f64d43ff0c18 842 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 843 //! @brief Read current value of the MCM_ETBCC_RSPT field.
mbed_official 146:f64d43ff0c18 844 #define BR_MCM_ETBCC_RSPT (HW_MCM_ETBCC.B.RSPT)
mbed_official 146:f64d43ff0c18 845 #endif
mbed_official 146:f64d43ff0c18 846
mbed_official 146:f64d43ff0c18 847 //! @brief Format value for bitfield MCM_ETBCC_RSPT.
mbed_official 146:f64d43ff0c18 848 #define BF_MCM_ETBCC_RSPT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ETBCC_RSPT), uint32_t) & BM_MCM_ETBCC_RSPT)
mbed_official 146:f64d43ff0c18 849
mbed_official 146:f64d43ff0c18 850 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 851 //! @brief Set the RSPT field to a new value.
mbed_official 146:f64d43ff0c18 852 #define BW_MCM_ETBCC_RSPT(v) (HW_MCM_ETBCC_WR((HW_MCM_ETBCC_RD() & ~BM_MCM_ETBCC_RSPT) | BF_MCM_ETBCC_RSPT(v)))
mbed_official 146:f64d43ff0c18 853 #endif
mbed_official 146:f64d43ff0c18 854 //@}
mbed_official 146:f64d43ff0c18 855
mbed_official 146:f64d43ff0c18 856 /*!
mbed_official 146:f64d43ff0c18 857 * @name Register MCM_ETBCC, field RLRQ[3] (RW)
mbed_official 146:f64d43ff0c18 858 *
mbed_official 146:f64d43ff0c18 859 * Reloads the ETB packet counter with the MCM_ETBRL RELOAD value. If IRQ or NMI
mbed_official 146:f64d43ff0c18 860 * interrupts were enabled and an NMI or IRQ interrupt was generated on counter
mbed_official 146:f64d43ff0c18 861 * expiration, setting this bit clears the pending NMI or IRQ interrupt request.
mbed_official 146:f64d43ff0c18 862 * If debug halt was enabled and a debug halt request was asserted on counter
mbed_official 146:f64d43ff0c18 863 * expiration, setting this bit clears the debug halt request.
mbed_official 146:f64d43ff0c18 864 *
mbed_official 146:f64d43ff0c18 865 * Values:
mbed_official 146:f64d43ff0c18 866 * - 0 - No effect
mbed_official 146:f64d43ff0c18 867 * - 1 - Clears pending debug halt, NMI, or IRQ interrupt requests
mbed_official 146:f64d43ff0c18 868 */
mbed_official 146:f64d43ff0c18 869 //@{
mbed_official 146:f64d43ff0c18 870 #define BP_MCM_ETBCC_RLRQ (3U) //!< Bit position for MCM_ETBCC_RLRQ.
mbed_official 146:f64d43ff0c18 871 #define BM_MCM_ETBCC_RLRQ (0x00000008U) //!< Bit mask for MCM_ETBCC_RLRQ.
mbed_official 146:f64d43ff0c18 872 #define BS_MCM_ETBCC_RLRQ (1U) //!< Bit field size in bits for MCM_ETBCC_RLRQ.
mbed_official 146:f64d43ff0c18 873
mbed_official 146:f64d43ff0c18 874 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 875 //! @brief Read current value of the MCM_ETBCC_RLRQ field.
mbed_official 146:f64d43ff0c18 876 #define BR_MCM_ETBCC_RLRQ (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_RLRQ))
mbed_official 146:f64d43ff0c18 877 #endif
mbed_official 146:f64d43ff0c18 878
mbed_official 146:f64d43ff0c18 879 //! @brief Format value for bitfield MCM_ETBCC_RLRQ.
mbed_official 146:f64d43ff0c18 880 #define BF_MCM_ETBCC_RLRQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ETBCC_RLRQ), uint32_t) & BM_MCM_ETBCC_RLRQ)
mbed_official 146:f64d43ff0c18 881
mbed_official 146:f64d43ff0c18 882 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 883 //! @brief Set the RLRQ field to a new value.
mbed_official 146:f64d43ff0c18 884 #define BW_MCM_ETBCC_RLRQ(v) (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_RLRQ) = (v))
mbed_official 146:f64d43ff0c18 885 #endif
mbed_official 146:f64d43ff0c18 886 //@}
mbed_official 146:f64d43ff0c18 887
mbed_official 146:f64d43ff0c18 888 /*!
mbed_official 146:f64d43ff0c18 889 * @name Register MCM_ETBCC, field ETDIS[4] (RW)
mbed_official 146:f64d43ff0c18 890 *
mbed_official 146:f64d43ff0c18 891 * Disables the trace path from ETM to TPIU.
mbed_official 146:f64d43ff0c18 892 *
mbed_official 146:f64d43ff0c18 893 * Values:
mbed_official 146:f64d43ff0c18 894 * - 0 - ETM-to-TPIU trace path enabled
mbed_official 146:f64d43ff0c18 895 * - 1 - ETM-to-TPIU trace path disabled
mbed_official 146:f64d43ff0c18 896 */
mbed_official 146:f64d43ff0c18 897 //@{
mbed_official 146:f64d43ff0c18 898 #define BP_MCM_ETBCC_ETDIS (4U) //!< Bit position for MCM_ETBCC_ETDIS.
mbed_official 146:f64d43ff0c18 899 #define BM_MCM_ETBCC_ETDIS (0x00000010U) //!< Bit mask for MCM_ETBCC_ETDIS.
mbed_official 146:f64d43ff0c18 900 #define BS_MCM_ETBCC_ETDIS (1U) //!< Bit field size in bits for MCM_ETBCC_ETDIS.
mbed_official 146:f64d43ff0c18 901
mbed_official 146:f64d43ff0c18 902 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 903 //! @brief Read current value of the MCM_ETBCC_ETDIS field.
mbed_official 146:f64d43ff0c18 904 #define BR_MCM_ETBCC_ETDIS (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_ETDIS))
mbed_official 146:f64d43ff0c18 905 #endif
mbed_official 146:f64d43ff0c18 906
mbed_official 146:f64d43ff0c18 907 //! @brief Format value for bitfield MCM_ETBCC_ETDIS.
mbed_official 146:f64d43ff0c18 908 #define BF_MCM_ETBCC_ETDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ETBCC_ETDIS), uint32_t) & BM_MCM_ETBCC_ETDIS)
mbed_official 146:f64d43ff0c18 909
mbed_official 146:f64d43ff0c18 910 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 911 //! @brief Set the ETDIS field to a new value.
mbed_official 146:f64d43ff0c18 912 #define BW_MCM_ETBCC_ETDIS(v) (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_ETDIS) = (v))
mbed_official 146:f64d43ff0c18 913 #endif
mbed_official 146:f64d43ff0c18 914 //@}
mbed_official 146:f64d43ff0c18 915
mbed_official 146:f64d43ff0c18 916 /*!
mbed_official 146:f64d43ff0c18 917 * @name Register MCM_ETBCC, field ITDIS[5] (RW)
mbed_official 146:f64d43ff0c18 918 *
mbed_official 146:f64d43ff0c18 919 * Disables the trace path from ITM to TPIU.
mbed_official 146:f64d43ff0c18 920 *
mbed_official 146:f64d43ff0c18 921 * Values:
mbed_official 146:f64d43ff0c18 922 * - 0 - ITM-to-TPIU trace path enabled
mbed_official 146:f64d43ff0c18 923 * - 1 - ITM-to-TPIU trace path disabled
mbed_official 146:f64d43ff0c18 924 */
mbed_official 146:f64d43ff0c18 925 //@{
mbed_official 146:f64d43ff0c18 926 #define BP_MCM_ETBCC_ITDIS (5U) //!< Bit position for MCM_ETBCC_ITDIS.
mbed_official 146:f64d43ff0c18 927 #define BM_MCM_ETBCC_ITDIS (0x00000020U) //!< Bit mask for MCM_ETBCC_ITDIS.
mbed_official 146:f64d43ff0c18 928 #define BS_MCM_ETBCC_ITDIS (1U) //!< Bit field size in bits for MCM_ETBCC_ITDIS.
mbed_official 146:f64d43ff0c18 929
mbed_official 146:f64d43ff0c18 930 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 931 //! @brief Read current value of the MCM_ETBCC_ITDIS field.
mbed_official 146:f64d43ff0c18 932 #define BR_MCM_ETBCC_ITDIS (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_ITDIS))
mbed_official 146:f64d43ff0c18 933 #endif
mbed_official 146:f64d43ff0c18 934
mbed_official 146:f64d43ff0c18 935 //! @brief Format value for bitfield MCM_ETBCC_ITDIS.
mbed_official 146:f64d43ff0c18 936 #define BF_MCM_ETBCC_ITDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ETBCC_ITDIS), uint32_t) & BM_MCM_ETBCC_ITDIS)
mbed_official 146:f64d43ff0c18 937
mbed_official 146:f64d43ff0c18 938 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 939 //! @brief Set the ITDIS field to a new value.
mbed_official 146:f64d43ff0c18 940 #define BW_MCM_ETBCC_ITDIS(v) (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_ITDIS) = (v))
mbed_official 146:f64d43ff0c18 941 #endif
mbed_official 146:f64d43ff0c18 942 //@}
mbed_official 146:f64d43ff0c18 943
mbed_official 146:f64d43ff0c18 944 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 945 // HW_MCM_ETBRL - ETB Reload register
mbed_official 146:f64d43ff0c18 946 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 947
mbed_official 146:f64d43ff0c18 948 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 949 /*!
mbed_official 146:f64d43ff0c18 950 * @brief HW_MCM_ETBRL - ETB Reload register (RW)
mbed_official 146:f64d43ff0c18 951 *
mbed_official 146:f64d43ff0c18 952 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 953 */
mbed_official 146:f64d43ff0c18 954 typedef union _hw_mcm_etbrl
mbed_official 146:f64d43ff0c18 955 {
mbed_official 146:f64d43ff0c18 956 uint32_t U;
mbed_official 146:f64d43ff0c18 957 struct _hw_mcm_etbrl_bitfields
mbed_official 146:f64d43ff0c18 958 {
mbed_official 146:f64d43ff0c18 959 uint32_t RELOAD : 11; //!< [10:0] Byte Count Reload Value
mbed_official 146:f64d43ff0c18 960 uint32_t RESERVED0 : 21; //!< [31:11]
mbed_official 146:f64d43ff0c18 961 } B;
mbed_official 146:f64d43ff0c18 962 } hw_mcm_etbrl_t;
mbed_official 146:f64d43ff0c18 963 #endif
mbed_official 146:f64d43ff0c18 964
mbed_official 146:f64d43ff0c18 965 /*!
mbed_official 146:f64d43ff0c18 966 * @name Constants and macros for entire MCM_ETBRL register
mbed_official 146:f64d43ff0c18 967 */
mbed_official 146:f64d43ff0c18 968 //@{
mbed_official 146:f64d43ff0c18 969 #define HW_MCM_ETBRL_ADDR (REGS_MCM_BASE + 0x18U)
mbed_official 146:f64d43ff0c18 970
mbed_official 146:f64d43ff0c18 971 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 972 #define HW_MCM_ETBRL (*(__IO hw_mcm_etbrl_t *) HW_MCM_ETBRL_ADDR)
mbed_official 146:f64d43ff0c18 973 #define HW_MCM_ETBRL_RD() (HW_MCM_ETBRL.U)
mbed_official 146:f64d43ff0c18 974 #define HW_MCM_ETBRL_WR(v) (HW_MCM_ETBRL.U = (v))
mbed_official 146:f64d43ff0c18 975 #define HW_MCM_ETBRL_SET(v) (HW_MCM_ETBRL_WR(HW_MCM_ETBRL_RD() | (v)))
mbed_official 146:f64d43ff0c18 976 #define HW_MCM_ETBRL_CLR(v) (HW_MCM_ETBRL_WR(HW_MCM_ETBRL_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 977 #define HW_MCM_ETBRL_TOG(v) (HW_MCM_ETBRL_WR(HW_MCM_ETBRL_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 978 #endif
mbed_official 146:f64d43ff0c18 979 //@}
mbed_official 146:f64d43ff0c18 980
mbed_official 146:f64d43ff0c18 981 /*
mbed_official 146:f64d43ff0c18 982 * Constants & macros for individual MCM_ETBRL bitfields
mbed_official 146:f64d43ff0c18 983 */
mbed_official 146:f64d43ff0c18 984
mbed_official 146:f64d43ff0c18 985 /*!
mbed_official 146:f64d43ff0c18 986 * @name Register MCM_ETBRL, field RELOAD[10:0] (RW)
mbed_official 146:f64d43ff0c18 987 *
mbed_official 146:f64d43ff0c18 988 * Indicates the 0-mod-4 value the counter reloads to. Writing a non-0-mod-4
mbed_official 146:f64d43ff0c18 989 * value to this field results in a bus error.
mbed_official 146:f64d43ff0c18 990 */
mbed_official 146:f64d43ff0c18 991 //@{
mbed_official 146:f64d43ff0c18 992 #define BP_MCM_ETBRL_RELOAD (0U) //!< Bit position for MCM_ETBRL_RELOAD.
mbed_official 146:f64d43ff0c18 993 #define BM_MCM_ETBRL_RELOAD (0x000007FFU) //!< Bit mask for MCM_ETBRL_RELOAD.
mbed_official 146:f64d43ff0c18 994 #define BS_MCM_ETBRL_RELOAD (11U) //!< Bit field size in bits for MCM_ETBRL_RELOAD.
mbed_official 146:f64d43ff0c18 995
mbed_official 146:f64d43ff0c18 996 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 997 //! @brief Read current value of the MCM_ETBRL_RELOAD field.
mbed_official 146:f64d43ff0c18 998 #define BR_MCM_ETBRL_RELOAD (HW_MCM_ETBRL.B.RELOAD)
mbed_official 146:f64d43ff0c18 999 #endif
mbed_official 146:f64d43ff0c18 1000
mbed_official 146:f64d43ff0c18 1001 //! @brief Format value for bitfield MCM_ETBRL_RELOAD.
mbed_official 146:f64d43ff0c18 1002 #define BF_MCM_ETBRL_RELOAD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ETBRL_RELOAD), uint32_t) & BM_MCM_ETBRL_RELOAD)
mbed_official 146:f64d43ff0c18 1003
mbed_official 146:f64d43ff0c18 1004 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1005 //! @brief Set the RELOAD field to a new value.
mbed_official 146:f64d43ff0c18 1006 #define BW_MCM_ETBRL_RELOAD(v) (HW_MCM_ETBRL_WR((HW_MCM_ETBRL_RD() & ~BM_MCM_ETBRL_RELOAD) | BF_MCM_ETBRL_RELOAD(v)))
mbed_official 146:f64d43ff0c18 1007 #endif
mbed_official 146:f64d43ff0c18 1008 //@}
mbed_official 146:f64d43ff0c18 1009
mbed_official 146:f64d43ff0c18 1010 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1011 // HW_MCM_ETBCNT - ETB Counter Value register
mbed_official 146:f64d43ff0c18 1012 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1013
mbed_official 146:f64d43ff0c18 1014 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1015 /*!
mbed_official 146:f64d43ff0c18 1016 * @brief HW_MCM_ETBCNT - ETB Counter Value register (RO)
mbed_official 146:f64d43ff0c18 1017 *
mbed_official 146:f64d43ff0c18 1018 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 1019 */
mbed_official 146:f64d43ff0c18 1020 typedef union _hw_mcm_etbcnt
mbed_official 146:f64d43ff0c18 1021 {
mbed_official 146:f64d43ff0c18 1022 uint32_t U;
mbed_official 146:f64d43ff0c18 1023 struct _hw_mcm_etbcnt_bitfields
mbed_official 146:f64d43ff0c18 1024 {
mbed_official 146:f64d43ff0c18 1025 uint32_t COUNTER : 11; //!< [10:0] Byte Count Counter Value
mbed_official 146:f64d43ff0c18 1026 uint32_t RESERVED0 : 21; //!< [31:11]
mbed_official 146:f64d43ff0c18 1027 } B;
mbed_official 146:f64d43ff0c18 1028 } hw_mcm_etbcnt_t;
mbed_official 146:f64d43ff0c18 1029 #endif
mbed_official 146:f64d43ff0c18 1030
mbed_official 146:f64d43ff0c18 1031 /*!
mbed_official 146:f64d43ff0c18 1032 * @name Constants and macros for entire MCM_ETBCNT register
mbed_official 146:f64d43ff0c18 1033 */
mbed_official 146:f64d43ff0c18 1034 //@{
mbed_official 146:f64d43ff0c18 1035 #define HW_MCM_ETBCNT_ADDR (REGS_MCM_BASE + 0x1CU)
mbed_official 146:f64d43ff0c18 1036
mbed_official 146:f64d43ff0c18 1037 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1038 #define HW_MCM_ETBCNT (*(__I hw_mcm_etbcnt_t *) HW_MCM_ETBCNT_ADDR)
mbed_official 146:f64d43ff0c18 1039 #define HW_MCM_ETBCNT_RD() (HW_MCM_ETBCNT.U)
mbed_official 146:f64d43ff0c18 1040 #endif
mbed_official 146:f64d43ff0c18 1041 //@}
mbed_official 146:f64d43ff0c18 1042
mbed_official 146:f64d43ff0c18 1043 /*
mbed_official 146:f64d43ff0c18 1044 * Constants & macros for individual MCM_ETBCNT bitfields
mbed_official 146:f64d43ff0c18 1045 */
mbed_official 146:f64d43ff0c18 1046
mbed_official 146:f64d43ff0c18 1047 /*!
mbed_official 146:f64d43ff0c18 1048 * @name Register MCM_ETBCNT, field COUNTER[10:0] (RO)
mbed_official 146:f64d43ff0c18 1049 *
mbed_official 146:f64d43ff0c18 1050 * Indicates the current 0-mod-4 value of the counter.
mbed_official 146:f64d43ff0c18 1051 */
mbed_official 146:f64d43ff0c18 1052 //@{
mbed_official 146:f64d43ff0c18 1053 #define BP_MCM_ETBCNT_COUNTER (0U) //!< Bit position for MCM_ETBCNT_COUNTER.
mbed_official 146:f64d43ff0c18 1054 #define BM_MCM_ETBCNT_COUNTER (0x000007FFU) //!< Bit mask for MCM_ETBCNT_COUNTER.
mbed_official 146:f64d43ff0c18 1055 #define BS_MCM_ETBCNT_COUNTER (11U) //!< Bit field size in bits for MCM_ETBCNT_COUNTER.
mbed_official 146:f64d43ff0c18 1056
mbed_official 146:f64d43ff0c18 1057 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1058 //! @brief Read current value of the MCM_ETBCNT_COUNTER field.
mbed_official 146:f64d43ff0c18 1059 #define BR_MCM_ETBCNT_COUNTER (HW_MCM_ETBCNT.B.COUNTER)
mbed_official 146:f64d43ff0c18 1060 #endif
mbed_official 146:f64d43ff0c18 1061 //@}
mbed_official 146:f64d43ff0c18 1062
mbed_official 146:f64d43ff0c18 1063 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1064 // HW_MCM_PID - Process ID register
mbed_official 146:f64d43ff0c18 1065 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1066
mbed_official 146:f64d43ff0c18 1067 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1068 /*!
mbed_official 146:f64d43ff0c18 1069 * @brief HW_MCM_PID - Process ID register (RW)
mbed_official 146:f64d43ff0c18 1070 *
mbed_official 146:f64d43ff0c18 1071 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 1072 *
mbed_official 146:f64d43ff0c18 1073 * This register drives the M0_PID and M1_PID values in the Memory Protection
mbed_official 146:f64d43ff0c18 1074 * Unit(MPU). System software loads this register before passing control to a given
mbed_official 146:f64d43ff0c18 1075 * user mode process. If the PID of the process does not match the value in this
mbed_official 146:f64d43ff0c18 1076 * register, a bus error occurs. See the MPU chapter for more details.
mbed_official 146:f64d43ff0c18 1077 */
mbed_official 146:f64d43ff0c18 1078 typedef union _hw_mcm_pid
mbed_official 146:f64d43ff0c18 1079 {
mbed_official 146:f64d43ff0c18 1080 uint32_t U;
mbed_official 146:f64d43ff0c18 1081 struct _hw_mcm_pid_bitfields
mbed_official 146:f64d43ff0c18 1082 {
mbed_official 146:f64d43ff0c18 1083 uint32_t PID : 8; //!< [7:0] M0_PID And M1_PID For MPU
mbed_official 146:f64d43ff0c18 1084 uint32_t RESERVED0 : 24; //!< [31:8]
mbed_official 146:f64d43ff0c18 1085 } B;
mbed_official 146:f64d43ff0c18 1086 } hw_mcm_pid_t;
mbed_official 146:f64d43ff0c18 1087 #endif
mbed_official 146:f64d43ff0c18 1088
mbed_official 146:f64d43ff0c18 1089 /*!
mbed_official 146:f64d43ff0c18 1090 * @name Constants and macros for entire MCM_PID register
mbed_official 146:f64d43ff0c18 1091 */
mbed_official 146:f64d43ff0c18 1092 //@{
mbed_official 146:f64d43ff0c18 1093 #define HW_MCM_PID_ADDR (REGS_MCM_BASE + 0x30U)
mbed_official 146:f64d43ff0c18 1094
mbed_official 146:f64d43ff0c18 1095 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1096 #define HW_MCM_PID (*(__IO hw_mcm_pid_t *) HW_MCM_PID_ADDR)
mbed_official 146:f64d43ff0c18 1097 #define HW_MCM_PID_RD() (HW_MCM_PID.U)
mbed_official 146:f64d43ff0c18 1098 #define HW_MCM_PID_WR(v) (HW_MCM_PID.U = (v))
mbed_official 146:f64d43ff0c18 1099 #define HW_MCM_PID_SET(v) (HW_MCM_PID_WR(HW_MCM_PID_RD() | (v)))
mbed_official 146:f64d43ff0c18 1100 #define HW_MCM_PID_CLR(v) (HW_MCM_PID_WR(HW_MCM_PID_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 1101 #define HW_MCM_PID_TOG(v) (HW_MCM_PID_WR(HW_MCM_PID_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 1102 #endif
mbed_official 146:f64d43ff0c18 1103 //@}
mbed_official 146:f64d43ff0c18 1104
mbed_official 146:f64d43ff0c18 1105 /*
mbed_official 146:f64d43ff0c18 1106 * Constants & macros for individual MCM_PID bitfields
mbed_official 146:f64d43ff0c18 1107 */
mbed_official 146:f64d43ff0c18 1108
mbed_official 146:f64d43ff0c18 1109 /*!
mbed_official 146:f64d43ff0c18 1110 * @name Register MCM_PID, field PID[7:0] (RW)
mbed_official 146:f64d43ff0c18 1111 *
mbed_official 146:f64d43ff0c18 1112 * Drives the M0_PID and M1_PID values in the MPU.
mbed_official 146:f64d43ff0c18 1113 */
mbed_official 146:f64d43ff0c18 1114 //@{
mbed_official 146:f64d43ff0c18 1115 #define BP_MCM_PID_PID (0U) //!< Bit position for MCM_PID_PID.
mbed_official 146:f64d43ff0c18 1116 #define BM_MCM_PID_PID (0x000000FFU) //!< Bit mask for MCM_PID_PID.
mbed_official 146:f64d43ff0c18 1117 #define BS_MCM_PID_PID (8U) //!< Bit field size in bits for MCM_PID_PID.
mbed_official 146:f64d43ff0c18 1118
mbed_official 146:f64d43ff0c18 1119 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1120 //! @brief Read current value of the MCM_PID_PID field.
mbed_official 146:f64d43ff0c18 1121 #define BR_MCM_PID_PID (HW_MCM_PID.B.PID)
mbed_official 146:f64d43ff0c18 1122 #endif
mbed_official 146:f64d43ff0c18 1123
mbed_official 146:f64d43ff0c18 1124 //! @brief Format value for bitfield MCM_PID_PID.
mbed_official 146:f64d43ff0c18 1125 #define BF_MCM_PID_PID(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_PID_PID), uint32_t) & BM_MCM_PID_PID)
mbed_official 146:f64d43ff0c18 1126
mbed_official 146:f64d43ff0c18 1127 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1128 //! @brief Set the PID field to a new value.
mbed_official 146:f64d43ff0c18 1129 #define BW_MCM_PID_PID(v) (HW_MCM_PID_WR((HW_MCM_PID_RD() & ~BM_MCM_PID_PID) | BF_MCM_PID_PID(v)))
mbed_official 146:f64d43ff0c18 1130 #endif
mbed_official 146:f64d43ff0c18 1131 //@}
mbed_official 146:f64d43ff0c18 1132
mbed_official 146:f64d43ff0c18 1133 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1134 // hw_mcm_t - module struct
mbed_official 146:f64d43ff0c18 1135 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1136 /*!
mbed_official 146:f64d43ff0c18 1137 * @brief All MCM module registers.
mbed_official 146:f64d43ff0c18 1138 */
mbed_official 146:f64d43ff0c18 1139 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1140 #pragma pack(1)
mbed_official 146:f64d43ff0c18 1141 typedef struct _hw_mcm
mbed_official 146:f64d43ff0c18 1142 {
mbed_official 146:f64d43ff0c18 1143 uint8_t _reserved0[8];
mbed_official 146:f64d43ff0c18 1144 __I hw_mcm_plasc_t PLASC; //!< [0x8] Crossbar Switch (AXBS) Slave Configuration
mbed_official 146:f64d43ff0c18 1145 __I hw_mcm_plamc_t PLAMC; //!< [0xA] Crossbar Switch (AXBS) Master Configuration
mbed_official 146:f64d43ff0c18 1146 __IO hw_mcm_cr_t CR; //!< [0xC] Control Register
mbed_official 146:f64d43ff0c18 1147 __IO hw_mcm_isr_t ISR; //!< [0x10] Interrupt Status Register
mbed_official 146:f64d43ff0c18 1148 __IO hw_mcm_etbcc_t ETBCC; //!< [0x14] ETB Counter Control register
mbed_official 146:f64d43ff0c18 1149 __IO hw_mcm_etbrl_t ETBRL; //!< [0x18] ETB Reload register
mbed_official 146:f64d43ff0c18 1150 __I hw_mcm_etbcnt_t ETBCNT; //!< [0x1C] ETB Counter Value register
mbed_official 146:f64d43ff0c18 1151 uint8_t _reserved1[16];
mbed_official 146:f64d43ff0c18 1152 __IO hw_mcm_pid_t PID; //!< [0x30] Process ID register
mbed_official 146:f64d43ff0c18 1153 } hw_mcm_t;
mbed_official 146:f64d43ff0c18 1154 #pragma pack()
mbed_official 146:f64d43ff0c18 1155
mbed_official 146:f64d43ff0c18 1156 //! @brief Macro to access all MCM registers.
mbed_official 146:f64d43ff0c18 1157 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 146:f64d43ff0c18 1158 //! use the '&' operator, like <code>&HW_MCM</code>.
mbed_official 146:f64d43ff0c18 1159 #define HW_MCM (*(hw_mcm_t *) REGS_MCM_BASE)
mbed_official 146:f64d43ff0c18 1160 #endif
mbed_official 146:f64d43ff0c18 1161
mbed_official 146:f64d43ff0c18 1162 #endif // __HW_MCM_REGISTERS_H__
mbed_official 146:f64d43ff0c18 1163 // v22/130726/0.9
mbed_official 146:f64d43ff0c18 1164 // EOF