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targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_i2c.h@149:1fb5f62b92bd, 2014-04-03 (annotated)

Committer:: mbed_official
Date:: Thu Apr 03 11:45:06 2014 +0100
Revision:: 149:1fb5f62b92bd
Parent:: targets/hal/TARGET_Freescale/TARGET_KSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_i2c.h@146:f64d43ff0c18

Synchronized with git revision 220c0bb39ceee40016e1e86350c058963d01ed42



Full URL: https://github.com/mbedmicro/mbed/commit/220c0bb39ceee40016e1e86350c058963d01ed42/

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	146:f64d43ff0c18	1	/*
mbed_official	146:f64d43ff0c18	2	* Copyright (c) 2014, Freescale Semiconductor, Inc.
mbed_official	146:f64d43ff0c18	3	* All rights reserved.
mbed_official	146:f64d43ff0c18	4	*
mbed_official	146:f64d43ff0c18	5	* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official	146:f64d43ff0c18	6	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official	146:f64d43ff0c18	7	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
mbed_official	146:f64d43ff0c18	8	* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
mbed_official	146:f64d43ff0c18	9	* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
mbed_official	146:f64d43ff0c18	10	* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official	146:f64d43ff0c18	11	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official	146:f64d43ff0c18	12	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
mbed_official	146:f64d43ff0c18	13	* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
mbed_official	146:f64d43ff0c18	14	* OF SUCH DAMAGE.
mbed_official	146:f64d43ff0c18	15	*/
mbed_official	146:f64d43ff0c18	16	/*
mbed_official	146:f64d43ff0c18	17	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official	146:f64d43ff0c18	18	*
mbed_official	146:f64d43ff0c18	19	* This file was generated automatically and any changes may be lost.
mbed_official	146:f64d43ff0c18	20	*/
mbed_official	146:f64d43ff0c18	21	#ifndef __HW_I2C_REGISTERS_H__
mbed_official	146:f64d43ff0c18	22	#define __HW_I2C_REGISTERS_H__
mbed_official	146:f64d43ff0c18	23
mbed_official	146:f64d43ff0c18	24	#include "regs.h"
mbed_official	146:f64d43ff0c18	25
mbed_official	146:f64d43ff0c18	26	/*
mbed_official	146:f64d43ff0c18	27	* MK64F12 I2C
mbed_official	146:f64d43ff0c18	28	*
mbed_official	146:f64d43ff0c18	29	* Inter-Integrated Circuit
mbed_official	146:f64d43ff0c18	30	*
mbed_official	146:f64d43ff0c18	31	* Registers defined in this header file:
mbed_official	146:f64d43ff0c18	32	* - HW_I2C_A1 - I2C Address Register 1
mbed_official	146:f64d43ff0c18	33	* - HW_I2C_F - I2C Frequency Divider register
mbed_official	146:f64d43ff0c18	34	* - HW_I2C_C1 - I2C Control Register 1
mbed_official	146:f64d43ff0c18	35	* - HW_I2C_S - I2C Status register
mbed_official	146:f64d43ff0c18	36	* - HW_I2C_D - I2C Data I/O register
mbed_official	146:f64d43ff0c18	37	* - HW_I2C_C2 - I2C Control Register 2
mbed_official	146:f64d43ff0c18	38	* - HW_I2C_FLT - I2C Programmable Input Glitch Filter register
mbed_official	146:f64d43ff0c18	39	* - HW_I2C_RA - I2C Range Address register
mbed_official	146:f64d43ff0c18	40	* - HW_I2C_SMB - I2C SMBus Control and Status register
mbed_official	146:f64d43ff0c18	41	* - HW_I2C_A2 - I2C Address Register 2
mbed_official	146:f64d43ff0c18	42	* - HW_I2C_SLTH - I2C SCL Low Timeout Register High
mbed_official	146:f64d43ff0c18	43	* - HW_I2C_SLTL - I2C SCL Low Timeout Register Low
mbed_official	146:f64d43ff0c18	44	*
mbed_official	146:f64d43ff0c18	45	* - hw_i2c_t - Struct containing all module registers.
mbed_official	146:f64d43ff0c18	46	*/
mbed_official	146:f64d43ff0c18	47
mbed_official	146:f64d43ff0c18	48	//! @name Module base addresses
mbed_official	146:f64d43ff0c18	49	//@{
mbed_official	146:f64d43ff0c18	50	#ifndef REGS_I2C_BASE
mbed_official	146:f64d43ff0c18	51	#define HW_I2C_INSTANCE_COUNT (3U) //!< Number of instances of the I2C module.
mbed_official	146:f64d43ff0c18	52	#define HW_I2C0 (0U) //!< Instance number for I2C0.
mbed_official	146:f64d43ff0c18	53	#define HW_I2C1 (1U) //!< Instance number for I2C1.
mbed_official	146:f64d43ff0c18	54	#define HW_I2C2 (2U) //!< Instance number for I2C2.
mbed_official	146:f64d43ff0c18	55	#define REGS_I2C0_BASE (0x40066000U) //!< Base address for I2C0.
mbed_official	146:f64d43ff0c18	56	#define REGS_I2C1_BASE (0x40067000U) //!< Base address for I2C1.
mbed_official	146:f64d43ff0c18	57	#define REGS_I2C2_BASE (0x400E6000U) //!< Base address for I2C2.
mbed_official	146:f64d43ff0c18	58
mbed_official	146:f64d43ff0c18	59	//! @brief Table of base addresses for I2C instances.
mbed_official	146:f64d43ff0c18	60	static const uint32_t __g_regs_I2C_base_addresses[] = {
mbed_official	146:f64d43ff0c18	61	REGS_I2C0_BASE,
mbed_official	146:f64d43ff0c18	62	REGS_I2C1_BASE,
mbed_official	146:f64d43ff0c18	63	REGS_I2C2_BASE,
mbed_official	146:f64d43ff0c18	64	};
mbed_official	146:f64d43ff0c18	65
mbed_official	146:f64d43ff0c18	66	//! @brief Get the base address of I2C by instance number.
mbed_official	146:f64d43ff0c18	67	//! @param x I2C instance number, from 0 through 2.
mbed_official	146:f64d43ff0c18	68	#define REGS_I2C_BASE(x) (__g_regs_I2C_base_addresses[(x)])
mbed_official	146:f64d43ff0c18	69
mbed_official	146:f64d43ff0c18	70	//! @brief Get the instance number given a base address.
mbed_official	146:f64d43ff0c18	71	//! @param b Base address for an instance of I2C.
mbed_official	146:f64d43ff0c18	72	#define REGS_I2C_INSTANCE(b) ((b) == REGS_I2C0_BASE ? HW_I2C0 : (b) == REGS_I2C1_BASE ? HW_I2C1 : (b) == REGS_I2C2_BASE ? HW_I2C2 : 0)
mbed_official	146:f64d43ff0c18	73	#endif
mbed_official	146:f64d43ff0c18	74	//@}
mbed_official	146:f64d43ff0c18	75
mbed_official	146:f64d43ff0c18	76	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	77	// HW_I2C_A1 - I2C Address Register 1
mbed_official	146:f64d43ff0c18	78	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	79
mbed_official	146:f64d43ff0c18	80	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	81	/*!
mbed_official	146:f64d43ff0c18	82	* @brief HW_I2C_A1 - I2C Address Register 1 (RW)
mbed_official	146:f64d43ff0c18	83	*
mbed_official	146:f64d43ff0c18	84	* Reset value: 0x00U
mbed_official	146:f64d43ff0c18	85	*
mbed_official	146:f64d43ff0c18	86	* This register contains the slave address to be used by the I2C module.
mbed_official	146:f64d43ff0c18	87	*/
mbed_official	146:f64d43ff0c18	88	typedef union _hw_i2c_a1
mbed_official	146:f64d43ff0c18	89	{
mbed_official	146:f64d43ff0c18	90	uint8_t U;
mbed_official	146:f64d43ff0c18	91	struct _hw_i2c_a1_bitfields
mbed_official	146:f64d43ff0c18	92	{
mbed_official	146:f64d43ff0c18	93	uint8_t RESERVED0 : 1; //!< [0]
mbed_official	146:f64d43ff0c18	94	uint8_t AD : 7; //!< [7:1] Address
mbed_official	146:f64d43ff0c18	95	} B;
mbed_official	146:f64d43ff0c18	96	} hw_i2c_a1_t;
mbed_official	146:f64d43ff0c18	97	#endif
mbed_official	146:f64d43ff0c18	98
mbed_official	146:f64d43ff0c18	99	/*!
mbed_official	146:f64d43ff0c18	100	* @name Constants and macros for entire I2C_A1 register
mbed_official	146:f64d43ff0c18	101	*/
mbed_official	146:f64d43ff0c18	102	//@{
mbed_official	146:f64d43ff0c18	103	#define HW_I2C_A1_ADDR(x) (REGS_I2C_BASE(x) + 0x0U)
mbed_official	146:f64d43ff0c18	104
mbed_official	146:f64d43ff0c18	105	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	106	#define HW_I2C_A1(x) ((__IO hw_i2c_a1_t ) HW_I2C_A1_ADDR(x))
mbed_official	146:f64d43ff0c18	107	#define HW_I2C_A1_RD(x) (HW_I2C_A1(x).U)
mbed_official	146:f64d43ff0c18	108	#define HW_I2C_A1_WR(x, v) (HW_I2C_A1(x).U = (v))
mbed_official	146:f64d43ff0c18	109	#define HW_I2C_A1_SET(x, v) (HW_I2C_A1_WR(x, HW_I2C_A1_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	110	#define HW_I2C_A1_CLR(x, v) (HW_I2C_A1_WR(x, HW_I2C_A1_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	111	#define HW_I2C_A1_TOG(x, v) (HW_I2C_A1_WR(x, HW_I2C_A1_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	112	#endif
mbed_official	146:f64d43ff0c18	113	//@}
mbed_official	146:f64d43ff0c18	114
mbed_official	146:f64d43ff0c18	115	/*
mbed_official	146:f64d43ff0c18	116	* Constants & macros for individual I2C_A1 bitfields
mbed_official	146:f64d43ff0c18	117	*/
mbed_official	146:f64d43ff0c18	118
mbed_official	146:f64d43ff0c18	119	/*!
mbed_official	146:f64d43ff0c18	120	* @name Register I2C_A1, field AD[7:1] (RW)
mbed_official	146:f64d43ff0c18	121	*
mbed_official	146:f64d43ff0c18	122	* Contains the primary slave address used by the I2C module when it is
mbed_official	146:f64d43ff0c18	123	* addressed as a slave. This field is used in the 7-bit address scheme and the lower
mbed_official	146:f64d43ff0c18	124	* seven bits in the 10-bit address scheme.
mbed_official	146:f64d43ff0c18	125	*/
mbed_official	146:f64d43ff0c18	126	//@{
mbed_official	146:f64d43ff0c18	127	#define BP_I2C_A1_AD (1U) //!< Bit position for I2C_A1_AD.
mbed_official	146:f64d43ff0c18	128	#define BM_I2C_A1_AD (0xFEU) //!< Bit mask for I2C_A1_AD.
mbed_official	146:f64d43ff0c18	129	#define BS_I2C_A1_AD (7U) //!< Bit field size in bits for I2C_A1_AD.
mbed_official	146:f64d43ff0c18	130
mbed_official	146:f64d43ff0c18	131	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	132	//! @brief Read current value of the I2C_A1_AD field.
mbed_official	146:f64d43ff0c18	133	#define BR_I2C_A1_AD(x) (HW_I2C_A1(x).B.AD)
mbed_official	146:f64d43ff0c18	134	#endif
mbed_official	146:f64d43ff0c18	135
mbed_official	146:f64d43ff0c18	136	//! @brief Format value for bitfield I2C_A1_AD.
mbed_official	146:f64d43ff0c18	137	#define BF_I2C_A1_AD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_A1_AD), uint8_t) & BM_I2C_A1_AD)
mbed_official	146:f64d43ff0c18	138
mbed_official	146:f64d43ff0c18	139	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	140	//! @brief Set the AD field to a new value.
mbed_official	146:f64d43ff0c18	141	#define BW_I2C_A1_AD(x, v) (HW_I2C_A1_WR(x, (HW_I2C_A1_RD(x) & ~BM_I2C_A1_AD) \| BF_I2C_A1_AD(v)))
mbed_official	146:f64d43ff0c18	142	#endif
mbed_official	146:f64d43ff0c18	143	//@}
mbed_official	146:f64d43ff0c18	144
mbed_official	146:f64d43ff0c18	145	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	146	// HW_I2C_F - I2C Frequency Divider register
mbed_official	146:f64d43ff0c18	147	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	148
mbed_official	146:f64d43ff0c18	149	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	150	/*!
mbed_official	146:f64d43ff0c18	151	* @brief HW_I2C_F - I2C Frequency Divider register (RW)
mbed_official	146:f64d43ff0c18	152	*
mbed_official	146:f64d43ff0c18	153	* Reset value: 0x00U
mbed_official	146:f64d43ff0c18	154	*/
mbed_official	146:f64d43ff0c18	155	typedef union _hw_i2c_f
mbed_official	146:f64d43ff0c18	156	{
mbed_official	146:f64d43ff0c18	157	uint8_t U;
mbed_official	146:f64d43ff0c18	158	struct _hw_i2c_f_bitfields
mbed_official	146:f64d43ff0c18	159	{
mbed_official	146:f64d43ff0c18	160	uint8_t ICR : 6; //!< [5:0] ClockRate
mbed_official	146:f64d43ff0c18	161	uint8_t MULT : 2; //!< [7:6] Multiplier Factor
mbed_official	146:f64d43ff0c18	162	} B;
mbed_official	146:f64d43ff0c18	163	} hw_i2c_f_t;
mbed_official	146:f64d43ff0c18	164	#endif
mbed_official	146:f64d43ff0c18	165
mbed_official	146:f64d43ff0c18	166	/*!
mbed_official	146:f64d43ff0c18	167	* @name Constants and macros for entire I2C_F register
mbed_official	146:f64d43ff0c18	168	*/
mbed_official	146:f64d43ff0c18	169	//@{
mbed_official	146:f64d43ff0c18	170	#define HW_I2C_F_ADDR(x) (REGS_I2C_BASE(x) + 0x1U)
mbed_official	146:f64d43ff0c18	171
mbed_official	146:f64d43ff0c18	172	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	173	#define HW_I2C_F(x) ((__IO hw_i2c_f_t ) HW_I2C_F_ADDR(x))
mbed_official	146:f64d43ff0c18	174	#define HW_I2C_F_RD(x) (HW_I2C_F(x).U)
mbed_official	146:f64d43ff0c18	175	#define HW_I2C_F_WR(x, v) (HW_I2C_F(x).U = (v))
mbed_official	146:f64d43ff0c18	176	#define HW_I2C_F_SET(x, v) (HW_I2C_F_WR(x, HW_I2C_F_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	177	#define HW_I2C_F_CLR(x, v) (HW_I2C_F_WR(x, HW_I2C_F_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	178	#define HW_I2C_F_TOG(x, v) (HW_I2C_F_WR(x, HW_I2C_F_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	179	#endif
mbed_official	146:f64d43ff0c18	180	//@}
mbed_official	146:f64d43ff0c18	181
mbed_official	146:f64d43ff0c18	182	/*
mbed_official	146:f64d43ff0c18	183	* Constants & macros for individual I2C_F bitfields
mbed_official	146:f64d43ff0c18	184	*/
mbed_official	146:f64d43ff0c18	185
mbed_official	146:f64d43ff0c18	186	/*!
mbed_official	146:f64d43ff0c18	187	* @name Register I2C_F, field ICR[5:0] (RW)
mbed_official	146:f64d43ff0c18	188	*
mbed_official	146:f64d43ff0c18	189	* Prescales the I2C module clock for bit rate selection. This field and the
mbed_official	146:f64d43ff0c18	190	* MULT field determine the I2C baud rate, the SDA hold time, the SCL start hold
mbed_official	146:f64d43ff0c18	191	* time, and the SCL stop hold time. For a list of values corresponding to each ICR
mbed_official	146:f64d43ff0c18	192	* setting, see I2C divider and hold values. The SCL divider multiplied by
mbed_official	146:f64d43ff0c18	193	* multiplier factor (mul) determines the I2C baud rate. I2C baud rate = I2C module
mbed_official	146:f64d43ff0c18	194	* clock speed (Hz)/(mul * SCL divider) The SDA hold time is the delay from the
mbed_official	146:f64d43ff0c18	195	* falling edge of SCL (I2C clock) to the changing of SDA (I2C data). SDA hold time =
mbed_official	146:f64d43ff0c18	196	* I2C module clock period (s) * mul * SDA hold value The SCL start hold time is
mbed_official	146:f64d43ff0c18	197	* the delay from the falling edge of SDA (I2C data) while SCL is high (start
mbed_official	146:f64d43ff0c18	198	* condition) to the falling edge of SCL (I2C clock). SCL start hold time = I2C
mbed_official	146:f64d43ff0c18	199	* module clock period (s) * mul * SCL start hold value The SCL stop hold time is
mbed_official	146:f64d43ff0c18	200	* the delay from the rising edge of SCL (I2C clock) to the rising edge of SDA (I2C
mbed_official	146:f64d43ff0c18	201	* data) while SCL is high (stop condition). SCL stop hold time = I2C module
mbed_official	146:f64d43ff0c18	202	* clock period (s) * mul * SCL stop hold value For example, if the I2C module clock
mbed_official	146:f64d43ff0c18	203	* speed is 8 MHz, the following table shows the possible hold time values with
mbed_official	146:f64d43ff0c18	204	* different ICR and MULT selections to achieve an I2C baud rate of 100 kbit/s.
mbed_official	146:f64d43ff0c18	205	* MULT ICR Hold times (μs) SDA SCL Start SCL Stop 2h 00h 3.500 3.000 5.500 1h
mbed_official	146:f64d43ff0c18	206	* 07h 2.500 4.000 5.250 1h 0Bh 2.250 4.000 5.250 0h 14h 2.125 4.250 5.125 0h 18h
mbed_official	146:f64d43ff0c18	207	* 1.125 4.750 5.125
mbed_official	146:f64d43ff0c18	208	*/
mbed_official	146:f64d43ff0c18	209	//@{
mbed_official	146:f64d43ff0c18	210	#define BP_I2C_F_ICR (0U) //!< Bit position for I2C_F_ICR.
mbed_official	146:f64d43ff0c18	211	#define BM_I2C_F_ICR (0x3FU) //!< Bit mask for I2C_F_ICR.
mbed_official	146:f64d43ff0c18	212	#define BS_I2C_F_ICR (6U) //!< Bit field size in bits for I2C_F_ICR.
mbed_official	146:f64d43ff0c18	213
mbed_official	146:f64d43ff0c18	214	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	215	//! @brief Read current value of the I2C_F_ICR field.
mbed_official	146:f64d43ff0c18	216	#define BR_I2C_F_ICR(x) (HW_I2C_F(x).B.ICR)
mbed_official	146:f64d43ff0c18	217	#endif
mbed_official	146:f64d43ff0c18	218
mbed_official	146:f64d43ff0c18	219	//! @brief Format value for bitfield I2C_F_ICR.
mbed_official	146:f64d43ff0c18	220	#define BF_I2C_F_ICR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_F_ICR), uint8_t) & BM_I2C_F_ICR)
mbed_official	146:f64d43ff0c18	221
mbed_official	146:f64d43ff0c18	222	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	223	//! @brief Set the ICR field to a new value.
mbed_official	146:f64d43ff0c18	224	#define BW_I2C_F_ICR(x, v) (HW_I2C_F_WR(x, (HW_I2C_F_RD(x) & ~BM_I2C_F_ICR) \| BF_I2C_F_ICR(v)))
mbed_official	146:f64d43ff0c18	225	#endif
mbed_official	146:f64d43ff0c18	226	//@}
mbed_official	146:f64d43ff0c18	227
mbed_official	146:f64d43ff0c18	228	/*!
mbed_official	146:f64d43ff0c18	229	* @name Register I2C_F, field MULT[7:6] (RW)
mbed_official	146:f64d43ff0c18	230	*
mbed_official	146:f64d43ff0c18	231	* Defines the multiplier factor (mul). This factor is used along with the SCL
mbed_official	146:f64d43ff0c18	232	* divider to generate the I2C baud rate.
mbed_official	146:f64d43ff0c18	233	*
mbed_official	146:f64d43ff0c18	234	* Values:
mbed_official	146:f64d43ff0c18	235	* - 00 - mul = 1
mbed_official	146:f64d43ff0c18	236	* - 01 - mul = 2
mbed_official	146:f64d43ff0c18	237	* - 10 - mul = 4
mbed_official	146:f64d43ff0c18	238	* - 11 - Reserved
mbed_official	146:f64d43ff0c18	239	*/
mbed_official	146:f64d43ff0c18	240	//@{
mbed_official	146:f64d43ff0c18	241	#define BP_I2C_F_MULT (6U) //!< Bit position for I2C_F_MULT.
mbed_official	146:f64d43ff0c18	242	#define BM_I2C_F_MULT (0xC0U) //!< Bit mask for I2C_F_MULT.
mbed_official	146:f64d43ff0c18	243	#define BS_I2C_F_MULT (2U) //!< Bit field size in bits for I2C_F_MULT.
mbed_official	146:f64d43ff0c18	244
mbed_official	146:f64d43ff0c18	245	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	246	//! @brief Read current value of the I2C_F_MULT field.
mbed_official	146:f64d43ff0c18	247	#define BR_I2C_F_MULT(x) (HW_I2C_F(x).B.MULT)
mbed_official	146:f64d43ff0c18	248	#endif
mbed_official	146:f64d43ff0c18	249
mbed_official	146:f64d43ff0c18	250	//! @brief Format value for bitfield I2C_F_MULT.
mbed_official	146:f64d43ff0c18	251	#define BF_I2C_F_MULT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_F_MULT), uint8_t) & BM_I2C_F_MULT)
mbed_official	146:f64d43ff0c18	252
mbed_official	146:f64d43ff0c18	253	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	254	//! @brief Set the MULT field to a new value.
mbed_official	146:f64d43ff0c18	255	#define BW_I2C_F_MULT(x, v) (HW_I2C_F_WR(x, (HW_I2C_F_RD(x) & ~BM_I2C_F_MULT) \| BF_I2C_F_MULT(v)))
mbed_official	146:f64d43ff0c18	256	#endif
mbed_official	146:f64d43ff0c18	257	//@}
mbed_official	146:f64d43ff0c18	258
mbed_official	146:f64d43ff0c18	259	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	260	// HW_I2C_C1 - I2C Control Register 1
mbed_official	146:f64d43ff0c18	261	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	262
mbed_official	146:f64d43ff0c18	263	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	264	/*!
mbed_official	146:f64d43ff0c18	265	* @brief HW_I2C_C1 - I2C Control Register 1 (RW)
mbed_official	146:f64d43ff0c18	266	*
mbed_official	146:f64d43ff0c18	267	* Reset value: 0x00U
mbed_official	146:f64d43ff0c18	268	*/
mbed_official	146:f64d43ff0c18	269	typedef union _hw_i2c_c1
mbed_official	146:f64d43ff0c18	270	{
mbed_official	146:f64d43ff0c18	271	uint8_t U;
mbed_official	146:f64d43ff0c18	272	struct _hw_i2c_c1_bitfields
mbed_official	146:f64d43ff0c18	273	{
mbed_official	146:f64d43ff0c18	274	uint8_t DMAEN : 1; //!< [0] DMA Enable
mbed_official	146:f64d43ff0c18	275	uint8_t WUEN : 1; //!< [1] Wakeup Enable
mbed_official	146:f64d43ff0c18	276	uint8_t RSTA : 1; //!< [2] Repeat START
mbed_official	146:f64d43ff0c18	277	uint8_t TXAK : 1; //!< [3] Transmit Acknowledge Enable
mbed_official	146:f64d43ff0c18	278	uint8_t TX : 1; //!< [4] Transmit Mode Select
mbed_official	146:f64d43ff0c18	279	uint8_t MST : 1; //!< [5] Master Mode Select
mbed_official	146:f64d43ff0c18	280	uint8_t IICIE : 1; //!< [6] I2C Interrupt Enable
mbed_official	146:f64d43ff0c18	281	uint8_t IICEN : 1; //!< [7] I2C Enable
mbed_official	146:f64d43ff0c18	282	} B;
mbed_official	146:f64d43ff0c18	283	} hw_i2c_c1_t;
mbed_official	146:f64d43ff0c18	284	#endif
mbed_official	146:f64d43ff0c18	285
mbed_official	146:f64d43ff0c18	286	/*!
mbed_official	146:f64d43ff0c18	287	* @name Constants and macros for entire I2C_C1 register
mbed_official	146:f64d43ff0c18	288	*/
mbed_official	146:f64d43ff0c18	289	//@{
mbed_official	146:f64d43ff0c18	290	#define HW_I2C_C1_ADDR(x) (REGS_I2C_BASE(x) + 0x2U)
mbed_official	146:f64d43ff0c18	291
mbed_official	146:f64d43ff0c18	292	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	293	#define HW_I2C_C1(x) ((__IO hw_i2c_c1_t ) HW_I2C_C1_ADDR(x))
mbed_official	146:f64d43ff0c18	294	#define HW_I2C_C1_RD(x) (HW_I2C_C1(x).U)
mbed_official	146:f64d43ff0c18	295	#define HW_I2C_C1_WR(x, v) (HW_I2C_C1(x).U = (v))
mbed_official	146:f64d43ff0c18	296	#define HW_I2C_C1_SET(x, v) (HW_I2C_C1_WR(x, HW_I2C_C1_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	297	#define HW_I2C_C1_CLR(x, v) (HW_I2C_C1_WR(x, HW_I2C_C1_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	298	#define HW_I2C_C1_TOG(x, v) (HW_I2C_C1_WR(x, HW_I2C_C1_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	299	#endif
mbed_official	146:f64d43ff0c18	300	//@}
mbed_official	146:f64d43ff0c18	301
mbed_official	146:f64d43ff0c18	302	/*
mbed_official	146:f64d43ff0c18	303	* Constants & macros for individual I2C_C1 bitfields
mbed_official	146:f64d43ff0c18	304	*/
mbed_official	146:f64d43ff0c18	305
mbed_official	146:f64d43ff0c18	306	/*!
mbed_official	146:f64d43ff0c18	307	* @name Register I2C_C1, field DMAEN[0] (RW)
mbed_official	146:f64d43ff0c18	308	*
mbed_official	146:f64d43ff0c18	309	* Enables or disables the DMA function.
mbed_official	146:f64d43ff0c18	310	*
mbed_official	146:f64d43ff0c18	311	* Values:
mbed_official	146:f64d43ff0c18	312	* - 0 - All DMA signalling disabled.
mbed_official	146:f64d43ff0c18	313	* - 1 - DMA transfer is enabled. While SMB[FACK] = 0, the following conditions
mbed_official	146:f64d43ff0c18	314	* trigger the DMA request: a data byte is received, and either address or
mbed_official	146:f64d43ff0c18	315	* data is transmitted. (ACK/NACK is automatic) the first byte received matches
mbed_official	146:f64d43ff0c18	316	* the A1 register or is a general call address. If any address matching
mbed_official	146:f64d43ff0c18	317	* occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known
mbed_official	146:f64d43ff0c18	318	* from master to slave, then it is not required to check S[SRW]. With this
mbed_official	146:f64d43ff0c18	319	* assumption, DMA can also be used in this case. In other cases, if the master
mbed_official	146:f64d43ff0c18	320	* reads data from the slave, then it is required to rewrite the C1 register
mbed_official	146:f64d43ff0c18	321	* operation. With this assumption, DMA cannot be used. When FACK = 1, an
mbed_official	146:f64d43ff0c18	322	* address or a data byte is transmitted.
mbed_official	146:f64d43ff0c18	323	*/
mbed_official	146:f64d43ff0c18	324	//@{
mbed_official	146:f64d43ff0c18	325	#define BP_I2C_C1_DMAEN (0U) //!< Bit position for I2C_C1_DMAEN.
mbed_official	146:f64d43ff0c18	326	#define BM_I2C_C1_DMAEN (0x01U) //!< Bit mask for I2C_C1_DMAEN.
mbed_official	146:f64d43ff0c18	327	#define BS_I2C_C1_DMAEN (1U) //!< Bit field size in bits for I2C_C1_DMAEN.
mbed_official	146:f64d43ff0c18	328
mbed_official	146:f64d43ff0c18	329	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	330	//! @brief Read current value of the I2C_C1_DMAEN field.
mbed_official	146:f64d43ff0c18	331	#define BR_I2C_C1_DMAEN(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_DMAEN))
mbed_official	146:f64d43ff0c18	332	#endif
mbed_official	146:f64d43ff0c18	333
mbed_official	146:f64d43ff0c18	334	//! @brief Format value for bitfield I2C_C1_DMAEN.
mbed_official	146:f64d43ff0c18	335	#define BF_I2C_C1_DMAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_DMAEN), uint8_t) & BM_I2C_C1_DMAEN)
mbed_official	146:f64d43ff0c18	336
mbed_official	146:f64d43ff0c18	337	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	338	//! @brief Set the DMAEN field to a new value.
mbed_official	146:f64d43ff0c18	339	#define BW_I2C_C1_DMAEN(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_DMAEN) = (v))
mbed_official	146:f64d43ff0c18	340	#endif
mbed_official	146:f64d43ff0c18	341	//@}
mbed_official	146:f64d43ff0c18	342
mbed_official	146:f64d43ff0c18	343	/*!
mbed_official	146:f64d43ff0c18	344	* @name Register I2C_C1, field WUEN[1] (RW)
mbed_official	146:f64d43ff0c18	345	*
mbed_official	146:f64d43ff0c18	346	* The I2C module can wake the MCU from low power mode with no peripheral bus
mbed_official	146:f64d43ff0c18	347	* running when slave address matching occurs.
mbed_official	146:f64d43ff0c18	348	*
mbed_official	146:f64d43ff0c18	349	* Values:
mbed_official	146:f64d43ff0c18	350	* - 0 - Normal operation. No interrupt generated when address matching in low
mbed_official	146:f64d43ff0c18	351	* power mode.
mbed_official	146:f64d43ff0c18	352	* - 1 - Enables the wakeup function in low power mode.
mbed_official	146:f64d43ff0c18	353	*/
mbed_official	146:f64d43ff0c18	354	//@{
mbed_official	146:f64d43ff0c18	355	#define BP_I2C_C1_WUEN (1U) //!< Bit position for I2C_C1_WUEN.
mbed_official	146:f64d43ff0c18	356	#define BM_I2C_C1_WUEN (0x02U) //!< Bit mask for I2C_C1_WUEN.
mbed_official	146:f64d43ff0c18	357	#define BS_I2C_C1_WUEN (1U) //!< Bit field size in bits for I2C_C1_WUEN.
mbed_official	146:f64d43ff0c18	358
mbed_official	146:f64d43ff0c18	359	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	360	//! @brief Read current value of the I2C_C1_WUEN field.
mbed_official	146:f64d43ff0c18	361	#define BR_I2C_C1_WUEN(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_WUEN))
mbed_official	146:f64d43ff0c18	362	#endif
mbed_official	146:f64d43ff0c18	363
mbed_official	146:f64d43ff0c18	364	//! @brief Format value for bitfield I2C_C1_WUEN.
mbed_official	146:f64d43ff0c18	365	#define BF_I2C_C1_WUEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_WUEN), uint8_t) & BM_I2C_C1_WUEN)
mbed_official	146:f64d43ff0c18	366
mbed_official	146:f64d43ff0c18	367	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	368	//! @brief Set the WUEN field to a new value.
mbed_official	146:f64d43ff0c18	369	#define BW_I2C_C1_WUEN(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_WUEN) = (v))
mbed_official	146:f64d43ff0c18	370	#endif
mbed_official	146:f64d43ff0c18	371	//@}
mbed_official	146:f64d43ff0c18	372
mbed_official	146:f64d43ff0c18	373	/*!
mbed_official	146:f64d43ff0c18	374	* @name Register I2C_C1, field RSTA[2] (WORZ)
mbed_official	146:f64d43ff0c18	375	*
mbed_official	146:f64d43ff0c18	376	* Writing 1 to this bit generates a repeated START condition provided it is the
mbed_official	146:f64d43ff0c18	377	* current master. This bit will always be read as 0. Attempting a repeat at the
mbed_official	146:f64d43ff0c18	378	* wrong time results in loss of arbitration.
mbed_official	146:f64d43ff0c18	379	*/
mbed_official	146:f64d43ff0c18	380	//@{
mbed_official	146:f64d43ff0c18	381	#define BP_I2C_C1_RSTA (2U) //!< Bit position for I2C_C1_RSTA.
mbed_official	146:f64d43ff0c18	382	#define BM_I2C_C1_RSTA (0x04U) //!< Bit mask for I2C_C1_RSTA.
mbed_official	146:f64d43ff0c18	383	#define BS_I2C_C1_RSTA (1U) //!< Bit field size in bits for I2C_C1_RSTA.
mbed_official	146:f64d43ff0c18	384
mbed_official	146:f64d43ff0c18	385	//! @brief Format value for bitfield I2C_C1_RSTA.
mbed_official	146:f64d43ff0c18	386	#define BF_I2C_C1_RSTA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_RSTA), uint8_t) & BM_I2C_C1_RSTA)
mbed_official	146:f64d43ff0c18	387
mbed_official	146:f64d43ff0c18	388	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	389	//! @brief Set the RSTA field to a new value.
mbed_official	146:f64d43ff0c18	390	#define BW_I2C_C1_RSTA(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_RSTA) = (v))
mbed_official	146:f64d43ff0c18	391	#endif
mbed_official	146:f64d43ff0c18	392	//@}
mbed_official	146:f64d43ff0c18	393
mbed_official	146:f64d43ff0c18	394	/*!
mbed_official	146:f64d43ff0c18	395	* @name Register I2C_C1, field TXAK[3] (RW)
mbed_official	146:f64d43ff0c18	396	*
mbed_official	146:f64d43ff0c18	397	* Specifies the value driven onto the SDA during data acknowledge cycles for
mbed_official	146:f64d43ff0c18	398	* both master and slave receivers. The value of SMB[FACK] affects NACK/ACK
mbed_official	146:f64d43ff0c18	399	* generation. SCL is held low until TXAK is written.
mbed_official	146:f64d43ff0c18	400	*
mbed_official	146:f64d43ff0c18	401	* Values:
mbed_official	146:f64d43ff0c18	402	* - 0 - An acknowledge signal is sent to the bus on the following receiving
mbed_official	146:f64d43ff0c18	403	* byte (if FACK is cleared) or the current receiving byte (if FACK is set).
mbed_official	146:f64d43ff0c18	404	* - 1 - No acknowledge signal is sent to the bus on the following receiving
mbed_official	146:f64d43ff0c18	405	* data byte (if FACK is cleared) or the current receiving data byte (if FACK is
mbed_official	146:f64d43ff0c18	406	* set).
mbed_official	146:f64d43ff0c18	407	*/
mbed_official	146:f64d43ff0c18	408	//@{
mbed_official	146:f64d43ff0c18	409	#define BP_I2C_C1_TXAK (3U) //!< Bit position for I2C_C1_TXAK.
mbed_official	146:f64d43ff0c18	410	#define BM_I2C_C1_TXAK (0x08U) //!< Bit mask for I2C_C1_TXAK.
mbed_official	146:f64d43ff0c18	411	#define BS_I2C_C1_TXAK (1U) //!< Bit field size in bits for I2C_C1_TXAK.
mbed_official	146:f64d43ff0c18	412
mbed_official	146:f64d43ff0c18	413	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	414	//! @brief Read current value of the I2C_C1_TXAK field.
mbed_official	146:f64d43ff0c18	415	#define BR_I2C_C1_TXAK(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TXAK))
mbed_official	146:f64d43ff0c18	416	#endif
mbed_official	146:f64d43ff0c18	417
mbed_official	146:f64d43ff0c18	418	//! @brief Format value for bitfield I2C_C1_TXAK.
mbed_official	146:f64d43ff0c18	419	#define BF_I2C_C1_TXAK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_TXAK), uint8_t) & BM_I2C_C1_TXAK)
mbed_official	146:f64d43ff0c18	420
mbed_official	146:f64d43ff0c18	421	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	422	//! @brief Set the TXAK field to a new value.
mbed_official	146:f64d43ff0c18	423	#define BW_I2C_C1_TXAK(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TXAK) = (v))
mbed_official	146:f64d43ff0c18	424	#endif
mbed_official	146:f64d43ff0c18	425	//@}
mbed_official	146:f64d43ff0c18	426
mbed_official	146:f64d43ff0c18	427	/*!
mbed_official	146:f64d43ff0c18	428	* @name Register I2C_C1, field TX[4] (RW)
mbed_official	146:f64d43ff0c18	429	*
mbed_official	146:f64d43ff0c18	430	* Selects the direction of master and slave transfers. In master mode this bit
mbed_official	146:f64d43ff0c18	431	* must be set according to the type of transfer required. Therefore, for address
mbed_official	146:f64d43ff0c18	432	* cycles, this bit is always set. When addressed as a slave this bit must be
mbed_official	146:f64d43ff0c18	433	* set by software according to the SRW bit in the status register.
mbed_official	146:f64d43ff0c18	434	*
mbed_official	146:f64d43ff0c18	435	* Values:
mbed_official	146:f64d43ff0c18	436	* - 0 - Receive
mbed_official	146:f64d43ff0c18	437	* - 1 - Transmit
mbed_official	146:f64d43ff0c18	438	*/
mbed_official	146:f64d43ff0c18	439	//@{
mbed_official	146:f64d43ff0c18	440	#define BP_I2C_C1_TX (4U) //!< Bit position for I2C_C1_TX.
mbed_official	146:f64d43ff0c18	441	#define BM_I2C_C1_TX (0x10U) //!< Bit mask for I2C_C1_TX.
mbed_official	146:f64d43ff0c18	442	#define BS_I2C_C1_TX (1U) //!< Bit field size in bits for I2C_C1_TX.
mbed_official	146:f64d43ff0c18	443
mbed_official	146:f64d43ff0c18	444	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	445	//! @brief Read current value of the I2C_C1_TX field.
mbed_official	146:f64d43ff0c18	446	#define BR_I2C_C1_TX(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TX))
mbed_official	146:f64d43ff0c18	447	#endif
mbed_official	146:f64d43ff0c18	448
mbed_official	146:f64d43ff0c18	449	//! @brief Format value for bitfield I2C_C1_TX.
mbed_official	146:f64d43ff0c18	450	#define BF_I2C_C1_TX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_TX), uint8_t) & BM_I2C_C1_TX)
mbed_official	146:f64d43ff0c18	451
mbed_official	146:f64d43ff0c18	452	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	453	//! @brief Set the TX field to a new value.
mbed_official	146:f64d43ff0c18	454	#define BW_I2C_C1_TX(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TX) = (v))
mbed_official	146:f64d43ff0c18	455	#endif
mbed_official	146:f64d43ff0c18	456	//@}
mbed_official	146:f64d43ff0c18	457
mbed_official	146:f64d43ff0c18	458	/*!
mbed_official	146:f64d43ff0c18	459	* @name Register I2C_C1, field MST[5] (RW)
mbed_official	146:f64d43ff0c18	460	*
mbed_official	146:f64d43ff0c18	461	* When MST is changed from 0 to 1, a START signal is generated on the bus and
mbed_official	146:f64d43ff0c18	462	* master mode is selected. When this bit changes from 1 to 0, a STOP signal is
mbed_official	146:f64d43ff0c18	463	* generated and the mode of operation changes from master to slave.
mbed_official	146:f64d43ff0c18	464	*
mbed_official	146:f64d43ff0c18	465	* Values:
mbed_official	146:f64d43ff0c18	466	* - 0 - Slave mode
mbed_official	146:f64d43ff0c18	467	* - 1 - Master mode
mbed_official	146:f64d43ff0c18	468	*/
mbed_official	146:f64d43ff0c18	469	//@{
mbed_official	146:f64d43ff0c18	470	#define BP_I2C_C1_MST (5U) //!< Bit position for I2C_C1_MST.
mbed_official	146:f64d43ff0c18	471	#define BM_I2C_C1_MST (0x20U) //!< Bit mask for I2C_C1_MST.
mbed_official	146:f64d43ff0c18	472	#define BS_I2C_C1_MST (1U) //!< Bit field size in bits for I2C_C1_MST.
mbed_official	146:f64d43ff0c18	473
mbed_official	146:f64d43ff0c18	474	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	475	//! @brief Read current value of the I2C_C1_MST field.
mbed_official	146:f64d43ff0c18	476	#define BR_I2C_C1_MST(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_MST))
mbed_official	146:f64d43ff0c18	477	#endif
mbed_official	146:f64d43ff0c18	478
mbed_official	146:f64d43ff0c18	479	//! @brief Format value for bitfield I2C_C1_MST.
mbed_official	146:f64d43ff0c18	480	#define BF_I2C_C1_MST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_MST), uint8_t) & BM_I2C_C1_MST)
mbed_official	146:f64d43ff0c18	481
mbed_official	146:f64d43ff0c18	482	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	483	//! @brief Set the MST field to a new value.
mbed_official	146:f64d43ff0c18	484	#define BW_I2C_C1_MST(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_MST) = (v))
mbed_official	146:f64d43ff0c18	485	#endif
mbed_official	146:f64d43ff0c18	486	//@}
mbed_official	146:f64d43ff0c18	487
mbed_official	146:f64d43ff0c18	488	/*!
mbed_official	146:f64d43ff0c18	489	* @name Register I2C_C1, field IICIE[6] (RW)
mbed_official	146:f64d43ff0c18	490	*
mbed_official	146:f64d43ff0c18	491	* Enables I2C interrupt requests.
mbed_official	146:f64d43ff0c18	492	*
mbed_official	146:f64d43ff0c18	493	* Values:
mbed_official	146:f64d43ff0c18	494	* - 0 - Disabled
mbed_official	146:f64d43ff0c18	495	* - 1 - Enabled
mbed_official	146:f64d43ff0c18	496	*/
mbed_official	146:f64d43ff0c18	497	//@{
mbed_official	146:f64d43ff0c18	498	#define BP_I2C_C1_IICIE (6U) //!< Bit position for I2C_C1_IICIE.
mbed_official	146:f64d43ff0c18	499	#define BM_I2C_C1_IICIE (0x40U) //!< Bit mask for I2C_C1_IICIE.
mbed_official	146:f64d43ff0c18	500	#define BS_I2C_C1_IICIE (1U) //!< Bit field size in bits for I2C_C1_IICIE.
mbed_official	146:f64d43ff0c18	501
mbed_official	146:f64d43ff0c18	502	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	503	//! @brief Read current value of the I2C_C1_IICIE field.
mbed_official	146:f64d43ff0c18	504	#define BR_I2C_C1_IICIE(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICIE))
mbed_official	146:f64d43ff0c18	505	#endif
mbed_official	146:f64d43ff0c18	506
mbed_official	146:f64d43ff0c18	507	//! @brief Format value for bitfield I2C_C1_IICIE.
mbed_official	146:f64d43ff0c18	508	#define BF_I2C_C1_IICIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_IICIE), uint8_t) & BM_I2C_C1_IICIE)
mbed_official	146:f64d43ff0c18	509
mbed_official	146:f64d43ff0c18	510	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	511	//! @brief Set the IICIE field to a new value.
mbed_official	146:f64d43ff0c18	512	#define BW_I2C_C1_IICIE(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICIE) = (v))
mbed_official	146:f64d43ff0c18	513	#endif
mbed_official	146:f64d43ff0c18	514	//@}
mbed_official	146:f64d43ff0c18	515
mbed_official	146:f64d43ff0c18	516	/*!
mbed_official	146:f64d43ff0c18	517	* @name Register I2C_C1, field IICEN[7] (RW)
mbed_official	146:f64d43ff0c18	518	*
mbed_official	146:f64d43ff0c18	519	* Enables I2C module operation.
mbed_official	146:f64d43ff0c18	520	*
mbed_official	146:f64d43ff0c18	521	* Values:
mbed_official	146:f64d43ff0c18	522	* - 0 - Disabled
mbed_official	146:f64d43ff0c18	523	* - 1 - Enabled
mbed_official	146:f64d43ff0c18	524	*/
mbed_official	146:f64d43ff0c18	525	//@{
mbed_official	146:f64d43ff0c18	526	#define BP_I2C_C1_IICEN (7U) //!< Bit position for I2C_C1_IICEN.
mbed_official	146:f64d43ff0c18	527	#define BM_I2C_C1_IICEN (0x80U) //!< Bit mask for I2C_C1_IICEN.
mbed_official	146:f64d43ff0c18	528	#define BS_I2C_C1_IICEN (1U) //!< Bit field size in bits for I2C_C1_IICEN.
mbed_official	146:f64d43ff0c18	529
mbed_official	146:f64d43ff0c18	530	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	531	//! @brief Read current value of the I2C_C1_IICEN field.
mbed_official	146:f64d43ff0c18	532	#define BR_I2C_C1_IICEN(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICEN))
mbed_official	146:f64d43ff0c18	533	#endif
mbed_official	146:f64d43ff0c18	534
mbed_official	146:f64d43ff0c18	535	//! @brief Format value for bitfield I2C_C1_IICEN.
mbed_official	146:f64d43ff0c18	536	#define BF_I2C_C1_IICEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_IICEN), uint8_t) & BM_I2C_C1_IICEN)
mbed_official	146:f64d43ff0c18	537
mbed_official	146:f64d43ff0c18	538	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	539	//! @brief Set the IICEN field to a new value.
mbed_official	146:f64d43ff0c18	540	#define BW_I2C_C1_IICEN(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICEN) = (v))
mbed_official	146:f64d43ff0c18	541	#endif
mbed_official	146:f64d43ff0c18	542	//@}
mbed_official	146:f64d43ff0c18	543
mbed_official	146:f64d43ff0c18	544	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	545	// HW_I2C_S - I2C Status register
mbed_official	146:f64d43ff0c18	546	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	547
mbed_official	146:f64d43ff0c18	548	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	549	/*!
mbed_official	146:f64d43ff0c18	550	* @brief HW_I2C_S - I2C Status register (RW)
mbed_official	146:f64d43ff0c18	551	*
mbed_official	146:f64d43ff0c18	552	* Reset value: 0x80U
mbed_official	146:f64d43ff0c18	553	*/
mbed_official	146:f64d43ff0c18	554	typedef union _hw_i2c_s
mbed_official	146:f64d43ff0c18	555	{
mbed_official	146:f64d43ff0c18	556	uint8_t U;
mbed_official	146:f64d43ff0c18	557	struct _hw_i2c_s_bitfields
mbed_official	146:f64d43ff0c18	558	{
mbed_official	146:f64d43ff0c18	559	uint8_t RXAK : 1; //!< [0] Receive Acknowledge
mbed_official	146:f64d43ff0c18	560	uint8_t IICIF : 1; //!< [1] Interrupt Flag
mbed_official	146:f64d43ff0c18	561	uint8_t SRW : 1; //!< [2] Slave Read/Write
mbed_official	146:f64d43ff0c18	562	uint8_t RAM : 1; //!< [3] Range Address Match
mbed_official	146:f64d43ff0c18	563	uint8_t ARBL : 1; //!< [4] Arbitration Lost
mbed_official	146:f64d43ff0c18	564	uint8_t BUSY : 1; //!< [5] Bus Busy
mbed_official	146:f64d43ff0c18	565	uint8_t IAAS : 1; //!< [6] Addressed As A Slave
mbed_official	146:f64d43ff0c18	566	uint8_t TCF : 1; //!< [7] Transfer Complete Flag
mbed_official	146:f64d43ff0c18	567	} B;
mbed_official	146:f64d43ff0c18	568	} hw_i2c_s_t;
mbed_official	146:f64d43ff0c18	569	#endif
mbed_official	146:f64d43ff0c18	570
mbed_official	146:f64d43ff0c18	571	/*!
mbed_official	146:f64d43ff0c18	572	* @name Constants and macros for entire I2C_S register
mbed_official	146:f64d43ff0c18	573	*/
mbed_official	146:f64d43ff0c18	574	//@{
mbed_official	146:f64d43ff0c18	575	#define HW_I2C_S_ADDR(x) (REGS_I2C_BASE(x) + 0x3U)
mbed_official	146:f64d43ff0c18	576
mbed_official	146:f64d43ff0c18	577	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	578	#define HW_I2C_S(x) ((__IO hw_i2c_s_t ) HW_I2C_S_ADDR(x))
mbed_official	146:f64d43ff0c18	579	#define HW_I2C_S_RD(x) (HW_I2C_S(x).U)
mbed_official	146:f64d43ff0c18	580	#define HW_I2C_S_WR(x, v) (HW_I2C_S(x).U = (v))
mbed_official	146:f64d43ff0c18	581	#define HW_I2C_S_SET(x, v) (HW_I2C_S_WR(x, HW_I2C_S_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	582	#define HW_I2C_S_CLR(x, v) (HW_I2C_S_WR(x, HW_I2C_S_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	583	#define HW_I2C_S_TOG(x, v) (HW_I2C_S_WR(x, HW_I2C_S_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	584	#endif
mbed_official	146:f64d43ff0c18	585	//@}
mbed_official	146:f64d43ff0c18	586
mbed_official	146:f64d43ff0c18	587	/*
mbed_official	146:f64d43ff0c18	588	* Constants & macros for individual I2C_S bitfields
mbed_official	146:f64d43ff0c18	589	*/
mbed_official	146:f64d43ff0c18	590
mbed_official	146:f64d43ff0c18	591	/*!
mbed_official	146:f64d43ff0c18	592	* @name Register I2C_S, field RXAK[0] (RO)
mbed_official	146:f64d43ff0c18	593	*
mbed_official	146:f64d43ff0c18	594	* Values:
mbed_official	146:f64d43ff0c18	595	* - 0 - Acknowledge signal was received after the completion of one byte of
mbed_official	146:f64d43ff0c18	596	* data transmission on the bus
mbed_official	146:f64d43ff0c18	597	* - 1 - No acknowledge signal detected
mbed_official	146:f64d43ff0c18	598	*/
mbed_official	146:f64d43ff0c18	599	//@{
mbed_official	146:f64d43ff0c18	600	#define BP_I2C_S_RXAK (0U) //!< Bit position for I2C_S_RXAK.
mbed_official	146:f64d43ff0c18	601	#define BM_I2C_S_RXAK (0x01U) //!< Bit mask for I2C_S_RXAK.
mbed_official	146:f64d43ff0c18	602	#define BS_I2C_S_RXAK (1U) //!< Bit field size in bits for I2C_S_RXAK.
mbed_official	146:f64d43ff0c18	603
mbed_official	146:f64d43ff0c18	604	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	605	//! @brief Read current value of the I2C_S_RXAK field.
mbed_official	146:f64d43ff0c18	606	#define BR_I2C_S_RXAK(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_RXAK))
mbed_official	146:f64d43ff0c18	607	#endif
mbed_official	146:f64d43ff0c18	608	//@}
mbed_official	146:f64d43ff0c18	609
mbed_official	146:f64d43ff0c18	610	/*!
mbed_official	146:f64d43ff0c18	611	* @name Register I2C_S, field IICIF[1] (W1C)
mbed_official	146:f64d43ff0c18	612	*
mbed_official	146:f64d43ff0c18	613	* This bit sets when an interrupt is pending. This bit must be cleared by
mbed_official	146:f64d43ff0c18	614	* software by writing 1 to it, such as in the interrupt routine. One of the following
mbed_official	146:f64d43ff0c18	615	* events can set this bit: One byte transfer, including ACK/NACK bit, completes
mbed_official	146:f64d43ff0c18	616	* if FACK is 0. An ACK or NACK is sent on the bus by writing 0 or 1 to TXAK
mbed_official	146:f64d43ff0c18	617	* after this bit is set in receive mode. One byte transfer, excluding ACK/NACK bit,
mbed_official	146:f64d43ff0c18	618	* completes if FACK is 1. Match of slave address to calling address including
mbed_official	146:f64d43ff0c18	619	* primary slave address, range slave address , alert response address, second
mbed_official	146:f64d43ff0c18	620	* slave address, or general call address. Arbitration lost In SMBus mode, any
mbed_official	146:f64d43ff0c18	621	* timeouts except SCL and SDA high timeouts I2C bus stop or start detection if the
mbed_official	146:f64d43ff0c18	622	* SSIE bit in the Input Glitch Filter register is 1 To clear the I2C bus stop or
mbed_official	146:f64d43ff0c18	623	* start detection interrupt: In the interrupt service routine, first clear the
mbed_official	146:f64d43ff0c18	624	* STOPF or STARTF bit in the Input Glitch Filter register by writing 1 to it, and
mbed_official	146:f64d43ff0c18	625	* then clear the IICIF bit. If this sequence is reversed, the IICIF bit is
mbed_official	146:f64d43ff0c18	626	* asserted again.
mbed_official	146:f64d43ff0c18	627	*
mbed_official	146:f64d43ff0c18	628	* Values:
mbed_official	146:f64d43ff0c18	629	* - 0 - No interrupt pending
mbed_official	146:f64d43ff0c18	630	* - 1 - Interrupt pending
mbed_official	146:f64d43ff0c18	631	*/
mbed_official	146:f64d43ff0c18	632	//@{
mbed_official	146:f64d43ff0c18	633	#define BP_I2C_S_IICIF (1U) //!< Bit position for I2C_S_IICIF.
mbed_official	146:f64d43ff0c18	634	#define BM_I2C_S_IICIF (0x02U) //!< Bit mask for I2C_S_IICIF.
mbed_official	146:f64d43ff0c18	635	#define BS_I2C_S_IICIF (1U) //!< Bit field size in bits for I2C_S_IICIF.
mbed_official	146:f64d43ff0c18	636
mbed_official	146:f64d43ff0c18	637	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	638	//! @brief Read current value of the I2C_S_IICIF field.
mbed_official	146:f64d43ff0c18	639	#define BR_I2C_S_IICIF(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IICIF))
mbed_official	146:f64d43ff0c18	640	#endif
mbed_official	146:f64d43ff0c18	641
mbed_official	146:f64d43ff0c18	642	//! @brief Format value for bitfield I2C_S_IICIF.
mbed_official	146:f64d43ff0c18	643	#define BF_I2C_S_IICIF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_S_IICIF), uint8_t) & BM_I2C_S_IICIF)
mbed_official	146:f64d43ff0c18	644
mbed_official	146:f64d43ff0c18	645	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	646	//! @brief Set the IICIF field to a new value.
mbed_official	146:f64d43ff0c18	647	#define BW_I2C_S_IICIF(x, v) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IICIF) = (v))
mbed_official	146:f64d43ff0c18	648	#endif
mbed_official	146:f64d43ff0c18	649	//@}
mbed_official	146:f64d43ff0c18	650
mbed_official	146:f64d43ff0c18	651	/*!
mbed_official	146:f64d43ff0c18	652	* @name Register I2C_S, field SRW[2] (RO)
mbed_official	146:f64d43ff0c18	653	*
mbed_official	146:f64d43ff0c18	654	* When addressed as a slave, SRW indicates the value of the R/W command bit of
mbed_official	146:f64d43ff0c18	655	* the calling address sent to the master.
mbed_official	146:f64d43ff0c18	656	*
mbed_official	146:f64d43ff0c18	657	* Values:
mbed_official	146:f64d43ff0c18	658	* - 0 - Slave receive, master writing to slave
mbed_official	146:f64d43ff0c18	659	* - 1 - Slave transmit, master reading from slave
mbed_official	146:f64d43ff0c18	660	*/
mbed_official	146:f64d43ff0c18	661	//@{
mbed_official	146:f64d43ff0c18	662	#define BP_I2C_S_SRW (2U) //!< Bit position for I2C_S_SRW.
mbed_official	146:f64d43ff0c18	663	#define BM_I2C_S_SRW (0x04U) //!< Bit mask for I2C_S_SRW.
mbed_official	146:f64d43ff0c18	664	#define BS_I2C_S_SRW (1U) //!< Bit field size in bits for I2C_S_SRW.
mbed_official	146:f64d43ff0c18	665
mbed_official	146:f64d43ff0c18	666	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	667	//! @brief Read current value of the I2C_S_SRW field.
mbed_official	146:f64d43ff0c18	668	#define BR_I2C_S_SRW(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_SRW))
mbed_official	146:f64d43ff0c18	669	#endif
mbed_official	146:f64d43ff0c18	670	//@}
mbed_official	146:f64d43ff0c18	671
mbed_official	146:f64d43ff0c18	672	/*!
mbed_official	146:f64d43ff0c18	673	* @name Register I2C_S, field RAM[3] (RW)
mbed_official	146:f64d43ff0c18	674	*
mbed_official	146:f64d43ff0c18	675	* This bit is set to 1 by any of the following conditions, if I2C_C2[RMEN] = 1:
mbed_official	146:f64d43ff0c18	676	* Any nonzero calling address is received that matches the address in the RA
mbed_official	146:f64d43ff0c18	677	* register. The calling address is within the range of values of the A1 and RA
mbed_official	146:f64d43ff0c18	678	* registers. For the RAM bit to be set to 1 correctly, C1[IICIE] must be set to 1.
mbed_official	146:f64d43ff0c18	679	* Writing the C1 register with any value clears this bit to 0.
mbed_official	146:f64d43ff0c18	680	*
mbed_official	146:f64d43ff0c18	681	* Values:
mbed_official	146:f64d43ff0c18	682	* - 0 - Not addressed
mbed_official	146:f64d43ff0c18	683	* - 1 - Addressed as a slave
mbed_official	146:f64d43ff0c18	684	*/
mbed_official	146:f64d43ff0c18	685	//@{
mbed_official	146:f64d43ff0c18	686	#define BP_I2C_S_RAM (3U) //!< Bit position for I2C_S_RAM.
mbed_official	146:f64d43ff0c18	687	#define BM_I2C_S_RAM (0x08U) //!< Bit mask for I2C_S_RAM.
mbed_official	146:f64d43ff0c18	688	#define BS_I2C_S_RAM (1U) //!< Bit field size in bits for I2C_S_RAM.
mbed_official	146:f64d43ff0c18	689
mbed_official	146:f64d43ff0c18	690	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	691	//! @brief Read current value of the I2C_S_RAM field.
mbed_official	146:f64d43ff0c18	692	#define BR_I2C_S_RAM(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_RAM))
mbed_official	146:f64d43ff0c18	693	#endif
mbed_official	146:f64d43ff0c18	694
mbed_official	146:f64d43ff0c18	695	//! @brief Format value for bitfield I2C_S_RAM.
mbed_official	146:f64d43ff0c18	696	#define BF_I2C_S_RAM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_S_RAM), uint8_t) & BM_I2C_S_RAM)
mbed_official	146:f64d43ff0c18	697
mbed_official	146:f64d43ff0c18	698	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	699	//! @brief Set the RAM field to a new value.
mbed_official	146:f64d43ff0c18	700	#define BW_I2C_S_RAM(x, v) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_RAM) = (v))
mbed_official	146:f64d43ff0c18	701	#endif
mbed_official	146:f64d43ff0c18	702	//@}
mbed_official	146:f64d43ff0c18	703
mbed_official	146:f64d43ff0c18	704	/*!
mbed_official	146:f64d43ff0c18	705	* @name Register I2C_S, field ARBL[4] (W1C)
mbed_official	146:f64d43ff0c18	706	*
mbed_official	146:f64d43ff0c18	707	* This bit is set by hardware when the arbitration procedure is lost. The ARBL
mbed_official	146:f64d43ff0c18	708	* bit must be cleared by software, by writing 1 to it.
mbed_official	146:f64d43ff0c18	709	*
mbed_official	146:f64d43ff0c18	710	* Values:
mbed_official	146:f64d43ff0c18	711	* - 0 - Standard bus operation.
mbed_official	146:f64d43ff0c18	712	* - 1 - Loss of arbitration.
mbed_official	146:f64d43ff0c18	713	*/
mbed_official	146:f64d43ff0c18	714	//@{
mbed_official	146:f64d43ff0c18	715	#define BP_I2C_S_ARBL (4U) //!< Bit position for I2C_S_ARBL.
mbed_official	146:f64d43ff0c18	716	#define BM_I2C_S_ARBL (0x10U) //!< Bit mask for I2C_S_ARBL.
mbed_official	146:f64d43ff0c18	717	#define BS_I2C_S_ARBL (1U) //!< Bit field size in bits for I2C_S_ARBL.
mbed_official	146:f64d43ff0c18	718
mbed_official	146:f64d43ff0c18	719	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	720	//! @brief Read current value of the I2C_S_ARBL field.
mbed_official	146:f64d43ff0c18	721	#define BR_I2C_S_ARBL(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_ARBL))
mbed_official	146:f64d43ff0c18	722	#endif
mbed_official	146:f64d43ff0c18	723
mbed_official	146:f64d43ff0c18	724	//! @brief Format value for bitfield I2C_S_ARBL.
mbed_official	146:f64d43ff0c18	725	#define BF_I2C_S_ARBL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_S_ARBL), uint8_t) & BM_I2C_S_ARBL)
mbed_official	146:f64d43ff0c18	726
mbed_official	146:f64d43ff0c18	727	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	728	//! @brief Set the ARBL field to a new value.
mbed_official	146:f64d43ff0c18	729	#define BW_I2C_S_ARBL(x, v) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_ARBL) = (v))
mbed_official	146:f64d43ff0c18	730	#endif
mbed_official	146:f64d43ff0c18	731	//@}
mbed_official	146:f64d43ff0c18	732
mbed_official	146:f64d43ff0c18	733	/*!
mbed_official	146:f64d43ff0c18	734	* @name Register I2C_S, field BUSY[5] (RO)
mbed_official	146:f64d43ff0c18	735	*
mbed_official	146:f64d43ff0c18	736	* Indicates the status of the bus regardless of slave or master mode. This bit
mbed_official	146:f64d43ff0c18	737	* is set when a START signal is detected and cleared when a STOP signal is
mbed_official	146:f64d43ff0c18	738	* detected.
mbed_official	146:f64d43ff0c18	739	*
mbed_official	146:f64d43ff0c18	740	* Values:
mbed_official	146:f64d43ff0c18	741	* - 0 - Bus is idle
mbed_official	146:f64d43ff0c18	742	* - 1 - Bus is busy
mbed_official	146:f64d43ff0c18	743	*/
mbed_official	146:f64d43ff0c18	744	//@{
mbed_official	146:f64d43ff0c18	745	#define BP_I2C_S_BUSY (5U) //!< Bit position for I2C_S_BUSY.
mbed_official	146:f64d43ff0c18	746	#define BM_I2C_S_BUSY (0x20U) //!< Bit mask for I2C_S_BUSY.
mbed_official	146:f64d43ff0c18	747	#define BS_I2C_S_BUSY (1U) //!< Bit field size in bits for I2C_S_BUSY.
mbed_official	146:f64d43ff0c18	748
mbed_official	146:f64d43ff0c18	749	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	750	//! @brief Read current value of the I2C_S_BUSY field.
mbed_official	146:f64d43ff0c18	751	#define BR_I2C_S_BUSY(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_BUSY))
mbed_official	146:f64d43ff0c18	752	#endif
mbed_official	146:f64d43ff0c18	753	//@}
mbed_official	146:f64d43ff0c18	754
mbed_official	146:f64d43ff0c18	755	/*!
mbed_official	146:f64d43ff0c18	756	* @name Register I2C_S, field IAAS[6] (RW)
mbed_official	146:f64d43ff0c18	757	*
mbed_official	146:f64d43ff0c18	758	* This bit is set by one of the following conditions: The calling address
mbed_official	146:f64d43ff0c18	759	* matches the programmed primary slave address in the A1 register, or matches the
mbed_official	146:f64d43ff0c18	760	* range address in the RA register (which must be set to a nonzero value and under
mbed_official	146:f64d43ff0c18	761	* the condition I2C_C2[RMEN] = 1). C2[GCAEN] is set and a general call is
mbed_official	146:f64d43ff0c18	762	* received. SMB[SIICAEN] is set and the calling address matches the second programmed
mbed_official	146:f64d43ff0c18	763	* slave address. ALERTEN is set and an SMBus alert response address is received
mbed_official	146:f64d43ff0c18	764	* RMEN is set and an address is received that is within the range between the
mbed_official	146:f64d43ff0c18	765	* values of the A1 and RA registers. IAAS sets before the ACK bit. The CPU must
mbed_official	146:f64d43ff0c18	766	* check the SRW bit and set TX/RX accordingly. Writing the C1 register with any
mbed_official	146:f64d43ff0c18	767	* value clears this bit.
mbed_official	146:f64d43ff0c18	768	*
mbed_official	146:f64d43ff0c18	769	* Values:
mbed_official	146:f64d43ff0c18	770	* - 0 - Not addressed
mbed_official	146:f64d43ff0c18	771	* - 1 - Addressed as a slave
mbed_official	146:f64d43ff0c18	772	*/
mbed_official	146:f64d43ff0c18	773	//@{
mbed_official	146:f64d43ff0c18	774	#define BP_I2C_S_IAAS (6U) //!< Bit position for I2C_S_IAAS.
mbed_official	146:f64d43ff0c18	775	#define BM_I2C_S_IAAS (0x40U) //!< Bit mask for I2C_S_IAAS.
mbed_official	146:f64d43ff0c18	776	#define BS_I2C_S_IAAS (1U) //!< Bit field size in bits for I2C_S_IAAS.
mbed_official	146:f64d43ff0c18	777
mbed_official	146:f64d43ff0c18	778	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	779	//! @brief Read current value of the I2C_S_IAAS field.
mbed_official	146:f64d43ff0c18	780	#define BR_I2C_S_IAAS(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IAAS))
mbed_official	146:f64d43ff0c18	781	#endif
mbed_official	146:f64d43ff0c18	782
mbed_official	146:f64d43ff0c18	783	//! @brief Format value for bitfield I2C_S_IAAS.
mbed_official	146:f64d43ff0c18	784	#define BF_I2C_S_IAAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_S_IAAS), uint8_t) & BM_I2C_S_IAAS)
mbed_official	146:f64d43ff0c18	785
mbed_official	146:f64d43ff0c18	786	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	787	//! @brief Set the IAAS field to a new value.
mbed_official	146:f64d43ff0c18	788	#define BW_I2C_S_IAAS(x, v) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IAAS) = (v))
mbed_official	146:f64d43ff0c18	789	#endif
mbed_official	146:f64d43ff0c18	790	//@}
mbed_official	146:f64d43ff0c18	791
mbed_official	146:f64d43ff0c18	792	/*!
mbed_official	146:f64d43ff0c18	793	* @name Register I2C_S, field TCF[7] (RO)
mbed_official	146:f64d43ff0c18	794	*
mbed_official	146:f64d43ff0c18	795	* Acknowledges a byte transfer; TCF sets on the completion of a byte transfer.
mbed_official	146:f64d43ff0c18	796	* This bit is valid only during or immediately following a transfer to or from
mbed_official	146:f64d43ff0c18	797	* the I2C module. TCF is cleared by reading the I2C data register in receive mode
mbed_official	146:f64d43ff0c18	798	* or by writing to the I2C data register in transmit mode.
mbed_official	146:f64d43ff0c18	799	*
mbed_official	146:f64d43ff0c18	800	* Values:
mbed_official	146:f64d43ff0c18	801	* - 0 - Transfer in progress
mbed_official	146:f64d43ff0c18	802	* - 1 - Transfer complete
mbed_official	146:f64d43ff0c18	803	*/
mbed_official	146:f64d43ff0c18	804	//@{
mbed_official	146:f64d43ff0c18	805	#define BP_I2C_S_TCF (7U) //!< Bit position for I2C_S_TCF.
mbed_official	146:f64d43ff0c18	806	#define BM_I2C_S_TCF (0x80U) //!< Bit mask for I2C_S_TCF.
mbed_official	146:f64d43ff0c18	807	#define BS_I2C_S_TCF (1U) //!< Bit field size in bits for I2C_S_TCF.
mbed_official	146:f64d43ff0c18	808
mbed_official	146:f64d43ff0c18	809	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	810	//! @brief Read current value of the I2C_S_TCF field.
mbed_official	146:f64d43ff0c18	811	#define BR_I2C_S_TCF(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_TCF))
mbed_official	146:f64d43ff0c18	812	#endif
mbed_official	146:f64d43ff0c18	813	//@}
mbed_official	146:f64d43ff0c18	814
mbed_official	146:f64d43ff0c18	815	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	816	// HW_I2C_D - I2C Data I/O register
mbed_official	146:f64d43ff0c18	817	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	818
mbed_official	146:f64d43ff0c18	819	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	820	/*!
mbed_official	146:f64d43ff0c18	821	* @brief HW_I2C_D - I2C Data I/O register (RW)
mbed_official	146:f64d43ff0c18	822	*
mbed_official	146:f64d43ff0c18	823	* Reset value: 0x00U
mbed_official	146:f64d43ff0c18	824	*/
mbed_official	146:f64d43ff0c18	825	typedef union _hw_i2c_d
mbed_official	146:f64d43ff0c18	826	{
mbed_official	146:f64d43ff0c18	827	uint8_t U;
mbed_official	146:f64d43ff0c18	828	struct _hw_i2c_d_bitfields
mbed_official	146:f64d43ff0c18	829	{
mbed_official	146:f64d43ff0c18	830	uint8_t DATA : 8; //!< [7:0] Data
mbed_official	146:f64d43ff0c18	831	} B;
mbed_official	146:f64d43ff0c18	832	} hw_i2c_d_t;
mbed_official	146:f64d43ff0c18	833	#endif
mbed_official	146:f64d43ff0c18	834
mbed_official	146:f64d43ff0c18	835	/*!
mbed_official	146:f64d43ff0c18	836	* @name Constants and macros for entire I2C_D register
mbed_official	146:f64d43ff0c18	837	*/
mbed_official	146:f64d43ff0c18	838	//@{
mbed_official	146:f64d43ff0c18	839	#define HW_I2C_D_ADDR(x) (REGS_I2C_BASE(x) + 0x4U)
mbed_official	146:f64d43ff0c18	840
mbed_official	146:f64d43ff0c18	841	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	842	#define HW_I2C_D(x) ((__IO hw_i2c_d_t ) HW_I2C_D_ADDR(x))
mbed_official	146:f64d43ff0c18	843	#define HW_I2C_D_RD(x) (HW_I2C_D(x).U)
mbed_official	146:f64d43ff0c18	844	#define HW_I2C_D_WR(x, v) (HW_I2C_D(x).U = (v))
mbed_official	146:f64d43ff0c18	845	#define HW_I2C_D_SET(x, v) (HW_I2C_D_WR(x, HW_I2C_D_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	846	#define HW_I2C_D_CLR(x, v) (HW_I2C_D_WR(x, HW_I2C_D_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	847	#define HW_I2C_D_TOG(x, v) (HW_I2C_D_WR(x, HW_I2C_D_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	848	#endif
mbed_official	146:f64d43ff0c18	849	//@}
mbed_official	146:f64d43ff0c18	850
mbed_official	146:f64d43ff0c18	851	/*
mbed_official	146:f64d43ff0c18	852	* Constants & macros for individual I2C_D bitfields
mbed_official	146:f64d43ff0c18	853	*/
mbed_official	146:f64d43ff0c18	854
mbed_official	146:f64d43ff0c18	855	/*!
mbed_official	146:f64d43ff0c18	856	* @name Register I2C_D, field DATA[7:0] (RW)
mbed_official	146:f64d43ff0c18	857	*
mbed_official	146:f64d43ff0c18	858	* In master transmit mode, when data is written to this register, a data
mbed_official	146:f64d43ff0c18	859	* transfer is initiated. The most significant bit is sent first. In master receive
mbed_official	146:f64d43ff0c18	860	* mode, reading this register initiates receiving of the next byte of data. When
mbed_official	146:f64d43ff0c18	861	* making the transition out of master receive mode, switch the I2C mode before
mbed_official	146:f64d43ff0c18	862	* reading the Data register to prevent an inadvertent initiation of a master
mbed_official	146:f64d43ff0c18	863	* receive data transfer. In slave mode, the same functions are available after an
mbed_official	146:f64d43ff0c18	864	* address match occurs. The C1[TX] bit must correctly reflect the desired direction
mbed_official	146:f64d43ff0c18	865	* of transfer in master and slave modes for the transmission to begin. For
mbed_official	146:f64d43ff0c18	866	* example, if the I2C module is configured for master transmit but a master receive
mbed_official	146:f64d43ff0c18	867	* is desired, reading the Data register does not initiate the receive. Reading
mbed_official	146:f64d43ff0c18	868	* the Data register returns the last byte received while the I2C module is
mbed_official	146:f64d43ff0c18	869	* configured in master receive or slave receive mode. The Data register does not
mbed_official	146:f64d43ff0c18	870	* reflect every byte that is transmitted on the I2C bus, and neither can software
mbed_official	146:f64d43ff0c18	871	* verify that a byte has been written to the Data register correctly by reading it
mbed_official	146:f64d43ff0c18	872	* back. In master transmit mode, the first byte of data written to the Data
mbed_official	146:f64d43ff0c18	873	* register following assertion of MST (start bit) or assertion of RSTA (repeated
mbed_official	146:f64d43ff0c18	874	* start bit) is used for the address transfer and must consist of the calling
mbed_official	146:f64d43ff0c18	875	* address (in bits 7-1) concatenated with the required R/W bit (in position bit 0).
mbed_official	146:f64d43ff0c18	876	*/
mbed_official	146:f64d43ff0c18	877	//@{
mbed_official	146:f64d43ff0c18	878	#define BP_I2C_D_DATA (0U) //!< Bit position for I2C_D_DATA.
mbed_official	146:f64d43ff0c18	879	#define BM_I2C_D_DATA (0xFFU) //!< Bit mask for I2C_D_DATA.
mbed_official	146:f64d43ff0c18	880	#define BS_I2C_D_DATA (8U) //!< Bit field size in bits for I2C_D_DATA.
mbed_official	146:f64d43ff0c18	881
mbed_official	146:f64d43ff0c18	882	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	883	//! @brief Read current value of the I2C_D_DATA field.
mbed_official	146:f64d43ff0c18	884	#define BR_I2C_D_DATA(x) (HW_I2C_D(x).U)
mbed_official	146:f64d43ff0c18	885	#endif
mbed_official	146:f64d43ff0c18	886
mbed_official	146:f64d43ff0c18	887	//! @brief Format value for bitfield I2C_D_DATA.
mbed_official	146:f64d43ff0c18	888	#define BF_I2C_D_DATA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_D_DATA), uint8_t) & BM_I2C_D_DATA)
mbed_official	146:f64d43ff0c18	889
mbed_official	146:f64d43ff0c18	890	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	891	//! @brief Set the DATA field to a new value.
mbed_official	146:f64d43ff0c18	892	#define BW_I2C_D_DATA(x, v) (HW_I2C_D_WR(x, v))
mbed_official	146:f64d43ff0c18	893	#endif
mbed_official	146:f64d43ff0c18	894	//@}
mbed_official	146:f64d43ff0c18	895
mbed_official	146:f64d43ff0c18	896	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	897	// HW_I2C_C2 - I2C Control Register 2
mbed_official	146:f64d43ff0c18	898	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	899
mbed_official	146:f64d43ff0c18	900	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	901	/*!
mbed_official	146:f64d43ff0c18	902	* @brief HW_I2C_C2 - I2C Control Register 2 (RW)
mbed_official	146:f64d43ff0c18	903	*
mbed_official	146:f64d43ff0c18	904	* Reset value: 0x00U
mbed_official	146:f64d43ff0c18	905	*/
mbed_official	146:f64d43ff0c18	906	typedef union _hw_i2c_c2
mbed_official	146:f64d43ff0c18	907	{
mbed_official	146:f64d43ff0c18	908	uint8_t U;
mbed_official	146:f64d43ff0c18	909	struct _hw_i2c_c2_bitfields
mbed_official	146:f64d43ff0c18	910	{
mbed_official	146:f64d43ff0c18	911	uint8_t AD : 3; //!< [2:0] Slave Address
mbed_official	146:f64d43ff0c18	912	uint8_t RMEN : 1; //!< [3] Range Address Matching Enable
mbed_official	146:f64d43ff0c18	913	uint8_t SBRC : 1; //!< [4] Slave Baud Rate Control
mbed_official	146:f64d43ff0c18	914	uint8_t HDRS : 1; //!< [5] High Drive Select
mbed_official	146:f64d43ff0c18	915	uint8_t ADEXT : 1; //!< [6] Address Extension
mbed_official	146:f64d43ff0c18	916	uint8_t GCAEN : 1; //!< [7] General Call Address Enable
mbed_official	146:f64d43ff0c18	917	} B;
mbed_official	146:f64d43ff0c18	918	} hw_i2c_c2_t;
mbed_official	146:f64d43ff0c18	919	#endif
mbed_official	146:f64d43ff0c18	920
mbed_official	146:f64d43ff0c18	921	/*!
mbed_official	146:f64d43ff0c18	922	* @name Constants and macros for entire I2C_C2 register
mbed_official	146:f64d43ff0c18	923	*/
mbed_official	146:f64d43ff0c18	924	//@{
mbed_official	146:f64d43ff0c18	925	#define HW_I2C_C2_ADDR(x) (REGS_I2C_BASE(x) + 0x5U)
mbed_official	146:f64d43ff0c18	926
mbed_official	146:f64d43ff0c18	927	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	928	#define HW_I2C_C2(x) ((__IO hw_i2c_c2_t ) HW_I2C_C2_ADDR(x))
mbed_official	146:f64d43ff0c18	929	#define HW_I2C_C2_RD(x) (HW_I2C_C2(x).U)
mbed_official	146:f64d43ff0c18	930	#define HW_I2C_C2_WR(x, v) (HW_I2C_C2(x).U = (v))
mbed_official	146:f64d43ff0c18	931	#define HW_I2C_C2_SET(x, v) (HW_I2C_C2_WR(x, HW_I2C_C2_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	932	#define HW_I2C_C2_CLR(x, v) (HW_I2C_C2_WR(x, HW_I2C_C2_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	933	#define HW_I2C_C2_TOG(x, v) (HW_I2C_C2_WR(x, HW_I2C_C2_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	934	#endif
mbed_official	146:f64d43ff0c18	935	//@}
mbed_official	146:f64d43ff0c18	936
mbed_official	146:f64d43ff0c18	937	/*
mbed_official	146:f64d43ff0c18	938	* Constants & macros for individual I2C_C2 bitfields
mbed_official	146:f64d43ff0c18	939	*/
mbed_official	146:f64d43ff0c18	940
mbed_official	146:f64d43ff0c18	941	/*!
mbed_official	146:f64d43ff0c18	942	* @name Register I2C_C2, field AD[2:0] (RW)
mbed_official	146:f64d43ff0c18	943	*
mbed_official	146:f64d43ff0c18	944	* Contains the upper three bits of the slave address in the 10-bit address
mbed_official	146:f64d43ff0c18	945	* scheme. This field is valid only while the ADEXT bit is set.
mbed_official	146:f64d43ff0c18	946	*/
mbed_official	146:f64d43ff0c18	947	//@{
mbed_official	146:f64d43ff0c18	948	#define BP_I2C_C2_AD (0U) //!< Bit position for I2C_C2_AD.
mbed_official	146:f64d43ff0c18	949	#define BM_I2C_C2_AD (0x07U) //!< Bit mask for I2C_C2_AD.
mbed_official	146:f64d43ff0c18	950	#define BS_I2C_C2_AD (3U) //!< Bit field size in bits for I2C_C2_AD.
mbed_official	146:f64d43ff0c18	951
mbed_official	146:f64d43ff0c18	952	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	953	//! @brief Read current value of the I2C_C2_AD field.
mbed_official	146:f64d43ff0c18	954	#define BR_I2C_C2_AD(x) (HW_I2C_C2(x).B.AD)
mbed_official	146:f64d43ff0c18	955	#endif
mbed_official	146:f64d43ff0c18	956
mbed_official	146:f64d43ff0c18	957	//! @brief Format value for bitfield I2C_C2_AD.
mbed_official	146:f64d43ff0c18	958	#define BF_I2C_C2_AD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C2_AD), uint8_t) & BM_I2C_C2_AD)
mbed_official	146:f64d43ff0c18	959
mbed_official	146:f64d43ff0c18	960	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	961	//! @brief Set the AD field to a new value.
mbed_official	146:f64d43ff0c18	962	#define BW_I2C_C2_AD(x, v) (HW_I2C_C2_WR(x, (HW_I2C_C2_RD(x) & ~BM_I2C_C2_AD) \| BF_I2C_C2_AD(v)))
mbed_official	146:f64d43ff0c18	963	#endif
mbed_official	146:f64d43ff0c18	964	//@}
mbed_official	146:f64d43ff0c18	965
mbed_official	146:f64d43ff0c18	966	/*!
mbed_official	146:f64d43ff0c18	967	* @name Register I2C_C2, field RMEN[3] (RW)
mbed_official	146:f64d43ff0c18	968	*
mbed_official	146:f64d43ff0c18	969	* This bit controls the slave address matching for addresses between the values
mbed_official	146:f64d43ff0c18	970	* of the A1 and RA registers. When this bit is set, a slave address matching
mbed_official	146:f64d43ff0c18	971	* occurs for any address greater than the value of the A1 register and less than
mbed_official	146:f64d43ff0c18	972	* or equal to the value of the RA register.
mbed_official	146:f64d43ff0c18	973	*
mbed_official	146:f64d43ff0c18	974	* Values:
mbed_official	146:f64d43ff0c18	975	* - 0 - Range mode disabled. No address matching occurs for an address within
mbed_official	146:f64d43ff0c18	976	* the range of values of the A1 and RA registers.
mbed_official	146:f64d43ff0c18	977	* - 1 - Range mode enabled. Address matching occurs when a slave receives an
mbed_official	146:f64d43ff0c18	978	* address within the range of values of the A1 and RA registers.
mbed_official	146:f64d43ff0c18	979	*/
mbed_official	146:f64d43ff0c18	980	//@{
mbed_official	146:f64d43ff0c18	981	#define BP_I2C_C2_RMEN (3U) //!< Bit position for I2C_C2_RMEN.
mbed_official	146:f64d43ff0c18	982	#define BM_I2C_C2_RMEN (0x08U) //!< Bit mask for I2C_C2_RMEN.
mbed_official	146:f64d43ff0c18	983	#define BS_I2C_C2_RMEN (1U) //!< Bit field size in bits for I2C_C2_RMEN.
mbed_official	146:f64d43ff0c18	984
mbed_official	146:f64d43ff0c18	985	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	986	//! @brief Read current value of the I2C_C2_RMEN field.
mbed_official	146:f64d43ff0c18	987	#define BR_I2C_C2_RMEN(x) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_RMEN))
mbed_official	146:f64d43ff0c18	988	#endif
mbed_official	146:f64d43ff0c18	989
mbed_official	146:f64d43ff0c18	990	//! @brief Format value for bitfield I2C_C2_RMEN.
mbed_official	146:f64d43ff0c18	991	#define BF_I2C_C2_RMEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C2_RMEN), uint8_t) & BM_I2C_C2_RMEN)
mbed_official	146:f64d43ff0c18	992
mbed_official	146:f64d43ff0c18	993	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	994	//! @brief Set the RMEN field to a new value.
mbed_official	146:f64d43ff0c18	995	#define BW_I2C_C2_RMEN(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_RMEN) = (v))
mbed_official	146:f64d43ff0c18	996	#endif
mbed_official	146:f64d43ff0c18	997	//@}
mbed_official	146:f64d43ff0c18	998
mbed_official	146:f64d43ff0c18	999	/*!
mbed_official	146:f64d43ff0c18	1000	* @name Register I2C_C2, field SBRC[4] (RW)
mbed_official	146:f64d43ff0c18	1001	*
mbed_official	146:f64d43ff0c18	1002	* Enables independent slave mode baud rate at maximum frequency, which forces
mbed_official	146:f64d43ff0c18	1003	* clock stretching on SCL in very fast I2C modes. To a slave, an example of a
mbed_official	146:f64d43ff0c18	1004	* "very fast" mode is when the master transfers at 40 kbit/s but the slave can
mbed_official	146:f64d43ff0c18	1005	* capture the master's data at only 10 kbit/s.
mbed_official	146:f64d43ff0c18	1006	*
mbed_official	146:f64d43ff0c18	1007	* Values:
mbed_official	146:f64d43ff0c18	1008	* - 0 - The slave baud rate follows the master baud rate and clock stretching
mbed_official	146:f64d43ff0c18	1009	* may occur
mbed_official	146:f64d43ff0c18	1010	* - 1 - Slave baud rate is independent of the master baud rate
mbed_official	146:f64d43ff0c18	1011	*/
mbed_official	146:f64d43ff0c18	1012	//@{
mbed_official	146:f64d43ff0c18	1013	#define BP_I2C_C2_SBRC (4U) //!< Bit position for I2C_C2_SBRC.
mbed_official	146:f64d43ff0c18	1014	#define BM_I2C_C2_SBRC (0x10U) //!< Bit mask for I2C_C2_SBRC.
mbed_official	146:f64d43ff0c18	1015	#define BS_I2C_C2_SBRC (1U) //!< Bit field size in bits for I2C_C2_SBRC.
mbed_official	146:f64d43ff0c18	1016
mbed_official	146:f64d43ff0c18	1017	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1018	//! @brief Read current value of the I2C_C2_SBRC field.
mbed_official	146:f64d43ff0c18	1019	#define BR_I2C_C2_SBRC(x) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_SBRC))
mbed_official	146:f64d43ff0c18	1020	#endif
mbed_official	146:f64d43ff0c18	1021
mbed_official	146:f64d43ff0c18	1022	//! @brief Format value for bitfield I2C_C2_SBRC.
mbed_official	146:f64d43ff0c18	1023	#define BF_I2C_C2_SBRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C2_SBRC), uint8_t) & BM_I2C_C2_SBRC)
mbed_official	146:f64d43ff0c18	1024
mbed_official	146:f64d43ff0c18	1025	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1026	//! @brief Set the SBRC field to a new value.
mbed_official	146:f64d43ff0c18	1027	#define BW_I2C_C2_SBRC(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_SBRC) = (v))
mbed_official	146:f64d43ff0c18	1028	#endif
mbed_official	146:f64d43ff0c18	1029	//@}
mbed_official	146:f64d43ff0c18	1030
mbed_official	146:f64d43ff0c18	1031	/*!
mbed_official	146:f64d43ff0c18	1032	* @name Register I2C_C2, field HDRS[5] (RW)
mbed_official	146:f64d43ff0c18	1033	*
mbed_official	146:f64d43ff0c18	1034	* Controls the drive capability of the I2C pads.
mbed_official	146:f64d43ff0c18	1035	*
mbed_official	146:f64d43ff0c18	1036	* Values:
mbed_official	146:f64d43ff0c18	1037	* - 0 - Normal drive mode
mbed_official	146:f64d43ff0c18	1038	* - 1 - High drive mode
mbed_official	146:f64d43ff0c18	1039	*/
mbed_official	146:f64d43ff0c18	1040	//@{
mbed_official	146:f64d43ff0c18	1041	#define BP_I2C_C2_HDRS (5U) //!< Bit position for I2C_C2_HDRS.
mbed_official	146:f64d43ff0c18	1042	#define BM_I2C_C2_HDRS (0x20U) //!< Bit mask for I2C_C2_HDRS.
mbed_official	146:f64d43ff0c18	1043	#define BS_I2C_C2_HDRS (1U) //!< Bit field size in bits for I2C_C2_HDRS.
mbed_official	146:f64d43ff0c18	1044
mbed_official	146:f64d43ff0c18	1045	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1046	//! @brief Read current value of the I2C_C2_HDRS field.
mbed_official	146:f64d43ff0c18	1047	#define BR_I2C_C2_HDRS(x) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_HDRS))
mbed_official	146:f64d43ff0c18	1048	#endif
mbed_official	146:f64d43ff0c18	1049
mbed_official	146:f64d43ff0c18	1050	//! @brief Format value for bitfield I2C_C2_HDRS.
mbed_official	146:f64d43ff0c18	1051	#define BF_I2C_C2_HDRS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C2_HDRS), uint8_t) & BM_I2C_C2_HDRS)
mbed_official	146:f64d43ff0c18	1052
mbed_official	146:f64d43ff0c18	1053	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1054	//! @brief Set the HDRS field to a new value.
mbed_official	146:f64d43ff0c18	1055	#define BW_I2C_C2_HDRS(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_HDRS) = (v))
mbed_official	146:f64d43ff0c18	1056	#endif
mbed_official	146:f64d43ff0c18	1057	//@}
mbed_official	146:f64d43ff0c18	1058
mbed_official	146:f64d43ff0c18	1059	/*!
mbed_official	146:f64d43ff0c18	1060	* @name Register I2C_C2, field ADEXT[6] (RW)
mbed_official	146:f64d43ff0c18	1061	*
mbed_official	146:f64d43ff0c18	1062	* Controls the number of bits used for the slave address.
mbed_official	146:f64d43ff0c18	1063	*
mbed_official	146:f64d43ff0c18	1064	* Values:
mbed_official	146:f64d43ff0c18	1065	* - 0 - 7-bit address scheme
mbed_official	146:f64d43ff0c18	1066	* - 1 - 10-bit address scheme
mbed_official	146:f64d43ff0c18	1067	*/
mbed_official	146:f64d43ff0c18	1068	//@{
mbed_official	146:f64d43ff0c18	1069	#define BP_I2C_C2_ADEXT (6U) //!< Bit position for I2C_C2_ADEXT.
mbed_official	146:f64d43ff0c18	1070	#define BM_I2C_C2_ADEXT (0x40U) //!< Bit mask for I2C_C2_ADEXT.
mbed_official	146:f64d43ff0c18	1071	#define BS_I2C_C2_ADEXT (1U) //!< Bit field size in bits for I2C_C2_ADEXT.
mbed_official	146:f64d43ff0c18	1072
mbed_official	146:f64d43ff0c18	1073	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1074	//! @brief Read current value of the I2C_C2_ADEXT field.
mbed_official	146:f64d43ff0c18	1075	#define BR_I2C_C2_ADEXT(x) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_ADEXT))
mbed_official	146:f64d43ff0c18	1076	#endif
mbed_official	146:f64d43ff0c18	1077
mbed_official	146:f64d43ff0c18	1078	//! @brief Format value for bitfield I2C_C2_ADEXT.
mbed_official	146:f64d43ff0c18	1079	#define BF_I2C_C2_ADEXT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C2_ADEXT), uint8_t) & BM_I2C_C2_ADEXT)
mbed_official	146:f64d43ff0c18	1080
mbed_official	146:f64d43ff0c18	1081	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1082	//! @brief Set the ADEXT field to a new value.
mbed_official	146:f64d43ff0c18	1083	#define BW_I2C_C2_ADEXT(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_ADEXT) = (v))
mbed_official	146:f64d43ff0c18	1084	#endif
mbed_official	146:f64d43ff0c18	1085	//@}
mbed_official	146:f64d43ff0c18	1086
mbed_official	146:f64d43ff0c18	1087	/*!
mbed_official	146:f64d43ff0c18	1088	* @name Register I2C_C2, field GCAEN[7] (RW)
mbed_official	146:f64d43ff0c18	1089	*
mbed_official	146:f64d43ff0c18	1090	* Enables general call address.
mbed_official	146:f64d43ff0c18	1091	*
mbed_official	146:f64d43ff0c18	1092	* Values:
mbed_official	146:f64d43ff0c18	1093	* - 0 - Disabled
mbed_official	146:f64d43ff0c18	1094	* - 1 - Enabled
mbed_official	146:f64d43ff0c18	1095	*/
mbed_official	146:f64d43ff0c18	1096	//@{
mbed_official	146:f64d43ff0c18	1097	#define BP_I2C_C2_GCAEN (7U) //!< Bit position for I2C_C2_GCAEN.
mbed_official	146:f64d43ff0c18	1098	#define BM_I2C_C2_GCAEN (0x80U) //!< Bit mask for I2C_C2_GCAEN.
mbed_official	146:f64d43ff0c18	1099	#define BS_I2C_C2_GCAEN (1U) //!< Bit field size in bits for I2C_C2_GCAEN.
mbed_official	146:f64d43ff0c18	1100
mbed_official	146:f64d43ff0c18	1101	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1102	//! @brief Read current value of the I2C_C2_GCAEN field.
mbed_official	146:f64d43ff0c18	1103	#define BR_I2C_C2_GCAEN(x) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_GCAEN))
mbed_official	146:f64d43ff0c18	1104	#endif
mbed_official	146:f64d43ff0c18	1105
mbed_official	146:f64d43ff0c18	1106	//! @brief Format value for bitfield I2C_C2_GCAEN.
mbed_official	146:f64d43ff0c18	1107	#define BF_I2C_C2_GCAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C2_GCAEN), uint8_t) & BM_I2C_C2_GCAEN)
mbed_official	146:f64d43ff0c18	1108
mbed_official	146:f64d43ff0c18	1109	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1110	//! @brief Set the GCAEN field to a new value.
mbed_official	146:f64d43ff0c18	1111	#define BW_I2C_C2_GCAEN(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_GCAEN) = (v))
mbed_official	146:f64d43ff0c18	1112	#endif
mbed_official	146:f64d43ff0c18	1113	//@}
mbed_official	146:f64d43ff0c18	1114
mbed_official	146:f64d43ff0c18	1115	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1116	// HW_I2C_FLT - I2C Programmable Input Glitch Filter register
mbed_official	146:f64d43ff0c18	1117	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1118
mbed_official	146:f64d43ff0c18	1119	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1120	/*!
mbed_official	146:f64d43ff0c18	1121	* @brief HW_I2C_FLT - I2C Programmable Input Glitch Filter register (RW)
mbed_official	146:f64d43ff0c18	1122	*
mbed_official	146:f64d43ff0c18	1123	* Reset value: 0x00U
mbed_official	146:f64d43ff0c18	1124	*/
mbed_official	146:f64d43ff0c18	1125	typedef union _hw_i2c_flt
mbed_official	146:f64d43ff0c18	1126	{
mbed_official	146:f64d43ff0c18	1127	uint8_t U;
mbed_official	146:f64d43ff0c18	1128	struct _hw_i2c_flt_bitfields
mbed_official	146:f64d43ff0c18	1129	{
mbed_official	146:f64d43ff0c18	1130	uint8_t FLT : 4; //!< [3:0] I2C Programmable Filter Factor
mbed_official	146:f64d43ff0c18	1131	uint8_t STARTF : 1; //!< [4] I2C Bus Start Detect Flag
mbed_official	146:f64d43ff0c18	1132	uint8_t SSIE : 1; //!< [5] I2C Bus Stop or Start Interrupt Enable
mbed_official	146:f64d43ff0c18	1133	uint8_t STOPF : 1; //!< [6] I2C Bus Stop Detect Flag
mbed_official	146:f64d43ff0c18	1134	uint8_t SHEN : 1; //!< [7] Stop Hold Enable
mbed_official	146:f64d43ff0c18	1135	} B;
mbed_official	146:f64d43ff0c18	1136	} hw_i2c_flt_t;
mbed_official	146:f64d43ff0c18	1137	#endif
mbed_official	146:f64d43ff0c18	1138
mbed_official	146:f64d43ff0c18	1139	/*!
mbed_official	146:f64d43ff0c18	1140	* @name Constants and macros for entire I2C_FLT register
mbed_official	146:f64d43ff0c18	1141	*/
mbed_official	146:f64d43ff0c18	1142	//@{
mbed_official	146:f64d43ff0c18	1143	#define HW_I2C_FLT_ADDR(x) (REGS_I2C_BASE(x) + 0x6U)
mbed_official	146:f64d43ff0c18	1144
mbed_official	146:f64d43ff0c18	1145	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1146	#define HW_I2C_FLT(x) ((__IO hw_i2c_flt_t ) HW_I2C_FLT_ADDR(x))
mbed_official	146:f64d43ff0c18	1147	#define HW_I2C_FLT_RD(x) (HW_I2C_FLT(x).U)
mbed_official	146:f64d43ff0c18	1148	#define HW_I2C_FLT_WR(x, v) (HW_I2C_FLT(x).U = (v))
mbed_official	146:f64d43ff0c18	1149	#define HW_I2C_FLT_SET(x, v) (HW_I2C_FLT_WR(x, HW_I2C_FLT_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	1150	#define HW_I2C_FLT_CLR(x, v) (HW_I2C_FLT_WR(x, HW_I2C_FLT_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	1151	#define HW_I2C_FLT_TOG(x, v) (HW_I2C_FLT_WR(x, HW_I2C_FLT_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	1152	#endif
mbed_official	146:f64d43ff0c18	1153	//@}
mbed_official	146:f64d43ff0c18	1154
mbed_official	146:f64d43ff0c18	1155	/*
mbed_official	146:f64d43ff0c18	1156	* Constants & macros for individual I2C_FLT bitfields
mbed_official	146:f64d43ff0c18	1157	*/
mbed_official	146:f64d43ff0c18	1158
mbed_official	146:f64d43ff0c18	1159	/*!
mbed_official	146:f64d43ff0c18	1160	* @name Register I2C_FLT, field FLT[3:0] (RW)
mbed_official	146:f64d43ff0c18	1161	*
mbed_official	146:f64d43ff0c18	1162	* Controls the width of the glitch, in terms of I2C module clock cycles, that
mbed_official	146:f64d43ff0c18	1163	* the filter must absorb. For any glitch whose size is less than or equal to this
mbed_official	146:f64d43ff0c18	1164	* width setting, the filter does not allow the glitch to pass.
mbed_official	146:f64d43ff0c18	1165	*
mbed_official	146:f64d43ff0c18	1166	* Values:
mbed_official	146:f64d43ff0c18	1167	* - 0 - No filter/bypass
mbed_official	146:f64d43ff0c18	1168	*/
mbed_official	146:f64d43ff0c18	1169	//@{
mbed_official	146:f64d43ff0c18	1170	#define BP_I2C_FLT_FLT (0U) //!< Bit position for I2C_FLT_FLT.
mbed_official	146:f64d43ff0c18	1171	#define BM_I2C_FLT_FLT (0x0FU) //!< Bit mask for I2C_FLT_FLT.
mbed_official	146:f64d43ff0c18	1172	#define BS_I2C_FLT_FLT (4U) //!< Bit field size in bits for I2C_FLT_FLT.
mbed_official	146:f64d43ff0c18	1173
mbed_official	146:f64d43ff0c18	1174	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1175	//! @brief Read current value of the I2C_FLT_FLT field.
mbed_official	146:f64d43ff0c18	1176	#define BR_I2C_FLT_FLT(x) (HW_I2C_FLT(x).B.FLT)
mbed_official	146:f64d43ff0c18	1177	#endif
mbed_official	146:f64d43ff0c18	1178
mbed_official	146:f64d43ff0c18	1179	//! @brief Format value for bitfield I2C_FLT_FLT.
mbed_official	146:f64d43ff0c18	1180	#define BF_I2C_FLT_FLT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_FLT_FLT), uint8_t) & BM_I2C_FLT_FLT)
mbed_official	146:f64d43ff0c18	1181
mbed_official	146:f64d43ff0c18	1182	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1183	//! @brief Set the FLT field to a new value.
mbed_official	146:f64d43ff0c18	1184	#define BW_I2C_FLT_FLT(x, v) (HW_I2C_FLT_WR(x, (HW_I2C_FLT_RD(x) & ~BM_I2C_FLT_FLT) \| BF_I2C_FLT_FLT(v)))
mbed_official	146:f64d43ff0c18	1185	#endif
mbed_official	146:f64d43ff0c18	1186	//@}
mbed_official	146:f64d43ff0c18	1187
mbed_official	146:f64d43ff0c18	1188	/*!
mbed_official	146:f64d43ff0c18	1189	* @name Register I2C_FLT, field STARTF[4] (W1C)
mbed_official	146:f64d43ff0c18	1190	*
mbed_official	146:f64d43ff0c18	1191	* Hardware sets this bit when the I2C bus's start status is detected. The
mbed_official	146:f64d43ff0c18	1192	* STARTF bit must be cleared by writing 1 to it.
mbed_official	146:f64d43ff0c18	1193	*
mbed_official	146:f64d43ff0c18	1194	* Values:
mbed_official	146:f64d43ff0c18	1195	* - 0 - No start happens on I2C bus
mbed_official	146:f64d43ff0c18	1196	* - 1 - Start detected on I2C bus
mbed_official	146:f64d43ff0c18	1197	*/
mbed_official	146:f64d43ff0c18	1198	//@{
mbed_official	146:f64d43ff0c18	1199	#define BP_I2C_FLT_STARTF (4U) //!< Bit position for I2C_FLT_STARTF.
mbed_official	146:f64d43ff0c18	1200	#define BM_I2C_FLT_STARTF (0x10U) //!< Bit mask for I2C_FLT_STARTF.
mbed_official	146:f64d43ff0c18	1201	#define BS_I2C_FLT_STARTF (1U) //!< Bit field size in bits for I2C_FLT_STARTF.
mbed_official	146:f64d43ff0c18	1202
mbed_official	146:f64d43ff0c18	1203	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1204	//! @brief Read current value of the I2C_FLT_STARTF field.
mbed_official	146:f64d43ff0c18	1205	#define BR_I2C_FLT_STARTF(x) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STARTF))
mbed_official	146:f64d43ff0c18	1206	#endif
mbed_official	146:f64d43ff0c18	1207
mbed_official	146:f64d43ff0c18	1208	//! @brief Format value for bitfield I2C_FLT_STARTF.
mbed_official	146:f64d43ff0c18	1209	#define BF_I2C_FLT_STARTF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_FLT_STARTF), uint8_t) & BM_I2C_FLT_STARTF)
mbed_official	146:f64d43ff0c18	1210
mbed_official	146:f64d43ff0c18	1211	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1212	//! @brief Set the STARTF field to a new value.
mbed_official	146:f64d43ff0c18	1213	#define BW_I2C_FLT_STARTF(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STARTF) = (v))
mbed_official	146:f64d43ff0c18	1214	#endif
mbed_official	146:f64d43ff0c18	1215	//@}
mbed_official	146:f64d43ff0c18	1216
mbed_official	146:f64d43ff0c18	1217	/*!
mbed_official	146:f64d43ff0c18	1218	* @name Register I2C_FLT, field SSIE[5] (RW)
mbed_official	146:f64d43ff0c18	1219	*
mbed_official	146:f64d43ff0c18	1220	* This bit enables the interrupt for I2C bus stop or start detection. To clear
mbed_official	146:f64d43ff0c18	1221	* the I2C bus stop or start detection interrupt: In the interrupt service
mbed_official	146:f64d43ff0c18	1222	* routine, first clear the STOPF or STARTF bit by writing 1 to it, and then clear the
mbed_official	146:f64d43ff0c18	1223	* IICIF bit in the status register. If this sequence is reversed, the IICIF bit
mbed_official	146:f64d43ff0c18	1224	* is asserted again.
mbed_official	146:f64d43ff0c18	1225	*
mbed_official	146:f64d43ff0c18	1226	* Values:
mbed_official	146:f64d43ff0c18	1227	* - 0 - Stop or start detection interrupt is disabled
mbed_official	146:f64d43ff0c18	1228	* - 1 - Stop or start detection interrupt is enabled
mbed_official	146:f64d43ff0c18	1229	*/
mbed_official	146:f64d43ff0c18	1230	//@{
mbed_official	146:f64d43ff0c18	1231	#define BP_I2C_FLT_SSIE (5U) //!< Bit position for I2C_FLT_SSIE.
mbed_official	146:f64d43ff0c18	1232	#define BM_I2C_FLT_SSIE (0x20U) //!< Bit mask for I2C_FLT_SSIE.
mbed_official	146:f64d43ff0c18	1233	#define BS_I2C_FLT_SSIE (1U) //!< Bit field size in bits for I2C_FLT_SSIE.
mbed_official	146:f64d43ff0c18	1234
mbed_official	146:f64d43ff0c18	1235	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1236	//! @brief Read current value of the I2C_FLT_SSIE field.
mbed_official	146:f64d43ff0c18	1237	#define BR_I2C_FLT_SSIE(x) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SSIE))
mbed_official	146:f64d43ff0c18	1238	#endif
mbed_official	146:f64d43ff0c18	1239
mbed_official	146:f64d43ff0c18	1240	//! @brief Format value for bitfield I2C_FLT_SSIE.
mbed_official	146:f64d43ff0c18	1241	#define BF_I2C_FLT_SSIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_FLT_SSIE), uint8_t) & BM_I2C_FLT_SSIE)
mbed_official	146:f64d43ff0c18	1242
mbed_official	146:f64d43ff0c18	1243	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1244	//! @brief Set the SSIE field to a new value.
mbed_official	146:f64d43ff0c18	1245	#define BW_I2C_FLT_SSIE(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SSIE) = (v))
mbed_official	146:f64d43ff0c18	1246	#endif
mbed_official	146:f64d43ff0c18	1247	//@}
mbed_official	146:f64d43ff0c18	1248
mbed_official	146:f64d43ff0c18	1249	/*!
mbed_official	146:f64d43ff0c18	1250	* @name Register I2C_FLT, field STOPF[6] (W1C)
mbed_official	146:f64d43ff0c18	1251	*
mbed_official	146:f64d43ff0c18	1252	* Hardware sets this bit when the I2C bus's stop status is detected. The STOPF
mbed_official	146:f64d43ff0c18	1253	* bit must be cleared by writing 1 to it.
mbed_official	146:f64d43ff0c18	1254	*
mbed_official	146:f64d43ff0c18	1255	* Values:
mbed_official	146:f64d43ff0c18	1256	* - 0 - No stop happens on I2C bus
mbed_official	146:f64d43ff0c18	1257	* - 1 - Stop detected on I2C bus
mbed_official	146:f64d43ff0c18	1258	*/
mbed_official	146:f64d43ff0c18	1259	//@{
mbed_official	146:f64d43ff0c18	1260	#define BP_I2C_FLT_STOPF (6U) //!< Bit position for I2C_FLT_STOPF.
mbed_official	146:f64d43ff0c18	1261	#define BM_I2C_FLT_STOPF (0x40U) //!< Bit mask for I2C_FLT_STOPF.
mbed_official	146:f64d43ff0c18	1262	#define BS_I2C_FLT_STOPF (1U) //!< Bit field size in bits for I2C_FLT_STOPF.
mbed_official	146:f64d43ff0c18	1263
mbed_official	146:f64d43ff0c18	1264	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1265	//! @brief Read current value of the I2C_FLT_STOPF field.
mbed_official	146:f64d43ff0c18	1266	#define BR_I2C_FLT_STOPF(x) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STOPF))
mbed_official	146:f64d43ff0c18	1267	#endif
mbed_official	146:f64d43ff0c18	1268
mbed_official	146:f64d43ff0c18	1269	//! @brief Format value for bitfield I2C_FLT_STOPF.
mbed_official	146:f64d43ff0c18	1270	#define BF_I2C_FLT_STOPF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_FLT_STOPF), uint8_t) & BM_I2C_FLT_STOPF)
mbed_official	146:f64d43ff0c18	1271
mbed_official	146:f64d43ff0c18	1272	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1273	//! @brief Set the STOPF field to a new value.
mbed_official	146:f64d43ff0c18	1274	#define BW_I2C_FLT_STOPF(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STOPF) = (v))
mbed_official	146:f64d43ff0c18	1275	#endif
mbed_official	146:f64d43ff0c18	1276	//@}
mbed_official	146:f64d43ff0c18	1277
mbed_official	146:f64d43ff0c18	1278	/*!
mbed_official	146:f64d43ff0c18	1279	* @name Register I2C_FLT, field SHEN[7] (RW)
mbed_official	146:f64d43ff0c18	1280	*
mbed_official	146:f64d43ff0c18	1281	* Set this bit to hold off entry to stop mode when any data transmission or
mbed_official	146:f64d43ff0c18	1282	* reception is occurring. The following scenario explains the holdoff
mbed_official	146:f64d43ff0c18	1283	* functionality: The I2C module is configured for a basic transfer, and the SHEN bit is set
mbed_official	146:f64d43ff0c18	1284	* to 1. A transfer begins. The MCU signals the I2C module to enter stop mode. The
mbed_official	146:f64d43ff0c18	1285	* byte currently being transferred, including both address and data, completes
mbed_official	146:f64d43ff0c18	1286	* its transfer. The I2C slave or master acknowledges that the in-transfer byte
mbed_official	146:f64d43ff0c18	1287	* completed its transfer and acknowledges the request to enter stop mode. After
mbed_official	146:f64d43ff0c18	1288	* receiving the I2C module's acknowledgment of the request to enter stop mode,
mbed_official	146:f64d43ff0c18	1289	* the MCU determines whether to shut off the I2C module's clock. If the SHEN bit
mbed_official	146:f64d43ff0c18	1290	* is set to 1 and the I2C module is in an idle or disabled state when the MCU
mbed_official	146:f64d43ff0c18	1291	* signals to enter stop mode, the module immediately acknowledges the request to
mbed_official	146:f64d43ff0c18	1292	* enter stop mode. If SHEN is cleared to 0 and the overall data transmission or
mbed_official	146:f64d43ff0c18	1293	* reception that was suspended by stop mode entry was incomplete: To resume the
mbed_official	146:f64d43ff0c18	1294	* overall transmission or reception after the MCU exits stop mode, software must
mbed_official	146:f64d43ff0c18	1295	* reinitialize the transfer by resending the address of the slave. If the I2C
mbed_official	146:f64d43ff0c18	1296	* Control Register 1's IICIE bit was set to 1 before the MCU entered stop mode,
mbed_official	146:f64d43ff0c18	1297	* system software will receive the interrupt triggered by the I2C Status Register's
mbed_official	146:f64d43ff0c18	1298	* TCF bit after the MCU wakes from the stop mode.
mbed_official	146:f64d43ff0c18	1299	*
mbed_official	146:f64d43ff0c18	1300	* Values:
mbed_official	146:f64d43ff0c18	1301	* - 0 - Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
mbed_official	146:f64d43ff0c18	1302	* - 1 - Stop holdoff is enabled.
mbed_official	146:f64d43ff0c18	1303	*/
mbed_official	146:f64d43ff0c18	1304	//@{
mbed_official	146:f64d43ff0c18	1305	#define BP_I2C_FLT_SHEN (7U) //!< Bit position for I2C_FLT_SHEN.
mbed_official	146:f64d43ff0c18	1306	#define BM_I2C_FLT_SHEN (0x80U) //!< Bit mask for I2C_FLT_SHEN.
mbed_official	146:f64d43ff0c18	1307	#define BS_I2C_FLT_SHEN (1U) //!< Bit field size in bits for I2C_FLT_SHEN.
mbed_official	146:f64d43ff0c18	1308
mbed_official	146:f64d43ff0c18	1309	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1310	//! @brief Read current value of the I2C_FLT_SHEN field.
mbed_official	146:f64d43ff0c18	1311	#define BR_I2C_FLT_SHEN(x) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SHEN))
mbed_official	146:f64d43ff0c18	1312	#endif
mbed_official	146:f64d43ff0c18	1313
mbed_official	146:f64d43ff0c18	1314	//! @brief Format value for bitfield I2C_FLT_SHEN.
mbed_official	146:f64d43ff0c18	1315	#define BF_I2C_FLT_SHEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_FLT_SHEN), uint8_t) & BM_I2C_FLT_SHEN)
mbed_official	146:f64d43ff0c18	1316
mbed_official	146:f64d43ff0c18	1317	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1318	//! @brief Set the SHEN field to a new value.
mbed_official	146:f64d43ff0c18	1319	#define BW_I2C_FLT_SHEN(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SHEN) = (v))
mbed_official	146:f64d43ff0c18	1320	#endif
mbed_official	146:f64d43ff0c18	1321	//@}
mbed_official	146:f64d43ff0c18	1322
mbed_official	146:f64d43ff0c18	1323	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1324	// HW_I2C_RA - I2C Range Address register
mbed_official	146:f64d43ff0c18	1325	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1326
mbed_official	146:f64d43ff0c18	1327	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1328	/*!
mbed_official	146:f64d43ff0c18	1329	* @brief HW_I2C_RA - I2C Range Address register (RW)
mbed_official	146:f64d43ff0c18	1330	*
mbed_official	146:f64d43ff0c18	1331	* Reset value: 0x00U
mbed_official	146:f64d43ff0c18	1332	*/
mbed_official	146:f64d43ff0c18	1333	typedef union _hw_i2c_ra
mbed_official	146:f64d43ff0c18	1334	{
mbed_official	146:f64d43ff0c18	1335	uint8_t U;
mbed_official	146:f64d43ff0c18	1336	struct _hw_i2c_ra_bitfields
mbed_official	146:f64d43ff0c18	1337	{
mbed_official	146:f64d43ff0c18	1338	uint8_t RESERVED0 : 1; //!< [0]
mbed_official	146:f64d43ff0c18	1339	uint8_t RAD : 7; //!< [7:1] Range Slave Address
mbed_official	146:f64d43ff0c18	1340	} B;
mbed_official	146:f64d43ff0c18	1341	} hw_i2c_ra_t;
mbed_official	146:f64d43ff0c18	1342	#endif
mbed_official	146:f64d43ff0c18	1343
mbed_official	146:f64d43ff0c18	1344	/*!
mbed_official	146:f64d43ff0c18	1345	* @name Constants and macros for entire I2C_RA register
mbed_official	146:f64d43ff0c18	1346	*/
mbed_official	146:f64d43ff0c18	1347	//@{
mbed_official	146:f64d43ff0c18	1348	#define HW_I2C_RA_ADDR(x) (REGS_I2C_BASE(x) + 0x7U)
mbed_official	146:f64d43ff0c18	1349
mbed_official	146:f64d43ff0c18	1350	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1351	#define HW_I2C_RA(x) ((__IO hw_i2c_ra_t ) HW_I2C_RA_ADDR(x))
mbed_official	146:f64d43ff0c18	1352	#define HW_I2C_RA_RD(x) (HW_I2C_RA(x).U)
mbed_official	146:f64d43ff0c18	1353	#define HW_I2C_RA_WR(x, v) (HW_I2C_RA(x).U = (v))
mbed_official	146:f64d43ff0c18	1354	#define HW_I2C_RA_SET(x, v) (HW_I2C_RA_WR(x, HW_I2C_RA_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	1355	#define HW_I2C_RA_CLR(x, v) (HW_I2C_RA_WR(x, HW_I2C_RA_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	1356	#define HW_I2C_RA_TOG(x, v) (HW_I2C_RA_WR(x, HW_I2C_RA_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	1357	#endif
mbed_official	146:f64d43ff0c18	1358	//@}
mbed_official	146:f64d43ff0c18	1359
mbed_official	146:f64d43ff0c18	1360	/*
mbed_official	146:f64d43ff0c18	1361	* Constants & macros for individual I2C_RA bitfields
mbed_official	146:f64d43ff0c18	1362	*/
mbed_official	146:f64d43ff0c18	1363
mbed_official	146:f64d43ff0c18	1364	/*!
mbed_official	146:f64d43ff0c18	1365	* @name Register I2C_RA, field RAD[7:1] (RW)
mbed_official	146:f64d43ff0c18	1366	*
mbed_official	146:f64d43ff0c18	1367	* This field contains the slave address to be used by the I2C module. The field
mbed_official	146:f64d43ff0c18	1368	* is used in the 7-bit address scheme. If I2C_C2[RMEN] is set to 1, any nonzero
mbed_official	146:f64d43ff0c18	1369	* value write enables this register. This register value can be considered as a
mbed_official	146:f64d43ff0c18	1370	* maximum boundary in the range matching mode.
mbed_official	146:f64d43ff0c18	1371	*/
mbed_official	146:f64d43ff0c18	1372	//@{
mbed_official	146:f64d43ff0c18	1373	#define BP_I2C_RA_RAD (1U) //!< Bit position for I2C_RA_RAD.
mbed_official	146:f64d43ff0c18	1374	#define BM_I2C_RA_RAD (0xFEU) //!< Bit mask for I2C_RA_RAD.
mbed_official	146:f64d43ff0c18	1375	#define BS_I2C_RA_RAD (7U) //!< Bit field size in bits for I2C_RA_RAD.
mbed_official	146:f64d43ff0c18	1376
mbed_official	146:f64d43ff0c18	1377	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1378	//! @brief Read current value of the I2C_RA_RAD field.
mbed_official	146:f64d43ff0c18	1379	#define BR_I2C_RA_RAD(x) (HW_I2C_RA(x).B.RAD)
mbed_official	146:f64d43ff0c18	1380	#endif
mbed_official	146:f64d43ff0c18	1381
mbed_official	146:f64d43ff0c18	1382	//! @brief Format value for bitfield I2C_RA_RAD.
mbed_official	146:f64d43ff0c18	1383	#define BF_I2C_RA_RAD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_RA_RAD), uint8_t) & BM_I2C_RA_RAD)
mbed_official	146:f64d43ff0c18	1384
mbed_official	146:f64d43ff0c18	1385	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1386	//! @brief Set the RAD field to a new value.
mbed_official	146:f64d43ff0c18	1387	#define BW_I2C_RA_RAD(x, v) (HW_I2C_RA_WR(x, (HW_I2C_RA_RD(x) & ~BM_I2C_RA_RAD) \| BF_I2C_RA_RAD(v)))
mbed_official	146:f64d43ff0c18	1388	#endif
mbed_official	146:f64d43ff0c18	1389	//@}
mbed_official	146:f64d43ff0c18	1390
mbed_official	146:f64d43ff0c18	1391	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1392	// HW_I2C_SMB - I2C SMBus Control and Status register
mbed_official	146:f64d43ff0c18	1393	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1394
mbed_official	146:f64d43ff0c18	1395	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1396	/*!
mbed_official	146:f64d43ff0c18	1397	* @brief HW_I2C_SMB - I2C SMBus Control and Status register (RW)
mbed_official	146:f64d43ff0c18	1398	*
mbed_official	146:f64d43ff0c18	1399	* Reset value: 0x00U
mbed_official	146:f64d43ff0c18	1400	*
mbed_official	146:f64d43ff0c18	1401	* When the SCL and SDA signals are held high for a length of time greater than
mbed_official	146:f64d43ff0c18	1402	* the high timeout period, the SHTF1 flag sets. Before reaching this threshold,
mbed_official	146:f64d43ff0c18	1403	* while the system is detecting how long these signals are being held high, a
mbed_official	146:f64d43ff0c18	1404	* master assumes that the bus is free. However, the SHTF1 bit is set to 1 in the
mbed_official	146:f64d43ff0c18	1405	* bus transmission process with the idle bus state. When the TCKSEL bit is set,
mbed_official	146:f64d43ff0c18	1406	* there is no need to monitor the SHTF1 bit because the bus speed is too high to
mbed_official	146:f64d43ff0c18	1407	* match the protocol of SMBus.
mbed_official	146:f64d43ff0c18	1408	*/
mbed_official	146:f64d43ff0c18	1409	typedef union _hw_i2c_smb
mbed_official	146:f64d43ff0c18	1410	{
mbed_official	146:f64d43ff0c18	1411	uint8_t U;
mbed_official	146:f64d43ff0c18	1412	struct _hw_i2c_smb_bitfields
mbed_official	146:f64d43ff0c18	1413	{
mbed_official	146:f64d43ff0c18	1414	uint8_t SHTF2IE : 1; //!< [0] SHTF2 Interrupt Enable
mbed_official	146:f64d43ff0c18	1415	uint8_t SHTF2 : 1; //!< [1] SCL High Timeout Flag 2
mbed_official	146:f64d43ff0c18	1416	uint8_t SHTF1 : 1; //!< [2] SCL High Timeout Flag 1
mbed_official	146:f64d43ff0c18	1417	uint8_t SLTF : 1; //!< [3] SCL Low Timeout Flag
mbed_official	146:f64d43ff0c18	1418	uint8_t TCKSEL : 1; //!< [4] Timeout Counter Clock Select
mbed_official	146:f64d43ff0c18	1419	uint8_t SIICAEN : 1; //!< [5] Second I2C Address Enable
mbed_official	146:f64d43ff0c18	1420	uint8_t ALERTEN : 1; //!< [6] SMBus Alert Response Address Enable
mbed_official	146:f64d43ff0c18	1421	uint8_t FACK : 1; //!< [7] Fast NACK/ACK Enable
mbed_official	146:f64d43ff0c18	1422	} B;
mbed_official	146:f64d43ff0c18	1423	} hw_i2c_smb_t;
mbed_official	146:f64d43ff0c18	1424	#endif
mbed_official	146:f64d43ff0c18	1425
mbed_official	146:f64d43ff0c18	1426	/*!
mbed_official	146:f64d43ff0c18	1427	* @name Constants and macros for entire I2C_SMB register
mbed_official	146:f64d43ff0c18	1428	*/
mbed_official	146:f64d43ff0c18	1429	//@{
mbed_official	146:f64d43ff0c18	1430	#define HW_I2C_SMB_ADDR(x) (REGS_I2C_BASE(x) + 0x8U)
mbed_official	146:f64d43ff0c18	1431
mbed_official	146:f64d43ff0c18	1432	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1433	#define HW_I2C_SMB(x) ((__IO hw_i2c_smb_t ) HW_I2C_SMB_ADDR(x))
mbed_official	146:f64d43ff0c18	1434	#define HW_I2C_SMB_RD(x) (HW_I2C_SMB(x).U)
mbed_official	146:f64d43ff0c18	1435	#define HW_I2C_SMB_WR(x, v) (HW_I2C_SMB(x).U = (v))
mbed_official	146:f64d43ff0c18	1436	#define HW_I2C_SMB_SET(x, v) (HW_I2C_SMB_WR(x, HW_I2C_SMB_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	1437	#define HW_I2C_SMB_CLR(x, v) (HW_I2C_SMB_WR(x, HW_I2C_SMB_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	1438	#define HW_I2C_SMB_TOG(x, v) (HW_I2C_SMB_WR(x, HW_I2C_SMB_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	1439	#endif
mbed_official	146:f64d43ff0c18	1440	//@}
mbed_official	146:f64d43ff0c18	1441
mbed_official	146:f64d43ff0c18	1442	/*
mbed_official	146:f64d43ff0c18	1443	* Constants & macros for individual I2C_SMB bitfields
mbed_official	146:f64d43ff0c18	1444	*/
mbed_official	146:f64d43ff0c18	1445
mbed_official	146:f64d43ff0c18	1446	/*!
mbed_official	146:f64d43ff0c18	1447	* @name Register I2C_SMB, field SHTF2IE[0] (RW)
mbed_official	146:f64d43ff0c18	1448	*
mbed_official	146:f64d43ff0c18	1449	* Enables SCL high and SDA low timeout interrupt.
mbed_official	146:f64d43ff0c18	1450	*
mbed_official	146:f64d43ff0c18	1451	* Values:
mbed_official	146:f64d43ff0c18	1452	* - 0 - SHTF2 interrupt is disabled
mbed_official	146:f64d43ff0c18	1453	* - 1 - SHTF2 interrupt is enabled
mbed_official	146:f64d43ff0c18	1454	*/
mbed_official	146:f64d43ff0c18	1455	//@{
mbed_official	146:f64d43ff0c18	1456	#define BP_I2C_SMB_SHTF2IE (0U) //!< Bit position for I2C_SMB_SHTF2IE.
mbed_official	146:f64d43ff0c18	1457	#define BM_I2C_SMB_SHTF2IE (0x01U) //!< Bit mask for I2C_SMB_SHTF2IE.
mbed_official	146:f64d43ff0c18	1458	#define BS_I2C_SMB_SHTF2IE (1U) //!< Bit field size in bits for I2C_SMB_SHTF2IE.
mbed_official	146:f64d43ff0c18	1459
mbed_official	146:f64d43ff0c18	1460	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1461	//! @brief Read current value of the I2C_SMB_SHTF2IE field.
mbed_official	146:f64d43ff0c18	1462	#define BR_I2C_SMB_SHTF2IE(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2IE))
mbed_official	146:f64d43ff0c18	1463	#endif
mbed_official	146:f64d43ff0c18	1464
mbed_official	146:f64d43ff0c18	1465	//! @brief Format value for bitfield I2C_SMB_SHTF2IE.
mbed_official	146:f64d43ff0c18	1466	#define BF_I2C_SMB_SHTF2IE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SMB_SHTF2IE), uint8_t) & BM_I2C_SMB_SHTF2IE)
mbed_official	146:f64d43ff0c18	1467
mbed_official	146:f64d43ff0c18	1468	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1469	//! @brief Set the SHTF2IE field to a new value.
mbed_official	146:f64d43ff0c18	1470	#define BW_I2C_SMB_SHTF2IE(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2IE) = (v))
mbed_official	146:f64d43ff0c18	1471	#endif
mbed_official	146:f64d43ff0c18	1472	//@}
mbed_official	146:f64d43ff0c18	1473
mbed_official	146:f64d43ff0c18	1474	/*!
mbed_official	146:f64d43ff0c18	1475	* @name Register I2C_SMB, field SHTF2[1] (W1C)
mbed_official	146:f64d43ff0c18	1476	*
mbed_official	146:f64d43ff0c18	1477	* This bit sets when SCL is held high and SDA is held low more than clock *
mbed_official	146:f64d43ff0c18	1478	* LoValue / 512. Software clears this bit by writing 1 to it.
mbed_official	146:f64d43ff0c18	1479	*
mbed_official	146:f64d43ff0c18	1480	* Values:
mbed_official	146:f64d43ff0c18	1481	* - 0 - No SCL high and SDA low timeout occurs
mbed_official	146:f64d43ff0c18	1482	* - 1 - SCL high and SDA low timeout occurs
mbed_official	146:f64d43ff0c18	1483	*/
mbed_official	146:f64d43ff0c18	1484	//@{
mbed_official	146:f64d43ff0c18	1485	#define BP_I2C_SMB_SHTF2 (1U) //!< Bit position for I2C_SMB_SHTF2.
mbed_official	146:f64d43ff0c18	1486	#define BM_I2C_SMB_SHTF2 (0x02U) //!< Bit mask for I2C_SMB_SHTF2.
mbed_official	146:f64d43ff0c18	1487	#define BS_I2C_SMB_SHTF2 (1U) //!< Bit field size in bits for I2C_SMB_SHTF2.
mbed_official	146:f64d43ff0c18	1488
mbed_official	146:f64d43ff0c18	1489	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1490	//! @brief Read current value of the I2C_SMB_SHTF2 field.
mbed_official	146:f64d43ff0c18	1491	#define BR_I2C_SMB_SHTF2(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2))
mbed_official	146:f64d43ff0c18	1492	#endif
mbed_official	146:f64d43ff0c18	1493
mbed_official	146:f64d43ff0c18	1494	//! @brief Format value for bitfield I2C_SMB_SHTF2.
mbed_official	146:f64d43ff0c18	1495	#define BF_I2C_SMB_SHTF2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SMB_SHTF2), uint8_t) & BM_I2C_SMB_SHTF2)
mbed_official	146:f64d43ff0c18	1496
mbed_official	146:f64d43ff0c18	1497	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1498	//! @brief Set the SHTF2 field to a new value.
mbed_official	146:f64d43ff0c18	1499	#define BW_I2C_SMB_SHTF2(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2) = (v))
mbed_official	146:f64d43ff0c18	1500	#endif
mbed_official	146:f64d43ff0c18	1501	//@}
mbed_official	146:f64d43ff0c18	1502
mbed_official	146:f64d43ff0c18	1503	/*!
mbed_official	146:f64d43ff0c18	1504	* @name Register I2C_SMB, field SHTF1[2] (RO)
mbed_official	146:f64d43ff0c18	1505	*
mbed_official	146:f64d43ff0c18	1506	* This read-only bit sets when SCL and SDA are held high more than clock *
mbed_official	146:f64d43ff0c18	1507	* LoValue / 512, which indicates the bus is free. This bit is cleared automatically.
mbed_official	146:f64d43ff0c18	1508	*
mbed_official	146:f64d43ff0c18	1509	* Values:
mbed_official	146:f64d43ff0c18	1510	* - 0 - No SCL high and SDA high timeout occurs
mbed_official	146:f64d43ff0c18	1511	* - 1 - SCL high and SDA high timeout occurs
mbed_official	146:f64d43ff0c18	1512	*/
mbed_official	146:f64d43ff0c18	1513	//@{
mbed_official	146:f64d43ff0c18	1514	#define BP_I2C_SMB_SHTF1 (2U) //!< Bit position for I2C_SMB_SHTF1.
mbed_official	146:f64d43ff0c18	1515	#define BM_I2C_SMB_SHTF1 (0x04U) //!< Bit mask for I2C_SMB_SHTF1.
mbed_official	146:f64d43ff0c18	1516	#define BS_I2C_SMB_SHTF1 (1U) //!< Bit field size in bits for I2C_SMB_SHTF1.
mbed_official	146:f64d43ff0c18	1517
mbed_official	146:f64d43ff0c18	1518	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1519	//! @brief Read current value of the I2C_SMB_SHTF1 field.
mbed_official	146:f64d43ff0c18	1520	#define BR_I2C_SMB_SHTF1(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF1))
mbed_official	146:f64d43ff0c18	1521	#endif
mbed_official	146:f64d43ff0c18	1522	//@}
mbed_official	146:f64d43ff0c18	1523
mbed_official	146:f64d43ff0c18	1524	/*!
mbed_official	146:f64d43ff0c18	1525	* @name Register I2C_SMB, field SLTF[3] (W1C)
mbed_official	146:f64d43ff0c18	1526	*
mbed_official	146:f64d43ff0c18	1527	* This bit is set when the SLT register (consisting of the SLTH and SLTL
mbed_official	146:f64d43ff0c18	1528	* registers) is loaded with a non-zero value (LoValue) and an SCL low timeout occurs.
mbed_official	146:f64d43ff0c18	1529	* Software clears this bit by writing a logic 1 to it. The low timeout function
mbed_official	146:f64d43ff0c18	1530	* is disabled when the SLT register's value is 0.
mbed_official	146:f64d43ff0c18	1531	*
mbed_official	146:f64d43ff0c18	1532	* Values:
mbed_official	146:f64d43ff0c18	1533	* - 0 - No low timeout occurs
mbed_official	146:f64d43ff0c18	1534	* - 1 - Low timeout occurs
mbed_official	146:f64d43ff0c18	1535	*/
mbed_official	146:f64d43ff0c18	1536	//@{
mbed_official	146:f64d43ff0c18	1537	#define BP_I2C_SMB_SLTF (3U) //!< Bit position for I2C_SMB_SLTF.
mbed_official	146:f64d43ff0c18	1538	#define BM_I2C_SMB_SLTF (0x08U) //!< Bit mask for I2C_SMB_SLTF.
mbed_official	146:f64d43ff0c18	1539	#define BS_I2C_SMB_SLTF (1U) //!< Bit field size in bits for I2C_SMB_SLTF.
mbed_official	146:f64d43ff0c18	1540
mbed_official	146:f64d43ff0c18	1541	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1542	//! @brief Read current value of the I2C_SMB_SLTF field.
mbed_official	146:f64d43ff0c18	1543	#define BR_I2C_SMB_SLTF(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SLTF))
mbed_official	146:f64d43ff0c18	1544	#endif
mbed_official	146:f64d43ff0c18	1545
mbed_official	146:f64d43ff0c18	1546	//! @brief Format value for bitfield I2C_SMB_SLTF.
mbed_official	146:f64d43ff0c18	1547	#define BF_I2C_SMB_SLTF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SMB_SLTF), uint8_t) & BM_I2C_SMB_SLTF)
mbed_official	146:f64d43ff0c18	1548
mbed_official	146:f64d43ff0c18	1549	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1550	//! @brief Set the SLTF field to a new value.
mbed_official	146:f64d43ff0c18	1551	#define BW_I2C_SMB_SLTF(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SLTF) = (v))
mbed_official	146:f64d43ff0c18	1552	#endif
mbed_official	146:f64d43ff0c18	1553	//@}
mbed_official	146:f64d43ff0c18	1554
mbed_official	146:f64d43ff0c18	1555	/*!
mbed_official	146:f64d43ff0c18	1556	* @name Register I2C_SMB, field TCKSEL[4] (RW)
mbed_official	146:f64d43ff0c18	1557	*
mbed_official	146:f64d43ff0c18	1558	* Selects the clock source of the timeout counter.
mbed_official	146:f64d43ff0c18	1559	*
mbed_official	146:f64d43ff0c18	1560	* Values:
mbed_official	146:f64d43ff0c18	1561	* - 0 - Timeout counter counts at the frequency of the I2C module clock / 64
mbed_official	146:f64d43ff0c18	1562	* - 1 - Timeout counter counts at the frequency of the I2C module clock
mbed_official	146:f64d43ff0c18	1563	*/
mbed_official	146:f64d43ff0c18	1564	//@{
mbed_official	146:f64d43ff0c18	1565	#define BP_I2C_SMB_TCKSEL (4U) //!< Bit position for I2C_SMB_TCKSEL.
mbed_official	146:f64d43ff0c18	1566	#define BM_I2C_SMB_TCKSEL (0x10U) //!< Bit mask for I2C_SMB_TCKSEL.
mbed_official	146:f64d43ff0c18	1567	#define BS_I2C_SMB_TCKSEL (1U) //!< Bit field size in bits for I2C_SMB_TCKSEL.
mbed_official	146:f64d43ff0c18	1568
mbed_official	146:f64d43ff0c18	1569	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1570	//! @brief Read current value of the I2C_SMB_TCKSEL field.
mbed_official	146:f64d43ff0c18	1571	#define BR_I2C_SMB_TCKSEL(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_TCKSEL))
mbed_official	146:f64d43ff0c18	1572	#endif
mbed_official	146:f64d43ff0c18	1573
mbed_official	146:f64d43ff0c18	1574	//! @brief Format value for bitfield I2C_SMB_TCKSEL.
mbed_official	146:f64d43ff0c18	1575	#define BF_I2C_SMB_TCKSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SMB_TCKSEL), uint8_t) & BM_I2C_SMB_TCKSEL)
mbed_official	146:f64d43ff0c18	1576
mbed_official	146:f64d43ff0c18	1577	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1578	//! @brief Set the TCKSEL field to a new value.
mbed_official	146:f64d43ff0c18	1579	#define BW_I2C_SMB_TCKSEL(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_TCKSEL) = (v))
mbed_official	146:f64d43ff0c18	1580	#endif
mbed_official	146:f64d43ff0c18	1581	//@}
mbed_official	146:f64d43ff0c18	1582
mbed_official	146:f64d43ff0c18	1583	/*!
mbed_official	146:f64d43ff0c18	1584	* @name Register I2C_SMB, field SIICAEN[5] (RW)
mbed_official	146:f64d43ff0c18	1585	*
mbed_official	146:f64d43ff0c18	1586	* Enables or disables SMBus device default address.
mbed_official	146:f64d43ff0c18	1587	*
mbed_official	146:f64d43ff0c18	1588	* Values:
mbed_official	146:f64d43ff0c18	1589	* - 0 - I2C address register 2 matching is disabled
mbed_official	146:f64d43ff0c18	1590	* - 1 - I2C address register 2 matching is enabled
mbed_official	146:f64d43ff0c18	1591	*/
mbed_official	146:f64d43ff0c18	1592	//@{
mbed_official	146:f64d43ff0c18	1593	#define BP_I2C_SMB_SIICAEN (5U) //!< Bit position for I2C_SMB_SIICAEN.
mbed_official	146:f64d43ff0c18	1594	#define BM_I2C_SMB_SIICAEN (0x20U) //!< Bit mask for I2C_SMB_SIICAEN.
mbed_official	146:f64d43ff0c18	1595	#define BS_I2C_SMB_SIICAEN (1U) //!< Bit field size in bits for I2C_SMB_SIICAEN.
mbed_official	146:f64d43ff0c18	1596
mbed_official	146:f64d43ff0c18	1597	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1598	//! @brief Read current value of the I2C_SMB_SIICAEN field.
mbed_official	146:f64d43ff0c18	1599	#define BR_I2C_SMB_SIICAEN(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SIICAEN))
mbed_official	146:f64d43ff0c18	1600	#endif
mbed_official	146:f64d43ff0c18	1601
mbed_official	146:f64d43ff0c18	1602	//! @brief Format value for bitfield I2C_SMB_SIICAEN.
mbed_official	146:f64d43ff0c18	1603	#define BF_I2C_SMB_SIICAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SMB_SIICAEN), uint8_t) & BM_I2C_SMB_SIICAEN)
mbed_official	146:f64d43ff0c18	1604
mbed_official	146:f64d43ff0c18	1605	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1606	//! @brief Set the SIICAEN field to a new value.
mbed_official	146:f64d43ff0c18	1607	#define BW_I2C_SMB_SIICAEN(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SIICAEN) = (v))
mbed_official	146:f64d43ff0c18	1608	#endif
mbed_official	146:f64d43ff0c18	1609	//@}
mbed_official	146:f64d43ff0c18	1610
mbed_official	146:f64d43ff0c18	1611	/*!
mbed_official	146:f64d43ff0c18	1612	* @name Register I2C_SMB, field ALERTEN[6] (RW)
mbed_official	146:f64d43ff0c18	1613	*
mbed_official	146:f64d43ff0c18	1614	* Enables or disables SMBus alert response address matching. After the host
mbed_official	146:f64d43ff0c18	1615	* responds to a device that used the alert response address, you must use software
mbed_official	146:f64d43ff0c18	1616	* to put the device's address on the bus. The alert protocol is described in the
mbed_official	146:f64d43ff0c18	1617	* SMBus specification.
mbed_official	146:f64d43ff0c18	1618	*
mbed_official	146:f64d43ff0c18	1619	* Values:
mbed_official	146:f64d43ff0c18	1620	* - 0 - SMBus alert response address matching is disabled
mbed_official	146:f64d43ff0c18	1621	* - 1 - SMBus alert response address matching is enabled
mbed_official	146:f64d43ff0c18	1622	*/
mbed_official	146:f64d43ff0c18	1623	//@{
mbed_official	146:f64d43ff0c18	1624	#define BP_I2C_SMB_ALERTEN (6U) //!< Bit position for I2C_SMB_ALERTEN.
mbed_official	146:f64d43ff0c18	1625	#define BM_I2C_SMB_ALERTEN (0x40U) //!< Bit mask for I2C_SMB_ALERTEN.
mbed_official	146:f64d43ff0c18	1626	#define BS_I2C_SMB_ALERTEN (1U) //!< Bit field size in bits for I2C_SMB_ALERTEN.
mbed_official	146:f64d43ff0c18	1627
mbed_official	146:f64d43ff0c18	1628	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1629	//! @brief Read current value of the I2C_SMB_ALERTEN field.
mbed_official	146:f64d43ff0c18	1630	#define BR_I2C_SMB_ALERTEN(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_ALERTEN))
mbed_official	146:f64d43ff0c18	1631	#endif
mbed_official	146:f64d43ff0c18	1632
mbed_official	146:f64d43ff0c18	1633	//! @brief Format value for bitfield I2C_SMB_ALERTEN.
mbed_official	146:f64d43ff0c18	1634	#define BF_I2C_SMB_ALERTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SMB_ALERTEN), uint8_t) & BM_I2C_SMB_ALERTEN)
mbed_official	146:f64d43ff0c18	1635
mbed_official	146:f64d43ff0c18	1636	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1637	//! @brief Set the ALERTEN field to a new value.
mbed_official	146:f64d43ff0c18	1638	#define BW_I2C_SMB_ALERTEN(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_ALERTEN) = (v))
mbed_official	146:f64d43ff0c18	1639	#endif
mbed_official	146:f64d43ff0c18	1640	//@}
mbed_official	146:f64d43ff0c18	1641
mbed_official	146:f64d43ff0c18	1642	/*!
mbed_official	146:f64d43ff0c18	1643	* @name Register I2C_SMB, field FACK[7] (RW)
mbed_official	146:f64d43ff0c18	1644	*
mbed_official	146:f64d43ff0c18	1645	* For SMBus packet error checking, the CPU must be able to issue an ACK or NACK
mbed_official	146:f64d43ff0c18	1646	* according to the result of receiving data byte.
mbed_official	146:f64d43ff0c18	1647	*
mbed_official	146:f64d43ff0c18	1648	* Values:
mbed_official	146:f64d43ff0c18	1649	* - 0 - An ACK or NACK is sent on the following receiving data byte
mbed_official	146:f64d43ff0c18	1650	* - 1 - Writing 0 to TXAK after receiving a data byte generates an ACK. Writing
mbed_official	146:f64d43ff0c18	1651	* 1 to TXAK after receiving a data byte generates a NACK.
mbed_official	146:f64d43ff0c18	1652	*/
mbed_official	146:f64d43ff0c18	1653	//@{
mbed_official	146:f64d43ff0c18	1654	#define BP_I2C_SMB_FACK (7U) //!< Bit position for I2C_SMB_FACK.
mbed_official	146:f64d43ff0c18	1655	#define BM_I2C_SMB_FACK (0x80U) //!< Bit mask for I2C_SMB_FACK.
mbed_official	146:f64d43ff0c18	1656	#define BS_I2C_SMB_FACK (1U) //!< Bit field size in bits for I2C_SMB_FACK.
mbed_official	146:f64d43ff0c18	1657
mbed_official	146:f64d43ff0c18	1658	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1659	//! @brief Read current value of the I2C_SMB_FACK field.
mbed_official	146:f64d43ff0c18	1660	#define BR_I2C_SMB_FACK(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_FACK))
mbed_official	146:f64d43ff0c18	1661	#endif
mbed_official	146:f64d43ff0c18	1662
mbed_official	146:f64d43ff0c18	1663	//! @brief Format value for bitfield I2C_SMB_FACK.
mbed_official	146:f64d43ff0c18	1664	#define BF_I2C_SMB_FACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SMB_FACK), uint8_t) & BM_I2C_SMB_FACK)
mbed_official	146:f64d43ff0c18	1665
mbed_official	146:f64d43ff0c18	1666	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1667	//! @brief Set the FACK field to a new value.
mbed_official	146:f64d43ff0c18	1668	#define BW_I2C_SMB_FACK(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_FACK) = (v))
mbed_official	146:f64d43ff0c18	1669	#endif
mbed_official	146:f64d43ff0c18	1670	//@}
mbed_official	146:f64d43ff0c18	1671
mbed_official	146:f64d43ff0c18	1672	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1673	// HW_I2C_A2 - I2C Address Register 2
mbed_official	146:f64d43ff0c18	1674	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1675
mbed_official	146:f64d43ff0c18	1676	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1677	/*!
mbed_official	146:f64d43ff0c18	1678	* @brief HW_I2C_A2 - I2C Address Register 2 (RW)
mbed_official	146:f64d43ff0c18	1679	*
mbed_official	146:f64d43ff0c18	1680	* Reset value: 0xC2U
mbed_official	146:f64d43ff0c18	1681	*/
mbed_official	146:f64d43ff0c18	1682	typedef union _hw_i2c_a2
mbed_official	146:f64d43ff0c18	1683	{
mbed_official	146:f64d43ff0c18	1684	uint8_t U;
mbed_official	146:f64d43ff0c18	1685	struct _hw_i2c_a2_bitfields
mbed_official	146:f64d43ff0c18	1686	{
mbed_official	146:f64d43ff0c18	1687	uint8_t RESERVED0 : 1; //!< [0]
mbed_official	146:f64d43ff0c18	1688	uint8_t SAD : 7; //!< [7:1] SMBus Address
mbed_official	146:f64d43ff0c18	1689	} B;
mbed_official	146:f64d43ff0c18	1690	} hw_i2c_a2_t;
mbed_official	146:f64d43ff0c18	1691	#endif
mbed_official	146:f64d43ff0c18	1692
mbed_official	146:f64d43ff0c18	1693	/*!
mbed_official	146:f64d43ff0c18	1694	* @name Constants and macros for entire I2C_A2 register
mbed_official	146:f64d43ff0c18	1695	*/
mbed_official	146:f64d43ff0c18	1696	//@{
mbed_official	146:f64d43ff0c18	1697	#define HW_I2C_A2_ADDR(x) (REGS_I2C_BASE(x) + 0x9U)
mbed_official	146:f64d43ff0c18	1698
mbed_official	146:f64d43ff0c18	1699	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1700	#define HW_I2C_A2(x) ((__IO hw_i2c_a2_t ) HW_I2C_A2_ADDR(x))
mbed_official	146:f64d43ff0c18	1701	#define HW_I2C_A2_RD(x) (HW_I2C_A2(x).U)
mbed_official	146:f64d43ff0c18	1702	#define HW_I2C_A2_WR(x, v) (HW_I2C_A2(x).U = (v))
mbed_official	146:f64d43ff0c18	1703	#define HW_I2C_A2_SET(x, v) (HW_I2C_A2_WR(x, HW_I2C_A2_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	1704	#define HW_I2C_A2_CLR(x, v) (HW_I2C_A2_WR(x, HW_I2C_A2_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	1705	#define HW_I2C_A2_TOG(x, v) (HW_I2C_A2_WR(x, HW_I2C_A2_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	1706	#endif
mbed_official	146:f64d43ff0c18	1707	//@}
mbed_official	146:f64d43ff0c18	1708
mbed_official	146:f64d43ff0c18	1709	/*
mbed_official	146:f64d43ff0c18	1710	* Constants & macros for individual I2C_A2 bitfields
mbed_official	146:f64d43ff0c18	1711	*/
mbed_official	146:f64d43ff0c18	1712
mbed_official	146:f64d43ff0c18	1713	/*!
mbed_official	146:f64d43ff0c18	1714	* @name Register I2C_A2, field SAD[7:1] (RW)
mbed_official	146:f64d43ff0c18	1715	*
mbed_official	146:f64d43ff0c18	1716	* Contains the slave address used by the SMBus. This field is used on the
mbed_official	146:f64d43ff0c18	1717	* device default address or other related addresses.
mbed_official	146:f64d43ff0c18	1718	*/
mbed_official	146:f64d43ff0c18	1719	//@{
mbed_official	146:f64d43ff0c18	1720	#define BP_I2C_A2_SAD (1U) //!< Bit position for I2C_A2_SAD.
mbed_official	146:f64d43ff0c18	1721	#define BM_I2C_A2_SAD (0xFEU) //!< Bit mask for I2C_A2_SAD.
mbed_official	146:f64d43ff0c18	1722	#define BS_I2C_A2_SAD (7U) //!< Bit field size in bits for I2C_A2_SAD.
mbed_official	146:f64d43ff0c18	1723
mbed_official	146:f64d43ff0c18	1724	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1725	//! @brief Read current value of the I2C_A2_SAD field.
mbed_official	146:f64d43ff0c18	1726	#define BR_I2C_A2_SAD(x) (HW_I2C_A2(x).B.SAD)
mbed_official	146:f64d43ff0c18	1727	#endif
mbed_official	146:f64d43ff0c18	1728
mbed_official	146:f64d43ff0c18	1729	//! @brief Format value for bitfield I2C_A2_SAD.
mbed_official	146:f64d43ff0c18	1730	#define BF_I2C_A2_SAD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_A2_SAD), uint8_t) & BM_I2C_A2_SAD)
mbed_official	146:f64d43ff0c18	1731
mbed_official	146:f64d43ff0c18	1732	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1733	//! @brief Set the SAD field to a new value.
mbed_official	146:f64d43ff0c18	1734	#define BW_I2C_A2_SAD(x, v) (HW_I2C_A2_WR(x, (HW_I2C_A2_RD(x) & ~BM_I2C_A2_SAD) \| BF_I2C_A2_SAD(v)))
mbed_official	146:f64d43ff0c18	1735	#endif
mbed_official	146:f64d43ff0c18	1736	//@}
mbed_official	146:f64d43ff0c18	1737
mbed_official	146:f64d43ff0c18	1738	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1739	// HW_I2C_SLTH - I2C SCL Low Timeout Register High
mbed_official	146:f64d43ff0c18	1740	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1741
mbed_official	146:f64d43ff0c18	1742	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1743	/*!
mbed_official	146:f64d43ff0c18	1744	* @brief HW_I2C_SLTH - I2C SCL Low Timeout Register High (RW)
mbed_official	146:f64d43ff0c18	1745	*
mbed_official	146:f64d43ff0c18	1746	* Reset value: 0x00U
mbed_official	146:f64d43ff0c18	1747	*/
mbed_official	146:f64d43ff0c18	1748	typedef union _hw_i2c_slth
mbed_official	146:f64d43ff0c18	1749	{
mbed_official	146:f64d43ff0c18	1750	uint8_t U;
mbed_official	146:f64d43ff0c18	1751	struct _hw_i2c_slth_bitfields
mbed_official	146:f64d43ff0c18	1752	{
mbed_official	146:f64d43ff0c18	1753	uint8_t SSLT : 8; //!< [7:0]
mbed_official	146:f64d43ff0c18	1754	} B;
mbed_official	146:f64d43ff0c18	1755	} hw_i2c_slth_t;
mbed_official	146:f64d43ff0c18	1756	#endif
mbed_official	146:f64d43ff0c18	1757
mbed_official	146:f64d43ff0c18	1758	/*!
mbed_official	146:f64d43ff0c18	1759	* @name Constants and macros for entire I2C_SLTH register
mbed_official	146:f64d43ff0c18	1760	*/
mbed_official	146:f64d43ff0c18	1761	//@{
mbed_official	146:f64d43ff0c18	1762	#define HW_I2C_SLTH_ADDR(x) (REGS_I2C_BASE(x) + 0xAU)
mbed_official	146:f64d43ff0c18	1763
mbed_official	146:f64d43ff0c18	1764	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1765	#define HW_I2C_SLTH(x) ((__IO hw_i2c_slth_t ) HW_I2C_SLTH_ADDR(x))
mbed_official	146:f64d43ff0c18	1766	#define HW_I2C_SLTH_RD(x) (HW_I2C_SLTH(x).U)
mbed_official	146:f64d43ff0c18	1767	#define HW_I2C_SLTH_WR(x, v) (HW_I2C_SLTH(x).U = (v))
mbed_official	146:f64d43ff0c18	1768	#define HW_I2C_SLTH_SET(x, v) (HW_I2C_SLTH_WR(x, HW_I2C_SLTH_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	1769	#define HW_I2C_SLTH_CLR(x, v) (HW_I2C_SLTH_WR(x, HW_I2C_SLTH_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	1770	#define HW_I2C_SLTH_TOG(x, v) (HW_I2C_SLTH_WR(x, HW_I2C_SLTH_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	1771	#endif
mbed_official	146:f64d43ff0c18	1772	//@}
mbed_official	146:f64d43ff0c18	1773
mbed_official	146:f64d43ff0c18	1774	/*
mbed_official	146:f64d43ff0c18	1775	* Constants & macros for individual I2C_SLTH bitfields
mbed_official	146:f64d43ff0c18	1776	*/
mbed_official	146:f64d43ff0c18	1777
mbed_official	146:f64d43ff0c18	1778	/*!
mbed_official	146:f64d43ff0c18	1779	* @name Register I2C_SLTH, field SSLT[7:0] (RW)
mbed_official	146:f64d43ff0c18	1780	*
mbed_official	146:f64d43ff0c18	1781	* Most significant byte of SCL low timeout value that determines the timeout
mbed_official	146:f64d43ff0c18	1782	* period of SCL low.
mbed_official	146:f64d43ff0c18	1783	*/
mbed_official	146:f64d43ff0c18	1784	//@{
mbed_official	146:f64d43ff0c18	1785	#define BP_I2C_SLTH_SSLT (0U) //!< Bit position for I2C_SLTH_SSLT.
mbed_official	146:f64d43ff0c18	1786	#define BM_I2C_SLTH_SSLT (0xFFU) //!< Bit mask for I2C_SLTH_SSLT.
mbed_official	146:f64d43ff0c18	1787	#define BS_I2C_SLTH_SSLT (8U) //!< Bit field size in bits for I2C_SLTH_SSLT.
mbed_official	146:f64d43ff0c18	1788
mbed_official	146:f64d43ff0c18	1789	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1790	//! @brief Read current value of the I2C_SLTH_SSLT field.
mbed_official	146:f64d43ff0c18	1791	#define BR_I2C_SLTH_SSLT(x) (HW_I2C_SLTH(x).U)
mbed_official	146:f64d43ff0c18	1792	#endif
mbed_official	146:f64d43ff0c18	1793
mbed_official	146:f64d43ff0c18	1794	//! @brief Format value for bitfield I2C_SLTH_SSLT.
mbed_official	146:f64d43ff0c18	1795	#define BF_I2C_SLTH_SSLT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SLTH_SSLT), uint8_t) & BM_I2C_SLTH_SSLT)
mbed_official	146:f64d43ff0c18	1796
mbed_official	146:f64d43ff0c18	1797	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1798	//! @brief Set the SSLT field to a new value.
mbed_official	146:f64d43ff0c18	1799	#define BW_I2C_SLTH_SSLT(x, v) (HW_I2C_SLTH_WR(x, v))
mbed_official	146:f64d43ff0c18	1800	#endif
mbed_official	146:f64d43ff0c18	1801	//@}
mbed_official	146:f64d43ff0c18	1802
mbed_official	146:f64d43ff0c18	1803	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1804	// HW_I2C_SLTL - I2C SCL Low Timeout Register Low
mbed_official	146:f64d43ff0c18	1805	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1806
mbed_official	146:f64d43ff0c18	1807	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1808	/*!
mbed_official	146:f64d43ff0c18	1809	* @brief HW_I2C_SLTL - I2C SCL Low Timeout Register Low (RW)
mbed_official	146:f64d43ff0c18	1810	*
mbed_official	146:f64d43ff0c18	1811	* Reset value: 0x00U
mbed_official	146:f64d43ff0c18	1812	*/
mbed_official	146:f64d43ff0c18	1813	typedef union _hw_i2c_sltl
mbed_official	146:f64d43ff0c18	1814	{
mbed_official	146:f64d43ff0c18	1815	uint8_t U;
mbed_official	146:f64d43ff0c18	1816	struct _hw_i2c_sltl_bitfields
mbed_official	146:f64d43ff0c18	1817	{
mbed_official	146:f64d43ff0c18	1818	uint8_t SSLT : 8; //!< [7:0]
mbed_official	146:f64d43ff0c18	1819	} B;
mbed_official	146:f64d43ff0c18	1820	} hw_i2c_sltl_t;
mbed_official	146:f64d43ff0c18	1821	#endif
mbed_official	146:f64d43ff0c18	1822
mbed_official	146:f64d43ff0c18	1823	/*!
mbed_official	146:f64d43ff0c18	1824	* @name Constants and macros for entire I2C_SLTL register
mbed_official	146:f64d43ff0c18	1825	*/
mbed_official	146:f64d43ff0c18	1826	//@{
mbed_official	146:f64d43ff0c18	1827	#define HW_I2C_SLTL_ADDR(x) (REGS_I2C_BASE(x) + 0xBU)
mbed_official	146:f64d43ff0c18	1828
mbed_official	146:f64d43ff0c18	1829	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1830	#define HW_I2C_SLTL(x) ((__IO hw_i2c_sltl_t ) HW_I2C_SLTL_ADDR(x))
mbed_official	146:f64d43ff0c18	1831	#define HW_I2C_SLTL_RD(x) (HW_I2C_SLTL(x).U)
mbed_official	146:f64d43ff0c18	1832	#define HW_I2C_SLTL_WR(x, v) (HW_I2C_SLTL(x).U = (v))
mbed_official	146:f64d43ff0c18	1833	#define HW_I2C_SLTL_SET(x, v) (HW_I2C_SLTL_WR(x, HW_I2C_SLTL_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	1834	#define HW_I2C_SLTL_CLR(x, v) (HW_I2C_SLTL_WR(x, HW_I2C_SLTL_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	1835	#define HW_I2C_SLTL_TOG(x, v) (HW_I2C_SLTL_WR(x, HW_I2C_SLTL_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	1836	#endif
mbed_official	146:f64d43ff0c18	1837	//@}
mbed_official	146:f64d43ff0c18	1838
mbed_official	146:f64d43ff0c18	1839	/*
mbed_official	146:f64d43ff0c18	1840	* Constants & macros for individual I2C_SLTL bitfields
mbed_official	146:f64d43ff0c18	1841	*/
mbed_official	146:f64d43ff0c18	1842
mbed_official	146:f64d43ff0c18	1843	/*!
mbed_official	146:f64d43ff0c18	1844	* @name Register I2C_SLTL, field SSLT[7:0] (RW)
mbed_official	146:f64d43ff0c18	1845	*
mbed_official	146:f64d43ff0c18	1846	* Least significant byte of SCL low timeout value that determines the timeout
mbed_official	146:f64d43ff0c18	1847	* period of SCL low.
mbed_official	146:f64d43ff0c18	1848	*/
mbed_official	146:f64d43ff0c18	1849	//@{
mbed_official	146:f64d43ff0c18	1850	#define BP_I2C_SLTL_SSLT (0U) //!< Bit position for I2C_SLTL_SSLT.
mbed_official	146:f64d43ff0c18	1851	#define BM_I2C_SLTL_SSLT (0xFFU) //!< Bit mask for I2C_SLTL_SSLT.
mbed_official	146:f64d43ff0c18	1852	#define BS_I2C_SLTL_SSLT (8U) //!< Bit field size in bits for I2C_SLTL_SSLT.
mbed_official	146:f64d43ff0c18	1853
mbed_official	146:f64d43ff0c18	1854	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1855	//! @brief Read current value of the I2C_SLTL_SSLT field.
mbed_official	146:f64d43ff0c18	1856	#define BR_I2C_SLTL_SSLT(x) (HW_I2C_SLTL(x).U)
mbed_official	146:f64d43ff0c18	1857	#endif
mbed_official	146:f64d43ff0c18	1858
mbed_official	146:f64d43ff0c18	1859	//! @brief Format value for bitfield I2C_SLTL_SSLT.
mbed_official	146:f64d43ff0c18	1860	#define BF_I2C_SLTL_SSLT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SLTL_SSLT), uint8_t) & BM_I2C_SLTL_SSLT)
mbed_official	146:f64d43ff0c18	1861
mbed_official	146:f64d43ff0c18	1862	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1863	//! @brief Set the SSLT field to a new value.
mbed_official	146:f64d43ff0c18	1864	#define BW_I2C_SLTL_SSLT(x, v) (HW_I2C_SLTL_WR(x, v))
mbed_official	146:f64d43ff0c18	1865	#endif
mbed_official	146:f64d43ff0c18	1866	//@}
mbed_official	146:f64d43ff0c18	1867
mbed_official	146:f64d43ff0c18	1868	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1869	// hw_i2c_t - module struct
mbed_official	146:f64d43ff0c18	1870	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1871	/*!
mbed_official	146:f64d43ff0c18	1872	* @brief All I2C module registers.
mbed_official	146:f64d43ff0c18	1873	*/
mbed_official	146:f64d43ff0c18	1874	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1875	#pragma pack(1)
mbed_official	146:f64d43ff0c18	1876	typedef struct _hw_i2c
mbed_official	146:f64d43ff0c18	1877	{
mbed_official	146:f64d43ff0c18	1878	__IO hw_i2c_a1_t A1; //!< [0x0] I2C Address Register 1
mbed_official	146:f64d43ff0c18	1879	__IO hw_i2c_f_t F; //!< [0x1] I2C Frequency Divider register
mbed_official	146:f64d43ff0c18	1880	__IO hw_i2c_c1_t C1; //!< [0x2] I2C Control Register 1
mbed_official	146:f64d43ff0c18	1881	__IO hw_i2c_s_t S; //!< [0x3] I2C Status register
mbed_official	146:f64d43ff0c18	1882	__IO hw_i2c_d_t D; //!< [0x4] I2C Data I/O register
mbed_official	146:f64d43ff0c18	1883	__IO hw_i2c_c2_t C2; //!< [0x5] I2C Control Register 2
mbed_official	146:f64d43ff0c18	1884	__IO hw_i2c_flt_t FLT; //!< [0x6] I2C Programmable Input Glitch Filter register
mbed_official	146:f64d43ff0c18	1885	__IO hw_i2c_ra_t RA; //!< [0x7] I2C Range Address register
mbed_official	146:f64d43ff0c18	1886	__IO hw_i2c_smb_t SMB; //!< [0x8] I2C SMBus Control and Status register
mbed_official	146:f64d43ff0c18	1887	__IO hw_i2c_a2_t A2; //!< [0x9] I2C Address Register 2
mbed_official	146:f64d43ff0c18	1888	__IO hw_i2c_slth_t SLTH; //!< [0xA] I2C SCL Low Timeout Register High
mbed_official	146:f64d43ff0c18	1889	__IO hw_i2c_sltl_t SLTL; //!< [0xB] I2C SCL Low Timeout Register Low
mbed_official	146:f64d43ff0c18	1890	} hw_i2c_t;
mbed_official	146:f64d43ff0c18	1891	#pragma pack()
mbed_official	146:f64d43ff0c18	1892
mbed_official	146:f64d43ff0c18	1893	//! @brief Macro to access all I2C registers.
mbed_official	146:f64d43ff0c18	1894	//! @param x I2C instance number.
mbed_official	146:f64d43ff0c18	1895	//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official	146:f64d43ff0c18	1896	//! use the '&' operator, like <code>&HW_I2C(0)</code>.
mbed_official	146:f64d43ff0c18	1897	#define HW_I2C(x) ((hw_i2c_t ) REGS_I2C_BASE(x))
mbed_official	146:f64d43ff0c18	1898	#endif
mbed_official	146:f64d43ff0c18	1899
mbed_official	146:f64d43ff0c18	1900	#endif // __HW_I2C_REGISTERS_H__
mbed_official	146:f64d43ff0c18	1901	// v22/130726/0.9
mbed_official	146:f64d43ff0c18	1902	// EOF