mbed-src - mbed library sources

Users » mbed_official » Code » mbed-src

mbed library sources

Dependents: Encrypted my_mbed lklk CyaSSL_DTLS_Cellular ... more

Superseded

This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

Import library mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_ftm.h@149:1fb5f62b92bd, 2014-04-03 (annotated)

Committer:: mbed_official
Date:: Thu Apr 03 11:45:06 2014 +0100
Revision:: 149:1fb5f62b92bd
Parent:: targets/hal/TARGET_Freescale/TARGET_KSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_ftm.h@146:f64d43ff0c18

Synchronized with git revision 220c0bb39ceee40016e1e86350c058963d01ed42



Full URL: https://github.com/mbedmicro/mbed/commit/220c0bb39ceee40016e1e86350c058963d01ed42/

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	146:f64d43ff0c18	1	/*
mbed_official	146:f64d43ff0c18	2	* Copyright (c) 2014, Freescale Semiconductor, Inc.
mbed_official	146:f64d43ff0c18	3	* All rights reserved.
mbed_official	146:f64d43ff0c18	4	*
mbed_official	146:f64d43ff0c18	5	* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official	146:f64d43ff0c18	6	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official	146:f64d43ff0c18	7	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
mbed_official	146:f64d43ff0c18	8	* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
mbed_official	146:f64d43ff0c18	9	* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
mbed_official	146:f64d43ff0c18	10	* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official	146:f64d43ff0c18	11	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official	146:f64d43ff0c18	12	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
mbed_official	146:f64d43ff0c18	13	* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
mbed_official	146:f64d43ff0c18	14	* OF SUCH DAMAGE.
mbed_official	146:f64d43ff0c18	15	*/
mbed_official	146:f64d43ff0c18	16	/*
mbed_official	146:f64d43ff0c18	17	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official	146:f64d43ff0c18	18	*
mbed_official	146:f64d43ff0c18	19	* This file was generated automatically and any changes may be lost.
mbed_official	146:f64d43ff0c18	20	*/
mbed_official	146:f64d43ff0c18	21	#ifndef __HW_FTM_REGISTERS_H__
mbed_official	146:f64d43ff0c18	22	#define __HW_FTM_REGISTERS_H__
mbed_official	146:f64d43ff0c18	23
mbed_official	146:f64d43ff0c18	24	#include "regs.h"
mbed_official	146:f64d43ff0c18	25
mbed_official	146:f64d43ff0c18	26	/*
mbed_official	146:f64d43ff0c18	27	* MK64F12 FTM
mbed_official	146:f64d43ff0c18	28	*
mbed_official	146:f64d43ff0c18	29	* FlexTimer Module
mbed_official	146:f64d43ff0c18	30	*
mbed_official	146:f64d43ff0c18	31	* Registers defined in this header file:
mbed_official	146:f64d43ff0c18	32	* - HW_FTM_SC - Status And Control
mbed_official	146:f64d43ff0c18	33	* - HW_FTM_CNT - Counter
mbed_official	146:f64d43ff0c18	34	* - HW_FTM_MOD - Modulo
mbed_official	146:f64d43ff0c18	35	* - HW_FTM_CnSC - Channel (n) Status And Control
mbed_official	146:f64d43ff0c18	36	* - HW_FTM_CnV - Channel (n) Value
mbed_official	146:f64d43ff0c18	37	* - HW_FTM_CNTIN - Counter Initial Value
mbed_official	146:f64d43ff0c18	38	* - HW_FTM_STATUS - Capture And Compare Status
mbed_official	146:f64d43ff0c18	39	* - HW_FTM_MODE - Features Mode Selection
mbed_official	146:f64d43ff0c18	40	* - HW_FTM_SYNC - Synchronization
mbed_official	146:f64d43ff0c18	41	* - HW_FTM_OUTINIT - Initial State For Channels Output
mbed_official	146:f64d43ff0c18	42	* - HW_FTM_OUTMASK - Output Mask
mbed_official	146:f64d43ff0c18	43	* - HW_FTM_COMBINE - Function For Linked Channels
mbed_official	146:f64d43ff0c18	44	* - HW_FTM_DEADTIME - Deadtime Insertion Control
mbed_official	146:f64d43ff0c18	45	* - HW_FTM_EXTTRIG - FTM External Trigger
mbed_official	146:f64d43ff0c18	46	* - HW_FTM_POL - Channels Polarity
mbed_official	146:f64d43ff0c18	47	* - HW_FTM_FMS - Fault Mode Status
mbed_official	146:f64d43ff0c18	48	* - HW_FTM_FILTER - Input Capture Filter Control
mbed_official	146:f64d43ff0c18	49	* - HW_FTM_FLTCTRL - Fault Control
mbed_official	146:f64d43ff0c18	50	* - HW_FTM_QDCTRL - Quadrature Decoder Control And Status
mbed_official	146:f64d43ff0c18	51	* - HW_FTM_CONF - Configuration
mbed_official	146:f64d43ff0c18	52	* - HW_FTM_FLTPOL - FTM Fault Input Polarity
mbed_official	146:f64d43ff0c18	53	* - HW_FTM_SYNCONF - Synchronization Configuration
mbed_official	146:f64d43ff0c18	54	* - HW_FTM_INVCTRL - FTM Inverting Control
mbed_official	146:f64d43ff0c18	55	* - HW_FTM_SWOCTRL - FTM Software Output Control
mbed_official	146:f64d43ff0c18	56	* - HW_FTM_PWMLOAD - FTM PWM Load
mbed_official	146:f64d43ff0c18	57	*
mbed_official	146:f64d43ff0c18	58	* - hw_ftm_t - Struct containing all module registers.
mbed_official	146:f64d43ff0c18	59	*/
mbed_official	146:f64d43ff0c18	60
mbed_official	146:f64d43ff0c18	61	//! @name Module base addresses
mbed_official	146:f64d43ff0c18	62	//@{
mbed_official	146:f64d43ff0c18	63	#ifndef REGS_FTM_BASE
mbed_official	146:f64d43ff0c18	64	#define HW_FTM_INSTANCE_COUNT (4U) //!< Number of instances of the FTM module.
mbed_official	146:f64d43ff0c18	65	#define HW_FTM0 (0U) //!< Instance number for FTM0.
mbed_official	146:f64d43ff0c18	66	#define HW_FTM1 (1U) //!< Instance number for FTM1.
mbed_official	146:f64d43ff0c18	67	#define HW_FTM2 (2U) //!< Instance number for FTM2.
mbed_official	146:f64d43ff0c18	68	#define HW_FTM3 (3U) //!< Instance number for FTM3.
mbed_official	146:f64d43ff0c18	69	#define REGS_FTM0_BASE (0x40038000U) //!< Base address for FTM0.
mbed_official	146:f64d43ff0c18	70	#define REGS_FTM1_BASE (0x40039000U) //!< Base address for FTM1.
mbed_official	146:f64d43ff0c18	71	#define REGS_FTM2_BASE (0x4003A000U) //!< Base address for FTM2.
mbed_official	146:f64d43ff0c18	72	#define REGS_FTM3_BASE (0x400B9000U) //!< Base address for FTM3.
mbed_official	146:f64d43ff0c18	73
mbed_official	146:f64d43ff0c18	74	//! @brief Table of base addresses for FTM instances.
mbed_official	146:f64d43ff0c18	75	static const uint32_t __g_regs_FTM_base_addresses[] = {
mbed_official	146:f64d43ff0c18	76	REGS_FTM0_BASE,
mbed_official	146:f64d43ff0c18	77	REGS_FTM1_BASE,
mbed_official	146:f64d43ff0c18	78	REGS_FTM2_BASE,
mbed_official	146:f64d43ff0c18	79	REGS_FTM3_BASE,
mbed_official	146:f64d43ff0c18	80	};
mbed_official	146:f64d43ff0c18	81
mbed_official	146:f64d43ff0c18	82	//! @brief Get the base address of FTM by instance number.
mbed_official	146:f64d43ff0c18	83	//! @param x FTM instance number, from 0 through 3.
mbed_official	146:f64d43ff0c18	84	#define REGS_FTM_BASE(x) (__g_regs_FTM_base_addresses[(x)])
mbed_official	146:f64d43ff0c18	85
mbed_official	146:f64d43ff0c18	86	//! @brief Get the instance number given a base address.
mbed_official	146:f64d43ff0c18	87	//! @param b Base address for an instance of FTM.
mbed_official	146:f64d43ff0c18	88	#define REGS_FTM_INSTANCE(b) ((b) == REGS_FTM0_BASE ? HW_FTM0 : (b) == REGS_FTM1_BASE ? HW_FTM1 : (b) == REGS_FTM2_BASE ? HW_FTM2 : (b) == REGS_FTM3_BASE ? HW_FTM3 : 0)
mbed_official	146:f64d43ff0c18	89	#endif
mbed_official	146:f64d43ff0c18	90	//@}
mbed_official	146:f64d43ff0c18	91
mbed_official	146:f64d43ff0c18	92	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	93	// HW_FTM_SC - Status And Control
mbed_official	146:f64d43ff0c18	94	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	95
mbed_official	146:f64d43ff0c18	96	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	97	/*!
mbed_official	146:f64d43ff0c18	98	* @brief HW_FTM_SC - Status And Control (RW)
mbed_official	146:f64d43ff0c18	99	*
mbed_official	146:f64d43ff0c18	100	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	101	*
mbed_official	146:f64d43ff0c18	102	* SC contains the overflow status flag and control bits used to configure the
mbed_official	146:f64d43ff0c18	103	* interrupt enable, FTM configuration, clock source, and prescaler factor. These
mbed_official	146:f64d43ff0c18	104	* controls relate to all channels within this module.
mbed_official	146:f64d43ff0c18	105	*/
mbed_official	146:f64d43ff0c18	106	typedef union _hw_ftm_sc
mbed_official	146:f64d43ff0c18	107	{
mbed_official	146:f64d43ff0c18	108	uint32_t U;
mbed_official	146:f64d43ff0c18	109	struct _hw_ftm_sc_bitfields
mbed_official	146:f64d43ff0c18	110	{
mbed_official	146:f64d43ff0c18	111	uint32_t PS : 3; //!< [2:0] Prescale Factor Selection
mbed_official	146:f64d43ff0c18	112	uint32_t CLKS : 2; //!< [4:3] Clock Source Selection
mbed_official	146:f64d43ff0c18	113	uint32_t CPWMS : 1; //!< [5] Center-Aligned PWM Select
mbed_official	146:f64d43ff0c18	114	uint32_t TOIE : 1; //!< [6] Timer Overflow Interrupt Enable
mbed_official	146:f64d43ff0c18	115	uint32_t TOF : 1; //!< [7] Timer Overflow Flag
mbed_official	146:f64d43ff0c18	116	uint32_t RESERVED0 : 24; //!< [31:8]
mbed_official	146:f64d43ff0c18	117	} B;
mbed_official	146:f64d43ff0c18	118	} hw_ftm_sc_t;
mbed_official	146:f64d43ff0c18	119	#endif
mbed_official	146:f64d43ff0c18	120
mbed_official	146:f64d43ff0c18	121	/*!
mbed_official	146:f64d43ff0c18	122	* @name Constants and macros for entire FTM_SC register
mbed_official	146:f64d43ff0c18	123	*/
mbed_official	146:f64d43ff0c18	124	//@{
mbed_official	146:f64d43ff0c18	125	#define HW_FTM_SC_ADDR(x) (REGS_FTM_BASE(x) + 0x0U)
mbed_official	146:f64d43ff0c18	126
mbed_official	146:f64d43ff0c18	127	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	128	#define HW_FTM_SC(x) ((__IO hw_ftm_sc_t ) HW_FTM_SC_ADDR(x))
mbed_official	146:f64d43ff0c18	129	#define HW_FTM_SC_RD(x) (HW_FTM_SC(x).U)
mbed_official	146:f64d43ff0c18	130	#define HW_FTM_SC_WR(x, v) (HW_FTM_SC(x).U = (v))
mbed_official	146:f64d43ff0c18	131	#define HW_FTM_SC_SET(x, v) (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	132	#define HW_FTM_SC_CLR(x, v) (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	133	#define HW_FTM_SC_TOG(x, v) (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	134	#endif
mbed_official	146:f64d43ff0c18	135	//@}
mbed_official	146:f64d43ff0c18	136
mbed_official	146:f64d43ff0c18	137	/*
mbed_official	146:f64d43ff0c18	138	* Constants & macros for individual FTM_SC bitfields
mbed_official	146:f64d43ff0c18	139	*/
mbed_official	146:f64d43ff0c18	140
mbed_official	146:f64d43ff0c18	141	/*!
mbed_official	146:f64d43ff0c18	142	* @name Register FTM_SC, field PS[2:0] (RW)
mbed_official	146:f64d43ff0c18	143	*
mbed_official	146:f64d43ff0c18	144	* Selects one of 8 division factors for the clock source selected by CLKS. The
mbed_official	146:f64d43ff0c18	145	* new prescaler factor affects the clock source on the next system clock cycle
mbed_official	146:f64d43ff0c18	146	* after the new value is updated into the register bits. This field is write
mbed_official	146:f64d43ff0c18	147	* protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	148	*
mbed_official	146:f64d43ff0c18	149	* Values:
mbed_official	146:f64d43ff0c18	150	* - 000 - Divide by 1
mbed_official	146:f64d43ff0c18	151	* - 001 - Divide by 2
mbed_official	146:f64d43ff0c18	152	* - 010 - Divide by 4
mbed_official	146:f64d43ff0c18	153	* - 011 - Divide by 8
mbed_official	146:f64d43ff0c18	154	* - 100 - Divide by 16
mbed_official	146:f64d43ff0c18	155	* - 101 - Divide by 32
mbed_official	146:f64d43ff0c18	156	* - 110 - Divide by 64
mbed_official	146:f64d43ff0c18	157	* - 111 - Divide by 128
mbed_official	146:f64d43ff0c18	158	*/
mbed_official	146:f64d43ff0c18	159	//@{
mbed_official	146:f64d43ff0c18	160	#define BP_FTM_SC_PS (0U) //!< Bit position for FTM_SC_PS.
mbed_official	146:f64d43ff0c18	161	#define BM_FTM_SC_PS (0x00000007U) //!< Bit mask for FTM_SC_PS.
mbed_official	146:f64d43ff0c18	162	#define BS_FTM_SC_PS (3U) //!< Bit field size in bits for FTM_SC_PS.
mbed_official	146:f64d43ff0c18	163
mbed_official	146:f64d43ff0c18	164	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	165	//! @brief Read current value of the FTM_SC_PS field.
mbed_official	146:f64d43ff0c18	166	#define BR_FTM_SC_PS(x) (HW_FTM_SC(x).B.PS)
mbed_official	146:f64d43ff0c18	167	#endif
mbed_official	146:f64d43ff0c18	168
mbed_official	146:f64d43ff0c18	169	//! @brief Format value for bitfield FTM_SC_PS.
mbed_official	146:f64d43ff0c18	170	#define BF_FTM_SC_PS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SC_PS), uint32_t) & BM_FTM_SC_PS)
mbed_official	146:f64d43ff0c18	171
mbed_official	146:f64d43ff0c18	172	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	173	//! @brief Set the PS field to a new value.
mbed_official	146:f64d43ff0c18	174	#define BW_FTM_SC_PS(x, v) (HW_FTM_SC_WR(x, (HW_FTM_SC_RD(x) & ~BM_FTM_SC_PS) \| BF_FTM_SC_PS(v)))
mbed_official	146:f64d43ff0c18	175	#endif
mbed_official	146:f64d43ff0c18	176	//@}
mbed_official	146:f64d43ff0c18	177
mbed_official	146:f64d43ff0c18	178	/*!
mbed_official	146:f64d43ff0c18	179	* @name Register FTM_SC, field CLKS[4:3] (RW)
mbed_official	146:f64d43ff0c18	180	*
mbed_official	146:f64d43ff0c18	181	* Selects one of the three FTM counter clock sources. This field is write
mbed_official	146:f64d43ff0c18	182	* protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	183	*
mbed_official	146:f64d43ff0c18	184	* Values:
mbed_official	146:f64d43ff0c18	185	* - 00 - No clock selected. This in effect disables the FTM counter.
mbed_official	146:f64d43ff0c18	186	* - 01 - System clock
mbed_official	146:f64d43ff0c18	187	* - 10 - Fixed frequency clock
mbed_official	146:f64d43ff0c18	188	* - 11 - External clock
mbed_official	146:f64d43ff0c18	189	*/
mbed_official	146:f64d43ff0c18	190	//@{
mbed_official	146:f64d43ff0c18	191	#define BP_FTM_SC_CLKS (3U) //!< Bit position for FTM_SC_CLKS.
mbed_official	146:f64d43ff0c18	192	#define BM_FTM_SC_CLKS (0x00000018U) //!< Bit mask for FTM_SC_CLKS.
mbed_official	146:f64d43ff0c18	193	#define BS_FTM_SC_CLKS (2U) //!< Bit field size in bits for FTM_SC_CLKS.
mbed_official	146:f64d43ff0c18	194
mbed_official	146:f64d43ff0c18	195	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	196	//! @brief Read current value of the FTM_SC_CLKS field.
mbed_official	146:f64d43ff0c18	197	#define BR_FTM_SC_CLKS(x) (HW_FTM_SC(x).B.CLKS)
mbed_official	146:f64d43ff0c18	198	#endif
mbed_official	146:f64d43ff0c18	199
mbed_official	146:f64d43ff0c18	200	//! @brief Format value for bitfield FTM_SC_CLKS.
mbed_official	146:f64d43ff0c18	201	#define BF_FTM_SC_CLKS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SC_CLKS), uint32_t) & BM_FTM_SC_CLKS)
mbed_official	146:f64d43ff0c18	202
mbed_official	146:f64d43ff0c18	203	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	204	//! @brief Set the CLKS field to a new value.
mbed_official	146:f64d43ff0c18	205	#define BW_FTM_SC_CLKS(x, v) (HW_FTM_SC_WR(x, (HW_FTM_SC_RD(x) & ~BM_FTM_SC_CLKS) \| BF_FTM_SC_CLKS(v)))
mbed_official	146:f64d43ff0c18	206	#endif
mbed_official	146:f64d43ff0c18	207	//@}
mbed_official	146:f64d43ff0c18	208
mbed_official	146:f64d43ff0c18	209	/*!
mbed_official	146:f64d43ff0c18	210	* @name Register FTM_SC, field CPWMS[5] (RW)
mbed_official	146:f64d43ff0c18	211	*
mbed_official	146:f64d43ff0c18	212	* Selects CPWM mode. This mode configures the FTM to operate in Up-Down
mbed_official	146:f64d43ff0c18	213	* Counting mode. This field is write protected. It can be written only when MODE[WPDIS]
mbed_official	146:f64d43ff0c18	214	* = 1.
mbed_official	146:f64d43ff0c18	215	*
mbed_official	146:f64d43ff0c18	216	* Values:
mbed_official	146:f64d43ff0c18	217	* - 0 - FTM counter operates in Up Counting mode.
mbed_official	146:f64d43ff0c18	218	* - 1 - FTM counter operates in Up-Down Counting mode.
mbed_official	146:f64d43ff0c18	219	*/
mbed_official	146:f64d43ff0c18	220	//@{
mbed_official	146:f64d43ff0c18	221	#define BP_FTM_SC_CPWMS (5U) //!< Bit position for FTM_SC_CPWMS.
mbed_official	146:f64d43ff0c18	222	#define BM_FTM_SC_CPWMS (0x00000020U) //!< Bit mask for FTM_SC_CPWMS.
mbed_official	146:f64d43ff0c18	223	#define BS_FTM_SC_CPWMS (1U) //!< Bit field size in bits for FTM_SC_CPWMS.
mbed_official	146:f64d43ff0c18	224
mbed_official	146:f64d43ff0c18	225	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	226	//! @brief Read current value of the FTM_SC_CPWMS field.
mbed_official	146:f64d43ff0c18	227	#define BR_FTM_SC_CPWMS(x) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_CPWMS))
mbed_official	146:f64d43ff0c18	228	#endif
mbed_official	146:f64d43ff0c18	229
mbed_official	146:f64d43ff0c18	230	//! @brief Format value for bitfield FTM_SC_CPWMS.
mbed_official	146:f64d43ff0c18	231	#define BF_FTM_SC_CPWMS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SC_CPWMS), uint32_t) & BM_FTM_SC_CPWMS)
mbed_official	146:f64d43ff0c18	232
mbed_official	146:f64d43ff0c18	233	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	234	//! @brief Set the CPWMS field to a new value.
mbed_official	146:f64d43ff0c18	235	#define BW_FTM_SC_CPWMS(x, v) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_CPWMS) = (v))
mbed_official	146:f64d43ff0c18	236	#endif
mbed_official	146:f64d43ff0c18	237	//@}
mbed_official	146:f64d43ff0c18	238
mbed_official	146:f64d43ff0c18	239	/*!
mbed_official	146:f64d43ff0c18	240	* @name Register FTM_SC, field TOIE[6] (RW)
mbed_official	146:f64d43ff0c18	241	*
mbed_official	146:f64d43ff0c18	242	* Enables FTM overflow interrupts.
mbed_official	146:f64d43ff0c18	243	*
mbed_official	146:f64d43ff0c18	244	* Values:
mbed_official	146:f64d43ff0c18	245	* - 0 - Disable TOF interrupts. Use software polling.
mbed_official	146:f64d43ff0c18	246	* - 1 - Enable TOF interrupts. An interrupt is generated when TOF equals one.
mbed_official	146:f64d43ff0c18	247	*/
mbed_official	146:f64d43ff0c18	248	//@{
mbed_official	146:f64d43ff0c18	249	#define BP_FTM_SC_TOIE (6U) //!< Bit position for FTM_SC_TOIE.
mbed_official	146:f64d43ff0c18	250	#define BM_FTM_SC_TOIE (0x00000040U) //!< Bit mask for FTM_SC_TOIE.
mbed_official	146:f64d43ff0c18	251	#define BS_FTM_SC_TOIE (1U) //!< Bit field size in bits for FTM_SC_TOIE.
mbed_official	146:f64d43ff0c18	252
mbed_official	146:f64d43ff0c18	253	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	254	//! @brief Read current value of the FTM_SC_TOIE field.
mbed_official	146:f64d43ff0c18	255	#define BR_FTM_SC_TOIE(x) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOIE))
mbed_official	146:f64d43ff0c18	256	#endif
mbed_official	146:f64d43ff0c18	257
mbed_official	146:f64d43ff0c18	258	//! @brief Format value for bitfield FTM_SC_TOIE.
mbed_official	146:f64d43ff0c18	259	#define BF_FTM_SC_TOIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SC_TOIE), uint32_t) & BM_FTM_SC_TOIE)
mbed_official	146:f64d43ff0c18	260
mbed_official	146:f64d43ff0c18	261	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	262	//! @brief Set the TOIE field to a new value.
mbed_official	146:f64d43ff0c18	263	#define BW_FTM_SC_TOIE(x, v) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOIE) = (v))
mbed_official	146:f64d43ff0c18	264	#endif
mbed_official	146:f64d43ff0c18	265	//@}
mbed_official	146:f64d43ff0c18	266
mbed_official	146:f64d43ff0c18	267	/*!
mbed_official	146:f64d43ff0c18	268	* @name Register FTM_SC, field TOF[7] (ROWZ)
mbed_official	146:f64d43ff0c18	269	*
mbed_official	146:f64d43ff0c18	270	* Set by hardware when the FTM counter passes the value in the MOD register.
mbed_official	146:f64d43ff0c18	271	* The TOF bit is cleared by reading the SC register while TOF is set and then
mbed_official	146:f64d43ff0c18	272	* writing a 0 to TOF bit. Writing a 1 to TOF has no effect. If another FTM overflow
mbed_official	146:f64d43ff0c18	273	* occurs between the read and write operations, the write operation has no
mbed_official	146:f64d43ff0c18	274	* effect; therefore, TOF remains set indicating an overflow has occurred. In this
mbed_official	146:f64d43ff0c18	275	* case, a TOF interrupt request is not lost due to the clearing sequence for a
mbed_official	146:f64d43ff0c18	276	* previous TOF.
mbed_official	146:f64d43ff0c18	277	*
mbed_official	146:f64d43ff0c18	278	* Values:
mbed_official	146:f64d43ff0c18	279	* - 0 - FTM counter has not overflowed.
mbed_official	146:f64d43ff0c18	280	* - 1 - FTM counter has overflowed.
mbed_official	146:f64d43ff0c18	281	*/
mbed_official	146:f64d43ff0c18	282	//@{
mbed_official	146:f64d43ff0c18	283	#define BP_FTM_SC_TOF (7U) //!< Bit position for FTM_SC_TOF.
mbed_official	146:f64d43ff0c18	284	#define BM_FTM_SC_TOF (0x00000080U) //!< Bit mask for FTM_SC_TOF.
mbed_official	146:f64d43ff0c18	285	#define BS_FTM_SC_TOF (1U) //!< Bit field size in bits for FTM_SC_TOF.
mbed_official	146:f64d43ff0c18	286
mbed_official	146:f64d43ff0c18	287	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	288	//! @brief Read current value of the FTM_SC_TOF field.
mbed_official	146:f64d43ff0c18	289	#define BR_FTM_SC_TOF(x) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOF))
mbed_official	146:f64d43ff0c18	290	#endif
mbed_official	146:f64d43ff0c18	291	//@}
mbed_official	146:f64d43ff0c18	292
mbed_official	146:f64d43ff0c18	293	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	294	// HW_FTM_CNT - Counter
mbed_official	146:f64d43ff0c18	295	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	296
mbed_official	146:f64d43ff0c18	297	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	298	/*!
mbed_official	146:f64d43ff0c18	299	* @brief HW_FTM_CNT - Counter (RW)
mbed_official	146:f64d43ff0c18	300	*
mbed_official	146:f64d43ff0c18	301	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	302	*
mbed_official	146:f64d43ff0c18	303	* The CNT register contains the FTM counter value. Reset clears the CNT
mbed_official	146:f64d43ff0c18	304	* register. Writing any value to COUNT updates the counter with its initial value,
mbed_official	146:f64d43ff0c18	305	* CNTIN. When BDM is active, the FTM counter is frozen. This is the value that you
mbed_official	146:f64d43ff0c18	306	* may read.
mbed_official	146:f64d43ff0c18	307	*/
mbed_official	146:f64d43ff0c18	308	typedef union _hw_ftm_cnt
mbed_official	146:f64d43ff0c18	309	{
mbed_official	146:f64d43ff0c18	310	uint32_t U;
mbed_official	146:f64d43ff0c18	311	struct _hw_ftm_cnt_bitfields
mbed_official	146:f64d43ff0c18	312	{
mbed_official	146:f64d43ff0c18	313	uint32_t COUNT : 16; //!< [15:0] Counter Value
mbed_official	146:f64d43ff0c18	314	uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official	146:f64d43ff0c18	315	} B;
mbed_official	146:f64d43ff0c18	316	} hw_ftm_cnt_t;
mbed_official	146:f64d43ff0c18	317	#endif
mbed_official	146:f64d43ff0c18	318
mbed_official	146:f64d43ff0c18	319	/*!
mbed_official	146:f64d43ff0c18	320	* @name Constants and macros for entire FTM_CNT register
mbed_official	146:f64d43ff0c18	321	*/
mbed_official	146:f64d43ff0c18	322	//@{
mbed_official	146:f64d43ff0c18	323	#define HW_FTM_CNT_ADDR(x) (REGS_FTM_BASE(x) + 0x4U)
mbed_official	146:f64d43ff0c18	324
mbed_official	146:f64d43ff0c18	325	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	326	#define HW_FTM_CNT(x) ((__IO hw_ftm_cnt_t ) HW_FTM_CNT_ADDR(x))
mbed_official	146:f64d43ff0c18	327	#define HW_FTM_CNT_RD(x) (HW_FTM_CNT(x).U)
mbed_official	146:f64d43ff0c18	328	#define HW_FTM_CNT_WR(x, v) (HW_FTM_CNT(x).U = (v))
mbed_official	146:f64d43ff0c18	329	#define HW_FTM_CNT_SET(x, v) (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	330	#define HW_FTM_CNT_CLR(x, v) (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	331	#define HW_FTM_CNT_TOG(x, v) (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	332	#endif
mbed_official	146:f64d43ff0c18	333	//@}
mbed_official	146:f64d43ff0c18	334
mbed_official	146:f64d43ff0c18	335	/*
mbed_official	146:f64d43ff0c18	336	* Constants & macros for individual FTM_CNT bitfields
mbed_official	146:f64d43ff0c18	337	*/
mbed_official	146:f64d43ff0c18	338
mbed_official	146:f64d43ff0c18	339	/*!
mbed_official	146:f64d43ff0c18	340	* @name Register FTM_CNT, field COUNT[15:0] (RW)
mbed_official	146:f64d43ff0c18	341	*/
mbed_official	146:f64d43ff0c18	342	//@{
mbed_official	146:f64d43ff0c18	343	#define BP_FTM_CNT_COUNT (0U) //!< Bit position for FTM_CNT_COUNT.
mbed_official	146:f64d43ff0c18	344	#define BM_FTM_CNT_COUNT (0x0000FFFFU) //!< Bit mask for FTM_CNT_COUNT.
mbed_official	146:f64d43ff0c18	345	#define BS_FTM_CNT_COUNT (16U) //!< Bit field size in bits for FTM_CNT_COUNT.
mbed_official	146:f64d43ff0c18	346
mbed_official	146:f64d43ff0c18	347	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	348	//! @brief Read current value of the FTM_CNT_COUNT field.
mbed_official	146:f64d43ff0c18	349	#define BR_FTM_CNT_COUNT(x) (HW_FTM_CNT(x).B.COUNT)
mbed_official	146:f64d43ff0c18	350	#endif
mbed_official	146:f64d43ff0c18	351
mbed_official	146:f64d43ff0c18	352	//! @brief Format value for bitfield FTM_CNT_COUNT.
mbed_official	146:f64d43ff0c18	353	#define BF_FTM_CNT_COUNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CNT_COUNT), uint32_t) & BM_FTM_CNT_COUNT)
mbed_official	146:f64d43ff0c18	354
mbed_official	146:f64d43ff0c18	355	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	356	//! @brief Set the COUNT field to a new value.
mbed_official	146:f64d43ff0c18	357	#define BW_FTM_CNT_COUNT(x, v) (HW_FTM_CNT_WR(x, (HW_FTM_CNT_RD(x) & ~BM_FTM_CNT_COUNT) \| BF_FTM_CNT_COUNT(v)))
mbed_official	146:f64d43ff0c18	358	#endif
mbed_official	146:f64d43ff0c18	359	//@}
mbed_official	146:f64d43ff0c18	360
mbed_official	146:f64d43ff0c18	361	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	362	// HW_FTM_MOD - Modulo
mbed_official	146:f64d43ff0c18	363	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	364
mbed_official	146:f64d43ff0c18	365	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	366	/*!
mbed_official	146:f64d43ff0c18	367	* @brief HW_FTM_MOD - Modulo (RW)
mbed_official	146:f64d43ff0c18	368	*
mbed_official	146:f64d43ff0c18	369	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	370	*
mbed_official	146:f64d43ff0c18	371	* The Modulo register contains the modulo value for the FTM counter. After the
mbed_official	146:f64d43ff0c18	372	* FTM counter reaches the modulo value, the overflow flag (TOF) becomes set at
mbed_official	146:f64d43ff0c18	373	* the next clock, and the next value of FTM counter depends on the selected
mbed_official	146:f64d43ff0c18	374	* counting method; see Counter. Writing to the MOD register latches the value into a
mbed_official	146:f64d43ff0c18	375	* buffer. The MOD register is updated with the value of its write buffer
mbed_official	146:f64d43ff0c18	376	* according to Registers updated from write buffers. If FTMEN = 0, this write coherency
mbed_official	146:f64d43ff0c18	377	* mechanism may be manually reset by writing to the SC register whether BDM is
mbed_official	146:f64d43ff0c18	378	* active or not. Initialize the FTM counter, by writing to CNT, before writing
mbed_official	146:f64d43ff0c18	379	* to the MOD register to avoid confusion about when the first counter overflow
mbed_official	146:f64d43ff0c18	380	* will occur.
mbed_official	146:f64d43ff0c18	381	*/
mbed_official	146:f64d43ff0c18	382	typedef union _hw_ftm_mod
mbed_official	146:f64d43ff0c18	383	{
mbed_official	146:f64d43ff0c18	384	uint32_t U;
mbed_official	146:f64d43ff0c18	385	struct _hw_ftm_mod_bitfields
mbed_official	146:f64d43ff0c18	386	{
mbed_official	146:f64d43ff0c18	387	uint32_t MOD : 16; //!< [15:0]
mbed_official	146:f64d43ff0c18	388	uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official	146:f64d43ff0c18	389	} B;
mbed_official	146:f64d43ff0c18	390	} hw_ftm_mod_t;
mbed_official	146:f64d43ff0c18	391	#endif
mbed_official	146:f64d43ff0c18	392
mbed_official	146:f64d43ff0c18	393	/*!
mbed_official	146:f64d43ff0c18	394	* @name Constants and macros for entire FTM_MOD register
mbed_official	146:f64d43ff0c18	395	*/
mbed_official	146:f64d43ff0c18	396	//@{
mbed_official	146:f64d43ff0c18	397	#define HW_FTM_MOD_ADDR(x) (REGS_FTM_BASE(x) + 0x8U)
mbed_official	146:f64d43ff0c18	398
mbed_official	146:f64d43ff0c18	399	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	400	#define HW_FTM_MOD(x) ((__IO hw_ftm_mod_t ) HW_FTM_MOD_ADDR(x))
mbed_official	146:f64d43ff0c18	401	#define HW_FTM_MOD_RD(x) (HW_FTM_MOD(x).U)
mbed_official	146:f64d43ff0c18	402	#define HW_FTM_MOD_WR(x, v) (HW_FTM_MOD(x).U = (v))
mbed_official	146:f64d43ff0c18	403	#define HW_FTM_MOD_SET(x, v) (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	404	#define HW_FTM_MOD_CLR(x, v) (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	405	#define HW_FTM_MOD_TOG(x, v) (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	406	#endif
mbed_official	146:f64d43ff0c18	407	//@}
mbed_official	146:f64d43ff0c18	408
mbed_official	146:f64d43ff0c18	409	/*
mbed_official	146:f64d43ff0c18	410	* Constants & macros for individual FTM_MOD bitfields
mbed_official	146:f64d43ff0c18	411	*/
mbed_official	146:f64d43ff0c18	412
mbed_official	146:f64d43ff0c18	413	/*!
mbed_official	146:f64d43ff0c18	414	* @name Register FTM_MOD, field MOD[15:0] (RW)
mbed_official	146:f64d43ff0c18	415	*
mbed_official	146:f64d43ff0c18	416	* Modulo Value
mbed_official	146:f64d43ff0c18	417	*/
mbed_official	146:f64d43ff0c18	418	//@{
mbed_official	146:f64d43ff0c18	419	#define BP_FTM_MOD_MOD (0U) //!< Bit position for FTM_MOD_MOD.
mbed_official	146:f64d43ff0c18	420	#define BM_FTM_MOD_MOD (0x0000FFFFU) //!< Bit mask for FTM_MOD_MOD.
mbed_official	146:f64d43ff0c18	421	#define BS_FTM_MOD_MOD (16U) //!< Bit field size in bits for FTM_MOD_MOD.
mbed_official	146:f64d43ff0c18	422
mbed_official	146:f64d43ff0c18	423	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	424	//! @brief Read current value of the FTM_MOD_MOD field.
mbed_official	146:f64d43ff0c18	425	#define BR_FTM_MOD_MOD(x) (HW_FTM_MOD(x).B.MOD)
mbed_official	146:f64d43ff0c18	426	#endif
mbed_official	146:f64d43ff0c18	427
mbed_official	146:f64d43ff0c18	428	//! @brief Format value for bitfield FTM_MOD_MOD.
mbed_official	146:f64d43ff0c18	429	#define BF_FTM_MOD_MOD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MOD_MOD), uint32_t) & BM_FTM_MOD_MOD)
mbed_official	146:f64d43ff0c18	430
mbed_official	146:f64d43ff0c18	431	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	432	//! @brief Set the MOD field to a new value.
mbed_official	146:f64d43ff0c18	433	#define BW_FTM_MOD_MOD(x, v) (HW_FTM_MOD_WR(x, (HW_FTM_MOD_RD(x) & ~BM_FTM_MOD_MOD) \| BF_FTM_MOD_MOD(v)))
mbed_official	146:f64d43ff0c18	434	#endif
mbed_official	146:f64d43ff0c18	435	//@}
mbed_official	146:f64d43ff0c18	436
mbed_official	146:f64d43ff0c18	437	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	438	// HW_FTM_CnSC - Channel (n) Status And Control
mbed_official	146:f64d43ff0c18	439	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	440
mbed_official	146:f64d43ff0c18	441	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	442	/*!
mbed_official	146:f64d43ff0c18	443	* @brief HW_FTM_CnSC - Channel (n) Status And Control (RW)
mbed_official	146:f64d43ff0c18	444	*
mbed_official	146:f64d43ff0c18	445	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	446	*
mbed_official	146:f64d43ff0c18	447	* CnSC contains the channel-interrupt-status flag and control bits used to
mbed_official	146:f64d43ff0c18	448	* configure the interrupt enable, channel configuration, and pin function. Mode,
mbed_official	146:f64d43ff0c18	449	* edge, and level selection DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA Mode
mbed_official	146:f64d43ff0c18	450	* Configuration X X X XX 0 Pin not used for FTM-revert the channel pin to general
mbed_official	146:f64d43ff0c18	451	* purpose I/O or other peripheral control 0 0 0 0 1 Input Capture Capture on Rising
mbed_official	146:f64d43ff0c18	452	* Edge Only 10 Capture on Falling Edge Only 11 Capture on Rising or Falling Edge
mbed_official	146:f64d43ff0c18	453	* 1 1 Output Compare Toggle Output on match 10 Clear Output on match 11 Set
mbed_official	146:f64d43ff0c18	454	* Output on match 1X 10 Edge-Aligned PWM High-true pulses (clear Output on match)
mbed_official	146:f64d43ff0c18	455	* X1 Low-true pulses (set Output on match) 1 XX 10 Center-Aligned PWM High-true
mbed_official	146:f64d43ff0c18	456	* pulses (clear Output on match-up) X1 Low-true pulses (set Output on match-up) 1
mbed_official	146:f64d43ff0c18	457	* 0 XX 10 Combine PWM High-true pulses (set on channel (n) match, and clear on
mbed_official	146:f64d43ff0c18	458	* channel (n+1) match) X1 Low-true pulses (clear on channel (n) match, and set
mbed_official	146:f64d43ff0c18	459	* on channel (n+1) match) 1 0 0 X0 See the following table (#ModeSel2Table). Dual
mbed_official	146:f64d43ff0c18	460	* Edge Capture One-Shot Capture mode X1 Continuous Capture mode Dual Edge
mbed_official	146:f64d43ff0c18	461	* Capture mode - edge polarity selection ELSnB ELSnA Channel Port Enable Detected
mbed_official	146:f64d43ff0c18	462	* Edges 0 0 Disabled No edge 0 1 Enabled Rising edge 1 0 Enabled Falling edge 1 1
mbed_official	146:f64d43ff0c18	463	* Enabled Rising and falling edges
mbed_official	146:f64d43ff0c18	464	*/
mbed_official	146:f64d43ff0c18	465	typedef union _hw_ftm_cnsc
mbed_official	146:f64d43ff0c18	466	{
mbed_official	146:f64d43ff0c18	467	uint32_t U;
mbed_official	146:f64d43ff0c18	468	struct _hw_ftm_cnsc_bitfields
mbed_official	146:f64d43ff0c18	469	{
mbed_official	146:f64d43ff0c18	470	uint32_t DMAb : 1; //!< [0] DMA Enable
mbed_official	146:f64d43ff0c18	471	uint32_t RESERVED0 : 1; //!< [1]
mbed_official	146:f64d43ff0c18	472	uint32_t ELSA : 1; //!< [2] Edge or Level Select
mbed_official	146:f64d43ff0c18	473	uint32_t ELSB : 1; //!< [3] Edge or Level Select
mbed_official	146:f64d43ff0c18	474	uint32_t MSA : 1; //!< [4] Channel Mode Select
mbed_official	146:f64d43ff0c18	475	uint32_t MSB : 1; //!< [5] Channel Mode Select
mbed_official	146:f64d43ff0c18	476	uint32_t CHIE : 1; //!< [6] Channel Interrupt Enable
mbed_official	146:f64d43ff0c18	477	uint32_t CHF : 1; //!< [7] Channel Flag
mbed_official	146:f64d43ff0c18	478	uint32_t RESERVED1 : 24; //!< [31:8]
mbed_official	146:f64d43ff0c18	479	} B;
mbed_official	146:f64d43ff0c18	480	} hw_ftm_cnsc_t;
mbed_official	146:f64d43ff0c18	481	#endif
mbed_official	146:f64d43ff0c18	482
mbed_official	146:f64d43ff0c18	483	/*!
mbed_official	146:f64d43ff0c18	484	* @name Constants and macros for entire FTM_CnSC register
mbed_official	146:f64d43ff0c18	485	*/
mbed_official	146:f64d43ff0c18	486	//@{
mbed_official	146:f64d43ff0c18	487	#define HW_FTM_CnSC_COUNT (8U)
mbed_official	146:f64d43ff0c18	488
mbed_official	146:f64d43ff0c18	489	#define HW_FTM_CnSC_ADDR(x, n) (REGS_FTM_BASE(x) + 0xCU + (0x8U * n))
mbed_official	146:f64d43ff0c18	490
mbed_official	146:f64d43ff0c18	491	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	492	#define HW_FTM_CnSC(x, n) ((__IO hw_ftm_cnsc_t ) HW_FTM_CnSC_ADDR(x, n))
mbed_official	146:f64d43ff0c18	493	#define HW_FTM_CnSC_RD(x, n) (HW_FTM_CnSC(x, n).U)
mbed_official	146:f64d43ff0c18	494	#define HW_FTM_CnSC_WR(x, n, v) (HW_FTM_CnSC(x, n).U = (v))
mbed_official	146:f64d43ff0c18	495	#define HW_FTM_CnSC_SET(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) \| (v)))
mbed_official	146:f64d43ff0c18	496	#define HW_FTM_CnSC_CLR(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) & ~(v)))
mbed_official	146:f64d43ff0c18	497	#define HW_FTM_CnSC_TOG(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) ^ (v)))
mbed_official	146:f64d43ff0c18	498	#endif
mbed_official	146:f64d43ff0c18	499	//@}
mbed_official	146:f64d43ff0c18	500
mbed_official	146:f64d43ff0c18	501	/*
mbed_official	146:f64d43ff0c18	502	* Constants & macros for individual FTM_CnSC bitfields
mbed_official	146:f64d43ff0c18	503	*/
mbed_official	146:f64d43ff0c18	504
mbed_official	146:f64d43ff0c18	505	/*!
mbed_official	146:f64d43ff0c18	506	* @name Register FTM_CnSC, field DMA[0] (RW)
mbed_official	146:f64d43ff0c18	507	*
mbed_official	146:f64d43ff0c18	508	* Enables DMA transfers for the channel.
mbed_official	146:f64d43ff0c18	509	*
mbed_official	146:f64d43ff0c18	510	* Values:
mbed_official	146:f64d43ff0c18	511	* - 0 - Disable DMA transfers.
mbed_official	146:f64d43ff0c18	512	* - 1 - Enable DMA transfers.
mbed_official	146:f64d43ff0c18	513	*/
mbed_official	146:f64d43ff0c18	514	//@{
mbed_official	146:f64d43ff0c18	515	#define BP_FTM_CnSC_DMA (0U) //!< Bit position for FTM_CnSC_DMA.
mbed_official	146:f64d43ff0c18	516	#define BM_FTM_CnSC_DMA (0x00000001U) //!< Bit mask for FTM_CnSC_DMA.
mbed_official	146:f64d43ff0c18	517	#define BS_FTM_CnSC_DMA (1U) //!< Bit field size in bits for FTM_CnSC_DMA.
mbed_official	146:f64d43ff0c18	518
mbed_official	146:f64d43ff0c18	519	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	520	//! @brief Read current value of the FTM_CnSC_DMA field.
mbed_official	146:f64d43ff0c18	521	#define BR_FTM_CnSC_DMA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_DMA))
mbed_official	146:f64d43ff0c18	522	#endif
mbed_official	146:f64d43ff0c18	523
mbed_official	146:f64d43ff0c18	524	//! @brief Format value for bitfield FTM_CnSC_DMA.
mbed_official	146:f64d43ff0c18	525	#define BF_FTM_CnSC_DMA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CnSC_DMA), uint32_t) & BM_FTM_CnSC_DMA)
mbed_official	146:f64d43ff0c18	526
mbed_official	146:f64d43ff0c18	527	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	528	//! @brief Set the DMA field to a new value.
mbed_official	146:f64d43ff0c18	529	#define BW_FTM_CnSC_DMA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_DMA) = (v))
mbed_official	146:f64d43ff0c18	530	#endif
mbed_official	146:f64d43ff0c18	531	//@}
mbed_official	146:f64d43ff0c18	532
mbed_official	146:f64d43ff0c18	533	/*!
mbed_official	146:f64d43ff0c18	534	* @name Register FTM_CnSC, field ELSA[2] (RW)
mbed_official	146:f64d43ff0c18	535	*
mbed_official	146:f64d43ff0c18	536	* The functionality of ELSB and ELSA depends on the channel mode. See
mbed_official	146:f64d43ff0c18	537	* #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS]
mbed_official	146:f64d43ff0c18	538	* = 1.
mbed_official	146:f64d43ff0c18	539	*/
mbed_official	146:f64d43ff0c18	540	//@{
mbed_official	146:f64d43ff0c18	541	#define BP_FTM_CnSC_ELSA (2U) //!< Bit position for FTM_CnSC_ELSA.
mbed_official	146:f64d43ff0c18	542	#define BM_FTM_CnSC_ELSA (0x00000004U) //!< Bit mask for FTM_CnSC_ELSA.
mbed_official	146:f64d43ff0c18	543	#define BS_FTM_CnSC_ELSA (1U) //!< Bit field size in bits for FTM_CnSC_ELSA.
mbed_official	146:f64d43ff0c18	544
mbed_official	146:f64d43ff0c18	545	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	546	//! @brief Read current value of the FTM_CnSC_ELSA field.
mbed_official	146:f64d43ff0c18	547	#define BR_FTM_CnSC_ELSA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSA))
mbed_official	146:f64d43ff0c18	548	#endif
mbed_official	146:f64d43ff0c18	549
mbed_official	146:f64d43ff0c18	550	//! @brief Format value for bitfield FTM_CnSC_ELSA.
mbed_official	146:f64d43ff0c18	551	#define BF_FTM_CnSC_ELSA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CnSC_ELSA), uint32_t) & BM_FTM_CnSC_ELSA)
mbed_official	146:f64d43ff0c18	552
mbed_official	146:f64d43ff0c18	553	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	554	//! @brief Set the ELSA field to a new value.
mbed_official	146:f64d43ff0c18	555	#define BW_FTM_CnSC_ELSA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSA) = (v))
mbed_official	146:f64d43ff0c18	556	#endif
mbed_official	146:f64d43ff0c18	557	//@}
mbed_official	146:f64d43ff0c18	558
mbed_official	146:f64d43ff0c18	559	/*!
mbed_official	146:f64d43ff0c18	560	* @name Register FTM_CnSC, field ELSB[3] (RW)
mbed_official	146:f64d43ff0c18	561	*
mbed_official	146:f64d43ff0c18	562	* The functionality of ELSB and ELSA depends on the channel mode. See
mbed_official	146:f64d43ff0c18	563	* #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS]
mbed_official	146:f64d43ff0c18	564	* = 1.
mbed_official	146:f64d43ff0c18	565	*/
mbed_official	146:f64d43ff0c18	566	//@{
mbed_official	146:f64d43ff0c18	567	#define BP_FTM_CnSC_ELSB (3U) //!< Bit position for FTM_CnSC_ELSB.
mbed_official	146:f64d43ff0c18	568	#define BM_FTM_CnSC_ELSB (0x00000008U) //!< Bit mask for FTM_CnSC_ELSB.
mbed_official	146:f64d43ff0c18	569	#define BS_FTM_CnSC_ELSB (1U) //!< Bit field size in bits for FTM_CnSC_ELSB.
mbed_official	146:f64d43ff0c18	570
mbed_official	146:f64d43ff0c18	571	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	572	//! @brief Read current value of the FTM_CnSC_ELSB field.
mbed_official	146:f64d43ff0c18	573	#define BR_FTM_CnSC_ELSB(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSB))
mbed_official	146:f64d43ff0c18	574	#endif
mbed_official	146:f64d43ff0c18	575
mbed_official	146:f64d43ff0c18	576	//! @brief Format value for bitfield FTM_CnSC_ELSB.
mbed_official	146:f64d43ff0c18	577	#define BF_FTM_CnSC_ELSB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CnSC_ELSB), uint32_t) & BM_FTM_CnSC_ELSB)
mbed_official	146:f64d43ff0c18	578
mbed_official	146:f64d43ff0c18	579	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	580	//! @brief Set the ELSB field to a new value.
mbed_official	146:f64d43ff0c18	581	#define BW_FTM_CnSC_ELSB(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSB) = (v))
mbed_official	146:f64d43ff0c18	582	#endif
mbed_official	146:f64d43ff0c18	583	//@}
mbed_official	146:f64d43ff0c18	584
mbed_official	146:f64d43ff0c18	585	/*!
mbed_official	146:f64d43ff0c18	586	* @name Register FTM_CnSC, field MSA[4] (RW)
mbed_official	146:f64d43ff0c18	587	*
mbed_official	146:f64d43ff0c18	588	* Used for further selections in the channel logic. Its functionality is
mbed_official	146:f64d43ff0c18	589	* dependent on the channel mode. See #ModeSel1Table. This field is write protected. It
mbed_official	146:f64d43ff0c18	590	* can be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	591	*/
mbed_official	146:f64d43ff0c18	592	//@{
mbed_official	146:f64d43ff0c18	593	#define BP_FTM_CnSC_MSA (4U) //!< Bit position for FTM_CnSC_MSA.
mbed_official	146:f64d43ff0c18	594	#define BM_FTM_CnSC_MSA (0x00000010U) //!< Bit mask for FTM_CnSC_MSA.
mbed_official	146:f64d43ff0c18	595	#define BS_FTM_CnSC_MSA (1U) //!< Bit field size in bits for FTM_CnSC_MSA.
mbed_official	146:f64d43ff0c18	596
mbed_official	146:f64d43ff0c18	597	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	598	//! @brief Read current value of the FTM_CnSC_MSA field.
mbed_official	146:f64d43ff0c18	599	#define BR_FTM_CnSC_MSA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSA))
mbed_official	146:f64d43ff0c18	600	#endif
mbed_official	146:f64d43ff0c18	601
mbed_official	146:f64d43ff0c18	602	//! @brief Format value for bitfield FTM_CnSC_MSA.
mbed_official	146:f64d43ff0c18	603	#define BF_FTM_CnSC_MSA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CnSC_MSA), uint32_t) & BM_FTM_CnSC_MSA)
mbed_official	146:f64d43ff0c18	604
mbed_official	146:f64d43ff0c18	605	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	606	//! @brief Set the MSA field to a new value.
mbed_official	146:f64d43ff0c18	607	#define BW_FTM_CnSC_MSA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSA) = (v))
mbed_official	146:f64d43ff0c18	608	#endif
mbed_official	146:f64d43ff0c18	609	//@}
mbed_official	146:f64d43ff0c18	610
mbed_official	146:f64d43ff0c18	611	/*!
mbed_official	146:f64d43ff0c18	612	* @name Register FTM_CnSC, field MSB[5] (RW)
mbed_official	146:f64d43ff0c18	613	*
mbed_official	146:f64d43ff0c18	614	* Used for further selections in the channel logic. Its functionality is
mbed_official	146:f64d43ff0c18	615	* dependent on the channel mode. See #ModeSel1Table. This field is write protected. It
mbed_official	146:f64d43ff0c18	616	* can be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	617	*/
mbed_official	146:f64d43ff0c18	618	//@{
mbed_official	146:f64d43ff0c18	619	#define BP_FTM_CnSC_MSB (5U) //!< Bit position for FTM_CnSC_MSB.
mbed_official	146:f64d43ff0c18	620	#define BM_FTM_CnSC_MSB (0x00000020U) //!< Bit mask for FTM_CnSC_MSB.
mbed_official	146:f64d43ff0c18	621	#define BS_FTM_CnSC_MSB (1U) //!< Bit field size in bits for FTM_CnSC_MSB.
mbed_official	146:f64d43ff0c18	622
mbed_official	146:f64d43ff0c18	623	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	624	//! @brief Read current value of the FTM_CnSC_MSB field.
mbed_official	146:f64d43ff0c18	625	#define BR_FTM_CnSC_MSB(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSB))
mbed_official	146:f64d43ff0c18	626	#endif
mbed_official	146:f64d43ff0c18	627
mbed_official	146:f64d43ff0c18	628	//! @brief Format value for bitfield FTM_CnSC_MSB.
mbed_official	146:f64d43ff0c18	629	#define BF_FTM_CnSC_MSB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CnSC_MSB), uint32_t) & BM_FTM_CnSC_MSB)
mbed_official	146:f64d43ff0c18	630
mbed_official	146:f64d43ff0c18	631	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	632	//! @brief Set the MSB field to a new value.
mbed_official	146:f64d43ff0c18	633	#define BW_FTM_CnSC_MSB(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSB) = (v))
mbed_official	146:f64d43ff0c18	634	#endif
mbed_official	146:f64d43ff0c18	635	//@}
mbed_official	146:f64d43ff0c18	636
mbed_official	146:f64d43ff0c18	637	/*!
mbed_official	146:f64d43ff0c18	638	* @name Register FTM_CnSC, field CHIE[6] (RW)
mbed_official	146:f64d43ff0c18	639	*
mbed_official	146:f64d43ff0c18	640	* Enables channel interrupts.
mbed_official	146:f64d43ff0c18	641	*
mbed_official	146:f64d43ff0c18	642	* Values:
mbed_official	146:f64d43ff0c18	643	* - 0 - Disable channel interrupts. Use software polling.
mbed_official	146:f64d43ff0c18	644	* - 1 - Enable channel interrupts.
mbed_official	146:f64d43ff0c18	645	*/
mbed_official	146:f64d43ff0c18	646	//@{
mbed_official	146:f64d43ff0c18	647	#define BP_FTM_CnSC_CHIE (6U) //!< Bit position for FTM_CnSC_CHIE.
mbed_official	146:f64d43ff0c18	648	#define BM_FTM_CnSC_CHIE (0x00000040U) //!< Bit mask for FTM_CnSC_CHIE.
mbed_official	146:f64d43ff0c18	649	#define BS_FTM_CnSC_CHIE (1U) //!< Bit field size in bits for FTM_CnSC_CHIE.
mbed_official	146:f64d43ff0c18	650
mbed_official	146:f64d43ff0c18	651	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	652	//! @brief Read current value of the FTM_CnSC_CHIE field.
mbed_official	146:f64d43ff0c18	653	#define BR_FTM_CnSC_CHIE(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHIE))
mbed_official	146:f64d43ff0c18	654	#endif
mbed_official	146:f64d43ff0c18	655
mbed_official	146:f64d43ff0c18	656	//! @brief Format value for bitfield FTM_CnSC_CHIE.
mbed_official	146:f64d43ff0c18	657	#define BF_FTM_CnSC_CHIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CnSC_CHIE), uint32_t) & BM_FTM_CnSC_CHIE)
mbed_official	146:f64d43ff0c18	658
mbed_official	146:f64d43ff0c18	659	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	660	//! @brief Set the CHIE field to a new value.
mbed_official	146:f64d43ff0c18	661	#define BW_FTM_CnSC_CHIE(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHIE) = (v))
mbed_official	146:f64d43ff0c18	662	#endif
mbed_official	146:f64d43ff0c18	663	//@}
mbed_official	146:f64d43ff0c18	664
mbed_official	146:f64d43ff0c18	665	/*!
mbed_official	146:f64d43ff0c18	666	* @name Register FTM_CnSC, field CHF[7] (ROWZ)
mbed_official	146:f64d43ff0c18	667	*
mbed_official	146:f64d43ff0c18	668	* Set by hardware when an event occurs on the channel. CHF is cleared by
mbed_official	146:f64d43ff0c18	669	* reading the CSC register while CHnF is set and then writing a 0 to the CHF bit.
mbed_official	146:f64d43ff0c18	670	* Writing a 1 to CHF has no effect. If another event occurs between the read and
mbed_official	146:f64d43ff0c18	671	* write operations, the write operation has no effect; therefore, CHF remains set
mbed_official	146:f64d43ff0c18	672	* indicating an event has occurred. In this case a CHF interrupt request is not
mbed_official	146:f64d43ff0c18	673	* lost due to the clearing sequence for a previous CHF.
mbed_official	146:f64d43ff0c18	674	*
mbed_official	146:f64d43ff0c18	675	* Values:
mbed_official	146:f64d43ff0c18	676	* - 0 - No channel event has occurred.
mbed_official	146:f64d43ff0c18	677	* - 1 - A channel event has occurred.
mbed_official	146:f64d43ff0c18	678	*/
mbed_official	146:f64d43ff0c18	679	//@{
mbed_official	146:f64d43ff0c18	680	#define BP_FTM_CnSC_CHF (7U) //!< Bit position for FTM_CnSC_CHF.
mbed_official	146:f64d43ff0c18	681	#define BM_FTM_CnSC_CHF (0x00000080U) //!< Bit mask for FTM_CnSC_CHF.
mbed_official	146:f64d43ff0c18	682	#define BS_FTM_CnSC_CHF (1U) //!< Bit field size in bits for FTM_CnSC_CHF.
mbed_official	146:f64d43ff0c18	683
mbed_official	146:f64d43ff0c18	684	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	685	//! @brief Read current value of the FTM_CnSC_CHF field.
mbed_official	146:f64d43ff0c18	686	#define BR_FTM_CnSC_CHF(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHF))
mbed_official	146:f64d43ff0c18	687	#endif
mbed_official	146:f64d43ff0c18	688	//@}
mbed_official	146:f64d43ff0c18	689	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	690	// HW_FTM_CnV - Channel (n) Value
mbed_official	146:f64d43ff0c18	691	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	692
mbed_official	146:f64d43ff0c18	693	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	694	/*!
mbed_official	146:f64d43ff0c18	695	* @brief HW_FTM_CnV - Channel (n) Value (RW)
mbed_official	146:f64d43ff0c18	696	*
mbed_official	146:f64d43ff0c18	697	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	698	*
mbed_official	146:f64d43ff0c18	699	* These registers contain the captured FTM counter value for the input modes or
mbed_official	146:f64d43ff0c18	700	* the match value for the output modes. In Input Capture, Capture Test, and
mbed_official	146:f64d43ff0c18	701	* Dual Edge Capture modes, any write to a CnV register is ignored. In output modes,
mbed_official	146:f64d43ff0c18	702	* writing to a CnV register latches the value into a buffer. A CnV register is
mbed_official	146:f64d43ff0c18	703	* updated with the value of its write buffer according to Registers updated from
mbed_official	146:f64d43ff0c18	704	* write buffers. If FTMEN = 0, this write coherency mechanism may be manually
mbed_official	146:f64d43ff0c18	705	* reset by writing to the CnSC register whether BDM mode is active or not.
mbed_official	146:f64d43ff0c18	706	*/
mbed_official	146:f64d43ff0c18	707	typedef union _hw_ftm_cnv
mbed_official	146:f64d43ff0c18	708	{
mbed_official	146:f64d43ff0c18	709	uint32_t U;
mbed_official	146:f64d43ff0c18	710	struct _hw_ftm_cnv_bitfields
mbed_official	146:f64d43ff0c18	711	{
mbed_official	146:f64d43ff0c18	712	uint32_t VAL : 16; //!< [15:0] Channel Value
mbed_official	146:f64d43ff0c18	713	uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official	146:f64d43ff0c18	714	} B;
mbed_official	146:f64d43ff0c18	715	} hw_ftm_cnv_t;
mbed_official	146:f64d43ff0c18	716	#endif
mbed_official	146:f64d43ff0c18	717
mbed_official	146:f64d43ff0c18	718	/*!
mbed_official	146:f64d43ff0c18	719	* @name Constants and macros for entire FTM_CnV register
mbed_official	146:f64d43ff0c18	720	*/
mbed_official	146:f64d43ff0c18	721	//@{
mbed_official	146:f64d43ff0c18	722	#define HW_FTM_CnV_COUNT (8U)
mbed_official	146:f64d43ff0c18	723
mbed_official	146:f64d43ff0c18	724	#define HW_FTM_CnV_ADDR(x, n) (REGS_FTM_BASE(x) + 0x10U + (0x8U * n))
mbed_official	146:f64d43ff0c18	725
mbed_official	146:f64d43ff0c18	726	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	727	#define HW_FTM_CnV(x, n) ((__IO hw_ftm_cnv_t ) HW_FTM_CnV_ADDR(x, n))
mbed_official	146:f64d43ff0c18	728	#define HW_FTM_CnV_RD(x, n) (HW_FTM_CnV(x, n).U)
mbed_official	146:f64d43ff0c18	729	#define HW_FTM_CnV_WR(x, n, v) (HW_FTM_CnV(x, n).U = (v))
mbed_official	146:f64d43ff0c18	730	#define HW_FTM_CnV_SET(x, n, v) (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) \| (v)))
mbed_official	146:f64d43ff0c18	731	#define HW_FTM_CnV_CLR(x, n, v) (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) & ~(v)))
mbed_official	146:f64d43ff0c18	732	#define HW_FTM_CnV_TOG(x, n, v) (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) ^ (v)))
mbed_official	146:f64d43ff0c18	733	#endif
mbed_official	146:f64d43ff0c18	734	//@}
mbed_official	146:f64d43ff0c18	735
mbed_official	146:f64d43ff0c18	736	/*
mbed_official	146:f64d43ff0c18	737	* Constants & macros for individual FTM_CnV bitfields
mbed_official	146:f64d43ff0c18	738	*/
mbed_official	146:f64d43ff0c18	739
mbed_official	146:f64d43ff0c18	740	/*!
mbed_official	146:f64d43ff0c18	741	* @name Register FTM_CnV, field VAL[15:0] (RW)
mbed_official	146:f64d43ff0c18	742	*
mbed_official	146:f64d43ff0c18	743	* Captured FTM counter value of the input modes or the match value for the
mbed_official	146:f64d43ff0c18	744	* output modes
mbed_official	146:f64d43ff0c18	745	*/
mbed_official	146:f64d43ff0c18	746	//@{
mbed_official	146:f64d43ff0c18	747	#define BP_FTM_CnV_VAL (0U) //!< Bit position for FTM_CnV_VAL.
mbed_official	146:f64d43ff0c18	748	#define BM_FTM_CnV_VAL (0x0000FFFFU) //!< Bit mask for FTM_CnV_VAL.
mbed_official	146:f64d43ff0c18	749	#define BS_FTM_CnV_VAL (16U) //!< Bit field size in bits for FTM_CnV_VAL.
mbed_official	146:f64d43ff0c18	750
mbed_official	146:f64d43ff0c18	751	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	752	//! @brief Read current value of the FTM_CnV_VAL field.
mbed_official	146:f64d43ff0c18	753	#define BR_FTM_CnV_VAL(x, n) (HW_FTM_CnV(x, n).B.VAL)
mbed_official	146:f64d43ff0c18	754	#endif
mbed_official	146:f64d43ff0c18	755
mbed_official	146:f64d43ff0c18	756	//! @brief Format value for bitfield FTM_CnV_VAL.
mbed_official	146:f64d43ff0c18	757	#define BF_FTM_CnV_VAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CnV_VAL), uint32_t) & BM_FTM_CnV_VAL)
mbed_official	146:f64d43ff0c18	758
mbed_official	146:f64d43ff0c18	759	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	760	//! @brief Set the VAL field to a new value.
mbed_official	146:f64d43ff0c18	761	#define BW_FTM_CnV_VAL(x, n, v) (HW_FTM_CnV_WR(x, n, (HW_FTM_CnV_RD(x, n) & ~BM_FTM_CnV_VAL) \| BF_FTM_CnV_VAL(v)))
mbed_official	146:f64d43ff0c18	762	#endif
mbed_official	146:f64d43ff0c18	763	//@}
mbed_official	146:f64d43ff0c18	764
mbed_official	146:f64d43ff0c18	765	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	766	// HW_FTM_CNTIN - Counter Initial Value
mbed_official	146:f64d43ff0c18	767	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	768
mbed_official	146:f64d43ff0c18	769	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	770	/*!
mbed_official	146:f64d43ff0c18	771	* @brief HW_FTM_CNTIN - Counter Initial Value (RW)
mbed_official	146:f64d43ff0c18	772	*
mbed_official	146:f64d43ff0c18	773	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	774	*
mbed_official	146:f64d43ff0c18	775	* The Counter Initial Value register contains the initial value for the FTM
mbed_official	146:f64d43ff0c18	776	* counter. Writing to the CNTIN register latches the value into a buffer. The CNTIN
mbed_official	146:f64d43ff0c18	777	* register is updated with the value of its write buffer according to Registers
mbed_official	146:f64d43ff0c18	778	* updated from write buffers. When the FTM clock is initially selected, by
mbed_official	146:f64d43ff0c18	779	* writing a non-zero value to the CLKS bits, the FTM counter starts with the value
mbed_official	146:f64d43ff0c18	780	* 0x0000. To avoid this behavior, before the first write to select the FTM clock,
mbed_official	146:f64d43ff0c18	781	* write the new value to the the CNTIN register and then initialize the FTM
mbed_official	146:f64d43ff0c18	782	* counter by writing any value to the CNT register.
mbed_official	146:f64d43ff0c18	783	*/
mbed_official	146:f64d43ff0c18	784	typedef union _hw_ftm_cntin
mbed_official	146:f64d43ff0c18	785	{
mbed_official	146:f64d43ff0c18	786	uint32_t U;
mbed_official	146:f64d43ff0c18	787	struct _hw_ftm_cntin_bitfields
mbed_official	146:f64d43ff0c18	788	{
mbed_official	146:f64d43ff0c18	789	uint32_t INIT : 16; //!< [15:0]
mbed_official	146:f64d43ff0c18	790	uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official	146:f64d43ff0c18	791	} B;
mbed_official	146:f64d43ff0c18	792	} hw_ftm_cntin_t;
mbed_official	146:f64d43ff0c18	793	#endif
mbed_official	146:f64d43ff0c18	794
mbed_official	146:f64d43ff0c18	795	/*!
mbed_official	146:f64d43ff0c18	796	* @name Constants and macros for entire FTM_CNTIN register
mbed_official	146:f64d43ff0c18	797	*/
mbed_official	146:f64d43ff0c18	798	//@{
mbed_official	146:f64d43ff0c18	799	#define HW_FTM_CNTIN_ADDR(x) (REGS_FTM_BASE(x) + 0x4CU)
mbed_official	146:f64d43ff0c18	800
mbed_official	146:f64d43ff0c18	801	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	802	#define HW_FTM_CNTIN(x) ((__IO hw_ftm_cntin_t ) HW_FTM_CNTIN_ADDR(x))
mbed_official	146:f64d43ff0c18	803	#define HW_FTM_CNTIN_RD(x) (HW_FTM_CNTIN(x).U)
mbed_official	146:f64d43ff0c18	804	#define HW_FTM_CNTIN_WR(x, v) (HW_FTM_CNTIN(x).U = (v))
mbed_official	146:f64d43ff0c18	805	#define HW_FTM_CNTIN_SET(x, v) (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	806	#define HW_FTM_CNTIN_CLR(x, v) (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	807	#define HW_FTM_CNTIN_TOG(x, v) (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	808	#endif
mbed_official	146:f64d43ff0c18	809	//@}
mbed_official	146:f64d43ff0c18	810
mbed_official	146:f64d43ff0c18	811	/*
mbed_official	146:f64d43ff0c18	812	* Constants & macros for individual FTM_CNTIN bitfields
mbed_official	146:f64d43ff0c18	813	*/
mbed_official	146:f64d43ff0c18	814
mbed_official	146:f64d43ff0c18	815	/*!
mbed_official	146:f64d43ff0c18	816	* @name Register FTM_CNTIN, field INIT[15:0] (RW)
mbed_official	146:f64d43ff0c18	817	*
mbed_official	146:f64d43ff0c18	818	* Initial Value Of The FTM Counter
mbed_official	146:f64d43ff0c18	819	*/
mbed_official	146:f64d43ff0c18	820	//@{
mbed_official	146:f64d43ff0c18	821	#define BP_FTM_CNTIN_INIT (0U) //!< Bit position for FTM_CNTIN_INIT.
mbed_official	146:f64d43ff0c18	822	#define BM_FTM_CNTIN_INIT (0x0000FFFFU) //!< Bit mask for FTM_CNTIN_INIT.
mbed_official	146:f64d43ff0c18	823	#define BS_FTM_CNTIN_INIT (16U) //!< Bit field size in bits for FTM_CNTIN_INIT.
mbed_official	146:f64d43ff0c18	824
mbed_official	146:f64d43ff0c18	825	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	826	//! @brief Read current value of the FTM_CNTIN_INIT field.
mbed_official	146:f64d43ff0c18	827	#define BR_FTM_CNTIN_INIT(x) (HW_FTM_CNTIN(x).B.INIT)
mbed_official	146:f64d43ff0c18	828	#endif
mbed_official	146:f64d43ff0c18	829
mbed_official	146:f64d43ff0c18	830	//! @brief Format value for bitfield FTM_CNTIN_INIT.
mbed_official	146:f64d43ff0c18	831	#define BF_FTM_CNTIN_INIT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CNTIN_INIT), uint32_t) & BM_FTM_CNTIN_INIT)
mbed_official	146:f64d43ff0c18	832
mbed_official	146:f64d43ff0c18	833	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	834	//! @brief Set the INIT field to a new value.
mbed_official	146:f64d43ff0c18	835	#define BW_FTM_CNTIN_INIT(x, v) (HW_FTM_CNTIN_WR(x, (HW_FTM_CNTIN_RD(x) & ~BM_FTM_CNTIN_INIT) \| BF_FTM_CNTIN_INIT(v)))
mbed_official	146:f64d43ff0c18	836	#endif
mbed_official	146:f64d43ff0c18	837	//@}
mbed_official	146:f64d43ff0c18	838
mbed_official	146:f64d43ff0c18	839	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	840	// HW_FTM_STATUS - Capture And Compare Status
mbed_official	146:f64d43ff0c18	841	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	842
mbed_official	146:f64d43ff0c18	843	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	844	/*!
mbed_official	146:f64d43ff0c18	845	* @brief HW_FTM_STATUS - Capture And Compare Status (RW)
mbed_official	146:f64d43ff0c18	846	*
mbed_official	146:f64d43ff0c18	847	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	848	*
mbed_official	146:f64d43ff0c18	849	* The STATUS register contains a copy of the status flag CHnF bit in CnSC for
mbed_official	146:f64d43ff0c18	850	* each FTM channel for software convenience. Each CHnF bit in STATUS is a mirror
mbed_official	146:f64d43ff0c18	851	* of CHnF bit in CnSC. All CHnF bits can be checked using only one read of
mbed_official	146:f64d43ff0c18	852	* STATUS. All CHnF bits can be cleared by reading STATUS followed by writing 0x00 to
mbed_official	146:f64d43ff0c18	853	* STATUS. Hardware sets the individual channel flags when an event occurs on the
mbed_official	146:f64d43ff0c18	854	* channel. CHnF is cleared by reading STATUS while CHnF is set and then writing
mbed_official	146:f64d43ff0c18	855	* a 0 to the CHnF bit. Writing a 1 to CHnF has no effect. If another event
mbed_official	146:f64d43ff0c18	856	* occurs between the read and write operations, the write operation has no effect;
mbed_official	146:f64d43ff0c18	857	* therefore, CHnF remains set indicating an event has occurred. In this case, a
mbed_official	146:f64d43ff0c18	858	* CHnF interrupt request is not lost due to the clearing sequence for a previous
mbed_official	146:f64d43ff0c18	859	* CHnF. The STATUS register should be used only in Combine mode.
mbed_official	146:f64d43ff0c18	860	*/
mbed_official	146:f64d43ff0c18	861	typedef union _hw_ftm_status
mbed_official	146:f64d43ff0c18	862	{
mbed_official	146:f64d43ff0c18	863	uint32_t U;
mbed_official	146:f64d43ff0c18	864	struct _hw_ftm_status_bitfields
mbed_official	146:f64d43ff0c18	865	{
mbed_official	146:f64d43ff0c18	866	uint32_t CH0F : 1; //!< [0] Channel 0 Flag
mbed_official	146:f64d43ff0c18	867	uint32_t CH1F : 1; //!< [1] Channel 1 Flag
mbed_official	146:f64d43ff0c18	868	uint32_t CH2F : 1; //!< [2] Channel 2 Flag
mbed_official	146:f64d43ff0c18	869	uint32_t CH3F : 1; //!< [3] Channel 3 Flag
mbed_official	146:f64d43ff0c18	870	uint32_t CH4F : 1; //!< [4] Channel 4 Flag
mbed_official	146:f64d43ff0c18	871	uint32_t CH5F : 1; //!< [5] Channel 5 Flag
mbed_official	146:f64d43ff0c18	872	uint32_t CH6F : 1; //!< [6] Channel 6 Flag
mbed_official	146:f64d43ff0c18	873	uint32_t CH7F : 1; //!< [7] Channel 7 Flag
mbed_official	146:f64d43ff0c18	874	uint32_t RESERVED0 : 24; //!< [31:8]
mbed_official	146:f64d43ff0c18	875	} B;
mbed_official	146:f64d43ff0c18	876	} hw_ftm_status_t;
mbed_official	146:f64d43ff0c18	877	#endif
mbed_official	146:f64d43ff0c18	878
mbed_official	146:f64d43ff0c18	879	/*!
mbed_official	146:f64d43ff0c18	880	* @name Constants and macros for entire FTM_STATUS register
mbed_official	146:f64d43ff0c18	881	*/
mbed_official	146:f64d43ff0c18	882	//@{
mbed_official	146:f64d43ff0c18	883	#define HW_FTM_STATUS_ADDR(x) (REGS_FTM_BASE(x) + 0x50U)
mbed_official	146:f64d43ff0c18	884
mbed_official	146:f64d43ff0c18	885	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	886	#define HW_FTM_STATUS(x) ((__IO hw_ftm_status_t ) HW_FTM_STATUS_ADDR(x))
mbed_official	146:f64d43ff0c18	887	#define HW_FTM_STATUS_RD(x) (HW_FTM_STATUS(x).U)
mbed_official	146:f64d43ff0c18	888	#define HW_FTM_STATUS_WR(x, v) (HW_FTM_STATUS(x).U = (v))
mbed_official	146:f64d43ff0c18	889	#define HW_FTM_STATUS_SET(x, v) (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	890	#define HW_FTM_STATUS_CLR(x, v) (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	891	#define HW_FTM_STATUS_TOG(x, v) (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	892	#endif
mbed_official	146:f64d43ff0c18	893	//@}
mbed_official	146:f64d43ff0c18	894
mbed_official	146:f64d43ff0c18	895	/*
mbed_official	146:f64d43ff0c18	896	* Constants & macros for individual FTM_STATUS bitfields
mbed_official	146:f64d43ff0c18	897	*/
mbed_official	146:f64d43ff0c18	898
mbed_official	146:f64d43ff0c18	899	/*!
mbed_official	146:f64d43ff0c18	900	* @name Register FTM_STATUS, field CH0F[0] (W1C)
mbed_official	146:f64d43ff0c18	901	*
mbed_official	146:f64d43ff0c18	902	* See the register description.
mbed_official	146:f64d43ff0c18	903	*
mbed_official	146:f64d43ff0c18	904	* Values:
mbed_official	146:f64d43ff0c18	905	* - 0 - No channel event has occurred.
mbed_official	146:f64d43ff0c18	906	* - 1 - A channel event has occurred.
mbed_official	146:f64d43ff0c18	907	*/
mbed_official	146:f64d43ff0c18	908	//@{
mbed_official	146:f64d43ff0c18	909	#define BP_FTM_STATUS_CH0F (0U) //!< Bit position for FTM_STATUS_CH0F.
mbed_official	146:f64d43ff0c18	910	#define BM_FTM_STATUS_CH0F (0x00000001U) //!< Bit mask for FTM_STATUS_CH0F.
mbed_official	146:f64d43ff0c18	911	#define BS_FTM_STATUS_CH0F (1U) //!< Bit field size in bits for FTM_STATUS_CH0F.
mbed_official	146:f64d43ff0c18	912
mbed_official	146:f64d43ff0c18	913	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	914	//! @brief Read current value of the FTM_STATUS_CH0F field.
mbed_official	146:f64d43ff0c18	915	#define BR_FTM_STATUS_CH0F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH0F))
mbed_official	146:f64d43ff0c18	916	#endif
mbed_official	146:f64d43ff0c18	917
mbed_official	146:f64d43ff0c18	918	//! @brief Format value for bitfield FTM_STATUS_CH0F.
mbed_official	146:f64d43ff0c18	919	#define BF_FTM_STATUS_CH0F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH0F), uint32_t) & BM_FTM_STATUS_CH0F)
mbed_official	146:f64d43ff0c18	920
mbed_official	146:f64d43ff0c18	921	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	922	//! @brief Set the CH0F field to a new value.
mbed_official	146:f64d43ff0c18	923	#define BW_FTM_STATUS_CH0F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH0F) = (v))
mbed_official	146:f64d43ff0c18	924	#endif
mbed_official	146:f64d43ff0c18	925	//@}
mbed_official	146:f64d43ff0c18	926
mbed_official	146:f64d43ff0c18	927	/*!
mbed_official	146:f64d43ff0c18	928	* @name Register FTM_STATUS, field CH1F[1] (W1C)
mbed_official	146:f64d43ff0c18	929	*
mbed_official	146:f64d43ff0c18	930	* See the register description.
mbed_official	146:f64d43ff0c18	931	*
mbed_official	146:f64d43ff0c18	932	* Values:
mbed_official	146:f64d43ff0c18	933	* - 0 - No channel event has occurred.
mbed_official	146:f64d43ff0c18	934	* - 1 - A channel event has occurred.
mbed_official	146:f64d43ff0c18	935	*/
mbed_official	146:f64d43ff0c18	936	//@{
mbed_official	146:f64d43ff0c18	937	#define BP_FTM_STATUS_CH1F (1U) //!< Bit position for FTM_STATUS_CH1F.
mbed_official	146:f64d43ff0c18	938	#define BM_FTM_STATUS_CH1F (0x00000002U) //!< Bit mask for FTM_STATUS_CH1F.
mbed_official	146:f64d43ff0c18	939	#define BS_FTM_STATUS_CH1F (1U) //!< Bit field size in bits for FTM_STATUS_CH1F.
mbed_official	146:f64d43ff0c18	940
mbed_official	146:f64d43ff0c18	941	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	942	//! @brief Read current value of the FTM_STATUS_CH1F field.
mbed_official	146:f64d43ff0c18	943	#define BR_FTM_STATUS_CH1F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH1F))
mbed_official	146:f64d43ff0c18	944	#endif
mbed_official	146:f64d43ff0c18	945
mbed_official	146:f64d43ff0c18	946	//! @brief Format value for bitfield FTM_STATUS_CH1F.
mbed_official	146:f64d43ff0c18	947	#define BF_FTM_STATUS_CH1F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH1F), uint32_t) & BM_FTM_STATUS_CH1F)
mbed_official	146:f64d43ff0c18	948
mbed_official	146:f64d43ff0c18	949	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	950	//! @brief Set the CH1F field to a new value.
mbed_official	146:f64d43ff0c18	951	#define BW_FTM_STATUS_CH1F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH1F) = (v))
mbed_official	146:f64d43ff0c18	952	#endif
mbed_official	146:f64d43ff0c18	953	//@}
mbed_official	146:f64d43ff0c18	954
mbed_official	146:f64d43ff0c18	955	/*!
mbed_official	146:f64d43ff0c18	956	* @name Register FTM_STATUS, field CH2F[2] (W1C)
mbed_official	146:f64d43ff0c18	957	*
mbed_official	146:f64d43ff0c18	958	* See the register description.
mbed_official	146:f64d43ff0c18	959	*
mbed_official	146:f64d43ff0c18	960	* Values:
mbed_official	146:f64d43ff0c18	961	* - 0 - No channel event has occurred.
mbed_official	146:f64d43ff0c18	962	* - 1 - A channel event has occurred.
mbed_official	146:f64d43ff0c18	963	*/
mbed_official	146:f64d43ff0c18	964	//@{
mbed_official	146:f64d43ff0c18	965	#define BP_FTM_STATUS_CH2F (2U) //!< Bit position for FTM_STATUS_CH2F.
mbed_official	146:f64d43ff0c18	966	#define BM_FTM_STATUS_CH2F (0x00000004U) //!< Bit mask for FTM_STATUS_CH2F.
mbed_official	146:f64d43ff0c18	967	#define BS_FTM_STATUS_CH2F (1U) //!< Bit field size in bits for FTM_STATUS_CH2F.
mbed_official	146:f64d43ff0c18	968
mbed_official	146:f64d43ff0c18	969	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	970	//! @brief Read current value of the FTM_STATUS_CH2F field.
mbed_official	146:f64d43ff0c18	971	#define BR_FTM_STATUS_CH2F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH2F))
mbed_official	146:f64d43ff0c18	972	#endif
mbed_official	146:f64d43ff0c18	973
mbed_official	146:f64d43ff0c18	974	//! @brief Format value for bitfield FTM_STATUS_CH2F.
mbed_official	146:f64d43ff0c18	975	#define BF_FTM_STATUS_CH2F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH2F), uint32_t) & BM_FTM_STATUS_CH2F)
mbed_official	146:f64d43ff0c18	976
mbed_official	146:f64d43ff0c18	977	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	978	//! @brief Set the CH2F field to a new value.
mbed_official	146:f64d43ff0c18	979	#define BW_FTM_STATUS_CH2F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH2F) = (v))
mbed_official	146:f64d43ff0c18	980	#endif
mbed_official	146:f64d43ff0c18	981	//@}
mbed_official	146:f64d43ff0c18	982
mbed_official	146:f64d43ff0c18	983	/*!
mbed_official	146:f64d43ff0c18	984	* @name Register FTM_STATUS, field CH3F[3] (W1C)
mbed_official	146:f64d43ff0c18	985	*
mbed_official	146:f64d43ff0c18	986	* See the register description.
mbed_official	146:f64d43ff0c18	987	*
mbed_official	146:f64d43ff0c18	988	* Values:
mbed_official	146:f64d43ff0c18	989	* - 0 - No channel event has occurred.
mbed_official	146:f64d43ff0c18	990	* - 1 - A channel event has occurred.
mbed_official	146:f64d43ff0c18	991	*/
mbed_official	146:f64d43ff0c18	992	//@{
mbed_official	146:f64d43ff0c18	993	#define BP_FTM_STATUS_CH3F (3U) //!< Bit position for FTM_STATUS_CH3F.
mbed_official	146:f64d43ff0c18	994	#define BM_FTM_STATUS_CH3F (0x00000008U) //!< Bit mask for FTM_STATUS_CH3F.
mbed_official	146:f64d43ff0c18	995	#define BS_FTM_STATUS_CH3F (1U) //!< Bit field size in bits for FTM_STATUS_CH3F.
mbed_official	146:f64d43ff0c18	996
mbed_official	146:f64d43ff0c18	997	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	998	//! @brief Read current value of the FTM_STATUS_CH3F field.
mbed_official	146:f64d43ff0c18	999	#define BR_FTM_STATUS_CH3F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH3F))
mbed_official	146:f64d43ff0c18	1000	#endif
mbed_official	146:f64d43ff0c18	1001
mbed_official	146:f64d43ff0c18	1002	//! @brief Format value for bitfield FTM_STATUS_CH3F.
mbed_official	146:f64d43ff0c18	1003	#define BF_FTM_STATUS_CH3F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH3F), uint32_t) & BM_FTM_STATUS_CH3F)
mbed_official	146:f64d43ff0c18	1004
mbed_official	146:f64d43ff0c18	1005	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1006	//! @brief Set the CH3F field to a new value.
mbed_official	146:f64d43ff0c18	1007	#define BW_FTM_STATUS_CH3F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH3F) = (v))
mbed_official	146:f64d43ff0c18	1008	#endif
mbed_official	146:f64d43ff0c18	1009	//@}
mbed_official	146:f64d43ff0c18	1010
mbed_official	146:f64d43ff0c18	1011	/*!
mbed_official	146:f64d43ff0c18	1012	* @name Register FTM_STATUS, field CH4F[4] (W1C)
mbed_official	146:f64d43ff0c18	1013	*
mbed_official	146:f64d43ff0c18	1014	* See the register description.
mbed_official	146:f64d43ff0c18	1015	*
mbed_official	146:f64d43ff0c18	1016	* Values:
mbed_official	146:f64d43ff0c18	1017	* - 0 - No channel event has occurred.
mbed_official	146:f64d43ff0c18	1018	* - 1 - A channel event has occurred.
mbed_official	146:f64d43ff0c18	1019	*/
mbed_official	146:f64d43ff0c18	1020	//@{
mbed_official	146:f64d43ff0c18	1021	#define BP_FTM_STATUS_CH4F (4U) //!< Bit position for FTM_STATUS_CH4F.
mbed_official	146:f64d43ff0c18	1022	#define BM_FTM_STATUS_CH4F (0x00000010U) //!< Bit mask for FTM_STATUS_CH4F.
mbed_official	146:f64d43ff0c18	1023	#define BS_FTM_STATUS_CH4F (1U) //!< Bit field size in bits for FTM_STATUS_CH4F.
mbed_official	146:f64d43ff0c18	1024
mbed_official	146:f64d43ff0c18	1025	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1026	//! @brief Read current value of the FTM_STATUS_CH4F field.
mbed_official	146:f64d43ff0c18	1027	#define BR_FTM_STATUS_CH4F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH4F))
mbed_official	146:f64d43ff0c18	1028	#endif
mbed_official	146:f64d43ff0c18	1029
mbed_official	146:f64d43ff0c18	1030	//! @brief Format value for bitfield FTM_STATUS_CH4F.
mbed_official	146:f64d43ff0c18	1031	#define BF_FTM_STATUS_CH4F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH4F), uint32_t) & BM_FTM_STATUS_CH4F)
mbed_official	146:f64d43ff0c18	1032
mbed_official	146:f64d43ff0c18	1033	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1034	//! @brief Set the CH4F field to a new value.
mbed_official	146:f64d43ff0c18	1035	#define BW_FTM_STATUS_CH4F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH4F) = (v))
mbed_official	146:f64d43ff0c18	1036	#endif
mbed_official	146:f64d43ff0c18	1037	//@}
mbed_official	146:f64d43ff0c18	1038
mbed_official	146:f64d43ff0c18	1039	/*!
mbed_official	146:f64d43ff0c18	1040	* @name Register FTM_STATUS, field CH5F[5] (W1C)
mbed_official	146:f64d43ff0c18	1041	*
mbed_official	146:f64d43ff0c18	1042	* See the register description.
mbed_official	146:f64d43ff0c18	1043	*
mbed_official	146:f64d43ff0c18	1044	* Values:
mbed_official	146:f64d43ff0c18	1045	* - 0 - No channel event has occurred.
mbed_official	146:f64d43ff0c18	1046	* - 1 - A channel event has occurred.
mbed_official	146:f64d43ff0c18	1047	*/
mbed_official	146:f64d43ff0c18	1048	//@{
mbed_official	146:f64d43ff0c18	1049	#define BP_FTM_STATUS_CH5F (5U) //!< Bit position for FTM_STATUS_CH5F.
mbed_official	146:f64d43ff0c18	1050	#define BM_FTM_STATUS_CH5F (0x00000020U) //!< Bit mask for FTM_STATUS_CH5F.
mbed_official	146:f64d43ff0c18	1051	#define BS_FTM_STATUS_CH5F (1U) //!< Bit field size in bits for FTM_STATUS_CH5F.
mbed_official	146:f64d43ff0c18	1052
mbed_official	146:f64d43ff0c18	1053	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1054	//! @brief Read current value of the FTM_STATUS_CH5F field.
mbed_official	146:f64d43ff0c18	1055	#define BR_FTM_STATUS_CH5F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH5F))
mbed_official	146:f64d43ff0c18	1056	#endif
mbed_official	146:f64d43ff0c18	1057
mbed_official	146:f64d43ff0c18	1058	//! @brief Format value for bitfield FTM_STATUS_CH5F.
mbed_official	146:f64d43ff0c18	1059	#define BF_FTM_STATUS_CH5F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH5F), uint32_t) & BM_FTM_STATUS_CH5F)
mbed_official	146:f64d43ff0c18	1060
mbed_official	146:f64d43ff0c18	1061	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1062	//! @brief Set the CH5F field to a new value.
mbed_official	146:f64d43ff0c18	1063	#define BW_FTM_STATUS_CH5F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH5F) = (v))
mbed_official	146:f64d43ff0c18	1064	#endif
mbed_official	146:f64d43ff0c18	1065	//@}
mbed_official	146:f64d43ff0c18	1066
mbed_official	146:f64d43ff0c18	1067	/*!
mbed_official	146:f64d43ff0c18	1068	* @name Register FTM_STATUS, field CH6F[6] (W1C)
mbed_official	146:f64d43ff0c18	1069	*
mbed_official	146:f64d43ff0c18	1070	* See the register description.
mbed_official	146:f64d43ff0c18	1071	*
mbed_official	146:f64d43ff0c18	1072	* Values:
mbed_official	146:f64d43ff0c18	1073	* - 0 - No channel event has occurred.
mbed_official	146:f64d43ff0c18	1074	* - 1 - A channel event has occurred.
mbed_official	146:f64d43ff0c18	1075	*/
mbed_official	146:f64d43ff0c18	1076	//@{
mbed_official	146:f64d43ff0c18	1077	#define BP_FTM_STATUS_CH6F (6U) //!< Bit position for FTM_STATUS_CH6F.
mbed_official	146:f64d43ff0c18	1078	#define BM_FTM_STATUS_CH6F (0x00000040U) //!< Bit mask for FTM_STATUS_CH6F.
mbed_official	146:f64d43ff0c18	1079	#define BS_FTM_STATUS_CH6F (1U) //!< Bit field size in bits for FTM_STATUS_CH6F.
mbed_official	146:f64d43ff0c18	1080
mbed_official	146:f64d43ff0c18	1081	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1082	//! @brief Read current value of the FTM_STATUS_CH6F field.
mbed_official	146:f64d43ff0c18	1083	#define BR_FTM_STATUS_CH6F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH6F))
mbed_official	146:f64d43ff0c18	1084	#endif
mbed_official	146:f64d43ff0c18	1085
mbed_official	146:f64d43ff0c18	1086	//! @brief Format value for bitfield FTM_STATUS_CH6F.
mbed_official	146:f64d43ff0c18	1087	#define BF_FTM_STATUS_CH6F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH6F), uint32_t) & BM_FTM_STATUS_CH6F)
mbed_official	146:f64d43ff0c18	1088
mbed_official	146:f64d43ff0c18	1089	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1090	//! @brief Set the CH6F field to a new value.
mbed_official	146:f64d43ff0c18	1091	#define BW_FTM_STATUS_CH6F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH6F) = (v))
mbed_official	146:f64d43ff0c18	1092	#endif
mbed_official	146:f64d43ff0c18	1093	//@}
mbed_official	146:f64d43ff0c18	1094
mbed_official	146:f64d43ff0c18	1095	/*!
mbed_official	146:f64d43ff0c18	1096	* @name Register FTM_STATUS, field CH7F[7] (W1C)
mbed_official	146:f64d43ff0c18	1097	*
mbed_official	146:f64d43ff0c18	1098	* See the register description.
mbed_official	146:f64d43ff0c18	1099	*
mbed_official	146:f64d43ff0c18	1100	* Values:
mbed_official	146:f64d43ff0c18	1101	* - 0 - No channel event has occurred.
mbed_official	146:f64d43ff0c18	1102	* - 1 - A channel event has occurred.
mbed_official	146:f64d43ff0c18	1103	*/
mbed_official	146:f64d43ff0c18	1104	//@{
mbed_official	146:f64d43ff0c18	1105	#define BP_FTM_STATUS_CH7F (7U) //!< Bit position for FTM_STATUS_CH7F.
mbed_official	146:f64d43ff0c18	1106	#define BM_FTM_STATUS_CH7F (0x00000080U) //!< Bit mask for FTM_STATUS_CH7F.
mbed_official	146:f64d43ff0c18	1107	#define BS_FTM_STATUS_CH7F (1U) //!< Bit field size in bits for FTM_STATUS_CH7F.
mbed_official	146:f64d43ff0c18	1108
mbed_official	146:f64d43ff0c18	1109	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1110	//! @brief Read current value of the FTM_STATUS_CH7F field.
mbed_official	146:f64d43ff0c18	1111	#define BR_FTM_STATUS_CH7F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH7F))
mbed_official	146:f64d43ff0c18	1112	#endif
mbed_official	146:f64d43ff0c18	1113
mbed_official	146:f64d43ff0c18	1114	//! @brief Format value for bitfield FTM_STATUS_CH7F.
mbed_official	146:f64d43ff0c18	1115	#define BF_FTM_STATUS_CH7F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH7F), uint32_t) & BM_FTM_STATUS_CH7F)
mbed_official	146:f64d43ff0c18	1116
mbed_official	146:f64d43ff0c18	1117	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1118	//! @brief Set the CH7F field to a new value.
mbed_official	146:f64d43ff0c18	1119	#define BW_FTM_STATUS_CH7F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH7F) = (v))
mbed_official	146:f64d43ff0c18	1120	#endif
mbed_official	146:f64d43ff0c18	1121	//@}
mbed_official	146:f64d43ff0c18	1122
mbed_official	146:f64d43ff0c18	1123	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1124	// HW_FTM_MODE - Features Mode Selection
mbed_official	146:f64d43ff0c18	1125	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1126
mbed_official	146:f64d43ff0c18	1127	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1128	/*!
mbed_official	146:f64d43ff0c18	1129	* @brief HW_FTM_MODE - Features Mode Selection (RW)
mbed_official	146:f64d43ff0c18	1130	*
mbed_official	146:f64d43ff0c18	1131	* Reset value: 0x00000004U
mbed_official	146:f64d43ff0c18	1132	*
mbed_official	146:f64d43ff0c18	1133	* This register contains the global enable bit for FTM-specific features and
mbed_official	146:f64d43ff0c18	1134	* the control bits used to configure: Fault control mode and interrupt Capture
mbed_official	146:f64d43ff0c18	1135	* Test mode PWM synchronization Write protection Channel output initialization
mbed_official	146:f64d43ff0c18	1136	* These controls relate to all channels within this module.
mbed_official	146:f64d43ff0c18	1137	*/
mbed_official	146:f64d43ff0c18	1138	typedef union _hw_ftm_mode
mbed_official	146:f64d43ff0c18	1139	{
mbed_official	146:f64d43ff0c18	1140	uint32_t U;
mbed_official	146:f64d43ff0c18	1141	struct _hw_ftm_mode_bitfields
mbed_official	146:f64d43ff0c18	1142	{
mbed_official	146:f64d43ff0c18	1143	uint32_t FTMEN : 1; //!< [0] FTM Enable
mbed_official	146:f64d43ff0c18	1144	uint32_t INIT : 1; //!< [1] Initialize The Channels Output
mbed_official	146:f64d43ff0c18	1145	uint32_t WPDIS : 1; //!< [2] Write Protection Disable
mbed_official	146:f64d43ff0c18	1146	uint32_t PWMSYNC : 1; //!< [3] PWM Synchronization Mode
mbed_official	146:f64d43ff0c18	1147	uint32_t CAPTEST : 1; //!< [4] Capture Test Mode Enable
mbed_official	146:f64d43ff0c18	1148	uint32_t FAULTM : 2; //!< [6:5] Fault Control Mode
mbed_official	146:f64d43ff0c18	1149	uint32_t FAULTIE : 1; //!< [7] Fault Interrupt Enable
mbed_official	146:f64d43ff0c18	1150	uint32_t RESERVED0 : 24; //!< [31:8]
mbed_official	146:f64d43ff0c18	1151	} B;
mbed_official	146:f64d43ff0c18	1152	} hw_ftm_mode_t;
mbed_official	146:f64d43ff0c18	1153	#endif
mbed_official	146:f64d43ff0c18	1154
mbed_official	146:f64d43ff0c18	1155	/*!
mbed_official	146:f64d43ff0c18	1156	* @name Constants and macros for entire FTM_MODE register
mbed_official	146:f64d43ff0c18	1157	*/
mbed_official	146:f64d43ff0c18	1158	//@{
mbed_official	146:f64d43ff0c18	1159	#define HW_FTM_MODE_ADDR(x) (REGS_FTM_BASE(x) + 0x54U)
mbed_official	146:f64d43ff0c18	1160
mbed_official	146:f64d43ff0c18	1161	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1162	#define HW_FTM_MODE(x) ((__IO hw_ftm_mode_t ) HW_FTM_MODE_ADDR(x))
mbed_official	146:f64d43ff0c18	1163	#define HW_FTM_MODE_RD(x) (HW_FTM_MODE(x).U)
mbed_official	146:f64d43ff0c18	1164	#define HW_FTM_MODE_WR(x, v) (HW_FTM_MODE(x).U = (v))
mbed_official	146:f64d43ff0c18	1165	#define HW_FTM_MODE_SET(x, v) (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	1166	#define HW_FTM_MODE_CLR(x, v) (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	1167	#define HW_FTM_MODE_TOG(x, v) (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	1168	#endif
mbed_official	146:f64d43ff0c18	1169	//@}
mbed_official	146:f64d43ff0c18	1170
mbed_official	146:f64d43ff0c18	1171	/*
mbed_official	146:f64d43ff0c18	1172	* Constants & macros for individual FTM_MODE bitfields
mbed_official	146:f64d43ff0c18	1173	*/
mbed_official	146:f64d43ff0c18	1174
mbed_official	146:f64d43ff0c18	1175	/*!
mbed_official	146:f64d43ff0c18	1176	* @name Register FTM_MODE, field FTMEN[0] (RW)
mbed_official	146:f64d43ff0c18	1177	*
mbed_official	146:f64d43ff0c18	1178	* This field is write protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	1179	*
mbed_official	146:f64d43ff0c18	1180	* Values:
mbed_official	146:f64d43ff0c18	1181	* - 0 - Only the TPM-compatible registers (first set of registers) can be used
mbed_official	146:f64d43ff0c18	1182	* without any restriction. Do not use the FTM-specific registers.
mbed_official	146:f64d43ff0c18	1183	* - 1 - All registers including the FTM-specific registers (second set of
mbed_official	146:f64d43ff0c18	1184	* registers) are available for use with no restrictions.
mbed_official	146:f64d43ff0c18	1185	*/
mbed_official	146:f64d43ff0c18	1186	//@{
mbed_official	146:f64d43ff0c18	1187	#define BP_FTM_MODE_FTMEN (0U) //!< Bit position for FTM_MODE_FTMEN.
mbed_official	146:f64d43ff0c18	1188	#define BM_FTM_MODE_FTMEN (0x00000001U) //!< Bit mask for FTM_MODE_FTMEN.
mbed_official	146:f64d43ff0c18	1189	#define BS_FTM_MODE_FTMEN (1U) //!< Bit field size in bits for FTM_MODE_FTMEN.
mbed_official	146:f64d43ff0c18	1190
mbed_official	146:f64d43ff0c18	1191	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1192	//! @brief Read current value of the FTM_MODE_FTMEN field.
mbed_official	146:f64d43ff0c18	1193	#define BR_FTM_MODE_FTMEN(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FTMEN))
mbed_official	146:f64d43ff0c18	1194	#endif
mbed_official	146:f64d43ff0c18	1195
mbed_official	146:f64d43ff0c18	1196	//! @brief Format value for bitfield FTM_MODE_FTMEN.
mbed_official	146:f64d43ff0c18	1197	#define BF_FTM_MODE_FTMEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MODE_FTMEN), uint32_t) & BM_FTM_MODE_FTMEN)
mbed_official	146:f64d43ff0c18	1198
mbed_official	146:f64d43ff0c18	1199	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1200	//! @brief Set the FTMEN field to a new value.
mbed_official	146:f64d43ff0c18	1201	#define BW_FTM_MODE_FTMEN(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FTMEN) = (v))
mbed_official	146:f64d43ff0c18	1202	#endif
mbed_official	146:f64d43ff0c18	1203	//@}
mbed_official	146:f64d43ff0c18	1204
mbed_official	146:f64d43ff0c18	1205	/*!
mbed_official	146:f64d43ff0c18	1206	* @name Register FTM_MODE, field INIT[1] (RW)
mbed_official	146:f64d43ff0c18	1207	*
mbed_official	146:f64d43ff0c18	1208	* When a 1 is written to INIT bit the channels output is initialized according
mbed_official	146:f64d43ff0c18	1209	* to the state of their corresponding bit in the OUTINIT register. Writing a 0
mbed_official	146:f64d43ff0c18	1210	* to INIT bit has no effect. The INIT bit is always read as 0.
mbed_official	146:f64d43ff0c18	1211	*/
mbed_official	146:f64d43ff0c18	1212	//@{
mbed_official	146:f64d43ff0c18	1213	#define BP_FTM_MODE_INIT (1U) //!< Bit position for FTM_MODE_INIT.
mbed_official	146:f64d43ff0c18	1214	#define BM_FTM_MODE_INIT (0x00000002U) //!< Bit mask for FTM_MODE_INIT.
mbed_official	146:f64d43ff0c18	1215	#define BS_FTM_MODE_INIT (1U) //!< Bit field size in bits for FTM_MODE_INIT.
mbed_official	146:f64d43ff0c18	1216
mbed_official	146:f64d43ff0c18	1217	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1218	//! @brief Read current value of the FTM_MODE_INIT field.
mbed_official	146:f64d43ff0c18	1219	#define BR_FTM_MODE_INIT(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_INIT))
mbed_official	146:f64d43ff0c18	1220	#endif
mbed_official	146:f64d43ff0c18	1221
mbed_official	146:f64d43ff0c18	1222	//! @brief Format value for bitfield FTM_MODE_INIT.
mbed_official	146:f64d43ff0c18	1223	#define BF_FTM_MODE_INIT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MODE_INIT), uint32_t) & BM_FTM_MODE_INIT)
mbed_official	146:f64d43ff0c18	1224
mbed_official	146:f64d43ff0c18	1225	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1226	//! @brief Set the INIT field to a new value.
mbed_official	146:f64d43ff0c18	1227	#define BW_FTM_MODE_INIT(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_INIT) = (v))
mbed_official	146:f64d43ff0c18	1228	#endif
mbed_official	146:f64d43ff0c18	1229	//@}
mbed_official	146:f64d43ff0c18	1230
mbed_official	146:f64d43ff0c18	1231	/*!
mbed_official	146:f64d43ff0c18	1232	* @name Register FTM_MODE, field WPDIS[2] (RW)
mbed_official	146:f64d43ff0c18	1233	*
mbed_official	146:f64d43ff0c18	1234	* When write protection is enabled (WPDIS = 0), write protected bits cannot be
mbed_official	146:f64d43ff0c18	1235	* written. When write protection is disabled (WPDIS = 1), write protected bits
mbed_official	146:f64d43ff0c18	1236	* can be written. The WPDIS bit is the negation of the WPEN bit. WPDIS is cleared
mbed_official	146:f64d43ff0c18	1237	* when 1 is written to WPEN. WPDIS is set when WPEN bit is read as a 1 and then
mbed_official	146:f64d43ff0c18	1238	* 1 is written to WPDIS. Writing 0 to WPDIS has no effect.
mbed_official	146:f64d43ff0c18	1239	*
mbed_official	146:f64d43ff0c18	1240	* Values:
mbed_official	146:f64d43ff0c18	1241	* - 0 - Write protection is enabled.
mbed_official	146:f64d43ff0c18	1242	* - 1 - Write protection is disabled.
mbed_official	146:f64d43ff0c18	1243	*/
mbed_official	146:f64d43ff0c18	1244	//@{
mbed_official	146:f64d43ff0c18	1245	#define BP_FTM_MODE_WPDIS (2U) //!< Bit position for FTM_MODE_WPDIS.
mbed_official	146:f64d43ff0c18	1246	#define BM_FTM_MODE_WPDIS (0x00000004U) //!< Bit mask for FTM_MODE_WPDIS.
mbed_official	146:f64d43ff0c18	1247	#define BS_FTM_MODE_WPDIS (1U) //!< Bit field size in bits for FTM_MODE_WPDIS.
mbed_official	146:f64d43ff0c18	1248
mbed_official	146:f64d43ff0c18	1249	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1250	//! @brief Read current value of the FTM_MODE_WPDIS field.
mbed_official	146:f64d43ff0c18	1251	#define BR_FTM_MODE_WPDIS(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_WPDIS))
mbed_official	146:f64d43ff0c18	1252	#endif
mbed_official	146:f64d43ff0c18	1253
mbed_official	146:f64d43ff0c18	1254	//! @brief Format value for bitfield FTM_MODE_WPDIS.
mbed_official	146:f64d43ff0c18	1255	#define BF_FTM_MODE_WPDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MODE_WPDIS), uint32_t) & BM_FTM_MODE_WPDIS)
mbed_official	146:f64d43ff0c18	1256
mbed_official	146:f64d43ff0c18	1257	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1258	//! @brief Set the WPDIS field to a new value.
mbed_official	146:f64d43ff0c18	1259	#define BW_FTM_MODE_WPDIS(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_WPDIS) = (v))
mbed_official	146:f64d43ff0c18	1260	#endif
mbed_official	146:f64d43ff0c18	1261	//@}
mbed_official	146:f64d43ff0c18	1262
mbed_official	146:f64d43ff0c18	1263	/*!
mbed_official	146:f64d43ff0c18	1264	* @name Register FTM_MODE, field PWMSYNC[3] (RW)
mbed_official	146:f64d43ff0c18	1265	*
mbed_official	146:f64d43ff0c18	1266	* Selects which triggers can be used by MOD, CnV, OUTMASK, and FTM counter
mbed_official	146:f64d43ff0c18	1267	* synchronization. See PWM synchronization. The PWMSYNC bit configures the
mbed_official	146:f64d43ff0c18	1268	* synchronization when SYNCMODE is 0.
mbed_official	146:f64d43ff0c18	1269	*
mbed_official	146:f64d43ff0c18	1270	* Values:
mbed_official	146:f64d43ff0c18	1271	* - 0 - No restrictions. Software and hardware triggers can be used by MOD,
mbed_official	146:f64d43ff0c18	1272	* CnV, OUTMASK, and FTM counter synchronization.
mbed_official	146:f64d43ff0c18	1273	* - 1 - Software trigger can only be used by MOD and CnV synchronization, and
mbed_official	146:f64d43ff0c18	1274	* hardware triggers can only be used by OUTMASK and FTM counter
mbed_official	146:f64d43ff0c18	1275	* synchronization.
mbed_official	146:f64d43ff0c18	1276	*/
mbed_official	146:f64d43ff0c18	1277	//@{
mbed_official	146:f64d43ff0c18	1278	#define BP_FTM_MODE_PWMSYNC (3U) //!< Bit position for FTM_MODE_PWMSYNC.
mbed_official	146:f64d43ff0c18	1279	#define BM_FTM_MODE_PWMSYNC (0x00000008U) //!< Bit mask for FTM_MODE_PWMSYNC.
mbed_official	146:f64d43ff0c18	1280	#define BS_FTM_MODE_PWMSYNC (1U) //!< Bit field size in bits for FTM_MODE_PWMSYNC.
mbed_official	146:f64d43ff0c18	1281
mbed_official	146:f64d43ff0c18	1282	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1283	//! @brief Read current value of the FTM_MODE_PWMSYNC field.
mbed_official	146:f64d43ff0c18	1284	#define BR_FTM_MODE_PWMSYNC(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_PWMSYNC))
mbed_official	146:f64d43ff0c18	1285	#endif
mbed_official	146:f64d43ff0c18	1286
mbed_official	146:f64d43ff0c18	1287	//! @brief Format value for bitfield FTM_MODE_PWMSYNC.
mbed_official	146:f64d43ff0c18	1288	#define BF_FTM_MODE_PWMSYNC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MODE_PWMSYNC), uint32_t) & BM_FTM_MODE_PWMSYNC)
mbed_official	146:f64d43ff0c18	1289
mbed_official	146:f64d43ff0c18	1290	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1291	//! @brief Set the PWMSYNC field to a new value.
mbed_official	146:f64d43ff0c18	1292	#define BW_FTM_MODE_PWMSYNC(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_PWMSYNC) = (v))
mbed_official	146:f64d43ff0c18	1293	#endif
mbed_official	146:f64d43ff0c18	1294	//@}
mbed_official	146:f64d43ff0c18	1295
mbed_official	146:f64d43ff0c18	1296	/*!
mbed_official	146:f64d43ff0c18	1297	* @name Register FTM_MODE, field CAPTEST[4] (RW)
mbed_official	146:f64d43ff0c18	1298	*
mbed_official	146:f64d43ff0c18	1299	* Enables the capture test mode. This field is write protected. It can be
mbed_official	146:f64d43ff0c18	1300	* written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	1301	*
mbed_official	146:f64d43ff0c18	1302	* Values:
mbed_official	146:f64d43ff0c18	1303	* - 0 - Capture test mode is disabled.
mbed_official	146:f64d43ff0c18	1304	* - 1 - Capture test mode is enabled.
mbed_official	146:f64d43ff0c18	1305	*/
mbed_official	146:f64d43ff0c18	1306	//@{
mbed_official	146:f64d43ff0c18	1307	#define BP_FTM_MODE_CAPTEST (4U) //!< Bit position for FTM_MODE_CAPTEST.
mbed_official	146:f64d43ff0c18	1308	#define BM_FTM_MODE_CAPTEST (0x00000010U) //!< Bit mask for FTM_MODE_CAPTEST.
mbed_official	146:f64d43ff0c18	1309	#define BS_FTM_MODE_CAPTEST (1U) //!< Bit field size in bits for FTM_MODE_CAPTEST.
mbed_official	146:f64d43ff0c18	1310
mbed_official	146:f64d43ff0c18	1311	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1312	//! @brief Read current value of the FTM_MODE_CAPTEST field.
mbed_official	146:f64d43ff0c18	1313	#define BR_FTM_MODE_CAPTEST(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_CAPTEST))
mbed_official	146:f64d43ff0c18	1314	#endif
mbed_official	146:f64d43ff0c18	1315
mbed_official	146:f64d43ff0c18	1316	//! @brief Format value for bitfield FTM_MODE_CAPTEST.
mbed_official	146:f64d43ff0c18	1317	#define BF_FTM_MODE_CAPTEST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MODE_CAPTEST), uint32_t) & BM_FTM_MODE_CAPTEST)
mbed_official	146:f64d43ff0c18	1318
mbed_official	146:f64d43ff0c18	1319	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1320	//! @brief Set the CAPTEST field to a new value.
mbed_official	146:f64d43ff0c18	1321	#define BW_FTM_MODE_CAPTEST(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_CAPTEST) = (v))
mbed_official	146:f64d43ff0c18	1322	#endif
mbed_official	146:f64d43ff0c18	1323	//@}
mbed_official	146:f64d43ff0c18	1324
mbed_official	146:f64d43ff0c18	1325	/*!
mbed_official	146:f64d43ff0c18	1326	* @name Register FTM_MODE, field FAULTM[6:5] (RW)
mbed_official	146:f64d43ff0c18	1327	*
mbed_official	146:f64d43ff0c18	1328	* Defines the FTM fault control mode. This field is write protected. It can be
mbed_official	146:f64d43ff0c18	1329	* written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	1330	*
mbed_official	146:f64d43ff0c18	1331	* Values:
mbed_official	146:f64d43ff0c18	1332	* - 00 - Fault control is disabled for all channels.
mbed_official	146:f64d43ff0c18	1333	* - 01 - Fault control is enabled for even channels only (channels 0, 2, 4, and
mbed_official	146:f64d43ff0c18	1334	* 6), and the selected mode is the manual fault clearing.
mbed_official	146:f64d43ff0c18	1335	* - 10 - Fault control is enabled for all channels, and the selected mode is
mbed_official	146:f64d43ff0c18	1336	* the manual fault clearing.
mbed_official	146:f64d43ff0c18	1337	* - 11 - Fault control is enabled for all channels, and the selected mode is
mbed_official	146:f64d43ff0c18	1338	* the automatic fault clearing.
mbed_official	146:f64d43ff0c18	1339	*/
mbed_official	146:f64d43ff0c18	1340	//@{
mbed_official	146:f64d43ff0c18	1341	#define BP_FTM_MODE_FAULTM (5U) //!< Bit position for FTM_MODE_FAULTM.
mbed_official	146:f64d43ff0c18	1342	#define BM_FTM_MODE_FAULTM (0x00000060U) //!< Bit mask for FTM_MODE_FAULTM.
mbed_official	146:f64d43ff0c18	1343	#define BS_FTM_MODE_FAULTM (2U) //!< Bit field size in bits for FTM_MODE_FAULTM.
mbed_official	146:f64d43ff0c18	1344
mbed_official	146:f64d43ff0c18	1345	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1346	//! @brief Read current value of the FTM_MODE_FAULTM field.
mbed_official	146:f64d43ff0c18	1347	#define BR_FTM_MODE_FAULTM(x) (HW_FTM_MODE(x).B.FAULTM)
mbed_official	146:f64d43ff0c18	1348	#endif
mbed_official	146:f64d43ff0c18	1349
mbed_official	146:f64d43ff0c18	1350	//! @brief Format value for bitfield FTM_MODE_FAULTM.
mbed_official	146:f64d43ff0c18	1351	#define BF_FTM_MODE_FAULTM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MODE_FAULTM), uint32_t) & BM_FTM_MODE_FAULTM)
mbed_official	146:f64d43ff0c18	1352
mbed_official	146:f64d43ff0c18	1353	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1354	//! @brief Set the FAULTM field to a new value.
mbed_official	146:f64d43ff0c18	1355	#define BW_FTM_MODE_FAULTM(x, v) (HW_FTM_MODE_WR(x, (HW_FTM_MODE_RD(x) & ~BM_FTM_MODE_FAULTM) \| BF_FTM_MODE_FAULTM(v)))
mbed_official	146:f64d43ff0c18	1356	#endif
mbed_official	146:f64d43ff0c18	1357	//@}
mbed_official	146:f64d43ff0c18	1358
mbed_official	146:f64d43ff0c18	1359	/*!
mbed_official	146:f64d43ff0c18	1360	* @name Register FTM_MODE, field FAULTIE[7] (RW)
mbed_official	146:f64d43ff0c18	1361	*
mbed_official	146:f64d43ff0c18	1362	* Enables the generation of an interrupt when a fault is detected by FTM and
mbed_official	146:f64d43ff0c18	1363	* the FTM fault control is enabled.
mbed_official	146:f64d43ff0c18	1364	*
mbed_official	146:f64d43ff0c18	1365	* Values:
mbed_official	146:f64d43ff0c18	1366	* - 0 - Fault control interrupt is disabled.
mbed_official	146:f64d43ff0c18	1367	* - 1 - Fault control interrupt is enabled.
mbed_official	146:f64d43ff0c18	1368	*/
mbed_official	146:f64d43ff0c18	1369	//@{
mbed_official	146:f64d43ff0c18	1370	#define BP_FTM_MODE_FAULTIE (7U) //!< Bit position for FTM_MODE_FAULTIE.
mbed_official	146:f64d43ff0c18	1371	#define BM_FTM_MODE_FAULTIE (0x00000080U) //!< Bit mask for FTM_MODE_FAULTIE.
mbed_official	146:f64d43ff0c18	1372	#define BS_FTM_MODE_FAULTIE (1U) //!< Bit field size in bits for FTM_MODE_FAULTIE.
mbed_official	146:f64d43ff0c18	1373
mbed_official	146:f64d43ff0c18	1374	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1375	//! @brief Read current value of the FTM_MODE_FAULTIE field.
mbed_official	146:f64d43ff0c18	1376	#define BR_FTM_MODE_FAULTIE(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FAULTIE))
mbed_official	146:f64d43ff0c18	1377	#endif
mbed_official	146:f64d43ff0c18	1378
mbed_official	146:f64d43ff0c18	1379	//! @brief Format value for bitfield FTM_MODE_FAULTIE.
mbed_official	146:f64d43ff0c18	1380	#define BF_FTM_MODE_FAULTIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MODE_FAULTIE), uint32_t) & BM_FTM_MODE_FAULTIE)
mbed_official	146:f64d43ff0c18	1381
mbed_official	146:f64d43ff0c18	1382	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1383	//! @brief Set the FAULTIE field to a new value.
mbed_official	146:f64d43ff0c18	1384	#define BW_FTM_MODE_FAULTIE(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FAULTIE) = (v))
mbed_official	146:f64d43ff0c18	1385	#endif
mbed_official	146:f64d43ff0c18	1386	//@}
mbed_official	146:f64d43ff0c18	1387
mbed_official	146:f64d43ff0c18	1388	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1389	// HW_FTM_SYNC - Synchronization
mbed_official	146:f64d43ff0c18	1390	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1391
mbed_official	146:f64d43ff0c18	1392	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1393	/*!
mbed_official	146:f64d43ff0c18	1394	* @brief HW_FTM_SYNC - Synchronization (RW)
mbed_official	146:f64d43ff0c18	1395	*
mbed_official	146:f64d43ff0c18	1396	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	1397	*
mbed_official	146:f64d43ff0c18	1398	* This register configures the PWM synchronization. A synchronization event can
mbed_official	146:f64d43ff0c18	1399	* perform the synchronized update of MOD, CV, and OUTMASK registers with the
mbed_official	146:f64d43ff0c18	1400	* value of their write buffer and the FTM counter initialization. The software
mbed_official	146:f64d43ff0c18	1401	* trigger, SWSYNC bit, and hardware triggers TRIG0, TRIG1, and TRIG2 bits have a
mbed_official	146:f64d43ff0c18	1402	* potential conflict if used together when SYNCMODE = 0. Use only hardware or
mbed_official	146:f64d43ff0c18	1403	* software triggers but not both at the same time, otherwise unpredictable behavior
mbed_official	146:f64d43ff0c18	1404	* is likely to happen. The selection of the loading point, CNTMAX and CNTMIN
mbed_official	146:f64d43ff0c18	1405	* bits, is intended to provide the update of MOD, CNTIN, and CnV registers across
mbed_official	146:f64d43ff0c18	1406	* all enabled channels simultaneously. The use of the loading point selection
mbed_official	146:f64d43ff0c18	1407	* together with SYNCMODE = 0 and hardware trigger selection, TRIG0, TRIG1, or TRIG2
mbed_official	146:f64d43ff0c18	1408	* bits, is likely to result in unpredictable behavior. The synchronization
mbed_official	146:f64d43ff0c18	1409	* event selection also depends on the PWMSYNC (MODE register) and SYNCMODE (SYNCONF
mbed_official	146:f64d43ff0c18	1410	* register) bits. See PWM synchronization.
mbed_official	146:f64d43ff0c18	1411	*/
mbed_official	146:f64d43ff0c18	1412	typedef union _hw_ftm_sync
mbed_official	146:f64d43ff0c18	1413	{
mbed_official	146:f64d43ff0c18	1414	uint32_t U;
mbed_official	146:f64d43ff0c18	1415	struct _hw_ftm_sync_bitfields
mbed_official	146:f64d43ff0c18	1416	{
mbed_official	146:f64d43ff0c18	1417	uint32_t CNTMIN : 1; //!< [0] Minimum Loading Point Enable
mbed_official	146:f64d43ff0c18	1418	uint32_t CNTMAX : 1; //!< [1] Maximum Loading Point Enable
mbed_official	146:f64d43ff0c18	1419	uint32_t REINIT : 1; //!< [2] FTM Counter Reinitialization By
mbed_official	146:f64d43ff0c18	1420	//! Synchronization (FTM counter synchronization)
mbed_official	146:f64d43ff0c18	1421	uint32_t SYNCHOM : 1; //!< [3] Output Mask Synchronization
mbed_official	146:f64d43ff0c18	1422	uint32_t TRIG0 : 1; //!< [4] PWM Synchronization Hardware Trigger 0
mbed_official	146:f64d43ff0c18	1423	uint32_t TRIG1 : 1; //!< [5] PWM Synchronization Hardware Trigger 1
mbed_official	146:f64d43ff0c18	1424	uint32_t TRIG2 : 1; //!< [6] PWM Synchronization Hardware Trigger 2
mbed_official	146:f64d43ff0c18	1425	uint32_t SWSYNC : 1; //!< [7] PWM Synchronization Software Trigger
mbed_official	146:f64d43ff0c18	1426	uint32_t RESERVED0 : 24; //!< [31:8]
mbed_official	146:f64d43ff0c18	1427	} B;
mbed_official	146:f64d43ff0c18	1428	} hw_ftm_sync_t;
mbed_official	146:f64d43ff0c18	1429	#endif
mbed_official	146:f64d43ff0c18	1430
mbed_official	146:f64d43ff0c18	1431	/*!
mbed_official	146:f64d43ff0c18	1432	* @name Constants and macros for entire FTM_SYNC register
mbed_official	146:f64d43ff0c18	1433	*/
mbed_official	146:f64d43ff0c18	1434	//@{
mbed_official	146:f64d43ff0c18	1435	#define HW_FTM_SYNC_ADDR(x) (REGS_FTM_BASE(x) + 0x58U)
mbed_official	146:f64d43ff0c18	1436
mbed_official	146:f64d43ff0c18	1437	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1438	#define HW_FTM_SYNC(x) ((__IO hw_ftm_sync_t ) HW_FTM_SYNC_ADDR(x))
mbed_official	146:f64d43ff0c18	1439	#define HW_FTM_SYNC_RD(x) (HW_FTM_SYNC(x).U)
mbed_official	146:f64d43ff0c18	1440	#define HW_FTM_SYNC_WR(x, v) (HW_FTM_SYNC(x).U = (v))
mbed_official	146:f64d43ff0c18	1441	#define HW_FTM_SYNC_SET(x, v) (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	1442	#define HW_FTM_SYNC_CLR(x, v) (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	1443	#define HW_FTM_SYNC_TOG(x, v) (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	1444	#endif
mbed_official	146:f64d43ff0c18	1445	//@}
mbed_official	146:f64d43ff0c18	1446
mbed_official	146:f64d43ff0c18	1447	/*
mbed_official	146:f64d43ff0c18	1448	* Constants & macros for individual FTM_SYNC bitfields
mbed_official	146:f64d43ff0c18	1449	*/
mbed_official	146:f64d43ff0c18	1450
mbed_official	146:f64d43ff0c18	1451	/*!
mbed_official	146:f64d43ff0c18	1452	* @name Register FTM_SYNC, field CNTMIN[0] (RW)
mbed_official	146:f64d43ff0c18	1453	*
mbed_official	146:f64d43ff0c18	1454	* Selects the minimum loading point to PWM synchronization. See Boundary cycle
mbed_official	146:f64d43ff0c18	1455	* and loading points. If CNTMIN is one, the selected loading point is when the
mbed_official	146:f64d43ff0c18	1456	* FTM counter reaches its minimum value (CNTIN register).
mbed_official	146:f64d43ff0c18	1457	*
mbed_official	146:f64d43ff0c18	1458	* Values:
mbed_official	146:f64d43ff0c18	1459	* - 0 - The minimum loading point is disabled.
mbed_official	146:f64d43ff0c18	1460	* - 1 - The minimum loading point is enabled.
mbed_official	146:f64d43ff0c18	1461	*/
mbed_official	146:f64d43ff0c18	1462	//@{
mbed_official	146:f64d43ff0c18	1463	#define BP_FTM_SYNC_CNTMIN (0U) //!< Bit position for FTM_SYNC_CNTMIN.
mbed_official	146:f64d43ff0c18	1464	#define BM_FTM_SYNC_CNTMIN (0x00000001U) //!< Bit mask for FTM_SYNC_CNTMIN.
mbed_official	146:f64d43ff0c18	1465	#define BS_FTM_SYNC_CNTMIN (1U) //!< Bit field size in bits for FTM_SYNC_CNTMIN.
mbed_official	146:f64d43ff0c18	1466
mbed_official	146:f64d43ff0c18	1467	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1468	//! @brief Read current value of the FTM_SYNC_CNTMIN field.
mbed_official	146:f64d43ff0c18	1469	#define BR_FTM_SYNC_CNTMIN(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMIN))
mbed_official	146:f64d43ff0c18	1470	#endif
mbed_official	146:f64d43ff0c18	1471
mbed_official	146:f64d43ff0c18	1472	//! @brief Format value for bitfield FTM_SYNC_CNTMIN.
mbed_official	146:f64d43ff0c18	1473	#define BF_FTM_SYNC_CNTMIN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_CNTMIN), uint32_t) & BM_FTM_SYNC_CNTMIN)
mbed_official	146:f64d43ff0c18	1474
mbed_official	146:f64d43ff0c18	1475	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1476	//! @brief Set the CNTMIN field to a new value.
mbed_official	146:f64d43ff0c18	1477	#define BW_FTM_SYNC_CNTMIN(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMIN) = (v))
mbed_official	146:f64d43ff0c18	1478	#endif
mbed_official	146:f64d43ff0c18	1479	//@}
mbed_official	146:f64d43ff0c18	1480
mbed_official	146:f64d43ff0c18	1481	/*!
mbed_official	146:f64d43ff0c18	1482	* @name Register FTM_SYNC, field CNTMAX[1] (RW)
mbed_official	146:f64d43ff0c18	1483	*
mbed_official	146:f64d43ff0c18	1484	* Selects the maximum loading point to PWM synchronization. See Boundary cycle
mbed_official	146:f64d43ff0c18	1485	* and loading points. If CNTMAX is 1, the selected loading point is when the FTM
mbed_official	146:f64d43ff0c18	1486	* counter reaches its maximum value (MOD register).
mbed_official	146:f64d43ff0c18	1487	*
mbed_official	146:f64d43ff0c18	1488	* Values:
mbed_official	146:f64d43ff0c18	1489	* - 0 - The maximum loading point is disabled.
mbed_official	146:f64d43ff0c18	1490	* - 1 - The maximum loading point is enabled.
mbed_official	146:f64d43ff0c18	1491	*/
mbed_official	146:f64d43ff0c18	1492	//@{
mbed_official	146:f64d43ff0c18	1493	#define BP_FTM_SYNC_CNTMAX (1U) //!< Bit position for FTM_SYNC_CNTMAX.
mbed_official	146:f64d43ff0c18	1494	#define BM_FTM_SYNC_CNTMAX (0x00000002U) //!< Bit mask for FTM_SYNC_CNTMAX.
mbed_official	146:f64d43ff0c18	1495	#define BS_FTM_SYNC_CNTMAX (1U) //!< Bit field size in bits for FTM_SYNC_CNTMAX.
mbed_official	146:f64d43ff0c18	1496
mbed_official	146:f64d43ff0c18	1497	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1498	//! @brief Read current value of the FTM_SYNC_CNTMAX field.
mbed_official	146:f64d43ff0c18	1499	#define BR_FTM_SYNC_CNTMAX(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMAX))
mbed_official	146:f64d43ff0c18	1500	#endif
mbed_official	146:f64d43ff0c18	1501
mbed_official	146:f64d43ff0c18	1502	//! @brief Format value for bitfield FTM_SYNC_CNTMAX.
mbed_official	146:f64d43ff0c18	1503	#define BF_FTM_SYNC_CNTMAX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_CNTMAX), uint32_t) & BM_FTM_SYNC_CNTMAX)
mbed_official	146:f64d43ff0c18	1504
mbed_official	146:f64d43ff0c18	1505	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1506	//! @brief Set the CNTMAX field to a new value.
mbed_official	146:f64d43ff0c18	1507	#define BW_FTM_SYNC_CNTMAX(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMAX) = (v))
mbed_official	146:f64d43ff0c18	1508	#endif
mbed_official	146:f64d43ff0c18	1509	//@}
mbed_official	146:f64d43ff0c18	1510
mbed_official	146:f64d43ff0c18	1511	/*!
mbed_official	146:f64d43ff0c18	1512	* @name Register FTM_SYNC, field REINIT[2] (RW)
mbed_official	146:f64d43ff0c18	1513	*
mbed_official	146:f64d43ff0c18	1514	* Determines if the FTM counter is reinitialized when the selected trigger for
mbed_official	146:f64d43ff0c18	1515	* the synchronization is detected. The REINIT bit configures the synchronization
mbed_official	146:f64d43ff0c18	1516	* when SYNCMODE is zero.
mbed_official	146:f64d43ff0c18	1517	*
mbed_official	146:f64d43ff0c18	1518	* Values:
mbed_official	146:f64d43ff0c18	1519	* - 0 - FTM counter continues to count normally.
mbed_official	146:f64d43ff0c18	1520	* - 1 - FTM counter is updated with its initial value when the selected trigger
mbed_official	146:f64d43ff0c18	1521	* is detected.
mbed_official	146:f64d43ff0c18	1522	*/
mbed_official	146:f64d43ff0c18	1523	//@{
mbed_official	146:f64d43ff0c18	1524	#define BP_FTM_SYNC_REINIT (2U) //!< Bit position for FTM_SYNC_REINIT.
mbed_official	146:f64d43ff0c18	1525	#define BM_FTM_SYNC_REINIT (0x00000004U) //!< Bit mask for FTM_SYNC_REINIT.
mbed_official	146:f64d43ff0c18	1526	#define BS_FTM_SYNC_REINIT (1U) //!< Bit field size in bits for FTM_SYNC_REINIT.
mbed_official	146:f64d43ff0c18	1527
mbed_official	146:f64d43ff0c18	1528	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1529	//! @brief Read current value of the FTM_SYNC_REINIT field.
mbed_official	146:f64d43ff0c18	1530	#define BR_FTM_SYNC_REINIT(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_REINIT))
mbed_official	146:f64d43ff0c18	1531	#endif
mbed_official	146:f64d43ff0c18	1532
mbed_official	146:f64d43ff0c18	1533	//! @brief Format value for bitfield FTM_SYNC_REINIT.
mbed_official	146:f64d43ff0c18	1534	#define BF_FTM_SYNC_REINIT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_REINIT), uint32_t) & BM_FTM_SYNC_REINIT)
mbed_official	146:f64d43ff0c18	1535
mbed_official	146:f64d43ff0c18	1536	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1537	//! @brief Set the REINIT field to a new value.
mbed_official	146:f64d43ff0c18	1538	#define BW_FTM_SYNC_REINIT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_REINIT) = (v))
mbed_official	146:f64d43ff0c18	1539	#endif
mbed_official	146:f64d43ff0c18	1540	//@}
mbed_official	146:f64d43ff0c18	1541
mbed_official	146:f64d43ff0c18	1542	/*!
mbed_official	146:f64d43ff0c18	1543	* @name Register FTM_SYNC, field SYNCHOM[3] (RW)
mbed_official	146:f64d43ff0c18	1544	*
mbed_official	146:f64d43ff0c18	1545	* Selects when the OUTMASK register is updated with the value of its buffer.
mbed_official	146:f64d43ff0c18	1546	*
mbed_official	146:f64d43ff0c18	1547	* Values:
mbed_official	146:f64d43ff0c18	1548	* - 0 - OUTMASK register is updated with the value of its buffer in all rising
mbed_official	146:f64d43ff0c18	1549	* edges of the system clock.
mbed_official	146:f64d43ff0c18	1550	* - 1 - OUTMASK register is updated with the value of its buffer only by the
mbed_official	146:f64d43ff0c18	1551	* PWM synchronization.
mbed_official	146:f64d43ff0c18	1552	*/
mbed_official	146:f64d43ff0c18	1553	//@{
mbed_official	146:f64d43ff0c18	1554	#define BP_FTM_SYNC_SYNCHOM (3U) //!< Bit position for FTM_SYNC_SYNCHOM.
mbed_official	146:f64d43ff0c18	1555	#define BM_FTM_SYNC_SYNCHOM (0x00000008U) //!< Bit mask for FTM_SYNC_SYNCHOM.
mbed_official	146:f64d43ff0c18	1556	#define BS_FTM_SYNC_SYNCHOM (1U) //!< Bit field size in bits for FTM_SYNC_SYNCHOM.
mbed_official	146:f64d43ff0c18	1557
mbed_official	146:f64d43ff0c18	1558	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1559	//! @brief Read current value of the FTM_SYNC_SYNCHOM field.
mbed_official	146:f64d43ff0c18	1560	#define BR_FTM_SYNC_SYNCHOM(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SYNCHOM))
mbed_official	146:f64d43ff0c18	1561	#endif
mbed_official	146:f64d43ff0c18	1562
mbed_official	146:f64d43ff0c18	1563	//! @brief Format value for bitfield FTM_SYNC_SYNCHOM.
mbed_official	146:f64d43ff0c18	1564	#define BF_FTM_SYNC_SYNCHOM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_SYNCHOM), uint32_t) & BM_FTM_SYNC_SYNCHOM)
mbed_official	146:f64d43ff0c18	1565
mbed_official	146:f64d43ff0c18	1566	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1567	//! @brief Set the SYNCHOM field to a new value.
mbed_official	146:f64d43ff0c18	1568	#define BW_FTM_SYNC_SYNCHOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SYNCHOM) = (v))
mbed_official	146:f64d43ff0c18	1569	#endif
mbed_official	146:f64d43ff0c18	1570	//@}
mbed_official	146:f64d43ff0c18	1571
mbed_official	146:f64d43ff0c18	1572	/*!
mbed_official	146:f64d43ff0c18	1573	* @name Register FTM_SYNC, field TRIG0[4] (RW)
mbed_official	146:f64d43ff0c18	1574	*
mbed_official	146:f64d43ff0c18	1575	* Enables hardware trigger 0 to the PWM synchronization. Hardware trigger 0
mbed_official	146:f64d43ff0c18	1576	* occurs when a rising edge is detected at the trigger 0 input signal.
mbed_official	146:f64d43ff0c18	1577	*
mbed_official	146:f64d43ff0c18	1578	* Values:
mbed_official	146:f64d43ff0c18	1579	* - 0 - Trigger is disabled.
mbed_official	146:f64d43ff0c18	1580	* - 1 - Trigger is enabled.
mbed_official	146:f64d43ff0c18	1581	*/
mbed_official	146:f64d43ff0c18	1582	//@{
mbed_official	146:f64d43ff0c18	1583	#define BP_FTM_SYNC_TRIG0 (4U) //!< Bit position for FTM_SYNC_TRIG0.
mbed_official	146:f64d43ff0c18	1584	#define BM_FTM_SYNC_TRIG0 (0x00000010U) //!< Bit mask for FTM_SYNC_TRIG0.
mbed_official	146:f64d43ff0c18	1585	#define BS_FTM_SYNC_TRIG0 (1U) //!< Bit field size in bits for FTM_SYNC_TRIG0.
mbed_official	146:f64d43ff0c18	1586
mbed_official	146:f64d43ff0c18	1587	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1588	//! @brief Read current value of the FTM_SYNC_TRIG0 field.
mbed_official	146:f64d43ff0c18	1589	#define BR_FTM_SYNC_TRIG0(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG0))
mbed_official	146:f64d43ff0c18	1590	#endif
mbed_official	146:f64d43ff0c18	1591
mbed_official	146:f64d43ff0c18	1592	//! @brief Format value for bitfield FTM_SYNC_TRIG0.
mbed_official	146:f64d43ff0c18	1593	#define BF_FTM_SYNC_TRIG0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_TRIG0), uint32_t) & BM_FTM_SYNC_TRIG0)
mbed_official	146:f64d43ff0c18	1594
mbed_official	146:f64d43ff0c18	1595	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1596	//! @brief Set the TRIG0 field to a new value.
mbed_official	146:f64d43ff0c18	1597	#define BW_FTM_SYNC_TRIG0(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG0) = (v))
mbed_official	146:f64d43ff0c18	1598	#endif
mbed_official	146:f64d43ff0c18	1599	//@}
mbed_official	146:f64d43ff0c18	1600
mbed_official	146:f64d43ff0c18	1601	/*!
mbed_official	146:f64d43ff0c18	1602	* @name Register FTM_SYNC, field TRIG1[5] (RW)
mbed_official	146:f64d43ff0c18	1603	*
mbed_official	146:f64d43ff0c18	1604	* Enables hardware trigger 1 to the PWM synchronization. Hardware trigger 1
mbed_official	146:f64d43ff0c18	1605	* happens when a rising edge is detected at the trigger 1 input signal.
mbed_official	146:f64d43ff0c18	1606	*
mbed_official	146:f64d43ff0c18	1607	* Values:
mbed_official	146:f64d43ff0c18	1608	* - 0 - Trigger is disabled.
mbed_official	146:f64d43ff0c18	1609	* - 1 - Trigger is enabled.
mbed_official	146:f64d43ff0c18	1610	*/
mbed_official	146:f64d43ff0c18	1611	//@{
mbed_official	146:f64d43ff0c18	1612	#define BP_FTM_SYNC_TRIG1 (5U) //!< Bit position for FTM_SYNC_TRIG1.
mbed_official	146:f64d43ff0c18	1613	#define BM_FTM_SYNC_TRIG1 (0x00000020U) //!< Bit mask for FTM_SYNC_TRIG1.
mbed_official	146:f64d43ff0c18	1614	#define BS_FTM_SYNC_TRIG1 (1U) //!< Bit field size in bits for FTM_SYNC_TRIG1.
mbed_official	146:f64d43ff0c18	1615
mbed_official	146:f64d43ff0c18	1616	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1617	//! @brief Read current value of the FTM_SYNC_TRIG1 field.
mbed_official	146:f64d43ff0c18	1618	#define BR_FTM_SYNC_TRIG1(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG1))
mbed_official	146:f64d43ff0c18	1619	#endif
mbed_official	146:f64d43ff0c18	1620
mbed_official	146:f64d43ff0c18	1621	//! @brief Format value for bitfield FTM_SYNC_TRIG1.
mbed_official	146:f64d43ff0c18	1622	#define BF_FTM_SYNC_TRIG1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_TRIG1), uint32_t) & BM_FTM_SYNC_TRIG1)
mbed_official	146:f64d43ff0c18	1623
mbed_official	146:f64d43ff0c18	1624	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1625	//! @brief Set the TRIG1 field to a new value.
mbed_official	146:f64d43ff0c18	1626	#define BW_FTM_SYNC_TRIG1(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG1) = (v))
mbed_official	146:f64d43ff0c18	1627	#endif
mbed_official	146:f64d43ff0c18	1628	//@}
mbed_official	146:f64d43ff0c18	1629
mbed_official	146:f64d43ff0c18	1630	/*!
mbed_official	146:f64d43ff0c18	1631	* @name Register FTM_SYNC, field TRIG2[6] (RW)
mbed_official	146:f64d43ff0c18	1632	*
mbed_official	146:f64d43ff0c18	1633	* Enables hardware trigger 2 to the PWM synchronization. Hardware trigger 2
mbed_official	146:f64d43ff0c18	1634	* happens when a rising edge is detected at the trigger 2 input signal.
mbed_official	146:f64d43ff0c18	1635	*
mbed_official	146:f64d43ff0c18	1636	* Values:
mbed_official	146:f64d43ff0c18	1637	* - 0 - Trigger is disabled.
mbed_official	146:f64d43ff0c18	1638	* - 1 - Trigger is enabled.
mbed_official	146:f64d43ff0c18	1639	*/
mbed_official	146:f64d43ff0c18	1640	//@{
mbed_official	146:f64d43ff0c18	1641	#define BP_FTM_SYNC_TRIG2 (6U) //!< Bit position for FTM_SYNC_TRIG2.
mbed_official	146:f64d43ff0c18	1642	#define BM_FTM_SYNC_TRIG2 (0x00000040U) //!< Bit mask for FTM_SYNC_TRIG2.
mbed_official	146:f64d43ff0c18	1643	#define BS_FTM_SYNC_TRIG2 (1U) //!< Bit field size in bits for FTM_SYNC_TRIG2.
mbed_official	146:f64d43ff0c18	1644
mbed_official	146:f64d43ff0c18	1645	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1646	//! @brief Read current value of the FTM_SYNC_TRIG2 field.
mbed_official	146:f64d43ff0c18	1647	#define BR_FTM_SYNC_TRIG2(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG2))
mbed_official	146:f64d43ff0c18	1648	#endif
mbed_official	146:f64d43ff0c18	1649
mbed_official	146:f64d43ff0c18	1650	//! @brief Format value for bitfield FTM_SYNC_TRIG2.
mbed_official	146:f64d43ff0c18	1651	#define BF_FTM_SYNC_TRIG2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_TRIG2), uint32_t) & BM_FTM_SYNC_TRIG2)
mbed_official	146:f64d43ff0c18	1652
mbed_official	146:f64d43ff0c18	1653	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1654	//! @brief Set the TRIG2 field to a new value.
mbed_official	146:f64d43ff0c18	1655	#define BW_FTM_SYNC_TRIG2(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG2) = (v))
mbed_official	146:f64d43ff0c18	1656	#endif
mbed_official	146:f64d43ff0c18	1657	//@}
mbed_official	146:f64d43ff0c18	1658
mbed_official	146:f64d43ff0c18	1659	/*!
mbed_official	146:f64d43ff0c18	1660	* @name Register FTM_SYNC, field SWSYNC[7] (RW)
mbed_official	146:f64d43ff0c18	1661	*
mbed_official	146:f64d43ff0c18	1662	* Selects the software trigger as the PWM synchronization trigger. The software
mbed_official	146:f64d43ff0c18	1663	* trigger happens when a 1 is written to SWSYNC bit.
mbed_official	146:f64d43ff0c18	1664	*
mbed_official	146:f64d43ff0c18	1665	* Values:
mbed_official	146:f64d43ff0c18	1666	* - 0 - Software trigger is not selected.
mbed_official	146:f64d43ff0c18	1667	* - 1 - Software trigger is selected.
mbed_official	146:f64d43ff0c18	1668	*/
mbed_official	146:f64d43ff0c18	1669	//@{
mbed_official	146:f64d43ff0c18	1670	#define BP_FTM_SYNC_SWSYNC (7U) //!< Bit position for FTM_SYNC_SWSYNC.
mbed_official	146:f64d43ff0c18	1671	#define BM_FTM_SYNC_SWSYNC (0x00000080U) //!< Bit mask for FTM_SYNC_SWSYNC.
mbed_official	146:f64d43ff0c18	1672	#define BS_FTM_SYNC_SWSYNC (1U) //!< Bit field size in bits for FTM_SYNC_SWSYNC.
mbed_official	146:f64d43ff0c18	1673
mbed_official	146:f64d43ff0c18	1674	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1675	//! @brief Read current value of the FTM_SYNC_SWSYNC field.
mbed_official	146:f64d43ff0c18	1676	#define BR_FTM_SYNC_SWSYNC(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SWSYNC))
mbed_official	146:f64d43ff0c18	1677	#endif
mbed_official	146:f64d43ff0c18	1678
mbed_official	146:f64d43ff0c18	1679	//! @brief Format value for bitfield FTM_SYNC_SWSYNC.
mbed_official	146:f64d43ff0c18	1680	#define BF_FTM_SYNC_SWSYNC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_SWSYNC), uint32_t) & BM_FTM_SYNC_SWSYNC)
mbed_official	146:f64d43ff0c18	1681
mbed_official	146:f64d43ff0c18	1682	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1683	//! @brief Set the SWSYNC field to a new value.
mbed_official	146:f64d43ff0c18	1684	#define BW_FTM_SYNC_SWSYNC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SWSYNC) = (v))
mbed_official	146:f64d43ff0c18	1685	#endif
mbed_official	146:f64d43ff0c18	1686	//@}
mbed_official	146:f64d43ff0c18	1687
mbed_official	146:f64d43ff0c18	1688	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1689	// HW_FTM_OUTINIT - Initial State For Channels Output
mbed_official	146:f64d43ff0c18	1690	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1691
mbed_official	146:f64d43ff0c18	1692	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1693	/*!
mbed_official	146:f64d43ff0c18	1694	* @brief HW_FTM_OUTINIT - Initial State For Channels Output (RW)
mbed_official	146:f64d43ff0c18	1695	*
mbed_official	146:f64d43ff0c18	1696	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	1697	*/
mbed_official	146:f64d43ff0c18	1698	typedef union _hw_ftm_outinit
mbed_official	146:f64d43ff0c18	1699	{
mbed_official	146:f64d43ff0c18	1700	uint32_t U;
mbed_official	146:f64d43ff0c18	1701	struct _hw_ftm_outinit_bitfields
mbed_official	146:f64d43ff0c18	1702	{
mbed_official	146:f64d43ff0c18	1703	uint32_t CH0OI : 1; //!< [0] Channel 0 Output Initialization Value
mbed_official	146:f64d43ff0c18	1704	uint32_t CH1OI : 1; //!< [1] Channel 1 Output Initialization Value
mbed_official	146:f64d43ff0c18	1705	uint32_t CH2OI : 1; //!< [2] Channel 2 Output Initialization Value
mbed_official	146:f64d43ff0c18	1706	uint32_t CH3OI : 1; //!< [3] Channel 3 Output Initialization Value
mbed_official	146:f64d43ff0c18	1707	uint32_t CH4OI : 1; //!< [4] Channel 4 Output Initialization Value
mbed_official	146:f64d43ff0c18	1708	uint32_t CH5OI : 1; //!< [5] Channel 5 Output Initialization Value
mbed_official	146:f64d43ff0c18	1709	uint32_t CH6OI : 1; //!< [6] Channel 6 Output Initialization Value
mbed_official	146:f64d43ff0c18	1710	uint32_t CH7OI : 1; //!< [7] Channel 7 Output Initialization Value
mbed_official	146:f64d43ff0c18	1711	uint32_t RESERVED0 : 24; //!< [31:8]
mbed_official	146:f64d43ff0c18	1712	} B;
mbed_official	146:f64d43ff0c18	1713	} hw_ftm_outinit_t;
mbed_official	146:f64d43ff0c18	1714	#endif
mbed_official	146:f64d43ff0c18	1715
mbed_official	146:f64d43ff0c18	1716	/*!
mbed_official	146:f64d43ff0c18	1717	* @name Constants and macros for entire FTM_OUTINIT register
mbed_official	146:f64d43ff0c18	1718	*/
mbed_official	146:f64d43ff0c18	1719	//@{
mbed_official	146:f64d43ff0c18	1720	#define HW_FTM_OUTINIT_ADDR(x) (REGS_FTM_BASE(x) + 0x5CU)
mbed_official	146:f64d43ff0c18	1721
mbed_official	146:f64d43ff0c18	1722	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1723	#define HW_FTM_OUTINIT(x) ((__IO hw_ftm_outinit_t ) HW_FTM_OUTINIT_ADDR(x))
mbed_official	146:f64d43ff0c18	1724	#define HW_FTM_OUTINIT_RD(x) (HW_FTM_OUTINIT(x).U)
mbed_official	146:f64d43ff0c18	1725	#define HW_FTM_OUTINIT_WR(x, v) (HW_FTM_OUTINIT(x).U = (v))
mbed_official	146:f64d43ff0c18	1726	#define HW_FTM_OUTINIT_SET(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	1727	#define HW_FTM_OUTINIT_CLR(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	1728	#define HW_FTM_OUTINIT_TOG(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	1729	#endif
mbed_official	146:f64d43ff0c18	1730	//@}
mbed_official	146:f64d43ff0c18	1731
mbed_official	146:f64d43ff0c18	1732	/*
mbed_official	146:f64d43ff0c18	1733	* Constants & macros for individual FTM_OUTINIT bitfields
mbed_official	146:f64d43ff0c18	1734	*/
mbed_official	146:f64d43ff0c18	1735
mbed_official	146:f64d43ff0c18	1736	/*!
mbed_official	146:f64d43ff0c18	1737	* @name Register FTM_OUTINIT, field CH0OI[0] (RW)
mbed_official	146:f64d43ff0c18	1738	*
mbed_official	146:f64d43ff0c18	1739	* Selects the value that is forced into the channel output when the
mbed_official	146:f64d43ff0c18	1740	* initialization occurs.
mbed_official	146:f64d43ff0c18	1741	*
mbed_official	146:f64d43ff0c18	1742	* Values:
mbed_official	146:f64d43ff0c18	1743	* - 0 - The initialization value is 0.
mbed_official	146:f64d43ff0c18	1744	* - 1 - The initialization value is 1.
mbed_official	146:f64d43ff0c18	1745	*/
mbed_official	146:f64d43ff0c18	1746	//@{
mbed_official	146:f64d43ff0c18	1747	#define BP_FTM_OUTINIT_CH0OI (0U) //!< Bit position for FTM_OUTINIT_CH0OI.
mbed_official	146:f64d43ff0c18	1748	#define BM_FTM_OUTINIT_CH0OI (0x00000001U) //!< Bit mask for FTM_OUTINIT_CH0OI.
mbed_official	146:f64d43ff0c18	1749	#define BS_FTM_OUTINIT_CH0OI (1U) //!< Bit field size in bits for FTM_OUTINIT_CH0OI.
mbed_official	146:f64d43ff0c18	1750
mbed_official	146:f64d43ff0c18	1751	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1752	//! @brief Read current value of the FTM_OUTINIT_CH0OI field.
mbed_official	146:f64d43ff0c18	1753	#define BR_FTM_OUTINIT_CH0OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH0OI))
mbed_official	146:f64d43ff0c18	1754	#endif
mbed_official	146:f64d43ff0c18	1755
mbed_official	146:f64d43ff0c18	1756	//! @brief Format value for bitfield FTM_OUTINIT_CH0OI.
mbed_official	146:f64d43ff0c18	1757	#define BF_FTM_OUTINIT_CH0OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH0OI), uint32_t) & BM_FTM_OUTINIT_CH0OI)
mbed_official	146:f64d43ff0c18	1758
mbed_official	146:f64d43ff0c18	1759	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1760	//! @brief Set the CH0OI field to a new value.
mbed_official	146:f64d43ff0c18	1761	#define BW_FTM_OUTINIT_CH0OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH0OI) = (v))
mbed_official	146:f64d43ff0c18	1762	#endif
mbed_official	146:f64d43ff0c18	1763	//@}
mbed_official	146:f64d43ff0c18	1764
mbed_official	146:f64d43ff0c18	1765	/*!
mbed_official	146:f64d43ff0c18	1766	* @name Register FTM_OUTINIT, field CH1OI[1] (RW)
mbed_official	146:f64d43ff0c18	1767	*
mbed_official	146:f64d43ff0c18	1768	* Selects the value that is forced into the channel output when the
mbed_official	146:f64d43ff0c18	1769	* initialization occurs.
mbed_official	146:f64d43ff0c18	1770	*
mbed_official	146:f64d43ff0c18	1771	* Values:
mbed_official	146:f64d43ff0c18	1772	* - 0 - The initialization value is 0.
mbed_official	146:f64d43ff0c18	1773	* - 1 - The initialization value is 1.
mbed_official	146:f64d43ff0c18	1774	*/
mbed_official	146:f64d43ff0c18	1775	//@{
mbed_official	146:f64d43ff0c18	1776	#define BP_FTM_OUTINIT_CH1OI (1U) //!< Bit position for FTM_OUTINIT_CH1OI.
mbed_official	146:f64d43ff0c18	1777	#define BM_FTM_OUTINIT_CH1OI (0x00000002U) //!< Bit mask for FTM_OUTINIT_CH1OI.
mbed_official	146:f64d43ff0c18	1778	#define BS_FTM_OUTINIT_CH1OI (1U) //!< Bit field size in bits for FTM_OUTINIT_CH1OI.
mbed_official	146:f64d43ff0c18	1779
mbed_official	146:f64d43ff0c18	1780	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1781	//! @brief Read current value of the FTM_OUTINIT_CH1OI field.
mbed_official	146:f64d43ff0c18	1782	#define BR_FTM_OUTINIT_CH1OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH1OI))
mbed_official	146:f64d43ff0c18	1783	#endif
mbed_official	146:f64d43ff0c18	1784
mbed_official	146:f64d43ff0c18	1785	//! @brief Format value for bitfield FTM_OUTINIT_CH1OI.
mbed_official	146:f64d43ff0c18	1786	#define BF_FTM_OUTINIT_CH1OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH1OI), uint32_t) & BM_FTM_OUTINIT_CH1OI)
mbed_official	146:f64d43ff0c18	1787
mbed_official	146:f64d43ff0c18	1788	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1789	//! @brief Set the CH1OI field to a new value.
mbed_official	146:f64d43ff0c18	1790	#define BW_FTM_OUTINIT_CH1OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH1OI) = (v))
mbed_official	146:f64d43ff0c18	1791	#endif
mbed_official	146:f64d43ff0c18	1792	//@}
mbed_official	146:f64d43ff0c18	1793
mbed_official	146:f64d43ff0c18	1794	/*!
mbed_official	146:f64d43ff0c18	1795	* @name Register FTM_OUTINIT, field CH2OI[2] (RW)
mbed_official	146:f64d43ff0c18	1796	*
mbed_official	146:f64d43ff0c18	1797	* Selects the value that is forced into the channel output when the
mbed_official	146:f64d43ff0c18	1798	* initialization occurs.
mbed_official	146:f64d43ff0c18	1799	*
mbed_official	146:f64d43ff0c18	1800	* Values:
mbed_official	146:f64d43ff0c18	1801	* - 0 - The initialization value is 0.
mbed_official	146:f64d43ff0c18	1802	* - 1 - The initialization value is 1.
mbed_official	146:f64d43ff0c18	1803	*/
mbed_official	146:f64d43ff0c18	1804	//@{
mbed_official	146:f64d43ff0c18	1805	#define BP_FTM_OUTINIT_CH2OI (2U) //!< Bit position for FTM_OUTINIT_CH2OI.
mbed_official	146:f64d43ff0c18	1806	#define BM_FTM_OUTINIT_CH2OI (0x00000004U) //!< Bit mask for FTM_OUTINIT_CH2OI.
mbed_official	146:f64d43ff0c18	1807	#define BS_FTM_OUTINIT_CH2OI (1U) //!< Bit field size in bits for FTM_OUTINIT_CH2OI.
mbed_official	146:f64d43ff0c18	1808
mbed_official	146:f64d43ff0c18	1809	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1810	//! @brief Read current value of the FTM_OUTINIT_CH2OI field.
mbed_official	146:f64d43ff0c18	1811	#define BR_FTM_OUTINIT_CH2OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH2OI))
mbed_official	146:f64d43ff0c18	1812	#endif
mbed_official	146:f64d43ff0c18	1813
mbed_official	146:f64d43ff0c18	1814	//! @brief Format value for bitfield FTM_OUTINIT_CH2OI.
mbed_official	146:f64d43ff0c18	1815	#define BF_FTM_OUTINIT_CH2OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH2OI), uint32_t) & BM_FTM_OUTINIT_CH2OI)
mbed_official	146:f64d43ff0c18	1816
mbed_official	146:f64d43ff0c18	1817	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1818	//! @brief Set the CH2OI field to a new value.
mbed_official	146:f64d43ff0c18	1819	#define BW_FTM_OUTINIT_CH2OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH2OI) = (v))
mbed_official	146:f64d43ff0c18	1820	#endif
mbed_official	146:f64d43ff0c18	1821	//@}
mbed_official	146:f64d43ff0c18	1822
mbed_official	146:f64d43ff0c18	1823	/*!
mbed_official	146:f64d43ff0c18	1824	* @name Register FTM_OUTINIT, field CH3OI[3] (RW)
mbed_official	146:f64d43ff0c18	1825	*
mbed_official	146:f64d43ff0c18	1826	* Selects the value that is forced into the channel output when the
mbed_official	146:f64d43ff0c18	1827	* initialization occurs.
mbed_official	146:f64d43ff0c18	1828	*
mbed_official	146:f64d43ff0c18	1829	* Values:
mbed_official	146:f64d43ff0c18	1830	* - 0 - The initialization value is 0.
mbed_official	146:f64d43ff0c18	1831	* - 1 - The initialization value is 1.
mbed_official	146:f64d43ff0c18	1832	*/
mbed_official	146:f64d43ff0c18	1833	//@{
mbed_official	146:f64d43ff0c18	1834	#define BP_FTM_OUTINIT_CH3OI (3U) //!< Bit position for FTM_OUTINIT_CH3OI.
mbed_official	146:f64d43ff0c18	1835	#define BM_FTM_OUTINIT_CH3OI (0x00000008U) //!< Bit mask for FTM_OUTINIT_CH3OI.
mbed_official	146:f64d43ff0c18	1836	#define BS_FTM_OUTINIT_CH3OI (1U) //!< Bit field size in bits for FTM_OUTINIT_CH3OI.
mbed_official	146:f64d43ff0c18	1837
mbed_official	146:f64d43ff0c18	1838	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1839	//! @brief Read current value of the FTM_OUTINIT_CH3OI field.
mbed_official	146:f64d43ff0c18	1840	#define BR_FTM_OUTINIT_CH3OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH3OI))
mbed_official	146:f64d43ff0c18	1841	#endif
mbed_official	146:f64d43ff0c18	1842
mbed_official	146:f64d43ff0c18	1843	//! @brief Format value for bitfield FTM_OUTINIT_CH3OI.
mbed_official	146:f64d43ff0c18	1844	#define BF_FTM_OUTINIT_CH3OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH3OI), uint32_t) & BM_FTM_OUTINIT_CH3OI)
mbed_official	146:f64d43ff0c18	1845
mbed_official	146:f64d43ff0c18	1846	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1847	//! @brief Set the CH3OI field to a new value.
mbed_official	146:f64d43ff0c18	1848	#define BW_FTM_OUTINIT_CH3OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH3OI) = (v))
mbed_official	146:f64d43ff0c18	1849	#endif
mbed_official	146:f64d43ff0c18	1850	//@}
mbed_official	146:f64d43ff0c18	1851
mbed_official	146:f64d43ff0c18	1852	/*!
mbed_official	146:f64d43ff0c18	1853	* @name Register FTM_OUTINIT, field CH4OI[4] (RW)
mbed_official	146:f64d43ff0c18	1854	*
mbed_official	146:f64d43ff0c18	1855	* Selects the value that is forced into the channel output when the
mbed_official	146:f64d43ff0c18	1856	* initialization occurs.
mbed_official	146:f64d43ff0c18	1857	*
mbed_official	146:f64d43ff0c18	1858	* Values:
mbed_official	146:f64d43ff0c18	1859	* - 0 - The initialization value is 0.
mbed_official	146:f64d43ff0c18	1860	* - 1 - The initialization value is 1.
mbed_official	146:f64d43ff0c18	1861	*/
mbed_official	146:f64d43ff0c18	1862	//@{
mbed_official	146:f64d43ff0c18	1863	#define BP_FTM_OUTINIT_CH4OI (4U) //!< Bit position for FTM_OUTINIT_CH4OI.
mbed_official	146:f64d43ff0c18	1864	#define BM_FTM_OUTINIT_CH4OI (0x00000010U) //!< Bit mask for FTM_OUTINIT_CH4OI.
mbed_official	146:f64d43ff0c18	1865	#define BS_FTM_OUTINIT_CH4OI (1U) //!< Bit field size in bits for FTM_OUTINIT_CH4OI.
mbed_official	146:f64d43ff0c18	1866
mbed_official	146:f64d43ff0c18	1867	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1868	//! @brief Read current value of the FTM_OUTINIT_CH4OI field.
mbed_official	146:f64d43ff0c18	1869	#define BR_FTM_OUTINIT_CH4OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH4OI))
mbed_official	146:f64d43ff0c18	1870	#endif
mbed_official	146:f64d43ff0c18	1871
mbed_official	146:f64d43ff0c18	1872	//! @brief Format value for bitfield FTM_OUTINIT_CH4OI.
mbed_official	146:f64d43ff0c18	1873	#define BF_FTM_OUTINIT_CH4OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH4OI), uint32_t) & BM_FTM_OUTINIT_CH4OI)
mbed_official	146:f64d43ff0c18	1874
mbed_official	146:f64d43ff0c18	1875	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1876	//! @brief Set the CH4OI field to a new value.
mbed_official	146:f64d43ff0c18	1877	#define BW_FTM_OUTINIT_CH4OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH4OI) = (v))
mbed_official	146:f64d43ff0c18	1878	#endif
mbed_official	146:f64d43ff0c18	1879	//@}
mbed_official	146:f64d43ff0c18	1880
mbed_official	146:f64d43ff0c18	1881	/*!
mbed_official	146:f64d43ff0c18	1882	* @name Register FTM_OUTINIT, field CH5OI[5] (RW)
mbed_official	146:f64d43ff0c18	1883	*
mbed_official	146:f64d43ff0c18	1884	* Selects the value that is forced into the channel output when the
mbed_official	146:f64d43ff0c18	1885	* initialization occurs.
mbed_official	146:f64d43ff0c18	1886	*
mbed_official	146:f64d43ff0c18	1887	* Values:
mbed_official	146:f64d43ff0c18	1888	* - 0 - The initialization value is 0.
mbed_official	146:f64d43ff0c18	1889	* - 1 - The initialization value is 1.
mbed_official	146:f64d43ff0c18	1890	*/
mbed_official	146:f64d43ff0c18	1891	//@{
mbed_official	146:f64d43ff0c18	1892	#define BP_FTM_OUTINIT_CH5OI (5U) //!< Bit position for FTM_OUTINIT_CH5OI.
mbed_official	146:f64d43ff0c18	1893	#define BM_FTM_OUTINIT_CH5OI (0x00000020U) //!< Bit mask for FTM_OUTINIT_CH5OI.
mbed_official	146:f64d43ff0c18	1894	#define BS_FTM_OUTINIT_CH5OI (1U) //!< Bit field size in bits for FTM_OUTINIT_CH5OI.
mbed_official	146:f64d43ff0c18	1895
mbed_official	146:f64d43ff0c18	1896	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1897	//! @brief Read current value of the FTM_OUTINIT_CH5OI field.
mbed_official	146:f64d43ff0c18	1898	#define BR_FTM_OUTINIT_CH5OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH5OI))
mbed_official	146:f64d43ff0c18	1899	#endif
mbed_official	146:f64d43ff0c18	1900
mbed_official	146:f64d43ff0c18	1901	//! @brief Format value for bitfield FTM_OUTINIT_CH5OI.
mbed_official	146:f64d43ff0c18	1902	#define BF_FTM_OUTINIT_CH5OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH5OI), uint32_t) & BM_FTM_OUTINIT_CH5OI)
mbed_official	146:f64d43ff0c18	1903
mbed_official	146:f64d43ff0c18	1904	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1905	//! @brief Set the CH5OI field to a new value.
mbed_official	146:f64d43ff0c18	1906	#define BW_FTM_OUTINIT_CH5OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH5OI) = (v))
mbed_official	146:f64d43ff0c18	1907	#endif
mbed_official	146:f64d43ff0c18	1908	//@}
mbed_official	146:f64d43ff0c18	1909
mbed_official	146:f64d43ff0c18	1910	/*!
mbed_official	146:f64d43ff0c18	1911	* @name Register FTM_OUTINIT, field CH6OI[6] (RW)
mbed_official	146:f64d43ff0c18	1912	*
mbed_official	146:f64d43ff0c18	1913	* Selects the value that is forced into the channel output when the
mbed_official	146:f64d43ff0c18	1914	* initialization occurs.
mbed_official	146:f64d43ff0c18	1915	*
mbed_official	146:f64d43ff0c18	1916	* Values:
mbed_official	146:f64d43ff0c18	1917	* - 0 - The initialization value is 0.
mbed_official	146:f64d43ff0c18	1918	* - 1 - The initialization value is 1.
mbed_official	146:f64d43ff0c18	1919	*/
mbed_official	146:f64d43ff0c18	1920	//@{
mbed_official	146:f64d43ff0c18	1921	#define BP_FTM_OUTINIT_CH6OI (6U) //!< Bit position for FTM_OUTINIT_CH6OI.
mbed_official	146:f64d43ff0c18	1922	#define BM_FTM_OUTINIT_CH6OI (0x00000040U) //!< Bit mask for FTM_OUTINIT_CH6OI.
mbed_official	146:f64d43ff0c18	1923	#define BS_FTM_OUTINIT_CH6OI (1U) //!< Bit field size in bits for FTM_OUTINIT_CH6OI.
mbed_official	146:f64d43ff0c18	1924
mbed_official	146:f64d43ff0c18	1925	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1926	//! @brief Read current value of the FTM_OUTINIT_CH6OI field.
mbed_official	146:f64d43ff0c18	1927	#define BR_FTM_OUTINIT_CH6OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH6OI))
mbed_official	146:f64d43ff0c18	1928	#endif
mbed_official	146:f64d43ff0c18	1929
mbed_official	146:f64d43ff0c18	1930	//! @brief Format value for bitfield FTM_OUTINIT_CH6OI.
mbed_official	146:f64d43ff0c18	1931	#define BF_FTM_OUTINIT_CH6OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH6OI), uint32_t) & BM_FTM_OUTINIT_CH6OI)
mbed_official	146:f64d43ff0c18	1932
mbed_official	146:f64d43ff0c18	1933	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1934	//! @brief Set the CH6OI field to a new value.
mbed_official	146:f64d43ff0c18	1935	#define BW_FTM_OUTINIT_CH6OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH6OI) = (v))
mbed_official	146:f64d43ff0c18	1936	#endif
mbed_official	146:f64d43ff0c18	1937	//@}
mbed_official	146:f64d43ff0c18	1938
mbed_official	146:f64d43ff0c18	1939	/*!
mbed_official	146:f64d43ff0c18	1940	* @name Register FTM_OUTINIT, field CH7OI[7] (RW)
mbed_official	146:f64d43ff0c18	1941	*
mbed_official	146:f64d43ff0c18	1942	* Selects the value that is forced into the channel output when the
mbed_official	146:f64d43ff0c18	1943	* initialization occurs.
mbed_official	146:f64d43ff0c18	1944	*
mbed_official	146:f64d43ff0c18	1945	* Values:
mbed_official	146:f64d43ff0c18	1946	* - 0 - The initialization value is 0.
mbed_official	146:f64d43ff0c18	1947	* - 1 - The initialization value is 1.
mbed_official	146:f64d43ff0c18	1948	*/
mbed_official	146:f64d43ff0c18	1949	//@{
mbed_official	146:f64d43ff0c18	1950	#define BP_FTM_OUTINIT_CH7OI (7U) //!< Bit position for FTM_OUTINIT_CH7OI.
mbed_official	146:f64d43ff0c18	1951	#define BM_FTM_OUTINIT_CH7OI (0x00000080U) //!< Bit mask for FTM_OUTINIT_CH7OI.
mbed_official	146:f64d43ff0c18	1952	#define BS_FTM_OUTINIT_CH7OI (1U) //!< Bit field size in bits for FTM_OUTINIT_CH7OI.
mbed_official	146:f64d43ff0c18	1953
mbed_official	146:f64d43ff0c18	1954	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1955	//! @brief Read current value of the FTM_OUTINIT_CH7OI field.
mbed_official	146:f64d43ff0c18	1956	#define BR_FTM_OUTINIT_CH7OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH7OI))
mbed_official	146:f64d43ff0c18	1957	#endif
mbed_official	146:f64d43ff0c18	1958
mbed_official	146:f64d43ff0c18	1959	//! @brief Format value for bitfield FTM_OUTINIT_CH7OI.
mbed_official	146:f64d43ff0c18	1960	#define BF_FTM_OUTINIT_CH7OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH7OI), uint32_t) & BM_FTM_OUTINIT_CH7OI)
mbed_official	146:f64d43ff0c18	1961
mbed_official	146:f64d43ff0c18	1962	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1963	//! @brief Set the CH7OI field to a new value.
mbed_official	146:f64d43ff0c18	1964	#define BW_FTM_OUTINIT_CH7OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH7OI) = (v))
mbed_official	146:f64d43ff0c18	1965	#endif
mbed_official	146:f64d43ff0c18	1966	//@}
mbed_official	146:f64d43ff0c18	1967
mbed_official	146:f64d43ff0c18	1968	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1969	// HW_FTM_OUTMASK - Output Mask
mbed_official	146:f64d43ff0c18	1970	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1971
mbed_official	146:f64d43ff0c18	1972	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1973	/*!
mbed_official	146:f64d43ff0c18	1974	* @brief HW_FTM_OUTMASK - Output Mask (RW)
mbed_official	146:f64d43ff0c18	1975	*
mbed_official	146:f64d43ff0c18	1976	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	1977	*
mbed_official	146:f64d43ff0c18	1978	* This register provides a mask for each FTM channel. The mask of a channel
mbed_official	146:f64d43ff0c18	1979	* determines if its output responds, that is, it is masked or not, when a match
mbed_official	146:f64d43ff0c18	1980	* occurs. This feature is used for BLDC control where the PWM signal is presented
mbed_official	146:f64d43ff0c18	1981	* to an electric motor at specific times to provide electronic commutation. Any
mbed_official	146:f64d43ff0c18	1982	* write to the OUTMASK register, stores the value in its write buffer. The
mbed_official	146:f64d43ff0c18	1983	* register is updated with the value of its write buffer according to PWM
mbed_official	146:f64d43ff0c18	1984	* synchronization.
mbed_official	146:f64d43ff0c18	1985	*/
mbed_official	146:f64d43ff0c18	1986	typedef union _hw_ftm_outmask
mbed_official	146:f64d43ff0c18	1987	{
mbed_official	146:f64d43ff0c18	1988	uint32_t U;
mbed_official	146:f64d43ff0c18	1989	struct _hw_ftm_outmask_bitfields
mbed_official	146:f64d43ff0c18	1990	{
mbed_official	146:f64d43ff0c18	1991	uint32_t CH0OM : 1; //!< [0] Channel 0 Output Mask
mbed_official	146:f64d43ff0c18	1992	uint32_t CH1OM : 1; //!< [1] Channel 1 Output Mask
mbed_official	146:f64d43ff0c18	1993	uint32_t CH2OM : 1; //!< [2] Channel 2 Output Mask
mbed_official	146:f64d43ff0c18	1994	uint32_t CH3OM : 1; //!< [3] Channel 3 Output Mask
mbed_official	146:f64d43ff0c18	1995	uint32_t CH4OM : 1; //!< [4] Channel 4 Output Mask
mbed_official	146:f64d43ff0c18	1996	uint32_t CH5OM : 1; //!< [5] Channel 5 Output Mask
mbed_official	146:f64d43ff0c18	1997	uint32_t CH6OM : 1; //!< [6] Channel 6 Output Mask
mbed_official	146:f64d43ff0c18	1998	uint32_t CH7OM : 1; //!< [7] Channel 7 Output Mask
mbed_official	146:f64d43ff0c18	1999	uint32_t RESERVED0 : 24; //!< [31:8]
mbed_official	146:f64d43ff0c18	2000	} B;
mbed_official	146:f64d43ff0c18	2001	} hw_ftm_outmask_t;
mbed_official	146:f64d43ff0c18	2002	#endif
mbed_official	146:f64d43ff0c18	2003
mbed_official	146:f64d43ff0c18	2004	/*!
mbed_official	146:f64d43ff0c18	2005	* @name Constants and macros for entire FTM_OUTMASK register
mbed_official	146:f64d43ff0c18	2006	*/
mbed_official	146:f64d43ff0c18	2007	//@{
mbed_official	146:f64d43ff0c18	2008	#define HW_FTM_OUTMASK_ADDR(x) (REGS_FTM_BASE(x) + 0x60U)
mbed_official	146:f64d43ff0c18	2009
mbed_official	146:f64d43ff0c18	2010	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2011	#define HW_FTM_OUTMASK(x) ((__IO hw_ftm_outmask_t ) HW_FTM_OUTMASK_ADDR(x))
mbed_official	146:f64d43ff0c18	2012	#define HW_FTM_OUTMASK_RD(x) (HW_FTM_OUTMASK(x).U)
mbed_official	146:f64d43ff0c18	2013	#define HW_FTM_OUTMASK_WR(x, v) (HW_FTM_OUTMASK(x).U = (v))
mbed_official	146:f64d43ff0c18	2014	#define HW_FTM_OUTMASK_SET(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	2015	#define HW_FTM_OUTMASK_CLR(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	2016	#define HW_FTM_OUTMASK_TOG(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	2017	#endif
mbed_official	146:f64d43ff0c18	2018	//@}
mbed_official	146:f64d43ff0c18	2019
mbed_official	146:f64d43ff0c18	2020	/*
mbed_official	146:f64d43ff0c18	2021	* Constants & macros for individual FTM_OUTMASK bitfields
mbed_official	146:f64d43ff0c18	2022	*/
mbed_official	146:f64d43ff0c18	2023
mbed_official	146:f64d43ff0c18	2024	/*!
mbed_official	146:f64d43ff0c18	2025	* @name Register FTM_OUTMASK, field CH0OM[0] (RW)
mbed_official	146:f64d43ff0c18	2026	*
mbed_official	146:f64d43ff0c18	2027	* Defines if the channel output is masked or unmasked.
mbed_official	146:f64d43ff0c18	2028	*
mbed_official	146:f64d43ff0c18	2029	* Values:
mbed_official	146:f64d43ff0c18	2030	* - 0 - Channel output is not masked. It continues to operate normally.
mbed_official	146:f64d43ff0c18	2031	* - 1 - Channel output is masked. It is forced to its inactive state.
mbed_official	146:f64d43ff0c18	2032	*/
mbed_official	146:f64d43ff0c18	2033	//@{
mbed_official	146:f64d43ff0c18	2034	#define BP_FTM_OUTMASK_CH0OM (0U) //!< Bit position for FTM_OUTMASK_CH0OM.
mbed_official	146:f64d43ff0c18	2035	#define BM_FTM_OUTMASK_CH0OM (0x00000001U) //!< Bit mask for FTM_OUTMASK_CH0OM.
mbed_official	146:f64d43ff0c18	2036	#define BS_FTM_OUTMASK_CH0OM (1U) //!< Bit field size in bits for FTM_OUTMASK_CH0OM.
mbed_official	146:f64d43ff0c18	2037
mbed_official	146:f64d43ff0c18	2038	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2039	//! @brief Read current value of the FTM_OUTMASK_CH0OM field.
mbed_official	146:f64d43ff0c18	2040	#define BR_FTM_OUTMASK_CH0OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH0OM))
mbed_official	146:f64d43ff0c18	2041	#endif
mbed_official	146:f64d43ff0c18	2042
mbed_official	146:f64d43ff0c18	2043	//! @brief Format value for bitfield FTM_OUTMASK_CH0OM.
mbed_official	146:f64d43ff0c18	2044	#define BF_FTM_OUTMASK_CH0OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH0OM), uint32_t) & BM_FTM_OUTMASK_CH0OM)
mbed_official	146:f64d43ff0c18	2045
mbed_official	146:f64d43ff0c18	2046	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2047	//! @brief Set the CH0OM field to a new value.
mbed_official	146:f64d43ff0c18	2048	#define BW_FTM_OUTMASK_CH0OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH0OM) = (v))
mbed_official	146:f64d43ff0c18	2049	#endif
mbed_official	146:f64d43ff0c18	2050	//@}
mbed_official	146:f64d43ff0c18	2051
mbed_official	146:f64d43ff0c18	2052	/*!
mbed_official	146:f64d43ff0c18	2053	* @name Register FTM_OUTMASK, field CH1OM[1] (RW)
mbed_official	146:f64d43ff0c18	2054	*
mbed_official	146:f64d43ff0c18	2055	* Defines if the channel output is masked or unmasked.
mbed_official	146:f64d43ff0c18	2056	*
mbed_official	146:f64d43ff0c18	2057	* Values:
mbed_official	146:f64d43ff0c18	2058	* - 0 - Channel output is not masked. It continues to operate normally.
mbed_official	146:f64d43ff0c18	2059	* - 1 - Channel output is masked. It is forced to its inactive state.
mbed_official	146:f64d43ff0c18	2060	*/
mbed_official	146:f64d43ff0c18	2061	//@{
mbed_official	146:f64d43ff0c18	2062	#define BP_FTM_OUTMASK_CH1OM (1U) //!< Bit position for FTM_OUTMASK_CH1OM.
mbed_official	146:f64d43ff0c18	2063	#define BM_FTM_OUTMASK_CH1OM (0x00000002U) //!< Bit mask for FTM_OUTMASK_CH1OM.
mbed_official	146:f64d43ff0c18	2064	#define BS_FTM_OUTMASK_CH1OM (1U) //!< Bit field size in bits for FTM_OUTMASK_CH1OM.
mbed_official	146:f64d43ff0c18	2065
mbed_official	146:f64d43ff0c18	2066	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2067	//! @brief Read current value of the FTM_OUTMASK_CH1OM field.
mbed_official	146:f64d43ff0c18	2068	#define BR_FTM_OUTMASK_CH1OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH1OM))
mbed_official	146:f64d43ff0c18	2069	#endif
mbed_official	146:f64d43ff0c18	2070
mbed_official	146:f64d43ff0c18	2071	//! @brief Format value for bitfield FTM_OUTMASK_CH1OM.
mbed_official	146:f64d43ff0c18	2072	#define BF_FTM_OUTMASK_CH1OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH1OM), uint32_t) & BM_FTM_OUTMASK_CH1OM)
mbed_official	146:f64d43ff0c18	2073
mbed_official	146:f64d43ff0c18	2074	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2075	//! @brief Set the CH1OM field to a new value.
mbed_official	146:f64d43ff0c18	2076	#define BW_FTM_OUTMASK_CH1OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH1OM) = (v))
mbed_official	146:f64d43ff0c18	2077	#endif
mbed_official	146:f64d43ff0c18	2078	//@}
mbed_official	146:f64d43ff0c18	2079
mbed_official	146:f64d43ff0c18	2080	/*!
mbed_official	146:f64d43ff0c18	2081	* @name Register FTM_OUTMASK, field CH2OM[2] (RW)
mbed_official	146:f64d43ff0c18	2082	*
mbed_official	146:f64d43ff0c18	2083	* Defines if the channel output is masked or unmasked.
mbed_official	146:f64d43ff0c18	2084	*
mbed_official	146:f64d43ff0c18	2085	* Values:
mbed_official	146:f64d43ff0c18	2086	* - 0 - Channel output is not masked. It continues to operate normally.
mbed_official	146:f64d43ff0c18	2087	* - 1 - Channel output is masked. It is forced to its inactive state.
mbed_official	146:f64d43ff0c18	2088	*/
mbed_official	146:f64d43ff0c18	2089	//@{
mbed_official	146:f64d43ff0c18	2090	#define BP_FTM_OUTMASK_CH2OM (2U) //!< Bit position for FTM_OUTMASK_CH2OM.
mbed_official	146:f64d43ff0c18	2091	#define BM_FTM_OUTMASK_CH2OM (0x00000004U) //!< Bit mask for FTM_OUTMASK_CH2OM.
mbed_official	146:f64d43ff0c18	2092	#define BS_FTM_OUTMASK_CH2OM (1U) //!< Bit field size in bits for FTM_OUTMASK_CH2OM.
mbed_official	146:f64d43ff0c18	2093
mbed_official	146:f64d43ff0c18	2094	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2095	//! @brief Read current value of the FTM_OUTMASK_CH2OM field.
mbed_official	146:f64d43ff0c18	2096	#define BR_FTM_OUTMASK_CH2OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH2OM))
mbed_official	146:f64d43ff0c18	2097	#endif
mbed_official	146:f64d43ff0c18	2098
mbed_official	146:f64d43ff0c18	2099	//! @brief Format value for bitfield FTM_OUTMASK_CH2OM.
mbed_official	146:f64d43ff0c18	2100	#define BF_FTM_OUTMASK_CH2OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH2OM), uint32_t) & BM_FTM_OUTMASK_CH2OM)
mbed_official	146:f64d43ff0c18	2101
mbed_official	146:f64d43ff0c18	2102	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2103	//! @brief Set the CH2OM field to a new value.
mbed_official	146:f64d43ff0c18	2104	#define BW_FTM_OUTMASK_CH2OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH2OM) = (v))
mbed_official	146:f64d43ff0c18	2105	#endif
mbed_official	146:f64d43ff0c18	2106	//@}
mbed_official	146:f64d43ff0c18	2107
mbed_official	146:f64d43ff0c18	2108	/*!
mbed_official	146:f64d43ff0c18	2109	* @name Register FTM_OUTMASK, field CH3OM[3] (RW)
mbed_official	146:f64d43ff0c18	2110	*
mbed_official	146:f64d43ff0c18	2111	* Defines if the channel output is masked or unmasked.
mbed_official	146:f64d43ff0c18	2112	*
mbed_official	146:f64d43ff0c18	2113	* Values:
mbed_official	146:f64d43ff0c18	2114	* - 0 - Channel output is not masked. It continues to operate normally.
mbed_official	146:f64d43ff0c18	2115	* - 1 - Channel output is masked. It is forced to its inactive state.
mbed_official	146:f64d43ff0c18	2116	*/
mbed_official	146:f64d43ff0c18	2117	//@{
mbed_official	146:f64d43ff0c18	2118	#define BP_FTM_OUTMASK_CH3OM (3U) //!< Bit position for FTM_OUTMASK_CH3OM.
mbed_official	146:f64d43ff0c18	2119	#define BM_FTM_OUTMASK_CH3OM (0x00000008U) //!< Bit mask for FTM_OUTMASK_CH3OM.
mbed_official	146:f64d43ff0c18	2120	#define BS_FTM_OUTMASK_CH3OM (1U) //!< Bit field size in bits for FTM_OUTMASK_CH3OM.
mbed_official	146:f64d43ff0c18	2121
mbed_official	146:f64d43ff0c18	2122	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2123	//! @brief Read current value of the FTM_OUTMASK_CH3OM field.
mbed_official	146:f64d43ff0c18	2124	#define BR_FTM_OUTMASK_CH3OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH3OM))
mbed_official	146:f64d43ff0c18	2125	#endif
mbed_official	146:f64d43ff0c18	2126
mbed_official	146:f64d43ff0c18	2127	//! @brief Format value for bitfield FTM_OUTMASK_CH3OM.
mbed_official	146:f64d43ff0c18	2128	#define BF_FTM_OUTMASK_CH3OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH3OM), uint32_t) & BM_FTM_OUTMASK_CH3OM)
mbed_official	146:f64d43ff0c18	2129
mbed_official	146:f64d43ff0c18	2130	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2131	//! @brief Set the CH3OM field to a new value.
mbed_official	146:f64d43ff0c18	2132	#define BW_FTM_OUTMASK_CH3OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH3OM) = (v))
mbed_official	146:f64d43ff0c18	2133	#endif
mbed_official	146:f64d43ff0c18	2134	//@}
mbed_official	146:f64d43ff0c18	2135
mbed_official	146:f64d43ff0c18	2136	/*!
mbed_official	146:f64d43ff0c18	2137	* @name Register FTM_OUTMASK, field CH4OM[4] (RW)
mbed_official	146:f64d43ff0c18	2138	*
mbed_official	146:f64d43ff0c18	2139	* Defines if the channel output is masked or unmasked.
mbed_official	146:f64d43ff0c18	2140	*
mbed_official	146:f64d43ff0c18	2141	* Values:
mbed_official	146:f64d43ff0c18	2142	* - 0 - Channel output is not masked. It continues to operate normally.
mbed_official	146:f64d43ff0c18	2143	* - 1 - Channel output is masked. It is forced to its inactive state.
mbed_official	146:f64d43ff0c18	2144	*/
mbed_official	146:f64d43ff0c18	2145	//@{
mbed_official	146:f64d43ff0c18	2146	#define BP_FTM_OUTMASK_CH4OM (4U) //!< Bit position for FTM_OUTMASK_CH4OM.
mbed_official	146:f64d43ff0c18	2147	#define BM_FTM_OUTMASK_CH4OM (0x00000010U) //!< Bit mask for FTM_OUTMASK_CH4OM.
mbed_official	146:f64d43ff0c18	2148	#define BS_FTM_OUTMASK_CH4OM (1U) //!< Bit field size in bits for FTM_OUTMASK_CH4OM.
mbed_official	146:f64d43ff0c18	2149
mbed_official	146:f64d43ff0c18	2150	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2151	//! @brief Read current value of the FTM_OUTMASK_CH4OM field.
mbed_official	146:f64d43ff0c18	2152	#define BR_FTM_OUTMASK_CH4OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH4OM))
mbed_official	146:f64d43ff0c18	2153	#endif
mbed_official	146:f64d43ff0c18	2154
mbed_official	146:f64d43ff0c18	2155	//! @brief Format value for bitfield FTM_OUTMASK_CH4OM.
mbed_official	146:f64d43ff0c18	2156	#define BF_FTM_OUTMASK_CH4OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH4OM), uint32_t) & BM_FTM_OUTMASK_CH4OM)
mbed_official	146:f64d43ff0c18	2157
mbed_official	146:f64d43ff0c18	2158	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2159	//! @brief Set the CH4OM field to a new value.
mbed_official	146:f64d43ff0c18	2160	#define BW_FTM_OUTMASK_CH4OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH4OM) = (v))
mbed_official	146:f64d43ff0c18	2161	#endif
mbed_official	146:f64d43ff0c18	2162	//@}
mbed_official	146:f64d43ff0c18	2163
mbed_official	146:f64d43ff0c18	2164	/*!
mbed_official	146:f64d43ff0c18	2165	* @name Register FTM_OUTMASK, field CH5OM[5] (RW)
mbed_official	146:f64d43ff0c18	2166	*
mbed_official	146:f64d43ff0c18	2167	* Defines if the channel output is masked or unmasked.
mbed_official	146:f64d43ff0c18	2168	*
mbed_official	146:f64d43ff0c18	2169	* Values:
mbed_official	146:f64d43ff0c18	2170	* - 0 - Channel output is not masked. It continues to operate normally.
mbed_official	146:f64d43ff0c18	2171	* - 1 - Channel output is masked. It is forced to its inactive state.
mbed_official	146:f64d43ff0c18	2172	*/
mbed_official	146:f64d43ff0c18	2173	//@{
mbed_official	146:f64d43ff0c18	2174	#define BP_FTM_OUTMASK_CH5OM (5U) //!< Bit position for FTM_OUTMASK_CH5OM.
mbed_official	146:f64d43ff0c18	2175	#define BM_FTM_OUTMASK_CH5OM (0x00000020U) //!< Bit mask for FTM_OUTMASK_CH5OM.
mbed_official	146:f64d43ff0c18	2176	#define BS_FTM_OUTMASK_CH5OM (1U) //!< Bit field size in bits for FTM_OUTMASK_CH5OM.
mbed_official	146:f64d43ff0c18	2177
mbed_official	146:f64d43ff0c18	2178	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2179	//! @brief Read current value of the FTM_OUTMASK_CH5OM field.
mbed_official	146:f64d43ff0c18	2180	#define BR_FTM_OUTMASK_CH5OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH5OM))
mbed_official	146:f64d43ff0c18	2181	#endif
mbed_official	146:f64d43ff0c18	2182
mbed_official	146:f64d43ff0c18	2183	//! @brief Format value for bitfield FTM_OUTMASK_CH5OM.
mbed_official	146:f64d43ff0c18	2184	#define BF_FTM_OUTMASK_CH5OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH5OM), uint32_t) & BM_FTM_OUTMASK_CH5OM)
mbed_official	146:f64d43ff0c18	2185
mbed_official	146:f64d43ff0c18	2186	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2187	//! @brief Set the CH5OM field to a new value.
mbed_official	146:f64d43ff0c18	2188	#define BW_FTM_OUTMASK_CH5OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH5OM) = (v))
mbed_official	146:f64d43ff0c18	2189	#endif
mbed_official	146:f64d43ff0c18	2190	//@}
mbed_official	146:f64d43ff0c18	2191
mbed_official	146:f64d43ff0c18	2192	/*!
mbed_official	146:f64d43ff0c18	2193	* @name Register FTM_OUTMASK, field CH6OM[6] (RW)
mbed_official	146:f64d43ff0c18	2194	*
mbed_official	146:f64d43ff0c18	2195	* Defines if the channel output is masked or unmasked.
mbed_official	146:f64d43ff0c18	2196	*
mbed_official	146:f64d43ff0c18	2197	* Values:
mbed_official	146:f64d43ff0c18	2198	* - 0 - Channel output is not masked. It continues to operate normally.
mbed_official	146:f64d43ff0c18	2199	* - 1 - Channel output is masked. It is forced to its inactive state.
mbed_official	146:f64d43ff0c18	2200	*/
mbed_official	146:f64d43ff0c18	2201	//@{
mbed_official	146:f64d43ff0c18	2202	#define BP_FTM_OUTMASK_CH6OM (6U) //!< Bit position for FTM_OUTMASK_CH6OM.
mbed_official	146:f64d43ff0c18	2203	#define BM_FTM_OUTMASK_CH6OM (0x00000040U) //!< Bit mask for FTM_OUTMASK_CH6OM.
mbed_official	146:f64d43ff0c18	2204	#define BS_FTM_OUTMASK_CH6OM (1U) //!< Bit field size in bits for FTM_OUTMASK_CH6OM.
mbed_official	146:f64d43ff0c18	2205
mbed_official	146:f64d43ff0c18	2206	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2207	//! @brief Read current value of the FTM_OUTMASK_CH6OM field.
mbed_official	146:f64d43ff0c18	2208	#define BR_FTM_OUTMASK_CH6OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH6OM))
mbed_official	146:f64d43ff0c18	2209	#endif
mbed_official	146:f64d43ff0c18	2210
mbed_official	146:f64d43ff0c18	2211	//! @brief Format value for bitfield FTM_OUTMASK_CH6OM.
mbed_official	146:f64d43ff0c18	2212	#define BF_FTM_OUTMASK_CH6OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH6OM), uint32_t) & BM_FTM_OUTMASK_CH6OM)
mbed_official	146:f64d43ff0c18	2213
mbed_official	146:f64d43ff0c18	2214	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2215	//! @brief Set the CH6OM field to a new value.
mbed_official	146:f64d43ff0c18	2216	#define BW_FTM_OUTMASK_CH6OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH6OM) = (v))
mbed_official	146:f64d43ff0c18	2217	#endif
mbed_official	146:f64d43ff0c18	2218	//@}
mbed_official	146:f64d43ff0c18	2219
mbed_official	146:f64d43ff0c18	2220	/*!
mbed_official	146:f64d43ff0c18	2221	* @name Register FTM_OUTMASK, field CH7OM[7] (RW)
mbed_official	146:f64d43ff0c18	2222	*
mbed_official	146:f64d43ff0c18	2223	* Defines if the channel output is masked or unmasked.
mbed_official	146:f64d43ff0c18	2224	*
mbed_official	146:f64d43ff0c18	2225	* Values:
mbed_official	146:f64d43ff0c18	2226	* - 0 - Channel output is not masked. It continues to operate normally.
mbed_official	146:f64d43ff0c18	2227	* - 1 - Channel output is masked. It is forced to its inactive state.
mbed_official	146:f64d43ff0c18	2228	*/
mbed_official	146:f64d43ff0c18	2229	//@{
mbed_official	146:f64d43ff0c18	2230	#define BP_FTM_OUTMASK_CH7OM (7U) //!< Bit position for FTM_OUTMASK_CH7OM.
mbed_official	146:f64d43ff0c18	2231	#define BM_FTM_OUTMASK_CH7OM (0x00000080U) //!< Bit mask for FTM_OUTMASK_CH7OM.
mbed_official	146:f64d43ff0c18	2232	#define BS_FTM_OUTMASK_CH7OM (1U) //!< Bit field size in bits for FTM_OUTMASK_CH7OM.
mbed_official	146:f64d43ff0c18	2233
mbed_official	146:f64d43ff0c18	2234	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2235	//! @brief Read current value of the FTM_OUTMASK_CH7OM field.
mbed_official	146:f64d43ff0c18	2236	#define BR_FTM_OUTMASK_CH7OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH7OM))
mbed_official	146:f64d43ff0c18	2237	#endif
mbed_official	146:f64d43ff0c18	2238
mbed_official	146:f64d43ff0c18	2239	//! @brief Format value for bitfield FTM_OUTMASK_CH7OM.
mbed_official	146:f64d43ff0c18	2240	#define BF_FTM_OUTMASK_CH7OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH7OM), uint32_t) & BM_FTM_OUTMASK_CH7OM)
mbed_official	146:f64d43ff0c18	2241
mbed_official	146:f64d43ff0c18	2242	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2243	//! @brief Set the CH7OM field to a new value.
mbed_official	146:f64d43ff0c18	2244	#define BW_FTM_OUTMASK_CH7OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH7OM) = (v))
mbed_official	146:f64d43ff0c18	2245	#endif
mbed_official	146:f64d43ff0c18	2246	//@}
mbed_official	146:f64d43ff0c18	2247
mbed_official	146:f64d43ff0c18	2248	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	2249	// HW_FTM_COMBINE - Function For Linked Channels
mbed_official	146:f64d43ff0c18	2250	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	2251
mbed_official	146:f64d43ff0c18	2252	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2253	/*!
mbed_official	146:f64d43ff0c18	2254	* @brief HW_FTM_COMBINE - Function For Linked Channels (RW)
mbed_official	146:f64d43ff0c18	2255	*
mbed_official	146:f64d43ff0c18	2256	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	2257	*
mbed_official	146:f64d43ff0c18	2258	* This register contains the control bits used to configure the fault control,
mbed_official	146:f64d43ff0c18	2259	* synchronization, deadtime insertion, Dual Edge Capture mode, Complementary,
mbed_official	146:f64d43ff0c18	2260	* and Combine mode for each pair of channels (n) and (n+1), where n equals 0, 2,
mbed_official	146:f64d43ff0c18	2261	* 4, and 6.
mbed_official	146:f64d43ff0c18	2262	*/
mbed_official	146:f64d43ff0c18	2263	typedef union _hw_ftm_combine
mbed_official	146:f64d43ff0c18	2264	{
mbed_official	146:f64d43ff0c18	2265	uint32_t U;
mbed_official	146:f64d43ff0c18	2266	struct _hw_ftm_combine_bitfields
mbed_official	146:f64d43ff0c18	2267	{
mbed_official	146:f64d43ff0c18	2268	uint32_t COMBINE0 : 1; //!< [0] Combine Channels For n = 0
mbed_official	146:f64d43ff0c18	2269	uint32_t COMP0 : 1; //!< [1] Complement Of Channel (n) For n = 0
mbed_official	146:f64d43ff0c18	2270	uint32_t DECAPEN0 : 1; //!< [2] Dual Edge Capture Mode Enable For n =
mbed_official	146:f64d43ff0c18	2271	//! 0
mbed_official	146:f64d43ff0c18	2272	uint32_t DECAP0 : 1; //!< [3] Dual Edge Capture Mode Captures For n =
mbed_official	146:f64d43ff0c18	2273	//! 0
mbed_official	146:f64d43ff0c18	2274	uint32_t DTEN0 : 1; //!< [4] Deadtime Enable For n = 0
mbed_official	146:f64d43ff0c18	2275	uint32_t SYNCEN0 : 1; //!< [5] Synchronization Enable For n = 0
mbed_official	146:f64d43ff0c18	2276	uint32_t FAULTEN0 : 1; //!< [6] Fault Control Enable For n = 0
mbed_official	146:f64d43ff0c18	2277	uint32_t RESERVED0 : 1; //!< [7]
mbed_official	146:f64d43ff0c18	2278	uint32_t COMBINE1 : 1; //!< [8] Combine Channels For n = 2
mbed_official	146:f64d43ff0c18	2279	uint32_t COMP1 : 1; //!< [9] Complement Of Channel (n) For n = 2
mbed_official	146:f64d43ff0c18	2280	uint32_t DECAPEN1 : 1; //!< [10] Dual Edge Capture Mode Enable For n
mbed_official	146:f64d43ff0c18	2281	//! = 2
mbed_official	146:f64d43ff0c18	2282	uint32_t DECAP1 : 1; //!< [11] Dual Edge Capture Mode Captures For n
mbed_official	146:f64d43ff0c18	2283	//! = 2
mbed_official	146:f64d43ff0c18	2284	uint32_t DTEN1 : 1; //!< [12] Deadtime Enable For n = 2
mbed_official	146:f64d43ff0c18	2285	uint32_t SYNCEN1 : 1; //!< [13] Synchronization Enable For n = 2
mbed_official	146:f64d43ff0c18	2286	uint32_t FAULTEN1 : 1; //!< [14] Fault Control Enable For n = 2
mbed_official	146:f64d43ff0c18	2287	uint32_t RESERVED1 : 1; //!< [15]
mbed_official	146:f64d43ff0c18	2288	uint32_t COMBINE2 : 1; //!< [16] Combine Channels For n = 4
mbed_official	146:f64d43ff0c18	2289	uint32_t COMP2 : 1; //!< [17] Complement Of Channel (n) For n = 4
mbed_official	146:f64d43ff0c18	2290	uint32_t DECAPEN2 : 1; //!< [18] Dual Edge Capture Mode Enable For n
mbed_official	146:f64d43ff0c18	2291	//! = 4
mbed_official	146:f64d43ff0c18	2292	uint32_t DECAP2 : 1; //!< [19] Dual Edge Capture Mode Captures For n
mbed_official	146:f64d43ff0c18	2293	//! = 4
mbed_official	146:f64d43ff0c18	2294	uint32_t DTEN2 : 1; //!< [20] Deadtime Enable For n = 4
mbed_official	146:f64d43ff0c18	2295	uint32_t SYNCEN2 : 1; //!< [21] Synchronization Enable For n = 4
mbed_official	146:f64d43ff0c18	2296	uint32_t FAULTEN2 : 1; //!< [22] Fault Control Enable For n = 4
mbed_official	146:f64d43ff0c18	2297	uint32_t RESERVED2 : 1; //!< [23]
mbed_official	146:f64d43ff0c18	2298	uint32_t COMBINE3 : 1; //!< [24] Combine Channels For n = 6
mbed_official	146:f64d43ff0c18	2299	uint32_t COMP3 : 1; //!< [25] Complement Of Channel (n) for n = 6
mbed_official	146:f64d43ff0c18	2300	uint32_t DECAPEN3 : 1; //!< [26] Dual Edge Capture Mode Enable For n
mbed_official	146:f64d43ff0c18	2301	//! = 6
mbed_official	146:f64d43ff0c18	2302	uint32_t DECAP3 : 1; //!< [27] Dual Edge Capture Mode Captures For n
mbed_official	146:f64d43ff0c18	2303	//! = 6
mbed_official	146:f64d43ff0c18	2304	uint32_t DTEN3 : 1; //!< [28] Deadtime Enable For n = 6
mbed_official	146:f64d43ff0c18	2305	uint32_t SYNCEN3 : 1; //!< [29] Synchronization Enable For n = 6
mbed_official	146:f64d43ff0c18	2306	uint32_t FAULTEN3 : 1; //!< [30] Fault Control Enable For n = 6
mbed_official	146:f64d43ff0c18	2307	uint32_t RESERVED3 : 1; //!< [31]
mbed_official	146:f64d43ff0c18	2308	} B;
mbed_official	146:f64d43ff0c18	2309	} hw_ftm_combine_t;
mbed_official	146:f64d43ff0c18	2310	#endif
mbed_official	146:f64d43ff0c18	2311
mbed_official	146:f64d43ff0c18	2312	/*!
mbed_official	146:f64d43ff0c18	2313	* @name Constants and macros for entire FTM_COMBINE register
mbed_official	146:f64d43ff0c18	2314	*/
mbed_official	146:f64d43ff0c18	2315	//@{
mbed_official	146:f64d43ff0c18	2316	#define HW_FTM_COMBINE_ADDR(x) (REGS_FTM_BASE(x) + 0x64U)
mbed_official	146:f64d43ff0c18	2317
mbed_official	146:f64d43ff0c18	2318	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2319	#define HW_FTM_COMBINE(x) ((__IO hw_ftm_combine_t ) HW_FTM_COMBINE_ADDR(x))
mbed_official	146:f64d43ff0c18	2320	#define HW_FTM_COMBINE_RD(x) (HW_FTM_COMBINE(x).U)
mbed_official	146:f64d43ff0c18	2321	#define HW_FTM_COMBINE_WR(x, v) (HW_FTM_COMBINE(x).U = (v))
mbed_official	146:f64d43ff0c18	2322	#define HW_FTM_COMBINE_SET(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	2323	#define HW_FTM_COMBINE_CLR(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	2324	#define HW_FTM_COMBINE_TOG(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	2325	#endif
mbed_official	146:f64d43ff0c18	2326	//@}
mbed_official	146:f64d43ff0c18	2327
mbed_official	146:f64d43ff0c18	2328	/*
mbed_official	146:f64d43ff0c18	2329	* Constants & macros for individual FTM_COMBINE bitfields
mbed_official	146:f64d43ff0c18	2330	*/
mbed_official	146:f64d43ff0c18	2331
mbed_official	146:f64d43ff0c18	2332	/*!
mbed_official	146:f64d43ff0c18	2333	* @name Register FTM_COMBINE, field COMBINE0[0] (RW)
mbed_official	146:f64d43ff0c18	2334	*
mbed_official	146:f64d43ff0c18	2335	* Enables the combine feature for channels (n) and (n+1). This field is write
mbed_official	146:f64d43ff0c18	2336	* protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	2337	*
mbed_official	146:f64d43ff0c18	2338	* Values:
mbed_official	146:f64d43ff0c18	2339	* - 0 - Channels (n) and (n+1) are independent.
mbed_official	146:f64d43ff0c18	2340	* - 1 - Channels (n) and (n+1) are combined.
mbed_official	146:f64d43ff0c18	2341	*/
mbed_official	146:f64d43ff0c18	2342	//@{
mbed_official	146:f64d43ff0c18	2343	#define BP_FTM_COMBINE_COMBINE0 (0U) //!< Bit position for FTM_COMBINE_COMBINE0.
mbed_official	146:f64d43ff0c18	2344	#define BM_FTM_COMBINE_COMBINE0 (0x00000001U) //!< Bit mask for FTM_COMBINE_COMBINE0.
mbed_official	146:f64d43ff0c18	2345	#define BS_FTM_COMBINE_COMBINE0 (1U) //!< Bit field size in bits for FTM_COMBINE_COMBINE0.
mbed_official	146:f64d43ff0c18	2346
mbed_official	146:f64d43ff0c18	2347	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2348	//! @brief Read current value of the FTM_COMBINE_COMBINE0 field.
mbed_official	146:f64d43ff0c18	2349	#define BR_FTM_COMBINE_COMBINE0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE0))
mbed_official	146:f64d43ff0c18	2350	#endif
mbed_official	146:f64d43ff0c18	2351
mbed_official	146:f64d43ff0c18	2352	//! @brief Format value for bitfield FTM_COMBINE_COMBINE0.
mbed_official	146:f64d43ff0c18	2353	#define BF_FTM_COMBINE_COMBINE0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMBINE0), uint32_t) & BM_FTM_COMBINE_COMBINE0)
mbed_official	146:f64d43ff0c18	2354
mbed_official	146:f64d43ff0c18	2355	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2356	//! @brief Set the COMBINE0 field to a new value.
mbed_official	146:f64d43ff0c18	2357	#define BW_FTM_COMBINE_COMBINE0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE0) = (v))
mbed_official	146:f64d43ff0c18	2358	#endif
mbed_official	146:f64d43ff0c18	2359	//@}
mbed_official	146:f64d43ff0c18	2360
mbed_official	146:f64d43ff0c18	2361	/*!
mbed_official	146:f64d43ff0c18	2362	* @name Register FTM_COMBINE, field COMP0[1] (RW)
mbed_official	146:f64d43ff0c18	2363	*
mbed_official	146:f64d43ff0c18	2364	* Enables Complementary mode for the combined channels. In Complementary mode
mbed_official	146:f64d43ff0c18	2365	* the channel (n+1) output is the inverse of the channel (n) output. This field
mbed_official	146:f64d43ff0c18	2366	* is write protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	2367	*
mbed_official	146:f64d43ff0c18	2368	* Values:
mbed_official	146:f64d43ff0c18	2369	* - 0 - The channel (n+1) output is the same as the channel (n) output.
mbed_official	146:f64d43ff0c18	2370	* - 1 - The channel (n+1) output is the complement of the channel (n) output.
mbed_official	146:f64d43ff0c18	2371	*/
mbed_official	146:f64d43ff0c18	2372	//@{
mbed_official	146:f64d43ff0c18	2373	#define BP_FTM_COMBINE_COMP0 (1U) //!< Bit position for FTM_COMBINE_COMP0.
mbed_official	146:f64d43ff0c18	2374	#define BM_FTM_COMBINE_COMP0 (0x00000002U) //!< Bit mask for FTM_COMBINE_COMP0.
mbed_official	146:f64d43ff0c18	2375	#define BS_FTM_COMBINE_COMP0 (1U) //!< Bit field size in bits for FTM_COMBINE_COMP0.
mbed_official	146:f64d43ff0c18	2376
mbed_official	146:f64d43ff0c18	2377	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2378	//! @brief Read current value of the FTM_COMBINE_COMP0 field.
mbed_official	146:f64d43ff0c18	2379	#define BR_FTM_COMBINE_COMP0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP0))
mbed_official	146:f64d43ff0c18	2380	#endif
mbed_official	146:f64d43ff0c18	2381
mbed_official	146:f64d43ff0c18	2382	//! @brief Format value for bitfield FTM_COMBINE_COMP0.
mbed_official	146:f64d43ff0c18	2383	#define BF_FTM_COMBINE_COMP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMP0), uint32_t) & BM_FTM_COMBINE_COMP0)
mbed_official	146:f64d43ff0c18	2384
mbed_official	146:f64d43ff0c18	2385	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2386	//! @brief Set the COMP0 field to a new value.
mbed_official	146:f64d43ff0c18	2387	#define BW_FTM_COMBINE_COMP0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP0) = (v))
mbed_official	146:f64d43ff0c18	2388	#endif
mbed_official	146:f64d43ff0c18	2389	//@}
mbed_official	146:f64d43ff0c18	2390
mbed_official	146:f64d43ff0c18	2391	/*!
mbed_official	146:f64d43ff0c18	2392	* @name Register FTM_COMBINE, field DECAPEN0[2] (RW)
mbed_official	146:f64d43ff0c18	2393	*
mbed_official	146:f64d43ff0c18	2394	* Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
mbed_official	146:f64d43ff0c18	2395	* reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
mbed_official	146:f64d43ff0c18	2396	* Dual Edge Capture mode according to #ModeSel1Table. This field applies only
mbed_official	146:f64d43ff0c18	2397	* when FTMEN = 1. This field is write protected. It can be written only when
mbed_official	146:f64d43ff0c18	2398	* MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	2399	*
mbed_official	146:f64d43ff0c18	2400	* Values:
mbed_official	146:f64d43ff0c18	2401	* - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
mbed_official	146:f64d43ff0c18	2402	* - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
mbed_official	146:f64d43ff0c18	2403	*/
mbed_official	146:f64d43ff0c18	2404	//@{
mbed_official	146:f64d43ff0c18	2405	#define BP_FTM_COMBINE_DECAPEN0 (2U) //!< Bit position for FTM_COMBINE_DECAPEN0.
mbed_official	146:f64d43ff0c18	2406	#define BM_FTM_COMBINE_DECAPEN0 (0x00000004U) //!< Bit mask for FTM_COMBINE_DECAPEN0.
mbed_official	146:f64d43ff0c18	2407	#define BS_FTM_COMBINE_DECAPEN0 (1U) //!< Bit field size in bits for FTM_COMBINE_DECAPEN0.
mbed_official	146:f64d43ff0c18	2408
mbed_official	146:f64d43ff0c18	2409	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2410	//! @brief Read current value of the FTM_COMBINE_DECAPEN0 field.
mbed_official	146:f64d43ff0c18	2411	#define BR_FTM_COMBINE_DECAPEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN0))
mbed_official	146:f64d43ff0c18	2412	#endif
mbed_official	146:f64d43ff0c18	2413
mbed_official	146:f64d43ff0c18	2414	//! @brief Format value for bitfield FTM_COMBINE_DECAPEN0.
mbed_official	146:f64d43ff0c18	2415	#define BF_FTM_COMBINE_DECAPEN0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAPEN0), uint32_t) & BM_FTM_COMBINE_DECAPEN0)
mbed_official	146:f64d43ff0c18	2416
mbed_official	146:f64d43ff0c18	2417	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2418	//! @brief Set the DECAPEN0 field to a new value.
mbed_official	146:f64d43ff0c18	2419	#define BW_FTM_COMBINE_DECAPEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN0) = (v))
mbed_official	146:f64d43ff0c18	2420	#endif
mbed_official	146:f64d43ff0c18	2421	//@}
mbed_official	146:f64d43ff0c18	2422
mbed_official	146:f64d43ff0c18	2423	/*!
mbed_official	146:f64d43ff0c18	2424	* @name Register FTM_COMBINE, field DECAP0[3] (RW)
mbed_official	146:f64d43ff0c18	2425	*
mbed_official	146:f64d43ff0c18	2426	* Enables the capture of the FTM counter value according to the channel (n)
mbed_official	146:f64d43ff0c18	2427	* input event and the configuration of the dual edge capture bits. This field
mbed_official	146:f64d43ff0c18	2428	* applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
mbed_official	146:f64d43ff0c18	2429	* hardware if dual edge capture - one-shot mode is selected and when the capture
mbed_official	146:f64d43ff0c18	2430	* of channel (n+1) event is made.
mbed_official	146:f64d43ff0c18	2431	*
mbed_official	146:f64d43ff0c18	2432	* Values:
mbed_official	146:f64d43ff0c18	2433	* - 0 - The dual edge captures are inactive.
mbed_official	146:f64d43ff0c18	2434	* - 1 - The dual edge captures are active.
mbed_official	146:f64d43ff0c18	2435	*/
mbed_official	146:f64d43ff0c18	2436	//@{
mbed_official	146:f64d43ff0c18	2437	#define BP_FTM_COMBINE_DECAP0 (3U) //!< Bit position for FTM_COMBINE_DECAP0.
mbed_official	146:f64d43ff0c18	2438	#define BM_FTM_COMBINE_DECAP0 (0x00000008U) //!< Bit mask for FTM_COMBINE_DECAP0.
mbed_official	146:f64d43ff0c18	2439	#define BS_FTM_COMBINE_DECAP0 (1U) //!< Bit field size in bits for FTM_COMBINE_DECAP0.
mbed_official	146:f64d43ff0c18	2440
mbed_official	146:f64d43ff0c18	2441	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2442	//! @brief Read current value of the FTM_COMBINE_DECAP0 field.
mbed_official	146:f64d43ff0c18	2443	#define BR_FTM_COMBINE_DECAP0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP0))
mbed_official	146:f64d43ff0c18	2444	#endif
mbed_official	146:f64d43ff0c18	2445
mbed_official	146:f64d43ff0c18	2446	//! @brief Format value for bitfield FTM_COMBINE_DECAP0.
mbed_official	146:f64d43ff0c18	2447	#define BF_FTM_COMBINE_DECAP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAP0), uint32_t) & BM_FTM_COMBINE_DECAP0)
mbed_official	146:f64d43ff0c18	2448
mbed_official	146:f64d43ff0c18	2449	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2450	//! @brief Set the DECAP0 field to a new value.
mbed_official	146:f64d43ff0c18	2451	#define BW_FTM_COMBINE_DECAP0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP0) = (v))
mbed_official	146:f64d43ff0c18	2452	#endif
mbed_official	146:f64d43ff0c18	2453	//@}
mbed_official	146:f64d43ff0c18	2454
mbed_official	146:f64d43ff0c18	2455	/*!
mbed_official	146:f64d43ff0c18	2456	* @name Register FTM_COMBINE, field DTEN0[4] (RW)
mbed_official	146:f64d43ff0c18	2457	*
mbed_official	146:f64d43ff0c18	2458	* Enables the deadtime insertion in the channels (n) and (n+1). This field is
mbed_official	146:f64d43ff0c18	2459	* write protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	2460	*
mbed_official	146:f64d43ff0c18	2461	* Values:
mbed_official	146:f64d43ff0c18	2462	* - 0 - The deadtime insertion in this pair of channels is disabled.
mbed_official	146:f64d43ff0c18	2463	* - 1 - The deadtime insertion in this pair of channels is enabled.
mbed_official	146:f64d43ff0c18	2464	*/
mbed_official	146:f64d43ff0c18	2465	//@{
mbed_official	146:f64d43ff0c18	2466	#define BP_FTM_COMBINE_DTEN0 (4U) //!< Bit position for FTM_COMBINE_DTEN0.
mbed_official	146:f64d43ff0c18	2467	#define BM_FTM_COMBINE_DTEN0 (0x00000010U) //!< Bit mask for FTM_COMBINE_DTEN0.
mbed_official	146:f64d43ff0c18	2468	#define BS_FTM_COMBINE_DTEN0 (1U) //!< Bit field size in bits for FTM_COMBINE_DTEN0.
mbed_official	146:f64d43ff0c18	2469
mbed_official	146:f64d43ff0c18	2470	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2471	//! @brief Read current value of the FTM_COMBINE_DTEN0 field.
mbed_official	146:f64d43ff0c18	2472	#define BR_FTM_COMBINE_DTEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN0))
mbed_official	146:f64d43ff0c18	2473	#endif
mbed_official	146:f64d43ff0c18	2474
mbed_official	146:f64d43ff0c18	2475	//! @brief Format value for bitfield FTM_COMBINE_DTEN0.
mbed_official	146:f64d43ff0c18	2476	#define BF_FTM_COMBINE_DTEN0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DTEN0), uint32_t) & BM_FTM_COMBINE_DTEN0)
mbed_official	146:f64d43ff0c18	2477
mbed_official	146:f64d43ff0c18	2478	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2479	//! @brief Set the DTEN0 field to a new value.
mbed_official	146:f64d43ff0c18	2480	#define BW_FTM_COMBINE_DTEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN0) = (v))
mbed_official	146:f64d43ff0c18	2481	#endif
mbed_official	146:f64d43ff0c18	2482	//@}
mbed_official	146:f64d43ff0c18	2483
mbed_official	146:f64d43ff0c18	2484	/*!
mbed_official	146:f64d43ff0c18	2485	* @name Register FTM_COMBINE, field SYNCEN0[5] (RW)
mbed_official	146:f64d43ff0c18	2486	*
mbed_official	146:f64d43ff0c18	2487	* Enables PWM synchronization of registers C(n)V and C(n+1)V.
mbed_official	146:f64d43ff0c18	2488	*
mbed_official	146:f64d43ff0c18	2489	* Values:
mbed_official	146:f64d43ff0c18	2490	* - 0 - The PWM synchronization in this pair of channels is disabled.
mbed_official	146:f64d43ff0c18	2491	* - 1 - The PWM synchronization in this pair of channels is enabled.
mbed_official	146:f64d43ff0c18	2492	*/
mbed_official	146:f64d43ff0c18	2493	//@{
mbed_official	146:f64d43ff0c18	2494	#define BP_FTM_COMBINE_SYNCEN0 (5U) //!< Bit position for FTM_COMBINE_SYNCEN0.
mbed_official	146:f64d43ff0c18	2495	#define BM_FTM_COMBINE_SYNCEN0 (0x00000020U) //!< Bit mask for FTM_COMBINE_SYNCEN0.
mbed_official	146:f64d43ff0c18	2496	#define BS_FTM_COMBINE_SYNCEN0 (1U) //!< Bit field size in bits for FTM_COMBINE_SYNCEN0.
mbed_official	146:f64d43ff0c18	2497
mbed_official	146:f64d43ff0c18	2498	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2499	//! @brief Read current value of the FTM_COMBINE_SYNCEN0 field.
mbed_official	146:f64d43ff0c18	2500	#define BR_FTM_COMBINE_SYNCEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN0))
mbed_official	146:f64d43ff0c18	2501	#endif
mbed_official	146:f64d43ff0c18	2502
mbed_official	146:f64d43ff0c18	2503	//! @brief Format value for bitfield FTM_COMBINE_SYNCEN0.
mbed_official	146:f64d43ff0c18	2504	#define BF_FTM_COMBINE_SYNCEN0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_SYNCEN0), uint32_t) & BM_FTM_COMBINE_SYNCEN0)
mbed_official	146:f64d43ff0c18	2505
mbed_official	146:f64d43ff0c18	2506	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2507	//! @brief Set the SYNCEN0 field to a new value.
mbed_official	146:f64d43ff0c18	2508	#define BW_FTM_COMBINE_SYNCEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN0) = (v))
mbed_official	146:f64d43ff0c18	2509	#endif
mbed_official	146:f64d43ff0c18	2510	//@}
mbed_official	146:f64d43ff0c18	2511
mbed_official	146:f64d43ff0c18	2512	/*!
mbed_official	146:f64d43ff0c18	2513	* @name Register FTM_COMBINE, field FAULTEN0[6] (RW)
mbed_official	146:f64d43ff0c18	2514	*
mbed_official	146:f64d43ff0c18	2515	* Enables the fault control in channels (n) and (n+1). This field is write
mbed_official	146:f64d43ff0c18	2516	* protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	2517	*
mbed_official	146:f64d43ff0c18	2518	* Values:
mbed_official	146:f64d43ff0c18	2519	* - 0 - The fault control in this pair of channels is disabled.
mbed_official	146:f64d43ff0c18	2520	* - 1 - The fault control in this pair of channels is enabled.
mbed_official	146:f64d43ff0c18	2521	*/
mbed_official	146:f64d43ff0c18	2522	//@{
mbed_official	146:f64d43ff0c18	2523	#define BP_FTM_COMBINE_FAULTEN0 (6U) //!< Bit position for FTM_COMBINE_FAULTEN0.
mbed_official	146:f64d43ff0c18	2524	#define BM_FTM_COMBINE_FAULTEN0 (0x00000040U) //!< Bit mask for FTM_COMBINE_FAULTEN0.
mbed_official	146:f64d43ff0c18	2525	#define BS_FTM_COMBINE_FAULTEN0 (1U) //!< Bit field size in bits for FTM_COMBINE_FAULTEN0.
mbed_official	146:f64d43ff0c18	2526
mbed_official	146:f64d43ff0c18	2527	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2528	//! @brief Read current value of the FTM_COMBINE_FAULTEN0 field.
mbed_official	146:f64d43ff0c18	2529	#define BR_FTM_COMBINE_FAULTEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN0))
mbed_official	146:f64d43ff0c18	2530	#endif
mbed_official	146:f64d43ff0c18	2531
mbed_official	146:f64d43ff0c18	2532	//! @brief Format value for bitfield FTM_COMBINE_FAULTEN0.
mbed_official	146:f64d43ff0c18	2533	#define BF_FTM_COMBINE_FAULTEN0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_FAULTEN0), uint32_t) & BM_FTM_COMBINE_FAULTEN0)
mbed_official	146:f64d43ff0c18	2534
mbed_official	146:f64d43ff0c18	2535	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2536	//! @brief Set the FAULTEN0 field to a new value.
mbed_official	146:f64d43ff0c18	2537	#define BW_FTM_COMBINE_FAULTEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN0) = (v))
mbed_official	146:f64d43ff0c18	2538	#endif
mbed_official	146:f64d43ff0c18	2539	//@}
mbed_official	146:f64d43ff0c18	2540
mbed_official	146:f64d43ff0c18	2541	/*!
mbed_official	146:f64d43ff0c18	2542	* @name Register FTM_COMBINE, field COMBINE1[8] (RW)
mbed_official	146:f64d43ff0c18	2543	*
mbed_official	146:f64d43ff0c18	2544	* Enables the combine feature for channels (n) and (n+1). This field is write
mbed_official	146:f64d43ff0c18	2545	* protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	2546	*
mbed_official	146:f64d43ff0c18	2547	* Values:
mbed_official	146:f64d43ff0c18	2548	* - 0 - Channels (n) and (n+1) are independent.
mbed_official	146:f64d43ff0c18	2549	* - 1 - Channels (n) and (n+1) are combined.
mbed_official	146:f64d43ff0c18	2550	*/
mbed_official	146:f64d43ff0c18	2551	//@{
mbed_official	146:f64d43ff0c18	2552	#define BP_FTM_COMBINE_COMBINE1 (8U) //!< Bit position for FTM_COMBINE_COMBINE1.
mbed_official	146:f64d43ff0c18	2553	#define BM_FTM_COMBINE_COMBINE1 (0x00000100U) //!< Bit mask for FTM_COMBINE_COMBINE1.
mbed_official	146:f64d43ff0c18	2554	#define BS_FTM_COMBINE_COMBINE1 (1U) //!< Bit field size in bits for FTM_COMBINE_COMBINE1.
mbed_official	146:f64d43ff0c18	2555
mbed_official	146:f64d43ff0c18	2556	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2557	//! @brief Read current value of the FTM_COMBINE_COMBINE1 field.
mbed_official	146:f64d43ff0c18	2558	#define BR_FTM_COMBINE_COMBINE1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE1))
mbed_official	146:f64d43ff0c18	2559	#endif
mbed_official	146:f64d43ff0c18	2560
mbed_official	146:f64d43ff0c18	2561	//! @brief Format value for bitfield FTM_COMBINE_COMBINE1.
mbed_official	146:f64d43ff0c18	2562	#define BF_FTM_COMBINE_COMBINE1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMBINE1), uint32_t) & BM_FTM_COMBINE_COMBINE1)
mbed_official	146:f64d43ff0c18	2563
mbed_official	146:f64d43ff0c18	2564	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2565	//! @brief Set the COMBINE1 field to a new value.
mbed_official	146:f64d43ff0c18	2566	#define BW_FTM_COMBINE_COMBINE1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE1) = (v))
mbed_official	146:f64d43ff0c18	2567	#endif
mbed_official	146:f64d43ff0c18	2568	//@}
mbed_official	146:f64d43ff0c18	2569
mbed_official	146:f64d43ff0c18	2570	/*!
mbed_official	146:f64d43ff0c18	2571	* @name Register FTM_COMBINE, field COMP1[9] (RW)
mbed_official	146:f64d43ff0c18	2572	*
mbed_official	146:f64d43ff0c18	2573	* Enables Complementary mode for the combined channels. In Complementary mode
mbed_official	146:f64d43ff0c18	2574	* the channel (n+1) output is the inverse of the channel (n) output. This field
mbed_official	146:f64d43ff0c18	2575	* is write protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	2576	*
mbed_official	146:f64d43ff0c18	2577	* Values:
mbed_official	146:f64d43ff0c18	2578	* - 0 - The channel (n+1) output is the same as the channel (n) output.
mbed_official	146:f64d43ff0c18	2579	* - 1 - The channel (n+1) output is the complement of the channel (n) output.
mbed_official	146:f64d43ff0c18	2580	*/
mbed_official	146:f64d43ff0c18	2581	//@{
mbed_official	146:f64d43ff0c18	2582	#define BP_FTM_COMBINE_COMP1 (9U) //!< Bit position for FTM_COMBINE_COMP1.
mbed_official	146:f64d43ff0c18	2583	#define BM_FTM_COMBINE_COMP1 (0x00000200U) //!< Bit mask for FTM_COMBINE_COMP1.
mbed_official	146:f64d43ff0c18	2584	#define BS_FTM_COMBINE_COMP1 (1U) //!< Bit field size in bits for FTM_COMBINE_COMP1.
mbed_official	146:f64d43ff0c18	2585
mbed_official	146:f64d43ff0c18	2586	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2587	//! @brief Read current value of the FTM_COMBINE_COMP1 field.
mbed_official	146:f64d43ff0c18	2588	#define BR_FTM_COMBINE_COMP1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP1))
mbed_official	146:f64d43ff0c18	2589	#endif
mbed_official	146:f64d43ff0c18	2590
mbed_official	146:f64d43ff0c18	2591	//! @brief Format value for bitfield FTM_COMBINE_COMP1.
mbed_official	146:f64d43ff0c18	2592	#define BF_FTM_COMBINE_COMP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMP1), uint32_t) & BM_FTM_COMBINE_COMP1)
mbed_official	146:f64d43ff0c18	2593
mbed_official	146:f64d43ff0c18	2594	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2595	//! @brief Set the COMP1 field to a new value.
mbed_official	146:f64d43ff0c18	2596	#define BW_FTM_COMBINE_COMP1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP1) = (v))
mbed_official	146:f64d43ff0c18	2597	#endif
mbed_official	146:f64d43ff0c18	2598	//@}
mbed_official	146:f64d43ff0c18	2599
mbed_official	146:f64d43ff0c18	2600	/*!
mbed_official	146:f64d43ff0c18	2601	* @name Register FTM_COMBINE, field DECAPEN1[10] (RW)
mbed_official	146:f64d43ff0c18	2602	*
mbed_official	146:f64d43ff0c18	2603	* Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
mbed_official	146:f64d43ff0c18	2604	* reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
mbed_official	146:f64d43ff0c18	2605	* Dual Edge Capture mode according to #ModeSel1Table. This field applies only
mbed_official	146:f64d43ff0c18	2606	* when FTMEN = 1. This field is write protected. It can be written only when
mbed_official	146:f64d43ff0c18	2607	* MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	2608	*
mbed_official	146:f64d43ff0c18	2609	* Values:
mbed_official	146:f64d43ff0c18	2610	* - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
mbed_official	146:f64d43ff0c18	2611	* - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
mbed_official	146:f64d43ff0c18	2612	*/
mbed_official	146:f64d43ff0c18	2613	//@{
mbed_official	146:f64d43ff0c18	2614	#define BP_FTM_COMBINE_DECAPEN1 (10U) //!< Bit position for FTM_COMBINE_DECAPEN1.
mbed_official	146:f64d43ff0c18	2615	#define BM_FTM_COMBINE_DECAPEN1 (0x00000400U) //!< Bit mask for FTM_COMBINE_DECAPEN1.
mbed_official	146:f64d43ff0c18	2616	#define BS_FTM_COMBINE_DECAPEN1 (1U) //!< Bit field size in bits for FTM_COMBINE_DECAPEN1.
mbed_official	146:f64d43ff0c18	2617
mbed_official	146:f64d43ff0c18	2618	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2619	//! @brief Read current value of the FTM_COMBINE_DECAPEN1 field.
mbed_official	146:f64d43ff0c18	2620	#define BR_FTM_COMBINE_DECAPEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN1))
mbed_official	146:f64d43ff0c18	2621	#endif
mbed_official	146:f64d43ff0c18	2622
mbed_official	146:f64d43ff0c18	2623	//! @brief Format value for bitfield FTM_COMBINE_DECAPEN1.
mbed_official	146:f64d43ff0c18	2624	#define BF_FTM_COMBINE_DECAPEN1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAPEN1), uint32_t) & BM_FTM_COMBINE_DECAPEN1)
mbed_official	146:f64d43ff0c18	2625
mbed_official	146:f64d43ff0c18	2626	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2627	//! @brief Set the DECAPEN1 field to a new value.
mbed_official	146:f64d43ff0c18	2628	#define BW_FTM_COMBINE_DECAPEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN1) = (v))
mbed_official	146:f64d43ff0c18	2629	#endif
mbed_official	146:f64d43ff0c18	2630	//@}
mbed_official	146:f64d43ff0c18	2631
mbed_official	146:f64d43ff0c18	2632	/*!
mbed_official	146:f64d43ff0c18	2633	* @name Register FTM_COMBINE, field DECAP1[11] (RW)
mbed_official	146:f64d43ff0c18	2634	*
mbed_official	146:f64d43ff0c18	2635	* Enables the capture of the FTM counter value according to the channel (n)
mbed_official	146:f64d43ff0c18	2636	* input event and the configuration of the dual edge capture bits. This field
mbed_official	146:f64d43ff0c18	2637	* applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
mbed_official	146:f64d43ff0c18	2638	* hardware if Dual Edge Capture - One-Shot mode is selected and when the capture
mbed_official	146:f64d43ff0c18	2639	* of channel (n+1) event is made.
mbed_official	146:f64d43ff0c18	2640	*
mbed_official	146:f64d43ff0c18	2641	* Values:
mbed_official	146:f64d43ff0c18	2642	* - 0 - The dual edge captures are inactive.
mbed_official	146:f64d43ff0c18	2643	* - 1 - The dual edge captures are active.
mbed_official	146:f64d43ff0c18	2644	*/
mbed_official	146:f64d43ff0c18	2645	//@{
mbed_official	146:f64d43ff0c18	2646	#define BP_FTM_COMBINE_DECAP1 (11U) //!< Bit position for FTM_COMBINE_DECAP1.
mbed_official	146:f64d43ff0c18	2647	#define BM_FTM_COMBINE_DECAP1 (0x00000800U) //!< Bit mask for FTM_COMBINE_DECAP1.
mbed_official	146:f64d43ff0c18	2648	#define BS_FTM_COMBINE_DECAP1 (1U) //!< Bit field size in bits for FTM_COMBINE_DECAP1.
mbed_official	146:f64d43ff0c18	2649
mbed_official	146:f64d43ff0c18	2650	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2651	//! @brief Read current value of the FTM_COMBINE_DECAP1 field.
mbed_official	146:f64d43ff0c18	2652	#define BR_FTM_COMBINE_DECAP1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP1))
mbed_official	146:f64d43ff0c18	2653	#endif
mbed_official	146:f64d43ff0c18	2654
mbed_official	146:f64d43ff0c18	2655	//! @brief Format value for bitfield FTM_COMBINE_DECAP1.
mbed_official	146:f64d43ff0c18	2656	#define BF_FTM_COMBINE_DECAP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAP1), uint32_t) & BM_FTM_COMBINE_DECAP1)
mbed_official	146:f64d43ff0c18	2657
mbed_official	146:f64d43ff0c18	2658	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2659	//! @brief Set the DECAP1 field to a new value.
mbed_official	146:f64d43ff0c18	2660	#define BW_FTM_COMBINE_DECAP1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP1) = (v))
mbed_official	146:f64d43ff0c18	2661	#endif
mbed_official	146:f64d43ff0c18	2662	//@}
mbed_official	146:f64d43ff0c18	2663
mbed_official	146:f64d43ff0c18	2664	/*!
mbed_official	146:f64d43ff0c18	2665	* @name Register FTM_COMBINE, field DTEN1[12] (RW)
mbed_official	146:f64d43ff0c18	2666	*
mbed_official	146:f64d43ff0c18	2667	* Enables the deadtime insertion in the channels (n) and (n+1). This field is
mbed_official	146:f64d43ff0c18	2668	* write protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	2669	*
mbed_official	146:f64d43ff0c18	2670	* Values:
mbed_official	146:f64d43ff0c18	2671	* - 0 - The deadtime insertion in this pair of channels is disabled.
mbed_official	146:f64d43ff0c18	2672	* - 1 - The deadtime insertion in this pair of channels is enabled.
mbed_official	146:f64d43ff0c18	2673	*/
mbed_official	146:f64d43ff0c18	2674	//@{
mbed_official	146:f64d43ff0c18	2675	#define BP_FTM_COMBINE_DTEN1 (12U) //!< Bit position for FTM_COMBINE_DTEN1.
mbed_official	146:f64d43ff0c18	2676	#define BM_FTM_COMBINE_DTEN1 (0x00001000U) //!< Bit mask for FTM_COMBINE_DTEN1.
mbed_official	146:f64d43ff0c18	2677	#define BS_FTM_COMBINE_DTEN1 (1U) //!< Bit field size in bits for FTM_COMBINE_DTEN1.
mbed_official	146:f64d43ff0c18	2678
mbed_official	146:f64d43ff0c18	2679	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2680	//! @brief Read current value of the FTM_COMBINE_DTEN1 field.
mbed_official	146:f64d43ff0c18	2681	#define BR_FTM_COMBINE_DTEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN1))
mbed_official	146:f64d43ff0c18	2682	#endif
mbed_official	146:f64d43ff0c18	2683
mbed_official	146:f64d43ff0c18	2684	//! @brief Format value for bitfield FTM_COMBINE_DTEN1.
mbed_official	146:f64d43ff0c18	2685	#define BF_FTM_COMBINE_DTEN1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DTEN1), uint32_t) & BM_FTM_COMBINE_DTEN1)
mbed_official	146:f64d43ff0c18	2686
mbed_official	146:f64d43ff0c18	2687	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2688	//! @brief Set the DTEN1 field to a new value.
mbed_official	146:f64d43ff0c18	2689	#define BW_FTM_COMBINE_DTEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN1) = (v))
mbed_official	146:f64d43ff0c18	2690	#endif
mbed_official	146:f64d43ff0c18	2691	//@}
mbed_official	146:f64d43ff0c18	2692
mbed_official	146:f64d43ff0c18	2693	/*!
mbed_official	146:f64d43ff0c18	2694	* @name Register FTM_COMBINE, field SYNCEN1[13] (RW)
mbed_official	146:f64d43ff0c18	2695	*
mbed_official	146:f64d43ff0c18	2696	* Enables PWM synchronization of registers C(n)V and C(n+1)V.
mbed_official	146:f64d43ff0c18	2697	*
mbed_official	146:f64d43ff0c18	2698	* Values:
mbed_official	146:f64d43ff0c18	2699	* - 0 - The PWM synchronization in this pair of channels is disabled.
mbed_official	146:f64d43ff0c18	2700	* - 1 - The PWM synchronization in this pair of channels is enabled.
mbed_official	146:f64d43ff0c18	2701	*/
mbed_official	146:f64d43ff0c18	2702	//@{
mbed_official	146:f64d43ff0c18	2703	#define BP_FTM_COMBINE_SYNCEN1 (13U) //!< Bit position for FTM_COMBINE_SYNCEN1.
mbed_official	146:f64d43ff0c18	2704	#define BM_FTM_COMBINE_SYNCEN1 (0x00002000U) //!< Bit mask for FTM_COMBINE_SYNCEN1.
mbed_official	146:f64d43ff0c18	2705	#define BS_FTM_COMBINE_SYNCEN1 (1U) //!< Bit field size in bits for FTM_COMBINE_SYNCEN1.
mbed_official	146:f64d43ff0c18	2706
mbed_official	146:f64d43ff0c18	2707	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2708	//! @brief Read current value of the FTM_COMBINE_SYNCEN1 field.
mbed_official	146:f64d43ff0c18	2709	#define BR_FTM_COMBINE_SYNCEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN1))
mbed_official	146:f64d43ff0c18	2710	#endif
mbed_official	146:f64d43ff0c18	2711
mbed_official	146:f64d43ff0c18	2712	//! @brief Format value for bitfield FTM_COMBINE_SYNCEN1.
mbed_official	146:f64d43ff0c18	2713	#define BF_FTM_COMBINE_SYNCEN1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_SYNCEN1), uint32_t) & BM_FTM_COMBINE_SYNCEN1)
mbed_official	146:f64d43ff0c18	2714
mbed_official	146:f64d43ff0c18	2715	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2716	//! @brief Set the SYNCEN1 field to a new value.
mbed_official	146:f64d43ff0c18	2717	#define BW_FTM_COMBINE_SYNCEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN1) = (v))
mbed_official	146:f64d43ff0c18	2718	#endif
mbed_official	146:f64d43ff0c18	2719	//@}
mbed_official	146:f64d43ff0c18	2720
mbed_official	146:f64d43ff0c18	2721	/*!
mbed_official	146:f64d43ff0c18	2722	* @name Register FTM_COMBINE, field FAULTEN1[14] (RW)
mbed_official	146:f64d43ff0c18	2723	*
mbed_official	146:f64d43ff0c18	2724	* Enables the fault control in channels (n) and (n+1). This field is write
mbed_official	146:f64d43ff0c18	2725	* protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	2726	*
mbed_official	146:f64d43ff0c18	2727	* Values:
mbed_official	146:f64d43ff0c18	2728	* - 0 - The fault control in this pair of channels is disabled.
mbed_official	146:f64d43ff0c18	2729	* - 1 - The fault control in this pair of channels is enabled.
mbed_official	146:f64d43ff0c18	2730	*/
mbed_official	146:f64d43ff0c18	2731	//@{
mbed_official	146:f64d43ff0c18	2732	#define BP_FTM_COMBINE_FAULTEN1 (14U) //!< Bit position for FTM_COMBINE_FAULTEN1.
mbed_official	146:f64d43ff0c18	2733	#define BM_FTM_COMBINE_FAULTEN1 (0x00004000U) //!< Bit mask for FTM_COMBINE_FAULTEN1.
mbed_official	146:f64d43ff0c18	2734	#define BS_FTM_COMBINE_FAULTEN1 (1U) //!< Bit field size in bits for FTM_COMBINE_FAULTEN1.
mbed_official	146:f64d43ff0c18	2735
mbed_official	146:f64d43ff0c18	2736	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2737	//! @brief Read current value of the FTM_COMBINE_FAULTEN1 field.
mbed_official	146:f64d43ff0c18	2738	#define BR_FTM_COMBINE_FAULTEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN1))
mbed_official	146:f64d43ff0c18	2739	#endif
mbed_official	146:f64d43ff0c18	2740
mbed_official	146:f64d43ff0c18	2741	//! @brief Format value for bitfield FTM_COMBINE_FAULTEN1.
mbed_official	146:f64d43ff0c18	2742	#define BF_FTM_COMBINE_FAULTEN1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_FAULTEN1), uint32_t) & BM_FTM_COMBINE_FAULTEN1)
mbed_official	146:f64d43ff0c18	2743
mbed_official	146:f64d43ff0c18	2744	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2745	//! @brief Set the FAULTEN1 field to a new value.
mbed_official	146:f64d43ff0c18	2746	#define BW_FTM_COMBINE_FAULTEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN1) = (v))
mbed_official	146:f64d43ff0c18	2747	#endif
mbed_official	146:f64d43ff0c18	2748	//@}
mbed_official	146:f64d43ff0c18	2749
mbed_official	146:f64d43ff0c18	2750	/*!
mbed_official	146:f64d43ff0c18	2751	* @name Register FTM_COMBINE, field COMBINE2[16] (RW)
mbed_official	146:f64d43ff0c18	2752	*
mbed_official	146:f64d43ff0c18	2753	* Enables the combine feature for channels (n) and (n+1). This field is write
mbed_official	146:f64d43ff0c18	2754	* protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	2755	*
mbed_official	146:f64d43ff0c18	2756	* Values:
mbed_official	146:f64d43ff0c18	2757	* - 0 - Channels (n) and (n+1) are independent.
mbed_official	146:f64d43ff0c18	2758	* - 1 - Channels (n) and (n+1) are combined.
mbed_official	146:f64d43ff0c18	2759	*/
mbed_official	146:f64d43ff0c18	2760	//@{
mbed_official	146:f64d43ff0c18	2761	#define BP_FTM_COMBINE_COMBINE2 (16U) //!< Bit position for FTM_COMBINE_COMBINE2.
mbed_official	146:f64d43ff0c18	2762	#define BM_FTM_COMBINE_COMBINE2 (0x00010000U) //!< Bit mask for FTM_COMBINE_COMBINE2.
mbed_official	146:f64d43ff0c18	2763	#define BS_FTM_COMBINE_COMBINE2 (1U) //!< Bit field size in bits for FTM_COMBINE_COMBINE2.
mbed_official	146:f64d43ff0c18	2764
mbed_official	146:f64d43ff0c18	2765	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2766	//! @brief Read current value of the FTM_COMBINE_COMBINE2 field.
mbed_official	146:f64d43ff0c18	2767	#define BR_FTM_COMBINE_COMBINE2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE2))
mbed_official	146:f64d43ff0c18	2768	#endif
mbed_official	146:f64d43ff0c18	2769
mbed_official	146:f64d43ff0c18	2770	//! @brief Format value for bitfield FTM_COMBINE_COMBINE2.
mbed_official	146:f64d43ff0c18	2771	#define BF_FTM_COMBINE_COMBINE2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMBINE2), uint32_t) & BM_FTM_COMBINE_COMBINE2)
mbed_official	146:f64d43ff0c18	2772
mbed_official	146:f64d43ff0c18	2773	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2774	//! @brief Set the COMBINE2 field to a new value.
mbed_official	146:f64d43ff0c18	2775	#define BW_FTM_COMBINE_COMBINE2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE2) = (v))
mbed_official	146:f64d43ff0c18	2776	#endif
mbed_official	146:f64d43ff0c18	2777	//@}
mbed_official	146:f64d43ff0c18	2778
mbed_official	146:f64d43ff0c18	2779	/*!
mbed_official	146:f64d43ff0c18	2780	* @name Register FTM_COMBINE, field COMP2[17] (RW)
mbed_official	146:f64d43ff0c18	2781	*
mbed_official	146:f64d43ff0c18	2782	* Enables Complementary mode for the combined channels. In Complementary mode
mbed_official	146:f64d43ff0c18	2783	* the channel (n+1) output is the inverse of the channel (n) output. This field
mbed_official	146:f64d43ff0c18	2784	* is write protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	2785	*
mbed_official	146:f64d43ff0c18	2786	* Values:
mbed_official	146:f64d43ff0c18	2787	* - 0 - The channel (n+1) output is the same as the channel (n) output.
mbed_official	146:f64d43ff0c18	2788	* - 1 - The channel (n+1) output is the complement of the channel (n) output.
mbed_official	146:f64d43ff0c18	2789	*/
mbed_official	146:f64d43ff0c18	2790	//@{
mbed_official	146:f64d43ff0c18	2791	#define BP_FTM_COMBINE_COMP2 (17U) //!< Bit position for FTM_COMBINE_COMP2.
mbed_official	146:f64d43ff0c18	2792	#define BM_FTM_COMBINE_COMP2 (0x00020000U) //!< Bit mask for FTM_COMBINE_COMP2.
mbed_official	146:f64d43ff0c18	2793	#define BS_FTM_COMBINE_COMP2 (1U) //!< Bit field size in bits for FTM_COMBINE_COMP2.
mbed_official	146:f64d43ff0c18	2794
mbed_official	146:f64d43ff0c18	2795	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2796	//! @brief Read current value of the FTM_COMBINE_COMP2 field.
mbed_official	146:f64d43ff0c18	2797	#define BR_FTM_COMBINE_COMP2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP2))
mbed_official	146:f64d43ff0c18	2798	#endif
mbed_official	146:f64d43ff0c18	2799
mbed_official	146:f64d43ff0c18	2800	//! @brief Format value for bitfield FTM_COMBINE_COMP2.
mbed_official	146:f64d43ff0c18	2801	#define BF_FTM_COMBINE_COMP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMP2), uint32_t) & BM_FTM_COMBINE_COMP2)
mbed_official	146:f64d43ff0c18	2802
mbed_official	146:f64d43ff0c18	2803	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2804	//! @brief Set the COMP2 field to a new value.
mbed_official	146:f64d43ff0c18	2805	#define BW_FTM_COMBINE_COMP2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP2) = (v))
mbed_official	146:f64d43ff0c18	2806	#endif
mbed_official	146:f64d43ff0c18	2807	//@}
mbed_official	146:f64d43ff0c18	2808
mbed_official	146:f64d43ff0c18	2809	/*!
mbed_official	146:f64d43ff0c18	2810	* @name Register FTM_COMBINE, field DECAPEN2[18] (RW)
mbed_official	146:f64d43ff0c18	2811	*
mbed_official	146:f64d43ff0c18	2812	* Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
mbed_official	146:f64d43ff0c18	2813	* reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
mbed_official	146:f64d43ff0c18	2814	* Dual Edge Capture mode according to #ModeSel1Table. This field applies only
mbed_official	146:f64d43ff0c18	2815	* when FTMEN = 1. This field is write protected. It can be written only when
mbed_official	146:f64d43ff0c18	2816	* MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	2817	*
mbed_official	146:f64d43ff0c18	2818	* Values:
mbed_official	146:f64d43ff0c18	2819	* - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
mbed_official	146:f64d43ff0c18	2820	* - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
mbed_official	146:f64d43ff0c18	2821	*/
mbed_official	146:f64d43ff0c18	2822	//@{
mbed_official	146:f64d43ff0c18	2823	#define BP_FTM_COMBINE_DECAPEN2 (18U) //!< Bit position for FTM_COMBINE_DECAPEN2.
mbed_official	146:f64d43ff0c18	2824	#define BM_FTM_COMBINE_DECAPEN2 (0x00040000U) //!< Bit mask for FTM_COMBINE_DECAPEN2.
mbed_official	146:f64d43ff0c18	2825	#define BS_FTM_COMBINE_DECAPEN2 (1U) //!< Bit field size in bits for FTM_COMBINE_DECAPEN2.
mbed_official	146:f64d43ff0c18	2826
mbed_official	146:f64d43ff0c18	2827	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2828	//! @brief Read current value of the FTM_COMBINE_DECAPEN2 field.
mbed_official	146:f64d43ff0c18	2829	#define BR_FTM_COMBINE_DECAPEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN2))
mbed_official	146:f64d43ff0c18	2830	#endif
mbed_official	146:f64d43ff0c18	2831
mbed_official	146:f64d43ff0c18	2832	//! @brief Format value for bitfield FTM_COMBINE_DECAPEN2.
mbed_official	146:f64d43ff0c18	2833	#define BF_FTM_COMBINE_DECAPEN2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAPEN2), uint32_t) & BM_FTM_COMBINE_DECAPEN2)
mbed_official	146:f64d43ff0c18	2834
mbed_official	146:f64d43ff0c18	2835	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2836	//! @brief Set the DECAPEN2 field to a new value.
mbed_official	146:f64d43ff0c18	2837	#define BW_FTM_COMBINE_DECAPEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN2) = (v))
mbed_official	146:f64d43ff0c18	2838	#endif
mbed_official	146:f64d43ff0c18	2839	//@}
mbed_official	146:f64d43ff0c18	2840
mbed_official	146:f64d43ff0c18	2841	/*!
mbed_official	146:f64d43ff0c18	2842	* @name Register FTM_COMBINE, field DECAP2[19] (RW)
mbed_official	146:f64d43ff0c18	2843	*
mbed_official	146:f64d43ff0c18	2844	* Enables the capture of the FTM counter value according to the channel (n)
mbed_official	146:f64d43ff0c18	2845	* input event and the configuration of the dual edge capture bits. This field
mbed_official	146:f64d43ff0c18	2846	* applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
mbed_official	146:f64d43ff0c18	2847	* hardware if dual edge capture - one-shot mode is selected and when the capture
mbed_official	146:f64d43ff0c18	2848	* of channel (n+1) event is made.
mbed_official	146:f64d43ff0c18	2849	*
mbed_official	146:f64d43ff0c18	2850	* Values:
mbed_official	146:f64d43ff0c18	2851	* - 0 - The dual edge captures are inactive.
mbed_official	146:f64d43ff0c18	2852	* - 1 - The dual edge captures are active.
mbed_official	146:f64d43ff0c18	2853	*/
mbed_official	146:f64d43ff0c18	2854	//@{
mbed_official	146:f64d43ff0c18	2855	#define BP_FTM_COMBINE_DECAP2 (19U) //!< Bit position for FTM_COMBINE_DECAP2.
mbed_official	146:f64d43ff0c18	2856	#define BM_FTM_COMBINE_DECAP2 (0x00080000U) //!< Bit mask for FTM_COMBINE_DECAP2.
mbed_official	146:f64d43ff0c18	2857	#define BS_FTM_COMBINE_DECAP2 (1U) //!< Bit field size in bits for FTM_COMBINE_DECAP2.
mbed_official	146:f64d43ff0c18	2858
mbed_official	146:f64d43ff0c18	2859	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2860	//! @brief Read current value of the FTM_COMBINE_DECAP2 field.
mbed_official	146:f64d43ff0c18	2861	#define BR_FTM_COMBINE_DECAP2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP2))
mbed_official	146:f64d43ff0c18	2862	#endif
mbed_official	146:f64d43ff0c18	2863
mbed_official	146:f64d43ff0c18	2864	//! @brief Format value for bitfield FTM_COMBINE_DECAP2.
mbed_official	146:f64d43ff0c18	2865	#define BF_FTM_COMBINE_DECAP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAP2), uint32_t) & BM_FTM_COMBINE_DECAP2)
mbed_official	146:f64d43ff0c18	2866
mbed_official	146:f64d43ff0c18	2867	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2868	//! @brief Set the DECAP2 field to a new value.
mbed_official	146:f64d43ff0c18	2869	#define BW_FTM_COMBINE_DECAP2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP2) = (v))
mbed_official	146:f64d43ff0c18	2870	#endif
mbed_official	146:f64d43ff0c18	2871	//@}
mbed_official	146:f64d43ff0c18	2872
mbed_official	146:f64d43ff0c18	2873	/*!
mbed_official	146:f64d43ff0c18	2874	* @name Register FTM_COMBINE, field DTEN2[20] (RW)
mbed_official	146:f64d43ff0c18	2875	*
mbed_official	146:f64d43ff0c18	2876	* Enables the deadtime insertion in the channels (n) and (n+1). This field is
mbed_official	146:f64d43ff0c18	2877	* write protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	2878	*
mbed_official	146:f64d43ff0c18	2879	* Values:
mbed_official	146:f64d43ff0c18	2880	* - 0 - The deadtime insertion in this pair of channels is disabled.
mbed_official	146:f64d43ff0c18	2881	* - 1 - The deadtime insertion in this pair of channels is enabled.
mbed_official	146:f64d43ff0c18	2882	*/
mbed_official	146:f64d43ff0c18	2883	//@{
mbed_official	146:f64d43ff0c18	2884	#define BP_FTM_COMBINE_DTEN2 (20U) //!< Bit position for FTM_COMBINE_DTEN2.
mbed_official	146:f64d43ff0c18	2885	#define BM_FTM_COMBINE_DTEN2 (0x00100000U) //!< Bit mask for FTM_COMBINE_DTEN2.
mbed_official	146:f64d43ff0c18	2886	#define BS_FTM_COMBINE_DTEN2 (1U) //!< Bit field size in bits for FTM_COMBINE_DTEN2.
mbed_official	146:f64d43ff0c18	2887
mbed_official	146:f64d43ff0c18	2888	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2889	//! @brief Read current value of the FTM_COMBINE_DTEN2 field.
mbed_official	146:f64d43ff0c18	2890	#define BR_FTM_COMBINE_DTEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN2))
mbed_official	146:f64d43ff0c18	2891	#endif
mbed_official	146:f64d43ff0c18	2892
mbed_official	146:f64d43ff0c18	2893	//! @brief Format value for bitfield FTM_COMBINE_DTEN2.
mbed_official	146:f64d43ff0c18	2894	#define BF_FTM_COMBINE_DTEN2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DTEN2), uint32_t) & BM_FTM_COMBINE_DTEN2)
mbed_official	146:f64d43ff0c18	2895
mbed_official	146:f64d43ff0c18	2896	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2897	//! @brief Set the DTEN2 field to a new value.
mbed_official	146:f64d43ff0c18	2898	#define BW_FTM_COMBINE_DTEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN2) = (v))
mbed_official	146:f64d43ff0c18	2899	#endif
mbed_official	146:f64d43ff0c18	2900	//@}
mbed_official	146:f64d43ff0c18	2901
mbed_official	146:f64d43ff0c18	2902	/*!
mbed_official	146:f64d43ff0c18	2903	* @name Register FTM_COMBINE, field SYNCEN2[21] (RW)
mbed_official	146:f64d43ff0c18	2904	*
mbed_official	146:f64d43ff0c18	2905	* Enables PWM synchronization of registers C(n)V and C(n+1)V.
mbed_official	146:f64d43ff0c18	2906	*
mbed_official	146:f64d43ff0c18	2907	* Values:
mbed_official	146:f64d43ff0c18	2908	* - 0 - The PWM synchronization in this pair of channels is disabled.
mbed_official	146:f64d43ff0c18	2909	* - 1 - The PWM synchronization in this pair of channels is enabled.
mbed_official	146:f64d43ff0c18	2910	*/
mbed_official	146:f64d43ff0c18	2911	//@{
mbed_official	146:f64d43ff0c18	2912	#define BP_FTM_COMBINE_SYNCEN2 (21U) //!< Bit position for FTM_COMBINE_SYNCEN2.
mbed_official	146:f64d43ff0c18	2913	#define BM_FTM_COMBINE_SYNCEN2 (0x00200000U) //!< Bit mask for FTM_COMBINE_SYNCEN2.
mbed_official	146:f64d43ff0c18	2914	#define BS_FTM_COMBINE_SYNCEN2 (1U) //!< Bit field size in bits for FTM_COMBINE_SYNCEN2.
mbed_official	146:f64d43ff0c18	2915
mbed_official	146:f64d43ff0c18	2916	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2917	//! @brief Read current value of the FTM_COMBINE_SYNCEN2 field.
mbed_official	146:f64d43ff0c18	2918	#define BR_FTM_COMBINE_SYNCEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN2))
mbed_official	146:f64d43ff0c18	2919	#endif
mbed_official	146:f64d43ff0c18	2920
mbed_official	146:f64d43ff0c18	2921	//! @brief Format value for bitfield FTM_COMBINE_SYNCEN2.
mbed_official	146:f64d43ff0c18	2922	#define BF_FTM_COMBINE_SYNCEN2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_SYNCEN2), uint32_t) & BM_FTM_COMBINE_SYNCEN2)
mbed_official	146:f64d43ff0c18	2923
mbed_official	146:f64d43ff0c18	2924	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2925	//! @brief Set the SYNCEN2 field to a new value.
mbed_official	146:f64d43ff0c18	2926	#define BW_FTM_COMBINE_SYNCEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN2) = (v))
mbed_official	146:f64d43ff0c18	2927	#endif
mbed_official	146:f64d43ff0c18	2928	//@}
mbed_official	146:f64d43ff0c18	2929
mbed_official	146:f64d43ff0c18	2930	/*!
mbed_official	146:f64d43ff0c18	2931	* @name Register FTM_COMBINE, field FAULTEN2[22] (RW)
mbed_official	146:f64d43ff0c18	2932	*
mbed_official	146:f64d43ff0c18	2933	* Enables the fault control in channels (n) and (n+1). This field is write
mbed_official	146:f64d43ff0c18	2934	* protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	2935	*
mbed_official	146:f64d43ff0c18	2936	* Values:
mbed_official	146:f64d43ff0c18	2937	* - 0 - The fault control in this pair of channels is disabled.
mbed_official	146:f64d43ff0c18	2938	* - 1 - The fault control in this pair of channels is enabled.
mbed_official	146:f64d43ff0c18	2939	*/
mbed_official	146:f64d43ff0c18	2940	//@{
mbed_official	146:f64d43ff0c18	2941	#define BP_FTM_COMBINE_FAULTEN2 (22U) //!< Bit position for FTM_COMBINE_FAULTEN2.
mbed_official	146:f64d43ff0c18	2942	#define BM_FTM_COMBINE_FAULTEN2 (0x00400000U) //!< Bit mask for FTM_COMBINE_FAULTEN2.
mbed_official	146:f64d43ff0c18	2943	#define BS_FTM_COMBINE_FAULTEN2 (1U) //!< Bit field size in bits for FTM_COMBINE_FAULTEN2.
mbed_official	146:f64d43ff0c18	2944
mbed_official	146:f64d43ff0c18	2945	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2946	//! @brief Read current value of the FTM_COMBINE_FAULTEN2 field.
mbed_official	146:f64d43ff0c18	2947	#define BR_FTM_COMBINE_FAULTEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN2))
mbed_official	146:f64d43ff0c18	2948	#endif
mbed_official	146:f64d43ff0c18	2949
mbed_official	146:f64d43ff0c18	2950	//! @brief Format value for bitfield FTM_COMBINE_FAULTEN2.
mbed_official	146:f64d43ff0c18	2951	#define BF_FTM_COMBINE_FAULTEN2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_FAULTEN2), uint32_t) & BM_FTM_COMBINE_FAULTEN2)
mbed_official	146:f64d43ff0c18	2952
mbed_official	146:f64d43ff0c18	2953	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2954	//! @brief Set the FAULTEN2 field to a new value.
mbed_official	146:f64d43ff0c18	2955	#define BW_FTM_COMBINE_FAULTEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN2) = (v))
mbed_official	146:f64d43ff0c18	2956	#endif
mbed_official	146:f64d43ff0c18	2957	//@}
mbed_official	146:f64d43ff0c18	2958
mbed_official	146:f64d43ff0c18	2959	/*!
mbed_official	146:f64d43ff0c18	2960	* @name Register FTM_COMBINE, field COMBINE3[24] (RW)
mbed_official	146:f64d43ff0c18	2961	*
mbed_official	146:f64d43ff0c18	2962	* Enables the combine feature for channels (n) and (n+1). This field is write
mbed_official	146:f64d43ff0c18	2963	* protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	2964	*
mbed_official	146:f64d43ff0c18	2965	* Values:
mbed_official	146:f64d43ff0c18	2966	* - 0 - Channels (n) and (n+1) are independent.
mbed_official	146:f64d43ff0c18	2967	* - 1 - Channels (n) and (n+1) are combined.
mbed_official	146:f64d43ff0c18	2968	*/
mbed_official	146:f64d43ff0c18	2969	//@{
mbed_official	146:f64d43ff0c18	2970	#define BP_FTM_COMBINE_COMBINE3 (24U) //!< Bit position for FTM_COMBINE_COMBINE3.
mbed_official	146:f64d43ff0c18	2971	#define BM_FTM_COMBINE_COMBINE3 (0x01000000U) //!< Bit mask for FTM_COMBINE_COMBINE3.
mbed_official	146:f64d43ff0c18	2972	#define BS_FTM_COMBINE_COMBINE3 (1U) //!< Bit field size in bits for FTM_COMBINE_COMBINE3.
mbed_official	146:f64d43ff0c18	2973
mbed_official	146:f64d43ff0c18	2974	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2975	//! @brief Read current value of the FTM_COMBINE_COMBINE3 field.
mbed_official	146:f64d43ff0c18	2976	#define BR_FTM_COMBINE_COMBINE3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE3))
mbed_official	146:f64d43ff0c18	2977	#endif
mbed_official	146:f64d43ff0c18	2978
mbed_official	146:f64d43ff0c18	2979	//! @brief Format value for bitfield FTM_COMBINE_COMBINE3.
mbed_official	146:f64d43ff0c18	2980	#define BF_FTM_COMBINE_COMBINE3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMBINE3), uint32_t) & BM_FTM_COMBINE_COMBINE3)
mbed_official	146:f64d43ff0c18	2981
mbed_official	146:f64d43ff0c18	2982	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2983	//! @brief Set the COMBINE3 field to a new value.
mbed_official	146:f64d43ff0c18	2984	#define BW_FTM_COMBINE_COMBINE3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE3) = (v))
mbed_official	146:f64d43ff0c18	2985	#endif
mbed_official	146:f64d43ff0c18	2986	//@}
mbed_official	146:f64d43ff0c18	2987
mbed_official	146:f64d43ff0c18	2988	/*!
mbed_official	146:f64d43ff0c18	2989	* @name Register FTM_COMBINE, field COMP3[25] (RW)
mbed_official	146:f64d43ff0c18	2990	*
mbed_official	146:f64d43ff0c18	2991	* Enables Complementary mode for the combined channels. In Complementary mode
mbed_official	146:f64d43ff0c18	2992	* the channel (n+1) output is the inverse of the channel (n) output. This field
mbed_official	146:f64d43ff0c18	2993	* is write protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	2994	*
mbed_official	146:f64d43ff0c18	2995	* Values:
mbed_official	146:f64d43ff0c18	2996	* - 0 - The channel (n+1) output is the same as the channel (n) output.
mbed_official	146:f64d43ff0c18	2997	* - 1 - The channel (n+1) output is the complement of the channel (n) output.
mbed_official	146:f64d43ff0c18	2998	*/
mbed_official	146:f64d43ff0c18	2999	//@{
mbed_official	146:f64d43ff0c18	3000	#define BP_FTM_COMBINE_COMP3 (25U) //!< Bit position for FTM_COMBINE_COMP3.
mbed_official	146:f64d43ff0c18	3001	#define BM_FTM_COMBINE_COMP3 (0x02000000U) //!< Bit mask for FTM_COMBINE_COMP3.
mbed_official	146:f64d43ff0c18	3002	#define BS_FTM_COMBINE_COMP3 (1U) //!< Bit field size in bits for FTM_COMBINE_COMP3.
mbed_official	146:f64d43ff0c18	3003
mbed_official	146:f64d43ff0c18	3004	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3005	//! @brief Read current value of the FTM_COMBINE_COMP3 field.
mbed_official	146:f64d43ff0c18	3006	#define BR_FTM_COMBINE_COMP3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP3))
mbed_official	146:f64d43ff0c18	3007	#endif
mbed_official	146:f64d43ff0c18	3008
mbed_official	146:f64d43ff0c18	3009	//! @brief Format value for bitfield FTM_COMBINE_COMP3.
mbed_official	146:f64d43ff0c18	3010	#define BF_FTM_COMBINE_COMP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMP3), uint32_t) & BM_FTM_COMBINE_COMP3)
mbed_official	146:f64d43ff0c18	3011
mbed_official	146:f64d43ff0c18	3012	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3013	//! @brief Set the COMP3 field to a new value.
mbed_official	146:f64d43ff0c18	3014	#define BW_FTM_COMBINE_COMP3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP3) = (v))
mbed_official	146:f64d43ff0c18	3015	#endif
mbed_official	146:f64d43ff0c18	3016	//@}
mbed_official	146:f64d43ff0c18	3017
mbed_official	146:f64d43ff0c18	3018	/*!
mbed_official	146:f64d43ff0c18	3019	* @name Register FTM_COMBINE, field DECAPEN3[26] (RW)
mbed_official	146:f64d43ff0c18	3020	*
mbed_official	146:f64d43ff0c18	3021	* Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
mbed_official	146:f64d43ff0c18	3022	* reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
mbed_official	146:f64d43ff0c18	3023	* Dual Edge Capture mode according to #ModeSel1Table. This field applies only
mbed_official	146:f64d43ff0c18	3024	* when FTMEN = 1. This field is write protected. It can be written only when
mbed_official	146:f64d43ff0c18	3025	* MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	3026	*
mbed_official	146:f64d43ff0c18	3027	* Values:
mbed_official	146:f64d43ff0c18	3028	* - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
mbed_official	146:f64d43ff0c18	3029	* - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
mbed_official	146:f64d43ff0c18	3030	*/
mbed_official	146:f64d43ff0c18	3031	//@{
mbed_official	146:f64d43ff0c18	3032	#define BP_FTM_COMBINE_DECAPEN3 (26U) //!< Bit position for FTM_COMBINE_DECAPEN3.
mbed_official	146:f64d43ff0c18	3033	#define BM_FTM_COMBINE_DECAPEN3 (0x04000000U) //!< Bit mask for FTM_COMBINE_DECAPEN3.
mbed_official	146:f64d43ff0c18	3034	#define BS_FTM_COMBINE_DECAPEN3 (1U) //!< Bit field size in bits for FTM_COMBINE_DECAPEN3.
mbed_official	146:f64d43ff0c18	3035
mbed_official	146:f64d43ff0c18	3036	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3037	//! @brief Read current value of the FTM_COMBINE_DECAPEN3 field.
mbed_official	146:f64d43ff0c18	3038	#define BR_FTM_COMBINE_DECAPEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN3))
mbed_official	146:f64d43ff0c18	3039	#endif
mbed_official	146:f64d43ff0c18	3040
mbed_official	146:f64d43ff0c18	3041	//! @brief Format value for bitfield FTM_COMBINE_DECAPEN3.
mbed_official	146:f64d43ff0c18	3042	#define BF_FTM_COMBINE_DECAPEN3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAPEN3), uint32_t) & BM_FTM_COMBINE_DECAPEN3)
mbed_official	146:f64d43ff0c18	3043
mbed_official	146:f64d43ff0c18	3044	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3045	//! @brief Set the DECAPEN3 field to a new value.
mbed_official	146:f64d43ff0c18	3046	#define BW_FTM_COMBINE_DECAPEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN3) = (v))
mbed_official	146:f64d43ff0c18	3047	#endif
mbed_official	146:f64d43ff0c18	3048	//@}
mbed_official	146:f64d43ff0c18	3049
mbed_official	146:f64d43ff0c18	3050	/*!
mbed_official	146:f64d43ff0c18	3051	* @name Register FTM_COMBINE, field DECAP3[27] (RW)
mbed_official	146:f64d43ff0c18	3052	*
mbed_official	146:f64d43ff0c18	3053	* Enables the capture of the FTM counter value according to the channel (n)
mbed_official	146:f64d43ff0c18	3054	* input event and the configuration of the dual edge capture bits. This field
mbed_official	146:f64d43ff0c18	3055	* applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
mbed_official	146:f64d43ff0c18	3056	* hardware if dual edge capture - one-shot mode is selected and when the capture
mbed_official	146:f64d43ff0c18	3057	* of channel (n+1) event is made.
mbed_official	146:f64d43ff0c18	3058	*
mbed_official	146:f64d43ff0c18	3059	* Values:
mbed_official	146:f64d43ff0c18	3060	* - 0 - The dual edge captures are inactive.
mbed_official	146:f64d43ff0c18	3061	* - 1 - The dual edge captures are active.
mbed_official	146:f64d43ff0c18	3062	*/
mbed_official	146:f64d43ff0c18	3063	//@{
mbed_official	146:f64d43ff0c18	3064	#define BP_FTM_COMBINE_DECAP3 (27U) //!< Bit position for FTM_COMBINE_DECAP3.
mbed_official	146:f64d43ff0c18	3065	#define BM_FTM_COMBINE_DECAP3 (0x08000000U) //!< Bit mask for FTM_COMBINE_DECAP3.
mbed_official	146:f64d43ff0c18	3066	#define BS_FTM_COMBINE_DECAP3 (1U) //!< Bit field size in bits for FTM_COMBINE_DECAP3.
mbed_official	146:f64d43ff0c18	3067
mbed_official	146:f64d43ff0c18	3068	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3069	//! @brief Read current value of the FTM_COMBINE_DECAP3 field.
mbed_official	146:f64d43ff0c18	3070	#define BR_FTM_COMBINE_DECAP3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP3))
mbed_official	146:f64d43ff0c18	3071	#endif
mbed_official	146:f64d43ff0c18	3072
mbed_official	146:f64d43ff0c18	3073	//! @brief Format value for bitfield FTM_COMBINE_DECAP3.
mbed_official	146:f64d43ff0c18	3074	#define BF_FTM_COMBINE_DECAP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAP3), uint32_t) & BM_FTM_COMBINE_DECAP3)
mbed_official	146:f64d43ff0c18	3075
mbed_official	146:f64d43ff0c18	3076	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3077	//! @brief Set the DECAP3 field to a new value.
mbed_official	146:f64d43ff0c18	3078	#define BW_FTM_COMBINE_DECAP3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP3) = (v))
mbed_official	146:f64d43ff0c18	3079	#endif
mbed_official	146:f64d43ff0c18	3080	//@}
mbed_official	146:f64d43ff0c18	3081
mbed_official	146:f64d43ff0c18	3082	/*!
mbed_official	146:f64d43ff0c18	3083	* @name Register FTM_COMBINE, field DTEN3[28] (RW)
mbed_official	146:f64d43ff0c18	3084	*
mbed_official	146:f64d43ff0c18	3085	* Enables the deadtime insertion in the channels (n) and (n+1). This field is
mbed_official	146:f64d43ff0c18	3086	* write protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	3087	*
mbed_official	146:f64d43ff0c18	3088	* Values:
mbed_official	146:f64d43ff0c18	3089	* - 0 - The deadtime insertion in this pair of channels is disabled.
mbed_official	146:f64d43ff0c18	3090	* - 1 - The deadtime insertion in this pair of channels is enabled.
mbed_official	146:f64d43ff0c18	3091	*/
mbed_official	146:f64d43ff0c18	3092	//@{
mbed_official	146:f64d43ff0c18	3093	#define BP_FTM_COMBINE_DTEN3 (28U) //!< Bit position for FTM_COMBINE_DTEN3.
mbed_official	146:f64d43ff0c18	3094	#define BM_FTM_COMBINE_DTEN3 (0x10000000U) //!< Bit mask for FTM_COMBINE_DTEN3.
mbed_official	146:f64d43ff0c18	3095	#define BS_FTM_COMBINE_DTEN3 (1U) //!< Bit field size in bits for FTM_COMBINE_DTEN3.
mbed_official	146:f64d43ff0c18	3096
mbed_official	146:f64d43ff0c18	3097	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3098	//! @brief Read current value of the FTM_COMBINE_DTEN3 field.
mbed_official	146:f64d43ff0c18	3099	#define BR_FTM_COMBINE_DTEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN3))
mbed_official	146:f64d43ff0c18	3100	#endif
mbed_official	146:f64d43ff0c18	3101
mbed_official	146:f64d43ff0c18	3102	//! @brief Format value for bitfield FTM_COMBINE_DTEN3.
mbed_official	146:f64d43ff0c18	3103	#define BF_FTM_COMBINE_DTEN3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DTEN3), uint32_t) & BM_FTM_COMBINE_DTEN3)
mbed_official	146:f64d43ff0c18	3104
mbed_official	146:f64d43ff0c18	3105	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3106	//! @brief Set the DTEN3 field to a new value.
mbed_official	146:f64d43ff0c18	3107	#define BW_FTM_COMBINE_DTEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN3) = (v))
mbed_official	146:f64d43ff0c18	3108	#endif
mbed_official	146:f64d43ff0c18	3109	//@}
mbed_official	146:f64d43ff0c18	3110
mbed_official	146:f64d43ff0c18	3111	/*!
mbed_official	146:f64d43ff0c18	3112	* @name Register FTM_COMBINE, field SYNCEN3[29] (RW)
mbed_official	146:f64d43ff0c18	3113	*
mbed_official	146:f64d43ff0c18	3114	* Enables PWM synchronization of registers C(n)V and C(n+1)V.
mbed_official	146:f64d43ff0c18	3115	*
mbed_official	146:f64d43ff0c18	3116	* Values:
mbed_official	146:f64d43ff0c18	3117	* - 0 - The PWM synchronization in this pair of channels is disabled.
mbed_official	146:f64d43ff0c18	3118	* - 1 - The PWM synchronization in this pair of channels is enabled.
mbed_official	146:f64d43ff0c18	3119	*/
mbed_official	146:f64d43ff0c18	3120	//@{
mbed_official	146:f64d43ff0c18	3121	#define BP_FTM_COMBINE_SYNCEN3 (29U) //!< Bit position for FTM_COMBINE_SYNCEN3.
mbed_official	146:f64d43ff0c18	3122	#define BM_FTM_COMBINE_SYNCEN3 (0x20000000U) //!< Bit mask for FTM_COMBINE_SYNCEN3.
mbed_official	146:f64d43ff0c18	3123	#define BS_FTM_COMBINE_SYNCEN3 (1U) //!< Bit field size in bits for FTM_COMBINE_SYNCEN3.
mbed_official	146:f64d43ff0c18	3124
mbed_official	146:f64d43ff0c18	3125	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3126	//! @brief Read current value of the FTM_COMBINE_SYNCEN3 field.
mbed_official	146:f64d43ff0c18	3127	#define BR_FTM_COMBINE_SYNCEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN3))
mbed_official	146:f64d43ff0c18	3128	#endif
mbed_official	146:f64d43ff0c18	3129
mbed_official	146:f64d43ff0c18	3130	//! @brief Format value for bitfield FTM_COMBINE_SYNCEN3.
mbed_official	146:f64d43ff0c18	3131	#define BF_FTM_COMBINE_SYNCEN3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_SYNCEN3), uint32_t) & BM_FTM_COMBINE_SYNCEN3)
mbed_official	146:f64d43ff0c18	3132
mbed_official	146:f64d43ff0c18	3133	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3134	//! @brief Set the SYNCEN3 field to a new value.
mbed_official	146:f64d43ff0c18	3135	#define BW_FTM_COMBINE_SYNCEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN3) = (v))
mbed_official	146:f64d43ff0c18	3136	#endif
mbed_official	146:f64d43ff0c18	3137	//@}
mbed_official	146:f64d43ff0c18	3138
mbed_official	146:f64d43ff0c18	3139	/*!
mbed_official	146:f64d43ff0c18	3140	* @name Register FTM_COMBINE, field FAULTEN3[30] (RW)
mbed_official	146:f64d43ff0c18	3141	*
mbed_official	146:f64d43ff0c18	3142	* Enables the fault control in channels (n) and (n+1). This field is write
mbed_official	146:f64d43ff0c18	3143	* protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	3144	*
mbed_official	146:f64d43ff0c18	3145	* Values:
mbed_official	146:f64d43ff0c18	3146	* - 0 - The fault control in this pair of channels is disabled.
mbed_official	146:f64d43ff0c18	3147	* - 1 - The fault control in this pair of channels is enabled.
mbed_official	146:f64d43ff0c18	3148	*/
mbed_official	146:f64d43ff0c18	3149	//@{
mbed_official	146:f64d43ff0c18	3150	#define BP_FTM_COMBINE_FAULTEN3 (30U) //!< Bit position for FTM_COMBINE_FAULTEN3.
mbed_official	146:f64d43ff0c18	3151	#define BM_FTM_COMBINE_FAULTEN3 (0x40000000U) //!< Bit mask for FTM_COMBINE_FAULTEN3.
mbed_official	146:f64d43ff0c18	3152	#define BS_FTM_COMBINE_FAULTEN3 (1U) //!< Bit field size in bits for FTM_COMBINE_FAULTEN3.
mbed_official	146:f64d43ff0c18	3153
mbed_official	146:f64d43ff0c18	3154	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3155	//! @brief Read current value of the FTM_COMBINE_FAULTEN3 field.
mbed_official	146:f64d43ff0c18	3156	#define BR_FTM_COMBINE_FAULTEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN3))
mbed_official	146:f64d43ff0c18	3157	#endif
mbed_official	146:f64d43ff0c18	3158
mbed_official	146:f64d43ff0c18	3159	//! @brief Format value for bitfield FTM_COMBINE_FAULTEN3.
mbed_official	146:f64d43ff0c18	3160	#define BF_FTM_COMBINE_FAULTEN3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_FAULTEN3), uint32_t) & BM_FTM_COMBINE_FAULTEN3)
mbed_official	146:f64d43ff0c18	3161
mbed_official	146:f64d43ff0c18	3162	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3163	//! @brief Set the FAULTEN3 field to a new value.
mbed_official	146:f64d43ff0c18	3164	#define BW_FTM_COMBINE_FAULTEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN3) = (v))
mbed_official	146:f64d43ff0c18	3165	#endif
mbed_official	146:f64d43ff0c18	3166	//@}
mbed_official	146:f64d43ff0c18	3167
mbed_official	146:f64d43ff0c18	3168	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	3169	// HW_FTM_DEADTIME - Deadtime Insertion Control
mbed_official	146:f64d43ff0c18	3170	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	3171
mbed_official	146:f64d43ff0c18	3172	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3173	/*!
mbed_official	146:f64d43ff0c18	3174	* @brief HW_FTM_DEADTIME - Deadtime Insertion Control (RW)
mbed_official	146:f64d43ff0c18	3175	*
mbed_official	146:f64d43ff0c18	3176	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	3177	*
mbed_official	146:f64d43ff0c18	3178	* This register selects the deadtime prescaler factor and deadtime value. All
mbed_official	146:f64d43ff0c18	3179	* FTM channels use this clock prescaler and this deadtime value for the deadtime
mbed_official	146:f64d43ff0c18	3180	* insertion.
mbed_official	146:f64d43ff0c18	3181	*/
mbed_official	146:f64d43ff0c18	3182	typedef union _hw_ftm_deadtime
mbed_official	146:f64d43ff0c18	3183	{
mbed_official	146:f64d43ff0c18	3184	uint32_t U;
mbed_official	146:f64d43ff0c18	3185	struct _hw_ftm_deadtime_bitfields
mbed_official	146:f64d43ff0c18	3186	{
mbed_official	146:f64d43ff0c18	3187	uint32_t DTVAL : 6; //!< [5:0] Deadtime Value
mbed_official	146:f64d43ff0c18	3188	uint32_t DTPS : 2; //!< [7:6] Deadtime Prescaler Value
mbed_official	146:f64d43ff0c18	3189	uint32_t RESERVED0 : 24; //!< [31:8]
mbed_official	146:f64d43ff0c18	3190	} B;
mbed_official	146:f64d43ff0c18	3191	} hw_ftm_deadtime_t;
mbed_official	146:f64d43ff0c18	3192	#endif
mbed_official	146:f64d43ff0c18	3193
mbed_official	146:f64d43ff0c18	3194	/*!
mbed_official	146:f64d43ff0c18	3195	* @name Constants and macros for entire FTM_DEADTIME register
mbed_official	146:f64d43ff0c18	3196	*/
mbed_official	146:f64d43ff0c18	3197	//@{
mbed_official	146:f64d43ff0c18	3198	#define HW_FTM_DEADTIME_ADDR(x) (REGS_FTM_BASE(x) + 0x68U)
mbed_official	146:f64d43ff0c18	3199
mbed_official	146:f64d43ff0c18	3200	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3201	#define HW_FTM_DEADTIME(x) ((__IO hw_ftm_deadtime_t ) HW_FTM_DEADTIME_ADDR(x))
mbed_official	146:f64d43ff0c18	3202	#define HW_FTM_DEADTIME_RD(x) (HW_FTM_DEADTIME(x).U)
mbed_official	146:f64d43ff0c18	3203	#define HW_FTM_DEADTIME_WR(x, v) (HW_FTM_DEADTIME(x).U = (v))
mbed_official	146:f64d43ff0c18	3204	#define HW_FTM_DEADTIME_SET(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	3205	#define HW_FTM_DEADTIME_CLR(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	3206	#define HW_FTM_DEADTIME_TOG(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	3207	#endif
mbed_official	146:f64d43ff0c18	3208	//@}
mbed_official	146:f64d43ff0c18	3209
mbed_official	146:f64d43ff0c18	3210	/*
mbed_official	146:f64d43ff0c18	3211	* Constants & macros for individual FTM_DEADTIME bitfields
mbed_official	146:f64d43ff0c18	3212	*/
mbed_official	146:f64d43ff0c18	3213
mbed_official	146:f64d43ff0c18	3214	/*!
mbed_official	146:f64d43ff0c18	3215	* @name Register FTM_DEADTIME, field DTVAL[5:0] (RW)
mbed_official	146:f64d43ff0c18	3216	*
mbed_official	146:f64d43ff0c18	3217	* Selects the deadtime insertion value for the deadtime counter. The deadtime
mbed_official	146:f64d43ff0c18	3218	* counter is clocked by a scaled version of the system clock. See the description
mbed_official	146:f64d43ff0c18	3219	* of DTPS. Deadtime insert value = (DTPS * DTVAL). DTVAL selects the number of
mbed_official	146:f64d43ff0c18	3220	* deadtime counts inserted as follows: When DTVAL is 0, no counts are inserted.
mbed_official	146:f64d43ff0c18	3221	* When DTVAL is 1, 1 count is inserted. When DTVAL is 2, 2 counts are inserted.
mbed_official	146:f64d43ff0c18	3222	* This pattern continues up to a possible 63 counts. This field is write
mbed_official	146:f64d43ff0c18	3223	* protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	3224	*/
mbed_official	146:f64d43ff0c18	3225	//@{
mbed_official	146:f64d43ff0c18	3226	#define BP_FTM_DEADTIME_DTVAL (0U) //!< Bit position for FTM_DEADTIME_DTVAL.
mbed_official	146:f64d43ff0c18	3227	#define BM_FTM_DEADTIME_DTVAL (0x0000003FU) //!< Bit mask for FTM_DEADTIME_DTVAL.
mbed_official	146:f64d43ff0c18	3228	#define BS_FTM_DEADTIME_DTVAL (6U) //!< Bit field size in bits for FTM_DEADTIME_DTVAL.
mbed_official	146:f64d43ff0c18	3229
mbed_official	146:f64d43ff0c18	3230	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3231	//! @brief Read current value of the FTM_DEADTIME_DTVAL field.
mbed_official	146:f64d43ff0c18	3232	#define BR_FTM_DEADTIME_DTVAL(x) (HW_FTM_DEADTIME(x).B.DTVAL)
mbed_official	146:f64d43ff0c18	3233	#endif
mbed_official	146:f64d43ff0c18	3234
mbed_official	146:f64d43ff0c18	3235	//! @brief Format value for bitfield FTM_DEADTIME_DTVAL.
mbed_official	146:f64d43ff0c18	3236	#define BF_FTM_DEADTIME_DTVAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_DEADTIME_DTVAL), uint32_t) & BM_FTM_DEADTIME_DTVAL)
mbed_official	146:f64d43ff0c18	3237
mbed_official	146:f64d43ff0c18	3238	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3239	//! @brief Set the DTVAL field to a new value.
mbed_official	146:f64d43ff0c18	3240	#define BW_FTM_DEADTIME_DTVAL(x, v) (HW_FTM_DEADTIME_WR(x, (HW_FTM_DEADTIME_RD(x) & ~BM_FTM_DEADTIME_DTVAL) \| BF_FTM_DEADTIME_DTVAL(v)))
mbed_official	146:f64d43ff0c18	3241	#endif
mbed_official	146:f64d43ff0c18	3242	//@}
mbed_official	146:f64d43ff0c18	3243
mbed_official	146:f64d43ff0c18	3244	/*!
mbed_official	146:f64d43ff0c18	3245	* @name Register FTM_DEADTIME, field DTPS[7:6] (RW)
mbed_official	146:f64d43ff0c18	3246	*
mbed_official	146:f64d43ff0c18	3247	* Selects the division factor of the system clock. This prescaled clock is used
mbed_official	146:f64d43ff0c18	3248	* by the deadtime counter. This field is write protected. It can be written
mbed_official	146:f64d43ff0c18	3249	* only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	3250	*
mbed_official	146:f64d43ff0c18	3251	* Values:
mbed_official	146:f64d43ff0c18	3252	* - 0x - Divide the system clock by 1.
mbed_official	146:f64d43ff0c18	3253	* - 10 - Divide the system clock by 4.
mbed_official	146:f64d43ff0c18	3254	* - 11 - Divide the system clock by 16.
mbed_official	146:f64d43ff0c18	3255	*/
mbed_official	146:f64d43ff0c18	3256	//@{
mbed_official	146:f64d43ff0c18	3257	#define BP_FTM_DEADTIME_DTPS (6U) //!< Bit position for FTM_DEADTIME_DTPS.
mbed_official	146:f64d43ff0c18	3258	#define BM_FTM_DEADTIME_DTPS (0x000000C0U) //!< Bit mask for FTM_DEADTIME_DTPS.
mbed_official	146:f64d43ff0c18	3259	#define BS_FTM_DEADTIME_DTPS (2U) //!< Bit field size in bits for FTM_DEADTIME_DTPS.
mbed_official	146:f64d43ff0c18	3260
mbed_official	146:f64d43ff0c18	3261	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3262	//! @brief Read current value of the FTM_DEADTIME_DTPS field.
mbed_official	146:f64d43ff0c18	3263	#define BR_FTM_DEADTIME_DTPS(x) (HW_FTM_DEADTIME(x).B.DTPS)
mbed_official	146:f64d43ff0c18	3264	#endif
mbed_official	146:f64d43ff0c18	3265
mbed_official	146:f64d43ff0c18	3266	//! @brief Format value for bitfield FTM_DEADTIME_DTPS.
mbed_official	146:f64d43ff0c18	3267	#define BF_FTM_DEADTIME_DTPS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_DEADTIME_DTPS), uint32_t) & BM_FTM_DEADTIME_DTPS)
mbed_official	146:f64d43ff0c18	3268
mbed_official	146:f64d43ff0c18	3269	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3270	//! @brief Set the DTPS field to a new value.
mbed_official	146:f64d43ff0c18	3271	#define BW_FTM_DEADTIME_DTPS(x, v) (HW_FTM_DEADTIME_WR(x, (HW_FTM_DEADTIME_RD(x) & ~BM_FTM_DEADTIME_DTPS) \| BF_FTM_DEADTIME_DTPS(v)))
mbed_official	146:f64d43ff0c18	3272	#endif
mbed_official	146:f64d43ff0c18	3273	//@}
mbed_official	146:f64d43ff0c18	3274
mbed_official	146:f64d43ff0c18	3275	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	3276	// HW_FTM_EXTTRIG - FTM External Trigger
mbed_official	146:f64d43ff0c18	3277	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	3278
mbed_official	146:f64d43ff0c18	3279	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3280	/*!
mbed_official	146:f64d43ff0c18	3281	* @brief HW_FTM_EXTTRIG - FTM External Trigger (RW)
mbed_official	146:f64d43ff0c18	3282	*
mbed_official	146:f64d43ff0c18	3283	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	3284	*
mbed_official	146:f64d43ff0c18	3285	* This register: Indicates when a channel trigger was generated Enables the
mbed_official	146:f64d43ff0c18	3286	* generation of a trigger when the FTM counter is equal to its initial value
mbed_official	146:f64d43ff0c18	3287	* Selects which channels are used in the generation of the channel triggers Several
mbed_official	146:f64d43ff0c18	3288	* channels can be selected to generate multiple triggers in one PWM period.
mbed_official	146:f64d43ff0c18	3289	* Channels 6 and 7 are not used to generate channel triggers.
mbed_official	146:f64d43ff0c18	3290	*/
mbed_official	146:f64d43ff0c18	3291	typedef union _hw_ftm_exttrig
mbed_official	146:f64d43ff0c18	3292	{
mbed_official	146:f64d43ff0c18	3293	uint32_t U;
mbed_official	146:f64d43ff0c18	3294	struct _hw_ftm_exttrig_bitfields
mbed_official	146:f64d43ff0c18	3295	{
mbed_official	146:f64d43ff0c18	3296	uint32_t CH2TRIG : 1; //!< [0] Channel 2 Trigger Enable
mbed_official	146:f64d43ff0c18	3297	uint32_t CH3TRIG : 1; //!< [1] Channel 3 Trigger Enable
mbed_official	146:f64d43ff0c18	3298	uint32_t CH4TRIG : 1; //!< [2] Channel 4 Trigger Enable
mbed_official	146:f64d43ff0c18	3299	uint32_t CH5TRIG : 1; //!< [3] Channel 5 Trigger Enable
mbed_official	146:f64d43ff0c18	3300	uint32_t CH0TRIG : 1; //!< [4] Channel 0 Trigger Enable
mbed_official	146:f64d43ff0c18	3301	uint32_t CH1TRIG : 1; //!< [5] Channel 1 Trigger Enable
mbed_official	146:f64d43ff0c18	3302	uint32_t INITTRIGEN : 1; //!< [6] Initialization Trigger Enable
mbed_official	146:f64d43ff0c18	3303	uint32_t TRIGF : 1; //!< [7] Channel Trigger Flag
mbed_official	146:f64d43ff0c18	3304	uint32_t RESERVED0 : 24; //!< [31:8]
mbed_official	146:f64d43ff0c18	3305	} B;
mbed_official	146:f64d43ff0c18	3306	} hw_ftm_exttrig_t;
mbed_official	146:f64d43ff0c18	3307	#endif
mbed_official	146:f64d43ff0c18	3308
mbed_official	146:f64d43ff0c18	3309	/*!
mbed_official	146:f64d43ff0c18	3310	* @name Constants and macros for entire FTM_EXTTRIG register
mbed_official	146:f64d43ff0c18	3311	*/
mbed_official	146:f64d43ff0c18	3312	//@{
mbed_official	146:f64d43ff0c18	3313	#define HW_FTM_EXTTRIG_ADDR(x) (REGS_FTM_BASE(x) + 0x6CU)
mbed_official	146:f64d43ff0c18	3314
mbed_official	146:f64d43ff0c18	3315	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3316	#define HW_FTM_EXTTRIG(x) ((__IO hw_ftm_exttrig_t ) HW_FTM_EXTTRIG_ADDR(x))
mbed_official	146:f64d43ff0c18	3317	#define HW_FTM_EXTTRIG_RD(x) (HW_FTM_EXTTRIG(x).U)
mbed_official	146:f64d43ff0c18	3318	#define HW_FTM_EXTTRIG_WR(x, v) (HW_FTM_EXTTRIG(x).U = (v))
mbed_official	146:f64d43ff0c18	3319	#define HW_FTM_EXTTRIG_SET(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	3320	#define HW_FTM_EXTTRIG_CLR(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	3321	#define HW_FTM_EXTTRIG_TOG(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	3322	#endif
mbed_official	146:f64d43ff0c18	3323	//@}
mbed_official	146:f64d43ff0c18	3324
mbed_official	146:f64d43ff0c18	3325	/*
mbed_official	146:f64d43ff0c18	3326	* Constants & macros for individual FTM_EXTTRIG bitfields
mbed_official	146:f64d43ff0c18	3327	*/
mbed_official	146:f64d43ff0c18	3328
mbed_official	146:f64d43ff0c18	3329	/*!
mbed_official	146:f64d43ff0c18	3330	* @name Register FTM_EXTTRIG, field CH2TRIG[0] (RW)
mbed_official	146:f64d43ff0c18	3331	*
mbed_official	146:f64d43ff0c18	3332	* Enables the generation of the channel trigger when the FTM counter is equal
mbed_official	146:f64d43ff0c18	3333	* to the CnV register.
mbed_official	146:f64d43ff0c18	3334	*
mbed_official	146:f64d43ff0c18	3335	* Values:
mbed_official	146:f64d43ff0c18	3336	* - 0 - The generation of the channel trigger is disabled.
mbed_official	146:f64d43ff0c18	3337	* - 1 - The generation of the channel trigger is enabled.
mbed_official	146:f64d43ff0c18	3338	*/
mbed_official	146:f64d43ff0c18	3339	//@{
mbed_official	146:f64d43ff0c18	3340	#define BP_FTM_EXTTRIG_CH2TRIG (0U) //!< Bit position for FTM_EXTTRIG_CH2TRIG.
mbed_official	146:f64d43ff0c18	3341	#define BM_FTM_EXTTRIG_CH2TRIG (0x00000001U) //!< Bit mask for FTM_EXTTRIG_CH2TRIG.
mbed_official	146:f64d43ff0c18	3342	#define BS_FTM_EXTTRIG_CH2TRIG (1U) //!< Bit field size in bits for FTM_EXTTRIG_CH2TRIG.
mbed_official	146:f64d43ff0c18	3343
mbed_official	146:f64d43ff0c18	3344	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3345	//! @brief Read current value of the FTM_EXTTRIG_CH2TRIG field.
mbed_official	146:f64d43ff0c18	3346	#define BR_FTM_EXTTRIG_CH2TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH2TRIG))
mbed_official	146:f64d43ff0c18	3347	#endif
mbed_official	146:f64d43ff0c18	3348
mbed_official	146:f64d43ff0c18	3349	//! @brief Format value for bitfield FTM_EXTTRIG_CH2TRIG.
mbed_official	146:f64d43ff0c18	3350	#define BF_FTM_EXTTRIG_CH2TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_EXTTRIG_CH2TRIG), uint32_t) & BM_FTM_EXTTRIG_CH2TRIG)
mbed_official	146:f64d43ff0c18	3351
mbed_official	146:f64d43ff0c18	3352	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3353	//! @brief Set the CH2TRIG field to a new value.
mbed_official	146:f64d43ff0c18	3354	#define BW_FTM_EXTTRIG_CH2TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH2TRIG) = (v))
mbed_official	146:f64d43ff0c18	3355	#endif
mbed_official	146:f64d43ff0c18	3356	//@}
mbed_official	146:f64d43ff0c18	3357
mbed_official	146:f64d43ff0c18	3358	/*!
mbed_official	146:f64d43ff0c18	3359	* @name Register FTM_EXTTRIG, field CH3TRIG[1] (RW)
mbed_official	146:f64d43ff0c18	3360	*
mbed_official	146:f64d43ff0c18	3361	* Enables the generation of the channel trigger when the FTM counter is equal
mbed_official	146:f64d43ff0c18	3362	* to the CnV register.
mbed_official	146:f64d43ff0c18	3363	*
mbed_official	146:f64d43ff0c18	3364	* Values:
mbed_official	146:f64d43ff0c18	3365	* - 0 - The generation of the channel trigger is disabled.
mbed_official	146:f64d43ff0c18	3366	* - 1 - The generation of the channel trigger is enabled.
mbed_official	146:f64d43ff0c18	3367	*/
mbed_official	146:f64d43ff0c18	3368	//@{
mbed_official	146:f64d43ff0c18	3369	#define BP_FTM_EXTTRIG_CH3TRIG (1U) //!< Bit position for FTM_EXTTRIG_CH3TRIG.
mbed_official	146:f64d43ff0c18	3370	#define BM_FTM_EXTTRIG_CH3TRIG (0x00000002U) //!< Bit mask for FTM_EXTTRIG_CH3TRIG.
mbed_official	146:f64d43ff0c18	3371	#define BS_FTM_EXTTRIG_CH3TRIG (1U) //!< Bit field size in bits for FTM_EXTTRIG_CH3TRIG.
mbed_official	146:f64d43ff0c18	3372
mbed_official	146:f64d43ff0c18	3373	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3374	//! @brief Read current value of the FTM_EXTTRIG_CH3TRIG field.
mbed_official	146:f64d43ff0c18	3375	#define BR_FTM_EXTTRIG_CH3TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH3TRIG))
mbed_official	146:f64d43ff0c18	3376	#endif
mbed_official	146:f64d43ff0c18	3377
mbed_official	146:f64d43ff0c18	3378	//! @brief Format value for bitfield FTM_EXTTRIG_CH3TRIG.
mbed_official	146:f64d43ff0c18	3379	#define BF_FTM_EXTTRIG_CH3TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_EXTTRIG_CH3TRIG), uint32_t) & BM_FTM_EXTTRIG_CH3TRIG)
mbed_official	146:f64d43ff0c18	3380
mbed_official	146:f64d43ff0c18	3381	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3382	//! @brief Set the CH3TRIG field to a new value.
mbed_official	146:f64d43ff0c18	3383	#define BW_FTM_EXTTRIG_CH3TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH3TRIG) = (v))
mbed_official	146:f64d43ff0c18	3384	#endif
mbed_official	146:f64d43ff0c18	3385	//@}
mbed_official	146:f64d43ff0c18	3386
mbed_official	146:f64d43ff0c18	3387	/*!
mbed_official	146:f64d43ff0c18	3388	* @name Register FTM_EXTTRIG, field CH4TRIG[2] (RW)
mbed_official	146:f64d43ff0c18	3389	*
mbed_official	146:f64d43ff0c18	3390	* Enables the generation of the channel trigger when the FTM counter is equal
mbed_official	146:f64d43ff0c18	3391	* to the CnV register.
mbed_official	146:f64d43ff0c18	3392	*
mbed_official	146:f64d43ff0c18	3393	* Values:
mbed_official	146:f64d43ff0c18	3394	* - 0 - The generation of the channel trigger is disabled.
mbed_official	146:f64d43ff0c18	3395	* - 1 - The generation of the channel trigger is enabled.
mbed_official	146:f64d43ff0c18	3396	*/
mbed_official	146:f64d43ff0c18	3397	//@{
mbed_official	146:f64d43ff0c18	3398	#define BP_FTM_EXTTRIG_CH4TRIG (2U) //!< Bit position for FTM_EXTTRIG_CH4TRIG.
mbed_official	146:f64d43ff0c18	3399	#define BM_FTM_EXTTRIG_CH4TRIG (0x00000004U) //!< Bit mask for FTM_EXTTRIG_CH4TRIG.
mbed_official	146:f64d43ff0c18	3400	#define BS_FTM_EXTTRIG_CH4TRIG (1U) //!< Bit field size in bits for FTM_EXTTRIG_CH4TRIG.
mbed_official	146:f64d43ff0c18	3401
mbed_official	146:f64d43ff0c18	3402	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3403	//! @brief Read current value of the FTM_EXTTRIG_CH4TRIG field.
mbed_official	146:f64d43ff0c18	3404	#define BR_FTM_EXTTRIG_CH4TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH4TRIG))
mbed_official	146:f64d43ff0c18	3405	#endif
mbed_official	146:f64d43ff0c18	3406
mbed_official	146:f64d43ff0c18	3407	//! @brief Format value for bitfield FTM_EXTTRIG_CH4TRIG.
mbed_official	146:f64d43ff0c18	3408	#define BF_FTM_EXTTRIG_CH4TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_EXTTRIG_CH4TRIG), uint32_t) & BM_FTM_EXTTRIG_CH4TRIG)
mbed_official	146:f64d43ff0c18	3409
mbed_official	146:f64d43ff0c18	3410	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3411	//! @brief Set the CH4TRIG field to a new value.
mbed_official	146:f64d43ff0c18	3412	#define BW_FTM_EXTTRIG_CH4TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH4TRIG) = (v))
mbed_official	146:f64d43ff0c18	3413	#endif
mbed_official	146:f64d43ff0c18	3414	//@}
mbed_official	146:f64d43ff0c18	3415
mbed_official	146:f64d43ff0c18	3416	/*!
mbed_official	146:f64d43ff0c18	3417	* @name Register FTM_EXTTRIG, field CH5TRIG[3] (RW)
mbed_official	146:f64d43ff0c18	3418	*
mbed_official	146:f64d43ff0c18	3419	* Enables the generation of the channel trigger when the FTM counter is equal
mbed_official	146:f64d43ff0c18	3420	* to the CnV register.
mbed_official	146:f64d43ff0c18	3421	*
mbed_official	146:f64d43ff0c18	3422	* Values:
mbed_official	146:f64d43ff0c18	3423	* - 0 - The generation of the channel trigger is disabled.
mbed_official	146:f64d43ff0c18	3424	* - 1 - The generation of the channel trigger is enabled.
mbed_official	146:f64d43ff0c18	3425	*/
mbed_official	146:f64d43ff0c18	3426	//@{
mbed_official	146:f64d43ff0c18	3427	#define BP_FTM_EXTTRIG_CH5TRIG (3U) //!< Bit position for FTM_EXTTRIG_CH5TRIG.
mbed_official	146:f64d43ff0c18	3428	#define BM_FTM_EXTTRIG_CH5TRIG (0x00000008U) //!< Bit mask for FTM_EXTTRIG_CH5TRIG.
mbed_official	146:f64d43ff0c18	3429	#define BS_FTM_EXTTRIG_CH5TRIG (1U) //!< Bit field size in bits for FTM_EXTTRIG_CH5TRIG.
mbed_official	146:f64d43ff0c18	3430
mbed_official	146:f64d43ff0c18	3431	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3432	//! @brief Read current value of the FTM_EXTTRIG_CH5TRIG field.
mbed_official	146:f64d43ff0c18	3433	#define BR_FTM_EXTTRIG_CH5TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH5TRIG))
mbed_official	146:f64d43ff0c18	3434	#endif
mbed_official	146:f64d43ff0c18	3435
mbed_official	146:f64d43ff0c18	3436	//! @brief Format value for bitfield FTM_EXTTRIG_CH5TRIG.
mbed_official	146:f64d43ff0c18	3437	#define BF_FTM_EXTTRIG_CH5TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_EXTTRIG_CH5TRIG), uint32_t) & BM_FTM_EXTTRIG_CH5TRIG)
mbed_official	146:f64d43ff0c18	3438
mbed_official	146:f64d43ff0c18	3439	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3440	//! @brief Set the CH5TRIG field to a new value.
mbed_official	146:f64d43ff0c18	3441	#define BW_FTM_EXTTRIG_CH5TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH5TRIG) = (v))
mbed_official	146:f64d43ff0c18	3442	#endif
mbed_official	146:f64d43ff0c18	3443	//@}
mbed_official	146:f64d43ff0c18	3444
mbed_official	146:f64d43ff0c18	3445	/*!
mbed_official	146:f64d43ff0c18	3446	* @name Register FTM_EXTTRIG, field CH0TRIG[4] (RW)
mbed_official	146:f64d43ff0c18	3447	*
mbed_official	146:f64d43ff0c18	3448	* Enables the generation of the channel trigger when the FTM counter is equal
mbed_official	146:f64d43ff0c18	3449	* to the CnV register.
mbed_official	146:f64d43ff0c18	3450	*
mbed_official	146:f64d43ff0c18	3451	* Values:
mbed_official	146:f64d43ff0c18	3452	* - 0 - The generation of the channel trigger is disabled.
mbed_official	146:f64d43ff0c18	3453	* - 1 - The generation of the channel trigger is enabled.
mbed_official	146:f64d43ff0c18	3454	*/
mbed_official	146:f64d43ff0c18	3455	//@{
mbed_official	146:f64d43ff0c18	3456	#define BP_FTM_EXTTRIG_CH0TRIG (4U) //!< Bit position for FTM_EXTTRIG_CH0TRIG.
mbed_official	146:f64d43ff0c18	3457	#define BM_FTM_EXTTRIG_CH0TRIG (0x00000010U) //!< Bit mask for FTM_EXTTRIG_CH0TRIG.
mbed_official	146:f64d43ff0c18	3458	#define BS_FTM_EXTTRIG_CH0TRIG (1U) //!< Bit field size in bits for FTM_EXTTRIG_CH0TRIG.
mbed_official	146:f64d43ff0c18	3459
mbed_official	146:f64d43ff0c18	3460	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3461	//! @brief Read current value of the FTM_EXTTRIG_CH0TRIG field.
mbed_official	146:f64d43ff0c18	3462	#define BR_FTM_EXTTRIG_CH0TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH0TRIG))
mbed_official	146:f64d43ff0c18	3463	#endif
mbed_official	146:f64d43ff0c18	3464
mbed_official	146:f64d43ff0c18	3465	//! @brief Format value for bitfield FTM_EXTTRIG_CH0TRIG.
mbed_official	146:f64d43ff0c18	3466	#define BF_FTM_EXTTRIG_CH0TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_EXTTRIG_CH0TRIG), uint32_t) & BM_FTM_EXTTRIG_CH0TRIG)
mbed_official	146:f64d43ff0c18	3467
mbed_official	146:f64d43ff0c18	3468	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3469	//! @brief Set the CH0TRIG field to a new value.
mbed_official	146:f64d43ff0c18	3470	#define BW_FTM_EXTTRIG_CH0TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH0TRIG) = (v))
mbed_official	146:f64d43ff0c18	3471	#endif
mbed_official	146:f64d43ff0c18	3472	//@}
mbed_official	146:f64d43ff0c18	3473
mbed_official	146:f64d43ff0c18	3474	/*!
mbed_official	146:f64d43ff0c18	3475	* @name Register FTM_EXTTRIG, field CH1TRIG[5] (RW)
mbed_official	146:f64d43ff0c18	3476	*
mbed_official	146:f64d43ff0c18	3477	* Enables the generation of the channel trigger when the FTM counter is equal
mbed_official	146:f64d43ff0c18	3478	* to the CnV register.
mbed_official	146:f64d43ff0c18	3479	*
mbed_official	146:f64d43ff0c18	3480	* Values:
mbed_official	146:f64d43ff0c18	3481	* - 0 - The generation of the channel trigger is disabled.
mbed_official	146:f64d43ff0c18	3482	* - 1 - The generation of the channel trigger is enabled.
mbed_official	146:f64d43ff0c18	3483	*/
mbed_official	146:f64d43ff0c18	3484	//@{
mbed_official	146:f64d43ff0c18	3485	#define BP_FTM_EXTTRIG_CH1TRIG (5U) //!< Bit position for FTM_EXTTRIG_CH1TRIG.
mbed_official	146:f64d43ff0c18	3486	#define BM_FTM_EXTTRIG_CH1TRIG (0x00000020U) //!< Bit mask for FTM_EXTTRIG_CH1TRIG.
mbed_official	146:f64d43ff0c18	3487	#define BS_FTM_EXTTRIG_CH1TRIG (1U) //!< Bit field size in bits for FTM_EXTTRIG_CH1TRIG.
mbed_official	146:f64d43ff0c18	3488
mbed_official	146:f64d43ff0c18	3489	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3490	//! @brief Read current value of the FTM_EXTTRIG_CH1TRIG field.
mbed_official	146:f64d43ff0c18	3491	#define BR_FTM_EXTTRIG_CH1TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH1TRIG))
mbed_official	146:f64d43ff0c18	3492	#endif
mbed_official	146:f64d43ff0c18	3493
mbed_official	146:f64d43ff0c18	3494	//! @brief Format value for bitfield FTM_EXTTRIG_CH1TRIG.
mbed_official	146:f64d43ff0c18	3495	#define BF_FTM_EXTTRIG_CH1TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_EXTTRIG_CH1TRIG), uint32_t) & BM_FTM_EXTTRIG_CH1TRIG)
mbed_official	146:f64d43ff0c18	3496
mbed_official	146:f64d43ff0c18	3497	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3498	//! @brief Set the CH1TRIG field to a new value.
mbed_official	146:f64d43ff0c18	3499	#define BW_FTM_EXTTRIG_CH1TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH1TRIG) = (v))
mbed_official	146:f64d43ff0c18	3500	#endif
mbed_official	146:f64d43ff0c18	3501	//@}
mbed_official	146:f64d43ff0c18	3502
mbed_official	146:f64d43ff0c18	3503	/*!
mbed_official	146:f64d43ff0c18	3504	* @name Register FTM_EXTTRIG, field INITTRIGEN[6] (RW)
mbed_official	146:f64d43ff0c18	3505	*
mbed_official	146:f64d43ff0c18	3506	* Enables the generation of the trigger when the FTM counter is equal to the
mbed_official	146:f64d43ff0c18	3507	* CNTIN register.
mbed_official	146:f64d43ff0c18	3508	*
mbed_official	146:f64d43ff0c18	3509	* Values:
mbed_official	146:f64d43ff0c18	3510	* - 0 - The generation of initialization trigger is disabled.
mbed_official	146:f64d43ff0c18	3511	* - 1 - The generation of initialization trigger is enabled.
mbed_official	146:f64d43ff0c18	3512	*/
mbed_official	146:f64d43ff0c18	3513	//@{
mbed_official	146:f64d43ff0c18	3514	#define BP_FTM_EXTTRIG_INITTRIGEN (6U) //!< Bit position for FTM_EXTTRIG_INITTRIGEN.
mbed_official	146:f64d43ff0c18	3515	#define BM_FTM_EXTTRIG_INITTRIGEN (0x00000040U) //!< Bit mask for FTM_EXTTRIG_INITTRIGEN.
mbed_official	146:f64d43ff0c18	3516	#define BS_FTM_EXTTRIG_INITTRIGEN (1U) //!< Bit field size in bits for FTM_EXTTRIG_INITTRIGEN.
mbed_official	146:f64d43ff0c18	3517
mbed_official	146:f64d43ff0c18	3518	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3519	//! @brief Read current value of the FTM_EXTTRIG_INITTRIGEN field.
mbed_official	146:f64d43ff0c18	3520	#define BR_FTM_EXTTRIG_INITTRIGEN(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_INITTRIGEN))
mbed_official	146:f64d43ff0c18	3521	#endif
mbed_official	146:f64d43ff0c18	3522
mbed_official	146:f64d43ff0c18	3523	//! @brief Format value for bitfield FTM_EXTTRIG_INITTRIGEN.
mbed_official	146:f64d43ff0c18	3524	#define BF_FTM_EXTTRIG_INITTRIGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_EXTTRIG_INITTRIGEN), uint32_t) & BM_FTM_EXTTRIG_INITTRIGEN)
mbed_official	146:f64d43ff0c18	3525
mbed_official	146:f64d43ff0c18	3526	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3527	//! @brief Set the INITTRIGEN field to a new value.
mbed_official	146:f64d43ff0c18	3528	#define BW_FTM_EXTTRIG_INITTRIGEN(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_INITTRIGEN) = (v))
mbed_official	146:f64d43ff0c18	3529	#endif
mbed_official	146:f64d43ff0c18	3530	//@}
mbed_official	146:f64d43ff0c18	3531
mbed_official	146:f64d43ff0c18	3532	/*!
mbed_official	146:f64d43ff0c18	3533	* @name Register FTM_EXTTRIG, field TRIGF[7] (ROWZ)
mbed_official	146:f64d43ff0c18	3534	*
mbed_official	146:f64d43ff0c18	3535	* Set by hardware when a channel trigger is generated. Clear TRIGF by reading
mbed_official	146:f64d43ff0c18	3536	* EXTTRIG while TRIGF is set and then writing a 0 to TRIGF. Writing a 1 to TRIGF
mbed_official	146:f64d43ff0c18	3537	* has no effect. If another channel trigger is generated before the clearing
mbed_official	146:f64d43ff0c18	3538	* sequence is completed, the sequence is reset so TRIGF remains set after the clear
mbed_official	146:f64d43ff0c18	3539	* sequence is completed for the earlier TRIGF.
mbed_official	146:f64d43ff0c18	3540	*
mbed_official	146:f64d43ff0c18	3541	* Values:
mbed_official	146:f64d43ff0c18	3542	* - 0 - No channel trigger was generated.
mbed_official	146:f64d43ff0c18	3543	* - 1 - A channel trigger was generated.
mbed_official	146:f64d43ff0c18	3544	*/
mbed_official	146:f64d43ff0c18	3545	//@{
mbed_official	146:f64d43ff0c18	3546	#define BP_FTM_EXTTRIG_TRIGF (7U) //!< Bit position for FTM_EXTTRIG_TRIGF.
mbed_official	146:f64d43ff0c18	3547	#define BM_FTM_EXTTRIG_TRIGF (0x00000080U) //!< Bit mask for FTM_EXTTRIG_TRIGF.
mbed_official	146:f64d43ff0c18	3548	#define BS_FTM_EXTTRIG_TRIGF (1U) //!< Bit field size in bits for FTM_EXTTRIG_TRIGF.
mbed_official	146:f64d43ff0c18	3549
mbed_official	146:f64d43ff0c18	3550	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3551	//! @brief Read current value of the FTM_EXTTRIG_TRIGF field.
mbed_official	146:f64d43ff0c18	3552	#define BR_FTM_EXTTRIG_TRIGF(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_TRIGF))
mbed_official	146:f64d43ff0c18	3553	#endif
mbed_official	146:f64d43ff0c18	3554	//@}
mbed_official	146:f64d43ff0c18	3555
mbed_official	146:f64d43ff0c18	3556	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	3557	// HW_FTM_POL - Channels Polarity
mbed_official	146:f64d43ff0c18	3558	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	3559
mbed_official	146:f64d43ff0c18	3560	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3561	/*!
mbed_official	146:f64d43ff0c18	3562	* @brief HW_FTM_POL - Channels Polarity (RW)
mbed_official	146:f64d43ff0c18	3563	*
mbed_official	146:f64d43ff0c18	3564	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	3565	*
mbed_official	146:f64d43ff0c18	3566	* This register defines the output polarity of the FTM channels. The safe value
mbed_official	146:f64d43ff0c18	3567	* that is driven in a channel output when the fault control is enabled and a
mbed_official	146:f64d43ff0c18	3568	* fault condition is detected is the inactive state of the channel. That is, the
mbed_official	146:f64d43ff0c18	3569	* safe value of a channel is the value of its POL bit.
mbed_official	146:f64d43ff0c18	3570	*/
mbed_official	146:f64d43ff0c18	3571	typedef union _hw_ftm_pol
mbed_official	146:f64d43ff0c18	3572	{
mbed_official	146:f64d43ff0c18	3573	uint32_t U;
mbed_official	146:f64d43ff0c18	3574	struct _hw_ftm_pol_bitfields
mbed_official	146:f64d43ff0c18	3575	{
mbed_official	146:f64d43ff0c18	3576	uint32_t POL0 : 1; //!< [0] Channel 0 Polarity
mbed_official	146:f64d43ff0c18	3577	uint32_t POL1 : 1; //!< [1] Channel 1 Polarity
mbed_official	146:f64d43ff0c18	3578	uint32_t POL2 : 1; //!< [2] Channel 2 Polarity
mbed_official	146:f64d43ff0c18	3579	uint32_t POL3 : 1; //!< [3] Channel 3 Polarity
mbed_official	146:f64d43ff0c18	3580	uint32_t POL4 : 1; //!< [4] Channel 4 Polarity
mbed_official	146:f64d43ff0c18	3581	uint32_t POL5 : 1; //!< [5] Channel 5 Polarity
mbed_official	146:f64d43ff0c18	3582	uint32_t POL6 : 1; //!< [6] Channel 6 Polarity
mbed_official	146:f64d43ff0c18	3583	uint32_t POL7 : 1; //!< [7] Channel 7 Polarity
mbed_official	146:f64d43ff0c18	3584	uint32_t RESERVED0 : 24; //!< [31:8]
mbed_official	146:f64d43ff0c18	3585	} B;
mbed_official	146:f64d43ff0c18	3586	} hw_ftm_pol_t;
mbed_official	146:f64d43ff0c18	3587	#endif
mbed_official	146:f64d43ff0c18	3588
mbed_official	146:f64d43ff0c18	3589	/*!
mbed_official	146:f64d43ff0c18	3590	* @name Constants and macros for entire FTM_POL register
mbed_official	146:f64d43ff0c18	3591	*/
mbed_official	146:f64d43ff0c18	3592	//@{
mbed_official	146:f64d43ff0c18	3593	#define HW_FTM_POL_ADDR(x) (REGS_FTM_BASE(x) + 0x70U)
mbed_official	146:f64d43ff0c18	3594
mbed_official	146:f64d43ff0c18	3595	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3596	#define HW_FTM_POL(x) ((__IO hw_ftm_pol_t ) HW_FTM_POL_ADDR(x))
mbed_official	146:f64d43ff0c18	3597	#define HW_FTM_POL_RD(x) (HW_FTM_POL(x).U)
mbed_official	146:f64d43ff0c18	3598	#define HW_FTM_POL_WR(x, v) (HW_FTM_POL(x).U = (v))
mbed_official	146:f64d43ff0c18	3599	#define HW_FTM_POL_SET(x, v) (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	3600	#define HW_FTM_POL_CLR(x, v) (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	3601	#define HW_FTM_POL_TOG(x, v) (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	3602	#endif
mbed_official	146:f64d43ff0c18	3603	//@}
mbed_official	146:f64d43ff0c18	3604
mbed_official	146:f64d43ff0c18	3605	/*
mbed_official	146:f64d43ff0c18	3606	* Constants & macros for individual FTM_POL bitfields
mbed_official	146:f64d43ff0c18	3607	*/
mbed_official	146:f64d43ff0c18	3608
mbed_official	146:f64d43ff0c18	3609	/*!
mbed_official	146:f64d43ff0c18	3610	* @name Register FTM_POL, field POL0[0] (RW)
mbed_official	146:f64d43ff0c18	3611	*
mbed_official	146:f64d43ff0c18	3612	* Defines the polarity of the channel output. This field is write protected. It
mbed_official	146:f64d43ff0c18	3613	* can be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	3614	*
mbed_official	146:f64d43ff0c18	3615	* Values:
mbed_official	146:f64d43ff0c18	3616	* - 0 - The channel polarity is active high.
mbed_official	146:f64d43ff0c18	3617	* - 1 - The channel polarity is active low.
mbed_official	146:f64d43ff0c18	3618	*/
mbed_official	146:f64d43ff0c18	3619	//@{
mbed_official	146:f64d43ff0c18	3620	#define BP_FTM_POL_POL0 (0U) //!< Bit position for FTM_POL_POL0.
mbed_official	146:f64d43ff0c18	3621	#define BM_FTM_POL_POL0 (0x00000001U) //!< Bit mask for FTM_POL_POL0.
mbed_official	146:f64d43ff0c18	3622	#define BS_FTM_POL_POL0 (1U) //!< Bit field size in bits for FTM_POL_POL0.
mbed_official	146:f64d43ff0c18	3623
mbed_official	146:f64d43ff0c18	3624	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3625	//! @brief Read current value of the FTM_POL_POL0 field.
mbed_official	146:f64d43ff0c18	3626	#define BR_FTM_POL_POL0(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL0))
mbed_official	146:f64d43ff0c18	3627	#endif
mbed_official	146:f64d43ff0c18	3628
mbed_official	146:f64d43ff0c18	3629	//! @brief Format value for bitfield FTM_POL_POL0.
mbed_official	146:f64d43ff0c18	3630	#define BF_FTM_POL_POL0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL0), uint32_t) & BM_FTM_POL_POL0)
mbed_official	146:f64d43ff0c18	3631
mbed_official	146:f64d43ff0c18	3632	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3633	//! @brief Set the POL0 field to a new value.
mbed_official	146:f64d43ff0c18	3634	#define BW_FTM_POL_POL0(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL0) = (v))
mbed_official	146:f64d43ff0c18	3635	#endif
mbed_official	146:f64d43ff0c18	3636	//@}
mbed_official	146:f64d43ff0c18	3637
mbed_official	146:f64d43ff0c18	3638	/*!
mbed_official	146:f64d43ff0c18	3639	* @name Register FTM_POL, field POL1[1] (RW)
mbed_official	146:f64d43ff0c18	3640	*
mbed_official	146:f64d43ff0c18	3641	* Defines the polarity of the channel output. This field is write protected. It
mbed_official	146:f64d43ff0c18	3642	* can be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	3643	*
mbed_official	146:f64d43ff0c18	3644	* Values:
mbed_official	146:f64d43ff0c18	3645	* - 0 - The channel polarity is active high.
mbed_official	146:f64d43ff0c18	3646	* - 1 - The channel polarity is active low.
mbed_official	146:f64d43ff0c18	3647	*/
mbed_official	146:f64d43ff0c18	3648	//@{
mbed_official	146:f64d43ff0c18	3649	#define BP_FTM_POL_POL1 (1U) //!< Bit position for FTM_POL_POL1.
mbed_official	146:f64d43ff0c18	3650	#define BM_FTM_POL_POL1 (0x00000002U) //!< Bit mask for FTM_POL_POL1.
mbed_official	146:f64d43ff0c18	3651	#define BS_FTM_POL_POL1 (1U) //!< Bit field size in bits for FTM_POL_POL1.
mbed_official	146:f64d43ff0c18	3652
mbed_official	146:f64d43ff0c18	3653	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3654	//! @brief Read current value of the FTM_POL_POL1 field.
mbed_official	146:f64d43ff0c18	3655	#define BR_FTM_POL_POL1(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL1))
mbed_official	146:f64d43ff0c18	3656	#endif
mbed_official	146:f64d43ff0c18	3657
mbed_official	146:f64d43ff0c18	3658	//! @brief Format value for bitfield FTM_POL_POL1.
mbed_official	146:f64d43ff0c18	3659	#define BF_FTM_POL_POL1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL1), uint32_t) & BM_FTM_POL_POL1)
mbed_official	146:f64d43ff0c18	3660
mbed_official	146:f64d43ff0c18	3661	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3662	//! @brief Set the POL1 field to a new value.
mbed_official	146:f64d43ff0c18	3663	#define BW_FTM_POL_POL1(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL1) = (v))
mbed_official	146:f64d43ff0c18	3664	#endif
mbed_official	146:f64d43ff0c18	3665	//@}
mbed_official	146:f64d43ff0c18	3666
mbed_official	146:f64d43ff0c18	3667	/*!
mbed_official	146:f64d43ff0c18	3668	* @name Register FTM_POL, field POL2[2] (RW)
mbed_official	146:f64d43ff0c18	3669	*
mbed_official	146:f64d43ff0c18	3670	* Defines the polarity of the channel output. This field is write protected. It
mbed_official	146:f64d43ff0c18	3671	* can be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	3672	*
mbed_official	146:f64d43ff0c18	3673	* Values:
mbed_official	146:f64d43ff0c18	3674	* - 0 - The channel polarity is active high.
mbed_official	146:f64d43ff0c18	3675	* - 1 - The channel polarity is active low.
mbed_official	146:f64d43ff0c18	3676	*/
mbed_official	146:f64d43ff0c18	3677	//@{
mbed_official	146:f64d43ff0c18	3678	#define BP_FTM_POL_POL2 (2U) //!< Bit position for FTM_POL_POL2.
mbed_official	146:f64d43ff0c18	3679	#define BM_FTM_POL_POL2 (0x00000004U) //!< Bit mask for FTM_POL_POL2.
mbed_official	146:f64d43ff0c18	3680	#define BS_FTM_POL_POL2 (1U) //!< Bit field size in bits for FTM_POL_POL2.
mbed_official	146:f64d43ff0c18	3681
mbed_official	146:f64d43ff0c18	3682	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3683	//! @brief Read current value of the FTM_POL_POL2 field.
mbed_official	146:f64d43ff0c18	3684	#define BR_FTM_POL_POL2(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL2))
mbed_official	146:f64d43ff0c18	3685	#endif
mbed_official	146:f64d43ff0c18	3686
mbed_official	146:f64d43ff0c18	3687	//! @brief Format value for bitfield FTM_POL_POL2.
mbed_official	146:f64d43ff0c18	3688	#define BF_FTM_POL_POL2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL2), uint32_t) & BM_FTM_POL_POL2)
mbed_official	146:f64d43ff0c18	3689
mbed_official	146:f64d43ff0c18	3690	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3691	//! @brief Set the POL2 field to a new value.
mbed_official	146:f64d43ff0c18	3692	#define BW_FTM_POL_POL2(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL2) = (v))
mbed_official	146:f64d43ff0c18	3693	#endif
mbed_official	146:f64d43ff0c18	3694	//@}
mbed_official	146:f64d43ff0c18	3695
mbed_official	146:f64d43ff0c18	3696	/*!
mbed_official	146:f64d43ff0c18	3697	* @name Register FTM_POL, field POL3[3] (RW)
mbed_official	146:f64d43ff0c18	3698	*
mbed_official	146:f64d43ff0c18	3699	* Defines the polarity of the channel output. This field is write protected. It
mbed_official	146:f64d43ff0c18	3700	* can be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	3701	*
mbed_official	146:f64d43ff0c18	3702	* Values:
mbed_official	146:f64d43ff0c18	3703	* - 0 - The channel polarity is active high.
mbed_official	146:f64d43ff0c18	3704	* - 1 - The channel polarity is active low.
mbed_official	146:f64d43ff0c18	3705	*/
mbed_official	146:f64d43ff0c18	3706	//@{
mbed_official	146:f64d43ff0c18	3707	#define BP_FTM_POL_POL3 (3U) //!< Bit position for FTM_POL_POL3.
mbed_official	146:f64d43ff0c18	3708	#define BM_FTM_POL_POL3 (0x00000008U) //!< Bit mask for FTM_POL_POL3.
mbed_official	146:f64d43ff0c18	3709	#define BS_FTM_POL_POL3 (1U) //!< Bit field size in bits for FTM_POL_POL3.
mbed_official	146:f64d43ff0c18	3710
mbed_official	146:f64d43ff0c18	3711	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3712	//! @brief Read current value of the FTM_POL_POL3 field.
mbed_official	146:f64d43ff0c18	3713	#define BR_FTM_POL_POL3(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL3))
mbed_official	146:f64d43ff0c18	3714	#endif
mbed_official	146:f64d43ff0c18	3715
mbed_official	146:f64d43ff0c18	3716	//! @brief Format value for bitfield FTM_POL_POL3.
mbed_official	146:f64d43ff0c18	3717	#define BF_FTM_POL_POL3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL3), uint32_t) & BM_FTM_POL_POL3)
mbed_official	146:f64d43ff0c18	3718
mbed_official	146:f64d43ff0c18	3719	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3720	//! @brief Set the POL3 field to a new value.
mbed_official	146:f64d43ff0c18	3721	#define BW_FTM_POL_POL3(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL3) = (v))
mbed_official	146:f64d43ff0c18	3722	#endif
mbed_official	146:f64d43ff0c18	3723	//@}
mbed_official	146:f64d43ff0c18	3724
mbed_official	146:f64d43ff0c18	3725	/*!
mbed_official	146:f64d43ff0c18	3726	* @name Register FTM_POL, field POL4[4] (RW)
mbed_official	146:f64d43ff0c18	3727	*
mbed_official	146:f64d43ff0c18	3728	* Defines the polarity of the channel output. This field is write protected. It
mbed_official	146:f64d43ff0c18	3729	* can be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	3730	*
mbed_official	146:f64d43ff0c18	3731	* Values:
mbed_official	146:f64d43ff0c18	3732	* - 0 - The channel polarity is active high.
mbed_official	146:f64d43ff0c18	3733	* - 1 - The channel polarity is active low.
mbed_official	146:f64d43ff0c18	3734	*/
mbed_official	146:f64d43ff0c18	3735	//@{
mbed_official	146:f64d43ff0c18	3736	#define BP_FTM_POL_POL4 (4U) //!< Bit position for FTM_POL_POL4.
mbed_official	146:f64d43ff0c18	3737	#define BM_FTM_POL_POL4 (0x00000010U) //!< Bit mask for FTM_POL_POL4.
mbed_official	146:f64d43ff0c18	3738	#define BS_FTM_POL_POL4 (1U) //!< Bit field size in bits for FTM_POL_POL4.
mbed_official	146:f64d43ff0c18	3739
mbed_official	146:f64d43ff0c18	3740	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3741	//! @brief Read current value of the FTM_POL_POL4 field.
mbed_official	146:f64d43ff0c18	3742	#define BR_FTM_POL_POL4(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL4))
mbed_official	146:f64d43ff0c18	3743	#endif
mbed_official	146:f64d43ff0c18	3744
mbed_official	146:f64d43ff0c18	3745	//! @brief Format value for bitfield FTM_POL_POL4.
mbed_official	146:f64d43ff0c18	3746	#define BF_FTM_POL_POL4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL4), uint32_t) & BM_FTM_POL_POL4)
mbed_official	146:f64d43ff0c18	3747
mbed_official	146:f64d43ff0c18	3748	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3749	//! @brief Set the POL4 field to a new value.
mbed_official	146:f64d43ff0c18	3750	#define BW_FTM_POL_POL4(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL4) = (v))
mbed_official	146:f64d43ff0c18	3751	#endif
mbed_official	146:f64d43ff0c18	3752	//@}
mbed_official	146:f64d43ff0c18	3753
mbed_official	146:f64d43ff0c18	3754	/*!
mbed_official	146:f64d43ff0c18	3755	* @name Register FTM_POL, field POL5[5] (RW)
mbed_official	146:f64d43ff0c18	3756	*
mbed_official	146:f64d43ff0c18	3757	* Defines the polarity of the channel output. This field is write protected. It
mbed_official	146:f64d43ff0c18	3758	* can be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	3759	*
mbed_official	146:f64d43ff0c18	3760	* Values:
mbed_official	146:f64d43ff0c18	3761	* - 0 - The channel polarity is active high.
mbed_official	146:f64d43ff0c18	3762	* - 1 - The channel polarity is active low.
mbed_official	146:f64d43ff0c18	3763	*/
mbed_official	146:f64d43ff0c18	3764	//@{
mbed_official	146:f64d43ff0c18	3765	#define BP_FTM_POL_POL5 (5U) //!< Bit position for FTM_POL_POL5.
mbed_official	146:f64d43ff0c18	3766	#define BM_FTM_POL_POL5 (0x00000020U) //!< Bit mask for FTM_POL_POL5.
mbed_official	146:f64d43ff0c18	3767	#define BS_FTM_POL_POL5 (1U) //!< Bit field size in bits for FTM_POL_POL5.
mbed_official	146:f64d43ff0c18	3768
mbed_official	146:f64d43ff0c18	3769	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3770	//! @brief Read current value of the FTM_POL_POL5 field.
mbed_official	146:f64d43ff0c18	3771	#define BR_FTM_POL_POL5(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL5))
mbed_official	146:f64d43ff0c18	3772	#endif
mbed_official	146:f64d43ff0c18	3773
mbed_official	146:f64d43ff0c18	3774	//! @brief Format value for bitfield FTM_POL_POL5.
mbed_official	146:f64d43ff0c18	3775	#define BF_FTM_POL_POL5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL5), uint32_t) & BM_FTM_POL_POL5)
mbed_official	146:f64d43ff0c18	3776
mbed_official	146:f64d43ff0c18	3777	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3778	//! @brief Set the POL5 field to a new value.
mbed_official	146:f64d43ff0c18	3779	#define BW_FTM_POL_POL5(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL5) = (v))
mbed_official	146:f64d43ff0c18	3780	#endif
mbed_official	146:f64d43ff0c18	3781	//@}
mbed_official	146:f64d43ff0c18	3782
mbed_official	146:f64d43ff0c18	3783	/*!
mbed_official	146:f64d43ff0c18	3784	* @name Register FTM_POL, field POL6[6] (RW)
mbed_official	146:f64d43ff0c18	3785	*
mbed_official	146:f64d43ff0c18	3786	* Defines the polarity of the channel output. This field is write protected. It
mbed_official	146:f64d43ff0c18	3787	* can be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	3788	*
mbed_official	146:f64d43ff0c18	3789	* Values:
mbed_official	146:f64d43ff0c18	3790	* - 0 - The channel polarity is active high.
mbed_official	146:f64d43ff0c18	3791	* - 1 - The channel polarity is active low.
mbed_official	146:f64d43ff0c18	3792	*/
mbed_official	146:f64d43ff0c18	3793	//@{
mbed_official	146:f64d43ff0c18	3794	#define BP_FTM_POL_POL6 (6U) //!< Bit position for FTM_POL_POL6.
mbed_official	146:f64d43ff0c18	3795	#define BM_FTM_POL_POL6 (0x00000040U) //!< Bit mask for FTM_POL_POL6.
mbed_official	146:f64d43ff0c18	3796	#define BS_FTM_POL_POL6 (1U) //!< Bit field size in bits for FTM_POL_POL6.
mbed_official	146:f64d43ff0c18	3797
mbed_official	146:f64d43ff0c18	3798	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3799	//! @brief Read current value of the FTM_POL_POL6 field.
mbed_official	146:f64d43ff0c18	3800	#define BR_FTM_POL_POL6(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL6))
mbed_official	146:f64d43ff0c18	3801	#endif
mbed_official	146:f64d43ff0c18	3802
mbed_official	146:f64d43ff0c18	3803	//! @brief Format value for bitfield FTM_POL_POL6.
mbed_official	146:f64d43ff0c18	3804	#define BF_FTM_POL_POL6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL6), uint32_t) & BM_FTM_POL_POL6)
mbed_official	146:f64d43ff0c18	3805
mbed_official	146:f64d43ff0c18	3806	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3807	//! @brief Set the POL6 field to a new value.
mbed_official	146:f64d43ff0c18	3808	#define BW_FTM_POL_POL6(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL6) = (v))
mbed_official	146:f64d43ff0c18	3809	#endif
mbed_official	146:f64d43ff0c18	3810	//@}
mbed_official	146:f64d43ff0c18	3811
mbed_official	146:f64d43ff0c18	3812	/*!
mbed_official	146:f64d43ff0c18	3813	* @name Register FTM_POL, field POL7[7] (RW)
mbed_official	146:f64d43ff0c18	3814	*
mbed_official	146:f64d43ff0c18	3815	* Defines the polarity of the channel output. This field is write protected. It
mbed_official	146:f64d43ff0c18	3816	* can be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	3817	*
mbed_official	146:f64d43ff0c18	3818	* Values:
mbed_official	146:f64d43ff0c18	3819	* - 0 - The channel polarity is active high.
mbed_official	146:f64d43ff0c18	3820	* - 1 - The channel polarity is active low.
mbed_official	146:f64d43ff0c18	3821	*/
mbed_official	146:f64d43ff0c18	3822	//@{
mbed_official	146:f64d43ff0c18	3823	#define BP_FTM_POL_POL7 (7U) //!< Bit position for FTM_POL_POL7.
mbed_official	146:f64d43ff0c18	3824	#define BM_FTM_POL_POL7 (0x00000080U) //!< Bit mask for FTM_POL_POL7.
mbed_official	146:f64d43ff0c18	3825	#define BS_FTM_POL_POL7 (1U) //!< Bit field size in bits for FTM_POL_POL7.
mbed_official	146:f64d43ff0c18	3826
mbed_official	146:f64d43ff0c18	3827	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3828	//! @brief Read current value of the FTM_POL_POL7 field.
mbed_official	146:f64d43ff0c18	3829	#define BR_FTM_POL_POL7(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL7))
mbed_official	146:f64d43ff0c18	3830	#endif
mbed_official	146:f64d43ff0c18	3831
mbed_official	146:f64d43ff0c18	3832	//! @brief Format value for bitfield FTM_POL_POL7.
mbed_official	146:f64d43ff0c18	3833	#define BF_FTM_POL_POL7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL7), uint32_t) & BM_FTM_POL_POL7)
mbed_official	146:f64d43ff0c18	3834
mbed_official	146:f64d43ff0c18	3835	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3836	//! @brief Set the POL7 field to a new value.
mbed_official	146:f64d43ff0c18	3837	#define BW_FTM_POL_POL7(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL7) = (v))
mbed_official	146:f64d43ff0c18	3838	#endif
mbed_official	146:f64d43ff0c18	3839	//@}
mbed_official	146:f64d43ff0c18	3840
mbed_official	146:f64d43ff0c18	3841	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	3842	// HW_FTM_FMS - Fault Mode Status
mbed_official	146:f64d43ff0c18	3843	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	3844
mbed_official	146:f64d43ff0c18	3845	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3846	/*!
mbed_official	146:f64d43ff0c18	3847	* @brief HW_FTM_FMS - Fault Mode Status (RW)
mbed_official	146:f64d43ff0c18	3848	*
mbed_official	146:f64d43ff0c18	3849	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	3850	*
mbed_official	146:f64d43ff0c18	3851	* This register contains the fault detection flags, write protection enable
mbed_official	146:f64d43ff0c18	3852	* bit, and the logic OR of the enabled fault inputs.
mbed_official	146:f64d43ff0c18	3853	*/
mbed_official	146:f64d43ff0c18	3854	typedef union _hw_ftm_fms
mbed_official	146:f64d43ff0c18	3855	{
mbed_official	146:f64d43ff0c18	3856	uint32_t U;
mbed_official	146:f64d43ff0c18	3857	struct _hw_ftm_fms_bitfields
mbed_official	146:f64d43ff0c18	3858	{
mbed_official	146:f64d43ff0c18	3859	uint32_t FAULTF0 : 1; //!< [0] Fault Detection Flag 0
mbed_official	146:f64d43ff0c18	3860	uint32_t FAULTF1 : 1; //!< [1] Fault Detection Flag 1
mbed_official	146:f64d43ff0c18	3861	uint32_t FAULTF2 : 1; //!< [2] Fault Detection Flag 2
mbed_official	146:f64d43ff0c18	3862	uint32_t FAULTF3 : 1; //!< [3] Fault Detection Flag 3
mbed_official	146:f64d43ff0c18	3863	uint32_t RESERVED0 : 1; //!< [4]
mbed_official	146:f64d43ff0c18	3864	uint32_t FAULTIN : 1; //!< [5] Fault Inputs
mbed_official	146:f64d43ff0c18	3865	uint32_t WPEN : 1; //!< [6] Write Protection Enable
mbed_official	146:f64d43ff0c18	3866	uint32_t FAULTF : 1; //!< [7] Fault Detection Flag
mbed_official	146:f64d43ff0c18	3867	uint32_t RESERVED1 : 24; //!< [31:8]
mbed_official	146:f64d43ff0c18	3868	} B;
mbed_official	146:f64d43ff0c18	3869	} hw_ftm_fms_t;
mbed_official	146:f64d43ff0c18	3870	#endif
mbed_official	146:f64d43ff0c18	3871
mbed_official	146:f64d43ff0c18	3872	/*!
mbed_official	146:f64d43ff0c18	3873	* @name Constants and macros for entire FTM_FMS register
mbed_official	146:f64d43ff0c18	3874	*/
mbed_official	146:f64d43ff0c18	3875	//@{
mbed_official	146:f64d43ff0c18	3876	#define HW_FTM_FMS_ADDR(x) (REGS_FTM_BASE(x) + 0x74U)
mbed_official	146:f64d43ff0c18	3877
mbed_official	146:f64d43ff0c18	3878	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3879	#define HW_FTM_FMS(x) ((__IO hw_ftm_fms_t ) HW_FTM_FMS_ADDR(x))
mbed_official	146:f64d43ff0c18	3880	#define HW_FTM_FMS_RD(x) (HW_FTM_FMS(x).U)
mbed_official	146:f64d43ff0c18	3881	#define HW_FTM_FMS_WR(x, v) (HW_FTM_FMS(x).U = (v))
mbed_official	146:f64d43ff0c18	3882	#define HW_FTM_FMS_SET(x, v) (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	3883	#define HW_FTM_FMS_CLR(x, v) (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	3884	#define HW_FTM_FMS_TOG(x, v) (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	3885	#endif
mbed_official	146:f64d43ff0c18	3886	//@}
mbed_official	146:f64d43ff0c18	3887
mbed_official	146:f64d43ff0c18	3888	/*
mbed_official	146:f64d43ff0c18	3889	* Constants & macros for individual FTM_FMS bitfields
mbed_official	146:f64d43ff0c18	3890	*/
mbed_official	146:f64d43ff0c18	3891
mbed_official	146:f64d43ff0c18	3892	/*!
mbed_official	146:f64d43ff0c18	3893	* @name Register FTM_FMS, field FAULTF0[0] (ROWZ)
mbed_official	146:f64d43ff0c18	3894	*
mbed_official	146:f64d43ff0c18	3895	* Set by hardware when fault control is enabled, the corresponding fault input
mbed_official	146:f64d43ff0c18	3896	* is enabled and a fault condition is detected at the fault input. Clear FAULTF0
mbed_official	146:f64d43ff0c18	3897	* by reading the FMS register while FAULTF0 is set and then writing a 0 to
mbed_official	146:f64d43ff0c18	3898	* FAULTF0 while there is no existing fault condition at the corresponding fault
mbed_official	146:f64d43ff0c18	3899	* input. Writing a 1 to FAULTF0 has no effect. FAULTF0 bit is also cleared when
mbed_official	146:f64d43ff0c18	3900	* FAULTF bit is cleared. If another fault condition is detected at the corresponding
mbed_official	146:f64d43ff0c18	3901	* fault input before the clearing sequence is completed, the sequence is reset
mbed_official	146:f64d43ff0c18	3902	* so FAULTF0 remains set after the clearing sequence is completed for the
mbed_official	146:f64d43ff0c18	3903	* earlier fault condition.
mbed_official	146:f64d43ff0c18	3904	*
mbed_official	146:f64d43ff0c18	3905	* Values:
mbed_official	146:f64d43ff0c18	3906	* - 0 - No fault condition was detected at the fault input.
mbed_official	146:f64d43ff0c18	3907	* - 1 - A fault condition was detected at the fault input.
mbed_official	146:f64d43ff0c18	3908	*/
mbed_official	146:f64d43ff0c18	3909	//@{
mbed_official	146:f64d43ff0c18	3910	#define BP_FTM_FMS_FAULTF0 (0U) //!< Bit position for FTM_FMS_FAULTF0.
mbed_official	146:f64d43ff0c18	3911	#define BM_FTM_FMS_FAULTF0 (0x00000001U) //!< Bit mask for FTM_FMS_FAULTF0.
mbed_official	146:f64d43ff0c18	3912	#define BS_FTM_FMS_FAULTF0 (1U) //!< Bit field size in bits for FTM_FMS_FAULTF0.
mbed_official	146:f64d43ff0c18	3913
mbed_official	146:f64d43ff0c18	3914	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3915	//! @brief Read current value of the FTM_FMS_FAULTF0 field.
mbed_official	146:f64d43ff0c18	3916	#define BR_FTM_FMS_FAULTF0(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF0))
mbed_official	146:f64d43ff0c18	3917	#endif
mbed_official	146:f64d43ff0c18	3918	//@}
mbed_official	146:f64d43ff0c18	3919
mbed_official	146:f64d43ff0c18	3920	/*!
mbed_official	146:f64d43ff0c18	3921	* @name Register FTM_FMS, field FAULTF1[1] (ROWZ)
mbed_official	146:f64d43ff0c18	3922	*
mbed_official	146:f64d43ff0c18	3923	* Set by hardware when fault control is enabled, the corresponding fault input
mbed_official	146:f64d43ff0c18	3924	* is enabled and a fault condition is detected at the fault input. Clear FAULTF1
mbed_official	146:f64d43ff0c18	3925	* by reading the FMS register while FAULTF1 is set and then writing a 0 to
mbed_official	146:f64d43ff0c18	3926	* FAULTF1 while there is no existing fault condition at the corresponding fault
mbed_official	146:f64d43ff0c18	3927	* input. Writing a 1 to FAULTF1 has no effect. FAULTF1 bit is also cleared when
mbed_official	146:f64d43ff0c18	3928	* FAULTF bit is cleared. If another fault condition is detected at the corresponding
mbed_official	146:f64d43ff0c18	3929	* fault input before the clearing sequence is completed, the sequence is reset
mbed_official	146:f64d43ff0c18	3930	* so FAULTF1 remains set after the clearing sequence is completed for the
mbed_official	146:f64d43ff0c18	3931	* earlier fault condition.
mbed_official	146:f64d43ff0c18	3932	*
mbed_official	146:f64d43ff0c18	3933	* Values:
mbed_official	146:f64d43ff0c18	3934	* - 0 - No fault condition was detected at the fault input.
mbed_official	146:f64d43ff0c18	3935	* - 1 - A fault condition was detected at the fault input.
mbed_official	146:f64d43ff0c18	3936	*/
mbed_official	146:f64d43ff0c18	3937	//@{
mbed_official	146:f64d43ff0c18	3938	#define BP_FTM_FMS_FAULTF1 (1U) //!< Bit position for FTM_FMS_FAULTF1.
mbed_official	146:f64d43ff0c18	3939	#define BM_FTM_FMS_FAULTF1 (0x00000002U) //!< Bit mask for FTM_FMS_FAULTF1.
mbed_official	146:f64d43ff0c18	3940	#define BS_FTM_FMS_FAULTF1 (1U) //!< Bit field size in bits for FTM_FMS_FAULTF1.
mbed_official	146:f64d43ff0c18	3941
mbed_official	146:f64d43ff0c18	3942	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3943	//! @brief Read current value of the FTM_FMS_FAULTF1 field.
mbed_official	146:f64d43ff0c18	3944	#define BR_FTM_FMS_FAULTF1(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF1))
mbed_official	146:f64d43ff0c18	3945	#endif
mbed_official	146:f64d43ff0c18	3946	//@}
mbed_official	146:f64d43ff0c18	3947
mbed_official	146:f64d43ff0c18	3948	/*!
mbed_official	146:f64d43ff0c18	3949	* @name Register FTM_FMS, field FAULTF2[2] (ROWZ)
mbed_official	146:f64d43ff0c18	3950	*
mbed_official	146:f64d43ff0c18	3951	* Set by hardware when fault control is enabled, the corresponding fault input
mbed_official	146:f64d43ff0c18	3952	* is enabled and a fault condition is detected at the fault input. Clear FAULTF2
mbed_official	146:f64d43ff0c18	3953	* by reading the FMS register while FAULTF2 is set and then writing a 0 to
mbed_official	146:f64d43ff0c18	3954	* FAULTF2 while there is no existing fault condition at the corresponding fault
mbed_official	146:f64d43ff0c18	3955	* input. Writing a 1 to FAULTF2 has no effect. FAULTF2 bit is also cleared when
mbed_official	146:f64d43ff0c18	3956	* FAULTF bit is cleared. If another fault condition is detected at the corresponding
mbed_official	146:f64d43ff0c18	3957	* fault input before the clearing sequence is completed, the sequence is reset
mbed_official	146:f64d43ff0c18	3958	* so FAULTF2 remains set after the clearing sequence is completed for the
mbed_official	146:f64d43ff0c18	3959	* earlier fault condition.
mbed_official	146:f64d43ff0c18	3960	*
mbed_official	146:f64d43ff0c18	3961	* Values:
mbed_official	146:f64d43ff0c18	3962	* - 0 - No fault condition was detected at the fault input.
mbed_official	146:f64d43ff0c18	3963	* - 1 - A fault condition was detected at the fault input.
mbed_official	146:f64d43ff0c18	3964	*/
mbed_official	146:f64d43ff0c18	3965	//@{
mbed_official	146:f64d43ff0c18	3966	#define BP_FTM_FMS_FAULTF2 (2U) //!< Bit position for FTM_FMS_FAULTF2.
mbed_official	146:f64d43ff0c18	3967	#define BM_FTM_FMS_FAULTF2 (0x00000004U) //!< Bit mask for FTM_FMS_FAULTF2.
mbed_official	146:f64d43ff0c18	3968	#define BS_FTM_FMS_FAULTF2 (1U) //!< Bit field size in bits for FTM_FMS_FAULTF2.
mbed_official	146:f64d43ff0c18	3969
mbed_official	146:f64d43ff0c18	3970	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3971	//! @brief Read current value of the FTM_FMS_FAULTF2 field.
mbed_official	146:f64d43ff0c18	3972	#define BR_FTM_FMS_FAULTF2(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF2))
mbed_official	146:f64d43ff0c18	3973	#endif
mbed_official	146:f64d43ff0c18	3974	//@}
mbed_official	146:f64d43ff0c18	3975
mbed_official	146:f64d43ff0c18	3976	/*!
mbed_official	146:f64d43ff0c18	3977	* @name Register FTM_FMS, field FAULTF3[3] (ROWZ)
mbed_official	146:f64d43ff0c18	3978	*
mbed_official	146:f64d43ff0c18	3979	* Set by hardware when fault control is enabled, the corresponding fault input
mbed_official	146:f64d43ff0c18	3980	* is enabled and a fault condition is detected at the fault input. Clear FAULTF3
mbed_official	146:f64d43ff0c18	3981	* by reading the FMS register while FAULTF3 is set and then writing a 0 to
mbed_official	146:f64d43ff0c18	3982	* FAULTF3 while there is no existing fault condition at the corresponding fault
mbed_official	146:f64d43ff0c18	3983	* input. Writing a 1 to FAULTF3 has no effect. FAULTF3 bit is also cleared when
mbed_official	146:f64d43ff0c18	3984	* FAULTF bit is cleared. If another fault condition is detected at the corresponding
mbed_official	146:f64d43ff0c18	3985	* fault input before the clearing sequence is completed, the sequence is reset
mbed_official	146:f64d43ff0c18	3986	* so FAULTF3 remains set after the clearing sequence is completed for the
mbed_official	146:f64d43ff0c18	3987	* earlier fault condition.
mbed_official	146:f64d43ff0c18	3988	*
mbed_official	146:f64d43ff0c18	3989	* Values:
mbed_official	146:f64d43ff0c18	3990	* - 0 - No fault condition was detected at the fault input.
mbed_official	146:f64d43ff0c18	3991	* - 1 - A fault condition was detected at the fault input.
mbed_official	146:f64d43ff0c18	3992	*/
mbed_official	146:f64d43ff0c18	3993	//@{
mbed_official	146:f64d43ff0c18	3994	#define BP_FTM_FMS_FAULTF3 (3U) //!< Bit position for FTM_FMS_FAULTF3.
mbed_official	146:f64d43ff0c18	3995	#define BM_FTM_FMS_FAULTF3 (0x00000008U) //!< Bit mask for FTM_FMS_FAULTF3.
mbed_official	146:f64d43ff0c18	3996	#define BS_FTM_FMS_FAULTF3 (1U) //!< Bit field size in bits for FTM_FMS_FAULTF3.
mbed_official	146:f64d43ff0c18	3997
mbed_official	146:f64d43ff0c18	3998	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3999	//! @brief Read current value of the FTM_FMS_FAULTF3 field.
mbed_official	146:f64d43ff0c18	4000	#define BR_FTM_FMS_FAULTF3(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF3))
mbed_official	146:f64d43ff0c18	4001	#endif
mbed_official	146:f64d43ff0c18	4002	//@}
mbed_official	146:f64d43ff0c18	4003
mbed_official	146:f64d43ff0c18	4004	/*!
mbed_official	146:f64d43ff0c18	4005	* @name Register FTM_FMS, field FAULTIN[5] (RO)
mbed_official	146:f64d43ff0c18	4006	*
mbed_official	146:f64d43ff0c18	4007	* Represents the logic OR of the enabled fault inputs after their filter (if
mbed_official	146:f64d43ff0c18	4008	* their filter is enabled) when fault control is enabled.
mbed_official	146:f64d43ff0c18	4009	*
mbed_official	146:f64d43ff0c18	4010	* Values:
mbed_official	146:f64d43ff0c18	4011	* - 0 - The logic OR of the enabled fault inputs is 0.
mbed_official	146:f64d43ff0c18	4012	* - 1 - The logic OR of the enabled fault inputs is 1.
mbed_official	146:f64d43ff0c18	4013	*/
mbed_official	146:f64d43ff0c18	4014	//@{
mbed_official	146:f64d43ff0c18	4015	#define BP_FTM_FMS_FAULTIN (5U) //!< Bit position for FTM_FMS_FAULTIN.
mbed_official	146:f64d43ff0c18	4016	#define BM_FTM_FMS_FAULTIN (0x00000020U) //!< Bit mask for FTM_FMS_FAULTIN.
mbed_official	146:f64d43ff0c18	4017	#define BS_FTM_FMS_FAULTIN (1U) //!< Bit field size in bits for FTM_FMS_FAULTIN.
mbed_official	146:f64d43ff0c18	4018
mbed_official	146:f64d43ff0c18	4019	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4020	//! @brief Read current value of the FTM_FMS_FAULTIN field.
mbed_official	146:f64d43ff0c18	4021	#define BR_FTM_FMS_FAULTIN(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTIN))
mbed_official	146:f64d43ff0c18	4022	#endif
mbed_official	146:f64d43ff0c18	4023	//@}
mbed_official	146:f64d43ff0c18	4024
mbed_official	146:f64d43ff0c18	4025	/*!
mbed_official	146:f64d43ff0c18	4026	* @name Register FTM_FMS, field WPEN[6] (RW)
mbed_official	146:f64d43ff0c18	4027	*
mbed_official	146:f64d43ff0c18	4028	* The WPEN bit is the negation of the WPDIS bit. WPEN is set when 1 is written
mbed_official	146:f64d43ff0c18	4029	* to it. WPEN is cleared when WPEN bit is read as a 1 and then 1 is written to
mbed_official	146:f64d43ff0c18	4030	* WPDIS. Writing 0 to WPEN has no effect.
mbed_official	146:f64d43ff0c18	4031	*
mbed_official	146:f64d43ff0c18	4032	* Values:
mbed_official	146:f64d43ff0c18	4033	* - 0 - Write protection is disabled. Write protected bits can be written.
mbed_official	146:f64d43ff0c18	4034	* - 1 - Write protection is enabled. Write protected bits cannot be written.
mbed_official	146:f64d43ff0c18	4035	*/
mbed_official	146:f64d43ff0c18	4036	//@{
mbed_official	146:f64d43ff0c18	4037	#define BP_FTM_FMS_WPEN (6U) //!< Bit position for FTM_FMS_WPEN.
mbed_official	146:f64d43ff0c18	4038	#define BM_FTM_FMS_WPEN (0x00000040U) //!< Bit mask for FTM_FMS_WPEN.
mbed_official	146:f64d43ff0c18	4039	#define BS_FTM_FMS_WPEN (1U) //!< Bit field size in bits for FTM_FMS_WPEN.
mbed_official	146:f64d43ff0c18	4040
mbed_official	146:f64d43ff0c18	4041	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4042	//! @brief Read current value of the FTM_FMS_WPEN field.
mbed_official	146:f64d43ff0c18	4043	#define BR_FTM_FMS_WPEN(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_WPEN))
mbed_official	146:f64d43ff0c18	4044	#endif
mbed_official	146:f64d43ff0c18	4045
mbed_official	146:f64d43ff0c18	4046	//! @brief Format value for bitfield FTM_FMS_WPEN.
mbed_official	146:f64d43ff0c18	4047	#define BF_FTM_FMS_WPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FMS_WPEN), uint32_t) & BM_FTM_FMS_WPEN)
mbed_official	146:f64d43ff0c18	4048
mbed_official	146:f64d43ff0c18	4049	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4050	//! @brief Set the WPEN field to a new value.
mbed_official	146:f64d43ff0c18	4051	#define BW_FTM_FMS_WPEN(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_WPEN) = (v))
mbed_official	146:f64d43ff0c18	4052	#endif
mbed_official	146:f64d43ff0c18	4053	//@}
mbed_official	146:f64d43ff0c18	4054
mbed_official	146:f64d43ff0c18	4055	/*!
mbed_official	146:f64d43ff0c18	4056	* @name Register FTM_FMS, field FAULTF[7] (ROWZ)
mbed_official	146:f64d43ff0c18	4057	*
mbed_official	146:f64d43ff0c18	4058	* Represents the logic OR of the individual FAULTFj bits where j = 3, 2, 1, 0.
mbed_official	146:f64d43ff0c18	4059	* Clear FAULTF by reading the FMS register while FAULTF is set and then writing
mbed_official	146:f64d43ff0c18	4060	* a 0 to FAULTF while there is no existing fault condition at the enabled fault
mbed_official	146:f64d43ff0c18	4061	* inputs. Writing a 1 to FAULTF has no effect. If another fault condition is
mbed_official	146:f64d43ff0c18	4062	* detected in an enabled fault input before the clearing sequence is completed, the
mbed_official	146:f64d43ff0c18	4063	* sequence is reset so FAULTF remains set after the clearing sequence is
mbed_official	146:f64d43ff0c18	4064	* completed for the earlier fault condition. FAULTF is also cleared when FAULTFj bits
mbed_official	146:f64d43ff0c18	4065	* are cleared individually.
mbed_official	146:f64d43ff0c18	4066	*
mbed_official	146:f64d43ff0c18	4067	* Values:
mbed_official	146:f64d43ff0c18	4068	* - 0 - No fault condition was detected.
mbed_official	146:f64d43ff0c18	4069	* - 1 - A fault condition was detected.
mbed_official	146:f64d43ff0c18	4070	*/
mbed_official	146:f64d43ff0c18	4071	//@{
mbed_official	146:f64d43ff0c18	4072	#define BP_FTM_FMS_FAULTF (7U) //!< Bit position for FTM_FMS_FAULTF.
mbed_official	146:f64d43ff0c18	4073	#define BM_FTM_FMS_FAULTF (0x00000080U) //!< Bit mask for FTM_FMS_FAULTF.
mbed_official	146:f64d43ff0c18	4074	#define BS_FTM_FMS_FAULTF (1U) //!< Bit field size in bits for FTM_FMS_FAULTF.
mbed_official	146:f64d43ff0c18	4075
mbed_official	146:f64d43ff0c18	4076	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4077	//! @brief Read current value of the FTM_FMS_FAULTF field.
mbed_official	146:f64d43ff0c18	4078	#define BR_FTM_FMS_FAULTF(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF))
mbed_official	146:f64d43ff0c18	4079	#endif
mbed_official	146:f64d43ff0c18	4080	//@}
mbed_official	146:f64d43ff0c18	4081
mbed_official	146:f64d43ff0c18	4082	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	4083	// HW_FTM_FILTER - Input Capture Filter Control
mbed_official	146:f64d43ff0c18	4084	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	4085
mbed_official	146:f64d43ff0c18	4086	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4087	/*!
mbed_official	146:f64d43ff0c18	4088	* @brief HW_FTM_FILTER - Input Capture Filter Control (RW)
mbed_official	146:f64d43ff0c18	4089	*
mbed_official	146:f64d43ff0c18	4090	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	4091	*
mbed_official	146:f64d43ff0c18	4092	* This register selects the filter value for the inputs of channels. Channels
mbed_official	146:f64d43ff0c18	4093	* 4, 5, 6 and 7 do not have an input filter. Writing to the FILTER register has
mbed_official	146:f64d43ff0c18	4094	* immediate effect and must be done only when the channels 0, 1, 2, and 3 are not
mbed_official	146:f64d43ff0c18	4095	* in input modes. Failure to do this could result in a missing valid signal.
mbed_official	146:f64d43ff0c18	4096	*/
mbed_official	146:f64d43ff0c18	4097	typedef union _hw_ftm_filter
mbed_official	146:f64d43ff0c18	4098	{
mbed_official	146:f64d43ff0c18	4099	uint32_t U;
mbed_official	146:f64d43ff0c18	4100	struct _hw_ftm_filter_bitfields
mbed_official	146:f64d43ff0c18	4101	{
mbed_official	146:f64d43ff0c18	4102	uint32_t CH0FVAL : 4; //!< [3:0] Channel 0 Input Filter
mbed_official	146:f64d43ff0c18	4103	uint32_t CH1FVAL : 4; //!< [7:4] Channel 1 Input Filter
mbed_official	146:f64d43ff0c18	4104	uint32_t CH2FVAL : 4; //!< [11:8] Channel 2 Input Filter
mbed_official	146:f64d43ff0c18	4105	uint32_t CH3FVAL : 4; //!< [15:12] Channel 3 Input Filter
mbed_official	146:f64d43ff0c18	4106	uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official	146:f64d43ff0c18	4107	} B;
mbed_official	146:f64d43ff0c18	4108	} hw_ftm_filter_t;
mbed_official	146:f64d43ff0c18	4109	#endif
mbed_official	146:f64d43ff0c18	4110
mbed_official	146:f64d43ff0c18	4111	/*!
mbed_official	146:f64d43ff0c18	4112	* @name Constants and macros for entire FTM_FILTER register
mbed_official	146:f64d43ff0c18	4113	*/
mbed_official	146:f64d43ff0c18	4114	//@{
mbed_official	146:f64d43ff0c18	4115	#define HW_FTM_FILTER_ADDR(x) (REGS_FTM_BASE(x) + 0x78U)
mbed_official	146:f64d43ff0c18	4116
mbed_official	146:f64d43ff0c18	4117	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4118	#define HW_FTM_FILTER(x) ((__IO hw_ftm_filter_t ) HW_FTM_FILTER_ADDR(x))
mbed_official	146:f64d43ff0c18	4119	#define HW_FTM_FILTER_RD(x) (HW_FTM_FILTER(x).U)
mbed_official	146:f64d43ff0c18	4120	#define HW_FTM_FILTER_WR(x, v) (HW_FTM_FILTER(x).U = (v))
mbed_official	146:f64d43ff0c18	4121	#define HW_FTM_FILTER_SET(x, v) (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	4122	#define HW_FTM_FILTER_CLR(x, v) (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	4123	#define HW_FTM_FILTER_TOG(x, v) (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	4124	#endif
mbed_official	146:f64d43ff0c18	4125	//@}
mbed_official	146:f64d43ff0c18	4126
mbed_official	146:f64d43ff0c18	4127	/*
mbed_official	146:f64d43ff0c18	4128	* Constants & macros for individual FTM_FILTER bitfields
mbed_official	146:f64d43ff0c18	4129	*/
mbed_official	146:f64d43ff0c18	4130
mbed_official	146:f64d43ff0c18	4131	/*!
mbed_official	146:f64d43ff0c18	4132	* @name Register FTM_FILTER, field CH0FVAL[3:0] (RW)
mbed_official	146:f64d43ff0c18	4133	*
mbed_official	146:f64d43ff0c18	4134	* Selects the filter value for the channel input. The filter is disabled when
mbed_official	146:f64d43ff0c18	4135	* the value is zero.
mbed_official	146:f64d43ff0c18	4136	*/
mbed_official	146:f64d43ff0c18	4137	//@{
mbed_official	146:f64d43ff0c18	4138	#define BP_FTM_FILTER_CH0FVAL (0U) //!< Bit position for FTM_FILTER_CH0FVAL.
mbed_official	146:f64d43ff0c18	4139	#define BM_FTM_FILTER_CH0FVAL (0x0000000FU) //!< Bit mask for FTM_FILTER_CH0FVAL.
mbed_official	146:f64d43ff0c18	4140	#define BS_FTM_FILTER_CH0FVAL (4U) //!< Bit field size in bits for FTM_FILTER_CH0FVAL.
mbed_official	146:f64d43ff0c18	4141
mbed_official	146:f64d43ff0c18	4142	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4143	//! @brief Read current value of the FTM_FILTER_CH0FVAL field.
mbed_official	146:f64d43ff0c18	4144	#define BR_FTM_FILTER_CH0FVAL(x) (HW_FTM_FILTER(x).B.CH0FVAL)
mbed_official	146:f64d43ff0c18	4145	#endif
mbed_official	146:f64d43ff0c18	4146
mbed_official	146:f64d43ff0c18	4147	//! @brief Format value for bitfield FTM_FILTER_CH0FVAL.
mbed_official	146:f64d43ff0c18	4148	#define BF_FTM_FILTER_CH0FVAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FILTER_CH0FVAL), uint32_t) & BM_FTM_FILTER_CH0FVAL)
mbed_official	146:f64d43ff0c18	4149
mbed_official	146:f64d43ff0c18	4150	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4151	//! @brief Set the CH0FVAL field to a new value.
mbed_official	146:f64d43ff0c18	4152	#define BW_FTM_FILTER_CH0FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH0FVAL) \| BF_FTM_FILTER_CH0FVAL(v)))
mbed_official	146:f64d43ff0c18	4153	#endif
mbed_official	146:f64d43ff0c18	4154	//@}
mbed_official	146:f64d43ff0c18	4155
mbed_official	146:f64d43ff0c18	4156	/*!
mbed_official	146:f64d43ff0c18	4157	* @name Register FTM_FILTER, field CH1FVAL[7:4] (RW)
mbed_official	146:f64d43ff0c18	4158	*
mbed_official	146:f64d43ff0c18	4159	* Selects the filter value for the channel input. The filter is disabled when
mbed_official	146:f64d43ff0c18	4160	* the value is zero.
mbed_official	146:f64d43ff0c18	4161	*/
mbed_official	146:f64d43ff0c18	4162	//@{
mbed_official	146:f64d43ff0c18	4163	#define BP_FTM_FILTER_CH1FVAL (4U) //!< Bit position for FTM_FILTER_CH1FVAL.
mbed_official	146:f64d43ff0c18	4164	#define BM_FTM_FILTER_CH1FVAL (0x000000F0U) //!< Bit mask for FTM_FILTER_CH1FVAL.
mbed_official	146:f64d43ff0c18	4165	#define BS_FTM_FILTER_CH1FVAL (4U) //!< Bit field size in bits for FTM_FILTER_CH1FVAL.
mbed_official	146:f64d43ff0c18	4166
mbed_official	146:f64d43ff0c18	4167	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4168	//! @brief Read current value of the FTM_FILTER_CH1FVAL field.
mbed_official	146:f64d43ff0c18	4169	#define BR_FTM_FILTER_CH1FVAL(x) (HW_FTM_FILTER(x).B.CH1FVAL)
mbed_official	146:f64d43ff0c18	4170	#endif
mbed_official	146:f64d43ff0c18	4171
mbed_official	146:f64d43ff0c18	4172	//! @brief Format value for bitfield FTM_FILTER_CH1FVAL.
mbed_official	146:f64d43ff0c18	4173	#define BF_FTM_FILTER_CH1FVAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FILTER_CH1FVAL), uint32_t) & BM_FTM_FILTER_CH1FVAL)
mbed_official	146:f64d43ff0c18	4174
mbed_official	146:f64d43ff0c18	4175	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4176	//! @brief Set the CH1FVAL field to a new value.
mbed_official	146:f64d43ff0c18	4177	#define BW_FTM_FILTER_CH1FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH1FVAL) \| BF_FTM_FILTER_CH1FVAL(v)))
mbed_official	146:f64d43ff0c18	4178	#endif
mbed_official	146:f64d43ff0c18	4179	//@}
mbed_official	146:f64d43ff0c18	4180
mbed_official	146:f64d43ff0c18	4181	/*!
mbed_official	146:f64d43ff0c18	4182	* @name Register FTM_FILTER, field CH2FVAL[11:8] (RW)
mbed_official	146:f64d43ff0c18	4183	*
mbed_official	146:f64d43ff0c18	4184	* Selects the filter value for the channel input. The filter is disabled when
mbed_official	146:f64d43ff0c18	4185	* the value is zero.
mbed_official	146:f64d43ff0c18	4186	*/
mbed_official	146:f64d43ff0c18	4187	//@{
mbed_official	146:f64d43ff0c18	4188	#define BP_FTM_FILTER_CH2FVAL (8U) //!< Bit position for FTM_FILTER_CH2FVAL.
mbed_official	146:f64d43ff0c18	4189	#define BM_FTM_FILTER_CH2FVAL (0x00000F00U) //!< Bit mask for FTM_FILTER_CH2FVAL.
mbed_official	146:f64d43ff0c18	4190	#define BS_FTM_FILTER_CH2FVAL (4U) //!< Bit field size in bits for FTM_FILTER_CH2FVAL.
mbed_official	146:f64d43ff0c18	4191
mbed_official	146:f64d43ff0c18	4192	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4193	//! @brief Read current value of the FTM_FILTER_CH2FVAL field.
mbed_official	146:f64d43ff0c18	4194	#define BR_FTM_FILTER_CH2FVAL(x) (HW_FTM_FILTER(x).B.CH2FVAL)
mbed_official	146:f64d43ff0c18	4195	#endif
mbed_official	146:f64d43ff0c18	4196
mbed_official	146:f64d43ff0c18	4197	//! @brief Format value for bitfield FTM_FILTER_CH2FVAL.
mbed_official	146:f64d43ff0c18	4198	#define BF_FTM_FILTER_CH2FVAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FILTER_CH2FVAL), uint32_t) & BM_FTM_FILTER_CH2FVAL)
mbed_official	146:f64d43ff0c18	4199
mbed_official	146:f64d43ff0c18	4200	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4201	//! @brief Set the CH2FVAL field to a new value.
mbed_official	146:f64d43ff0c18	4202	#define BW_FTM_FILTER_CH2FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH2FVAL) \| BF_FTM_FILTER_CH2FVAL(v)))
mbed_official	146:f64d43ff0c18	4203	#endif
mbed_official	146:f64d43ff0c18	4204	//@}
mbed_official	146:f64d43ff0c18	4205
mbed_official	146:f64d43ff0c18	4206	/*!
mbed_official	146:f64d43ff0c18	4207	* @name Register FTM_FILTER, field CH3FVAL[15:12] (RW)
mbed_official	146:f64d43ff0c18	4208	*
mbed_official	146:f64d43ff0c18	4209	* Selects the filter value for the channel input. The filter is disabled when
mbed_official	146:f64d43ff0c18	4210	* the value is zero.
mbed_official	146:f64d43ff0c18	4211	*/
mbed_official	146:f64d43ff0c18	4212	//@{
mbed_official	146:f64d43ff0c18	4213	#define BP_FTM_FILTER_CH3FVAL (12U) //!< Bit position for FTM_FILTER_CH3FVAL.
mbed_official	146:f64d43ff0c18	4214	#define BM_FTM_FILTER_CH3FVAL (0x0000F000U) //!< Bit mask for FTM_FILTER_CH3FVAL.
mbed_official	146:f64d43ff0c18	4215	#define BS_FTM_FILTER_CH3FVAL (4U) //!< Bit field size in bits for FTM_FILTER_CH3FVAL.
mbed_official	146:f64d43ff0c18	4216
mbed_official	146:f64d43ff0c18	4217	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4218	//! @brief Read current value of the FTM_FILTER_CH3FVAL field.
mbed_official	146:f64d43ff0c18	4219	#define BR_FTM_FILTER_CH3FVAL(x) (HW_FTM_FILTER(x).B.CH3FVAL)
mbed_official	146:f64d43ff0c18	4220	#endif
mbed_official	146:f64d43ff0c18	4221
mbed_official	146:f64d43ff0c18	4222	//! @brief Format value for bitfield FTM_FILTER_CH3FVAL.
mbed_official	146:f64d43ff0c18	4223	#define BF_FTM_FILTER_CH3FVAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FILTER_CH3FVAL), uint32_t) & BM_FTM_FILTER_CH3FVAL)
mbed_official	146:f64d43ff0c18	4224
mbed_official	146:f64d43ff0c18	4225	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4226	//! @brief Set the CH3FVAL field to a new value.
mbed_official	146:f64d43ff0c18	4227	#define BW_FTM_FILTER_CH3FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH3FVAL) \| BF_FTM_FILTER_CH3FVAL(v)))
mbed_official	146:f64d43ff0c18	4228	#endif
mbed_official	146:f64d43ff0c18	4229	//@}
mbed_official	146:f64d43ff0c18	4230
mbed_official	146:f64d43ff0c18	4231	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	4232	// HW_FTM_FLTCTRL - Fault Control
mbed_official	146:f64d43ff0c18	4233	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	4234
mbed_official	146:f64d43ff0c18	4235	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4236	/*!
mbed_official	146:f64d43ff0c18	4237	* @brief HW_FTM_FLTCTRL - Fault Control (RW)
mbed_official	146:f64d43ff0c18	4238	*
mbed_official	146:f64d43ff0c18	4239	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	4240	*
mbed_official	146:f64d43ff0c18	4241	* This register selects the filter value for the fault inputs, enables the
mbed_official	146:f64d43ff0c18	4242	* fault inputs and the fault inputs filter.
mbed_official	146:f64d43ff0c18	4243	*/
mbed_official	146:f64d43ff0c18	4244	typedef union _hw_ftm_fltctrl
mbed_official	146:f64d43ff0c18	4245	{
mbed_official	146:f64d43ff0c18	4246	uint32_t U;
mbed_official	146:f64d43ff0c18	4247	struct _hw_ftm_fltctrl_bitfields
mbed_official	146:f64d43ff0c18	4248	{
mbed_official	146:f64d43ff0c18	4249	uint32_t FAULT0EN : 1; //!< [0] Fault Input 0 Enable
mbed_official	146:f64d43ff0c18	4250	uint32_t FAULT1EN : 1; //!< [1] Fault Input 1 Enable
mbed_official	146:f64d43ff0c18	4251	uint32_t FAULT2EN : 1; //!< [2] Fault Input 2 Enable
mbed_official	146:f64d43ff0c18	4252	uint32_t FAULT3EN : 1; //!< [3] Fault Input 3 Enable
mbed_official	146:f64d43ff0c18	4253	uint32_t FFLTR0EN : 1; //!< [4] Fault Input 0 Filter Enable
mbed_official	146:f64d43ff0c18	4254	uint32_t FFLTR1EN : 1; //!< [5] Fault Input 1 Filter Enable
mbed_official	146:f64d43ff0c18	4255	uint32_t FFLTR2EN : 1; //!< [6] Fault Input 2 Filter Enable
mbed_official	146:f64d43ff0c18	4256	uint32_t FFLTR3EN : 1; //!< [7] Fault Input 3 Filter Enable
mbed_official	146:f64d43ff0c18	4257	uint32_t FFVAL : 4; //!< [11:8] Fault Input Filter
mbed_official	146:f64d43ff0c18	4258	uint32_t RESERVED0 : 20; //!< [31:12]
mbed_official	146:f64d43ff0c18	4259	} B;
mbed_official	146:f64d43ff0c18	4260	} hw_ftm_fltctrl_t;
mbed_official	146:f64d43ff0c18	4261	#endif
mbed_official	146:f64d43ff0c18	4262
mbed_official	146:f64d43ff0c18	4263	/*!
mbed_official	146:f64d43ff0c18	4264	* @name Constants and macros for entire FTM_FLTCTRL register
mbed_official	146:f64d43ff0c18	4265	*/
mbed_official	146:f64d43ff0c18	4266	//@{
mbed_official	146:f64d43ff0c18	4267	#define HW_FTM_FLTCTRL_ADDR(x) (REGS_FTM_BASE(x) + 0x7CU)
mbed_official	146:f64d43ff0c18	4268
mbed_official	146:f64d43ff0c18	4269	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4270	#define HW_FTM_FLTCTRL(x) ((__IO hw_ftm_fltctrl_t ) HW_FTM_FLTCTRL_ADDR(x))
mbed_official	146:f64d43ff0c18	4271	#define HW_FTM_FLTCTRL_RD(x) (HW_FTM_FLTCTRL(x).U)
mbed_official	146:f64d43ff0c18	4272	#define HW_FTM_FLTCTRL_WR(x, v) (HW_FTM_FLTCTRL(x).U = (v))
mbed_official	146:f64d43ff0c18	4273	#define HW_FTM_FLTCTRL_SET(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	4274	#define HW_FTM_FLTCTRL_CLR(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	4275	#define HW_FTM_FLTCTRL_TOG(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	4276	#endif
mbed_official	146:f64d43ff0c18	4277	//@}
mbed_official	146:f64d43ff0c18	4278
mbed_official	146:f64d43ff0c18	4279	/*
mbed_official	146:f64d43ff0c18	4280	* Constants & macros for individual FTM_FLTCTRL bitfields
mbed_official	146:f64d43ff0c18	4281	*/
mbed_official	146:f64d43ff0c18	4282
mbed_official	146:f64d43ff0c18	4283	/*!
mbed_official	146:f64d43ff0c18	4284	* @name Register FTM_FLTCTRL, field FAULT0EN[0] (RW)
mbed_official	146:f64d43ff0c18	4285	*
mbed_official	146:f64d43ff0c18	4286	* Enables the fault input. This field is write protected. It can be written
mbed_official	146:f64d43ff0c18	4287	* only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	4288	*
mbed_official	146:f64d43ff0c18	4289	* Values:
mbed_official	146:f64d43ff0c18	4290	* - 0 - Fault input is disabled.
mbed_official	146:f64d43ff0c18	4291	* - 1 - Fault input is enabled.
mbed_official	146:f64d43ff0c18	4292	*/
mbed_official	146:f64d43ff0c18	4293	//@{
mbed_official	146:f64d43ff0c18	4294	#define BP_FTM_FLTCTRL_FAULT0EN (0U) //!< Bit position for FTM_FLTCTRL_FAULT0EN.
mbed_official	146:f64d43ff0c18	4295	#define BM_FTM_FLTCTRL_FAULT0EN (0x00000001U) //!< Bit mask for FTM_FLTCTRL_FAULT0EN.
mbed_official	146:f64d43ff0c18	4296	#define BS_FTM_FLTCTRL_FAULT0EN (1U) //!< Bit field size in bits for FTM_FLTCTRL_FAULT0EN.
mbed_official	146:f64d43ff0c18	4297
mbed_official	146:f64d43ff0c18	4298	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4299	//! @brief Read current value of the FTM_FLTCTRL_FAULT0EN field.
mbed_official	146:f64d43ff0c18	4300	#define BR_FTM_FLTCTRL_FAULT0EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT0EN))
mbed_official	146:f64d43ff0c18	4301	#endif
mbed_official	146:f64d43ff0c18	4302
mbed_official	146:f64d43ff0c18	4303	//! @brief Format value for bitfield FTM_FLTCTRL_FAULT0EN.
mbed_official	146:f64d43ff0c18	4304	#define BF_FTM_FLTCTRL_FAULT0EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FAULT0EN), uint32_t) & BM_FTM_FLTCTRL_FAULT0EN)
mbed_official	146:f64d43ff0c18	4305
mbed_official	146:f64d43ff0c18	4306	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4307	//! @brief Set the FAULT0EN field to a new value.
mbed_official	146:f64d43ff0c18	4308	#define BW_FTM_FLTCTRL_FAULT0EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT0EN) = (v))
mbed_official	146:f64d43ff0c18	4309	#endif
mbed_official	146:f64d43ff0c18	4310	//@}
mbed_official	146:f64d43ff0c18	4311
mbed_official	146:f64d43ff0c18	4312	/*!
mbed_official	146:f64d43ff0c18	4313	* @name Register FTM_FLTCTRL, field FAULT1EN[1] (RW)
mbed_official	146:f64d43ff0c18	4314	*
mbed_official	146:f64d43ff0c18	4315	* Enables the fault input. This field is write protected. It can be written
mbed_official	146:f64d43ff0c18	4316	* only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	4317	*
mbed_official	146:f64d43ff0c18	4318	* Values:
mbed_official	146:f64d43ff0c18	4319	* - 0 - Fault input is disabled.
mbed_official	146:f64d43ff0c18	4320	* - 1 - Fault input is enabled.
mbed_official	146:f64d43ff0c18	4321	*/
mbed_official	146:f64d43ff0c18	4322	//@{
mbed_official	146:f64d43ff0c18	4323	#define BP_FTM_FLTCTRL_FAULT1EN (1U) //!< Bit position for FTM_FLTCTRL_FAULT1EN.
mbed_official	146:f64d43ff0c18	4324	#define BM_FTM_FLTCTRL_FAULT1EN (0x00000002U) //!< Bit mask for FTM_FLTCTRL_FAULT1EN.
mbed_official	146:f64d43ff0c18	4325	#define BS_FTM_FLTCTRL_FAULT1EN (1U) //!< Bit field size in bits for FTM_FLTCTRL_FAULT1EN.
mbed_official	146:f64d43ff0c18	4326
mbed_official	146:f64d43ff0c18	4327	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4328	//! @brief Read current value of the FTM_FLTCTRL_FAULT1EN field.
mbed_official	146:f64d43ff0c18	4329	#define BR_FTM_FLTCTRL_FAULT1EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT1EN))
mbed_official	146:f64d43ff0c18	4330	#endif
mbed_official	146:f64d43ff0c18	4331
mbed_official	146:f64d43ff0c18	4332	//! @brief Format value for bitfield FTM_FLTCTRL_FAULT1EN.
mbed_official	146:f64d43ff0c18	4333	#define BF_FTM_FLTCTRL_FAULT1EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FAULT1EN), uint32_t) & BM_FTM_FLTCTRL_FAULT1EN)
mbed_official	146:f64d43ff0c18	4334
mbed_official	146:f64d43ff0c18	4335	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4336	//! @brief Set the FAULT1EN field to a new value.
mbed_official	146:f64d43ff0c18	4337	#define BW_FTM_FLTCTRL_FAULT1EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT1EN) = (v))
mbed_official	146:f64d43ff0c18	4338	#endif
mbed_official	146:f64d43ff0c18	4339	//@}
mbed_official	146:f64d43ff0c18	4340
mbed_official	146:f64d43ff0c18	4341	/*!
mbed_official	146:f64d43ff0c18	4342	* @name Register FTM_FLTCTRL, field FAULT2EN[2] (RW)
mbed_official	146:f64d43ff0c18	4343	*
mbed_official	146:f64d43ff0c18	4344	* Enables the fault input. This field is write protected. It can be written
mbed_official	146:f64d43ff0c18	4345	* only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	4346	*
mbed_official	146:f64d43ff0c18	4347	* Values:
mbed_official	146:f64d43ff0c18	4348	* - 0 - Fault input is disabled.
mbed_official	146:f64d43ff0c18	4349	* - 1 - Fault input is enabled.
mbed_official	146:f64d43ff0c18	4350	*/
mbed_official	146:f64d43ff0c18	4351	//@{
mbed_official	146:f64d43ff0c18	4352	#define BP_FTM_FLTCTRL_FAULT2EN (2U) //!< Bit position for FTM_FLTCTRL_FAULT2EN.
mbed_official	146:f64d43ff0c18	4353	#define BM_FTM_FLTCTRL_FAULT2EN (0x00000004U) //!< Bit mask for FTM_FLTCTRL_FAULT2EN.
mbed_official	146:f64d43ff0c18	4354	#define BS_FTM_FLTCTRL_FAULT2EN (1U) //!< Bit field size in bits for FTM_FLTCTRL_FAULT2EN.
mbed_official	146:f64d43ff0c18	4355
mbed_official	146:f64d43ff0c18	4356	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4357	//! @brief Read current value of the FTM_FLTCTRL_FAULT2EN field.
mbed_official	146:f64d43ff0c18	4358	#define BR_FTM_FLTCTRL_FAULT2EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT2EN))
mbed_official	146:f64d43ff0c18	4359	#endif
mbed_official	146:f64d43ff0c18	4360
mbed_official	146:f64d43ff0c18	4361	//! @brief Format value for bitfield FTM_FLTCTRL_FAULT2EN.
mbed_official	146:f64d43ff0c18	4362	#define BF_FTM_FLTCTRL_FAULT2EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FAULT2EN), uint32_t) & BM_FTM_FLTCTRL_FAULT2EN)
mbed_official	146:f64d43ff0c18	4363
mbed_official	146:f64d43ff0c18	4364	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4365	//! @brief Set the FAULT2EN field to a new value.
mbed_official	146:f64d43ff0c18	4366	#define BW_FTM_FLTCTRL_FAULT2EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT2EN) = (v))
mbed_official	146:f64d43ff0c18	4367	#endif
mbed_official	146:f64d43ff0c18	4368	//@}
mbed_official	146:f64d43ff0c18	4369
mbed_official	146:f64d43ff0c18	4370	/*!
mbed_official	146:f64d43ff0c18	4371	* @name Register FTM_FLTCTRL, field FAULT3EN[3] (RW)
mbed_official	146:f64d43ff0c18	4372	*
mbed_official	146:f64d43ff0c18	4373	* Enables the fault input. This field is write protected. It can be written
mbed_official	146:f64d43ff0c18	4374	* only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	4375	*
mbed_official	146:f64d43ff0c18	4376	* Values:
mbed_official	146:f64d43ff0c18	4377	* - 0 - Fault input is disabled.
mbed_official	146:f64d43ff0c18	4378	* - 1 - Fault input is enabled.
mbed_official	146:f64d43ff0c18	4379	*/
mbed_official	146:f64d43ff0c18	4380	//@{
mbed_official	146:f64d43ff0c18	4381	#define BP_FTM_FLTCTRL_FAULT3EN (3U) //!< Bit position for FTM_FLTCTRL_FAULT3EN.
mbed_official	146:f64d43ff0c18	4382	#define BM_FTM_FLTCTRL_FAULT3EN (0x00000008U) //!< Bit mask for FTM_FLTCTRL_FAULT3EN.
mbed_official	146:f64d43ff0c18	4383	#define BS_FTM_FLTCTRL_FAULT3EN (1U) //!< Bit field size in bits for FTM_FLTCTRL_FAULT3EN.
mbed_official	146:f64d43ff0c18	4384
mbed_official	146:f64d43ff0c18	4385	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4386	//! @brief Read current value of the FTM_FLTCTRL_FAULT3EN field.
mbed_official	146:f64d43ff0c18	4387	#define BR_FTM_FLTCTRL_FAULT3EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT3EN))
mbed_official	146:f64d43ff0c18	4388	#endif
mbed_official	146:f64d43ff0c18	4389
mbed_official	146:f64d43ff0c18	4390	//! @brief Format value for bitfield FTM_FLTCTRL_FAULT3EN.
mbed_official	146:f64d43ff0c18	4391	#define BF_FTM_FLTCTRL_FAULT3EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FAULT3EN), uint32_t) & BM_FTM_FLTCTRL_FAULT3EN)
mbed_official	146:f64d43ff0c18	4392
mbed_official	146:f64d43ff0c18	4393	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4394	//! @brief Set the FAULT3EN field to a new value.
mbed_official	146:f64d43ff0c18	4395	#define BW_FTM_FLTCTRL_FAULT3EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT3EN) = (v))
mbed_official	146:f64d43ff0c18	4396	#endif
mbed_official	146:f64d43ff0c18	4397	//@}
mbed_official	146:f64d43ff0c18	4398
mbed_official	146:f64d43ff0c18	4399	/*!
mbed_official	146:f64d43ff0c18	4400	* @name Register FTM_FLTCTRL, field FFLTR0EN[4] (RW)
mbed_official	146:f64d43ff0c18	4401	*
mbed_official	146:f64d43ff0c18	4402	* Enables the filter for the fault input. This field is write protected. It can
mbed_official	146:f64d43ff0c18	4403	* be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	4404	*
mbed_official	146:f64d43ff0c18	4405	* Values:
mbed_official	146:f64d43ff0c18	4406	* - 0 - Fault input filter is disabled.
mbed_official	146:f64d43ff0c18	4407	* - 1 - Fault input filter is enabled.
mbed_official	146:f64d43ff0c18	4408	*/
mbed_official	146:f64d43ff0c18	4409	//@{
mbed_official	146:f64d43ff0c18	4410	#define BP_FTM_FLTCTRL_FFLTR0EN (4U) //!< Bit position for FTM_FLTCTRL_FFLTR0EN.
mbed_official	146:f64d43ff0c18	4411	#define BM_FTM_FLTCTRL_FFLTR0EN (0x00000010U) //!< Bit mask for FTM_FLTCTRL_FFLTR0EN.
mbed_official	146:f64d43ff0c18	4412	#define BS_FTM_FLTCTRL_FFLTR0EN (1U) //!< Bit field size in bits for FTM_FLTCTRL_FFLTR0EN.
mbed_official	146:f64d43ff0c18	4413
mbed_official	146:f64d43ff0c18	4414	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4415	//! @brief Read current value of the FTM_FLTCTRL_FFLTR0EN field.
mbed_official	146:f64d43ff0c18	4416	#define BR_FTM_FLTCTRL_FFLTR0EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR0EN))
mbed_official	146:f64d43ff0c18	4417	#endif
mbed_official	146:f64d43ff0c18	4418
mbed_official	146:f64d43ff0c18	4419	//! @brief Format value for bitfield FTM_FLTCTRL_FFLTR0EN.
mbed_official	146:f64d43ff0c18	4420	#define BF_FTM_FLTCTRL_FFLTR0EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FFLTR0EN), uint32_t) & BM_FTM_FLTCTRL_FFLTR0EN)
mbed_official	146:f64d43ff0c18	4421
mbed_official	146:f64d43ff0c18	4422	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4423	//! @brief Set the FFLTR0EN field to a new value.
mbed_official	146:f64d43ff0c18	4424	#define BW_FTM_FLTCTRL_FFLTR0EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR0EN) = (v))
mbed_official	146:f64d43ff0c18	4425	#endif
mbed_official	146:f64d43ff0c18	4426	//@}
mbed_official	146:f64d43ff0c18	4427
mbed_official	146:f64d43ff0c18	4428	/*!
mbed_official	146:f64d43ff0c18	4429	* @name Register FTM_FLTCTRL, field FFLTR1EN[5] (RW)
mbed_official	146:f64d43ff0c18	4430	*
mbed_official	146:f64d43ff0c18	4431	* Enables the filter for the fault input. This field is write protected. It can
mbed_official	146:f64d43ff0c18	4432	* be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	4433	*
mbed_official	146:f64d43ff0c18	4434	* Values:
mbed_official	146:f64d43ff0c18	4435	* - 0 - Fault input filter is disabled.
mbed_official	146:f64d43ff0c18	4436	* - 1 - Fault input filter is enabled.
mbed_official	146:f64d43ff0c18	4437	*/
mbed_official	146:f64d43ff0c18	4438	//@{
mbed_official	146:f64d43ff0c18	4439	#define BP_FTM_FLTCTRL_FFLTR1EN (5U) //!< Bit position for FTM_FLTCTRL_FFLTR1EN.
mbed_official	146:f64d43ff0c18	4440	#define BM_FTM_FLTCTRL_FFLTR1EN (0x00000020U) //!< Bit mask for FTM_FLTCTRL_FFLTR1EN.
mbed_official	146:f64d43ff0c18	4441	#define BS_FTM_FLTCTRL_FFLTR1EN (1U) //!< Bit field size in bits for FTM_FLTCTRL_FFLTR1EN.
mbed_official	146:f64d43ff0c18	4442
mbed_official	146:f64d43ff0c18	4443	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4444	//! @brief Read current value of the FTM_FLTCTRL_FFLTR1EN field.
mbed_official	146:f64d43ff0c18	4445	#define BR_FTM_FLTCTRL_FFLTR1EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR1EN))
mbed_official	146:f64d43ff0c18	4446	#endif
mbed_official	146:f64d43ff0c18	4447
mbed_official	146:f64d43ff0c18	4448	//! @brief Format value for bitfield FTM_FLTCTRL_FFLTR1EN.
mbed_official	146:f64d43ff0c18	4449	#define BF_FTM_FLTCTRL_FFLTR1EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FFLTR1EN), uint32_t) & BM_FTM_FLTCTRL_FFLTR1EN)
mbed_official	146:f64d43ff0c18	4450
mbed_official	146:f64d43ff0c18	4451	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4452	//! @brief Set the FFLTR1EN field to a new value.
mbed_official	146:f64d43ff0c18	4453	#define BW_FTM_FLTCTRL_FFLTR1EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR1EN) = (v))
mbed_official	146:f64d43ff0c18	4454	#endif
mbed_official	146:f64d43ff0c18	4455	//@}
mbed_official	146:f64d43ff0c18	4456
mbed_official	146:f64d43ff0c18	4457	/*!
mbed_official	146:f64d43ff0c18	4458	* @name Register FTM_FLTCTRL, field FFLTR2EN[6] (RW)
mbed_official	146:f64d43ff0c18	4459	*
mbed_official	146:f64d43ff0c18	4460	* Enables the filter for the fault input. This field is write protected. It can
mbed_official	146:f64d43ff0c18	4461	* be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	4462	*
mbed_official	146:f64d43ff0c18	4463	* Values:
mbed_official	146:f64d43ff0c18	4464	* - 0 - Fault input filter is disabled.
mbed_official	146:f64d43ff0c18	4465	* - 1 - Fault input filter is enabled.
mbed_official	146:f64d43ff0c18	4466	*/
mbed_official	146:f64d43ff0c18	4467	//@{
mbed_official	146:f64d43ff0c18	4468	#define BP_FTM_FLTCTRL_FFLTR2EN (6U) //!< Bit position for FTM_FLTCTRL_FFLTR2EN.
mbed_official	146:f64d43ff0c18	4469	#define BM_FTM_FLTCTRL_FFLTR2EN (0x00000040U) //!< Bit mask for FTM_FLTCTRL_FFLTR2EN.
mbed_official	146:f64d43ff0c18	4470	#define BS_FTM_FLTCTRL_FFLTR2EN (1U) //!< Bit field size in bits for FTM_FLTCTRL_FFLTR2EN.
mbed_official	146:f64d43ff0c18	4471
mbed_official	146:f64d43ff0c18	4472	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4473	//! @brief Read current value of the FTM_FLTCTRL_FFLTR2EN field.
mbed_official	146:f64d43ff0c18	4474	#define BR_FTM_FLTCTRL_FFLTR2EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR2EN))
mbed_official	146:f64d43ff0c18	4475	#endif
mbed_official	146:f64d43ff0c18	4476
mbed_official	146:f64d43ff0c18	4477	//! @brief Format value for bitfield FTM_FLTCTRL_FFLTR2EN.
mbed_official	146:f64d43ff0c18	4478	#define BF_FTM_FLTCTRL_FFLTR2EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FFLTR2EN), uint32_t) & BM_FTM_FLTCTRL_FFLTR2EN)
mbed_official	146:f64d43ff0c18	4479
mbed_official	146:f64d43ff0c18	4480	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4481	//! @brief Set the FFLTR2EN field to a new value.
mbed_official	146:f64d43ff0c18	4482	#define BW_FTM_FLTCTRL_FFLTR2EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR2EN) = (v))
mbed_official	146:f64d43ff0c18	4483	#endif
mbed_official	146:f64d43ff0c18	4484	//@}
mbed_official	146:f64d43ff0c18	4485
mbed_official	146:f64d43ff0c18	4486	/*!
mbed_official	146:f64d43ff0c18	4487	* @name Register FTM_FLTCTRL, field FFLTR3EN[7] (RW)
mbed_official	146:f64d43ff0c18	4488	*
mbed_official	146:f64d43ff0c18	4489	* Enables the filter for the fault input. This field is write protected. It can
mbed_official	146:f64d43ff0c18	4490	* be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	4491	*
mbed_official	146:f64d43ff0c18	4492	* Values:
mbed_official	146:f64d43ff0c18	4493	* - 0 - Fault input filter is disabled.
mbed_official	146:f64d43ff0c18	4494	* - 1 - Fault input filter is enabled.
mbed_official	146:f64d43ff0c18	4495	*/
mbed_official	146:f64d43ff0c18	4496	//@{
mbed_official	146:f64d43ff0c18	4497	#define BP_FTM_FLTCTRL_FFLTR3EN (7U) //!< Bit position for FTM_FLTCTRL_FFLTR3EN.
mbed_official	146:f64d43ff0c18	4498	#define BM_FTM_FLTCTRL_FFLTR3EN (0x00000080U) //!< Bit mask for FTM_FLTCTRL_FFLTR3EN.
mbed_official	146:f64d43ff0c18	4499	#define BS_FTM_FLTCTRL_FFLTR3EN (1U) //!< Bit field size in bits for FTM_FLTCTRL_FFLTR3EN.
mbed_official	146:f64d43ff0c18	4500
mbed_official	146:f64d43ff0c18	4501	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4502	//! @brief Read current value of the FTM_FLTCTRL_FFLTR3EN field.
mbed_official	146:f64d43ff0c18	4503	#define BR_FTM_FLTCTRL_FFLTR3EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR3EN))
mbed_official	146:f64d43ff0c18	4504	#endif
mbed_official	146:f64d43ff0c18	4505
mbed_official	146:f64d43ff0c18	4506	//! @brief Format value for bitfield FTM_FLTCTRL_FFLTR3EN.
mbed_official	146:f64d43ff0c18	4507	#define BF_FTM_FLTCTRL_FFLTR3EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FFLTR3EN), uint32_t) & BM_FTM_FLTCTRL_FFLTR3EN)
mbed_official	146:f64d43ff0c18	4508
mbed_official	146:f64d43ff0c18	4509	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4510	//! @brief Set the FFLTR3EN field to a new value.
mbed_official	146:f64d43ff0c18	4511	#define BW_FTM_FLTCTRL_FFLTR3EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR3EN) = (v))
mbed_official	146:f64d43ff0c18	4512	#endif
mbed_official	146:f64d43ff0c18	4513	//@}
mbed_official	146:f64d43ff0c18	4514
mbed_official	146:f64d43ff0c18	4515	/*!
mbed_official	146:f64d43ff0c18	4516	* @name Register FTM_FLTCTRL, field FFVAL[11:8] (RW)
mbed_official	146:f64d43ff0c18	4517	*
mbed_official	146:f64d43ff0c18	4518	* Selects the filter value for the fault inputs. The fault filter is disabled
mbed_official	146:f64d43ff0c18	4519	* when the value is zero. Writing to this field has immediate effect and must be
mbed_official	146:f64d43ff0c18	4520	* done only when the fault control or all fault inputs are disabled. Failure to
mbed_official	146:f64d43ff0c18	4521	* do this could result in a missing fault detection.
mbed_official	146:f64d43ff0c18	4522	*/
mbed_official	146:f64d43ff0c18	4523	//@{
mbed_official	146:f64d43ff0c18	4524	#define BP_FTM_FLTCTRL_FFVAL (8U) //!< Bit position for FTM_FLTCTRL_FFVAL.
mbed_official	146:f64d43ff0c18	4525	#define BM_FTM_FLTCTRL_FFVAL (0x00000F00U) //!< Bit mask for FTM_FLTCTRL_FFVAL.
mbed_official	146:f64d43ff0c18	4526	#define BS_FTM_FLTCTRL_FFVAL (4U) //!< Bit field size in bits for FTM_FLTCTRL_FFVAL.
mbed_official	146:f64d43ff0c18	4527
mbed_official	146:f64d43ff0c18	4528	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4529	//! @brief Read current value of the FTM_FLTCTRL_FFVAL field.
mbed_official	146:f64d43ff0c18	4530	#define BR_FTM_FLTCTRL_FFVAL(x) (HW_FTM_FLTCTRL(x).B.FFVAL)
mbed_official	146:f64d43ff0c18	4531	#endif
mbed_official	146:f64d43ff0c18	4532
mbed_official	146:f64d43ff0c18	4533	//! @brief Format value for bitfield FTM_FLTCTRL_FFVAL.
mbed_official	146:f64d43ff0c18	4534	#define BF_FTM_FLTCTRL_FFVAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FFVAL), uint32_t) & BM_FTM_FLTCTRL_FFVAL)
mbed_official	146:f64d43ff0c18	4535
mbed_official	146:f64d43ff0c18	4536	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4537	//! @brief Set the FFVAL field to a new value.
mbed_official	146:f64d43ff0c18	4538	#define BW_FTM_FLTCTRL_FFVAL(x, v) (HW_FTM_FLTCTRL_WR(x, (HW_FTM_FLTCTRL_RD(x) & ~BM_FTM_FLTCTRL_FFVAL) \| BF_FTM_FLTCTRL_FFVAL(v)))
mbed_official	146:f64d43ff0c18	4539	#endif
mbed_official	146:f64d43ff0c18	4540	//@}
mbed_official	146:f64d43ff0c18	4541
mbed_official	146:f64d43ff0c18	4542	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	4543	// HW_FTM_QDCTRL - Quadrature Decoder Control And Status
mbed_official	146:f64d43ff0c18	4544	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	4545
mbed_official	146:f64d43ff0c18	4546	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4547	/*!
mbed_official	146:f64d43ff0c18	4548	* @brief HW_FTM_QDCTRL - Quadrature Decoder Control And Status (RW)
mbed_official	146:f64d43ff0c18	4549	*
mbed_official	146:f64d43ff0c18	4550	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	4551	*
mbed_official	146:f64d43ff0c18	4552	* This register has the control and status bits for the Quadrature Decoder mode.
mbed_official	146:f64d43ff0c18	4553	*/
mbed_official	146:f64d43ff0c18	4554	typedef union _hw_ftm_qdctrl
mbed_official	146:f64d43ff0c18	4555	{
mbed_official	146:f64d43ff0c18	4556	uint32_t U;
mbed_official	146:f64d43ff0c18	4557	struct _hw_ftm_qdctrl_bitfields
mbed_official	146:f64d43ff0c18	4558	{
mbed_official	146:f64d43ff0c18	4559	uint32_t QUADEN : 1; //!< [0] Quadrature Decoder Mode Enable
mbed_official	146:f64d43ff0c18	4560	uint32_t TOFDIR : 1; //!< [1] Timer Overflow Direction In Quadrature
mbed_official	146:f64d43ff0c18	4561	//! Decoder Mode
mbed_official	146:f64d43ff0c18	4562	uint32_t QUADIR : 1; //!< [2] FTM Counter Direction In Quadrature
mbed_official	146:f64d43ff0c18	4563	//! Decoder Mode
mbed_official	146:f64d43ff0c18	4564	uint32_t QUADMODE : 1; //!< [3] Quadrature Decoder Mode
mbed_official	146:f64d43ff0c18	4565	uint32_t PHBPOL : 1; //!< [4] Phase B Input Polarity
mbed_official	146:f64d43ff0c18	4566	uint32_t PHAPOL : 1; //!< [5] Phase A Input Polarity
mbed_official	146:f64d43ff0c18	4567	uint32_t PHBFLTREN : 1; //!< [6] Phase B Input Filter Enable
mbed_official	146:f64d43ff0c18	4568	uint32_t PHAFLTREN : 1; //!< [7] Phase A Input Filter Enable
mbed_official	146:f64d43ff0c18	4569	uint32_t RESERVED0 : 24; //!< [31:8]
mbed_official	146:f64d43ff0c18	4570	} B;
mbed_official	146:f64d43ff0c18	4571	} hw_ftm_qdctrl_t;
mbed_official	146:f64d43ff0c18	4572	#endif
mbed_official	146:f64d43ff0c18	4573
mbed_official	146:f64d43ff0c18	4574	/*!
mbed_official	146:f64d43ff0c18	4575	* @name Constants and macros for entire FTM_QDCTRL register
mbed_official	146:f64d43ff0c18	4576	*/
mbed_official	146:f64d43ff0c18	4577	//@{
mbed_official	146:f64d43ff0c18	4578	#define HW_FTM_QDCTRL_ADDR(x) (REGS_FTM_BASE(x) + 0x80U)
mbed_official	146:f64d43ff0c18	4579
mbed_official	146:f64d43ff0c18	4580	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4581	#define HW_FTM_QDCTRL(x) ((__IO hw_ftm_qdctrl_t ) HW_FTM_QDCTRL_ADDR(x))
mbed_official	146:f64d43ff0c18	4582	#define HW_FTM_QDCTRL_RD(x) (HW_FTM_QDCTRL(x).U)
mbed_official	146:f64d43ff0c18	4583	#define HW_FTM_QDCTRL_WR(x, v) (HW_FTM_QDCTRL(x).U = (v))
mbed_official	146:f64d43ff0c18	4584	#define HW_FTM_QDCTRL_SET(x, v) (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	4585	#define HW_FTM_QDCTRL_CLR(x, v) (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	4586	#define HW_FTM_QDCTRL_TOG(x, v) (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	4587	#endif
mbed_official	146:f64d43ff0c18	4588	//@}
mbed_official	146:f64d43ff0c18	4589
mbed_official	146:f64d43ff0c18	4590	/*
mbed_official	146:f64d43ff0c18	4591	* Constants & macros for individual FTM_QDCTRL bitfields
mbed_official	146:f64d43ff0c18	4592	*/
mbed_official	146:f64d43ff0c18	4593
mbed_official	146:f64d43ff0c18	4594	/*!
mbed_official	146:f64d43ff0c18	4595	* @name Register FTM_QDCTRL, field QUADEN[0] (RW)
mbed_official	146:f64d43ff0c18	4596	*
mbed_official	146:f64d43ff0c18	4597	* Enables the Quadrature Decoder mode. In this mode, the phase A and B input
mbed_official	146:f64d43ff0c18	4598	* signals control the FTM counter direction. The Quadrature Decoder mode has
mbed_official	146:f64d43ff0c18	4599	* precedence over the other modes. See #ModeSel1Table. This field is write protected.
mbed_official	146:f64d43ff0c18	4600	* It can be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	4601	*
mbed_official	146:f64d43ff0c18	4602	* Values:
mbed_official	146:f64d43ff0c18	4603	* - 0 - Quadrature Decoder mode is disabled.
mbed_official	146:f64d43ff0c18	4604	* - 1 - Quadrature Decoder mode is enabled.
mbed_official	146:f64d43ff0c18	4605	*/
mbed_official	146:f64d43ff0c18	4606	//@{
mbed_official	146:f64d43ff0c18	4607	#define BP_FTM_QDCTRL_QUADEN (0U) //!< Bit position for FTM_QDCTRL_QUADEN.
mbed_official	146:f64d43ff0c18	4608	#define BM_FTM_QDCTRL_QUADEN (0x00000001U) //!< Bit mask for FTM_QDCTRL_QUADEN.
mbed_official	146:f64d43ff0c18	4609	#define BS_FTM_QDCTRL_QUADEN (1U) //!< Bit field size in bits for FTM_QDCTRL_QUADEN.
mbed_official	146:f64d43ff0c18	4610
mbed_official	146:f64d43ff0c18	4611	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4612	//! @brief Read current value of the FTM_QDCTRL_QUADEN field.
mbed_official	146:f64d43ff0c18	4613	#define BR_FTM_QDCTRL_QUADEN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADEN))
mbed_official	146:f64d43ff0c18	4614	#endif
mbed_official	146:f64d43ff0c18	4615
mbed_official	146:f64d43ff0c18	4616	//! @brief Format value for bitfield FTM_QDCTRL_QUADEN.
mbed_official	146:f64d43ff0c18	4617	#define BF_FTM_QDCTRL_QUADEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_QDCTRL_QUADEN), uint32_t) & BM_FTM_QDCTRL_QUADEN)
mbed_official	146:f64d43ff0c18	4618
mbed_official	146:f64d43ff0c18	4619	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4620	//! @brief Set the QUADEN field to a new value.
mbed_official	146:f64d43ff0c18	4621	#define BW_FTM_QDCTRL_QUADEN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADEN) = (v))
mbed_official	146:f64d43ff0c18	4622	#endif
mbed_official	146:f64d43ff0c18	4623	//@}
mbed_official	146:f64d43ff0c18	4624
mbed_official	146:f64d43ff0c18	4625	/*!
mbed_official	146:f64d43ff0c18	4626	* @name Register FTM_QDCTRL, field TOFDIR[1] (RO)
mbed_official	146:f64d43ff0c18	4627	*
mbed_official	146:f64d43ff0c18	4628	* Indicates if the TOF bit was set on the top or the bottom of counting.
mbed_official	146:f64d43ff0c18	4629	*
mbed_official	146:f64d43ff0c18	4630	* Values:
mbed_official	146:f64d43ff0c18	4631	* - 0 - TOF bit was set on the bottom of counting. There was an FTM counter
mbed_official	146:f64d43ff0c18	4632	* decrement and FTM counter changes from its minimum value (CNTIN register) to
mbed_official	146:f64d43ff0c18	4633	* its maximum value (MOD register).
mbed_official	146:f64d43ff0c18	4634	* - 1 - TOF bit was set on the top of counting. There was an FTM counter
mbed_official	146:f64d43ff0c18	4635	* increment and FTM counter changes from its maximum value (MOD register) to its
mbed_official	146:f64d43ff0c18	4636	* minimum value (CNTIN register).
mbed_official	146:f64d43ff0c18	4637	*/
mbed_official	146:f64d43ff0c18	4638	//@{
mbed_official	146:f64d43ff0c18	4639	#define BP_FTM_QDCTRL_TOFDIR (1U) //!< Bit position for FTM_QDCTRL_TOFDIR.
mbed_official	146:f64d43ff0c18	4640	#define BM_FTM_QDCTRL_TOFDIR (0x00000002U) //!< Bit mask for FTM_QDCTRL_TOFDIR.
mbed_official	146:f64d43ff0c18	4641	#define BS_FTM_QDCTRL_TOFDIR (1U) //!< Bit field size in bits for FTM_QDCTRL_TOFDIR.
mbed_official	146:f64d43ff0c18	4642
mbed_official	146:f64d43ff0c18	4643	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4644	//! @brief Read current value of the FTM_QDCTRL_TOFDIR field.
mbed_official	146:f64d43ff0c18	4645	#define BR_FTM_QDCTRL_TOFDIR(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_TOFDIR))
mbed_official	146:f64d43ff0c18	4646	#endif
mbed_official	146:f64d43ff0c18	4647	//@}
mbed_official	146:f64d43ff0c18	4648
mbed_official	146:f64d43ff0c18	4649	/*!
mbed_official	146:f64d43ff0c18	4650	* @name Register FTM_QDCTRL, field QUADIR[2] (RO)
mbed_official	146:f64d43ff0c18	4651	*
mbed_official	146:f64d43ff0c18	4652	* Indicates the counting direction.
mbed_official	146:f64d43ff0c18	4653	*
mbed_official	146:f64d43ff0c18	4654	* Values:
mbed_official	146:f64d43ff0c18	4655	* - 0 - Counting direction is decreasing (FTM counter decrement).
mbed_official	146:f64d43ff0c18	4656	* - 1 - Counting direction is increasing (FTM counter increment).
mbed_official	146:f64d43ff0c18	4657	*/
mbed_official	146:f64d43ff0c18	4658	//@{
mbed_official	146:f64d43ff0c18	4659	#define BP_FTM_QDCTRL_QUADIR (2U) //!< Bit position for FTM_QDCTRL_QUADIR.
mbed_official	146:f64d43ff0c18	4660	#define BM_FTM_QDCTRL_QUADIR (0x00000004U) //!< Bit mask for FTM_QDCTRL_QUADIR.
mbed_official	146:f64d43ff0c18	4661	#define BS_FTM_QDCTRL_QUADIR (1U) //!< Bit field size in bits for FTM_QDCTRL_QUADIR.
mbed_official	146:f64d43ff0c18	4662
mbed_official	146:f64d43ff0c18	4663	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4664	//! @brief Read current value of the FTM_QDCTRL_QUADIR field.
mbed_official	146:f64d43ff0c18	4665	#define BR_FTM_QDCTRL_QUADIR(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADIR))
mbed_official	146:f64d43ff0c18	4666	#endif
mbed_official	146:f64d43ff0c18	4667	//@}
mbed_official	146:f64d43ff0c18	4668
mbed_official	146:f64d43ff0c18	4669	/*!
mbed_official	146:f64d43ff0c18	4670	* @name Register FTM_QDCTRL, field QUADMODE[3] (RW)
mbed_official	146:f64d43ff0c18	4671	*
mbed_official	146:f64d43ff0c18	4672	* Selects the encoding mode used in the Quadrature Decoder mode.
mbed_official	146:f64d43ff0c18	4673	*
mbed_official	146:f64d43ff0c18	4674	* Values:
mbed_official	146:f64d43ff0c18	4675	* - 0 - Phase A and phase B encoding mode.
mbed_official	146:f64d43ff0c18	4676	* - 1 - Count and direction encoding mode.
mbed_official	146:f64d43ff0c18	4677	*/
mbed_official	146:f64d43ff0c18	4678	//@{
mbed_official	146:f64d43ff0c18	4679	#define BP_FTM_QDCTRL_QUADMODE (3U) //!< Bit position for FTM_QDCTRL_QUADMODE.
mbed_official	146:f64d43ff0c18	4680	#define BM_FTM_QDCTRL_QUADMODE (0x00000008U) //!< Bit mask for FTM_QDCTRL_QUADMODE.
mbed_official	146:f64d43ff0c18	4681	#define BS_FTM_QDCTRL_QUADMODE (1U) //!< Bit field size in bits for FTM_QDCTRL_QUADMODE.
mbed_official	146:f64d43ff0c18	4682
mbed_official	146:f64d43ff0c18	4683	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4684	//! @brief Read current value of the FTM_QDCTRL_QUADMODE field.
mbed_official	146:f64d43ff0c18	4685	#define BR_FTM_QDCTRL_QUADMODE(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADMODE))
mbed_official	146:f64d43ff0c18	4686	#endif
mbed_official	146:f64d43ff0c18	4687
mbed_official	146:f64d43ff0c18	4688	//! @brief Format value for bitfield FTM_QDCTRL_QUADMODE.
mbed_official	146:f64d43ff0c18	4689	#define BF_FTM_QDCTRL_QUADMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_QDCTRL_QUADMODE), uint32_t) & BM_FTM_QDCTRL_QUADMODE)
mbed_official	146:f64d43ff0c18	4690
mbed_official	146:f64d43ff0c18	4691	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4692	//! @brief Set the QUADMODE field to a new value.
mbed_official	146:f64d43ff0c18	4693	#define BW_FTM_QDCTRL_QUADMODE(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADMODE) = (v))
mbed_official	146:f64d43ff0c18	4694	#endif
mbed_official	146:f64d43ff0c18	4695	//@}
mbed_official	146:f64d43ff0c18	4696
mbed_official	146:f64d43ff0c18	4697	/*!
mbed_official	146:f64d43ff0c18	4698	* @name Register FTM_QDCTRL, field PHBPOL[4] (RW)
mbed_official	146:f64d43ff0c18	4699	*
mbed_official	146:f64d43ff0c18	4700	* Selects the polarity for the quadrature decoder phase B input.
mbed_official	146:f64d43ff0c18	4701	*
mbed_official	146:f64d43ff0c18	4702	* Values:
mbed_official	146:f64d43ff0c18	4703	* - 0 - Normal polarity. Phase B input signal is not inverted before
mbed_official	146:f64d43ff0c18	4704	* identifying the rising and falling edges of this signal.
mbed_official	146:f64d43ff0c18	4705	* - 1 - Inverted polarity. Phase B input signal is inverted before identifying
mbed_official	146:f64d43ff0c18	4706	* the rising and falling edges of this signal.
mbed_official	146:f64d43ff0c18	4707	*/
mbed_official	146:f64d43ff0c18	4708	//@{
mbed_official	146:f64d43ff0c18	4709	#define BP_FTM_QDCTRL_PHBPOL (4U) //!< Bit position for FTM_QDCTRL_PHBPOL.
mbed_official	146:f64d43ff0c18	4710	#define BM_FTM_QDCTRL_PHBPOL (0x00000010U) //!< Bit mask for FTM_QDCTRL_PHBPOL.
mbed_official	146:f64d43ff0c18	4711	#define BS_FTM_QDCTRL_PHBPOL (1U) //!< Bit field size in bits for FTM_QDCTRL_PHBPOL.
mbed_official	146:f64d43ff0c18	4712
mbed_official	146:f64d43ff0c18	4713	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4714	//! @brief Read current value of the FTM_QDCTRL_PHBPOL field.
mbed_official	146:f64d43ff0c18	4715	#define BR_FTM_QDCTRL_PHBPOL(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBPOL))
mbed_official	146:f64d43ff0c18	4716	#endif
mbed_official	146:f64d43ff0c18	4717
mbed_official	146:f64d43ff0c18	4718	//! @brief Format value for bitfield FTM_QDCTRL_PHBPOL.
mbed_official	146:f64d43ff0c18	4719	#define BF_FTM_QDCTRL_PHBPOL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_QDCTRL_PHBPOL), uint32_t) & BM_FTM_QDCTRL_PHBPOL)
mbed_official	146:f64d43ff0c18	4720
mbed_official	146:f64d43ff0c18	4721	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4722	//! @brief Set the PHBPOL field to a new value.
mbed_official	146:f64d43ff0c18	4723	#define BW_FTM_QDCTRL_PHBPOL(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBPOL) = (v))
mbed_official	146:f64d43ff0c18	4724	#endif
mbed_official	146:f64d43ff0c18	4725	//@}
mbed_official	146:f64d43ff0c18	4726
mbed_official	146:f64d43ff0c18	4727	/*!
mbed_official	146:f64d43ff0c18	4728	* @name Register FTM_QDCTRL, field PHAPOL[5] (RW)
mbed_official	146:f64d43ff0c18	4729	*
mbed_official	146:f64d43ff0c18	4730	* Selects the polarity for the quadrature decoder phase A input.
mbed_official	146:f64d43ff0c18	4731	*
mbed_official	146:f64d43ff0c18	4732	* Values:
mbed_official	146:f64d43ff0c18	4733	* - 0 - Normal polarity. Phase A input signal is not inverted before
mbed_official	146:f64d43ff0c18	4734	* identifying the rising and falling edges of this signal.
mbed_official	146:f64d43ff0c18	4735	* - 1 - Inverted polarity. Phase A input signal is inverted before identifying
mbed_official	146:f64d43ff0c18	4736	* the rising and falling edges of this signal.
mbed_official	146:f64d43ff0c18	4737	*/
mbed_official	146:f64d43ff0c18	4738	//@{
mbed_official	146:f64d43ff0c18	4739	#define BP_FTM_QDCTRL_PHAPOL (5U) //!< Bit position for FTM_QDCTRL_PHAPOL.
mbed_official	146:f64d43ff0c18	4740	#define BM_FTM_QDCTRL_PHAPOL (0x00000020U) //!< Bit mask for FTM_QDCTRL_PHAPOL.
mbed_official	146:f64d43ff0c18	4741	#define BS_FTM_QDCTRL_PHAPOL (1U) //!< Bit field size in bits for FTM_QDCTRL_PHAPOL.
mbed_official	146:f64d43ff0c18	4742
mbed_official	146:f64d43ff0c18	4743	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4744	//! @brief Read current value of the FTM_QDCTRL_PHAPOL field.
mbed_official	146:f64d43ff0c18	4745	#define BR_FTM_QDCTRL_PHAPOL(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAPOL))
mbed_official	146:f64d43ff0c18	4746	#endif
mbed_official	146:f64d43ff0c18	4747
mbed_official	146:f64d43ff0c18	4748	//! @brief Format value for bitfield FTM_QDCTRL_PHAPOL.
mbed_official	146:f64d43ff0c18	4749	#define BF_FTM_QDCTRL_PHAPOL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_QDCTRL_PHAPOL), uint32_t) & BM_FTM_QDCTRL_PHAPOL)
mbed_official	146:f64d43ff0c18	4750
mbed_official	146:f64d43ff0c18	4751	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4752	//! @brief Set the PHAPOL field to a new value.
mbed_official	146:f64d43ff0c18	4753	#define BW_FTM_QDCTRL_PHAPOL(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAPOL) = (v))
mbed_official	146:f64d43ff0c18	4754	#endif
mbed_official	146:f64d43ff0c18	4755	//@}
mbed_official	146:f64d43ff0c18	4756
mbed_official	146:f64d43ff0c18	4757	/*!
mbed_official	146:f64d43ff0c18	4758	* @name Register FTM_QDCTRL, field PHBFLTREN[6] (RW)
mbed_official	146:f64d43ff0c18	4759	*
mbed_official	146:f64d43ff0c18	4760	* Enables the filter for the quadrature decoder phase B input. The filter value
mbed_official	146:f64d43ff0c18	4761	* for the phase B input is defined by the CH1FVAL field of FILTER. The phase B
mbed_official	146:f64d43ff0c18	4762	* filter is also disabled when CH1FVAL is zero.
mbed_official	146:f64d43ff0c18	4763	*
mbed_official	146:f64d43ff0c18	4764	* Values:
mbed_official	146:f64d43ff0c18	4765	* - 0 - Phase B input filter is disabled.
mbed_official	146:f64d43ff0c18	4766	* - 1 - Phase B input filter is enabled.
mbed_official	146:f64d43ff0c18	4767	*/
mbed_official	146:f64d43ff0c18	4768	//@{
mbed_official	146:f64d43ff0c18	4769	#define BP_FTM_QDCTRL_PHBFLTREN (6U) //!< Bit position for FTM_QDCTRL_PHBFLTREN.
mbed_official	146:f64d43ff0c18	4770	#define BM_FTM_QDCTRL_PHBFLTREN (0x00000040U) //!< Bit mask for FTM_QDCTRL_PHBFLTREN.
mbed_official	146:f64d43ff0c18	4771	#define BS_FTM_QDCTRL_PHBFLTREN (1U) //!< Bit field size in bits for FTM_QDCTRL_PHBFLTREN.
mbed_official	146:f64d43ff0c18	4772
mbed_official	146:f64d43ff0c18	4773	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4774	//! @brief Read current value of the FTM_QDCTRL_PHBFLTREN field.
mbed_official	146:f64d43ff0c18	4775	#define BR_FTM_QDCTRL_PHBFLTREN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBFLTREN))
mbed_official	146:f64d43ff0c18	4776	#endif
mbed_official	146:f64d43ff0c18	4777
mbed_official	146:f64d43ff0c18	4778	//! @brief Format value for bitfield FTM_QDCTRL_PHBFLTREN.
mbed_official	146:f64d43ff0c18	4779	#define BF_FTM_QDCTRL_PHBFLTREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_QDCTRL_PHBFLTREN), uint32_t) & BM_FTM_QDCTRL_PHBFLTREN)
mbed_official	146:f64d43ff0c18	4780
mbed_official	146:f64d43ff0c18	4781	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4782	//! @brief Set the PHBFLTREN field to a new value.
mbed_official	146:f64d43ff0c18	4783	#define BW_FTM_QDCTRL_PHBFLTREN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBFLTREN) = (v))
mbed_official	146:f64d43ff0c18	4784	#endif
mbed_official	146:f64d43ff0c18	4785	//@}
mbed_official	146:f64d43ff0c18	4786
mbed_official	146:f64d43ff0c18	4787	/*!
mbed_official	146:f64d43ff0c18	4788	* @name Register FTM_QDCTRL, field PHAFLTREN[7] (RW)
mbed_official	146:f64d43ff0c18	4789	*
mbed_official	146:f64d43ff0c18	4790	* Enables the filter for the quadrature decoder phase A input. The filter value
mbed_official	146:f64d43ff0c18	4791	* for the phase A input is defined by the CH0FVAL field of FILTER. The phase A
mbed_official	146:f64d43ff0c18	4792	* filter is also disabled when CH0FVAL is zero.
mbed_official	146:f64d43ff0c18	4793	*
mbed_official	146:f64d43ff0c18	4794	* Values:
mbed_official	146:f64d43ff0c18	4795	* - 0 - Phase A input filter is disabled.
mbed_official	146:f64d43ff0c18	4796	* - 1 - Phase A input filter is enabled.
mbed_official	146:f64d43ff0c18	4797	*/
mbed_official	146:f64d43ff0c18	4798	//@{
mbed_official	146:f64d43ff0c18	4799	#define BP_FTM_QDCTRL_PHAFLTREN (7U) //!< Bit position for FTM_QDCTRL_PHAFLTREN.
mbed_official	146:f64d43ff0c18	4800	#define BM_FTM_QDCTRL_PHAFLTREN (0x00000080U) //!< Bit mask for FTM_QDCTRL_PHAFLTREN.
mbed_official	146:f64d43ff0c18	4801	#define BS_FTM_QDCTRL_PHAFLTREN (1U) //!< Bit field size in bits for FTM_QDCTRL_PHAFLTREN.
mbed_official	146:f64d43ff0c18	4802
mbed_official	146:f64d43ff0c18	4803	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4804	//! @brief Read current value of the FTM_QDCTRL_PHAFLTREN field.
mbed_official	146:f64d43ff0c18	4805	#define BR_FTM_QDCTRL_PHAFLTREN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAFLTREN))
mbed_official	146:f64d43ff0c18	4806	#endif
mbed_official	146:f64d43ff0c18	4807
mbed_official	146:f64d43ff0c18	4808	//! @brief Format value for bitfield FTM_QDCTRL_PHAFLTREN.
mbed_official	146:f64d43ff0c18	4809	#define BF_FTM_QDCTRL_PHAFLTREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_QDCTRL_PHAFLTREN), uint32_t) & BM_FTM_QDCTRL_PHAFLTREN)
mbed_official	146:f64d43ff0c18	4810
mbed_official	146:f64d43ff0c18	4811	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4812	//! @brief Set the PHAFLTREN field to a new value.
mbed_official	146:f64d43ff0c18	4813	#define BW_FTM_QDCTRL_PHAFLTREN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAFLTREN) = (v))
mbed_official	146:f64d43ff0c18	4814	#endif
mbed_official	146:f64d43ff0c18	4815	//@}
mbed_official	146:f64d43ff0c18	4816
mbed_official	146:f64d43ff0c18	4817	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	4818	// HW_FTM_CONF - Configuration
mbed_official	146:f64d43ff0c18	4819	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	4820
mbed_official	146:f64d43ff0c18	4821	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4822	/*!
mbed_official	146:f64d43ff0c18	4823	* @brief HW_FTM_CONF - Configuration (RW)
mbed_official	146:f64d43ff0c18	4824	*
mbed_official	146:f64d43ff0c18	4825	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	4826	*
mbed_official	146:f64d43ff0c18	4827	* This register selects the number of times that the FTM counter overflow
mbed_official	146:f64d43ff0c18	4828	* should occur before the TOF bit to be set, the FTM behavior in BDM modes, the use
mbed_official	146:f64d43ff0c18	4829	* of an external global time base, and the global time base signal generation.
mbed_official	146:f64d43ff0c18	4830	*/
mbed_official	146:f64d43ff0c18	4831	typedef union _hw_ftm_conf
mbed_official	146:f64d43ff0c18	4832	{
mbed_official	146:f64d43ff0c18	4833	uint32_t U;
mbed_official	146:f64d43ff0c18	4834	struct _hw_ftm_conf_bitfields
mbed_official	146:f64d43ff0c18	4835	{
mbed_official	146:f64d43ff0c18	4836	uint32_t NUMTOF : 5; //!< [4:0] TOF Frequency
mbed_official	146:f64d43ff0c18	4837	uint32_t RESERVED0 : 1; //!< [5]
mbed_official	146:f64d43ff0c18	4838	uint32_t BDMMODE : 2; //!< [7:6] BDM Mode
mbed_official	146:f64d43ff0c18	4839	uint32_t RESERVED1 : 1; //!< [8]
mbed_official	146:f64d43ff0c18	4840	uint32_t GTBEEN : 1; //!< [9] Global Time Base Enable
mbed_official	146:f64d43ff0c18	4841	uint32_t GTBEOUT : 1; //!< [10] Global Time Base Output
mbed_official	146:f64d43ff0c18	4842	uint32_t RESERVED2 : 21; //!< [31:11]
mbed_official	146:f64d43ff0c18	4843	} B;
mbed_official	146:f64d43ff0c18	4844	} hw_ftm_conf_t;
mbed_official	146:f64d43ff0c18	4845	#endif
mbed_official	146:f64d43ff0c18	4846
mbed_official	146:f64d43ff0c18	4847	/*!
mbed_official	146:f64d43ff0c18	4848	* @name Constants and macros for entire FTM_CONF register
mbed_official	146:f64d43ff0c18	4849	*/
mbed_official	146:f64d43ff0c18	4850	//@{
mbed_official	146:f64d43ff0c18	4851	#define HW_FTM_CONF_ADDR(x) (REGS_FTM_BASE(x) + 0x84U)
mbed_official	146:f64d43ff0c18	4852
mbed_official	146:f64d43ff0c18	4853	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4854	#define HW_FTM_CONF(x) ((__IO hw_ftm_conf_t ) HW_FTM_CONF_ADDR(x))
mbed_official	146:f64d43ff0c18	4855	#define HW_FTM_CONF_RD(x) (HW_FTM_CONF(x).U)
mbed_official	146:f64d43ff0c18	4856	#define HW_FTM_CONF_WR(x, v) (HW_FTM_CONF(x).U = (v))
mbed_official	146:f64d43ff0c18	4857	#define HW_FTM_CONF_SET(x, v) (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	4858	#define HW_FTM_CONF_CLR(x, v) (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	4859	#define HW_FTM_CONF_TOG(x, v) (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	4860	#endif
mbed_official	146:f64d43ff0c18	4861	//@}
mbed_official	146:f64d43ff0c18	4862
mbed_official	146:f64d43ff0c18	4863	/*
mbed_official	146:f64d43ff0c18	4864	* Constants & macros for individual FTM_CONF bitfields
mbed_official	146:f64d43ff0c18	4865	*/
mbed_official	146:f64d43ff0c18	4866
mbed_official	146:f64d43ff0c18	4867	/*!
mbed_official	146:f64d43ff0c18	4868	* @name Register FTM_CONF, field NUMTOF[4:0] (RW)
mbed_official	146:f64d43ff0c18	4869	*
mbed_official	146:f64d43ff0c18	4870	* Selects the ratio between the number of counter overflows to the number of
mbed_official	146:f64d43ff0c18	4871	* times the TOF bit is set. NUMTOF = 0: The TOF bit is set for each counter
mbed_official	146:f64d43ff0c18	4872	* overflow. NUMTOF = 1: The TOF bit is set for the first counter overflow but not for
mbed_official	146:f64d43ff0c18	4873	* the next overflow. NUMTOF = 2: The TOF bit is set for the first counter
mbed_official	146:f64d43ff0c18	4874	* overflow but not for the next 2 overflows. NUMTOF = 3: The TOF bit is set for the
mbed_official	146:f64d43ff0c18	4875	* first counter overflow but not for the next 3 overflows. This pattern continues
mbed_official	146:f64d43ff0c18	4876	* up to a maximum of 31.
mbed_official	146:f64d43ff0c18	4877	*/
mbed_official	146:f64d43ff0c18	4878	//@{
mbed_official	146:f64d43ff0c18	4879	#define BP_FTM_CONF_NUMTOF (0U) //!< Bit position for FTM_CONF_NUMTOF.
mbed_official	146:f64d43ff0c18	4880	#define BM_FTM_CONF_NUMTOF (0x0000001FU) //!< Bit mask for FTM_CONF_NUMTOF.
mbed_official	146:f64d43ff0c18	4881	#define BS_FTM_CONF_NUMTOF (5U) //!< Bit field size in bits for FTM_CONF_NUMTOF.
mbed_official	146:f64d43ff0c18	4882
mbed_official	146:f64d43ff0c18	4883	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4884	//! @brief Read current value of the FTM_CONF_NUMTOF field.
mbed_official	146:f64d43ff0c18	4885	#define BR_FTM_CONF_NUMTOF(x) (HW_FTM_CONF(x).B.NUMTOF)
mbed_official	146:f64d43ff0c18	4886	#endif
mbed_official	146:f64d43ff0c18	4887
mbed_official	146:f64d43ff0c18	4888	//! @brief Format value for bitfield FTM_CONF_NUMTOF.
mbed_official	146:f64d43ff0c18	4889	#define BF_FTM_CONF_NUMTOF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CONF_NUMTOF), uint32_t) & BM_FTM_CONF_NUMTOF)
mbed_official	146:f64d43ff0c18	4890
mbed_official	146:f64d43ff0c18	4891	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4892	//! @brief Set the NUMTOF field to a new value.
mbed_official	146:f64d43ff0c18	4893	#define BW_FTM_CONF_NUMTOF(x, v) (HW_FTM_CONF_WR(x, (HW_FTM_CONF_RD(x) & ~BM_FTM_CONF_NUMTOF) \| BF_FTM_CONF_NUMTOF(v)))
mbed_official	146:f64d43ff0c18	4894	#endif
mbed_official	146:f64d43ff0c18	4895	//@}
mbed_official	146:f64d43ff0c18	4896
mbed_official	146:f64d43ff0c18	4897	/*!
mbed_official	146:f64d43ff0c18	4898	* @name Register FTM_CONF, field BDMMODE[7:6] (RW)
mbed_official	146:f64d43ff0c18	4899	*
mbed_official	146:f64d43ff0c18	4900	* Selects the FTM behavior in BDM mode. See BDM mode.
mbed_official	146:f64d43ff0c18	4901	*/
mbed_official	146:f64d43ff0c18	4902	//@{
mbed_official	146:f64d43ff0c18	4903	#define BP_FTM_CONF_BDMMODE (6U) //!< Bit position for FTM_CONF_BDMMODE.
mbed_official	146:f64d43ff0c18	4904	#define BM_FTM_CONF_BDMMODE (0x000000C0U) //!< Bit mask for FTM_CONF_BDMMODE.
mbed_official	146:f64d43ff0c18	4905	#define BS_FTM_CONF_BDMMODE (2U) //!< Bit field size in bits for FTM_CONF_BDMMODE.
mbed_official	146:f64d43ff0c18	4906
mbed_official	146:f64d43ff0c18	4907	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4908	//! @brief Read current value of the FTM_CONF_BDMMODE field.
mbed_official	146:f64d43ff0c18	4909	#define BR_FTM_CONF_BDMMODE(x) (HW_FTM_CONF(x).B.BDMMODE)
mbed_official	146:f64d43ff0c18	4910	#endif
mbed_official	146:f64d43ff0c18	4911
mbed_official	146:f64d43ff0c18	4912	//! @brief Format value for bitfield FTM_CONF_BDMMODE.
mbed_official	146:f64d43ff0c18	4913	#define BF_FTM_CONF_BDMMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CONF_BDMMODE), uint32_t) & BM_FTM_CONF_BDMMODE)
mbed_official	146:f64d43ff0c18	4914
mbed_official	146:f64d43ff0c18	4915	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4916	//! @brief Set the BDMMODE field to a new value.
mbed_official	146:f64d43ff0c18	4917	#define BW_FTM_CONF_BDMMODE(x, v) (HW_FTM_CONF_WR(x, (HW_FTM_CONF_RD(x) & ~BM_FTM_CONF_BDMMODE) \| BF_FTM_CONF_BDMMODE(v)))
mbed_official	146:f64d43ff0c18	4918	#endif
mbed_official	146:f64d43ff0c18	4919	//@}
mbed_official	146:f64d43ff0c18	4920
mbed_official	146:f64d43ff0c18	4921	/*!
mbed_official	146:f64d43ff0c18	4922	* @name Register FTM_CONF, field GTBEEN[9] (RW)
mbed_official	146:f64d43ff0c18	4923	*
mbed_official	146:f64d43ff0c18	4924	* Configures the FTM to use an external global time base signal that is
mbed_official	146:f64d43ff0c18	4925	* generated by another FTM.
mbed_official	146:f64d43ff0c18	4926	*
mbed_official	146:f64d43ff0c18	4927	* Values:
mbed_official	146:f64d43ff0c18	4928	* - 0 - Use of an external global time base is disabled.
mbed_official	146:f64d43ff0c18	4929	* - 1 - Use of an external global time base is enabled.
mbed_official	146:f64d43ff0c18	4930	*/
mbed_official	146:f64d43ff0c18	4931	//@{
mbed_official	146:f64d43ff0c18	4932	#define BP_FTM_CONF_GTBEEN (9U) //!< Bit position for FTM_CONF_GTBEEN.
mbed_official	146:f64d43ff0c18	4933	#define BM_FTM_CONF_GTBEEN (0x00000200U) //!< Bit mask for FTM_CONF_GTBEEN.
mbed_official	146:f64d43ff0c18	4934	#define BS_FTM_CONF_GTBEEN (1U) //!< Bit field size in bits for FTM_CONF_GTBEEN.
mbed_official	146:f64d43ff0c18	4935
mbed_official	146:f64d43ff0c18	4936	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4937	//! @brief Read current value of the FTM_CONF_GTBEEN field.
mbed_official	146:f64d43ff0c18	4938	#define BR_FTM_CONF_GTBEEN(x) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEEN))
mbed_official	146:f64d43ff0c18	4939	#endif
mbed_official	146:f64d43ff0c18	4940
mbed_official	146:f64d43ff0c18	4941	//! @brief Format value for bitfield FTM_CONF_GTBEEN.
mbed_official	146:f64d43ff0c18	4942	#define BF_FTM_CONF_GTBEEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CONF_GTBEEN), uint32_t) & BM_FTM_CONF_GTBEEN)
mbed_official	146:f64d43ff0c18	4943
mbed_official	146:f64d43ff0c18	4944	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4945	//! @brief Set the GTBEEN field to a new value.
mbed_official	146:f64d43ff0c18	4946	#define BW_FTM_CONF_GTBEEN(x, v) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEEN) = (v))
mbed_official	146:f64d43ff0c18	4947	#endif
mbed_official	146:f64d43ff0c18	4948	//@}
mbed_official	146:f64d43ff0c18	4949
mbed_official	146:f64d43ff0c18	4950	/*!
mbed_official	146:f64d43ff0c18	4951	* @name Register FTM_CONF, field GTBEOUT[10] (RW)
mbed_official	146:f64d43ff0c18	4952	*
mbed_official	146:f64d43ff0c18	4953	* Enables the global time base signal generation to other FTMs.
mbed_official	146:f64d43ff0c18	4954	*
mbed_official	146:f64d43ff0c18	4955	* Values:
mbed_official	146:f64d43ff0c18	4956	* - 0 - A global time base signal generation is disabled.
mbed_official	146:f64d43ff0c18	4957	* - 1 - A global time base signal generation is enabled.
mbed_official	146:f64d43ff0c18	4958	*/
mbed_official	146:f64d43ff0c18	4959	//@{
mbed_official	146:f64d43ff0c18	4960	#define BP_FTM_CONF_GTBEOUT (10U) //!< Bit position for FTM_CONF_GTBEOUT.
mbed_official	146:f64d43ff0c18	4961	#define BM_FTM_CONF_GTBEOUT (0x00000400U) //!< Bit mask for FTM_CONF_GTBEOUT.
mbed_official	146:f64d43ff0c18	4962	#define BS_FTM_CONF_GTBEOUT (1U) //!< Bit field size in bits for FTM_CONF_GTBEOUT.
mbed_official	146:f64d43ff0c18	4963
mbed_official	146:f64d43ff0c18	4964	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4965	//! @brief Read current value of the FTM_CONF_GTBEOUT field.
mbed_official	146:f64d43ff0c18	4966	#define BR_FTM_CONF_GTBEOUT(x) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEOUT))
mbed_official	146:f64d43ff0c18	4967	#endif
mbed_official	146:f64d43ff0c18	4968
mbed_official	146:f64d43ff0c18	4969	//! @brief Format value for bitfield FTM_CONF_GTBEOUT.
mbed_official	146:f64d43ff0c18	4970	#define BF_FTM_CONF_GTBEOUT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CONF_GTBEOUT), uint32_t) & BM_FTM_CONF_GTBEOUT)
mbed_official	146:f64d43ff0c18	4971
mbed_official	146:f64d43ff0c18	4972	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4973	//! @brief Set the GTBEOUT field to a new value.
mbed_official	146:f64d43ff0c18	4974	#define BW_FTM_CONF_GTBEOUT(x, v) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEOUT) = (v))
mbed_official	146:f64d43ff0c18	4975	#endif
mbed_official	146:f64d43ff0c18	4976	//@}
mbed_official	146:f64d43ff0c18	4977
mbed_official	146:f64d43ff0c18	4978	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	4979	// HW_FTM_FLTPOL - FTM Fault Input Polarity
mbed_official	146:f64d43ff0c18	4980	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	4981
mbed_official	146:f64d43ff0c18	4982	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	4983	/*!
mbed_official	146:f64d43ff0c18	4984	* @brief HW_FTM_FLTPOL - FTM Fault Input Polarity (RW)
mbed_official	146:f64d43ff0c18	4985	*
mbed_official	146:f64d43ff0c18	4986	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	4987	*
mbed_official	146:f64d43ff0c18	4988	* This register defines the fault inputs polarity.
mbed_official	146:f64d43ff0c18	4989	*/
mbed_official	146:f64d43ff0c18	4990	typedef union _hw_ftm_fltpol
mbed_official	146:f64d43ff0c18	4991	{
mbed_official	146:f64d43ff0c18	4992	uint32_t U;
mbed_official	146:f64d43ff0c18	4993	struct _hw_ftm_fltpol_bitfields
mbed_official	146:f64d43ff0c18	4994	{
mbed_official	146:f64d43ff0c18	4995	uint32_t FLT0POL : 1; //!< [0] Fault Input 0 Polarity
mbed_official	146:f64d43ff0c18	4996	uint32_t FLT1POL : 1; //!< [1] Fault Input 1 Polarity
mbed_official	146:f64d43ff0c18	4997	uint32_t FLT2POL : 1; //!< [2] Fault Input 2 Polarity
mbed_official	146:f64d43ff0c18	4998	uint32_t FLT3POL : 1; //!< [3] Fault Input 3 Polarity
mbed_official	146:f64d43ff0c18	4999	uint32_t RESERVED0 : 28; //!< [31:4]
mbed_official	146:f64d43ff0c18	5000	} B;
mbed_official	146:f64d43ff0c18	5001	} hw_ftm_fltpol_t;
mbed_official	146:f64d43ff0c18	5002	#endif
mbed_official	146:f64d43ff0c18	5003
mbed_official	146:f64d43ff0c18	5004	/*!
mbed_official	146:f64d43ff0c18	5005	* @name Constants and macros for entire FTM_FLTPOL register
mbed_official	146:f64d43ff0c18	5006	*/
mbed_official	146:f64d43ff0c18	5007	//@{
mbed_official	146:f64d43ff0c18	5008	#define HW_FTM_FLTPOL_ADDR(x) (REGS_FTM_BASE(x) + 0x88U)
mbed_official	146:f64d43ff0c18	5009
mbed_official	146:f64d43ff0c18	5010	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5011	#define HW_FTM_FLTPOL(x) ((__IO hw_ftm_fltpol_t ) HW_FTM_FLTPOL_ADDR(x))
mbed_official	146:f64d43ff0c18	5012	#define HW_FTM_FLTPOL_RD(x) (HW_FTM_FLTPOL(x).U)
mbed_official	146:f64d43ff0c18	5013	#define HW_FTM_FLTPOL_WR(x, v) (HW_FTM_FLTPOL(x).U = (v))
mbed_official	146:f64d43ff0c18	5014	#define HW_FTM_FLTPOL_SET(x, v) (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	5015	#define HW_FTM_FLTPOL_CLR(x, v) (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	5016	#define HW_FTM_FLTPOL_TOG(x, v) (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	5017	#endif
mbed_official	146:f64d43ff0c18	5018	//@}
mbed_official	146:f64d43ff0c18	5019
mbed_official	146:f64d43ff0c18	5020	/*
mbed_official	146:f64d43ff0c18	5021	* Constants & macros for individual FTM_FLTPOL bitfields
mbed_official	146:f64d43ff0c18	5022	*/
mbed_official	146:f64d43ff0c18	5023
mbed_official	146:f64d43ff0c18	5024	/*!
mbed_official	146:f64d43ff0c18	5025	* @name Register FTM_FLTPOL, field FLT0POL[0] (RW)
mbed_official	146:f64d43ff0c18	5026	*
mbed_official	146:f64d43ff0c18	5027	* Defines the polarity of the fault input. This field is write protected. It
mbed_official	146:f64d43ff0c18	5028	* can be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	5029	*
mbed_official	146:f64d43ff0c18	5030	* Values:
mbed_official	146:f64d43ff0c18	5031	* - 0 - The fault input polarity is active high. A 1 at the fault input
mbed_official	146:f64d43ff0c18	5032	* indicates a fault.
mbed_official	146:f64d43ff0c18	5033	* - 1 - The fault input polarity is active low. A 0 at the fault input
mbed_official	146:f64d43ff0c18	5034	* indicates a fault.
mbed_official	146:f64d43ff0c18	5035	*/
mbed_official	146:f64d43ff0c18	5036	//@{
mbed_official	146:f64d43ff0c18	5037	#define BP_FTM_FLTPOL_FLT0POL (0U) //!< Bit position for FTM_FLTPOL_FLT0POL.
mbed_official	146:f64d43ff0c18	5038	#define BM_FTM_FLTPOL_FLT0POL (0x00000001U) //!< Bit mask for FTM_FLTPOL_FLT0POL.
mbed_official	146:f64d43ff0c18	5039	#define BS_FTM_FLTPOL_FLT0POL (1U) //!< Bit field size in bits for FTM_FLTPOL_FLT0POL.
mbed_official	146:f64d43ff0c18	5040
mbed_official	146:f64d43ff0c18	5041	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5042	//! @brief Read current value of the FTM_FLTPOL_FLT0POL field.
mbed_official	146:f64d43ff0c18	5043	#define BR_FTM_FLTPOL_FLT0POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT0POL))
mbed_official	146:f64d43ff0c18	5044	#endif
mbed_official	146:f64d43ff0c18	5045
mbed_official	146:f64d43ff0c18	5046	//! @brief Format value for bitfield FTM_FLTPOL_FLT0POL.
mbed_official	146:f64d43ff0c18	5047	#define BF_FTM_FLTPOL_FLT0POL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTPOL_FLT0POL), uint32_t) & BM_FTM_FLTPOL_FLT0POL)
mbed_official	146:f64d43ff0c18	5048
mbed_official	146:f64d43ff0c18	5049	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5050	//! @brief Set the FLT0POL field to a new value.
mbed_official	146:f64d43ff0c18	5051	#define BW_FTM_FLTPOL_FLT0POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT0POL) = (v))
mbed_official	146:f64d43ff0c18	5052	#endif
mbed_official	146:f64d43ff0c18	5053	//@}
mbed_official	146:f64d43ff0c18	5054
mbed_official	146:f64d43ff0c18	5055	/*!
mbed_official	146:f64d43ff0c18	5056	* @name Register FTM_FLTPOL, field FLT1POL[1] (RW)
mbed_official	146:f64d43ff0c18	5057	*
mbed_official	146:f64d43ff0c18	5058	* Defines the polarity of the fault input. This field is write protected. It
mbed_official	146:f64d43ff0c18	5059	* can be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	5060	*
mbed_official	146:f64d43ff0c18	5061	* Values:
mbed_official	146:f64d43ff0c18	5062	* - 0 - The fault input polarity is active high. A 1 at the fault input
mbed_official	146:f64d43ff0c18	5063	* indicates a fault.
mbed_official	146:f64d43ff0c18	5064	* - 1 - The fault input polarity is active low. A 0 at the fault input
mbed_official	146:f64d43ff0c18	5065	* indicates a fault.
mbed_official	146:f64d43ff0c18	5066	*/
mbed_official	146:f64d43ff0c18	5067	//@{
mbed_official	146:f64d43ff0c18	5068	#define BP_FTM_FLTPOL_FLT1POL (1U) //!< Bit position for FTM_FLTPOL_FLT1POL.
mbed_official	146:f64d43ff0c18	5069	#define BM_FTM_FLTPOL_FLT1POL (0x00000002U) //!< Bit mask for FTM_FLTPOL_FLT1POL.
mbed_official	146:f64d43ff0c18	5070	#define BS_FTM_FLTPOL_FLT1POL (1U) //!< Bit field size in bits for FTM_FLTPOL_FLT1POL.
mbed_official	146:f64d43ff0c18	5071
mbed_official	146:f64d43ff0c18	5072	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5073	//! @brief Read current value of the FTM_FLTPOL_FLT1POL field.
mbed_official	146:f64d43ff0c18	5074	#define BR_FTM_FLTPOL_FLT1POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT1POL))
mbed_official	146:f64d43ff0c18	5075	#endif
mbed_official	146:f64d43ff0c18	5076
mbed_official	146:f64d43ff0c18	5077	//! @brief Format value for bitfield FTM_FLTPOL_FLT1POL.
mbed_official	146:f64d43ff0c18	5078	#define BF_FTM_FLTPOL_FLT1POL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTPOL_FLT1POL), uint32_t) & BM_FTM_FLTPOL_FLT1POL)
mbed_official	146:f64d43ff0c18	5079
mbed_official	146:f64d43ff0c18	5080	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5081	//! @brief Set the FLT1POL field to a new value.
mbed_official	146:f64d43ff0c18	5082	#define BW_FTM_FLTPOL_FLT1POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT1POL) = (v))
mbed_official	146:f64d43ff0c18	5083	#endif
mbed_official	146:f64d43ff0c18	5084	//@}
mbed_official	146:f64d43ff0c18	5085
mbed_official	146:f64d43ff0c18	5086	/*!
mbed_official	146:f64d43ff0c18	5087	* @name Register FTM_FLTPOL, field FLT2POL[2] (RW)
mbed_official	146:f64d43ff0c18	5088	*
mbed_official	146:f64d43ff0c18	5089	* Defines the polarity of the fault input. This field is write protected. It
mbed_official	146:f64d43ff0c18	5090	* can be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	5091	*
mbed_official	146:f64d43ff0c18	5092	* Values:
mbed_official	146:f64d43ff0c18	5093	* - 0 - The fault input polarity is active high. A 1 at the fault input
mbed_official	146:f64d43ff0c18	5094	* indicates a fault.
mbed_official	146:f64d43ff0c18	5095	* - 1 - The fault input polarity is active low. A 0 at the fault input
mbed_official	146:f64d43ff0c18	5096	* indicates a fault.
mbed_official	146:f64d43ff0c18	5097	*/
mbed_official	146:f64d43ff0c18	5098	//@{
mbed_official	146:f64d43ff0c18	5099	#define BP_FTM_FLTPOL_FLT2POL (2U) //!< Bit position for FTM_FLTPOL_FLT2POL.
mbed_official	146:f64d43ff0c18	5100	#define BM_FTM_FLTPOL_FLT2POL (0x00000004U) //!< Bit mask for FTM_FLTPOL_FLT2POL.
mbed_official	146:f64d43ff0c18	5101	#define BS_FTM_FLTPOL_FLT2POL (1U) //!< Bit field size in bits for FTM_FLTPOL_FLT2POL.
mbed_official	146:f64d43ff0c18	5102
mbed_official	146:f64d43ff0c18	5103	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5104	//! @brief Read current value of the FTM_FLTPOL_FLT2POL field.
mbed_official	146:f64d43ff0c18	5105	#define BR_FTM_FLTPOL_FLT2POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT2POL))
mbed_official	146:f64d43ff0c18	5106	#endif
mbed_official	146:f64d43ff0c18	5107
mbed_official	146:f64d43ff0c18	5108	//! @brief Format value for bitfield FTM_FLTPOL_FLT2POL.
mbed_official	146:f64d43ff0c18	5109	#define BF_FTM_FLTPOL_FLT2POL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTPOL_FLT2POL), uint32_t) & BM_FTM_FLTPOL_FLT2POL)
mbed_official	146:f64d43ff0c18	5110
mbed_official	146:f64d43ff0c18	5111	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5112	//! @brief Set the FLT2POL field to a new value.
mbed_official	146:f64d43ff0c18	5113	#define BW_FTM_FLTPOL_FLT2POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT2POL) = (v))
mbed_official	146:f64d43ff0c18	5114	#endif
mbed_official	146:f64d43ff0c18	5115	//@}
mbed_official	146:f64d43ff0c18	5116
mbed_official	146:f64d43ff0c18	5117	/*!
mbed_official	146:f64d43ff0c18	5118	* @name Register FTM_FLTPOL, field FLT3POL[3] (RW)
mbed_official	146:f64d43ff0c18	5119	*
mbed_official	146:f64d43ff0c18	5120	* Defines the polarity of the fault input. This field is write protected. It
mbed_official	146:f64d43ff0c18	5121	* can be written only when MODE[WPDIS] = 1.
mbed_official	146:f64d43ff0c18	5122	*
mbed_official	146:f64d43ff0c18	5123	* Values:
mbed_official	146:f64d43ff0c18	5124	* - 0 - The fault input polarity is active high. A 1 at the fault input
mbed_official	146:f64d43ff0c18	5125	* indicates a fault.
mbed_official	146:f64d43ff0c18	5126	* - 1 - The fault input polarity is active low. A 0 at the fault input
mbed_official	146:f64d43ff0c18	5127	* indicates a fault.
mbed_official	146:f64d43ff0c18	5128	*/
mbed_official	146:f64d43ff0c18	5129	//@{
mbed_official	146:f64d43ff0c18	5130	#define BP_FTM_FLTPOL_FLT3POL (3U) //!< Bit position for FTM_FLTPOL_FLT3POL.
mbed_official	146:f64d43ff0c18	5131	#define BM_FTM_FLTPOL_FLT3POL (0x00000008U) //!< Bit mask for FTM_FLTPOL_FLT3POL.
mbed_official	146:f64d43ff0c18	5132	#define BS_FTM_FLTPOL_FLT3POL (1U) //!< Bit field size in bits for FTM_FLTPOL_FLT3POL.
mbed_official	146:f64d43ff0c18	5133
mbed_official	146:f64d43ff0c18	5134	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5135	//! @brief Read current value of the FTM_FLTPOL_FLT3POL field.
mbed_official	146:f64d43ff0c18	5136	#define BR_FTM_FLTPOL_FLT3POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT3POL))
mbed_official	146:f64d43ff0c18	5137	#endif
mbed_official	146:f64d43ff0c18	5138
mbed_official	146:f64d43ff0c18	5139	//! @brief Format value for bitfield FTM_FLTPOL_FLT3POL.
mbed_official	146:f64d43ff0c18	5140	#define BF_FTM_FLTPOL_FLT3POL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTPOL_FLT3POL), uint32_t) & BM_FTM_FLTPOL_FLT3POL)
mbed_official	146:f64d43ff0c18	5141
mbed_official	146:f64d43ff0c18	5142	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5143	//! @brief Set the FLT3POL field to a new value.
mbed_official	146:f64d43ff0c18	5144	#define BW_FTM_FLTPOL_FLT3POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT3POL) = (v))
mbed_official	146:f64d43ff0c18	5145	#endif
mbed_official	146:f64d43ff0c18	5146	//@}
mbed_official	146:f64d43ff0c18	5147
mbed_official	146:f64d43ff0c18	5148	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	5149	// HW_FTM_SYNCONF - Synchronization Configuration
mbed_official	146:f64d43ff0c18	5150	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	5151
mbed_official	146:f64d43ff0c18	5152	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5153	/*!
mbed_official	146:f64d43ff0c18	5154	* @brief HW_FTM_SYNCONF - Synchronization Configuration (RW)
mbed_official	146:f64d43ff0c18	5155	*
mbed_official	146:f64d43ff0c18	5156	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	5157	*
mbed_official	146:f64d43ff0c18	5158	* This register selects the PWM synchronization configuration, SWOCTRL, INVCTRL
mbed_official	146:f64d43ff0c18	5159	* and CNTIN registers synchronization, if FTM clears the TRIGj bit, where j =
mbed_official	146:f64d43ff0c18	5160	* 0, 1, 2, when the hardware trigger j is detected.
mbed_official	146:f64d43ff0c18	5161	*/
mbed_official	146:f64d43ff0c18	5162	typedef union _hw_ftm_synconf
mbed_official	146:f64d43ff0c18	5163	{
mbed_official	146:f64d43ff0c18	5164	uint32_t U;
mbed_official	146:f64d43ff0c18	5165	struct _hw_ftm_synconf_bitfields
mbed_official	146:f64d43ff0c18	5166	{
mbed_official	146:f64d43ff0c18	5167	uint32_t HWTRIGMODE : 1; //!< [0] Hardware Trigger Mode
mbed_official	146:f64d43ff0c18	5168	uint32_t RESERVED0 : 1; //!< [1]
mbed_official	146:f64d43ff0c18	5169	uint32_t CNTINC : 1; //!< [2] CNTIN Register Synchronization
mbed_official	146:f64d43ff0c18	5170	uint32_t RESERVED1 : 1; //!< [3]
mbed_official	146:f64d43ff0c18	5171	uint32_t INVC : 1; //!< [4] INVCTRL Register Synchronization
mbed_official	146:f64d43ff0c18	5172	uint32_t SWOC : 1; //!< [5] SWOCTRL Register Synchronization
mbed_official	146:f64d43ff0c18	5173	uint32_t RESERVED2 : 1; //!< [6]
mbed_official	146:f64d43ff0c18	5174	uint32_t SYNCMODE : 1; //!< [7] Synchronization Mode
mbed_official	146:f64d43ff0c18	5175	uint32_t SWRSTCNT : 1; //!< [8]
mbed_official	146:f64d43ff0c18	5176	uint32_t SWWRBUF : 1; //!< [9]
mbed_official	146:f64d43ff0c18	5177	uint32_t SWOM : 1; //!< [10]
mbed_official	146:f64d43ff0c18	5178	uint32_t SWINVC : 1; //!< [11]
mbed_official	146:f64d43ff0c18	5179	uint32_t SWSOC : 1; //!< [12]
mbed_official	146:f64d43ff0c18	5180	uint32_t RESERVED3 : 3; //!< [15:13]
mbed_official	146:f64d43ff0c18	5181	uint32_t HWRSTCNT : 1; //!< [16]
mbed_official	146:f64d43ff0c18	5182	uint32_t HWWRBUF : 1; //!< [17]
mbed_official	146:f64d43ff0c18	5183	uint32_t HWOM : 1; //!< [18]
mbed_official	146:f64d43ff0c18	5184	uint32_t HWINVC : 1; //!< [19]
mbed_official	146:f64d43ff0c18	5185	uint32_t HWSOC : 1; //!< [20]
mbed_official	146:f64d43ff0c18	5186	uint32_t RESERVED4 : 11; //!< [31:21]
mbed_official	146:f64d43ff0c18	5187	} B;
mbed_official	146:f64d43ff0c18	5188	} hw_ftm_synconf_t;
mbed_official	146:f64d43ff0c18	5189	#endif
mbed_official	146:f64d43ff0c18	5190
mbed_official	146:f64d43ff0c18	5191	/*!
mbed_official	146:f64d43ff0c18	5192	* @name Constants and macros for entire FTM_SYNCONF register
mbed_official	146:f64d43ff0c18	5193	*/
mbed_official	146:f64d43ff0c18	5194	//@{
mbed_official	146:f64d43ff0c18	5195	#define HW_FTM_SYNCONF_ADDR(x) (REGS_FTM_BASE(x) + 0x8CU)
mbed_official	146:f64d43ff0c18	5196
mbed_official	146:f64d43ff0c18	5197	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5198	#define HW_FTM_SYNCONF(x) ((__IO hw_ftm_synconf_t ) HW_FTM_SYNCONF_ADDR(x))
mbed_official	146:f64d43ff0c18	5199	#define HW_FTM_SYNCONF_RD(x) (HW_FTM_SYNCONF(x).U)
mbed_official	146:f64d43ff0c18	5200	#define HW_FTM_SYNCONF_WR(x, v) (HW_FTM_SYNCONF(x).U = (v))
mbed_official	146:f64d43ff0c18	5201	#define HW_FTM_SYNCONF_SET(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	5202	#define HW_FTM_SYNCONF_CLR(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	5203	#define HW_FTM_SYNCONF_TOG(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	5204	#endif
mbed_official	146:f64d43ff0c18	5205	//@}
mbed_official	146:f64d43ff0c18	5206
mbed_official	146:f64d43ff0c18	5207	/*
mbed_official	146:f64d43ff0c18	5208	* Constants & macros for individual FTM_SYNCONF bitfields
mbed_official	146:f64d43ff0c18	5209	*/
mbed_official	146:f64d43ff0c18	5210
mbed_official	146:f64d43ff0c18	5211	/*!
mbed_official	146:f64d43ff0c18	5212	* @name Register FTM_SYNCONF, field HWTRIGMODE[0] (RW)
mbed_official	146:f64d43ff0c18	5213	*
mbed_official	146:f64d43ff0c18	5214	* Values:
mbed_official	146:f64d43ff0c18	5215	* - 0 - FTM clears the TRIGj bit when the hardware trigger j is detected, where
mbed_official	146:f64d43ff0c18	5216	* j = 0, 1,2.
mbed_official	146:f64d43ff0c18	5217	* - 1 - FTM does not clear the TRIGj bit when the hardware trigger j is
mbed_official	146:f64d43ff0c18	5218	* detected, where j = 0, 1,2.
mbed_official	146:f64d43ff0c18	5219	*/
mbed_official	146:f64d43ff0c18	5220	//@{
mbed_official	146:f64d43ff0c18	5221	#define BP_FTM_SYNCONF_HWTRIGMODE (0U) //!< Bit position for FTM_SYNCONF_HWTRIGMODE.
mbed_official	146:f64d43ff0c18	5222	#define BM_FTM_SYNCONF_HWTRIGMODE (0x00000001U) //!< Bit mask for FTM_SYNCONF_HWTRIGMODE.
mbed_official	146:f64d43ff0c18	5223	#define BS_FTM_SYNCONF_HWTRIGMODE (1U) //!< Bit field size in bits for FTM_SYNCONF_HWTRIGMODE.
mbed_official	146:f64d43ff0c18	5224
mbed_official	146:f64d43ff0c18	5225	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5226	//! @brief Read current value of the FTM_SYNCONF_HWTRIGMODE field.
mbed_official	146:f64d43ff0c18	5227	#define BR_FTM_SYNCONF_HWTRIGMODE(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWTRIGMODE))
mbed_official	146:f64d43ff0c18	5228	#endif
mbed_official	146:f64d43ff0c18	5229
mbed_official	146:f64d43ff0c18	5230	//! @brief Format value for bitfield FTM_SYNCONF_HWTRIGMODE.
mbed_official	146:f64d43ff0c18	5231	#define BF_FTM_SYNCONF_HWTRIGMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_HWTRIGMODE), uint32_t) & BM_FTM_SYNCONF_HWTRIGMODE)
mbed_official	146:f64d43ff0c18	5232
mbed_official	146:f64d43ff0c18	5233	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5234	//! @brief Set the HWTRIGMODE field to a new value.
mbed_official	146:f64d43ff0c18	5235	#define BW_FTM_SYNCONF_HWTRIGMODE(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWTRIGMODE) = (v))
mbed_official	146:f64d43ff0c18	5236	#endif
mbed_official	146:f64d43ff0c18	5237	//@}
mbed_official	146:f64d43ff0c18	5238
mbed_official	146:f64d43ff0c18	5239	/*!
mbed_official	146:f64d43ff0c18	5240	* @name Register FTM_SYNCONF, field CNTINC[2] (RW)
mbed_official	146:f64d43ff0c18	5241	*
mbed_official	146:f64d43ff0c18	5242	* Values:
mbed_official	146:f64d43ff0c18	5243	* - 0 - CNTIN register is updated with its buffer value at all rising edges of
mbed_official	146:f64d43ff0c18	5244	* system clock.
mbed_official	146:f64d43ff0c18	5245	* - 1 - CNTIN register is updated with its buffer value by the PWM
mbed_official	146:f64d43ff0c18	5246	* synchronization.
mbed_official	146:f64d43ff0c18	5247	*/
mbed_official	146:f64d43ff0c18	5248	//@{
mbed_official	146:f64d43ff0c18	5249	#define BP_FTM_SYNCONF_CNTINC (2U) //!< Bit position for FTM_SYNCONF_CNTINC.
mbed_official	146:f64d43ff0c18	5250	#define BM_FTM_SYNCONF_CNTINC (0x00000004U) //!< Bit mask for FTM_SYNCONF_CNTINC.
mbed_official	146:f64d43ff0c18	5251	#define BS_FTM_SYNCONF_CNTINC (1U) //!< Bit field size in bits for FTM_SYNCONF_CNTINC.
mbed_official	146:f64d43ff0c18	5252
mbed_official	146:f64d43ff0c18	5253	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5254	//! @brief Read current value of the FTM_SYNCONF_CNTINC field.
mbed_official	146:f64d43ff0c18	5255	#define BR_FTM_SYNCONF_CNTINC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_CNTINC))
mbed_official	146:f64d43ff0c18	5256	#endif
mbed_official	146:f64d43ff0c18	5257
mbed_official	146:f64d43ff0c18	5258	//! @brief Format value for bitfield FTM_SYNCONF_CNTINC.
mbed_official	146:f64d43ff0c18	5259	#define BF_FTM_SYNCONF_CNTINC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_CNTINC), uint32_t) & BM_FTM_SYNCONF_CNTINC)
mbed_official	146:f64d43ff0c18	5260
mbed_official	146:f64d43ff0c18	5261	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5262	//! @brief Set the CNTINC field to a new value.
mbed_official	146:f64d43ff0c18	5263	#define BW_FTM_SYNCONF_CNTINC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_CNTINC) = (v))
mbed_official	146:f64d43ff0c18	5264	#endif
mbed_official	146:f64d43ff0c18	5265	//@}
mbed_official	146:f64d43ff0c18	5266
mbed_official	146:f64d43ff0c18	5267	/*!
mbed_official	146:f64d43ff0c18	5268	* @name Register FTM_SYNCONF, field INVC[4] (RW)
mbed_official	146:f64d43ff0c18	5269	*
mbed_official	146:f64d43ff0c18	5270	* Values:
mbed_official	146:f64d43ff0c18	5271	* - 0 - INVCTRL register is updated with its buffer value at all rising edges
mbed_official	146:f64d43ff0c18	5272	* of system clock.
mbed_official	146:f64d43ff0c18	5273	* - 1 - INVCTRL register is updated with its buffer value by the PWM
mbed_official	146:f64d43ff0c18	5274	* synchronization.
mbed_official	146:f64d43ff0c18	5275	*/
mbed_official	146:f64d43ff0c18	5276	//@{
mbed_official	146:f64d43ff0c18	5277	#define BP_FTM_SYNCONF_INVC (4U) //!< Bit position for FTM_SYNCONF_INVC.
mbed_official	146:f64d43ff0c18	5278	#define BM_FTM_SYNCONF_INVC (0x00000010U) //!< Bit mask for FTM_SYNCONF_INVC.
mbed_official	146:f64d43ff0c18	5279	#define BS_FTM_SYNCONF_INVC (1U) //!< Bit field size in bits for FTM_SYNCONF_INVC.
mbed_official	146:f64d43ff0c18	5280
mbed_official	146:f64d43ff0c18	5281	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5282	//! @brief Read current value of the FTM_SYNCONF_INVC field.
mbed_official	146:f64d43ff0c18	5283	#define BR_FTM_SYNCONF_INVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_INVC))
mbed_official	146:f64d43ff0c18	5284	#endif
mbed_official	146:f64d43ff0c18	5285
mbed_official	146:f64d43ff0c18	5286	//! @brief Format value for bitfield FTM_SYNCONF_INVC.
mbed_official	146:f64d43ff0c18	5287	#define BF_FTM_SYNCONF_INVC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_INVC), uint32_t) & BM_FTM_SYNCONF_INVC)
mbed_official	146:f64d43ff0c18	5288
mbed_official	146:f64d43ff0c18	5289	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5290	//! @brief Set the INVC field to a new value.
mbed_official	146:f64d43ff0c18	5291	#define BW_FTM_SYNCONF_INVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_INVC) = (v))
mbed_official	146:f64d43ff0c18	5292	#endif
mbed_official	146:f64d43ff0c18	5293	//@}
mbed_official	146:f64d43ff0c18	5294
mbed_official	146:f64d43ff0c18	5295	/*!
mbed_official	146:f64d43ff0c18	5296	* @name Register FTM_SYNCONF, field SWOC[5] (RW)
mbed_official	146:f64d43ff0c18	5297	*
mbed_official	146:f64d43ff0c18	5298	* Values:
mbed_official	146:f64d43ff0c18	5299	* - 0 - SWOCTRL register is updated with its buffer value at all rising edges
mbed_official	146:f64d43ff0c18	5300	* of system clock.
mbed_official	146:f64d43ff0c18	5301	* - 1 - SWOCTRL register is updated with its buffer value by the PWM
mbed_official	146:f64d43ff0c18	5302	* synchronization.
mbed_official	146:f64d43ff0c18	5303	*/
mbed_official	146:f64d43ff0c18	5304	//@{
mbed_official	146:f64d43ff0c18	5305	#define BP_FTM_SYNCONF_SWOC (5U) //!< Bit position for FTM_SYNCONF_SWOC.
mbed_official	146:f64d43ff0c18	5306	#define BM_FTM_SYNCONF_SWOC (0x00000020U) //!< Bit mask for FTM_SYNCONF_SWOC.
mbed_official	146:f64d43ff0c18	5307	#define BS_FTM_SYNCONF_SWOC (1U) //!< Bit field size in bits for FTM_SYNCONF_SWOC.
mbed_official	146:f64d43ff0c18	5308
mbed_official	146:f64d43ff0c18	5309	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5310	//! @brief Read current value of the FTM_SYNCONF_SWOC field.
mbed_official	146:f64d43ff0c18	5311	#define BR_FTM_SYNCONF_SWOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOC))
mbed_official	146:f64d43ff0c18	5312	#endif
mbed_official	146:f64d43ff0c18	5313
mbed_official	146:f64d43ff0c18	5314	//! @brief Format value for bitfield FTM_SYNCONF_SWOC.
mbed_official	146:f64d43ff0c18	5315	#define BF_FTM_SYNCONF_SWOC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_SWOC), uint32_t) & BM_FTM_SYNCONF_SWOC)
mbed_official	146:f64d43ff0c18	5316
mbed_official	146:f64d43ff0c18	5317	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5318	//! @brief Set the SWOC field to a new value.
mbed_official	146:f64d43ff0c18	5319	#define BW_FTM_SYNCONF_SWOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOC) = (v))
mbed_official	146:f64d43ff0c18	5320	#endif
mbed_official	146:f64d43ff0c18	5321	//@}
mbed_official	146:f64d43ff0c18	5322
mbed_official	146:f64d43ff0c18	5323	/*!
mbed_official	146:f64d43ff0c18	5324	* @name Register FTM_SYNCONF, field SYNCMODE[7] (RW)
mbed_official	146:f64d43ff0c18	5325	*
mbed_official	146:f64d43ff0c18	5326	* Selects the PWM Synchronization mode.
mbed_official	146:f64d43ff0c18	5327	*
mbed_official	146:f64d43ff0c18	5328	* Values:
mbed_official	146:f64d43ff0c18	5329	* - 0 - Legacy PWM synchronization is selected.
mbed_official	146:f64d43ff0c18	5330	* - 1 - Enhanced PWM synchronization is selected.
mbed_official	146:f64d43ff0c18	5331	*/
mbed_official	146:f64d43ff0c18	5332	//@{
mbed_official	146:f64d43ff0c18	5333	#define BP_FTM_SYNCONF_SYNCMODE (7U) //!< Bit position for FTM_SYNCONF_SYNCMODE.
mbed_official	146:f64d43ff0c18	5334	#define BM_FTM_SYNCONF_SYNCMODE (0x00000080U) //!< Bit mask for FTM_SYNCONF_SYNCMODE.
mbed_official	146:f64d43ff0c18	5335	#define BS_FTM_SYNCONF_SYNCMODE (1U) //!< Bit field size in bits for FTM_SYNCONF_SYNCMODE.
mbed_official	146:f64d43ff0c18	5336
mbed_official	146:f64d43ff0c18	5337	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5338	//! @brief Read current value of the FTM_SYNCONF_SYNCMODE field.
mbed_official	146:f64d43ff0c18	5339	#define BR_FTM_SYNCONF_SYNCMODE(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SYNCMODE))
mbed_official	146:f64d43ff0c18	5340	#endif
mbed_official	146:f64d43ff0c18	5341
mbed_official	146:f64d43ff0c18	5342	//! @brief Format value for bitfield FTM_SYNCONF_SYNCMODE.
mbed_official	146:f64d43ff0c18	5343	#define BF_FTM_SYNCONF_SYNCMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_SYNCMODE), uint32_t) & BM_FTM_SYNCONF_SYNCMODE)
mbed_official	146:f64d43ff0c18	5344
mbed_official	146:f64d43ff0c18	5345	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5346	//! @brief Set the SYNCMODE field to a new value.
mbed_official	146:f64d43ff0c18	5347	#define BW_FTM_SYNCONF_SYNCMODE(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SYNCMODE) = (v))
mbed_official	146:f64d43ff0c18	5348	#endif
mbed_official	146:f64d43ff0c18	5349	//@}
mbed_official	146:f64d43ff0c18	5350
mbed_official	146:f64d43ff0c18	5351	/*!
mbed_official	146:f64d43ff0c18	5352	* @name Register FTM_SYNCONF, field SWRSTCNT[8] (RW)
mbed_official	146:f64d43ff0c18	5353	*
mbed_official	146:f64d43ff0c18	5354	* FTM counter synchronization is activated by the software trigger.
mbed_official	146:f64d43ff0c18	5355	*
mbed_official	146:f64d43ff0c18	5356	* Values:
mbed_official	146:f64d43ff0c18	5357	* - 0 - The software trigger does not activate the FTM counter synchronization.
mbed_official	146:f64d43ff0c18	5358	* - 1 - The software trigger activates the FTM counter synchronization.
mbed_official	146:f64d43ff0c18	5359	*/
mbed_official	146:f64d43ff0c18	5360	//@{
mbed_official	146:f64d43ff0c18	5361	#define BP_FTM_SYNCONF_SWRSTCNT (8U) //!< Bit position for FTM_SYNCONF_SWRSTCNT.
mbed_official	146:f64d43ff0c18	5362	#define BM_FTM_SYNCONF_SWRSTCNT (0x00000100U) //!< Bit mask for FTM_SYNCONF_SWRSTCNT.
mbed_official	146:f64d43ff0c18	5363	#define BS_FTM_SYNCONF_SWRSTCNT (1U) //!< Bit field size in bits for FTM_SYNCONF_SWRSTCNT.
mbed_official	146:f64d43ff0c18	5364
mbed_official	146:f64d43ff0c18	5365	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5366	//! @brief Read current value of the FTM_SYNCONF_SWRSTCNT field.
mbed_official	146:f64d43ff0c18	5367	#define BR_FTM_SYNCONF_SWRSTCNT(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWRSTCNT))
mbed_official	146:f64d43ff0c18	5368	#endif
mbed_official	146:f64d43ff0c18	5369
mbed_official	146:f64d43ff0c18	5370	//! @brief Format value for bitfield FTM_SYNCONF_SWRSTCNT.
mbed_official	146:f64d43ff0c18	5371	#define BF_FTM_SYNCONF_SWRSTCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_SWRSTCNT), uint32_t) & BM_FTM_SYNCONF_SWRSTCNT)
mbed_official	146:f64d43ff0c18	5372
mbed_official	146:f64d43ff0c18	5373	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5374	//! @brief Set the SWRSTCNT field to a new value.
mbed_official	146:f64d43ff0c18	5375	#define BW_FTM_SYNCONF_SWRSTCNT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWRSTCNT) = (v))
mbed_official	146:f64d43ff0c18	5376	#endif
mbed_official	146:f64d43ff0c18	5377	//@}
mbed_official	146:f64d43ff0c18	5378
mbed_official	146:f64d43ff0c18	5379	/*!
mbed_official	146:f64d43ff0c18	5380	* @name Register FTM_SYNCONF, field SWWRBUF[9] (RW)
mbed_official	146:f64d43ff0c18	5381	*
mbed_official	146:f64d43ff0c18	5382	* MOD, CNTIN, and CV registers synchronization is activated by the software
mbed_official	146:f64d43ff0c18	5383	* trigger.
mbed_official	146:f64d43ff0c18	5384	*
mbed_official	146:f64d43ff0c18	5385	* Values:
mbed_official	146:f64d43ff0c18	5386	* - 0 - The software trigger does not activate MOD, CNTIN, and CV registers
mbed_official	146:f64d43ff0c18	5387	* synchronization.
mbed_official	146:f64d43ff0c18	5388	* - 1 - The software trigger activates MOD, CNTIN, and CV registers
mbed_official	146:f64d43ff0c18	5389	* synchronization.
mbed_official	146:f64d43ff0c18	5390	*/
mbed_official	146:f64d43ff0c18	5391	//@{
mbed_official	146:f64d43ff0c18	5392	#define BP_FTM_SYNCONF_SWWRBUF (9U) //!< Bit position for FTM_SYNCONF_SWWRBUF.
mbed_official	146:f64d43ff0c18	5393	#define BM_FTM_SYNCONF_SWWRBUF (0x00000200U) //!< Bit mask for FTM_SYNCONF_SWWRBUF.
mbed_official	146:f64d43ff0c18	5394	#define BS_FTM_SYNCONF_SWWRBUF (1U) //!< Bit field size in bits for FTM_SYNCONF_SWWRBUF.
mbed_official	146:f64d43ff0c18	5395
mbed_official	146:f64d43ff0c18	5396	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5397	//! @brief Read current value of the FTM_SYNCONF_SWWRBUF field.
mbed_official	146:f64d43ff0c18	5398	#define BR_FTM_SYNCONF_SWWRBUF(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWWRBUF))
mbed_official	146:f64d43ff0c18	5399	#endif
mbed_official	146:f64d43ff0c18	5400
mbed_official	146:f64d43ff0c18	5401	//! @brief Format value for bitfield FTM_SYNCONF_SWWRBUF.
mbed_official	146:f64d43ff0c18	5402	#define BF_FTM_SYNCONF_SWWRBUF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_SWWRBUF), uint32_t) & BM_FTM_SYNCONF_SWWRBUF)
mbed_official	146:f64d43ff0c18	5403
mbed_official	146:f64d43ff0c18	5404	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5405	//! @brief Set the SWWRBUF field to a new value.
mbed_official	146:f64d43ff0c18	5406	#define BW_FTM_SYNCONF_SWWRBUF(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWWRBUF) = (v))
mbed_official	146:f64d43ff0c18	5407	#endif
mbed_official	146:f64d43ff0c18	5408	//@}
mbed_official	146:f64d43ff0c18	5409
mbed_official	146:f64d43ff0c18	5410	/*!
mbed_official	146:f64d43ff0c18	5411	* @name Register FTM_SYNCONF, field SWOM[10] (RW)
mbed_official	146:f64d43ff0c18	5412	*
mbed_official	146:f64d43ff0c18	5413	* Output mask synchronization is activated by the software trigger.
mbed_official	146:f64d43ff0c18	5414	*
mbed_official	146:f64d43ff0c18	5415	* Values:
mbed_official	146:f64d43ff0c18	5416	* - 0 - The software trigger does not activate the OUTMASK register
mbed_official	146:f64d43ff0c18	5417	* synchronization.
mbed_official	146:f64d43ff0c18	5418	* - 1 - The software trigger activates the OUTMASK register synchronization.
mbed_official	146:f64d43ff0c18	5419	*/
mbed_official	146:f64d43ff0c18	5420	//@{
mbed_official	146:f64d43ff0c18	5421	#define BP_FTM_SYNCONF_SWOM (10U) //!< Bit position for FTM_SYNCONF_SWOM.
mbed_official	146:f64d43ff0c18	5422	#define BM_FTM_SYNCONF_SWOM (0x00000400U) //!< Bit mask for FTM_SYNCONF_SWOM.
mbed_official	146:f64d43ff0c18	5423	#define BS_FTM_SYNCONF_SWOM (1U) //!< Bit field size in bits for FTM_SYNCONF_SWOM.
mbed_official	146:f64d43ff0c18	5424
mbed_official	146:f64d43ff0c18	5425	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5426	//! @brief Read current value of the FTM_SYNCONF_SWOM field.
mbed_official	146:f64d43ff0c18	5427	#define BR_FTM_SYNCONF_SWOM(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOM))
mbed_official	146:f64d43ff0c18	5428	#endif
mbed_official	146:f64d43ff0c18	5429
mbed_official	146:f64d43ff0c18	5430	//! @brief Format value for bitfield FTM_SYNCONF_SWOM.
mbed_official	146:f64d43ff0c18	5431	#define BF_FTM_SYNCONF_SWOM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_SWOM), uint32_t) & BM_FTM_SYNCONF_SWOM)
mbed_official	146:f64d43ff0c18	5432
mbed_official	146:f64d43ff0c18	5433	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5434	//! @brief Set the SWOM field to a new value.
mbed_official	146:f64d43ff0c18	5435	#define BW_FTM_SYNCONF_SWOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOM) = (v))
mbed_official	146:f64d43ff0c18	5436	#endif
mbed_official	146:f64d43ff0c18	5437	//@}
mbed_official	146:f64d43ff0c18	5438
mbed_official	146:f64d43ff0c18	5439	/*!
mbed_official	146:f64d43ff0c18	5440	* @name Register FTM_SYNCONF, field SWINVC[11] (RW)
mbed_official	146:f64d43ff0c18	5441	*
mbed_official	146:f64d43ff0c18	5442	* Inverting control synchronization is activated by the software trigger.
mbed_official	146:f64d43ff0c18	5443	*
mbed_official	146:f64d43ff0c18	5444	* Values:
mbed_official	146:f64d43ff0c18	5445	* - 0 - The software trigger does not activate the INVCTRL register
mbed_official	146:f64d43ff0c18	5446	* synchronization.
mbed_official	146:f64d43ff0c18	5447	* - 1 - The software trigger activates the INVCTRL register synchronization.
mbed_official	146:f64d43ff0c18	5448	*/
mbed_official	146:f64d43ff0c18	5449	//@{
mbed_official	146:f64d43ff0c18	5450	#define BP_FTM_SYNCONF_SWINVC (11U) //!< Bit position for FTM_SYNCONF_SWINVC.
mbed_official	146:f64d43ff0c18	5451	#define BM_FTM_SYNCONF_SWINVC (0x00000800U) //!< Bit mask for FTM_SYNCONF_SWINVC.
mbed_official	146:f64d43ff0c18	5452	#define BS_FTM_SYNCONF_SWINVC (1U) //!< Bit field size in bits for FTM_SYNCONF_SWINVC.
mbed_official	146:f64d43ff0c18	5453
mbed_official	146:f64d43ff0c18	5454	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5455	//! @brief Read current value of the FTM_SYNCONF_SWINVC field.
mbed_official	146:f64d43ff0c18	5456	#define BR_FTM_SYNCONF_SWINVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWINVC))
mbed_official	146:f64d43ff0c18	5457	#endif
mbed_official	146:f64d43ff0c18	5458
mbed_official	146:f64d43ff0c18	5459	//! @brief Format value for bitfield FTM_SYNCONF_SWINVC.
mbed_official	146:f64d43ff0c18	5460	#define BF_FTM_SYNCONF_SWINVC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_SWINVC), uint32_t) & BM_FTM_SYNCONF_SWINVC)
mbed_official	146:f64d43ff0c18	5461
mbed_official	146:f64d43ff0c18	5462	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5463	//! @brief Set the SWINVC field to a new value.
mbed_official	146:f64d43ff0c18	5464	#define BW_FTM_SYNCONF_SWINVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWINVC) = (v))
mbed_official	146:f64d43ff0c18	5465	#endif
mbed_official	146:f64d43ff0c18	5466	//@}
mbed_official	146:f64d43ff0c18	5467
mbed_official	146:f64d43ff0c18	5468	/*!
mbed_official	146:f64d43ff0c18	5469	* @name Register FTM_SYNCONF, field SWSOC[12] (RW)
mbed_official	146:f64d43ff0c18	5470	*
mbed_official	146:f64d43ff0c18	5471	* Software output control synchronization is activated by the software trigger.
mbed_official	146:f64d43ff0c18	5472	*
mbed_official	146:f64d43ff0c18	5473	* Values:
mbed_official	146:f64d43ff0c18	5474	* - 0 - The software trigger does not activate the SWOCTRL register
mbed_official	146:f64d43ff0c18	5475	* synchronization.
mbed_official	146:f64d43ff0c18	5476	* - 1 - The software trigger activates the SWOCTRL register synchronization.
mbed_official	146:f64d43ff0c18	5477	*/
mbed_official	146:f64d43ff0c18	5478	//@{
mbed_official	146:f64d43ff0c18	5479	#define BP_FTM_SYNCONF_SWSOC (12U) //!< Bit position for FTM_SYNCONF_SWSOC.
mbed_official	146:f64d43ff0c18	5480	#define BM_FTM_SYNCONF_SWSOC (0x00001000U) //!< Bit mask for FTM_SYNCONF_SWSOC.
mbed_official	146:f64d43ff0c18	5481	#define BS_FTM_SYNCONF_SWSOC (1U) //!< Bit field size in bits for FTM_SYNCONF_SWSOC.
mbed_official	146:f64d43ff0c18	5482
mbed_official	146:f64d43ff0c18	5483	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5484	//! @brief Read current value of the FTM_SYNCONF_SWSOC field.
mbed_official	146:f64d43ff0c18	5485	#define BR_FTM_SYNCONF_SWSOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWSOC))
mbed_official	146:f64d43ff0c18	5486	#endif
mbed_official	146:f64d43ff0c18	5487
mbed_official	146:f64d43ff0c18	5488	//! @brief Format value for bitfield FTM_SYNCONF_SWSOC.
mbed_official	146:f64d43ff0c18	5489	#define BF_FTM_SYNCONF_SWSOC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_SWSOC), uint32_t) & BM_FTM_SYNCONF_SWSOC)
mbed_official	146:f64d43ff0c18	5490
mbed_official	146:f64d43ff0c18	5491	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5492	//! @brief Set the SWSOC field to a new value.
mbed_official	146:f64d43ff0c18	5493	#define BW_FTM_SYNCONF_SWSOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWSOC) = (v))
mbed_official	146:f64d43ff0c18	5494	#endif
mbed_official	146:f64d43ff0c18	5495	//@}
mbed_official	146:f64d43ff0c18	5496
mbed_official	146:f64d43ff0c18	5497	/*!
mbed_official	146:f64d43ff0c18	5498	* @name Register FTM_SYNCONF, field HWRSTCNT[16] (RW)
mbed_official	146:f64d43ff0c18	5499	*
mbed_official	146:f64d43ff0c18	5500	* FTM counter synchronization is activated by a hardware trigger.
mbed_official	146:f64d43ff0c18	5501	*
mbed_official	146:f64d43ff0c18	5502	* Values:
mbed_official	146:f64d43ff0c18	5503	* - 0 - A hardware trigger does not activate the FTM counter synchronization.
mbed_official	146:f64d43ff0c18	5504	* - 1 - A hardware trigger activates the FTM counter synchronization.
mbed_official	146:f64d43ff0c18	5505	*/
mbed_official	146:f64d43ff0c18	5506	//@{
mbed_official	146:f64d43ff0c18	5507	#define BP_FTM_SYNCONF_HWRSTCNT (16U) //!< Bit position for FTM_SYNCONF_HWRSTCNT.
mbed_official	146:f64d43ff0c18	5508	#define BM_FTM_SYNCONF_HWRSTCNT (0x00010000U) //!< Bit mask for FTM_SYNCONF_HWRSTCNT.
mbed_official	146:f64d43ff0c18	5509	#define BS_FTM_SYNCONF_HWRSTCNT (1U) //!< Bit field size in bits for FTM_SYNCONF_HWRSTCNT.
mbed_official	146:f64d43ff0c18	5510
mbed_official	146:f64d43ff0c18	5511	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5512	//! @brief Read current value of the FTM_SYNCONF_HWRSTCNT field.
mbed_official	146:f64d43ff0c18	5513	#define BR_FTM_SYNCONF_HWRSTCNT(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWRSTCNT))
mbed_official	146:f64d43ff0c18	5514	#endif
mbed_official	146:f64d43ff0c18	5515
mbed_official	146:f64d43ff0c18	5516	//! @brief Format value for bitfield FTM_SYNCONF_HWRSTCNT.
mbed_official	146:f64d43ff0c18	5517	#define BF_FTM_SYNCONF_HWRSTCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_HWRSTCNT), uint32_t) & BM_FTM_SYNCONF_HWRSTCNT)
mbed_official	146:f64d43ff0c18	5518
mbed_official	146:f64d43ff0c18	5519	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5520	//! @brief Set the HWRSTCNT field to a new value.
mbed_official	146:f64d43ff0c18	5521	#define BW_FTM_SYNCONF_HWRSTCNT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWRSTCNT) = (v))
mbed_official	146:f64d43ff0c18	5522	#endif
mbed_official	146:f64d43ff0c18	5523	//@}
mbed_official	146:f64d43ff0c18	5524
mbed_official	146:f64d43ff0c18	5525	/*!
mbed_official	146:f64d43ff0c18	5526	* @name Register FTM_SYNCONF, field HWWRBUF[17] (RW)
mbed_official	146:f64d43ff0c18	5527	*
mbed_official	146:f64d43ff0c18	5528	* MOD, CNTIN, and CV registers synchronization is activated by a hardware
mbed_official	146:f64d43ff0c18	5529	* trigger.
mbed_official	146:f64d43ff0c18	5530	*
mbed_official	146:f64d43ff0c18	5531	* Values:
mbed_official	146:f64d43ff0c18	5532	* - 0 - A hardware trigger does not activate MOD, CNTIN, and CV registers
mbed_official	146:f64d43ff0c18	5533	* synchronization.
mbed_official	146:f64d43ff0c18	5534	* - 1 - A hardware trigger activates MOD, CNTIN, and CV registers
mbed_official	146:f64d43ff0c18	5535	* synchronization.
mbed_official	146:f64d43ff0c18	5536	*/
mbed_official	146:f64d43ff0c18	5537	//@{
mbed_official	146:f64d43ff0c18	5538	#define BP_FTM_SYNCONF_HWWRBUF (17U) //!< Bit position for FTM_SYNCONF_HWWRBUF.
mbed_official	146:f64d43ff0c18	5539	#define BM_FTM_SYNCONF_HWWRBUF (0x00020000U) //!< Bit mask for FTM_SYNCONF_HWWRBUF.
mbed_official	146:f64d43ff0c18	5540	#define BS_FTM_SYNCONF_HWWRBUF (1U) //!< Bit field size in bits for FTM_SYNCONF_HWWRBUF.
mbed_official	146:f64d43ff0c18	5541
mbed_official	146:f64d43ff0c18	5542	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5543	//! @brief Read current value of the FTM_SYNCONF_HWWRBUF field.
mbed_official	146:f64d43ff0c18	5544	#define BR_FTM_SYNCONF_HWWRBUF(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWWRBUF))
mbed_official	146:f64d43ff0c18	5545	#endif
mbed_official	146:f64d43ff0c18	5546
mbed_official	146:f64d43ff0c18	5547	//! @brief Format value for bitfield FTM_SYNCONF_HWWRBUF.
mbed_official	146:f64d43ff0c18	5548	#define BF_FTM_SYNCONF_HWWRBUF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_HWWRBUF), uint32_t) & BM_FTM_SYNCONF_HWWRBUF)
mbed_official	146:f64d43ff0c18	5549
mbed_official	146:f64d43ff0c18	5550	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5551	//! @brief Set the HWWRBUF field to a new value.
mbed_official	146:f64d43ff0c18	5552	#define BW_FTM_SYNCONF_HWWRBUF(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWWRBUF) = (v))
mbed_official	146:f64d43ff0c18	5553	#endif
mbed_official	146:f64d43ff0c18	5554	//@}
mbed_official	146:f64d43ff0c18	5555
mbed_official	146:f64d43ff0c18	5556	/*!
mbed_official	146:f64d43ff0c18	5557	* @name Register FTM_SYNCONF, field HWOM[18] (RW)
mbed_official	146:f64d43ff0c18	5558	*
mbed_official	146:f64d43ff0c18	5559	* Output mask synchronization is activated by a hardware trigger.
mbed_official	146:f64d43ff0c18	5560	*
mbed_official	146:f64d43ff0c18	5561	* Values:
mbed_official	146:f64d43ff0c18	5562	* - 0 - A hardware trigger does not activate the OUTMASK register
mbed_official	146:f64d43ff0c18	5563	* synchronization.
mbed_official	146:f64d43ff0c18	5564	* - 1 - A hardware trigger activates the OUTMASK register synchronization.
mbed_official	146:f64d43ff0c18	5565	*/
mbed_official	146:f64d43ff0c18	5566	//@{
mbed_official	146:f64d43ff0c18	5567	#define BP_FTM_SYNCONF_HWOM (18U) //!< Bit position for FTM_SYNCONF_HWOM.
mbed_official	146:f64d43ff0c18	5568	#define BM_FTM_SYNCONF_HWOM (0x00040000U) //!< Bit mask for FTM_SYNCONF_HWOM.
mbed_official	146:f64d43ff0c18	5569	#define BS_FTM_SYNCONF_HWOM (1U) //!< Bit field size in bits for FTM_SYNCONF_HWOM.
mbed_official	146:f64d43ff0c18	5570
mbed_official	146:f64d43ff0c18	5571	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5572	//! @brief Read current value of the FTM_SYNCONF_HWOM field.
mbed_official	146:f64d43ff0c18	5573	#define BR_FTM_SYNCONF_HWOM(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWOM))
mbed_official	146:f64d43ff0c18	5574	#endif
mbed_official	146:f64d43ff0c18	5575
mbed_official	146:f64d43ff0c18	5576	//! @brief Format value for bitfield FTM_SYNCONF_HWOM.
mbed_official	146:f64d43ff0c18	5577	#define BF_FTM_SYNCONF_HWOM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_HWOM), uint32_t) & BM_FTM_SYNCONF_HWOM)
mbed_official	146:f64d43ff0c18	5578
mbed_official	146:f64d43ff0c18	5579	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5580	//! @brief Set the HWOM field to a new value.
mbed_official	146:f64d43ff0c18	5581	#define BW_FTM_SYNCONF_HWOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWOM) = (v))
mbed_official	146:f64d43ff0c18	5582	#endif
mbed_official	146:f64d43ff0c18	5583	//@}
mbed_official	146:f64d43ff0c18	5584
mbed_official	146:f64d43ff0c18	5585	/*!
mbed_official	146:f64d43ff0c18	5586	* @name Register FTM_SYNCONF, field HWINVC[19] (RW)
mbed_official	146:f64d43ff0c18	5587	*
mbed_official	146:f64d43ff0c18	5588	* Inverting control synchronization is activated by a hardware trigger.
mbed_official	146:f64d43ff0c18	5589	*
mbed_official	146:f64d43ff0c18	5590	* Values:
mbed_official	146:f64d43ff0c18	5591	* - 0 - A hardware trigger does not activate the INVCTRL register
mbed_official	146:f64d43ff0c18	5592	* synchronization.
mbed_official	146:f64d43ff0c18	5593	* - 1 - A hardware trigger activates the INVCTRL register synchronization.
mbed_official	146:f64d43ff0c18	5594	*/
mbed_official	146:f64d43ff0c18	5595	//@{
mbed_official	146:f64d43ff0c18	5596	#define BP_FTM_SYNCONF_HWINVC (19U) //!< Bit position for FTM_SYNCONF_HWINVC.
mbed_official	146:f64d43ff0c18	5597	#define BM_FTM_SYNCONF_HWINVC (0x00080000U) //!< Bit mask for FTM_SYNCONF_HWINVC.
mbed_official	146:f64d43ff0c18	5598	#define BS_FTM_SYNCONF_HWINVC (1U) //!< Bit field size in bits for FTM_SYNCONF_HWINVC.
mbed_official	146:f64d43ff0c18	5599
mbed_official	146:f64d43ff0c18	5600	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5601	//! @brief Read current value of the FTM_SYNCONF_HWINVC field.
mbed_official	146:f64d43ff0c18	5602	#define BR_FTM_SYNCONF_HWINVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWINVC))
mbed_official	146:f64d43ff0c18	5603	#endif
mbed_official	146:f64d43ff0c18	5604
mbed_official	146:f64d43ff0c18	5605	//! @brief Format value for bitfield FTM_SYNCONF_HWINVC.
mbed_official	146:f64d43ff0c18	5606	#define BF_FTM_SYNCONF_HWINVC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_HWINVC), uint32_t) & BM_FTM_SYNCONF_HWINVC)
mbed_official	146:f64d43ff0c18	5607
mbed_official	146:f64d43ff0c18	5608	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5609	//! @brief Set the HWINVC field to a new value.
mbed_official	146:f64d43ff0c18	5610	#define BW_FTM_SYNCONF_HWINVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWINVC) = (v))
mbed_official	146:f64d43ff0c18	5611	#endif
mbed_official	146:f64d43ff0c18	5612	//@}
mbed_official	146:f64d43ff0c18	5613
mbed_official	146:f64d43ff0c18	5614	/*!
mbed_official	146:f64d43ff0c18	5615	* @name Register FTM_SYNCONF, field HWSOC[20] (RW)
mbed_official	146:f64d43ff0c18	5616	*
mbed_official	146:f64d43ff0c18	5617	* Software output control synchronization is activated by a hardware trigger.
mbed_official	146:f64d43ff0c18	5618	*
mbed_official	146:f64d43ff0c18	5619	* Values:
mbed_official	146:f64d43ff0c18	5620	* - 0 - A hardware trigger does not activate the SWOCTRL register
mbed_official	146:f64d43ff0c18	5621	* synchronization.
mbed_official	146:f64d43ff0c18	5622	* - 1 - A hardware trigger activates the SWOCTRL register synchronization.
mbed_official	146:f64d43ff0c18	5623	*/
mbed_official	146:f64d43ff0c18	5624	//@{
mbed_official	146:f64d43ff0c18	5625	#define BP_FTM_SYNCONF_HWSOC (20U) //!< Bit position for FTM_SYNCONF_HWSOC.
mbed_official	146:f64d43ff0c18	5626	#define BM_FTM_SYNCONF_HWSOC (0x00100000U) //!< Bit mask for FTM_SYNCONF_HWSOC.
mbed_official	146:f64d43ff0c18	5627	#define BS_FTM_SYNCONF_HWSOC (1U) //!< Bit field size in bits for FTM_SYNCONF_HWSOC.
mbed_official	146:f64d43ff0c18	5628
mbed_official	146:f64d43ff0c18	5629	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5630	//! @brief Read current value of the FTM_SYNCONF_HWSOC field.
mbed_official	146:f64d43ff0c18	5631	#define BR_FTM_SYNCONF_HWSOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWSOC))
mbed_official	146:f64d43ff0c18	5632	#endif
mbed_official	146:f64d43ff0c18	5633
mbed_official	146:f64d43ff0c18	5634	//! @brief Format value for bitfield FTM_SYNCONF_HWSOC.
mbed_official	146:f64d43ff0c18	5635	#define BF_FTM_SYNCONF_HWSOC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_HWSOC), uint32_t) & BM_FTM_SYNCONF_HWSOC)
mbed_official	146:f64d43ff0c18	5636
mbed_official	146:f64d43ff0c18	5637	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5638	//! @brief Set the HWSOC field to a new value.
mbed_official	146:f64d43ff0c18	5639	#define BW_FTM_SYNCONF_HWSOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWSOC) = (v))
mbed_official	146:f64d43ff0c18	5640	#endif
mbed_official	146:f64d43ff0c18	5641	//@}
mbed_official	146:f64d43ff0c18	5642
mbed_official	146:f64d43ff0c18	5643	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	5644	// HW_FTM_INVCTRL - FTM Inverting Control
mbed_official	146:f64d43ff0c18	5645	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	5646
mbed_official	146:f64d43ff0c18	5647	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5648	/*!
mbed_official	146:f64d43ff0c18	5649	* @brief HW_FTM_INVCTRL - FTM Inverting Control (RW)
mbed_official	146:f64d43ff0c18	5650	*
mbed_official	146:f64d43ff0c18	5651	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	5652	*
mbed_official	146:f64d43ff0c18	5653	* This register controls when the channel (n) output becomes the channel (n+1)
mbed_official	146:f64d43ff0c18	5654	* output, and channel (n+1) output becomes the channel (n) output. Each INVmEN
mbed_official	146:f64d43ff0c18	5655	* bit enables the inverting operation for the corresponding pair channels m. This
mbed_official	146:f64d43ff0c18	5656	* register has a write buffer. The INVmEN bit is updated by the INVCTRL
mbed_official	146:f64d43ff0c18	5657	* register synchronization.
mbed_official	146:f64d43ff0c18	5658	*/
mbed_official	146:f64d43ff0c18	5659	typedef union _hw_ftm_invctrl
mbed_official	146:f64d43ff0c18	5660	{
mbed_official	146:f64d43ff0c18	5661	uint32_t U;
mbed_official	146:f64d43ff0c18	5662	struct _hw_ftm_invctrl_bitfields
mbed_official	146:f64d43ff0c18	5663	{
mbed_official	146:f64d43ff0c18	5664	uint32_t INV0EN : 1; //!< [0] Pair Channels 0 Inverting Enable
mbed_official	146:f64d43ff0c18	5665	uint32_t INV1EN : 1; //!< [1] Pair Channels 1 Inverting Enable
mbed_official	146:f64d43ff0c18	5666	uint32_t INV2EN : 1; //!< [2] Pair Channels 2 Inverting Enable
mbed_official	146:f64d43ff0c18	5667	uint32_t INV3EN : 1; //!< [3] Pair Channels 3 Inverting Enable
mbed_official	146:f64d43ff0c18	5668	uint32_t RESERVED0 : 28; //!< [31:4]
mbed_official	146:f64d43ff0c18	5669	} B;
mbed_official	146:f64d43ff0c18	5670	} hw_ftm_invctrl_t;
mbed_official	146:f64d43ff0c18	5671	#endif
mbed_official	146:f64d43ff0c18	5672
mbed_official	146:f64d43ff0c18	5673	/*!
mbed_official	146:f64d43ff0c18	5674	* @name Constants and macros for entire FTM_INVCTRL register
mbed_official	146:f64d43ff0c18	5675	*/
mbed_official	146:f64d43ff0c18	5676	//@{
mbed_official	146:f64d43ff0c18	5677	#define HW_FTM_INVCTRL_ADDR(x) (REGS_FTM_BASE(x) + 0x90U)
mbed_official	146:f64d43ff0c18	5678
mbed_official	146:f64d43ff0c18	5679	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5680	#define HW_FTM_INVCTRL(x) ((__IO hw_ftm_invctrl_t ) HW_FTM_INVCTRL_ADDR(x))
mbed_official	146:f64d43ff0c18	5681	#define HW_FTM_INVCTRL_RD(x) (HW_FTM_INVCTRL(x).U)
mbed_official	146:f64d43ff0c18	5682	#define HW_FTM_INVCTRL_WR(x, v) (HW_FTM_INVCTRL(x).U = (v))
mbed_official	146:f64d43ff0c18	5683	#define HW_FTM_INVCTRL_SET(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	5684	#define HW_FTM_INVCTRL_CLR(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	5685	#define HW_FTM_INVCTRL_TOG(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	5686	#endif
mbed_official	146:f64d43ff0c18	5687	//@}
mbed_official	146:f64d43ff0c18	5688
mbed_official	146:f64d43ff0c18	5689	/*
mbed_official	146:f64d43ff0c18	5690	* Constants & macros for individual FTM_INVCTRL bitfields
mbed_official	146:f64d43ff0c18	5691	*/
mbed_official	146:f64d43ff0c18	5692
mbed_official	146:f64d43ff0c18	5693	/*!
mbed_official	146:f64d43ff0c18	5694	* @name Register FTM_INVCTRL, field INV0EN[0] (RW)
mbed_official	146:f64d43ff0c18	5695	*
mbed_official	146:f64d43ff0c18	5696	* Values:
mbed_official	146:f64d43ff0c18	5697	* - 0 - Inverting is disabled.
mbed_official	146:f64d43ff0c18	5698	* - 1 - Inverting is enabled.
mbed_official	146:f64d43ff0c18	5699	*/
mbed_official	146:f64d43ff0c18	5700	//@{
mbed_official	146:f64d43ff0c18	5701	#define BP_FTM_INVCTRL_INV0EN (0U) //!< Bit position for FTM_INVCTRL_INV0EN.
mbed_official	146:f64d43ff0c18	5702	#define BM_FTM_INVCTRL_INV0EN (0x00000001U) //!< Bit mask for FTM_INVCTRL_INV0EN.
mbed_official	146:f64d43ff0c18	5703	#define BS_FTM_INVCTRL_INV0EN (1U) //!< Bit field size in bits for FTM_INVCTRL_INV0EN.
mbed_official	146:f64d43ff0c18	5704
mbed_official	146:f64d43ff0c18	5705	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5706	//! @brief Read current value of the FTM_INVCTRL_INV0EN field.
mbed_official	146:f64d43ff0c18	5707	#define BR_FTM_INVCTRL_INV0EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV0EN))
mbed_official	146:f64d43ff0c18	5708	#endif
mbed_official	146:f64d43ff0c18	5709
mbed_official	146:f64d43ff0c18	5710	//! @brief Format value for bitfield FTM_INVCTRL_INV0EN.
mbed_official	146:f64d43ff0c18	5711	#define BF_FTM_INVCTRL_INV0EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_INVCTRL_INV0EN), uint32_t) & BM_FTM_INVCTRL_INV0EN)
mbed_official	146:f64d43ff0c18	5712
mbed_official	146:f64d43ff0c18	5713	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5714	//! @brief Set the INV0EN field to a new value.
mbed_official	146:f64d43ff0c18	5715	#define BW_FTM_INVCTRL_INV0EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV0EN) = (v))
mbed_official	146:f64d43ff0c18	5716	#endif
mbed_official	146:f64d43ff0c18	5717	//@}
mbed_official	146:f64d43ff0c18	5718
mbed_official	146:f64d43ff0c18	5719	/*!
mbed_official	146:f64d43ff0c18	5720	* @name Register FTM_INVCTRL, field INV1EN[1] (RW)
mbed_official	146:f64d43ff0c18	5721	*
mbed_official	146:f64d43ff0c18	5722	* Values:
mbed_official	146:f64d43ff0c18	5723	* - 0 - Inverting is disabled.
mbed_official	146:f64d43ff0c18	5724	* - 1 - Inverting is enabled.
mbed_official	146:f64d43ff0c18	5725	*/
mbed_official	146:f64d43ff0c18	5726	//@{
mbed_official	146:f64d43ff0c18	5727	#define BP_FTM_INVCTRL_INV1EN (1U) //!< Bit position for FTM_INVCTRL_INV1EN.
mbed_official	146:f64d43ff0c18	5728	#define BM_FTM_INVCTRL_INV1EN (0x00000002U) //!< Bit mask for FTM_INVCTRL_INV1EN.
mbed_official	146:f64d43ff0c18	5729	#define BS_FTM_INVCTRL_INV1EN (1U) //!< Bit field size in bits for FTM_INVCTRL_INV1EN.
mbed_official	146:f64d43ff0c18	5730
mbed_official	146:f64d43ff0c18	5731	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5732	//! @brief Read current value of the FTM_INVCTRL_INV1EN field.
mbed_official	146:f64d43ff0c18	5733	#define BR_FTM_INVCTRL_INV1EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV1EN))
mbed_official	146:f64d43ff0c18	5734	#endif
mbed_official	146:f64d43ff0c18	5735
mbed_official	146:f64d43ff0c18	5736	//! @brief Format value for bitfield FTM_INVCTRL_INV1EN.
mbed_official	146:f64d43ff0c18	5737	#define BF_FTM_INVCTRL_INV1EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_INVCTRL_INV1EN), uint32_t) & BM_FTM_INVCTRL_INV1EN)
mbed_official	146:f64d43ff0c18	5738
mbed_official	146:f64d43ff0c18	5739	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5740	//! @brief Set the INV1EN field to a new value.
mbed_official	146:f64d43ff0c18	5741	#define BW_FTM_INVCTRL_INV1EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV1EN) = (v))
mbed_official	146:f64d43ff0c18	5742	#endif
mbed_official	146:f64d43ff0c18	5743	//@}
mbed_official	146:f64d43ff0c18	5744
mbed_official	146:f64d43ff0c18	5745	/*!
mbed_official	146:f64d43ff0c18	5746	* @name Register FTM_INVCTRL, field INV2EN[2] (RW)
mbed_official	146:f64d43ff0c18	5747	*
mbed_official	146:f64d43ff0c18	5748	* Values:
mbed_official	146:f64d43ff0c18	5749	* - 0 - Inverting is disabled.
mbed_official	146:f64d43ff0c18	5750	* - 1 - Inverting is enabled.
mbed_official	146:f64d43ff0c18	5751	*/
mbed_official	146:f64d43ff0c18	5752	//@{
mbed_official	146:f64d43ff0c18	5753	#define BP_FTM_INVCTRL_INV2EN (2U) //!< Bit position for FTM_INVCTRL_INV2EN.
mbed_official	146:f64d43ff0c18	5754	#define BM_FTM_INVCTRL_INV2EN (0x00000004U) //!< Bit mask for FTM_INVCTRL_INV2EN.
mbed_official	146:f64d43ff0c18	5755	#define BS_FTM_INVCTRL_INV2EN (1U) //!< Bit field size in bits for FTM_INVCTRL_INV2EN.
mbed_official	146:f64d43ff0c18	5756
mbed_official	146:f64d43ff0c18	5757	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5758	//! @brief Read current value of the FTM_INVCTRL_INV2EN field.
mbed_official	146:f64d43ff0c18	5759	#define BR_FTM_INVCTRL_INV2EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV2EN))
mbed_official	146:f64d43ff0c18	5760	#endif
mbed_official	146:f64d43ff0c18	5761
mbed_official	146:f64d43ff0c18	5762	//! @brief Format value for bitfield FTM_INVCTRL_INV2EN.
mbed_official	146:f64d43ff0c18	5763	#define BF_FTM_INVCTRL_INV2EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_INVCTRL_INV2EN), uint32_t) & BM_FTM_INVCTRL_INV2EN)
mbed_official	146:f64d43ff0c18	5764
mbed_official	146:f64d43ff0c18	5765	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5766	//! @brief Set the INV2EN field to a new value.
mbed_official	146:f64d43ff0c18	5767	#define BW_FTM_INVCTRL_INV2EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV2EN) = (v))
mbed_official	146:f64d43ff0c18	5768	#endif
mbed_official	146:f64d43ff0c18	5769	//@}
mbed_official	146:f64d43ff0c18	5770
mbed_official	146:f64d43ff0c18	5771	/*!
mbed_official	146:f64d43ff0c18	5772	* @name Register FTM_INVCTRL, field INV3EN[3] (RW)
mbed_official	146:f64d43ff0c18	5773	*
mbed_official	146:f64d43ff0c18	5774	* Values:
mbed_official	146:f64d43ff0c18	5775	* - 0 - Inverting is disabled.
mbed_official	146:f64d43ff0c18	5776	* - 1 - Inverting is enabled.
mbed_official	146:f64d43ff0c18	5777	*/
mbed_official	146:f64d43ff0c18	5778	//@{
mbed_official	146:f64d43ff0c18	5779	#define BP_FTM_INVCTRL_INV3EN (3U) //!< Bit position for FTM_INVCTRL_INV3EN.
mbed_official	146:f64d43ff0c18	5780	#define BM_FTM_INVCTRL_INV3EN (0x00000008U) //!< Bit mask for FTM_INVCTRL_INV3EN.
mbed_official	146:f64d43ff0c18	5781	#define BS_FTM_INVCTRL_INV3EN (1U) //!< Bit field size in bits for FTM_INVCTRL_INV3EN.
mbed_official	146:f64d43ff0c18	5782
mbed_official	146:f64d43ff0c18	5783	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5784	//! @brief Read current value of the FTM_INVCTRL_INV3EN field.
mbed_official	146:f64d43ff0c18	5785	#define BR_FTM_INVCTRL_INV3EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV3EN))
mbed_official	146:f64d43ff0c18	5786	#endif
mbed_official	146:f64d43ff0c18	5787
mbed_official	146:f64d43ff0c18	5788	//! @brief Format value for bitfield FTM_INVCTRL_INV3EN.
mbed_official	146:f64d43ff0c18	5789	#define BF_FTM_INVCTRL_INV3EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_INVCTRL_INV3EN), uint32_t) & BM_FTM_INVCTRL_INV3EN)
mbed_official	146:f64d43ff0c18	5790
mbed_official	146:f64d43ff0c18	5791	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5792	//! @brief Set the INV3EN field to a new value.
mbed_official	146:f64d43ff0c18	5793	#define BW_FTM_INVCTRL_INV3EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV3EN) = (v))
mbed_official	146:f64d43ff0c18	5794	#endif
mbed_official	146:f64d43ff0c18	5795	//@}
mbed_official	146:f64d43ff0c18	5796
mbed_official	146:f64d43ff0c18	5797	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	5798	// HW_FTM_SWOCTRL - FTM Software Output Control
mbed_official	146:f64d43ff0c18	5799	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	5800
mbed_official	146:f64d43ff0c18	5801	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5802	/*!
mbed_official	146:f64d43ff0c18	5803	* @brief HW_FTM_SWOCTRL - FTM Software Output Control (RW)
mbed_official	146:f64d43ff0c18	5804	*
mbed_official	146:f64d43ff0c18	5805	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	5806	*
mbed_official	146:f64d43ff0c18	5807	* This register enables software control of channel (n) output and defines the
mbed_official	146:f64d43ff0c18	5808	* value forced to the channel (n) output: The CHnOC bits enable the control of
mbed_official	146:f64d43ff0c18	5809	* the corresponding channel (n) output by software. The CHnOCV bits select the
mbed_official	146:f64d43ff0c18	5810	* value that is forced at the corresponding channel (n) output. This register has
mbed_official	146:f64d43ff0c18	5811	* a write buffer. The fields are updated by the SWOCTRL register synchronization.
mbed_official	146:f64d43ff0c18	5812	*/
mbed_official	146:f64d43ff0c18	5813	typedef union _hw_ftm_swoctrl
mbed_official	146:f64d43ff0c18	5814	{
mbed_official	146:f64d43ff0c18	5815	uint32_t U;
mbed_official	146:f64d43ff0c18	5816	struct _hw_ftm_swoctrl_bitfields
mbed_official	146:f64d43ff0c18	5817	{
mbed_official	146:f64d43ff0c18	5818	uint32_t CH0OC : 1; //!< [0] Channel 0 Software Output Control Enable
mbed_official	146:f64d43ff0c18	5819	uint32_t CH1OC : 1; //!< [1] Channel 1 Software Output Control Enable
mbed_official	146:f64d43ff0c18	5820	uint32_t CH2OC : 1; //!< [2] Channel 2 Software Output Control Enable
mbed_official	146:f64d43ff0c18	5821	uint32_t CH3OC : 1; //!< [3] Channel 3 Software Output Control Enable
mbed_official	146:f64d43ff0c18	5822	uint32_t CH4OC : 1; //!< [4] Channel 4 Software Output Control Enable
mbed_official	146:f64d43ff0c18	5823	uint32_t CH5OC : 1; //!< [5] Channel 5 Software Output Control Enable
mbed_official	146:f64d43ff0c18	5824	uint32_t CH6OC : 1; //!< [6] Channel 6 Software Output Control Enable
mbed_official	146:f64d43ff0c18	5825	uint32_t CH7OC : 1; //!< [7] Channel 7 Software Output Control Enable
mbed_official	146:f64d43ff0c18	5826	uint32_t CH0OCV : 1; //!< [8] Channel 0 Software Output Control Value
mbed_official	146:f64d43ff0c18	5827	uint32_t CH1OCV : 1; //!< [9] Channel 1 Software Output Control Value
mbed_official	146:f64d43ff0c18	5828	uint32_t CH2OCV : 1; //!< [10] Channel 2 Software Output Control Value
mbed_official	146:f64d43ff0c18	5829	uint32_t CH3OCV : 1; //!< [11] Channel 3 Software Output Control Value
mbed_official	146:f64d43ff0c18	5830	uint32_t CH4OCV : 1; //!< [12] Channel 4 Software Output Control Value
mbed_official	146:f64d43ff0c18	5831	uint32_t CH5OCV : 1; //!< [13] Channel 5 Software Output Control Value
mbed_official	146:f64d43ff0c18	5832	uint32_t CH6OCV : 1; //!< [14] Channel 6 Software Output Control Value
mbed_official	146:f64d43ff0c18	5833	uint32_t CH7OCV : 1; //!< [15] Channel 7 Software Output Control Value
mbed_official	146:f64d43ff0c18	5834	uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official	146:f64d43ff0c18	5835	} B;
mbed_official	146:f64d43ff0c18	5836	} hw_ftm_swoctrl_t;
mbed_official	146:f64d43ff0c18	5837	#endif
mbed_official	146:f64d43ff0c18	5838
mbed_official	146:f64d43ff0c18	5839	/*!
mbed_official	146:f64d43ff0c18	5840	* @name Constants and macros for entire FTM_SWOCTRL register
mbed_official	146:f64d43ff0c18	5841	*/
mbed_official	146:f64d43ff0c18	5842	//@{
mbed_official	146:f64d43ff0c18	5843	#define HW_FTM_SWOCTRL_ADDR(x) (REGS_FTM_BASE(x) + 0x94U)
mbed_official	146:f64d43ff0c18	5844
mbed_official	146:f64d43ff0c18	5845	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5846	#define HW_FTM_SWOCTRL(x) ((__IO hw_ftm_swoctrl_t ) HW_FTM_SWOCTRL_ADDR(x))
mbed_official	146:f64d43ff0c18	5847	#define HW_FTM_SWOCTRL_RD(x) (HW_FTM_SWOCTRL(x).U)
mbed_official	146:f64d43ff0c18	5848	#define HW_FTM_SWOCTRL_WR(x, v) (HW_FTM_SWOCTRL(x).U = (v))
mbed_official	146:f64d43ff0c18	5849	#define HW_FTM_SWOCTRL_SET(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	5850	#define HW_FTM_SWOCTRL_CLR(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	5851	#define HW_FTM_SWOCTRL_TOG(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	5852	#endif
mbed_official	146:f64d43ff0c18	5853	//@}
mbed_official	146:f64d43ff0c18	5854
mbed_official	146:f64d43ff0c18	5855	/*
mbed_official	146:f64d43ff0c18	5856	* Constants & macros for individual FTM_SWOCTRL bitfields
mbed_official	146:f64d43ff0c18	5857	*/
mbed_official	146:f64d43ff0c18	5858
mbed_official	146:f64d43ff0c18	5859	/*!
mbed_official	146:f64d43ff0c18	5860	* @name Register FTM_SWOCTRL, field CH0OC[0] (RW)
mbed_official	146:f64d43ff0c18	5861	*
mbed_official	146:f64d43ff0c18	5862	* Values:
mbed_official	146:f64d43ff0c18	5863	* - 0 - The channel output is not affected by software output control.
mbed_official	146:f64d43ff0c18	5864	* - 1 - The channel output is affected by software output control.
mbed_official	146:f64d43ff0c18	5865	*/
mbed_official	146:f64d43ff0c18	5866	//@{
mbed_official	146:f64d43ff0c18	5867	#define BP_FTM_SWOCTRL_CH0OC (0U) //!< Bit position for FTM_SWOCTRL_CH0OC.
mbed_official	146:f64d43ff0c18	5868	#define BM_FTM_SWOCTRL_CH0OC (0x00000001U) //!< Bit mask for FTM_SWOCTRL_CH0OC.
mbed_official	146:f64d43ff0c18	5869	#define BS_FTM_SWOCTRL_CH0OC (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH0OC.
mbed_official	146:f64d43ff0c18	5870
mbed_official	146:f64d43ff0c18	5871	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5872	//! @brief Read current value of the FTM_SWOCTRL_CH0OC field.
mbed_official	146:f64d43ff0c18	5873	#define BR_FTM_SWOCTRL_CH0OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OC))
mbed_official	146:f64d43ff0c18	5874	#endif
mbed_official	146:f64d43ff0c18	5875
mbed_official	146:f64d43ff0c18	5876	//! @brief Format value for bitfield FTM_SWOCTRL_CH0OC.
mbed_official	146:f64d43ff0c18	5877	#define BF_FTM_SWOCTRL_CH0OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH0OC), uint32_t) & BM_FTM_SWOCTRL_CH0OC)
mbed_official	146:f64d43ff0c18	5878
mbed_official	146:f64d43ff0c18	5879	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5880	//! @brief Set the CH0OC field to a new value.
mbed_official	146:f64d43ff0c18	5881	#define BW_FTM_SWOCTRL_CH0OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OC) = (v))
mbed_official	146:f64d43ff0c18	5882	#endif
mbed_official	146:f64d43ff0c18	5883	//@}
mbed_official	146:f64d43ff0c18	5884
mbed_official	146:f64d43ff0c18	5885	/*!
mbed_official	146:f64d43ff0c18	5886	* @name Register FTM_SWOCTRL, field CH1OC[1] (RW)
mbed_official	146:f64d43ff0c18	5887	*
mbed_official	146:f64d43ff0c18	5888	* Values:
mbed_official	146:f64d43ff0c18	5889	* - 0 - The channel output is not affected by software output control.
mbed_official	146:f64d43ff0c18	5890	* - 1 - The channel output is affected by software output control.
mbed_official	146:f64d43ff0c18	5891	*/
mbed_official	146:f64d43ff0c18	5892	//@{
mbed_official	146:f64d43ff0c18	5893	#define BP_FTM_SWOCTRL_CH1OC (1U) //!< Bit position for FTM_SWOCTRL_CH1OC.
mbed_official	146:f64d43ff0c18	5894	#define BM_FTM_SWOCTRL_CH1OC (0x00000002U) //!< Bit mask for FTM_SWOCTRL_CH1OC.
mbed_official	146:f64d43ff0c18	5895	#define BS_FTM_SWOCTRL_CH1OC (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH1OC.
mbed_official	146:f64d43ff0c18	5896
mbed_official	146:f64d43ff0c18	5897	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5898	//! @brief Read current value of the FTM_SWOCTRL_CH1OC field.
mbed_official	146:f64d43ff0c18	5899	#define BR_FTM_SWOCTRL_CH1OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OC))
mbed_official	146:f64d43ff0c18	5900	#endif
mbed_official	146:f64d43ff0c18	5901
mbed_official	146:f64d43ff0c18	5902	//! @brief Format value for bitfield FTM_SWOCTRL_CH1OC.
mbed_official	146:f64d43ff0c18	5903	#define BF_FTM_SWOCTRL_CH1OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH1OC), uint32_t) & BM_FTM_SWOCTRL_CH1OC)
mbed_official	146:f64d43ff0c18	5904
mbed_official	146:f64d43ff0c18	5905	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5906	//! @brief Set the CH1OC field to a new value.
mbed_official	146:f64d43ff0c18	5907	#define BW_FTM_SWOCTRL_CH1OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OC) = (v))
mbed_official	146:f64d43ff0c18	5908	#endif
mbed_official	146:f64d43ff0c18	5909	//@}
mbed_official	146:f64d43ff0c18	5910
mbed_official	146:f64d43ff0c18	5911	/*!
mbed_official	146:f64d43ff0c18	5912	* @name Register FTM_SWOCTRL, field CH2OC[2] (RW)
mbed_official	146:f64d43ff0c18	5913	*
mbed_official	146:f64d43ff0c18	5914	* Values:
mbed_official	146:f64d43ff0c18	5915	* - 0 - The channel output is not affected by software output control.
mbed_official	146:f64d43ff0c18	5916	* - 1 - The channel output is affected by software output control.
mbed_official	146:f64d43ff0c18	5917	*/
mbed_official	146:f64d43ff0c18	5918	//@{
mbed_official	146:f64d43ff0c18	5919	#define BP_FTM_SWOCTRL_CH2OC (2U) //!< Bit position for FTM_SWOCTRL_CH2OC.
mbed_official	146:f64d43ff0c18	5920	#define BM_FTM_SWOCTRL_CH2OC (0x00000004U) //!< Bit mask for FTM_SWOCTRL_CH2OC.
mbed_official	146:f64d43ff0c18	5921	#define BS_FTM_SWOCTRL_CH2OC (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH2OC.
mbed_official	146:f64d43ff0c18	5922
mbed_official	146:f64d43ff0c18	5923	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5924	//! @brief Read current value of the FTM_SWOCTRL_CH2OC field.
mbed_official	146:f64d43ff0c18	5925	#define BR_FTM_SWOCTRL_CH2OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OC))
mbed_official	146:f64d43ff0c18	5926	#endif
mbed_official	146:f64d43ff0c18	5927
mbed_official	146:f64d43ff0c18	5928	//! @brief Format value for bitfield FTM_SWOCTRL_CH2OC.
mbed_official	146:f64d43ff0c18	5929	#define BF_FTM_SWOCTRL_CH2OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH2OC), uint32_t) & BM_FTM_SWOCTRL_CH2OC)
mbed_official	146:f64d43ff0c18	5930
mbed_official	146:f64d43ff0c18	5931	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5932	//! @brief Set the CH2OC field to a new value.
mbed_official	146:f64d43ff0c18	5933	#define BW_FTM_SWOCTRL_CH2OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OC) = (v))
mbed_official	146:f64d43ff0c18	5934	#endif
mbed_official	146:f64d43ff0c18	5935	//@}
mbed_official	146:f64d43ff0c18	5936
mbed_official	146:f64d43ff0c18	5937	/*!
mbed_official	146:f64d43ff0c18	5938	* @name Register FTM_SWOCTRL, field CH3OC[3] (RW)
mbed_official	146:f64d43ff0c18	5939	*
mbed_official	146:f64d43ff0c18	5940	* Values:
mbed_official	146:f64d43ff0c18	5941	* - 0 - The channel output is not affected by software output control.
mbed_official	146:f64d43ff0c18	5942	* - 1 - The channel output is affected by software output control.
mbed_official	146:f64d43ff0c18	5943	*/
mbed_official	146:f64d43ff0c18	5944	//@{
mbed_official	146:f64d43ff0c18	5945	#define BP_FTM_SWOCTRL_CH3OC (3U) //!< Bit position for FTM_SWOCTRL_CH3OC.
mbed_official	146:f64d43ff0c18	5946	#define BM_FTM_SWOCTRL_CH3OC (0x00000008U) //!< Bit mask for FTM_SWOCTRL_CH3OC.
mbed_official	146:f64d43ff0c18	5947	#define BS_FTM_SWOCTRL_CH3OC (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH3OC.
mbed_official	146:f64d43ff0c18	5948
mbed_official	146:f64d43ff0c18	5949	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5950	//! @brief Read current value of the FTM_SWOCTRL_CH3OC field.
mbed_official	146:f64d43ff0c18	5951	#define BR_FTM_SWOCTRL_CH3OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OC))
mbed_official	146:f64d43ff0c18	5952	#endif
mbed_official	146:f64d43ff0c18	5953
mbed_official	146:f64d43ff0c18	5954	//! @brief Format value for bitfield FTM_SWOCTRL_CH3OC.
mbed_official	146:f64d43ff0c18	5955	#define BF_FTM_SWOCTRL_CH3OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH3OC), uint32_t) & BM_FTM_SWOCTRL_CH3OC)
mbed_official	146:f64d43ff0c18	5956
mbed_official	146:f64d43ff0c18	5957	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5958	//! @brief Set the CH3OC field to a new value.
mbed_official	146:f64d43ff0c18	5959	#define BW_FTM_SWOCTRL_CH3OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OC) = (v))
mbed_official	146:f64d43ff0c18	5960	#endif
mbed_official	146:f64d43ff0c18	5961	//@}
mbed_official	146:f64d43ff0c18	5962
mbed_official	146:f64d43ff0c18	5963	/*!
mbed_official	146:f64d43ff0c18	5964	* @name Register FTM_SWOCTRL, field CH4OC[4] (RW)
mbed_official	146:f64d43ff0c18	5965	*
mbed_official	146:f64d43ff0c18	5966	* Values:
mbed_official	146:f64d43ff0c18	5967	* - 0 - The channel output is not affected by software output control.
mbed_official	146:f64d43ff0c18	5968	* - 1 - The channel output is affected by software output control.
mbed_official	146:f64d43ff0c18	5969	*/
mbed_official	146:f64d43ff0c18	5970	//@{
mbed_official	146:f64d43ff0c18	5971	#define BP_FTM_SWOCTRL_CH4OC (4U) //!< Bit position for FTM_SWOCTRL_CH4OC.
mbed_official	146:f64d43ff0c18	5972	#define BM_FTM_SWOCTRL_CH4OC (0x00000010U) //!< Bit mask for FTM_SWOCTRL_CH4OC.
mbed_official	146:f64d43ff0c18	5973	#define BS_FTM_SWOCTRL_CH4OC (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH4OC.
mbed_official	146:f64d43ff0c18	5974
mbed_official	146:f64d43ff0c18	5975	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5976	//! @brief Read current value of the FTM_SWOCTRL_CH4OC field.
mbed_official	146:f64d43ff0c18	5977	#define BR_FTM_SWOCTRL_CH4OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OC))
mbed_official	146:f64d43ff0c18	5978	#endif
mbed_official	146:f64d43ff0c18	5979
mbed_official	146:f64d43ff0c18	5980	//! @brief Format value for bitfield FTM_SWOCTRL_CH4OC.
mbed_official	146:f64d43ff0c18	5981	#define BF_FTM_SWOCTRL_CH4OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH4OC), uint32_t) & BM_FTM_SWOCTRL_CH4OC)
mbed_official	146:f64d43ff0c18	5982
mbed_official	146:f64d43ff0c18	5983	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	5984	//! @brief Set the CH4OC field to a new value.
mbed_official	146:f64d43ff0c18	5985	#define BW_FTM_SWOCTRL_CH4OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OC) = (v))
mbed_official	146:f64d43ff0c18	5986	#endif
mbed_official	146:f64d43ff0c18	5987	//@}
mbed_official	146:f64d43ff0c18	5988
mbed_official	146:f64d43ff0c18	5989	/*!
mbed_official	146:f64d43ff0c18	5990	* @name Register FTM_SWOCTRL, field CH5OC[5] (RW)
mbed_official	146:f64d43ff0c18	5991	*
mbed_official	146:f64d43ff0c18	5992	* Values:
mbed_official	146:f64d43ff0c18	5993	* - 0 - The channel output is not affected by software output control.
mbed_official	146:f64d43ff0c18	5994	* - 1 - The channel output is affected by software output control.
mbed_official	146:f64d43ff0c18	5995	*/
mbed_official	146:f64d43ff0c18	5996	//@{
mbed_official	146:f64d43ff0c18	5997	#define BP_FTM_SWOCTRL_CH5OC (5U) //!< Bit position for FTM_SWOCTRL_CH5OC.
mbed_official	146:f64d43ff0c18	5998	#define BM_FTM_SWOCTRL_CH5OC (0x00000020U) //!< Bit mask for FTM_SWOCTRL_CH5OC.
mbed_official	146:f64d43ff0c18	5999	#define BS_FTM_SWOCTRL_CH5OC (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH5OC.
mbed_official	146:f64d43ff0c18	6000
mbed_official	146:f64d43ff0c18	6001	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6002	//! @brief Read current value of the FTM_SWOCTRL_CH5OC field.
mbed_official	146:f64d43ff0c18	6003	#define BR_FTM_SWOCTRL_CH5OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OC))
mbed_official	146:f64d43ff0c18	6004	#endif
mbed_official	146:f64d43ff0c18	6005
mbed_official	146:f64d43ff0c18	6006	//! @brief Format value for bitfield FTM_SWOCTRL_CH5OC.
mbed_official	146:f64d43ff0c18	6007	#define BF_FTM_SWOCTRL_CH5OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH5OC), uint32_t) & BM_FTM_SWOCTRL_CH5OC)
mbed_official	146:f64d43ff0c18	6008
mbed_official	146:f64d43ff0c18	6009	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6010	//! @brief Set the CH5OC field to a new value.
mbed_official	146:f64d43ff0c18	6011	#define BW_FTM_SWOCTRL_CH5OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OC) = (v))
mbed_official	146:f64d43ff0c18	6012	#endif
mbed_official	146:f64d43ff0c18	6013	//@}
mbed_official	146:f64d43ff0c18	6014
mbed_official	146:f64d43ff0c18	6015	/*!
mbed_official	146:f64d43ff0c18	6016	* @name Register FTM_SWOCTRL, field CH6OC[6] (RW)
mbed_official	146:f64d43ff0c18	6017	*
mbed_official	146:f64d43ff0c18	6018	* Values:
mbed_official	146:f64d43ff0c18	6019	* - 0 - The channel output is not affected by software output control.
mbed_official	146:f64d43ff0c18	6020	* - 1 - The channel output is affected by software output control.
mbed_official	146:f64d43ff0c18	6021	*/
mbed_official	146:f64d43ff0c18	6022	//@{
mbed_official	146:f64d43ff0c18	6023	#define BP_FTM_SWOCTRL_CH6OC (6U) //!< Bit position for FTM_SWOCTRL_CH6OC.
mbed_official	146:f64d43ff0c18	6024	#define BM_FTM_SWOCTRL_CH6OC (0x00000040U) //!< Bit mask for FTM_SWOCTRL_CH6OC.
mbed_official	146:f64d43ff0c18	6025	#define BS_FTM_SWOCTRL_CH6OC (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH6OC.
mbed_official	146:f64d43ff0c18	6026
mbed_official	146:f64d43ff0c18	6027	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6028	//! @brief Read current value of the FTM_SWOCTRL_CH6OC field.
mbed_official	146:f64d43ff0c18	6029	#define BR_FTM_SWOCTRL_CH6OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OC))
mbed_official	146:f64d43ff0c18	6030	#endif
mbed_official	146:f64d43ff0c18	6031
mbed_official	146:f64d43ff0c18	6032	//! @brief Format value for bitfield FTM_SWOCTRL_CH6OC.
mbed_official	146:f64d43ff0c18	6033	#define BF_FTM_SWOCTRL_CH6OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH6OC), uint32_t) & BM_FTM_SWOCTRL_CH6OC)
mbed_official	146:f64d43ff0c18	6034
mbed_official	146:f64d43ff0c18	6035	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6036	//! @brief Set the CH6OC field to a new value.
mbed_official	146:f64d43ff0c18	6037	#define BW_FTM_SWOCTRL_CH6OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OC) = (v))
mbed_official	146:f64d43ff0c18	6038	#endif
mbed_official	146:f64d43ff0c18	6039	//@}
mbed_official	146:f64d43ff0c18	6040
mbed_official	146:f64d43ff0c18	6041	/*!
mbed_official	146:f64d43ff0c18	6042	* @name Register FTM_SWOCTRL, field CH7OC[7] (RW)
mbed_official	146:f64d43ff0c18	6043	*
mbed_official	146:f64d43ff0c18	6044	* Values:
mbed_official	146:f64d43ff0c18	6045	* - 0 - The channel output is not affected by software output control.
mbed_official	146:f64d43ff0c18	6046	* - 1 - The channel output is affected by software output control.
mbed_official	146:f64d43ff0c18	6047	*/
mbed_official	146:f64d43ff0c18	6048	//@{
mbed_official	146:f64d43ff0c18	6049	#define BP_FTM_SWOCTRL_CH7OC (7U) //!< Bit position for FTM_SWOCTRL_CH7OC.
mbed_official	146:f64d43ff0c18	6050	#define BM_FTM_SWOCTRL_CH7OC (0x00000080U) //!< Bit mask for FTM_SWOCTRL_CH7OC.
mbed_official	146:f64d43ff0c18	6051	#define BS_FTM_SWOCTRL_CH7OC (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH7OC.
mbed_official	146:f64d43ff0c18	6052
mbed_official	146:f64d43ff0c18	6053	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6054	//! @brief Read current value of the FTM_SWOCTRL_CH7OC field.
mbed_official	146:f64d43ff0c18	6055	#define BR_FTM_SWOCTRL_CH7OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OC))
mbed_official	146:f64d43ff0c18	6056	#endif
mbed_official	146:f64d43ff0c18	6057
mbed_official	146:f64d43ff0c18	6058	//! @brief Format value for bitfield FTM_SWOCTRL_CH7OC.
mbed_official	146:f64d43ff0c18	6059	#define BF_FTM_SWOCTRL_CH7OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH7OC), uint32_t) & BM_FTM_SWOCTRL_CH7OC)
mbed_official	146:f64d43ff0c18	6060
mbed_official	146:f64d43ff0c18	6061	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6062	//! @brief Set the CH7OC field to a new value.
mbed_official	146:f64d43ff0c18	6063	#define BW_FTM_SWOCTRL_CH7OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OC) = (v))
mbed_official	146:f64d43ff0c18	6064	#endif
mbed_official	146:f64d43ff0c18	6065	//@}
mbed_official	146:f64d43ff0c18	6066
mbed_official	146:f64d43ff0c18	6067	/*!
mbed_official	146:f64d43ff0c18	6068	* @name Register FTM_SWOCTRL, field CH0OCV[8] (RW)
mbed_official	146:f64d43ff0c18	6069	*
mbed_official	146:f64d43ff0c18	6070	* Values:
mbed_official	146:f64d43ff0c18	6071	* - 0 - The software output control forces 0 to the channel output.
mbed_official	146:f64d43ff0c18	6072	* - 1 - The software output control forces 1 to the channel output.
mbed_official	146:f64d43ff0c18	6073	*/
mbed_official	146:f64d43ff0c18	6074	//@{
mbed_official	146:f64d43ff0c18	6075	#define BP_FTM_SWOCTRL_CH0OCV (8U) //!< Bit position for FTM_SWOCTRL_CH0OCV.
mbed_official	146:f64d43ff0c18	6076	#define BM_FTM_SWOCTRL_CH0OCV (0x00000100U) //!< Bit mask for FTM_SWOCTRL_CH0OCV.
mbed_official	146:f64d43ff0c18	6077	#define BS_FTM_SWOCTRL_CH0OCV (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH0OCV.
mbed_official	146:f64d43ff0c18	6078
mbed_official	146:f64d43ff0c18	6079	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6080	//! @brief Read current value of the FTM_SWOCTRL_CH0OCV field.
mbed_official	146:f64d43ff0c18	6081	#define BR_FTM_SWOCTRL_CH0OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OCV))
mbed_official	146:f64d43ff0c18	6082	#endif
mbed_official	146:f64d43ff0c18	6083
mbed_official	146:f64d43ff0c18	6084	//! @brief Format value for bitfield FTM_SWOCTRL_CH0OCV.
mbed_official	146:f64d43ff0c18	6085	#define BF_FTM_SWOCTRL_CH0OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH0OCV), uint32_t) & BM_FTM_SWOCTRL_CH0OCV)
mbed_official	146:f64d43ff0c18	6086
mbed_official	146:f64d43ff0c18	6087	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6088	//! @brief Set the CH0OCV field to a new value.
mbed_official	146:f64d43ff0c18	6089	#define BW_FTM_SWOCTRL_CH0OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OCV) = (v))
mbed_official	146:f64d43ff0c18	6090	#endif
mbed_official	146:f64d43ff0c18	6091	//@}
mbed_official	146:f64d43ff0c18	6092
mbed_official	146:f64d43ff0c18	6093	/*!
mbed_official	146:f64d43ff0c18	6094	* @name Register FTM_SWOCTRL, field CH1OCV[9] (RW)
mbed_official	146:f64d43ff0c18	6095	*
mbed_official	146:f64d43ff0c18	6096	* Values:
mbed_official	146:f64d43ff0c18	6097	* - 0 - The software output control forces 0 to the channel output.
mbed_official	146:f64d43ff0c18	6098	* - 1 - The software output control forces 1 to the channel output.
mbed_official	146:f64d43ff0c18	6099	*/
mbed_official	146:f64d43ff0c18	6100	//@{
mbed_official	146:f64d43ff0c18	6101	#define BP_FTM_SWOCTRL_CH1OCV (9U) //!< Bit position for FTM_SWOCTRL_CH1OCV.
mbed_official	146:f64d43ff0c18	6102	#define BM_FTM_SWOCTRL_CH1OCV (0x00000200U) //!< Bit mask for FTM_SWOCTRL_CH1OCV.
mbed_official	146:f64d43ff0c18	6103	#define BS_FTM_SWOCTRL_CH1OCV (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH1OCV.
mbed_official	146:f64d43ff0c18	6104
mbed_official	146:f64d43ff0c18	6105	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6106	//! @brief Read current value of the FTM_SWOCTRL_CH1OCV field.
mbed_official	146:f64d43ff0c18	6107	#define BR_FTM_SWOCTRL_CH1OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OCV))
mbed_official	146:f64d43ff0c18	6108	#endif
mbed_official	146:f64d43ff0c18	6109
mbed_official	146:f64d43ff0c18	6110	//! @brief Format value for bitfield FTM_SWOCTRL_CH1OCV.
mbed_official	146:f64d43ff0c18	6111	#define BF_FTM_SWOCTRL_CH1OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH1OCV), uint32_t) & BM_FTM_SWOCTRL_CH1OCV)
mbed_official	146:f64d43ff0c18	6112
mbed_official	146:f64d43ff0c18	6113	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6114	//! @brief Set the CH1OCV field to a new value.
mbed_official	146:f64d43ff0c18	6115	#define BW_FTM_SWOCTRL_CH1OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OCV) = (v))
mbed_official	146:f64d43ff0c18	6116	#endif
mbed_official	146:f64d43ff0c18	6117	//@}
mbed_official	146:f64d43ff0c18	6118
mbed_official	146:f64d43ff0c18	6119	/*!
mbed_official	146:f64d43ff0c18	6120	* @name Register FTM_SWOCTRL, field CH2OCV[10] (RW)
mbed_official	146:f64d43ff0c18	6121	*
mbed_official	146:f64d43ff0c18	6122	* Values:
mbed_official	146:f64d43ff0c18	6123	* - 0 - The software output control forces 0 to the channel output.
mbed_official	146:f64d43ff0c18	6124	* - 1 - The software output control forces 1 to the channel output.
mbed_official	146:f64d43ff0c18	6125	*/
mbed_official	146:f64d43ff0c18	6126	//@{
mbed_official	146:f64d43ff0c18	6127	#define BP_FTM_SWOCTRL_CH2OCV (10U) //!< Bit position for FTM_SWOCTRL_CH2OCV.
mbed_official	146:f64d43ff0c18	6128	#define BM_FTM_SWOCTRL_CH2OCV (0x00000400U) //!< Bit mask for FTM_SWOCTRL_CH2OCV.
mbed_official	146:f64d43ff0c18	6129	#define BS_FTM_SWOCTRL_CH2OCV (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH2OCV.
mbed_official	146:f64d43ff0c18	6130
mbed_official	146:f64d43ff0c18	6131	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6132	//! @brief Read current value of the FTM_SWOCTRL_CH2OCV field.
mbed_official	146:f64d43ff0c18	6133	#define BR_FTM_SWOCTRL_CH2OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OCV))
mbed_official	146:f64d43ff0c18	6134	#endif
mbed_official	146:f64d43ff0c18	6135
mbed_official	146:f64d43ff0c18	6136	//! @brief Format value for bitfield FTM_SWOCTRL_CH2OCV.
mbed_official	146:f64d43ff0c18	6137	#define BF_FTM_SWOCTRL_CH2OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH2OCV), uint32_t) & BM_FTM_SWOCTRL_CH2OCV)
mbed_official	146:f64d43ff0c18	6138
mbed_official	146:f64d43ff0c18	6139	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6140	//! @brief Set the CH2OCV field to a new value.
mbed_official	146:f64d43ff0c18	6141	#define BW_FTM_SWOCTRL_CH2OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OCV) = (v))
mbed_official	146:f64d43ff0c18	6142	#endif
mbed_official	146:f64d43ff0c18	6143	//@}
mbed_official	146:f64d43ff0c18	6144
mbed_official	146:f64d43ff0c18	6145	/*!
mbed_official	146:f64d43ff0c18	6146	* @name Register FTM_SWOCTRL, field CH3OCV[11] (RW)
mbed_official	146:f64d43ff0c18	6147	*
mbed_official	146:f64d43ff0c18	6148	* Values:
mbed_official	146:f64d43ff0c18	6149	* - 0 - The software output control forces 0 to the channel output.
mbed_official	146:f64d43ff0c18	6150	* - 1 - The software output control forces 1 to the channel output.
mbed_official	146:f64d43ff0c18	6151	*/
mbed_official	146:f64d43ff0c18	6152	//@{
mbed_official	146:f64d43ff0c18	6153	#define BP_FTM_SWOCTRL_CH3OCV (11U) //!< Bit position for FTM_SWOCTRL_CH3OCV.
mbed_official	146:f64d43ff0c18	6154	#define BM_FTM_SWOCTRL_CH3OCV (0x00000800U) //!< Bit mask for FTM_SWOCTRL_CH3OCV.
mbed_official	146:f64d43ff0c18	6155	#define BS_FTM_SWOCTRL_CH3OCV (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH3OCV.
mbed_official	146:f64d43ff0c18	6156
mbed_official	146:f64d43ff0c18	6157	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6158	//! @brief Read current value of the FTM_SWOCTRL_CH3OCV field.
mbed_official	146:f64d43ff0c18	6159	#define BR_FTM_SWOCTRL_CH3OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OCV))
mbed_official	146:f64d43ff0c18	6160	#endif
mbed_official	146:f64d43ff0c18	6161
mbed_official	146:f64d43ff0c18	6162	//! @brief Format value for bitfield FTM_SWOCTRL_CH3OCV.
mbed_official	146:f64d43ff0c18	6163	#define BF_FTM_SWOCTRL_CH3OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH3OCV), uint32_t) & BM_FTM_SWOCTRL_CH3OCV)
mbed_official	146:f64d43ff0c18	6164
mbed_official	146:f64d43ff0c18	6165	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6166	//! @brief Set the CH3OCV field to a new value.
mbed_official	146:f64d43ff0c18	6167	#define BW_FTM_SWOCTRL_CH3OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OCV) = (v))
mbed_official	146:f64d43ff0c18	6168	#endif
mbed_official	146:f64d43ff0c18	6169	//@}
mbed_official	146:f64d43ff0c18	6170
mbed_official	146:f64d43ff0c18	6171	/*!
mbed_official	146:f64d43ff0c18	6172	* @name Register FTM_SWOCTRL, field CH4OCV[12] (RW)
mbed_official	146:f64d43ff0c18	6173	*
mbed_official	146:f64d43ff0c18	6174	* Values:
mbed_official	146:f64d43ff0c18	6175	* - 0 - The software output control forces 0 to the channel output.
mbed_official	146:f64d43ff0c18	6176	* - 1 - The software output control forces 1 to the channel output.
mbed_official	146:f64d43ff0c18	6177	*/
mbed_official	146:f64d43ff0c18	6178	//@{
mbed_official	146:f64d43ff0c18	6179	#define BP_FTM_SWOCTRL_CH4OCV (12U) //!< Bit position for FTM_SWOCTRL_CH4OCV.
mbed_official	146:f64d43ff0c18	6180	#define BM_FTM_SWOCTRL_CH4OCV (0x00001000U) //!< Bit mask for FTM_SWOCTRL_CH4OCV.
mbed_official	146:f64d43ff0c18	6181	#define BS_FTM_SWOCTRL_CH4OCV (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH4OCV.
mbed_official	146:f64d43ff0c18	6182
mbed_official	146:f64d43ff0c18	6183	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6184	//! @brief Read current value of the FTM_SWOCTRL_CH4OCV field.
mbed_official	146:f64d43ff0c18	6185	#define BR_FTM_SWOCTRL_CH4OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OCV))
mbed_official	146:f64d43ff0c18	6186	#endif
mbed_official	146:f64d43ff0c18	6187
mbed_official	146:f64d43ff0c18	6188	//! @brief Format value for bitfield FTM_SWOCTRL_CH4OCV.
mbed_official	146:f64d43ff0c18	6189	#define BF_FTM_SWOCTRL_CH4OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH4OCV), uint32_t) & BM_FTM_SWOCTRL_CH4OCV)
mbed_official	146:f64d43ff0c18	6190
mbed_official	146:f64d43ff0c18	6191	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6192	//! @brief Set the CH4OCV field to a new value.
mbed_official	146:f64d43ff0c18	6193	#define BW_FTM_SWOCTRL_CH4OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OCV) = (v))
mbed_official	146:f64d43ff0c18	6194	#endif
mbed_official	146:f64d43ff0c18	6195	//@}
mbed_official	146:f64d43ff0c18	6196
mbed_official	146:f64d43ff0c18	6197	/*!
mbed_official	146:f64d43ff0c18	6198	* @name Register FTM_SWOCTRL, field CH5OCV[13] (RW)
mbed_official	146:f64d43ff0c18	6199	*
mbed_official	146:f64d43ff0c18	6200	* Values:
mbed_official	146:f64d43ff0c18	6201	* - 0 - The software output control forces 0 to the channel output.
mbed_official	146:f64d43ff0c18	6202	* - 1 - The software output control forces 1 to the channel output.
mbed_official	146:f64d43ff0c18	6203	*/
mbed_official	146:f64d43ff0c18	6204	//@{
mbed_official	146:f64d43ff0c18	6205	#define BP_FTM_SWOCTRL_CH5OCV (13U) //!< Bit position for FTM_SWOCTRL_CH5OCV.
mbed_official	146:f64d43ff0c18	6206	#define BM_FTM_SWOCTRL_CH5OCV (0x00002000U) //!< Bit mask for FTM_SWOCTRL_CH5OCV.
mbed_official	146:f64d43ff0c18	6207	#define BS_FTM_SWOCTRL_CH5OCV (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH5OCV.
mbed_official	146:f64d43ff0c18	6208
mbed_official	146:f64d43ff0c18	6209	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6210	//! @brief Read current value of the FTM_SWOCTRL_CH5OCV field.
mbed_official	146:f64d43ff0c18	6211	#define BR_FTM_SWOCTRL_CH5OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OCV))
mbed_official	146:f64d43ff0c18	6212	#endif
mbed_official	146:f64d43ff0c18	6213
mbed_official	146:f64d43ff0c18	6214	//! @brief Format value for bitfield FTM_SWOCTRL_CH5OCV.
mbed_official	146:f64d43ff0c18	6215	#define BF_FTM_SWOCTRL_CH5OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH5OCV), uint32_t) & BM_FTM_SWOCTRL_CH5OCV)
mbed_official	146:f64d43ff0c18	6216
mbed_official	146:f64d43ff0c18	6217	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6218	//! @brief Set the CH5OCV field to a new value.
mbed_official	146:f64d43ff0c18	6219	#define BW_FTM_SWOCTRL_CH5OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OCV) = (v))
mbed_official	146:f64d43ff0c18	6220	#endif
mbed_official	146:f64d43ff0c18	6221	//@}
mbed_official	146:f64d43ff0c18	6222
mbed_official	146:f64d43ff0c18	6223	/*!
mbed_official	146:f64d43ff0c18	6224	* @name Register FTM_SWOCTRL, field CH6OCV[14] (RW)
mbed_official	146:f64d43ff0c18	6225	*
mbed_official	146:f64d43ff0c18	6226	* Values:
mbed_official	146:f64d43ff0c18	6227	* - 0 - The software output control forces 0 to the channel output.
mbed_official	146:f64d43ff0c18	6228	* - 1 - The software output control forces 1 to the channel output.
mbed_official	146:f64d43ff0c18	6229	*/
mbed_official	146:f64d43ff0c18	6230	//@{
mbed_official	146:f64d43ff0c18	6231	#define BP_FTM_SWOCTRL_CH6OCV (14U) //!< Bit position for FTM_SWOCTRL_CH6OCV.
mbed_official	146:f64d43ff0c18	6232	#define BM_FTM_SWOCTRL_CH6OCV (0x00004000U) //!< Bit mask for FTM_SWOCTRL_CH6OCV.
mbed_official	146:f64d43ff0c18	6233	#define BS_FTM_SWOCTRL_CH6OCV (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH6OCV.
mbed_official	146:f64d43ff0c18	6234
mbed_official	146:f64d43ff0c18	6235	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6236	//! @brief Read current value of the FTM_SWOCTRL_CH6OCV field.
mbed_official	146:f64d43ff0c18	6237	#define BR_FTM_SWOCTRL_CH6OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OCV))
mbed_official	146:f64d43ff0c18	6238	#endif
mbed_official	146:f64d43ff0c18	6239
mbed_official	146:f64d43ff0c18	6240	//! @brief Format value for bitfield FTM_SWOCTRL_CH6OCV.
mbed_official	146:f64d43ff0c18	6241	#define BF_FTM_SWOCTRL_CH6OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH6OCV), uint32_t) & BM_FTM_SWOCTRL_CH6OCV)
mbed_official	146:f64d43ff0c18	6242
mbed_official	146:f64d43ff0c18	6243	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6244	//! @brief Set the CH6OCV field to a new value.
mbed_official	146:f64d43ff0c18	6245	#define BW_FTM_SWOCTRL_CH6OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OCV) = (v))
mbed_official	146:f64d43ff0c18	6246	#endif
mbed_official	146:f64d43ff0c18	6247	//@}
mbed_official	146:f64d43ff0c18	6248
mbed_official	146:f64d43ff0c18	6249	/*!
mbed_official	146:f64d43ff0c18	6250	* @name Register FTM_SWOCTRL, field CH7OCV[15] (RW)
mbed_official	146:f64d43ff0c18	6251	*
mbed_official	146:f64d43ff0c18	6252	* Values:
mbed_official	146:f64d43ff0c18	6253	* - 0 - The software output control forces 0 to the channel output.
mbed_official	146:f64d43ff0c18	6254	* - 1 - The software output control forces 1 to the channel output.
mbed_official	146:f64d43ff0c18	6255	*/
mbed_official	146:f64d43ff0c18	6256	//@{
mbed_official	146:f64d43ff0c18	6257	#define BP_FTM_SWOCTRL_CH7OCV (15U) //!< Bit position for FTM_SWOCTRL_CH7OCV.
mbed_official	146:f64d43ff0c18	6258	#define BM_FTM_SWOCTRL_CH7OCV (0x00008000U) //!< Bit mask for FTM_SWOCTRL_CH7OCV.
mbed_official	146:f64d43ff0c18	6259	#define BS_FTM_SWOCTRL_CH7OCV (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH7OCV.
mbed_official	146:f64d43ff0c18	6260
mbed_official	146:f64d43ff0c18	6261	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6262	//! @brief Read current value of the FTM_SWOCTRL_CH7OCV field.
mbed_official	146:f64d43ff0c18	6263	#define BR_FTM_SWOCTRL_CH7OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OCV))
mbed_official	146:f64d43ff0c18	6264	#endif
mbed_official	146:f64d43ff0c18	6265
mbed_official	146:f64d43ff0c18	6266	//! @brief Format value for bitfield FTM_SWOCTRL_CH7OCV.
mbed_official	146:f64d43ff0c18	6267	#define BF_FTM_SWOCTRL_CH7OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH7OCV), uint32_t) & BM_FTM_SWOCTRL_CH7OCV)
mbed_official	146:f64d43ff0c18	6268
mbed_official	146:f64d43ff0c18	6269	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6270	//! @brief Set the CH7OCV field to a new value.
mbed_official	146:f64d43ff0c18	6271	#define BW_FTM_SWOCTRL_CH7OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OCV) = (v))
mbed_official	146:f64d43ff0c18	6272	#endif
mbed_official	146:f64d43ff0c18	6273	//@}
mbed_official	146:f64d43ff0c18	6274
mbed_official	146:f64d43ff0c18	6275	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	6276	// HW_FTM_PWMLOAD - FTM PWM Load
mbed_official	146:f64d43ff0c18	6277	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	6278
mbed_official	146:f64d43ff0c18	6279	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6280	/*!
mbed_official	146:f64d43ff0c18	6281	* @brief HW_FTM_PWMLOAD - FTM PWM Load (RW)
mbed_official	146:f64d43ff0c18	6282	*
mbed_official	146:f64d43ff0c18	6283	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	6284	*
mbed_official	146:f64d43ff0c18	6285	* Enables the loading of the MOD, CNTIN, C(n)V, and C(n+1)V registers with the
mbed_official	146:f64d43ff0c18	6286	* values of their write buffers when the FTM counter changes from the MOD
mbed_official	146:f64d43ff0c18	6287	* register value to its next value or when a channel (j) match occurs. A match occurs
mbed_official	146:f64d43ff0c18	6288	* for the channel (j) when FTM counter = C(j)V.
mbed_official	146:f64d43ff0c18	6289	*/
mbed_official	146:f64d43ff0c18	6290	typedef union _hw_ftm_pwmload
mbed_official	146:f64d43ff0c18	6291	{
mbed_official	146:f64d43ff0c18	6292	uint32_t U;
mbed_official	146:f64d43ff0c18	6293	struct _hw_ftm_pwmload_bitfields
mbed_official	146:f64d43ff0c18	6294	{
mbed_official	146:f64d43ff0c18	6295	uint32_t CH0SEL : 1; //!< [0] Channel 0 Select
mbed_official	146:f64d43ff0c18	6296	uint32_t CH1SEL : 1; //!< [1] Channel 1 Select
mbed_official	146:f64d43ff0c18	6297	uint32_t CH2SEL : 1; //!< [2] Channel 2 Select
mbed_official	146:f64d43ff0c18	6298	uint32_t CH3SEL : 1; //!< [3] Channel 3 Select
mbed_official	146:f64d43ff0c18	6299	uint32_t CH4SEL : 1; //!< [4] Channel 4 Select
mbed_official	146:f64d43ff0c18	6300	uint32_t CH5SEL : 1; //!< [5] Channel 5 Select
mbed_official	146:f64d43ff0c18	6301	uint32_t CH6SEL : 1; //!< [6] Channel 6 Select
mbed_official	146:f64d43ff0c18	6302	uint32_t CH7SEL : 1; //!< [7] Channel 7 Select
mbed_official	146:f64d43ff0c18	6303	uint32_t RESERVED0 : 1; //!< [8]
mbed_official	146:f64d43ff0c18	6304	uint32_t LDOK : 1; //!< [9] Load Enable
mbed_official	146:f64d43ff0c18	6305	uint32_t RESERVED1 : 22; //!< [31:10]
mbed_official	146:f64d43ff0c18	6306	} B;
mbed_official	146:f64d43ff0c18	6307	} hw_ftm_pwmload_t;
mbed_official	146:f64d43ff0c18	6308	#endif
mbed_official	146:f64d43ff0c18	6309
mbed_official	146:f64d43ff0c18	6310	/*!
mbed_official	146:f64d43ff0c18	6311	* @name Constants and macros for entire FTM_PWMLOAD register
mbed_official	146:f64d43ff0c18	6312	*/
mbed_official	146:f64d43ff0c18	6313	//@{
mbed_official	146:f64d43ff0c18	6314	#define HW_FTM_PWMLOAD_ADDR(x) (REGS_FTM_BASE(x) + 0x98U)
mbed_official	146:f64d43ff0c18	6315
mbed_official	146:f64d43ff0c18	6316	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6317	#define HW_FTM_PWMLOAD(x) ((__IO hw_ftm_pwmload_t ) HW_FTM_PWMLOAD_ADDR(x))
mbed_official	146:f64d43ff0c18	6318	#define HW_FTM_PWMLOAD_RD(x) (HW_FTM_PWMLOAD(x).U)
mbed_official	146:f64d43ff0c18	6319	#define HW_FTM_PWMLOAD_WR(x, v) (HW_FTM_PWMLOAD(x).U = (v))
mbed_official	146:f64d43ff0c18	6320	#define HW_FTM_PWMLOAD_SET(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	6321	#define HW_FTM_PWMLOAD_CLR(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	6322	#define HW_FTM_PWMLOAD_TOG(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	6323	#endif
mbed_official	146:f64d43ff0c18	6324	//@}
mbed_official	146:f64d43ff0c18	6325
mbed_official	146:f64d43ff0c18	6326	/*
mbed_official	146:f64d43ff0c18	6327	* Constants & macros for individual FTM_PWMLOAD bitfields
mbed_official	146:f64d43ff0c18	6328	*/
mbed_official	146:f64d43ff0c18	6329
mbed_official	146:f64d43ff0c18	6330	/*!
mbed_official	146:f64d43ff0c18	6331	* @name Register FTM_PWMLOAD, field CH0SEL[0] (RW)
mbed_official	146:f64d43ff0c18	6332	*
mbed_official	146:f64d43ff0c18	6333	* Values:
mbed_official	146:f64d43ff0c18	6334	* - 0 - Do not include the channel in the matching process.
mbed_official	146:f64d43ff0c18	6335	* - 1 - Include the channel in the matching process.
mbed_official	146:f64d43ff0c18	6336	*/
mbed_official	146:f64d43ff0c18	6337	//@{
mbed_official	146:f64d43ff0c18	6338	#define BP_FTM_PWMLOAD_CH0SEL (0U) //!< Bit position for FTM_PWMLOAD_CH0SEL.
mbed_official	146:f64d43ff0c18	6339	#define BM_FTM_PWMLOAD_CH0SEL (0x00000001U) //!< Bit mask for FTM_PWMLOAD_CH0SEL.
mbed_official	146:f64d43ff0c18	6340	#define BS_FTM_PWMLOAD_CH0SEL (1U) //!< Bit field size in bits for FTM_PWMLOAD_CH0SEL.
mbed_official	146:f64d43ff0c18	6341
mbed_official	146:f64d43ff0c18	6342	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6343	//! @brief Read current value of the FTM_PWMLOAD_CH0SEL field.
mbed_official	146:f64d43ff0c18	6344	#define BR_FTM_PWMLOAD_CH0SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH0SEL))
mbed_official	146:f64d43ff0c18	6345	#endif
mbed_official	146:f64d43ff0c18	6346
mbed_official	146:f64d43ff0c18	6347	//! @brief Format value for bitfield FTM_PWMLOAD_CH0SEL.
mbed_official	146:f64d43ff0c18	6348	#define BF_FTM_PWMLOAD_CH0SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH0SEL), uint32_t) & BM_FTM_PWMLOAD_CH0SEL)
mbed_official	146:f64d43ff0c18	6349
mbed_official	146:f64d43ff0c18	6350	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6351	//! @brief Set the CH0SEL field to a new value.
mbed_official	146:f64d43ff0c18	6352	#define BW_FTM_PWMLOAD_CH0SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH0SEL) = (v))
mbed_official	146:f64d43ff0c18	6353	#endif
mbed_official	146:f64d43ff0c18	6354	//@}
mbed_official	146:f64d43ff0c18	6355
mbed_official	146:f64d43ff0c18	6356	/*!
mbed_official	146:f64d43ff0c18	6357	* @name Register FTM_PWMLOAD, field CH1SEL[1] (RW)
mbed_official	146:f64d43ff0c18	6358	*
mbed_official	146:f64d43ff0c18	6359	* Values:
mbed_official	146:f64d43ff0c18	6360	* - 0 - Do not include the channel in the matching process.
mbed_official	146:f64d43ff0c18	6361	* - 1 - Include the channel in the matching process.
mbed_official	146:f64d43ff0c18	6362	*/
mbed_official	146:f64d43ff0c18	6363	//@{
mbed_official	146:f64d43ff0c18	6364	#define BP_FTM_PWMLOAD_CH1SEL (1U) //!< Bit position for FTM_PWMLOAD_CH1SEL.
mbed_official	146:f64d43ff0c18	6365	#define BM_FTM_PWMLOAD_CH1SEL (0x00000002U) //!< Bit mask for FTM_PWMLOAD_CH1SEL.
mbed_official	146:f64d43ff0c18	6366	#define BS_FTM_PWMLOAD_CH1SEL (1U) //!< Bit field size in bits for FTM_PWMLOAD_CH1SEL.
mbed_official	146:f64d43ff0c18	6367
mbed_official	146:f64d43ff0c18	6368	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6369	//! @brief Read current value of the FTM_PWMLOAD_CH1SEL field.
mbed_official	146:f64d43ff0c18	6370	#define BR_FTM_PWMLOAD_CH1SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH1SEL))
mbed_official	146:f64d43ff0c18	6371	#endif
mbed_official	146:f64d43ff0c18	6372
mbed_official	146:f64d43ff0c18	6373	//! @brief Format value for bitfield FTM_PWMLOAD_CH1SEL.
mbed_official	146:f64d43ff0c18	6374	#define BF_FTM_PWMLOAD_CH1SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH1SEL), uint32_t) & BM_FTM_PWMLOAD_CH1SEL)
mbed_official	146:f64d43ff0c18	6375
mbed_official	146:f64d43ff0c18	6376	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6377	//! @brief Set the CH1SEL field to a new value.
mbed_official	146:f64d43ff0c18	6378	#define BW_FTM_PWMLOAD_CH1SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH1SEL) = (v))
mbed_official	146:f64d43ff0c18	6379	#endif
mbed_official	146:f64d43ff0c18	6380	//@}
mbed_official	146:f64d43ff0c18	6381
mbed_official	146:f64d43ff0c18	6382	/*!
mbed_official	146:f64d43ff0c18	6383	* @name Register FTM_PWMLOAD, field CH2SEL[2] (RW)
mbed_official	146:f64d43ff0c18	6384	*
mbed_official	146:f64d43ff0c18	6385	* Values:
mbed_official	146:f64d43ff0c18	6386	* - 0 - Do not include the channel in the matching process.
mbed_official	146:f64d43ff0c18	6387	* - 1 - Include the channel in the matching process.
mbed_official	146:f64d43ff0c18	6388	*/
mbed_official	146:f64d43ff0c18	6389	//@{
mbed_official	146:f64d43ff0c18	6390	#define BP_FTM_PWMLOAD_CH2SEL (2U) //!< Bit position for FTM_PWMLOAD_CH2SEL.
mbed_official	146:f64d43ff0c18	6391	#define BM_FTM_PWMLOAD_CH2SEL (0x00000004U) //!< Bit mask for FTM_PWMLOAD_CH2SEL.
mbed_official	146:f64d43ff0c18	6392	#define BS_FTM_PWMLOAD_CH2SEL (1U) //!< Bit field size in bits for FTM_PWMLOAD_CH2SEL.
mbed_official	146:f64d43ff0c18	6393
mbed_official	146:f64d43ff0c18	6394	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6395	//! @brief Read current value of the FTM_PWMLOAD_CH2SEL field.
mbed_official	146:f64d43ff0c18	6396	#define BR_FTM_PWMLOAD_CH2SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH2SEL))
mbed_official	146:f64d43ff0c18	6397	#endif
mbed_official	146:f64d43ff0c18	6398
mbed_official	146:f64d43ff0c18	6399	//! @brief Format value for bitfield FTM_PWMLOAD_CH2SEL.
mbed_official	146:f64d43ff0c18	6400	#define BF_FTM_PWMLOAD_CH2SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH2SEL), uint32_t) & BM_FTM_PWMLOAD_CH2SEL)
mbed_official	146:f64d43ff0c18	6401
mbed_official	146:f64d43ff0c18	6402	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6403	//! @brief Set the CH2SEL field to a new value.
mbed_official	146:f64d43ff0c18	6404	#define BW_FTM_PWMLOAD_CH2SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH2SEL) = (v))
mbed_official	146:f64d43ff0c18	6405	#endif
mbed_official	146:f64d43ff0c18	6406	//@}
mbed_official	146:f64d43ff0c18	6407
mbed_official	146:f64d43ff0c18	6408	/*!
mbed_official	146:f64d43ff0c18	6409	* @name Register FTM_PWMLOAD, field CH3SEL[3] (RW)
mbed_official	146:f64d43ff0c18	6410	*
mbed_official	146:f64d43ff0c18	6411	* Values:
mbed_official	146:f64d43ff0c18	6412	* - 0 - Do not include the channel in the matching process.
mbed_official	146:f64d43ff0c18	6413	* - 1 - Include the channel in the matching process.
mbed_official	146:f64d43ff0c18	6414	*/
mbed_official	146:f64d43ff0c18	6415	//@{
mbed_official	146:f64d43ff0c18	6416	#define BP_FTM_PWMLOAD_CH3SEL (3U) //!< Bit position for FTM_PWMLOAD_CH3SEL.
mbed_official	146:f64d43ff0c18	6417	#define BM_FTM_PWMLOAD_CH3SEL (0x00000008U) //!< Bit mask for FTM_PWMLOAD_CH3SEL.
mbed_official	146:f64d43ff0c18	6418	#define BS_FTM_PWMLOAD_CH3SEL (1U) //!< Bit field size in bits for FTM_PWMLOAD_CH3SEL.
mbed_official	146:f64d43ff0c18	6419
mbed_official	146:f64d43ff0c18	6420	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6421	//! @brief Read current value of the FTM_PWMLOAD_CH3SEL field.
mbed_official	146:f64d43ff0c18	6422	#define BR_FTM_PWMLOAD_CH3SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH3SEL))
mbed_official	146:f64d43ff0c18	6423	#endif
mbed_official	146:f64d43ff0c18	6424
mbed_official	146:f64d43ff0c18	6425	//! @brief Format value for bitfield FTM_PWMLOAD_CH3SEL.
mbed_official	146:f64d43ff0c18	6426	#define BF_FTM_PWMLOAD_CH3SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH3SEL), uint32_t) & BM_FTM_PWMLOAD_CH3SEL)
mbed_official	146:f64d43ff0c18	6427
mbed_official	146:f64d43ff0c18	6428	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6429	//! @brief Set the CH3SEL field to a new value.
mbed_official	146:f64d43ff0c18	6430	#define BW_FTM_PWMLOAD_CH3SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH3SEL) = (v))
mbed_official	146:f64d43ff0c18	6431	#endif
mbed_official	146:f64d43ff0c18	6432	//@}
mbed_official	146:f64d43ff0c18	6433
mbed_official	146:f64d43ff0c18	6434	/*!
mbed_official	146:f64d43ff0c18	6435	* @name Register FTM_PWMLOAD, field CH4SEL[4] (RW)
mbed_official	146:f64d43ff0c18	6436	*
mbed_official	146:f64d43ff0c18	6437	* Values:
mbed_official	146:f64d43ff0c18	6438	* - 0 - Do not include the channel in the matching process.
mbed_official	146:f64d43ff0c18	6439	* - 1 - Include the channel in the matching process.
mbed_official	146:f64d43ff0c18	6440	*/
mbed_official	146:f64d43ff0c18	6441	//@{
mbed_official	146:f64d43ff0c18	6442	#define BP_FTM_PWMLOAD_CH4SEL (4U) //!< Bit position for FTM_PWMLOAD_CH4SEL.
mbed_official	146:f64d43ff0c18	6443	#define BM_FTM_PWMLOAD_CH4SEL (0x00000010U) //!< Bit mask for FTM_PWMLOAD_CH4SEL.
mbed_official	146:f64d43ff0c18	6444	#define BS_FTM_PWMLOAD_CH4SEL (1U) //!< Bit field size in bits for FTM_PWMLOAD_CH4SEL.
mbed_official	146:f64d43ff0c18	6445
mbed_official	146:f64d43ff0c18	6446	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6447	//! @brief Read current value of the FTM_PWMLOAD_CH4SEL field.
mbed_official	146:f64d43ff0c18	6448	#define BR_FTM_PWMLOAD_CH4SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH4SEL))
mbed_official	146:f64d43ff0c18	6449	#endif
mbed_official	146:f64d43ff0c18	6450
mbed_official	146:f64d43ff0c18	6451	//! @brief Format value for bitfield FTM_PWMLOAD_CH4SEL.
mbed_official	146:f64d43ff0c18	6452	#define BF_FTM_PWMLOAD_CH4SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH4SEL), uint32_t) & BM_FTM_PWMLOAD_CH4SEL)
mbed_official	146:f64d43ff0c18	6453
mbed_official	146:f64d43ff0c18	6454	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6455	//! @brief Set the CH4SEL field to a new value.
mbed_official	146:f64d43ff0c18	6456	#define BW_FTM_PWMLOAD_CH4SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH4SEL) = (v))
mbed_official	146:f64d43ff0c18	6457	#endif
mbed_official	146:f64d43ff0c18	6458	//@}
mbed_official	146:f64d43ff0c18	6459
mbed_official	146:f64d43ff0c18	6460	/*!
mbed_official	146:f64d43ff0c18	6461	* @name Register FTM_PWMLOAD, field CH5SEL[5] (RW)
mbed_official	146:f64d43ff0c18	6462	*
mbed_official	146:f64d43ff0c18	6463	* Values:
mbed_official	146:f64d43ff0c18	6464	* - 0 - Do not include the channel in the matching process.
mbed_official	146:f64d43ff0c18	6465	* - 1 - Include the channel in the matching process.
mbed_official	146:f64d43ff0c18	6466	*/
mbed_official	146:f64d43ff0c18	6467	//@{
mbed_official	146:f64d43ff0c18	6468	#define BP_FTM_PWMLOAD_CH5SEL (5U) //!< Bit position for FTM_PWMLOAD_CH5SEL.
mbed_official	146:f64d43ff0c18	6469	#define BM_FTM_PWMLOAD_CH5SEL (0x00000020U) //!< Bit mask for FTM_PWMLOAD_CH5SEL.
mbed_official	146:f64d43ff0c18	6470	#define BS_FTM_PWMLOAD_CH5SEL (1U) //!< Bit field size in bits for FTM_PWMLOAD_CH5SEL.
mbed_official	146:f64d43ff0c18	6471
mbed_official	146:f64d43ff0c18	6472	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6473	//! @brief Read current value of the FTM_PWMLOAD_CH5SEL field.
mbed_official	146:f64d43ff0c18	6474	#define BR_FTM_PWMLOAD_CH5SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH5SEL))
mbed_official	146:f64d43ff0c18	6475	#endif
mbed_official	146:f64d43ff0c18	6476
mbed_official	146:f64d43ff0c18	6477	//! @brief Format value for bitfield FTM_PWMLOAD_CH5SEL.
mbed_official	146:f64d43ff0c18	6478	#define BF_FTM_PWMLOAD_CH5SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH5SEL), uint32_t) & BM_FTM_PWMLOAD_CH5SEL)
mbed_official	146:f64d43ff0c18	6479
mbed_official	146:f64d43ff0c18	6480	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6481	//! @brief Set the CH5SEL field to a new value.
mbed_official	146:f64d43ff0c18	6482	#define BW_FTM_PWMLOAD_CH5SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH5SEL) = (v))
mbed_official	146:f64d43ff0c18	6483	#endif
mbed_official	146:f64d43ff0c18	6484	//@}
mbed_official	146:f64d43ff0c18	6485
mbed_official	146:f64d43ff0c18	6486	/*!
mbed_official	146:f64d43ff0c18	6487	* @name Register FTM_PWMLOAD, field CH6SEL[6] (RW)
mbed_official	146:f64d43ff0c18	6488	*
mbed_official	146:f64d43ff0c18	6489	* Values:
mbed_official	146:f64d43ff0c18	6490	* - 0 - Do not include the channel in the matching process.
mbed_official	146:f64d43ff0c18	6491	* - 1 - Include the channel in the matching process.
mbed_official	146:f64d43ff0c18	6492	*/
mbed_official	146:f64d43ff0c18	6493	//@{
mbed_official	146:f64d43ff0c18	6494	#define BP_FTM_PWMLOAD_CH6SEL (6U) //!< Bit position for FTM_PWMLOAD_CH6SEL.
mbed_official	146:f64d43ff0c18	6495	#define BM_FTM_PWMLOAD_CH6SEL (0x00000040U) //!< Bit mask for FTM_PWMLOAD_CH6SEL.
mbed_official	146:f64d43ff0c18	6496	#define BS_FTM_PWMLOAD_CH6SEL (1U) //!< Bit field size in bits for FTM_PWMLOAD_CH6SEL.
mbed_official	146:f64d43ff0c18	6497
mbed_official	146:f64d43ff0c18	6498	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6499	//! @brief Read current value of the FTM_PWMLOAD_CH6SEL field.
mbed_official	146:f64d43ff0c18	6500	#define BR_FTM_PWMLOAD_CH6SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH6SEL))
mbed_official	146:f64d43ff0c18	6501	#endif
mbed_official	146:f64d43ff0c18	6502
mbed_official	146:f64d43ff0c18	6503	//! @brief Format value for bitfield FTM_PWMLOAD_CH6SEL.
mbed_official	146:f64d43ff0c18	6504	#define BF_FTM_PWMLOAD_CH6SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH6SEL), uint32_t) & BM_FTM_PWMLOAD_CH6SEL)
mbed_official	146:f64d43ff0c18	6505
mbed_official	146:f64d43ff0c18	6506	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6507	//! @brief Set the CH6SEL field to a new value.
mbed_official	146:f64d43ff0c18	6508	#define BW_FTM_PWMLOAD_CH6SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH6SEL) = (v))
mbed_official	146:f64d43ff0c18	6509	#endif
mbed_official	146:f64d43ff0c18	6510	//@}
mbed_official	146:f64d43ff0c18	6511
mbed_official	146:f64d43ff0c18	6512	/*!
mbed_official	146:f64d43ff0c18	6513	* @name Register FTM_PWMLOAD, field CH7SEL[7] (RW)
mbed_official	146:f64d43ff0c18	6514	*
mbed_official	146:f64d43ff0c18	6515	* Values:
mbed_official	146:f64d43ff0c18	6516	* - 0 - Do not include the channel in the matching process.
mbed_official	146:f64d43ff0c18	6517	* - 1 - Include the channel in the matching process.
mbed_official	146:f64d43ff0c18	6518	*/
mbed_official	146:f64d43ff0c18	6519	//@{
mbed_official	146:f64d43ff0c18	6520	#define BP_FTM_PWMLOAD_CH7SEL (7U) //!< Bit position for FTM_PWMLOAD_CH7SEL.
mbed_official	146:f64d43ff0c18	6521	#define BM_FTM_PWMLOAD_CH7SEL (0x00000080U) //!< Bit mask for FTM_PWMLOAD_CH7SEL.
mbed_official	146:f64d43ff0c18	6522	#define BS_FTM_PWMLOAD_CH7SEL (1U) //!< Bit field size in bits for FTM_PWMLOAD_CH7SEL.
mbed_official	146:f64d43ff0c18	6523
mbed_official	146:f64d43ff0c18	6524	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6525	//! @brief Read current value of the FTM_PWMLOAD_CH7SEL field.
mbed_official	146:f64d43ff0c18	6526	#define BR_FTM_PWMLOAD_CH7SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH7SEL))
mbed_official	146:f64d43ff0c18	6527	#endif
mbed_official	146:f64d43ff0c18	6528
mbed_official	146:f64d43ff0c18	6529	//! @brief Format value for bitfield FTM_PWMLOAD_CH7SEL.
mbed_official	146:f64d43ff0c18	6530	#define BF_FTM_PWMLOAD_CH7SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH7SEL), uint32_t) & BM_FTM_PWMLOAD_CH7SEL)
mbed_official	146:f64d43ff0c18	6531
mbed_official	146:f64d43ff0c18	6532	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6533	//! @brief Set the CH7SEL field to a new value.
mbed_official	146:f64d43ff0c18	6534	#define BW_FTM_PWMLOAD_CH7SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH7SEL) = (v))
mbed_official	146:f64d43ff0c18	6535	#endif
mbed_official	146:f64d43ff0c18	6536	//@}
mbed_official	146:f64d43ff0c18	6537
mbed_official	146:f64d43ff0c18	6538	/*!
mbed_official	146:f64d43ff0c18	6539	* @name Register FTM_PWMLOAD, field LDOK[9] (RW)
mbed_official	146:f64d43ff0c18	6540	*
mbed_official	146:f64d43ff0c18	6541	* Enables the loading of the MOD, CNTIN, and CV registers with the values of
mbed_official	146:f64d43ff0c18	6542	* their write buffers.
mbed_official	146:f64d43ff0c18	6543	*
mbed_official	146:f64d43ff0c18	6544	* Values:
mbed_official	146:f64d43ff0c18	6545	* - 0 - Loading updated values is disabled.
mbed_official	146:f64d43ff0c18	6546	* - 1 - Loading updated values is enabled.
mbed_official	146:f64d43ff0c18	6547	*/
mbed_official	146:f64d43ff0c18	6548	//@{
mbed_official	146:f64d43ff0c18	6549	#define BP_FTM_PWMLOAD_LDOK (9U) //!< Bit position for FTM_PWMLOAD_LDOK.
mbed_official	146:f64d43ff0c18	6550	#define BM_FTM_PWMLOAD_LDOK (0x00000200U) //!< Bit mask for FTM_PWMLOAD_LDOK.
mbed_official	146:f64d43ff0c18	6551	#define BS_FTM_PWMLOAD_LDOK (1U) //!< Bit field size in bits for FTM_PWMLOAD_LDOK.
mbed_official	146:f64d43ff0c18	6552
mbed_official	146:f64d43ff0c18	6553	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6554	//! @brief Read current value of the FTM_PWMLOAD_LDOK field.
mbed_official	146:f64d43ff0c18	6555	#define BR_FTM_PWMLOAD_LDOK(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_LDOK))
mbed_official	146:f64d43ff0c18	6556	#endif
mbed_official	146:f64d43ff0c18	6557
mbed_official	146:f64d43ff0c18	6558	//! @brief Format value for bitfield FTM_PWMLOAD_LDOK.
mbed_official	146:f64d43ff0c18	6559	#define BF_FTM_PWMLOAD_LDOK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_LDOK), uint32_t) & BM_FTM_PWMLOAD_LDOK)
mbed_official	146:f64d43ff0c18	6560
mbed_official	146:f64d43ff0c18	6561	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6562	//! @brief Set the LDOK field to a new value.
mbed_official	146:f64d43ff0c18	6563	#define BW_FTM_PWMLOAD_LDOK(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_LDOK) = (v))
mbed_official	146:f64d43ff0c18	6564	#endif
mbed_official	146:f64d43ff0c18	6565	//@}
mbed_official	146:f64d43ff0c18	6566
mbed_official	146:f64d43ff0c18	6567	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	6568	// hw_ftm_t - module struct
mbed_official	146:f64d43ff0c18	6569	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	6570	/*!
mbed_official	146:f64d43ff0c18	6571	* @brief All FTM module registers.
mbed_official	146:f64d43ff0c18	6572	*/
mbed_official	146:f64d43ff0c18	6573	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	6574	#pragma pack(1)
mbed_official	146:f64d43ff0c18	6575	typedef struct _hw_ftm
mbed_official	146:f64d43ff0c18	6576	{
mbed_official	146:f64d43ff0c18	6577	__IO hw_ftm_sc_t SC; //!< [0x0] Status And Control
mbed_official	146:f64d43ff0c18	6578	__IO hw_ftm_cnt_t CNT; //!< [0x4] Counter
mbed_official	146:f64d43ff0c18	6579	__IO hw_ftm_mod_t MOD; //!< [0x8] Modulo
mbed_official	146:f64d43ff0c18	6580	struct {
mbed_official	146:f64d43ff0c18	6581	__IO hw_ftm_cnsc_t CnSC; //!< [0xC] Channel (n) Status And Control
mbed_official	146:f64d43ff0c18	6582	__IO hw_ftm_cnv_t CnV; //!< [0x10] Channel (n) Value
mbed_official	146:f64d43ff0c18	6583	} CONTROLS[8];
mbed_official	146:f64d43ff0c18	6584	__IO hw_ftm_cntin_t CNTIN; //!< [0x4C] Counter Initial Value
mbed_official	146:f64d43ff0c18	6585	__IO hw_ftm_status_t STATUS; //!< [0x50] Capture And Compare Status
mbed_official	146:f64d43ff0c18	6586	__IO hw_ftm_mode_t MODE; //!< [0x54] Features Mode Selection
mbed_official	146:f64d43ff0c18	6587	__IO hw_ftm_sync_t SYNC; //!< [0x58] Synchronization
mbed_official	146:f64d43ff0c18	6588	__IO hw_ftm_outinit_t OUTINIT; //!< [0x5C] Initial State For Channels Output
mbed_official	146:f64d43ff0c18	6589	__IO hw_ftm_outmask_t OUTMASK; //!< [0x60] Output Mask
mbed_official	146:f64d43ff0c18	6590	__IO hw_ftm_combine_t COMBINE; //!< [0x64] Function For Linked Channels
mbed_official	146:f64d43ff0c18	6591	__IO hw_ftm_deadtime_t DEADTIME; //!< [0x68] Deadtime Insertion Control
mbed_official	146:f64d43ff0c18	6592	__IO hw_ftm_exttrig_t EXTTRIG; //!< [0x6C] FTM External Trigger
mbed_official	146:f64d43ff0c18	6593	__IO hw_ftm_pol_t POL; //!< [0x70] Channels Polarity
mbed_official	146:f64d43ff0c18	6594	__IO hw_ftm_fms_t FMS; //!< [0x74] Fault Mode Status
mbed_official	146:f64d43ff0c18	6595	__IO hw_ftm_filter_t FILTER; //!< [0x78] Input Capture Filter Control
mbed_official	146:f64d43ff0c18	6596	__IO hw_ftm_fltctrl_t FLTCTRL; //!< [0x7C] Fault Control
mbed_official	146:f64d43ff0c18	6597	__IO hw_ftm_qdctrl_t QDCTRL; //!< [0x80] Quadrature Decoder Control And Status
mbed_official	146:f64d43ff0c18	6598	__IO hw_ftm_conf_t CONF; //!< [0x84] Configuration
mbed_official	146:f64d43ff0c18	6599	__IO hw_ftm_fltpol_t FLTPOL; //!< [0x88] FTM Fault Input Polarity
mbed_official	146:f64d43ff0c18	6600	__IO hw_ftm_synconf_t SYNCONF; //!< [0x8C] Synchronization Configuration
mbed_official	146:f64d43ff0c18	6601	__IO hw_ftm_invctrl_t INVCTRL; //!< [0x90] FTM Inverting Control
mbed_official	146:f64d43ff0c18	6602	__IO hw_ftm_swoctrl_t SWOCTRL; //!< [0x94] FTM Software Output Control
mbed_official	146:f64d43ff0c18	6603	__IO hw_ftm_pwmload_t PWMLOAD; //!< [0x98] FTM PWM Load
mbed_official	146:f64d43ff0c18	6604	} hw_ftm_t;
mbed_official	146:f64d43ff0c18	6605	#pragma pack()
mbed_official	146:f64d43ff0c18	6606
mbed_official	146:f64d43ff0c18	6607	//! @brief Macro to access all FTM registers.
mbed_official	146:f64d43ff0c18	6608	//! @param x FTM instance number.
mbed_official	146:f64d43ff0c18	6609	//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official	146:f64d43ff0c18	6610	//! use the '&' operator, like <code>&HW_FTM(0)</code>.
mbed_official	146:f64d43ff0c18	6611	#define HW_FTM(x) ((hw_ftm_t ) REGS_FTM_BASE(x))
mbed_official	146:f64d43ff0c18	6612	#endif
mbed_official	146:f64d43ff0c18	6613
mbed_official	146:f64d43ff0c18	6614	#endif // __HW_FTM_REGISTERS_H__
mbed_official	146:f64d43ff0c18	6615	// v22/130726/0.9
mbed_official	146:f64d43ff0c18	6616	// EOF