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Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_ewm.h@149:1fb5f62b92bd, 2014-04-03 (annotated)

Committer:
mbed_official
Date:
Thu Apr 03 11:45:06 2014 +0100
Revision:
149:1fb5f62b92bd
Parent:
targets/hal/TARGET_Freescale/TARGET_KSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_ewm.h@146:f64d43ff0c18 
Synchronized with git revision 220c0bb39ceee40016e1e86350c058963d01ed42



Full URL: https://github.com/mbedmicro/mbed/commit/220c0bb39ceee40016e1e86350c058963d01ed42/

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /*
mbed_official 146:f64d43ff0c18 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
mbed_official 146:f64d43ff0c18 3 * All rights reserved.
mbed_official 146:f64d43ff0c18 4 *
mbed_official 146:f64d43ff0c18 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official 146:f64d43ff0c18 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official 146:f64d43ff0c18 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
mbed_official 146:f64d43ff0c18 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
mbed_official 146:f64d43ff0c18 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
mbed_official 146:f64d43ff0c18 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 146:f64d43ff0c18 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 146:f64d43ff0c18 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
mbed_official 146:f64d43ff0c18 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
mbed_official 146:f64d43ff0c18 14 * OF SUCH DAMAGE.
mbed_official 146:f64d43ff0c18 15 */
mbed_official 146:f64d43ff0c18 16 /*
mbed_official 146:f64d43ff0c18 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 146:f64d43ff0c18 18 *
mbed_official 146:f64d43ff0c18 19 * This file was generated automatically and any changes may be lost.
mbed_official 146:f64d43ff0c18 20 */
mbed_official 146:f64d43ff0c18 21 #ifndef __HW_EWM_REGISTERS_H__
mbed_official 146:f64d43ff0c18 22 #define __HW_EWM_REGISTERS_H__
mbed_official 146:f64d43ff0c18 23
mbed_official 146:f64d43ff0c18 24 #include "regs.h"
mbed_official 146:f64d43ff0c18 25
mbed_official 146:f64d43ff0c18 26 /*
mbed_official 146:f64d43ff0c18 27 * MK64F12 EWM
mbed_official 146:f64d43ff0c18 28 *
mbed_official 146:f64d43ff0c18 29 * External Watchdog Monitor
mbed_official 146:f64d43ff0c18 30 *
mbed_official 146:f64d43ff0c18 31 * Registers defined in this header file:
mbed_official 146:f64d43ff0c18 32 * - HW_EWM_CTRL - Control Register
mbed_official 146:f64d43ff0c18 33 * - HW_EWM_SERV - Service Register
mbed_official 146:f64d43ff0c18 34 * - HW_EWM_CMPL - Compare Low Register
mbed_official 146:f64d43ff0c18 35 * - HW_EWM_CMPH - Compare High Register
mbed_official 146:f64d43ff0c18 36 *
mbed_official 146:f64d43ff0c18 37 * - hw_ewm_t - Struct containing all module registers.
mbed_official 146:f64d43ff0c18 38 */
mbed_official 146:f64d43ff0c18 39
mbed_official 146:f64d43ff0c18 40 //! @name Module base addresses
mbed_official 146:f64d43ff0c18 41 //@{
mbed_official 146:f64d43ff0c18 42 #ifndef REGS_EWM_BASE
mbed_official 146:f64d43ff0c18 43 #define HW_EWM_INSTANCE_COUNT (1U) //!< Number of instances of the EWM module.
mbed_official 146:f64d43ff0c18 44 #define REGS_EWM_BASE (0x40061000U) //!< Base address for EWM.
mbed_official 146:f64d43ff0c18 45 #endif
mbed_official 146:f64d43ff0c18 46 //@}
mbed_official 146:f64d43ff0c18 47
mbed_official 146:f64d43ff0c18 48 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 49 // HW_EWM_CTRL - Control Register
mbed_official 146:f64d43ff0c18 50 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 51
mbed_official 146:f64d43ff0c18 52 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 53 /*!
mbed_official 146:f64d43ff0c18 54 * @brief HW_EWM_CTRL - Control Register (RW)
mbed_official 146:f64d43ff0c18 55 *
mbed_official 146:f64d43ff0c18 56 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 57 *
mbed_official 146:f64d43ff0c18 58 * The CTRL register is cleared by any reset. INEN, ASSIN and EWMEN bits can be
mbed_official 146:f64d43ff0c18 59 * written once after a CPU reset. Modifying these bits more than once, generates
mbed_official 146:f64d43ff0c18 60 * a bus transfer error.
mbed_official 146:f64d43ff0c18 61 */
mbed_official 146:f64d43ff0c18 62 typedef union _hw_ewm_ctrl
mbed_official 146:f64d43ff0c18 63 {
mbed_official 146:f64d43ff0c18 64 uint8_t U;
mbed_official 146:f64d43ff0c18 65 struct _hw_ewm_ctrl_bitfields
mbed_official 146:f64d43ff0c18 66 {
mbed_official 146:f64d43ff0c18 67 uint8_t EWMEN : 1; //!< [0] EWM enable.
mbed_official 146:f64d43ff0c18 68 uint8_t ASSIN : 1; //!< [1] EWM_in's Assertion State Select.
mbed_official 146:f64d43ff0c18 69 uint8_t INEN : 1; //!< [2] Input Enable.
mbed_official 146:f64d43ff0c18 70 uint8_t INTEN : 1; //!< [3] Interrupt Enable.
mbed_official 146:f64d43ff0c18 71 uint8_t RESERVED0 : 4; //!< [7:4]
mbed_official 146:f64d43ff0c18 72 } B;
mbed_official 146:f64d43ff0c18 73 } hw_ewm_ctrl_t;
mbed_official 146:f64d43ff0c18 74 #endif
mbed_official 146:f64d43ff0c18 75
mbed_official 146:f64d43ff0c18 76 /*!
mbed_official 146:f64d43ff0c18 77 * @name Constants and macros for entire EWM_CTRL register
mbed_official 146:f64d43ff0c18 78 */
mbed_official 146:f64d43ff0c18 79 //@{
mbed_official 146:f64d43ff0c18 80 #define HW_EWM_CTRL_ADDR (REGS_EWM_BASE + 0x0U)
mbed_official 146:f64d43ff0c18 81
mbed_official 146:f64d43ff0c18 82 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 83 #define HW_EWM_CTRL (*(__IO hw_ewm_ctrl_t *) HW_EWM_CTRL_ADDR)
mbed_official 146:f64d43ff0c18 84 #define HW_EWM_CTRL_RD() (HW_EWM_CTRL.U)
mbed_official 146:f64d43ff0c18 85 #define HW_EWM_CTRL_WR(v) (HW_EWM_CTRL.U = (v))
mbed_official 146:f64d43ff0c18 86 #define HW_EWM_CTRL_SET(v) (HW_EWM_CTRL_WR(HW_EWM_CTRL_RD() | (v)))
mbed_official 146:f64d43ff0c18 87 #define HW_EWM_CTRL_CLR(v) (HW_EWM_CTRL_WR(HW_EWM_CTRL_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 88 #define HW_EWM_CTRL_TOG(v) (HW_EWM_CTRL_WR(HW_EWM_CTRL_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 89 #endif
mbed_official 146:f64d43ff0c18 90 //@}
mbed_official 146:f64d43ff0c18 91
mbed_official 146:f64d43ff0c18 92 /*
mbed_official 146:f64d43ff0c18 93 * Constants & macros for individual EWM_CTRL bitfields
mbed_official 146:f64d43ff0c18 94 */
mbed_official 146:f64d43ff0c18 95
mbed_official 146:f64d43ff0c18 96 /*!
mbed_official 146:f64d43ff0c18 97 * @name Register EWM_CTRL, field EWMEN[0] (RW)
mbed_official 146:f64d43ff0c18 98 *
mbed_official 146:f64d43ff0c18 99 * This bit when set, enables the EWM module. This resets the EWM counter to
mbed_official 146:f64d43ff0c18 100 * zero and deasserts the EWM_out signal. Clearing EWMEN bit disables the EWM, and
mbed_official 146:f64d43ff0c18 101 * therefore it cannot be enabled until a reset occurs, due to the write-once
mbed_official 146:f64d43ff0c18 102 * nature of this bit.
mbed_official 146:f64d43ff0c18 103 */
mbed_official 146:f64d43ff0c18 104 //@{
mbed_official 146:f64d43ff0c18 105 #define BP_EWM_CTRL_EWMEN (0U) //!< Bit position for EWM_CTRL_EWMEN.
mbed_official 146:f64d43ff0c18 106 #define BM_EWM_CTRL_EWMEN (0x01U) //!< Bit mask for EWM_CTRL_EWMEN.
mbed_official 146:f64d43ff0c18 107 #define BS_EWM_CTRL_EWMEN (1U) //!< Bit field size in bits for EWM_CTRL_EWMEN.
mbed_official 146:f64d43ff0c18 108
mbed_official 146:f64d43ff0c18 109 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 110 //! @brief Read current value of the EWM_CTRL_EWMEN field.
mbed_official 146:f64d43ff0c18 111 #define BR_EWM_CTRL_EWMEN (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_EWMEN))
mbed_official 146:f64d43ff0c18 112 #endif
mbed_official 146:f64d43ff0c18 113
mbed_official 146:f64d43ff0c18 114 //! @brief Format value for bitfield EWM_CTRL_EWMEN.
mbed_official 146:f64d43ff0c18 115 #define BF_EWM_CTRL_EWMEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CTRL_EWMEN), uint8_t) & BM_EWM_CTRL_EWMEN)
mbed_official 146:f64d43ff0c18 116
mbed_official 146:f64d43ff0c18 117 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 118 //! @brief Set the EWMEN field to a new value.
mbed_official 146:f64d43ff0c18 119 #define BW_EWM_CTRL_EWMEN(v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_EWMEN) = (v))
mbed_official 146:f64d43ff0c18 120 #endif
mbed_official 146:f64d43ff0c18 121 //@}
mbed_official 146:f64d43ff0c18 122
mbed_official 146:f64d43ff0c18 123 /*!
mbed_official 146:f64d43ff0c18 124 * @name Register EWM_CTRL, field ASSIN[1] (RW)
mbed_official 146:f64d43ff0c18 125 *
mbed_official 146:f64d43ff0c18 126 * Default assert state of the EWM_in signal is logic zero. Setting ASSIN bit
mbed_official 146:f64d43ff0c18 127 * inverts the assert state to a logic one.
mbed_official 146:f64d43ff0c18 128 */
mbed_official 146:f64d43ff0c18 129 //@{
mbed_official 146:f64d43ff0c18 130 #define BP_EWM_CTRL_ASSIN (1U) //!< Bit position for EWM_CTRL_ASSIN.
mbed_official 146:f64d43ff0c18 131 #define BM_EWM_CTRL_ASSIN (0x02U) //!< Bit mask for EWM_CTRL_ASSIN.
mbed_official 146:f64d43ff0c18 132 #define BS_EWM_CTRL_ASSIN (1U) //!< Bit field size in bits for EWM_CTRL_ASSIN.
mbed_official 146:f64d43ff0c18 133
mbed_official 146:f64d43ff0c18 134 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 135 //! @brief Read current value of the EWM_CTRL_ASSIN field.
mbed_official 146:f64d43ff0c18 136 #define BR_EWM_CTRL_ASSIN (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_ASSIN))
mbed_official 146:f64d43ff0c18 137 #endif
mbed_official 146:f64d43ff0c18 138
mbed_official 146:f64d43ff0c18 139 //! @brief Format value for bitfield EWM_CTRL_ASSIN.
mbed_official 146:f64d43ff0c18 140 #define BF_EWM_CTRL_ASSIN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CTRL_ASSIN), uint8_t) & BM_EWM_CTRL_ASSIN)
mbed_official 146:f64d43ff0c18 141
mbed_official 146:f64d43ff0c18 142 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 143 //! @brief Set the ASSIN field to a new value.
mbed_official 146:f64d43ff0c18 144 #define BW_EWM_CTRL_ASSIN(v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_ASSIN) = (v))
mbed_official 146:f64d43ff0c18 145 #endif
mbed_official 146:f64d43ff0c18 146 //@}
mbed_official 146:f64d43ff0c18 147
mbed_official 146:f64d43ff0c18 148 /*!
mbed_official 146:f64d43ff0c18 149 * @name Register EWM_CTRL, field INEN[2] (RW)
mbed_official 146:f64d43ff0c18 150 *
mbed_official 146:f64d43ff0c18 151 * This bit when set, enables the EWM_in port.
mbed_official 146:f64d43ff0c18 152 */
mbed_official 146:f64d43ff0c18 153 //@{
mbed_official 146:f64d43ff0c18 154 #define BP_EWM_CTRL_INEN (2U) //!< Bit position for EWM_CTRL_INEN.
mbed_official 146:f64d43ff0c18 155 #define BM_EWM_CTRL_INEN (0x04U) //!< Bit mask for EWM_CTRL_INEN.
mbed_official 146:f64d43ff0c18 156 #define BS_EWM_CTRL_INEN (1U) //!< Bit field size in bits for EWM_CTRL_INEN.
mbed_official 146:f64d43ff0c18 157
mbed_official 146:f64d43ff0c18 158 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 159 //! @brief Read current value of the EWM_CTRL_INEN field.
mbed_official 146:f64d43ff0c18 160 #define BR_EWM_CTRL_INEN (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_INEN))
mbed_official 146:f64d43ff0c18 161 #endif
mbed_official 146:f64d43ff0c18 162
mbed_official 146:f64d43ff0c18 163 //! @brief Format value for bitfield EWM_CTRL_INEN.
mbed_official 146:f64d43ff0c18 164 #define BF_EWM_CTRL_INEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CTRL_INEN), uint8_t) & BM_EWM_CTRL_INEN)
mbed_official 146:f64d43ff0c18 165
mbed_official 146:f64d43ff0c18 166 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 167 //! @brief Set the INEN field to a new value.
mbed_official 146:f64d43ff0c18 168 #define BW_EWM_CTRL_INEN(v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_INEN) = (v))
mbed_official 146:f64d43ff0c18 169 #endif
mbed_official 146:f64d43ff0c18 170 //@}
mbed_official 146:f64d43ff0c18 171
mbed_official 146:f64d43ff0c18 172 /*!
mbed_official 146:f64d43ff0c18 173 * @name Register EWM_CTRL, field INTEN[3] (RW)
mbed_official 146:f64d43ff0c18 174 *
mbed_official 146:f64d43ff0c18 175 * This bit when set and EWM_out is asserted, an interrupt request is generated.
mbed_official 146:f64d43ff0c18 176 * To de-assert interrupt request, user should clear this bit by writing 0.
mbed_official 146:f64d43ff0c18 177 */
mbed_official 146:f64d43ff0c18 178 //@{
mbed_official 146:f64d43ff0c18 179 #define BP_EWM_CTRL_INTEN (3U) //!< Bit position for EWM_CTRL_INTEN.
mbed_official 146:f64d43ff0c18 180 #define BM_EWM_CTRL_INTEN (0x08U) //!< Bit mask for EWM_CTRL_INTEN.
mbed_official 146:f64d43ff0c18 181 #define BS_EWM_CTRL_INTEN (1U) //!< Bit field size in bits for EWM_CTRL_INTEN.
mbed_official 146:f64d43ff0c18 182
mbed_official 146:f64d43ff0c18 183 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 184 //! @brief Read current value of the EWM_CTRL_INTEN field.
mbed_official 146:f64d43ff0c18 185 #define BR_EWM_CTRL_INTEN (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_INTEN))
mbed_official 146:f64d43ff0c18 186 #endif
mbed_official 146:f64d43ff0c18 187
mbed_official 146:f64d43ff0c18 188 //! @brief Format value for bitfield EWM_CTRL_INTEN.
mbed_official 146:f64d43ff0c18 189 #define BF_EWM_CTRL_INTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CTRL_INTEN), uint8_t) & BM_EWM_CTRL_INTEN)
mbed_official 146:f64d43ff0c18 190
mbed_official 146:f64d43ff0c18 191 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 192 //! @brief Set the INTEN field to a new value.
mbed_official 146:f64d43ff0c18 193 #define BW_EWM_CTRL_INTEN(v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_INTEN) = (v))
mbed_official 146:f64d43ff0c18 194 #endif
mbed_official 146:f64d43ff0c18 195 //@}
mbed_official 146:f64d43ff0c18 196
mbed_official 146:f64d43ff0c18 197 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 198 // HW_EWM_SERV - Service Register
mbed_official 146:f64d43ff0c18 199 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 200
mbed_official 146:f64d43ff0c18 201 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 202 /*!
mbed_official 146:f64d43ff0c18 203 * @brief HW_EWM_SERV - Service Register (WORZ)
mbed_official 146:f64d43ff0c18 204 *
mbed_official 146:f64d43ff0c18 205 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 206 *
mbed_official 146:f64d43ff0c18 207 * The SERV register provides the interface from the CPU to the EWM module. It
mbed_official 146:f64d43ff0c18 208 * is write-only and reads of this register return zero.
mbed_official 146:f64d43ff0c18 209 */
mbed_official 146:f64d43ff0c18 210 typedef union _hw_ewm_serv
mbed_official 146:f64d43ff0c18 211 {
mbed_official 146:f64d43ff0c18 212 uint8_t U;
mbed_official 146:f64d43ff0c18 213 struct _hw_ewm_serv_bitfields
mbed_official 146:f64d43ff0c18 214 {
mbed_official 146:f64d43ff0c18 215 uint8_t SERVICE : 8; //!< [7:0]
mbed_official 146:f64d43ff0c18 216 } B;
mbed_official 146:f64d43ff0c18 217 } hw_ewm_serv_t;
mbed_official 146:f64d43ff0c18 218 #endif
mbed_official 146:f64d43ff0c18 219
mbed_official 146:f64d43ff0c18 220 /*!
mbed_official 146:f64d43ff0c18 221 * @name Constants and macros for entire EWM_SERV register
mbed_official 146:f64d43ff0c18 222 */
mbed_official 146:f64d43ff0c18 223 //@{
mbed_official 146:f64d43ff0c18 224 #define HW_EWM_SERV_ADDR (REGS_EWM_BASE + 0x1U)
mbed_official 146:f64d43ff0c18 225
mbed_official 146:f64d43ff0c18 226 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 227 #define HW_EWM_SERV (*(__O hw_ewm_serv_t *) HW_EWM_SERV_ADDR)
mbed_official 146:f64d43ff0c18 228 #define HW_EWM_SERV_RD() (HW_EWM_SERV.U)
mbed_official 146:f64d43ff0c18 229 #define HW_EWM_SERV_WR(v) (HW_EWM_SERV.U = (v))
mbed_official 146:f64d43ff0c18 230 #endif
mbed_official 146:f64d43ff0c18 231 //@}
mbed_official 146:f64d43ff0c18 232
mbed_official 146:f64d43ff0c18 233 /*
mbed_official 146:f64d43ff0c18 234 * Constants & macros for individual EWM_SERV bitfields
mbed_official 146:f64d43ff0c18 235 */
mbed_official 146:f64d43ff0c18 236
mbed_official 146:f64d43ff0c18 237 /*!
mbed_official 146:f64d43ff0c18 238 * @name Register EWM_SERV, field SERVICE[7:0] (WORZ)
mbed_official 146:f64d43ff0c18 239 *
mbed_official 146:f64d43ff0c18 240 * The EWM service mechanism requires the CPU to write two values to the SERV
mbed_official 146:f64d43ff0c18 241 * register: a first data byte of 0xB4, followed by a second data byte of 0x2C. The
mbed_official 146:f64d43ff0c18 242 * EWM service is illegal if either of the following conditions is true. The
mbed_official 146:f64d43ff0c18 243 * first or second data byte is not written correctly. The second data byte is not
mbed_official 146:f64d43ff0c18 244 * written within a fixed number of peripheral bus cycles of the first data byte.
mbed_official 146:f64d43ff0c18 245 * This fixed number of cycles is called EWM_service_time.
mbed_official 146:f64d43ff0c18 246 */
mbed_official 146:f64d43ff0c18 247 //@{
mbed_official 146:f64d43ff0c18 248 #define BP_EWM_SERV_SERVICE (0U) //!< Bit position for EWM_SERV_SERVICE.
mbed_official 146:f64d43ff0c18 249 #define BM_EWM_SERV_SERVICE (0xFFU) //!< Bit mask for EWM_SERV_SERVICE.
mbed_official 146:f64d43ff0c18 250 #define BS_EWM_SERV_SERVICE (8U) //!< Bit field size in bits for EWM_SERV_SERVICE.
mbed_official 146:f64d43ff0c18 251
mbed_official 146:f64d43ff0c18 252 //! @brief Format value for bitfield EWM_SERV_SERVICE.
mbed_official 146:f64d43ff0c18 253 #define BF_EWM_SERV_SERVICE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_SERV_SERVICE), uint8_t) & BM_EWM_SERV_SERVICE)
mbed_official 146:f64d43ff0c18 254
mbed_official 146:f64d43ff0c18 255 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 256 //! @brief Set the SERVICE field to a new value.
mbed_official 146:f64d43ff0c18 257 #define BW_EWM_SERV_SERVICE(v) (HW_EWM_SERV_WR(v))
mbed_official 146:f64d43ff0c18 258 #endif
mbed_official 146:f64d43ff0c18 259 //@}
mbed_official 146:f64d43ff0c18 260
mbed_official 146:f64d43ff0c18 261 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 262 // HW_EWM_CMPL - Compare Low Register
mbed_official 146:f64d43ff0c18 263 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 264
mbed_official 146:f64d43ff0c18 265 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 266 /*!
mbed_official 146:f64d43ff0c18 267 * @brief HW_EWM_CMPL - Compare Low Register (RW)
mbed_official 146:f64d43ff0c18 268 *
mbed_official 146:f64d43ff0c18 269 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 270 *
mbed_official 146:f64d43ff0c18 271 * The CMPL register is reset to zero after a CPU reset. This provides no
mbed_official 146:f64d43ff0c18 272 * minimum time for the CPU to service the EWM counter. This register can be written
mbed_official 146:f64d43ff0c18 273 * only once after a CPU reset. Writing this register more than once generates a
mbed_official 146:f64d43ff0c18 274 * bus transfer error.
mbed_official 146:f64d43ff0c18 275 */
mbed_official 146:f64d43ff0c18 276 typedef union _hw_ewm_cmpl
mbed_official 146:f64d43ff0c18 277 {
mbed_official 146:f64d43ff0c18 278 uint8_t U;
mbed_official 146:f64d43ff0c18 279 struct _hw_ewm_cmpl_bitfields
mbed_official 146:f64d43ff0c18 280 {
mbed_official 146:f64d43ff0c18 281 uint8_t COMPAREL : 8; //!< [7:0]
mbed_official 146:f64d43ff0c18 282 } B;
mbed_official 146:f64d43ff0c18 283 } hw_ewm_cmpl_t;
mbed_official 146:f64d43ff0c18 284 #endif
mbed_official 146:f64d43ff0c18 285
mbed_official 146:f64d43ff0c18 286 /*!
mbed_official 146:f64d43ff0c18 287 * @name Constants and macros for entire EWM_CMPL register
mbed_official 146:f64d43ff0c18 288 */
mbed_official 146:f64d43ff0c18 289 //@{
mbed_official 146:f64d43ff0c18 290 #define HW_EWM_CMPL_ADDR (REGS_EWM_BASE + 0x2U)
mbed_official 146:f64d43ff0c18 291
mbed_official 146:f64d43ff0c18 292 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 293 #define HW_EWM_CMPL (*(__IO hw_ewm_cmpl_t *) HW_EWM_CMPL_ADDR)
mbed_official 146:f64d43ff0c18 294 #define HW_EWM_CMPL_RD() (HW_EWM_CMPL.U)
mbed_official 146:f64d43ff0c18 295 #define HW_EWM_CMPL_WR(v) (HW_EWM_CMPL.U = (v))
mbed_official 146:f64d43ff0c18 296 #define HW_EWM_CMPL_SET(v) (HW_EWM_CMPL_WR(HW_EWM_CMPL_RD() | (v)))
mbed_official 146:f64d43ff0c18 297 #define HW_EWM_CMPL_CLR(v) (HW_EWM_CMPL_WR(HW_EWM_CMPL_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 298 #define HW_EWM_CMPL_TOG(v) (HW_EWM_CMPL_WR(HW_EWM_CMPL_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 299 #endif
mbed_official 146:f64d43ff0c18 300 //@}
mbed_official 146:f64d43ff0c18 301
mbed_official 146:f64d43ff0c18 302 /*
mbed_official 146:f64d43ff0c18 303 * Constants & macros for individual EWM_CMPL bitfields
mbed_official 146:f64d43ff0c18 304 */
mbed_official 146:f64d43ff0c18 305
mbed_official 146:f64d43ff0c18 306 /*!
mbed_official 146:f64d43ff0c18 307 * @name Register EWM_CMPL, field COMPAREL[7:0] (RW)
mbed_official 146:f64d43ff0c18 308 *
mbed_official 146:f64d43ff0c18 309 * To prevent runaway code from changing this field, software should write to
mbed_official 146:f64d43ff0c18 310 * this field after a CPU reset even if the (default) minimum service time is
mbed_official 146:f64d43ff0c18 311 * required.
mbed_official 146:f64d43ff0c18 312 */
mbed_official 146:f64d43ff0c18 313 //@{
mbed_official 146:f64d43ff0c18 314 #define BP_EWM_CMPL_COMPAREL (0U) //!< Bit position for EWM_CMPL_COMPAREL.
mbed_official 146:f64d43ff0c18 315 #define BM_EWM_CMPL_COMPAREL (0xFFU) //!< Bit mask for EWM_CMPL_COMPAREL.
mbed_official 146:f64d43ff0c18 316 #define BS_EWM_CMPL_COMPAREL (8U) //!< Bit field size in bits for EWM_CMPL_COMPAREL.
mbed_official 146:f64d43ff0c18 317
mbed_official 146:f64d43ff0c18 318 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 319 //! @brief Read current value of the EWM_CMPL_COMPAREL field.
mbed_official 146:f64d43ff0c18 320 #define BR_EWM_CMPL_COMPAREL (HW_EWM_CMPL.U)
mbed_official 146:f64d43ff0c18 321 #endif
mbed_official 146:f64d43ff0c18 322
mbed_official 146:f64d43ff0c18 323 //! @brief Format value for bitfield EWM_CMPL_COMPAREL.
mbed_official 146:f64d43ff0c18 324 #define BF_EWM_CMPL_COMPAREL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CMPL_COMPAREL), uint8_t) & BM_EWM_CMPL_COMPAREL)
mbed_official 146:f64d43ff0c18 325
mbed_official 146:f64d43ff0c18 326 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 327 //! @brief Set the COMPAREL field to a new value.
mbed_official 146:f64d43ff0c18 328 #define BW_EWM_CMPL_COMPAREL(v) (HW_EWM_CMPL_WR(v))
mbed_official 146:f64d43ff0c18 329 #endif
mbed_official 146:f64d43ff0c18 330 //@}
mbed_official 146:f64d43ff0c18 331
mbed_official 146:f64d43ff0c18 332 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 333 // HW_EWM_CMPH - Compare High Register
mbed_official 146:f64d43ff0c18 334 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 335
mbed_official 146:f64d43ff0c18 336 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 337 /*!
mbed_official 146:f64d43ff0c18 338 * @brief HW_EWM_CMPH - Compare High Register (RW)
mbed_official 146:f64d43ff0c18 339 *
mbed_official 146:f64d43ff0c18 340 * Reset value: 0xFFU
mbed_official 146:f64d43ff0c18 341 *
mbed_official 146:f64d43ff0c18 342 * The CMPH register is reset to 0xFF after a CPU reset. This provides a maximum
mbed_official 146:f64d43ff0c18 343 * of 256 clocks time, for the CPU to service the EWM counter. This register can
mbed_official 146:f64d43ff0c18 344 * be written only once after a CPU reset. Writing this register more than once
mbed_official 146:f64d43ff0c18 345 * generates a bus transfer error. The valid values for CMPH are up to 0xFE
mbed_official 146:f64d43ff0c18 346 * because the EWM counter never expires when CMPH = 0xFF. The expiration happens only
mbed_official 146:f64d43ff0c18 347 * if EWM counter is greater than CMPH.
mbed_official 146:f64d43ff0c18 348 */
mbed_official 146:f64d43ff0c18 349 typedef union _hw_ewm_cmph
mbed_official 146:f64d43ff0c18 350 {
mbed_official 146:f64d43ff0c18 351 uint8_t U;
mbed_official 146:f64d43ff0c18 352 struct _hw_ewm_cmph_bitfields
mbed_official 146:f64d43ff0c18 353 {
mbed_official 146:f64d43ff0c18 354 uint8_t COMPAREH : 8; //!< [7:0]
mbed_official 146:f64d43ff0c18 355 } B;
mbed_official 146:f64d43ff0c18 356 } hw_ewm_cmph_t;
mbed_official 146:f64d43ff0c18 357 #endif
mbed_official 146:f64d43ff0c18 358
mbed_official 146:f64d43ff0c18 359 /*!
mbed_official 146:f64d43ff0c18 360 * @name Constants and macros for entire EWM_CMPH register
mbed_official 146:f64d43ff0c18 361 */
mbed_official 146:f64d43ff0c18 362 //@{
mbed_official 146:f64d43ff0c18 363 #define HW_EWM_CMPH_ADDR (REGS_EWM_BASE + 0x3U)
mbed_official 146:f64d43ff0c18 364
mbed_official 146:f64d43ff0c18 365 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 366 #define HW_EWM_CMPH (*(__IO hw_ewm_cmph_t *) HW_EWM_CMPH_ADDR)
mbed_official 146:f64d43ff0c18 367 #define HW_EWM_CMPH_RD() (HW_EWM_CMPH.U)
mbed_official 146:f64d43ff0c18 368 #define HW_EWM_CMPH_WR(v) (HW_EWM_CMPH.U = (v))
mbed_official 146:f64d43ff0c18 369 #define HW_EWM_CMPH_SET(v) (HW_EWM_CMPH_WR(HW_EWM_CMPH_RD() | (v)))
mbed_official 146:f64d43ff0c18 370 #define HW_EWM_CMPH_CLR(v) (HW_EWM_CMPH_WR(HW_EWM_CMPH_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 371 #define HW_EWM_CMPH_TOG(v) (HW_EWM_CMPH_WR(HW_EWM_CMPH_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 372 #endif
mbed_official 146:f64d43ff0c18 373 //@}
mbed_official 146:f64d43ff0c18 374
mbed_official 146:f64d43ff0c18 375 /*
mbed_official 146:f64d43ff0c18 376 * Constants & macros for individual EWM_CMPH bitfields
mbed_official 146:f64d43ff0c18 377 */
mbed_official 146:f64d43ff0c18 378
mbed_official 146:f64d43ff0c18 379 /*!
mbed_official 146:f64d43ff0c18 380 * @name Register EWM_CMPH, field COMPAREH[7:0] (RW)
mbed_official 146:f64d43ff0c18 381 *
mbed_official 146:f64d43ff0c18 382 * To prevent runaway code from changing this field, software should write to
mbed_official 146:f64d43ff0c18 383 * this field after a CPU reset even if the (default) maximum service time is
mbed_official 146:f64d43ff0c18 384 * required.
mbed_official 146:f64d43ff0c18 385 */
mbed_official 146:f64d43ff0c18 386 //@{
mbed_official 146:f64d43ff0c18 387 #define BP_EWM_CMPH_COMPAREH (0U) //!< Bit position for EWM_CMPH_COMPAREH.
mbed_official 146:f64d43ff0c18 388 #define BM_EWM_CMPH_COMPAREH (0xFFU) //!< Bit mask for EWM_CMPH_COMPAREH.
mbed_official 146:f64d43ff0c18 389 #define BS_EWM_CMPH_COMPAREH (8U) //!< Bit field size in bits for EWM_CMPH_COMPAREH.
mbed_official 146:f64d43ff0c18 390
mbed_official 146:f64d43ff0c18 391 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 392 //! @brief Read current value of the EWM_CMPH_COMPAREH field.
mbed_official 146:f64d43ff0c18 393 #define BR_EWM_CMPH_COMPAREH (HW_EWM_CMPH.U)
mbed_official 146:f64d43ff0c18 394 #endif
mbed_official 146:f64d43ff0c18 395
mbed_official 146:f64d43ff0c18 396 //! @brief Format value for bitfield EWM_CMPH_COMPAREH.
mbed_official 146:f64d43ff0c18 397 #define BF_EWM_CMPH_COMPAREH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CMPH_COMPAREH), uint8_t) & BM_EWM_CMPH_COMPAREH)
mbed_official 146:f64d43ff0c18 398
mbed_official 146:f64d43ff0c18 399 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 400 //! @brief Set the COMPAREH field to a new value.
mbed_official 146:f64d43ff0c18 401 #define BW_EWM_CMPH_COMPAREH(v) (HW_EWM_CMPH_WR(v))
mbed_official 146:f64d43ff0c18 402 #endif
mbed_official 146:f64d43ff0c18 403 //@}
mbed_official 146:f64d43ff0c18 404
mbed_official 146:f64d43ff0c18 405 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 406 // hw_ewm_t - module struct
mbed_official 146:f64d43ff0c18 407 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 408 /*!
mbed_official 146:f64d43ff0c18 409 * @brief All EWM module registers.
mbed_official 146:f64d43ff0c18 410 */
mbed_official 146:f64d43ff0c18 411 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 412 #pragma pack(1)
mbed_official 146:f64d43ff0c18 413 typedef struct _hw_ewm
mbed_official 146:f64d43ff0c18 414 {
mbed_official 146:f64d43ff0c18 415 __IO hw_ewm_ctrl_t CTRL; //!< [0x0] Control Register
mbed_official 146:f64d43ff0c18 416 __O hw_ewm_serv_t SERV; //!< [0x1] Service Register
mbed_official 146:f64d43ff0c18 417 __IO hw_ewm_cmpl_t CMPL; //!< [0x2] Compare Low Register
mbed_official 146:f64d43ff0c18 418 __IO hw_ewm_cmph_t CMPH; //!< [0x3] Compare High Register
mbed_official 146:f64d43ff0c18 419 } hw_ewm_t;
mbed_official 146:f64d43ff0c18 420 #pragma pack()
mbed_official 146:f64d43ff0c18 421
mbed_official 146:f64d43ff0c18 422 //! @brief Macro to access all EWM registers.
mbed_official 146:f64d43ff0c18 423 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 146:f64d43ff0c18 424 //! use the '&' operator, like <code>&HW_EWM</code>.
mbed_official 146:f64d43ff0c18 425 #define HW_EWM (*(hw_ewm_t *) REGS_EWM_BASE)
mbed_official 146:f64d43ff0c18 426 #endif
mbed_official 146:f64d43ff0c18 427
mbed_official 146:f64d43ff0c18 428 #endif // __HW_EWM_REGISTERS_H__
mbed_official 146:f64d43ff0c18 429 // v22/130726/0.9
mbed_official 146:f64d43ff0c18 430 // EOF