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targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_cau.h@149:1fb5f62b92bd, 2014-04-03 (annotated)

Committer:: mbed_official
Date:: Thu Apr 03 11:45:06 2014 +0100
Revision:: 149:1fb5f62b92bd
Parent:: targets/hal/TARGET_Freescale/TARGET_KSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_cau.h@146:f64d43ff0c18

Synchronized with git revision 220c0bb39ceee40016e1e86350c058963d01ed42



Full URL: https://github.com/mbedmicro/mbed/commit/220c0bb39ceee40016e1e86350c058963d01ed42/

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	146:f64d43ff0c18	1	/*
mbed_official	146:f64d43ff0c18	2	* Copyright (c) 2014, Freescale Semiconductor, Inc.
mbed_official	146:f64d43ff0c18	3	* All rights reserved.
mbed_official	146:f64d43ff0c18	4	*
mbed_official	146:f64d43ff0c18	5	* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official	146:f64d43ff0c18	6	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official	146:f64d43ff0c18	7	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
mbed_official	146:f64d43ff0c18	8	* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
mbed_official	146:f64d43ff0c18	9	* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
mbed_official	146:f64d43ff0c18	10	* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official	146:f64d43ff0c18	11	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official	146:f64d43ff0c18	12	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
mbed_official	146:f64d43ff0c18	13	* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
mbed_official	146:f64d43ff0c18	14	* OF SUCH DAMAGE.
mbed_official	146:f64d43ff0c18	15	*/
mbed_official	146:f64d43ff0c18	16	/*
mbed_official	146:f64d43ff0c18	17	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official	146:f64d43ff0c18	18	*
mbed_official	146:f64d43ff0c18	19	* This file was generated automatically and any changes may be lost.
mbed_official	146:f64d43ff0c18	20	*/
mbed_official	146:f64d43ff0c18	21	#ifndef __HW_CAU_REGISTERS_H__
mbed_official	146:f64d43ff0c18	22	#define __HW_CAU_REGISTERS_H__
mbed_official	146:f64d43ff0c18	23
mbed_official	146:f64d43ff0c18	24	#include "regs.h"
mbed_official	146:f64d43ff0c18	25
mbed_official	146:f64d43ff0c18	26	/*
mbed_official	146:f64d43ff0c18	27	* MK64F12 CAU
mbed_official	146:f64d43ff0c18	28	*
mbed_official	146:f64d43ff0c18	29	* Memory Mapped Cryptographic Acceleration Unit (MMCAU)
mbed_official	146:f64d43ff0c18	30	*
mbed_official	146:f64d43ff0c18	31	* Registers defined in this header file:
mbed_official	146:f64d43ff0c18	32	* - HW_CAU_DIRECT - Direct access register 0
mbed_official	146:f64d43ff0c18	33	* - HW_CAU_LDR_CASR - Status register - Load Register command
mbed_official	146:f64d43ff0c18	34	* - HW_CAU_LDR_CAA - Accumulator register - Load Register command
mbed_official	146:f64d43ff0c18	35	* - HW_CAU_LDR_CA - General Purpose Register 0 - Load Register command
mbed_official	146:f64d43ff0c18	36	* - HW_CAU_STR_CASR - Status register - Store Register command
mbed_official	146:f64d43ff0c18	37	* - HW_CAU_STR_CAA - Accumulator register - Store Register command
mbed_official	146:f64d43ff0c18	38	* - HW_CAU_STR_CA - General Purpose Register 0 - Store Register command
mbed_official	146:f64d43ff0c18	39	* - HW_CAU_ADR_CASR - Status register - Add Register command
mbed_official	146:f64d43ff0c18	40	* - HW_CAU_ADR_CAA - Accumulator register - Add to register command
mbed_official	146:f64d43ff0c18	41	* - HW_CAU_ADR_CA - General Purpose Register 0 - Add to register command
mbed_official	146:f64d43ff0c18	42	* - HW_CAU_RADR_CASR - Status register - Reverse and Add to Register command
mbed_official	146:f64d43ff0c18	43	* - HW_CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command
mbed_official	146:f64d43ff0c18	44	* - HW_CAU_RADR_CA - General Purpose Register 0 - Reverse and Add to Register command
mbed_official	146:f64d43ff0c18	45	* - HW_CAU_XOR_CASR - Status register - Exclusive Or command
mbed_official	146:f64d43ff0c18	46	* - HW_CAU_XOR_CAA - Accumulator register - Exclusive Or command
mbed_official	146:f64d43ff0c18	47	* - HW_CAU_XOR_CA - General Purpose Register 0 - Exclusive Or command
mbed_official	146:f64d43ff0c18	48	* - HW_CAU_ROTL_CASR - Status register - Rotate Left command
mbed_official	146:f64d43ff0c18	49	* - HW_CAU_ROTL_CAA - Accumulator register - Rotate Left command
mbed_official	146:f64d43ff0c18	50	* - HW_CAU_ROTL_CA - General Purpose Register 0 - Rotate Left command
mbed_official	146:f64d43ff0c18	51	* - HW_CAU_AESC_CASR - Status register - AES Column Operation command
mbed_official	146:f64d43ff0c18	52	* - HW_CAU_AESC_CAA - Accumulator register - AES Column Operation command
mbed_official	146:f64d43ff0c18	53	* - HW_CAU_AESC_CA - General Purpose Register 0 - AES Column Operation command
mbed_official	146:f64d43ff0c18	54	* - HW_CAU_AESIC_CASR - Status register - AES Inverse Column Operation command
mbed_official	146:f64d43ff0c18	55	* - HW_CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command
mbed_official	146:f64d43ff0c18	56	* - HW_CAU_AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command
mbed_official	146:f64d43ff0c18	57	*
mbed_official	146:f64d43ff0c18	58	* - hw_cau_t - Struct containing all module registers.
mbed_official	146:f64d43ff0c18	59	*/
mbed_official	146:f64d43ff0c18	60
mbed_official	146:f64d43ff0c18	61	//! @name Module base addresses
mbed_official	146:f64d43ff0c18	62	//@{
mbed_official	146:f64d43ff0c18	63	#ifndef REGS_CAU_BASE
mbed_official	146:f64d43ff0c18	64	#define HW_CAU_INSTANCE_COUNT (1U) //!< Number of instances of the CAU module.
mbed_official	146:f64d43ff0c18	65	#define REGS_CAU_BASE (0xE0081000U) //!< Base address for CAU.
mbed_official	146:f64d43ff0c18	66	#endif
mbed_official	146:f64d43ff0c18	67	//@}
mbed_official	146:f64d43ff0c18	68
mbed_official	146:f64d43ff0c18	69	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	70	// HW_CAU_DIRECT - Direct access register 0
mbed_official	146:f64d43ff0c18	71	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	72
mbed_official	146:f64d43ff0c18	73	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	74	/*!
mbed_official	146:f64d43ff0c18	75	* @brief HW_CAU_DIRECT - Direct access register 0 (WO)
mbed_official	146:f64d43ff0c18	76	*
mbed_official	146:f64d43ff0c18	77	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	78	*/
mbed_official	146:f64d43ff0c18	79	typedef union _hw_cau_direct
mbed_official	146:f64d43ff0c18	80	{
mbed_official	146:f64d43ff0c18	81	uint32_t U;
mbed_official	146:f64d43ff0c18	82	struct _hw_cau_direct_bitfields
mbed_official	146:f64d43ff0c18	83	{
mbed_official	146:f64d43ff0c18	84	uint32_t RESERVED0 : 32; //!< [31:0]
mbed_official	146:f64d43ff0c18	85	} B;
mbed_official	146:f64d43ff0c18	86	} hw_cau_direct_t;
mbed_official	146:f64d43ff0c18	87	#endif
mbed_official	146:f64d43ff0c18	88
mbed_official	146:f64d43ff0c18	89	/*!
mbed_official	146:f64d43ff0c18	90	* @name Constants and macros for entire CAU_DIRECT register
mbed_official	146:f64d43ff0c18	91	*/
mbed_official	146:f64d43ff0c18	92	//@{
mbed_official	146:f64d43ff0c18	93	#define HW_CAU_DIRECT_COUNT (16U)
mbed_official	146:f64d43ff0c18	94
mbed_official	146:f64d43ff0c18	95	#define HW_CAU_DIRECT_ADDR(n) (REGS_CAU_BASE + 0x0U + (0x4U * n))
mbed_official	146:f64d43ff0c18	96
mbed_official	146:f64d43ff0c18	97	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	98	#define HW_CAU_DIRECT(n) ((__O hw_cau_direct_t ) HW_CAU_DIRECT_ADDR(n))
mbed_official	146:f64d43ff0c18	99	#define HW_CAU_DIRECT_WR(n, v) (HW_CAU_DIRECT(n).U = (v))
mbed_official	146:f64d43ff0c18	100	#endif
mbed_official	146:f64d43ff0c18	101	//@}
mbed_official	146:f64d43ff0c18	102
mbed_official	146:f64d43ff0c18	103	/*
mbed_official	146:f64d43ff0c18	104	* Constants & macros for individual CAU_DIRECT bitfields
mbed_official	146:f64d43ff0c18	105	*/
mbed_official	146:f64d43ff0c18	106
mbed_official	146:f64d43ff0c18	107	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	108	// HW_CAU_LDR_CASR - Status register - Load Register command
mbed_official	146:f64d43ff0c18	109	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	110
mbed_official	146:f64d43ff0c18	111	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	112	/*!
mbed_official	146:f64d43ff0c18	113	* @brief HW_CAU_LDR_CASR - Status register - Load Register command (WO)
mbed_official	146:f64d43ff0c18	114	*
mbed_official	146:f64d43ff0c18	115	* Reset value: 0x20000000U
mbed_official	146:f64d43ff0c18	116	*/
mbed_official	146:f64d43ff0c18	117	typedef union _hw_cau_ldr_casr
mbed_official	146:f64d43ff0c18	118	{
mbed_official	146:f64d43ff0c18	119	uint32_t U;
mbed_official	146:f64d43ff0c18	120	struct _hw_cau_ldr_casr_bitfields
mbed_official	146:f64d43ff0c18	121	{
mbed_official	146:f64d43ff0c18	122	uint32_t IC : 1; //!< [0]
mbed_official	146:f64d43ff0c18	123	uint32_t DPE : 1; //!< [1]
mbed_official	146:f64d43ff0c18	124	uint32_t RESERVED0 : 26; //!< [27:2]
mbed_official	146:f64d43ff0c18	125	uint32_t VER : 4; //!< [31:28] CAU version
mbed_official	146:f64d43ff0c18	126	} B;
mbed_official	146:f64d43ff0c18	127	} hw_cau_ldr_casr_t;
mbed_official	146:f64d43ff0c18	128	#endif
mbed_official	146:f64d43ff0c18	129
mbed_official	146:f64d43ff0c18	130	/*!
mbed_official	146:f64d43ff0c18	131	* @name Constants and macros for entire CAU_LDR_CASR register
mbed_official	146:f64d43ff0c18	132	*/
mbed_official	146:f64d43ff0c18	133	//@{
mbed_official	146:f64d43ff0c18	134	#define HW_CAU_LDR_CASR_ADDR (REGS_CAU_BASE + 0x840U)
mbed_official	146:f64d43ff0c18	135
mbed_official	146:f64d43ff0c18	136	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	137	#define HW_CAU_LDR_CASR ((__O hw_cau_ldr_casr_t ) HW_CAU_LDR_CASR_ADDR)
mbed_official	146:f64d43ff0c18	138	#define HW_CAU_LDR_CASR_WR(v) (HW_CAU_LDR_CASR.U = (v))
mbed_official	146:f64d43ff0c18	139	#endif
mbed_official	146:f64d43ff0c18	140	//@}
mbed_official	146:f64d43ff0c18	141
mbed_official	146:f64d43ff0c18	142	/*
mbed_official	146:f64d43ff0c18	143	* Constants & macros for individual CAU_LDR_CASR bitfields
mbed_official	146:f64d43ff0c18	144	*/
mbed_official	146:f64d43ff0c18	145
mbed_official	146:f64d43ff0c18	146	/*!
mbed_official	146:f64d43ff0c18	147	* @name Register CAU_LDR_CASR, field IC[0] (WO)
mbed_official	146:f64d43ff0c18	148	*
mbed_official	146:f64d43ff0c18	149	* Values:
mbed_official	146:f64d43ff0c18	150	* - 0 - No illegal commands issued
mbed_official	146:f64d43ff0c18	151	* - 1 - Illegal command issued
mbed_official	146:f64d43ff0c18	152	*/
mbed_official	146:f64d43ff0c18	153	//@{
mbed_official	146:f64d43ff0c18	154	#define BP_CAU_LDR_CASR_IC (0U) //!< Bit position for CAU_LDR_CASR_IC.
mbed_official	146:f64d43ff0c18	155	#define BM_CAU_LDR_CASR_IC (0x00000001U) //!< Bit mask for CAU_LDR_CASR_IC.
mbed_official	146:f64d43ff0c18	156	#define BS_CAU_LDR_CASR_IC (1U) //!< Bit field size in bits for CAU_LDR_CASR_IC.
mbed_official	146:f64d43ff0c18	157
mbed_official	146:f64d43ff0c18	158	//! @brief Format value for bitfield CAU_LDR_CASR_IC.
mbed_official	146:f64d43ff0c18	159	#define BF_CAU_LDR_CASR_IC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_LDR_CASR_IC), uint32_t) & BM_CAU_LDR_CASR_IC)
mbed_official	146:f64d43ff0c18	160	//@}
mbed_official	146:f64d43ff0c18	161
mbed_official	146:f64d43ff0c18	162	/*!
mbed_official	146:f64d43ff0c18	163	* @name Register CAU_LDR_CASR, field DPE[1] (WO)
mbed_official	146:f64d43ff0c18	164	*
mbed_official	146:f64d43ff0c18	165	* Values:
mbed_official	146:f64d43ff0c18	166	* - 0 - No error detected
mbed_official	146:f64d43ff0c18	167	* - 1 - DES key parity error detected
mbed_official	146:f64d43ff0c18	168	*/
mbed_official	146:f64d43ff0c18	169	//@{
mbed_official	146:f64d43ff0c18	170	#define BP_CAU_LDR_CASR_DPE (1U) //!< Bit position for CAU_LDR_CASR_DPE.
mbed_official	146:f64d43ff0c18	171	#define BM_CAU_LDR_CASR_DPE (0x00000002U) //!< Bit mask for CAU_LDR_CASR_DPE.
mbed_official	146:f64d43ff0c18	172	#define BS_CAU_LDR_CASR_DPE (1U) //!< Bit field size in bits for CAU_LDR_CASR_DPE.
mbed_official	146:f64d43ff0c18	173
mbed_official	146:f64d43ff0c18	174	//! @brief Format value for bitfield CAU_LDR_CASR_DPE.
mbed_official	146:f64d43ff0c18	175	#define BF_CAU_LDR_CASR_DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_LDR_CASR_DPE), uint32_t) & BM_CAU_LDR_CASR_DPE)
mbed_official	146:f64d43ff0c18	176	//@}
mbed_official	146:f64d43ff0c18	177
mbed_official	146:f64d43ff0c18	178	/*!
mbed_official	146:f64d43ff0c18	179	* @name Register CAU_LDR_CASR, field VER[31:28] (WO)
mbed_official	146:f64d43ff0c18	180	*
mbed_official	146:f64d43ff0c18	181	* Values:
mbed_official	146:f64d43ff0c18	182	* - 0001 - Initial CAU version
mbed_official	146:f64d43ff0c18	183	* - 0010 - Second version, added support for SHA-256 algorithm.(This is the
mbed_official	146:f64d43ff0c18	184	* value on this device)
mbed_official	146:f64d43ff0c18	185	*/
mbed_official	146:f64d43ff0c18	186	//@{
mbed_official	146:f64d43ff0c18	187	#define BP_CAU_LDR_CASR_VER (28U) //!< Bit position for CAU_LDR_CASR_VER.
mbed_official	146:f64d43ff0c18	188	#define BM_CAU_LDR_CASR_VER (0xF0000000U) //!< Bit mask for CAU_LDR_CASR_VER.
mbed_official	146:f64d43ff0c18	189	#define BS_CAU_LDR_CASR_VER (4U) //!< Bit field size in bits for CAU_LDR_CASR_VER.
mbed_official	146:f64d43ff0c18	190
mbed_official	146:f64d43ff0c18	191	//! @brief Format value for bitfield CAU_LDR_CASR_VER.
mbed_official	146:f64d43ff0c18	192	#define BF_CAU_LDR_CASR_VER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_LDR_CASR_VER), uint32_t) & BM_CAU_LDR_CASR_VER)
mbed_official	146:f64d43ff0c18	193	//@}
mbed_official	146:f64d43ff0c18	194
mbed_official	146:f64d43ff0c18	195	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	196	// HW_CAU_LDR_CAA - Accumulator register - Load Register command
mbed_official	146:f64d43ff0c18	197	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	198
mbed_official	146:f64d43ff0c18	199	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	200	/*!
mbed_official	146:f64d43ff0c18	201	* @brief HW_CAU_LDR_CAA - Accumulator register - Load Register command (WO)
mbed_official	146:f64d43ff0c18	202	*
mbed_official	146:f64d43ff0c18	203	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	204	*/
mbed_official	146:f64d43ff0c18	205	typedef union _hw_cau_ldr_caa
mbed_official	146:f64d43ff0c18	206	{
mbed_official	146:f64d43ff0c18	207	uint32_t U;
mbed_official	146:f64d43ff0c18	208	struct _hw_cau_ldr_caa_bitfields
mbed_official	146:f64d43ff0c18	209	{
mbed_official	146:f64d43ff0c18	210	uint32_t RESERVED0 : 32; //!< [31:0]
mbed_official	146:f64d43ff0c18	211	} B;
mbed_official	146:f64d43ff0c18	212	} hw_cau_ldr_caa_t;
mbed_official	146:f64d43ff0c18	213	#endif
mbed_official	146:f64d43ff0c18	214
mbed_official	146:f64d43ff0c18	215	/*!
mbed_official	146:f64d43ff0c18	216	* @name Constants and macros for entire CAU_LDR_CAA register
mbed_official	146:f64d43ff0c18	217	*/
mbed_official	146:f64d43ff0c18	218	//@{
mbed_official	146:f64d43ff0c18	219	#define HW_CAU_LDR_CAA_ADDR (REGS_CAU_BASE + 0x844U)
mbed_official	146:f64d43ff0c18	220
mbed_official	146:f64d43ff0c18	221	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	222	#define HW_CAU_LDR_CAA ((__O hw_cau_ldr_caa_t ) HW_CAU_LDR_CAA_ADDR)
mbed_official	146:f64d43ff0c18	223	#define HW_CAU_LDR_CAA_WR(v) (HW_CAU_LDR_CAA.U = (v))
mbed_official	146:f64d43ff0c18	224	#endif
mbed_official	146:f64d43ff0c18	225	//@}
mbed_official	146:f64d43ff0c18	226
mbed_official	146:f64d43ff0c18	227	/*
mbed_official	146:f64d43ff0c18	228	* Constants & macros for individual CAU_LDR_CAA bitfields
mbed_official	146:f64d43ff0c18	229	*/
mbed_official	146:f64d43ff0c18	230
mbed_official	146:f64d43ff0c18	231	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	232	// HW_CAU_LDR_CA - General Purpose Register 0 - Load Register command
mbed_official	146:f64d43ff0c18	233	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	234
mbed_official	146:f64d43ff0c18	235	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	236	/*!
mbed_official	146:f64d43ff0c18	237	* @brief HW_CAU_LDR_CA - General Purpose Register 0 - Load Register command (WO)
mbed_official	146:f64d43ff0c18	238	*
mbed_official	146:f64d43ff0c18	239	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	240	*/
mbed_official	146:f64d43ff0c18	241	typedef union _hw_cau_ldr_ca
mbed_official	146:f64d43ff0c18	242	{
mbed_official	146:f64d43ff0c18	243	uint32_t U;
mbed_official	146:f64d43ff0c18	244	struct _hw_cau_ldr_ca_bitfields
mbed_official	146:f64d43ff0c18	245	{
mbed_official	146:f64d43ff0c18	246	uint32_t RESERVED0 : 32; //!< [31:0]
mbed_official	146:f64d43ff0c18	247	} B;
mbed_official	146:f64d43ff0c18	248	} hw_cau_ldr_ca_t;
mbed_official	146:f64d43ff0c18	249	#endif
mbed_official	146:f64d43ff0c18	250
mbed_official	146:f64d43ff0c18	251	/*!
mbed_official	146:f64d43ff0c18	252	* @name Constants and macros for entire CAU_LDR_CA register
mbed_official	146:f64d43ff0c18	253	*/
mbed_official	146:f64d43ff0c18	254	//@{
mbed_official	146:f64d43ff0c18	255	#define HW_CAU_LDR_CA_COUNT (9U)
mbed_official	146:f64d43ff0c18	256
mbed_official	146:f64d43ff0c18	257	#define HW_CAU_LDR_CA_ADDR(n) (REGS_CAU_BASE + 0x848U + (0x4U * n))
mbed_official	146:f64d43ff0c18	258
mbed_official	146:f64d43ff0c18	259	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	260	#define HW_CAU_LDR_CA(n) ((__O hw_cau_ldr_ca_t ) HW_CAU_LDR_CA_ADDR(n))
mbed_official	146:f64d43ff0c18	261	#define HW_CAU_LDR_CA_WR(n, v) (HW_CAU_LDR_CA(n).U = (v))
mbed_official	146:f64d43ff0c18	262	#endif
mbed_official	146:f64d43ff0c18	263	//@}
mbed_official	146:f64d43ff0c18	264
mbed_official	146:f64d43ff0c18	265	/*
mbed_official	146:f64d43ff0c18	266	* Constants & macros for individual CAU_LDR_CA bitfields
mbed_official	146:f64d43ff0c18	267	*/
mbed_official	146:f64d43ff0c18	268
mbed_official	146:f64d43ff0c18	269	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	270	// HW_CAU_STR_CASR - Status register - Store Register command
mbed_official	146:f64d43ff0c18	271	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	272
mbed_official	146:f64d43ff0c18	273	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	274	/*!
mbed_official	146:f64d43ff0c18	275	* @brief HW_CAU_STR_CASR - Status register - Store Register command (RO)
mbed_official	146:f64d43ff0c18	276	*
mbed_official	146:f64d43ff0c18	277	* Reset value: 0x20000000U
mbed_official	146:f64d43ff0c18	278	*/
mbed_official	146:f64d43ff0c18	279	typedef union _hw_cau_str_casr
mbed_official	146:f64d43ff0c18	280	{
mbed_official	146:f64d43ff0c18	281	uint32_t U;
mbed_official	146:f64d43ff0c18	282	struct _hw_cau_str_casr_bitfields
mbed_official	146:f64d43ff0c18	283	{
mbed_official	146:f64d43ff0c18	284	uint32_t IC : 1; //!< [0]
mbed_official	146:f64d43ff0c18	285	uint32_t DPE : 1; //!< [1]
mbed_official	146:f64d43ff0c18	286	uint32_t RESERVED0 : 26; //!< [27:2]
mbed_official	146:f64d43ff0c18	287	uint32_t VER : 4; //!< [31:28] CAU version
mbed_official	146:f64d43ff0c18	288	} B;
mbed_official	146:f64d43ff0c18	289	} hw_cau_str_casr_t;
mbed_official	146:f64d43ff0c18	290	#endif
mbed_official	146:f64d43ff0c18	291
mbed_official	146:f64d43ff0c18	292	/*!
mbed_official	146:f64d43ff0c18	293	* @name Constants and macros for entire CAU_STR_CASR register
mbed_official	146:f64d43ff0c18	294	*/
mbed_official	146:f64d43ff0c18	295	//@{
mbed_official	146:f64d43ff0c18	296	#define HW_CAU_STR_CASR_ADDR (REGS_CAU_BASE + 0x880U)
mbed_official	146:f64d43ff0c18	297
mbed_official	146:f64d43ff0c18	298	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	299	#define HW_CAU_STR_CASR ((__I hw_cau_str_casr_t ) HW_CAU_STR_CASR_ADDR)
mbed_official	146:f64d43ff0c18	300	#define HW_CAU_STR_CASR_RD() (HW_CAU_STR_CASR.U)
mbed_official	146:f64d43ff0c18	301	#endif
mbed_official	146:f64d43ff0c18	302	//@}
mbed_official	146:f64d43ff0c18	303
mbed_official	146:f64d43ff0c18	304	/*
mbed_official	146:f64d43ff0c18	305	* Constants & macros for individual CAU_STR_CASR bitfields
mbed_official	146:f64d43ff0c18	306	*/
mbed_official	146:f64d43ff0c18	307
mbed_official	146:f64d43ff0c18	308	/*!
mbed_official	146:f64d43ff0c18	309	* @name Register CAU_STR_CASR, field IC[0] (RO)
mbed_official	146:f64d43ff0c18	310	*
mbed_official	146:f64d43ff0c18	311	* Values:
mbed_official	146:f64d43ff0c18	312	* - 0 - No illegal commands issued
mbed_official	146:f64d43ff0c18	313	* - 1 - Illegal command issued
mbed_official	146:f64d43ff0c18	314	*/
mbed_official	146:f64d43ff0c18	315	//@{
mbed_official	146:f64d43ff0c18	316	#define BP_CAU_STR_CASR_IC (0U) //!< Bit position for CAU_STR_CASR_IC.
mbed_official	146:f64d43ff0c18	317	#define BM_CAU_STR_CASR_IC (0x00000001U) //!< Bit mask for CAU_STR_CASR_IC.
mbed_official	146:f64d43ff0c18	318	#define BS_CAU_STR_CASR_IC (1U) //!< Bit field size in bits for CAU_STR_CASR_IC.
mbed_official	146:f64d43ff0c18	319
mbed_official	146:f64d43ff0c18	320	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	321	//! @brief Read current value of the CAU_STR_CASR_IC field.
mbed_official	146:f64d43ff0c18	322	#define BR_CAU_STR_CASR_IC (BITBAND_ACCESS32(HW_CAU_STR_CASR_ADDR, BP_CAU_STR_CASR_IC))
mbed_official	146:f64d43ff0c18	323	#endif
mbed_official	146:f64d43ff0c18	324	//@}
mbed_official	146:f64d43ff0c18	325
mbed_official	146:f64d43ff0c18	326	/*!
mbed_official	146:f64d43ff0c18	327	* @name Register CAU_STR_CASR, field DPE[1] (RO)
mbed_official	146:f64d43ff0c18	328	*
mbed_official	146:f64d43ff0c18	329	* Values:
mbed_official	146:f64d43ff0c18	330	* - 0 - No error detected
mbed_official	146:f64d43ff0c18	331	* - 1 - DES key parity error detected
mbed_official	146:f64d43ff0c18	332	*/
mbed_official	146:f64d43ff0c18	333	//@{
mbed_official	146:f64d43ff0c18	334	#define BP_CAU_STR_CASR_DPE (1U) //!< Bit position for CAU_STR_CASR_DPE.
mbed_official	146:f64d43ff0c18	335	#define BM_CAU_STR_CASR_DPE (0x00000002U) //!< Bit mask for CAU_STR_CASR_DPE.
mbed_official	146:f64d43ff0c18	336	#define BS_CAU_STR_CASR_DPE (1U) //!< Bit field size in bits for CAU_STR_CASR_DPE.
mbed_official	146:f64d43ff0c18	337
mbed_official	146:f64d43ff0c18	338	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	339	//! @brief Read current value of the CAU_STR_CASR_DPE field.
mbed_official	146:f64d43ff0c18	340	#define BR_CAU_STR_CASR_DPE (BITBAND_ACCESS32(HW_CAU_STR_CASR_ADDR, BP_CAU_STR_CASR_DPE))
mbed_official	146:f64d43ff0c18	341	#endif
mbed_official	146:f64d43ff0c18	342	//@}
mbed_official	146:f64d43ff0c18	343
mbed_official	146:f64d43ff0c18	344	/*!
mbed_official	146:f64d43ff0c18	345	* @name Register CAU_STR_CASR, field VER[31:28] (RO)
mbed_official	146:f64d43ff0c18	346	*
mbed_official	146:f64d43ff0c18	347	* Values:
mbed_official	146:f64d43ff0c18	348	* - 0001 - Initial CAU version
mbed_official	146:f64d43ff0c18	349	* - 0010 - Second version, added support for SHA-256 algorithm.(This is the
mbed_official	146:f64d43ff0c18	350	* value on this device)
mbed_official	146:f64d43ff0c18	351	*/
mbed_official	146:f64d43ff0c18	352	//@{
mbed_official	146:f64d43ff0c18	353	#define BP_CAU_STR_CASR_VER (28U) //!< Bit position for CAU_STR_CASR_VER.
mbed_official	146:f64d43ff0c18	354	#define BM_CAU_STR_CASR_VER (0xF0000000U) //!< Bit mask for CAU_STR_CASR_VER.
mbed_official	146:f64d43ff0c18	355	#define BS_CAU_STR_CASR_VER (4U) //!< Bit field size in bits for CAU_STR_CASR_VER.
mbed_official	146:f64d43ff0c18	356
mbed_official	146:f64d43ff0c18	357	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	358	//! @brief Read current value of the CAU_STR_CASR_VER field.
mbed_official	146:f64d43ff0c18	359	#define BR_CAU_STR_CASR_VER (HW_CAU_STR_CASR.B.VER)
mbed_official	146:f64d43ff0c18	360	#endif
mbed_official	146:f64d43ff0c18	361	//@}
mbed_official	146:f64d43ff0c18	362
mbed_official	146:f64d43ff0c18	363	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	364	// HW_CAU_STR_CAA - Accumulator register - Store Register command
mbed_official	146:f64d43ff0c18	365	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	366
mbed_official	146:f64d43ff0c18	367	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	368	/*!
mbed_official	146:f64d43ff0c18	369	* @brief HW_CAU_STR_CAA - Accumulator register - Store Register command (RO)
mbed_official	146:f64d43ff0c18	370	*
mbed_official	146:f64d43ff0c18	371	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	372	*/
mbed_official	146:f64d43ff0c18	373	typedef union _hw_cau_str_caa
mbed_official	146:f64d43ff0c18	374	{
mbed_official	146:f64d43ff0c18	375	uint32_t U;
mbed_official	146:f64d43ff0c18	376	struct _hw_cau_str_caa_bitfields
mbed_official	146:f64d43ff0c18	377	{
mbed_official	146:f64d43ff0c18	378	uint32_t RESERVED0 : 32; //!< [31:0]
mbed_official	146:f64d43ff0c18	379	} B;
mbed_official	146:f64d43ff0c18	380	} hw_cau_str_caa_t;
mbed_official	146:f64d43ff0c18	381	#endif
mbed_official	146:f64d43ff0c18	382
mbed_official	146:f64d43ff0c18	383	/*!
mbed_official	146:f64d43ff0c18	384	* @name Constants and macros for entire CAU_STR_CAA register
mbed_official	146:f64d43ff0c18	385	*/
mbed_official	146:f64d43ff0c18	386	//@{
mbed_official	146:f64d43ff0c18	387	#define HW_CAU_STR_CAA_ADDR (REGS_CAU_BASE + 0x884U)
mbed_official	146:f64d43ff0c18	388
mbed_official	146:f64d43ff0c18	389	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	390	#define HW_CAU_STR_CAA ((__I hw_cau_str_caa_t ) HW_CAU_STR_CAA_ADDR)
mbed_official	146:f64d43ff0c18	391	#define HW_CAU_STR_CAA_RD() (HW_CAU_STR_CAA.U)
mbed_official	146:f64d43ff0c18	392	#endif
mbed_official	146:f64d43ff0c18	393	//@}
mbed_official	146:f64d43ff0c18	394
mbed_official	146:f64d43ff0c18	395	/*
mbed_official	146:f64d43ff0c18	396	* Constants & macros for individual CAU_STR_CAA bitfields
mbed_official	146:f64d43ff0c18	397	*/
mbed_official	146:f64d43ff0c18	398
mbed_official	146:f64d43ff0c18	399	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	400	// HW_CAU_STR_CA - General Purpose Register 0 - Store Register command
mbed_official	146:f64d43ff0c18	401	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	402
mbed_official	146:f64d43ff0c18	403	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	404	/*!
mbed_official	146:f64d43ff0c18	405	* @brief HW_CAU_STR_CA - General Purpose Register 0 - Store Register command (RO)
mbed_official	146:f64d43ff0c18	406	*
mbed_official	146:f64d43ff0c18	407	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	408	*/
mbed_official	146:f64d43ff0c18	409	typedef union _hw_cau_str_ca
mbed_official	146:f64d43ff0c18	410	{
mbed_official	146:f64d43ff0c18	411	uint32_t U;
mbed_official	146:f64d43ff0c18	412	struct _hw_cau_str_ca_bitfields
mbed_official	146:f64d43ff0c18	413	{
mbed_official	146:f64d43ff0c18	414	uint32_t RESERVED0 : 32; //!< [31:0]
mbed_official	146:f64d43ff0c18	415	} B;
mbed_official	146:f64d43ff0c18	416	} hw_cau_str_ca_t;
mbed_official	146:f64d43ff0c18	417	#endif
mbed_official	146:f64d43ff0c18	418
mbed_official	146:f64d43ff0c18	419	/*!
mbed_official	146:f64d43ff0c18	420	* @name Constants and macros for entire CAU_STR_CA register
mbed_official	146:f64d43ff0c18	421	*/
mbed_official	146:f64d43ff0c18	422	//@{
mbed_official	146:f64d43ff0c18	423	#define HW_CAU_STR_CA_COUNT (9U)
mbed_official	146:f64d43ff0c18	424
mbed_official	146:f64d43ff0c18	425	#define HW_CAU_STR_CA_ADDR(n) (REGS_CAU_BASE + 0x888U + (0x4U * n))
mbed_official	146:f64d43ff0c18	426
mbed_official	146:f64d43ff0c18	427	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	428	#define HW_CAU_STR_CA(n) ((__I hw_cau_str_ca_t ) HW_CAU_STR_CA_ADDR(n))
mbed_official	146:f64d43ff0c18	429	#define HW_CAU_STR_CA_RD(n) (HW_CAU_STR_CA(n).U)
mbed_official	146:f64d43ff0c18	430	#endif
mbed_official	146:f64d43ff0c18	431	//@}
mbed_official	146:f64d43ff0c18	432
mbed_official	146:f64d43ff0c18	433	/*
mbed_official	146:f64d43ff0c18	434	* Constants & macros for individual CAU_STR_CA bitfields
mbed_official	146:f64d43ff0c18	435	*/
mbed_official	146:f64d43ff0c18	436
mbed_official	146:f64d43ff0c18	437	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	438	// HW_CAU_ADR_CASR - Status register - Add Register command
mbed_official	146:f64d43ff0c18	439	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	440
mbed_official	146:f64d43ff0c18	441	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	442	/*!
mbed_official	146:f64d43ff0c18	443	* @brief HW_CAU_ADR_CASR - Status register - Add Register command (WO)
mbed_official	146:f64d43ff0c18	444	*
mbed_official	146:f64d43ff0c18	445	* Reset value: 0x20000000U
mbed_official	146:f64d43ff0c18	446	*/
mbed_official	146:f64d43ff0c18	447	typedef union _hw_cau_adr_casr
mbed_official	146:f64d43ff0c18	448	{
mbed_official	146:f64d43ff0c18	449	uint32_t U;
mbed_official	146:f64d43ff0c18	450	struct _hw_cau_adr_casr_bitfields
mbed_official	146:f64d43ff0c18	451	{
mbed_official	146:f64d43ff0c18	452	uint32_t IC : 1; //!< [0]
mbed_official	146:f64d43ff0c18	453	uint32_t DPE : 1; //!< [1]
mbed_official	146:f64d43ff0c18	454	uint32_t RESERVED0 : 26; //!< [27:2]
mbed_official	146:f64d43ff0c18	455	uint32_t VER : 4; //!< [31:28] CAU version
mbed_official	146:f64d43ff0c18	456	} B;
mbed_official	146:f64d43ff0c18	457	} hw_cau_adr_casr_t;
mbed_official	146:f64d43ff0c18	458	#endif
mbed_official	146:f64d43ff0c18	459
mbed_official	146:f64d43ff0c18	460	/*!
mbed_official	146:f64d43ff0c18	461	* @name Constants and macros for entire CAU_ADR_CASR register
mbed_official	146:f64d43ff0c18	462	*/
mbed_official	146:f64d43ff0c18	463	//@{
mbed_official	146:f64d43ff0c18	464	#define HW_CAU_ADR_CASR_ADDR (REGS_CAU_BASE + 0x8C0U)
mbed_official	146:f64d43ff0c18	465
mbed_official	146:f64d43ff0c18	466	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	467	#define HW_CAU_ADR_CASR ((__O hw_cau_adr_casr_t ) HW_CAU_ADR_CASR_ADDR)
mbed_official	146:f64d43ff0c18	468	#define HW_CAU_ADR_CASR_WR(v) (HW_CAU_ADR_CASR.U = (v))
mbed_official	146:f64d43ff0c18	469	#endif
mbed_official	146:f64d43ff0c18	470	//@}
mbed_official	146:f64d43ff0c18	471
mbed_official	146:f64d43ff0c18	472	/*
mbed_official	146:f64d43ff0c18	473	* Constants & macros for individual CAU_ADR_CASR bitfields
mbed_official	146:f64d43ff0c18	474	*/
mbed_official	146:f64d43ff0c18	475
mbed_official	146:f64d43ff0c18	476	/*!
mbed_official	146:f64d43ff0c18	477	* @name Register CAU_ADR_CASR, field IC[0] (WO)
mbed_official	146:f64d43ff0c18	478	*
mbed_official	146:f64d43ff0c18	479	* Values:
mbed_official	146:f64d43ff0c18	480	* - 0 - No illegal commands issued
mbed_official	146:f64d43ff0c18	481	* - 1 - Illegal command issued
mbed_official	146:f64d43ff0c18	482	*/
mbed_official	146:f64d43ff0c18	483	//@{
mbed_official	146:f64d43ff0c18	484	#define BP_CAU_ADR_CASR_IC (0U) //!< Bit position for CAU_ADR_CASR_IC.
mbed_official	146:f64d43ff0c18	485	#define BM_CAU_ADR_CASR_IC (0x00000001U) //!< Bit mask for CAU_ADR_CASR_IC.
mbed_official	146:f64d43ff0c18	486	#define BS_CAU_ADR_CASR_IC (1U) //!< Bit field size in bits for CAU_ADR_CASR_IC.
mbed_official	146:f64d43ff0c18	487
mbed_official	146:f64d43ff0c18	488	//! @brief Format value for bitfield CAU_ADR_CASR_IC.
mbed_official	146:f64d43ff0c18	489	#define BF_CAU_ADR_CASR_IC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_ADR_CASR_IC), uint32_t) & BM_CAU_ADR_CASR_IC)
mbed_official	146:f64d43ff0c18	490	//@}
mbed_official	146:f64d43ff0c18	491
mbed_official	146:f64d43ff0c18	492	/*!
mbed_official	146:f64d43ff0c18	493	* @name Register CAU_ADR_CASR, field DPE[1] (WO)
mbed_official	146:f64d43ff0c18	494	*
mbed_official	146:f64d43ff0c18	495	* Values:
mbed_official	146:f64d43ff0c18	496	* - 0 - No error detected
mbed_official	146:f64d43ff0c18	497	* - 1 - DES key parity error detected
mbed_official	146:f64d43ff0c18	498	*/
mbed_official	146:f64d43ff0c18	499	//@{
mbed_official	146:f64d43ff0c18	500	#define BP_CAU_ADR_CASR_DPE (1U) //!< Bit position for CAU_ADR_CASR_DPE.
mbed_official	146:f64d43ff0c18	501	#define BM_CAU_ADR_CASR_DPE (0x00000002U) //!< Bit mask for CAU_ADR_CASR_DPE.
mbed_official	146:f64d43ff0c18	502	#define BS_CAU_ADR_CASR_DPE (1U) //!< Bit field size in bits for CAU_ADR_CASR_DPE.
mbed_official	146:f64d43ff0c18	503
mbed_official	146:f64d43ff0c18	504	//! @brief Format value for bitfield CAU_ADR_CASR_DPE.
mbed_official	146:f64d43ff0c18	505	#define BF_CAU_ADR_CASR_DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_ADR_CASR_DPE), uint32_t) & BM_CAU_ADR_CASR_DPE)
mbed_official	146:f64d43ff0c18	506	//@}
mbed_official	146:f64d43ff0c18	507
mbed_official	146:f64d43ff0c18	508	/*!
mbed_official	146:f64d43ff0c18	509	* @name Register CAU_ADR_CASR, field VER[31:28] (WO)
mbed_official	146:f64d43ff0c18	510	*
mbed_official	146:f64d43ff0c18	511	* Values:
mbed_official	146:f64d43ff0c18	512	* - 0001 - Initial CAU version
mbed_official	146:f64d43ff0c18	513	* - 0010 - Second version, added support for SHA-256 algorithm.(This is the
mbed_official	146:f64d43ff0c18	514	* value on this device)
mbed_official	146:f64d43ff0c18	515	*/
mbed_official	146:f64d43ff0c18	516	//@{
mbed_official	146:f64d43ff0c18	517	#define BP_CAU_ADR_CASR_VER (28U) //!< Bit position for CAU_ADR_CASR_VER.
mbed_official	146:f64d43ff0c18	518	#define BM_CAU_ADR_CASR_VER (0xF0000000U) //!< Bit mask for CAU_ADR_CASR_VER.
mbed_official	146:f64d43ff0c18	519	#define BS_CAU_ADR_CASR_VER (4U) //!< Bit field size in bits for CAU_ADR_CASR_VER.
mbed_official	146:f64d43ff0c18	520
mbed_official	146:f64d43ff0c18	521	//! @brief Format value for bitfield CAU_ADR_CASR_VER.
mbed_official	146:f64d43ff0c18	522	#define BF_CAU_ADR_CASR_VER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_ADR_CASR_VER), uint32_t) & BM_CAU_ADR_CASR_VER)
mbed_official	146:f64d43ff0c18	523	//@}
mbed_official	146:f64d43ff0c18	524
mbed_official	146:f64d43ff0c18	525	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	526	// HW_CAU_ADR_CAA - Accumulator register - Add to register command
mbed_official	146:f64d43ff0c18	527	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	528
mbed_official	146:f64d43ff0c18	529	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	530	/*!
mbed_official	146:f64d43ff0c18	531	* @brief HW_CAU_ADR_CAA - Accumulator register - Add to register command (WO)
mbed_official	146:f64d43ff0c18	532	*
mbed_official	146:f64d43ff0c18	533	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	534	*/
mbed_official	146:f64d43ff0c18	535	typedef union _hw_cau_adr_caa
mbed_official	146:f64d43ff0c18	536	{
mbed_official	146:f64d43ff0c18	537	uint32_t U;
mbed_official	146:f64d43ff0c18	538	struct _hw_cau_adr_caa_bitfields
mbed_official	146:f64d43ff0c18	539	{
mbed_official	146:f64d43ff0c18	540	uint32_t RESERVED0 : 32; //!< [31:0]
mbed_official	146:f64d43ff0c18	541	} B;
mbed_official	146:f64d43ff0c18	542	} hw_cau_adr_caa_t;
mbed_official	146:f64d43ff0c18	543	#endif
mbed_official	146:f64d43ff0c18	544
mbed_official	146:f64d43ff0c18	545	/*!
mbed_official	146:f64d43ff0c18	546	* @name Constants and macros for entire CAU_ADR_CAA register
mbed_official	146:f64d43ff0c18	547	*/
mbed_official	146:f64d43ff0c18	548	//@{
mbed_official	146:f64d43ff0c18	549	#define HW_CAU_ADR_CAA_ADDR (REGS_CAU_BASE + 0x8C4U)
mbed_official	146:f64d43ff0c18	550
mbed_official	146:f64d43ff0c18	551	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	552	#define HW_CAU_ADR_CAA ((__O hw_cau_adr_caa_t ) HW_CAU_ADR_CAA_ADDR)
mbed_official	146:f64d43ff0c18	553	#define HW_CAU_ADR_CAA_WR(v) (HW_CAU_ADR_CAA.U = (v))
mbed_official	146:f64d43ff0c18	554	#endif
mbed_official	146:f64d43ff0c18	555	//@}
mbed_official	146:f64d43ff0c18	556
mbed_official	146:f64d43ff0c18	557	/*
mbed_official	146:f64d43ff0c18	558	* Constants & macros for individual CAU_ADR_CAA bitfields
mbed_official	146:f64d43ff0c18	559	*/
mbed_official	146:f64d43ff0c18	560
mbed_official	146:f64d43ff0c18	561	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	562	// HW_CAU_ADR_CA - General Purpose Register 0 - Add to register command
mbed_official	146:f64d43ff0c18	563	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	564
mbed_official	146:f64d43ff0c18	565	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	566	/*!
mbed_official	146:f64d43ff0c18	567	* @brief HW_CAU_ADR_CA - General Purpose Register 0 - Add to register command (WO)
mbed_official	146:f64d43ff0c18	568	*
mbed_official	146:f64d43ff0c18	569	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	570	*/
mbed_official	146:f64d43ff0c18	571	typedef union _hw_cau_adr_ca
mbed_official	146:f64d43ff0c18	572	{
mbed_official	146:f64d43ff0c18	573	uint32_t U;
mbed_official	146:f64d43ff0c18	574	struct _hw_cau_adr_ca_bitfields
mbed_official	146:f64d43ff0c18	575	{
mbed_official	146:f64d43ff0c18	576	uint32_t RESERVED0 : 32; //!< [31:0]
mbed_official	146:f64d43ff0c18	577	} B;
mbed_official	146:f64d43ff0c18	578	} hw_cau_adr_ca_t;
mbed_official	146:f64d43ff0c18	579	#endif
mbed_official	146:f64d43ff0c18	580
mbed_official	146:f64d43ff0c18	581	/*!
mbed_official	146:f64d43ff0c18	582	* @name Constants and macros for entire CAU_ADR_CA register
mbed_official	146:f64d43ff0c18	583	*/
mbed_official	146:f64d43ff0c18	584	//@{
mbed_official	146:f64d43ff0c18	585	#define HW_CAU_ADR_CA_COUNT (9U)
mbed_official	146:f64d43ff0c18	586
mbed_official	146:f64d43ff0c18	587	#define HW_CAU_ADR_CA_ADDR(n) (REGS_CAU_BASE + 0x8C8U + (0x4U * n))
mbed_official	146:f64d43ff0c18	588
mbed_official	146:f64d43ff0c18	589	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	590	#define HW_CAU_ADR_CA(n) ((__O hw_cau_adr_ca_t ) HW_CAU_ADR_CA_ADDR(n))
mbed_official	146:f64d43ff0c18	591	#define HW_CAU_ADR_CA_WR(n, v) (HW_CAU_ADR_CA(n).U = (v))
mbed_official	146:f64d43ff0c18	592	#endif
mbed_official	146:f64d43ff0c18	593	//@}
mbed_official	146:f64d43ff0c18	594
mbed_official	146:f64d43ff0c18	595	/*
mbed_official	146:f64d43ff0c18	596	* Constants & macros for individual CAU_ADR_CA bitfields
mbed_official	146:f64d43ff0c18	597	*/
mbed_official	146:f64d43ff0c18	598
mbed_official	146:f64d43ff0c18	599	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	600	// HW_CAU_RADR_CASR - Status register - Reverse and Add to Register command
mbed_official	146:f64d43ff0c18	601	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	602
mbed_official	146:f64d43ff0c18	603	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	604	/*!
mbed_official	146:f64d43ff0c18	605	* @brief HW_CAU_RADR_CASR - Status register - Reverse and Add to Register command (WO)
mbed_official	146:f64d43ff0c18	606	*
mbed_official	146:f64d43ff0c18	607	* Reset value: 0x20000000U
mbed_official	146:f64d43ff0c18	608	*/
mbed_official	146:f64d43ff0c18	609	typedef union _hw_cau_radr_casr
mbed_official	146:f64d43ff0c18	610	{
mbed_official	146:f64d43ff0c18	611	uint32_t U;
mbed_official	146:f64d43ff0c18	612	struct _hw_cau_radr_casr_bitfields
mbed_official	146:f64d43ff0c18	613	{
mbed_official	146:f64d43ff0c18	614	uint32_t IC : 1; //!< [0]
mbed_official	146:f64d43ff0c18	615	uint32_t DPE : 1; //!< [1]
mbed_official	146:f64d43ff0c18	616	uint32_t RESERVED0 : 26; //!< [27:2]
mbed_official	146:f64d43ff0c18	617	uint32_t VER : 4; //!< [31:28] CAU version
mbed_official	146:f64d43ff0c18	618	} B;
mbed_official	146:f64d43ff0c18	619	} hw_cau_radr_casr_t;
mbed_official	146:f64d43ff0c18	620	#endif
mbed_official	146:f64d43ff0c18	621
mbed_official	146:f64d43ff0c18	622	/*!
mbed_official	146:f64d43ff0c18	623	* @name Constants and macros for entire CAU_RADR_CASR register
mbed_official	146:f64d43ff0c18	624	*/
mbed_official	146:f64d43ff0c18	625	//@{
mbed_official	146:f64d43ff0c18	626	#define HW_CAU_RADR_CASR_ADDR (REGS_CAU_BASE + 0x900U)
mbed_official	146:f64d43ff0c18	627
mbed_official	146:f64d43ff0c18	628	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	629	#define HW_CAU_RADR_CASR ((__O hw_cau_radr_casr_t ) HW_CAU_RADR_CASR_ADDR)
mbed_official	146:f64d43ff0c18	630	#define HW_CAU_RADR_CASR_WR(v) (HW_CAU_RADR_CASR.U = (v))
mbed_official	146:f64d43ff0c18	631	#endif
mbed_official	146:f64d43ff0c18	632	//@}
mbed_official	146:f64d43ff0c18	633
mbed_official	146:f64d43ff0c18	634	/*
mbed_official	146:f64d43ff0c18	635	* Constants & macros for individual CAU_RADR_CASR bitfields
mbed_official	146:f64d43ff0c18	636	*/
mbed_official	146:f64d43ff0c18	637
mbed_official	146:f64d43ff0c18	638	/*!
mbed_official	146:f64d43ff0c18	639	* @name Register CAU_RADR_CASR, field IC[0] (WO)
mbed_official	146:f64d43ff0c18	640	*
mbed_official	146:f64d43ff0c18	641	* Values:
mbed_official	146:f64d43ff0c18	642	* - 0 - No illegal commands issued
mbed_official	146:f64d43ff0c18	643	* - 1 - Illegal command issued
mbed_official	146:f64d43ff0c18	644	*/
mbed_official	146:f64d43ff0c18	645	//@{
mbed_official	146:f64d43ff0c18	646	#define BP_CAU_RADR_CASR_IC (0U) //!< Bit position for CAU_RADR_CASR_IC.
mbed_official	146:f64d43ff0c18	647	#define BM_CAU_RADR_CASR_IC (0x00000001U) //!< Bit mask for CAU_RADR_CASR_IC.
mbed_official	146:f64d43ff0c18	648	#define BS_CAU_RADR_CASR_IC (1U) //!< Bit field size in bits for CAU_RADR_CASR_IC.
mbed_official	146:f64d43ff0c18	649
mbed_official	146:f64d43ff0c18	650	//! @brief Format value for bitfield CAU_RADR_CASR_IC.
mbed_official	146:f64d43ff0c18	651	#define BF_CAU_RADR_CASR_IC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_RADR_CASR_IC), uint32_t) & BM_CAU_RADR_CASR_IC)
mbed_official	146:f64d43ff0c18	652	//@}
mbed_official	146:f64d43ff0c18	653
mbed_official	146:f64d43ff0c18	654	/*!
mbed_official	146:f64d43ff0c18	655	* @name Register CAU_RADR_CASR, field DPE[1] (WO)
mbed_official	146:f64d43ff0c18	656	*
mbed_official	146:f64d43ff0c18	657	* Values:
mbed_official	146:f64d43ff0c18	658	* - 0 - No error detected
mbed_official	146:f64d43ff0c18	659	* - 1 - DES key parity error detected
mbed_official	146:f64d43ff0c18	660	*/
mbed_official	146:f64d43ff0c18	661	//@{
mbed_official	146:f64d43ff0c18	662	#define BP_CAU_RADR_CASR_DPE (1U) //!< Bit position for CAU_RADR_CASR_DPE.
mbed_official	146:f64d43ff0c18	663	#define BM_CAU_RADR_CASR_DPE (0x00000002U) //!< Bit mask for CAU_RADR_CASR_DPE.
mbed_official	146:f64d43ff0c18	664	#define BS_CAU_RADR_CASR_DPE (1U) //!< Bit field size in bits for CAU_RADR_CASR_DPE.
mbed_official	146:f64d43ff0c18	665
mbed_official	146:f64d43ff0c18	666	//! @brief Format value for bitfield CAU_RADR_CASR_DPE.
mbed_official	146:f64d43ff0c18	667	#define BF_CAU_RADR_CASR_DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_RADR_CASR_DPE), uint32_t) & BM_CAU_RADR_CASR_DPE)
mbed_official	146:f64d43ff0c18	668	//@}
mbed_official	146:f64d43ff0c18	669
mbed_official	146:f64d43ff0c18	670	/*!
mbed_official	146:f64d43ff0c18	671	* @name Register CAU_RADR_CASR, field VER[31:28] (WO)
mbed_official	146:f64d43ff0c18	672	*
mbed_official	146:f64d43ff0c18	673	* Values:
mbed_official	146:f64d43ff0c18	674	* - 0001 - Initial CAU version
mbed_official	146:f64d43ff0c18	675	* - 0010 - Second version, added support for SHA-256 algorithm.(This is the
mbed_official	146:f64d43ff0c18	676	* value on this device)
mbed_official	146:f64d43ff0c18	677	*/
mbed_official	146:f64d43ff0c18	678	//@{
mbed_official	146:f64d43ff0c18	679	#define BP_CAU_RADR_CASR_VER (28U) //!< Bit position for CAU_RADR_CASR_VER.
mbed_official	146:f64d43ff0c18	680	#define BM_CAU_RADR_CASR_VER (0xF0000000U) //!< Bit mask for CAU_RADR_CASR_VER.
mbed_official	146:f64d43ff0c18	681	#define BS_CAU_RADR_CASR_VER (4U) //!< Bit field size in bits for CAU_RADR_CASR_VER.
mbed_official	146:f64d43ff0c18	682
mbed_official	146:f64d43ff0c18	683	//! @brief Format value for bitfield CAU_RADR_CASR_VER.
mbed_official	146:f64d43ff0c18	684	#define BF_CAU_RADR_CASR_VER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_RADR_CASR_VER), uint32_t) & BM_CAU_RADR_CASR_VER)
mbed_official	146:f64d43ff0c18	685	//@}
mbed_official	146:f64d43ff0c18	686
mbed_official	146:f64d43ff0c18	687	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	688	// HW_CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command
mbed_official	146:f64d43ff0c18	689	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	690
mbed_official	146:f64d43ff0c18	691	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	692	/*!
mbed_official	146:f64d43ff0c18	693	* @brief HW_CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command (WO)
mbed_official	146:f64d43ff0c18	694	*
mbed_official	146:f64d43ff0c18	695	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	696	*/
mbed_official	146:f64d43ff0c18	697	typedef union _hw_cau_radr_caa
mbed_official	146:f64d43ff0c18	698	{
mbed_official	146:f64d43ff0c18	699	uint32_t U;
mbed_official	146:f64d43ff0c18	700	struct _hw_cau_radr_caa_bitfields
mbed_official	146:f64d43ff0c18	701	{
mbed_official	146:f64d43ff0c18	702	uint32_t RESERVED0 : 32; //!< [31:0]
mbed_official	146:f64d43ff0c18	703	} B;
mbed_official	146:f64d43ff0c18	704	} hw_cau_radr_caa_t;
mbed_official	146:f64d43ff0c18	705	#endif
mbed_official	146:f64d43ff0c18	706
mbed_official	146:f64d43ff0c18	707	/*!
mbed_official	146:f64d43ff0c18	708	* @name Constants and macros for entire CAU_RADR_CAA register
mbed_official	146:f64d43ff0c18	709	*/
mbed_official	146:f64d43ff0c18	710	//@{
mbed_official	146:f64d43ff0c18	711	#define HW_CAU_RADR_CAA_ADDR (REGS_CAU_BASE + 0x904U)
mbed_official	146:f64d43ff0c18	712
mbed_official	146:f64d43ff0c18	713	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	714	#define HW_CAU_RADR_CAA ((__O hw_cau_radr_caa_t ) HW_CAU_RADR_CAA_ADDR)
mbed_official	146:f64d43ff0c18	715	#define HW_CAU_RADR_CAA_WR(v) (HW_CAU_RADR_CAA.U = (v))
mbed_official	146:f64d43ff0c18	716	#endif
mbed_official	146:f64d43ff0c18	717	//@}
mbed_official	146:f64d43ff0c18	718
mbed_official	146:f64d43ff0c18	719	/*
mbed_official	146:f64d43ff0c18	720	* Constants & macros for individual CAU_RADR_CAA bitfields
mbed_official	146:f64d43ff0c18	721	*/
mbed_official	146:f64d43ff0c18	722
mbed_official	146:f64d43ff0c18	723	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	724	// HW_CAU_RADR_CA - General Purpose Register 0 - Reverse and Add to Register command
mbed_official	146:f64d43ff0c18	725	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	726
mbed_official	146:f64d43ff0c18	727	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	728	/*!
mbed_official	146:f64d43ff0c18	729	* @brief HW_CAU_RADR_CA - General Purpose Register 0 - Reverse and Add to Register command (WO)
mbed_official	146:f64d43ff0c18	730	*
mbed_official	146:f64d43ff0c18	731	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	732	*/
mbed_official	146:f64d43ff0c18	733	typedef union _hw_cau_radr_ca
mbed_official	146:f64d43ff0c18	734	{
mbed_official	146:f64d43ff0c18	735	uint32_t U;
mbed_official	146:f64d43ff0c18	736	struct _hw_cau_radr_ca_bitfields
mbed_official	146:f64d43ff0c18	737	{
mbed_official	146:f64d43ff0c18	738	uint32_t RESERVED0 : 32; //!< [31:0]
mbed_official	146:f64d43ff0c18	739	} B;
mbed_official	146:f64d43ff0c18	740	} hw_cau_radr_ca_t;
mbed_official	146:f64d43ff0c18	741	#endif
mbed_official	146:f64d43ff0c18	742
mbed_official	146:f64d43ff0c18	743	/*!
mbed_official	146:f64d43ff0c18	744	* @name Constants and macros for entire CAU_RADR_CA register
mbed_official	146:f64d43ff0c18	745	*/
mbed_official	146:f64d43ff0c18	746	//@{
mbed_official	146:f64d43ff0c18	747	#define HW_CAU_RADR_CA_COUNT (9U)
mbed_official	146:f64d43ff0c18	748
mbed_official	146:f64d43ff0c18	749	#define HW_CAU_RADR_CA_ADDR(n) (REGS_CAU_BASE + 0x908U + (0x4U * n))
mbed_official	146:f64d43ff0c18	750
mbed_official	146:f64d43ff0c18	751	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	752	#define HW_CAU_RADR_CA(n) ((__O hw_cau_radr_ca_t ) HW_CAU_RADR_CA_ADDR(n))
mbed_official	146:f64d43ff0c18	753	#define HW_CAU_RADR_CA_WR(n, v) (HW_CAU_RADR_CA(n).U = (v))
mbed_official	146:f64d43ff0c18	754	#endif
mbed_official	146:f64d43ff0c18	755	//@}
mbed_official	146:f64d43ff0c18	756
mbed_official	146:f64d43ff0c18	757	/*
mbed_official	146:f64d43ff0c18	758	* Constants & macros for individual CAU_RADR_CA bitfields
mbed_official	146:f64d43ff0c18	759	*/
mbed_official	146:f64d43ff0c18	760
mbed_official	146:f64d43ff0c18	761	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	762	// HW_CAU_XOR_CASR - Status register - Exclusive Or command
mbed_official	146:f64d43ff0c18	763	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	764
mbed_official	146:f64d43ff0c18	765	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	766	/*!
mbed_official	146:f64d43ff0c18	767	* @brief HW_CAU_XOR_CASR - Status register - Exclusive Or command (WO)
mbed_official	146:f64d43ff0c18	768	*
mbed_official	146:f64d43ff0c18	769	* Reset value: 0x20000000U
mbed_official	146:f64d43ff0c18	770	*/
mbed_official	146:f64d43ff0c18	771	typedef union _hw_cau_xor_casr
mbed_official	146:f64d43ff0c18	772	{
mbed_official	146:f64d43ff0c18	773	uint32_t U;
mbed_official	146:f64d43ff0c18	774	struct _hw_cau_xor_casr_bitfields
mbed_official	146:f64d43ff0c18	775	{
mbed_official	146:f64d43ff0c18	776	uint32_t IC : 1; //!< [0]
mbed_official	146:f64d43ff0c18	777	uint32_t DPE : 1; //!< [1]
mbed_official	146:f64d43ff0c18	778	uint32_t RESERVED0 : 26; //!< [27:2]
mbed_official	146:f64d43ff0c18	779	uint32_t VER : 4; //!< [31:28] CAU version
mbed_official	146:f64d43ff0c18	780	} B;
mbed_official	146:f64d43ff0c18	781	} hw_cau_xor_casr_t;
mbed_official	146:f64d43ff0c18	782	#endif
mbed_official	146:f64d43ff0c18	783
mbed_official	146:f64d43ff0c18	784	/*!
mbed_official	146:f64d43ff0c18	785	* @name Constants and macros for entire CAU_XOR_CASR register
mbed_official	146:f64d43ff0c18	786	*/
mbed_official	146:f64d43ff0c18	787	//@{
mbed_official	146:f64d43ff0c18	788	#define HW_CAU_XOR_CASR_ADDR (REGS_CAU_BASE + 0x980U)
mbed_official	146:f64d43ff0c18	789
mbed_official	146:f64d43ff0c18	790	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	791	#define HW_CAU_XOR_CASR ((__O hw_cau_xor_casr_t ) HW_CAU_XOR_CASR_ADDR)
mbed_official	146:f64d43ff0c18	792	#define HW_CAU_XOR_CASR_WR(v) (HW_CAU_XOR_CASR.U = (v))
mbed_official	146:f64d43ff0c18	793	#endif
mbed_official	146:f64d43ff0c18	794	//@}
mbed_official	146:f64d43ff0c18	795
mbed_official	146:f64d43ff0c18	796	/*
mbed_official	146:f64d43ff0c18	797	* Constants & macros for individual CAU_XOR_CASR bitfields
mbed_official	146:f64d43ff0c18	798	*/
mbed_official	146:f64d43ff0c18	799
mbed_official	146:f64d43ff0c18	800	/*!
mbed_official	146:f64d43ff0c18	801	* @name Register CAU_XOR_CASR, field IC[0] (WO)
mbed_official	146:f64d43ff0c18	802	*
mbed_official	146:f64d43ff0c18	803	* Values:
mbed_official	146:f64d43ff0c18	804	* - 0 - No illegal commands issued
mbed_official	146:f64d43ff0c18	805	* - 1 - Illegal command issued
mbed_official	146:f64d43ff0c18	806	*/
mbed_official	146:f64d43ff0c18	807	//@{
mbed_official	146:f64d43ff0c18	808	#define BP_CAU_XOR_CASR_IC (0U) //!< Bit position for CAU_XOR_CASR_IC.
mbed_official	146:f64d43ff0c18	809	#define BM_CAU_XOR_CASR_IC (0x00000001U) //!< Bit mask for CAU_XOR_CASR_IC.
mbed_official	146:f64d43ff0c18	810	#define BS_CAU_XOR_CASR_IC (1U) //!< Bit field size in bits for CAU_XOR_CASR_IC.
mbed_official	146:f64d43ff0c18	811
mbed_official	146:f64d43ff0c18	812	//! @brief Format value for bitfield CAU_XOR_CASR_IC.
mbed_official	146:f64d43ff0c18	813	#define BF_CAU_XOR_CASR_IC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_XOR_CASR_IC), uint32_t) & BM_CAU_XOR_CASR_IC)
mbed_official	146:f64d43ff0c18	814	//@}
mbed_official	146:f64d43ff0c18	815
mbed_official	146:f64d43ff0c18	816	/*!
mbed_official	146:f64d43ff0c18	817	* @name Register CAU_XOR_CASR, field DPE[1] (WO)
mbed_official	146:f64d43ff0c18	818	*
mbed_official	146:f64d43ff0c18	819	* Values:
mbed_official	146:f64d43ff0c18	820	* - 0 - No error detected
mbed_official	146:f64d43ff0c18	821	* - 1 - DES key parity error detected
mbed_official	146:f64d43ff0c18	822	*/
mbed_official	146:f64d43ff0c18	823	//@{
mbed_official	146:f64d43ff0c18	824	#define BP_CAU_XOR_CASR_DPE (1U) //!< Bit position for CAU_XOR_CASR_DPE.
mbed_official	146:f64d43ff0c18	825	#define BM_CAU_XOR_CASR_DPE (0x00000002U) //!< Bit mask for CAU_XOR_CASR_DPE.
mbed_official	146:f64d43ff0c18	826	#define BS_CAU_XOR_CASR_DPE (1U) //!< Bit field size in bits for CAU_XOR_CASR_DPE.
mbed_official	146:f64d43ff0c18	827
mbed_official	146:f64d43ff0c18	828	//! @brief Format value for bitfield CAU_XOR_CASR_DPE.
mbed_official	146:f64d43ff0c18	829	#define BF_CAU_XOR_CASR_DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_XOR_CASR_DPE), uint32_t) & BM_CAU_XOR_CASR_DPE)
mbed_official	146:f64d43ff0c18	830	//@}
mbed_official	146:f64d43ff0c18	831
mbed_official	146:f64d43ff0c18	832	/*!
mbed_official	146:f64d43ff0c18	833	* @name Register CAU_XOR_CASR, field VER[31:28] (WO)
mbed_official	146:f64d43ff0c18	834	*
mbed_official	146:f64d43ff0c18	835	* Values:
mbed_official	146:f64d43ff0c18	836	* - 0001 - Initial CAU version
mbed_official	146:f64d43ff0c18	837	* - 0010 - Second version, added support for SHA-256 algorithm.(This is the
mbed_official	146:f64d43ff0c18	838	* value on this device)
mbed_official	146:f64d43ff0c18	839	*/
mbed_official	146:f64d43ff0c18	840	//@{
mbed_official	146:f64d43ff0c18	841	#define BP_CAU_XOR_CASR_VER (28U) //!< Bit position for CAU_XOR_CASR_VER.
mbed_official	146:f64d43ff0c18	842	#define BM_CAU_XOR_CASR_VER (0xF0000000U) //!< Bit mask for CAU_XOR_CASR_VER.
mbed_official	146:f64d43ff0c18	843	#define BS_CAU_XOR_CASR_VER (4U) //!< Bit field size in bits for CAU_XOR_CASR_VER.
mbed_official	146:f64d43ff0c18	844
mbed_official	146:f64d43ff0c18	845	//! @brief Format value for bitfield CAU_XOR_CASR_VER.
mbed_official	146:f64d43ff0c18	846	#define BF_CAU_XOR_CASR_VER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_XOR_CASR_VER), uint32_t) & BM_CAU_XOR_CASR_VER)
mbed_official	146:f64d43ff0c18	847	//@}
mbed_official	146:f64d43ff0c18	848
mbed_official	146:f64d43ff0c18	849	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	850	// HW_CAU_XOR_CAA - Accumulator register - Exclusive Or command
mbed_official	146:f64d43ff0c18	851	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	852
mbed_official	146:f64d43ff0c18	853	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	854	/*!
mbed_official	146:f64d43ff0c18	855	* @brief HW_CAU_XOR_CAA - Accumulator register - Exclusive Or command (WO)
mbed_official	146:f64d43ff0c18	856	*
mbed_official	146:f64d43ff0c18	857	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	858	*/
mbed_official	146:f64d43ff0c18	859	typedef union _hw_cau_xor_caa
mbed_official	146:f64d43ff0c18	860	{
mbed_official	146:f64d43ff0c18	861	uint32_t U;
mbed_official	146:f64d43ff0c18	862	struct _hw_cau_xor_caa_bitfields
mbed_official	146:f64d43ff0c18	863	{
mbed_official	146:f64d43ff0c18	864	uint32_t RESERVED0 : 32; //!< [31:0]
mbed_official	146:f64d43ff0c18	865	} B;
mbed_official	146:f64d43ff0c18	866	} hw_cau_xor_caa_t;
mbed_official	146:f64d43ff0c18	867	#endif
mbed_official	146:f64d43ff0c18	868
mbed_official	146:f64d43ff0c18	869	/*!
mbed_official	146:f64d43ff0c18	870	* @name Constants and macros for entire CAU_XOR_CAA register
mbed_official	146:f64d43ff0c18	871	*/
mbed_official	146:f64d43ff0c18	872	//@{
mbed_official	146:f64d43ff0c18	873	#define HW_CAU_XOR_CAA_ADDR (REGS_CAU_BASE + 0x984U)
mbed_official	146:f64d43ff0c18	874
mbed_official	146:f64d43ff0c18	875	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	876	#define HW_CAU_XOR_CAA ((__O hw_cau_xor_caa_t ) HW_CAU_XOR_CAA_ADDR)
mbed_official	146:f64d43ff0c18	877	#define HW_CAU_XOR_CAA_WR(v) (HW_CAU_XOR_CAA.U = (v))
mbed_official	146:f64d43ff0c18	878	#endif
mbed_official	146:f64d43ff0c18	879	//@}
mbed_official	146:f64d43ff0c18	880
mbed_official	146:f64d43ff0c18	881	/*
mbed_official	146:f64d43ff0c18	882	* Constants & macros for individual CAU_XOR_CAA bitfields
mbed_official	146:f64d43ff0c18	883	*/
mbed_official	146:f64d43ff0c18	884
mbed_official	146:f64d43ff0c18	885	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	886	// HW_CAU_XOR_CA - General Purpose Register 0 - Exclusive Or command
mbed_official	146:f64d43ff0c18	887	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	888
mbed_official	146:f64d43ff0c18	889	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	890	/*!
mbed_official	146:f64d43ff0c18	891	* @brief HW_CAU_XOR_CA - General Purpose Register 0 - Exclusive Or command (WO)
mbed_official	146:f64d43ff0c18	892	*
mbed_official	146:f64d43ff0c18	893	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	894	*/
mbed_official	146:f64d43ff0c18	895	typedef union _hw_cau_xor_ca
mbed_official	146:f64d43ff0c18	896	{
mbed_official	146:f64d43ff0c18	897	uint32_t U;
mbed_official	146:f64d43ff0c18	898	struct _hw_cau_xor_ca_bitfields
mbed_official	146:f64d43ff0c18	899	{
mbed_official	146:f64d43ff0c18	900	uint32_t RESERVED0 : 32; //!< [31:0]
mbed_official	146:f64d43ff0c18	901	} B;
mbed_official	146:f64d43ff0c18	902	} hw_cau_xor_ca_t;
mbed_official	146:f64d43ff0c18	903	#endif
mbed_official	146:f64d43ff0c18	904
mbed_official	146:f64d43ff0c18	905	/*!
mbed_official	146:f64d43ff0c18	906	* @name Constants and macros for entire CAU_XOR_CA register
mbed_official	146:f64d43ff0c18	907	*/
mbed_official	146:f64d43ff0c18	908	//@{
mbed_official	146:f64d43ff0c18	909	#define HW_CAU_XOR_CA_COUNT (9U)
mbed_official	146:f64d43ff0c18	910
mbed_official	146:f64d43ff0c18	911	#define HW_CAU_XOR_CA_ADDR(n) (REGS_CAU_BASE + 0x988U + (0x4U * n))
mbed_official	146:f64d43ff0c18	912
mbed_official	146:f64d43ff0c18	913	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	914	#define HW_CAU_XOR_CA(n) ((__O hw_cau_xor_ca_t ) HW_CAU_XOR_CA_ADDR(n))
mbed_official	146:f64d43ff0c18	915	#define HW_CAU_XOR_CA_WR(n, v) (HW_CAU_XOR_CA(n).U = (v))
mbed_official	146:f64d43ff0c18	916	#endif
mbed_official	146:f64d43ff0c18	917	//@}
mbed_official	146:f64d43ff0c18	918
mbed_official	146:f64d43ff0c18	919	/*
mbed_official	146:f64d43ff0c18	920	* Constants & macros for individual CAU_XOR_CA bitfields
mbed_official	146:f64d43ff0c18	921	*/
mbed_official	146:f64d43ff0c18	922
mbed_official	146:f64d43ff0c18	923	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	924	// HW_CAU_ROTL_CASR - Status register - Rotate Left command
mbed_official	146:f64d43ff0c18	925	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	926
mbed_official	146:f64d43ff0c18	927	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	928	/*!
mbed_official	146:f64d43ff0c18	929	* @brief HW_CAU_ROTL_CASR - Status register - Rotate Left command (WO)
mbed_official	146:f64d43ff0c18	930	*
mbed_official	146:f64d43ff0c18	931	* Reset value: 0x20000000U
mbed_official	146:f64d43ff0c18	932	*/
mbed_official	146:f64d43ff0c18	933	typedef union _hw_cau_rotl_casr
mbed_official	146:f64d43ff0c18	934	{
mbed_official	146:f64d43ff0c18	935	uint32_t U;
mbed_official	146:f64d43ff0c18	936	struct _hw_cau_rotl_casr_bitfields
mbed_official	146:f64d43ff0c18	937	{
mbed_official	146:f64d43ff0c18	938	uint32_t IC : 1; //!< [0]
mbed_official	146:f64d43ff0c18	939	uint32_t DPE : 1; //!< [1]
mbed_official	146:f64d43ff0c18	940	uint32_t RESERVED0 : 26; //!< [27:2]
mbed_official	146:f64d43ff0c18	941	uint32_t VER : 4; //!< [31:28] CAU version
mbed_official	146:f64d43ff0c18	942	} B;
mbed_official	146:f64d43ff0c18	943	} hw_cau_rotl_casr_t;
mbed_official	146:f64d43ff0c18	944	#endif
mbed_official	146:f64d43ff0c18	945
mbed_official	146:f64d43ff0c18	946	/*!
mbed_official	146:f64d43ff0c18	947	* @name Constants and macros for entire CAU_ROTL_CASR register
mbed_official	146:f64d43ff0c18	948	*/
mbed_official	146:f64d43ff0c18	949	//@{
mbed_official	146:f64d43ff0c18	950	#define HW_CAU_ROTL_CASR_ADDR (REGS_CAU_BASE + 0x9C0U)
mbed_official	146:f64d43ff0c18	951
mbed_official	146:f64d43ff0c18	952	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	953	#define HW_CAU_ROTL_CASR ((__O hw_cau_rotl_casr_t ) HW_CAU_ROTL_CASR_ADDR)
mbed_official	146:f64d43ff0c18	954	#define HW_CAU_ROTL_CASR_WR(v) (HW_CAU_ROTL_CASR.U = (v))
mbed_official	146:f64d43ff0c18	955	#endif
mbed_official	146:f64d43ff0c18	956	//@}
mbed_official	146:f64d43ff0c18	957
mbed_official	146:f64d43ff0c18	958	/*
mbed_official	146:f64d43ff0c18	959	* Constants & macros for individual CAU_ROTL_CASR bitfields
mbed_official	146:f64d43ff0c18	960	*/
mbed_official	146:f64d43ff0c18	961
mbed_official	146:f64d43ff0c18	962	/*!
mbed_official	146:f64d43ff0c18	963	* @name Register CAU_ROTL_CASR, field IC[0] (WO)
mbed_official	146:f64d43ff0c18	964	*
mbed_official	146:f64d43ff0c18	965	* Values:
mbed_official	146:f64d43ff0c18	966	* - 0 - No illegal commands issued
mbed_official	146:f64d43ff0c18	967	* - 1 - Illegal command issued
mbed_official	146:f64d43ff0c18	968	*/
mbed_official	146:f64d43ff0c18	969	//@{
mbed_official	146:f64d43ff0c18	970	#define BP_CAU_ROTL_CASR_IC (0U) //!< Bit position for CAU_ROTL_CASR_IC.
mbed_official	146:f64d43ff0c18	971	#define BM_CAU_ROTL_CASR_IC (0x00000001U) //!< Bit mask for CAU_ROTL_CASR_IC.
mbed_official	146:f64d43ff0c18	972	#define BS_CAU_ROTL_CASR_IC (1U) //!< Bit field size in bits for CAU_ROTL_CASR_IC.
mbed_official	146:f64d43ff0c18	973
mbed_official	146:f64d43ff0c18	974	//! @brief Format value for bitfield CAU_ROTL_CASR_IC.
mbed_official	146:f64d43ff0c18	975	#define BF_CAU_ROTL_CASR_IC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_ROTL_CASR_IC), uint32_t) & BM_CAU_ROTL_CASR_IC)
mbed_official	146:f64d43ff0c18	976	//@}
mbed_official	146:f64d43ff0c18	977
mbed_official	146:f64d43ff0c18	978	/*!
mbed_official	146:f64d43ff0c18	979	* @name Register CAU_ROTL_CASR, field DPE[1] (WO)
mbed_official	146:f64d43ff0c18	980	*
mbed_official	146:f64d43ff0c18	981	* Values:
mbed_official	146:f64d43ff0c18	982	* - 0 - No error detected
mbed_official	146:f64d43ff0c18	983	* - 1 - DES key parity error detected
mbed_official	146:f64d43ff0c18	984	*/
mbed_official	146:f64d43ff0c18	985	//@{
mbed_official	146:f64d43ff0c18	986	#define BP_CAU_ROTL_CASR_DPE (1U) //!< Bit position for CAU_ROTL_CASR_DPE.
mbed_official	146:f64d43ff0c18	987	#define BM_CAU_ROTL_CASR_DPE (0x00000002U) //!< Bit mask for CAU_ROTL_CASR_DPE.
mbed_official	146:f64d43ff0c18	988	#define BS_CAU_ROTL_CASR_DPE (1U) //!< Bit field size in bits for CAU_ROTL_CASR_DPE.
mbed_official	146:f64d43ff0c18	989
mbed_official	146:f64d43ff0c18	990	//! @brief Format value for bitfield CAU_ROTL_CASR_DPE.
mbed_official	146:f64d43ff0c18	991	#define BF_CAU_ROTL_CASR_DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_ROTL_CASR_DPE), uint32_t) & BM_CAU_ROTL_CASR_DPE)
mbed_official	146:f64d43ff0c18	992	//@}
mbed_official	146:f64d43ff0c18	993
mbed_official	146:f64d43ff0c18	994	/*!
mbed_official	146:f64d43ff0c18	995	* @name Register CAU_ROTL_CASR, field VER[31:28] (WO)
mbed_official	146:f64d43ff0c18	996	*
mbed_official	146:f64d43ff0c18	997	* Values:
mbed_official	146:f64d43ff0c18	998	* - 0001 - Initial CAU version
mbed_official	146:f64d43ff0c18	999	* - 0010 - Second version, added support for SHA-256 algorithm.(This is the
mbed_official	146:f64d43ff0c18	1000	* value on this device)
mbed_official	146:f64d43ff0c18	1001	*/
mbed_official	146:f64d43ff0c18	1002	//@{
mbed_official	146:f64d43ff0c18	1003	#define BP_CAU_ROTL_CASR_VER (28U) //!< Bit position for CAU_ROTL_CASR_VER.
mbed_official	146:f64d43ff0c18	1004	#define BM_CAU_ROTL_CASR_VER (0xF0000000U) //!< Bit mask for CAU_ROTL_CASR_VER.
mbed_official	146:f64d43ff0c18	1005	#define BS_CAU_ROTL_CASR_VER (4U) //!< Bit field size in bits for CAU_ROTL_CASR_VER.
mbed_official	146:f64d43ff0c18	1006
mbed_official	146:f64d43ff0c18	1007	//! @brief Format value for bitfield CAU_ROTL_CASR_VER.
mbed_official	146:f64d43ff0c18	1008	#define BF_CAU_ROTL_CASR_VER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_ROTL_CASR_VER), uint32_t) & BM_CAU_ROTL_CASR_VER)
mbed_official	146:f64d43ff0c18	1009	//@}
mbed_official	146:f64d43ff0c18	1010
mbed_official	146:f64d43ff0c18	1011	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1012	// HW_CAU_ROTL_CAA - Accumulator register - Rotate Left command
mbed_official	146:f64d43ff0c18	1013	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1014
mbed_official	146:f64d43ff0c18	1015	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1016	/*!
mbed_official	146:f64d43ff0c18	1017	* @brief HW_CAU_ROTL_CAA - Accumulator register - Rotate Left command (WO)
mbed_official	146:f64d43ff0c18	1018	*
mbed_official	146:f64d43ff0c18	1019	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	1020	*/
mbed_official	146:f64d43ff0c18	1021	typedef union _hw_cau_rotl_caa
mbed_official	146:f64d43ff0c18	1022	{
mbed_official	146:f64d43ff0c18	1023	uint32_t U;
mbed_official	146:f64d43ff0c18	1024	struct _hw_cau_rotl_caa_bitfields
mbed_official	146:f64d43ff0c18	1025	{
mbed_official	146:f64d43ff0c18	1026	uint32_t RESERVED0 : 32; //!< [31:0]
mbed_official	146:f64d43ff0c18	1027	} B;
mbed_official	146:f64d43ff0c18	1028	} hw_cau_rotl_caa_t;
mbed_official	146:f64d43ff0c18	1029	#endif
mbed_official	146:f64d43ff0c18	1030
mbed_official	146:f64d43ff0c18	1031	/*!
mbed_official	146:f64d43ff0c18	1032	* @name Constants and macros for entire CAU_ROTL_CAA register
mbed_official	146:f64d43ff0c18	1033	*/
mbed_official	146:f64d43ff0c18	1034	//@{
mbed_official	146:f64d43ff0c18	1035	#define HW_CAU_ROTL_CAA_ADDR (REGS_CAU_BASE + 0x9C4U)
mbed_official	146:f64d43ff0c18	1036
mbed_official	146:f64d43ff0c18	1037	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1038	#define HW_CAU_ROTL_CAA ((__O hw_cau_rotl_caa_t ) HW_CAU_ROTL_CAA_ADDR)
mbed_official	146:f64d43ff0c18	1039	#define HW_CAU_ROTL_CAA_WR(v) (HW_CAU_ROTL_CAA.U = (v))
mbed_official	146:f64d43ff0c18	1040	#endif
mbed_official	146:f64d43ff0c18	1041	//@}
mbed_official	146:f64d43ff0c18	1042
mbed_official	146:f64d43ff0c18	1043	/*
mbed_official	146:f64d43ff0c18	1044	* Constants & macros for individual CAU_ROTL_CAA bitfields
mbed_official	146:f64d43ff0c18	1045	*/
mbed_official	146:f64d43ff0c18	1046
mbed_official	146:f64d43ff0c18	1047	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1048	// HW_CAU_ROTL_CA - General Purpose Register 0 - Rotate Left command
mbed_official	146:f64d43ff0c18	1049	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1050
mbed_official	146:f64d43ff0c18	1051	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1052	/*!
mbed_official	146:f64d43ff0c18	1053	* @brief HW_CAU_ROTL_CA - General Purpose Register 0 - Rotate Left command (WO)
mbed_official	146:f64d43ff0c18	1054	*
mbed_official	146:f64d43ff0c18	1055	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	1056	*/
mbed_official	146:f64d43ff0c18	1057	typedef union _hw_cau_rotl_ca
mbed_official	146:f64d43ff0c18	1058	{
mbed_official	146:f64d43ff0c18	1059	uint32_t U;
mbed_official	146:f64d43ff0c18	1060	struct _hw_cau_rotl_ca_bitfields
mbed_official	146:f64d43ff0c18	1061	{
mbed_official	146:f64d43ff0c18	1062	uint32_t RESERVED0 : 32; //!< [31:0]
mbed_official	146:f64d43ff0c18	1063	} B;
mbed_official	146:f64d43ff0c18	1064	} hw_cau_rotl_ca_t;
mbed_official	146:f64d43ff0c18	1065	#endif
mbed_official	146:f64d43ff0c18	1066
mbed_official	146:f64d43ff0c18	1067	/*!
mbed_official	146:f64d43ff0c18	1068	* @name Constants and macros for entire CAU_ROTL_CA register
mbed_official	146:f64d43ff0c18	1069	*/
mbed_official	146:f64d43ff0c18	1070	//@{
mbed_official	146:f64d43ff0c18	1071	#define HW_CAU_ROTL_CA_COUNT (9U)
mbed_official	146:f64d43ff0c18	1072
mbed_official	146:f64d43ff0c18	1073	#define HW_CAU_ROTL_CA_ADDR(n) (REGS_CAU_BASE + 0x9C8U + (0x4U * n))
mbed_official	146:f64d43ff0c18	1074
mbed_official	146:f64d43ff0c18	1075	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1076	#define HW_CAU_ROTL_CA(n) ((__O hw_cau_rotl_ca_t ) HW_CAU_ROTL_CA_ADDR(n))
mbed_official	146:f64d43ff0c18	1077	#define HW_CAU_ROTL_CA_WR(n, v) (HW_CAU_ROTL_CA(n).U = (v))
mbed_official	146:f64d43ff0c18	1078	#endif
mbed_official	146:f64d43ff0c18	1079	//@}
mbed_official	146:f64d43ff0c18	1080
mbed_official	146:f64d43ff0c18	1081	/*
mbed_official	146:f64d43ff0c18	1082	* Constants & macros for individual CAU_ROTL_CA bitfields
mbed_official	146:f64d43ff0c18	1083	*/
mbed_official	146:f64d43ff0c18	1084
mbed_official	146:f64d43ff0c18	1085	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1086	// HW_CAU_AESC_CASR - Status register - AES Column Operation command
mbed_official	146:f64d43ff0c18	1087	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1088
mbed_official	146:f64d43ff0c18	1089	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1090	/*!
mbed_official	146:f64d43ff0c18	1091	* @brief HW_CAU_AESC_CASR - Status register - AES Column Operation command (WO)
mbed_official	146:f64d43ff0c18	1092	*
mbed_official	146:f64d43ff0c18	1093	* Reset value: 0x20000000U
mbed_official	146:f64d43ff0c18	1094	*/
mbed_official	146:f64d43ff0c18	1095	typedef union _hw_cau_aesc_casr
mbed_official	146:f64d43ff0c18	1096	{
mbed_official	146:f64d43ff0c18	1097	uint32_t U;
mbed_official	146:f64d43ff0c18	1098	struct _hw_cau_aesc_casr_bitfields
mbed_official	146:f64d43ff0c18	1099	{
mbed_official	146:f64d43ff0c18	1100	uint32_t IC : 1; //!< [0]
mbed_official	146:f64d43ff0c18	1101	uint32_t DPE : 1; //!< [1]
mbed_official	146:f64d43ff0c18	1102	uint32_t RESERVED0 : 26; //!< [27:2]
mbed_official	146:f64d43ff0c18	1103	uint32_t VER : 4; //!< [31:28] CAU version
mbed_official	146:f64d43ff0c18	1104	} B;
mbed_official	146:f64d43ff0c18	1105	} hw_cau_aesc_casr_t;
mbed_official	146:f64d43ff0c18	1106	#endif
mbed_official	146:f64d43ff0c18	1107
mbed_official	146:f64d43ff0c18	1108	/*!
mbed_official	146:f64d43ff0c18	1109	* @name Constants and macros for entire CAU_AESC_CASR register
mbed_official	146:f64d43ff0c18	1110	*/
mbed_official	146:f64d43ff0c18	1111	//@{
mbed_official	146:f64d43ff0c18	1112	#define HW_CAU_AESC_CASR_ADDR (REGS_CAU_BASE + 0xB00U)
mbed_official	146:f64d43ff0c18	1113
mbed_official	146:f64d43ff0c18	1114	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1115	#define HW_CAU_AESC_CASR ((__O hw_cau_aesc_casr_t ) HW_CAU_AESC_CASR_ADDR)
mbed_official	146:f64d43ff0c18	1116	#define HW_CAU_AESC_CASR_WR(v) (HW_CAU_AESC_CASR.U = (v))
mbed_official	146:f64d43ff0c18	1117	#endif
mbed_official	146:f64d43ff0c18	1118	//@}
mbed_official	146:f64d43ff0c18	1119
mbed_official	146:f64d43ff0c18	1120	/*
mbed_official	146:f64d43ff0c18	1121	* Constants & macros for individual CAU_AESC_CASR bitfields
mbed_official	146:f64d43ff0c18	1122	*/
mbed_official	146:f64d43ff0c18	1123
mbed_official	146:f64d43ff0c18	1124	/*!
mbed_official	146:f64d43ff0c18	1125	* @name Register CAU_AESC_CASR, field IC[0] (WO)
mbed_official	146:f64d43ff0c18	1126	*
mbed_official	146:f64d43ff0c18	1127	* Values:
mbed_official	146:f64d43ff0c18	1128	* - 0 - No illegal commands issued
mbed_official	146:f64d43ff0c18	1129	* - 1 - Illegal command issued
mbed_official	146:f64d43ff0c18	1130	*/
mbed_official	146:f64d43ff0c18	1131	//@{
mbed_official	146:f64d43ff0c18	1132	#define BP_CAU_AESC_CASR_IC (0U) //!< Bit position for CAU_AESC_CASR_IC.
mbed_official	146:f64d43ff0c18	1133	#define BM_CAU_AESC_CASR_IC (0x00000001U) //!< Bit mask for CAU_AESC_CASR_IC.
mbed_official	146:f64d43ff0c18	1134	#define BS_CAU_AESC_CASR_IC (1U) //!< Bit field size in bits for CAU_AESC_CASR_IC.
mbed_official	146:f64d43ff0c18	1135
mbed_official	146:f64d43ff0c18	1136	//! @brief Format value for bitfield CAU_AESC_CASR_IC.
mbed_official	146:f64d43ff0c18	1137	#define BF_CAU_AESC_CASR_IC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_AESC_CASR_IC), uint32_t) & BM_CAU_AESC_CASR_IC)
mbed_official	146:f64d43ff0c18	1138	//@}
mbed_official	146:f64d43ff0c18	1139
mbed_official	146:f64d43ff0c18	1140	/*!
mbed_official	146:f64d43ff0c18	1141	* @name Register CAU_AESC_CASR, field DPE[1] (WO)
mbed_official	146:f64d43ff0c18	1142	*
mbed_official	146:f64d43ff0c18	1143	* Values:
mbed_official	146:f64d43ff0c18	1144	* - 0 - No error detected
mbed_official	146:f64d43ff0c18	1145	* - 1 - DES key parity error detected
mbed_official	146:f64d43ff0c18	1146	*/
mbed_official	146:f64d43ff0c18	1147	//@{
mbed_official	146:f64d43ff0c18	1148	#define BP_CAU_AESC_CASR_DPE (1U) //!< Bit position for CAU_AESC_CASR_DPE.
mbed_official	146:f64d43ff0c18	1149	#define BM_CAU_AESC_CASR_DPE (0x00000002U) //!< Bit mask for CAU_AESC_CASR_DPE.
mbed_official	146:f64d43ff0c18	1150	#define BS_CAU_AESC_CASR_DPE (1U) //!< Bit field size in bits for CAU_AESC_CASR_DPE.
mbed_official	146:f64d43ff0c18	1151
mbed_official	146:f64d43ff0c18	1152	//! @brief Format value for bitfield CAU_AESC_CASR_DPE.
mbed_official	146:f64d43ff0c18	1153	#define BF_CAU_AESC_CASR_DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_AESC_CASR_DPE), uint32_t) & BM_CAU_AESC_CASR_DPE)
mbed_official	146:f64d43ff0c18	1154	//@}
mbed_official	146:f64d43ff0c18	1155
mbed_official	146:f64d43ff0c18	1156	/*!
mbed_official	146:f64d43ff0c18	1157	* @name Register CAU_AESC_CASR, field VER[31:28] (WO)
mbed_official	146:f64d43ff0c18	1158	*
mbed_official	146:f64d43ff0c18	1159	* Values:
mbed_official	146:f64d43ff0c18	1160	* - 0001 - Initial CAU version
mbed_official	146:f64d43ff0c18	1161	* - 0010 - Second version, added support for SHA-256 algorithm.(This is the
mbed_official	146:f64d43ff0c18	1162	* value on this device)
mbed_official	146:f64d43ff0c18	1163	*/
mbed_official	146:f64d43ff0c18	1164	//@{
mbed_official	146:f64d43ff0c18	1165	#define BP_CAU_AESC_CASR_VER (28U) //!< Bit position for CAU_AESC_CASR_VER.
mbed_official	146:f64d43ff0c18	1166	#define BM_CAU_AESC_CASR_VER (0xF0000000U) //!< Bit mask for CAU_AESC_CASR_VER.
mbed_official	146:f64d43ff0c18	1167	#define BS_CAU_AESC_CASR_VER (4U) //!< Bit field size in bits for CAU_AESC_CASR_VER.
mbed_official	146:f64d43ff0c18	1168
mbed_official	146:f64d43ff0c18	1169	//! @brief Format value for bitfield CAU_AESC_CASR_VER.
mbed_official	146:f64d43ff0c18	1170	#define BF_CAU_AESC_CASR_VER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_AESC_CASR_VER), uint32_t) & BM_CAU_AESC_CASR_VER)
mbed_official	146:f64d43ff0c18	1171	//@}
mbed_official	146:f64d43ff0c18	1172
mbed_official	146:f64d43ff0c18	1173	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1174	// HW_CAU_AESC_CAA - Accumulator register - AES Column Operation command
mbed_official	146:f64d43ff0c18	1175	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1176
mbed_official	146:f64d43ff0c18	1177	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1178	/*!
mbed_official	146:f64d43ff0c18	1179	* @brief HW_CAU_AESC_CAA - Accumulator register - AES Column Operation command (WO)
mbed_official	146:f64d43ff0c18	1180	*
mbed_official	146:f64d43ff0c18	1181	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	1182	*/
mbed_official	146:f64d43ff0c18	1183	typedef union _hw_cau_aesc_caa
mbed_official	146:f64d43ff0c18	1184	{
mbed_official	146:f64d43ff0c18	1185	uint32_t U;
mbed_official	146:f64d43ff0c18	1186	struct _hw_cau_aesc_caa_bitfields
mbed_official	146:f64d43ff0c18	1187	{
mbed_official	146:f64d43ff0c18	1188	uint32_t RESERVED0 : 32; //!< [31:0]
mbed_official	146:f64d43ff0c18	1189	} B;
mbed_official	146:f64d43ff0c18	1190	} hw_cau_aesc_caa_t;
mbed_official	146:f64d43ff0c18	1191	#endif
mbed_official	146:f64d43ff0c18	1192
mbed_official	146:f64d43ff0c18	1193	/*!
mbed_official	146:f64d43ff0c18	1194	* @name Constants and macros for entire CAU_AESC_CAA register
mbed_official	146:f64d43ff0c18	1195	*/
mbed_official	146:f64d43ff0c18	1196	//@{
mbed_official	146:f64d43ff0c18	1197	#define HW_CAU_AESC_CAA_ADDR (REGS_CAU_BASE + 0xB04U)
mbed_official	146:f64d43ff0c18	1198
mbed_official	146:f64d43ff0c18	1199	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1200	#define HW_CAU_AESC_CAA ((__O hw_cau_aesc_caa_t ) HW_CAU_AESC_CAA_ADDR)
mbed_official	146:f64d43ff0c18	1201	#define HW_CAU_AESC_CAA_WR(v) (HW_CAU_AESC_CAA.U = (v))
mbed_official	146:f64d43ff0c18	1202	#endif
mbed_official	146:f64d43ff0c18	1203	//@}
mbed_official	146:f64d43ff0c18	1204
mbed_official	146:f64d43ff0c18	1205	/*
mbed_official	146:f64d43ff0c18	1206	* Constants & macros for individual CAU_AESC_CAA bitfields
mbed_official	146:f64d43ff0c18	1207	*/
mbed_official	146:f64d43ff0c18	1208
mbed_official	146:f64d43ff0c18	1209	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1210	// HW_CAU_AESC_CA - General Purpose Register 0 - AES Column Operation command
mbed_official	146:f64d43ff0c18	1211	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1212
mbed_official	146:f64d43ff0c18	1213	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1214	/*!
mbed_official	146:f64d43ff0c18	1215	* @brief HW_CAU_AESC_CA - General Purpose Register 0 - AES Column Operation command (WO)
mbed_official	146:f64d43ff0c18	1216	*
mbed_official	146:f64d43ff0c18	1217	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	1218	*/
mbed_official	146:f64d43ff0c18	1219	typedef union _hw_cau_aesc_ca
mbed_official	146:f64d43ff0c18	1220	{
mbed_official	146:f64d43ff0c18	1221	uint32_t U;
mbed_official	146:f64d43ff0c18	1222	struct _hw_cau_aesc_ca_bitfields
mbed_official	146:f64d43ff0c18	1223	{
mbed_official	146:f64d43ff0c18	1224	uint32_t RESERVED0 : 32; //!< [31:0]
mbed_official	146:f64d43ff0c18	1225	} B;
mbed_official	146:f64d43ff0c18	1226	} hw_cau_aesc_ca_t;
mbed_official	146:f64d43ff0c18	1227	#endif
mbed_official	146:f64d43ff0c18	1228
mbed_official	146:f64d43ff0c18	1229	/*!
mbed_official	146:f64d43ff0c18	1230	* @name Constants and macros for entire CAU_AESC_CA register
mbed_official	146:f64d43ff0c18	1231	*/
mbed_official	146:f64d43ff0c18	1232	//@{
mbed_official	146:f64d43ff0c18	1233	#define HW_CAU_AESC_CA_COUNT (9U)
mbed_official	146:f64d43ff0c18	1234
mbed_official	146:f64d43ff0c18	1235	#define HW_CAU_AESC_CA_ADDR(n) (REGS_CAU_BASE + 0xB08U + (0x4U * n))
mbed_official	146:f64d43ff0c18	1236
mbed_official	146:f64d43ff0c18	1237	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1238	#define HW_CAU_AESC_CA(n) ((__O hw_cau_aesc_ca_t ) HW_CAU_AESC_CA_ADDR(n))
mbed_official	146:f64d43ff0c18	1239	#define HW_CAU_AESC_CA_WR(n, v) (HW_CAU_AESC_CA(n).U = (v))
mbed_official	146:f64d43ff0c18	1240	#endif
mbed_official	146:f64d43ff0c18	1241	//@}
mbed_official	146:f64d43ff0c18	1242
mbed_official	146:f64d43ff0c18	1243	/*
mbed_official	146:f64d43ff0c18	1244	* Constants & macros for individual CAU_AESC_CA bitfields
mbed_official	146:f64d43ff0c18	1245	*/
mbed_official	146:f64d43ff0c18	1246
mbed_official	146:f64d43ff0c18	1247	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1248	// HW_CAU_AESIC_CASR - Status register - AES Inverse Column Operation command
mbed_official	146:f64d43ff0c18	1249	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1250
mbed_official	146:f64d43ff0c18	1251	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1252	/*!
mbed_official	146:f64d43ff0c18	1253	* @brief HW_CAU_AESIC_CASR - Status register - AES Inverse Column Operation command (WO)
mbed_official	146:f64d43ff0c18	1254	*
mbed_official	146:f64d43ff0c18	1255	* Reset value: 0x20000000U
mbed_official	146:f64d43ff0c18	1256	*/
mbed_official	146:f64d43ff0c18	1257	typedef union _hw_cau_aesic_casr
mbed_official	146:f64d43ff0c18	1258	{
mbed_official	146:f64d43ff0c18	1259	uint32_t U;
mbed_official	146:f64d43ff0c18	1260	struct _hw_cau_aesic_casr_bitfields
mbed_official	146:f64d43ff0c18	1261	{
mbed_official	146:f64d43ff0c18	1262	uint32_t IC : 1; //!< [0]
mbed_official	146:f64d43ff0c18	1263	uint32_t DPE : 1; //!< [1]
mbed_official	146:f64d43ff0c18	1264	uint32_t RESERVED0 : 26; //!< [27:2]
mbed_official	146:f64d43ff0c18	1265	uint32_t VER : 4; //!< [31:28] CAU version
mbed_official	146:f64d43ff0c18	1266	} B;
mbed_official	146:f64d43ff0c18	1267	} hw_cau_aesic_casr_t;
mbed_official	146:f64d43ff0c18	1268	#endif
mbed_official	146:f64d43ff0c18	1269
mbed_official	146:f64d43ff0c18	1270	/*!
mbed_official	146:f64d43ff0c18	1271	* @name Constants and macros for entire CAU_AESIC_CASR register
mbed_official	146:f64d43ff0c18	1272	*/
mbed_official	146:f64d43ff0c18	1273	//@{
mbed_official	146:f64d43ff0c18	1274	#define HW_CAU_AESIC_CASR_ADDR (REGS_CAU_BASE + 0xB40U)
mbed_official	146:f64d43ff0c18	1275
mbed_official	146:f64d43ff0c18	1276	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1277	#define HW_CAU_AESIC_CASR ((__O hw_cau_aesic_casr_t ) HW_CAU_AESIC_CASR_ADDR)
mbed_official	146:f64d43ff0c18	1278	#define HW_CAU_AESIC_CASR_WR(v) (HW_CAU_AESIC_CASR.U = (v))
mbed_official	146:f64d43ff0c18	1279	#endif
mbed_official	146:f64d43ff0c18	1280	//@}
mbed_official	146:f64d43ff0c18	1281
mbed_official	146:f64d43ff0c18	1282	/*
mbed_official	146:f64d43ff0c18	1283	* Constants & macros for individual CAU_AESIC_CASR bitfields
mbed_official	146:f64d43ff0c18	1284	*/
mbed_official	146:f64d43ff0c18	1285
mbed_official	146:f64d43ff0c18	1286	/*!
mbed_official	146:f64d43ff0c18	1287	* @name Register CAU_AESIC_CASR, field IC[0] (WO)
mbed_official	146:f64d43ff0c18	1288	*
mbed_official	146:f64d43ff0c18	1289	* Values:
mbed_official	146:f64d43ff0c18	1290	* - 0 - No illegal commands issued
mbed_official	146:f64d43ff0c18	1291	* - 1 - Illegal command issued
mbed_official	146:f64d43ff0c18	1292	*/
mbed_official	146:f64d43ff0c18	1293	//@{
mbed_official	146:f64d43ff0c18	1294	#define BP_CAU_AESIC_CASR_IC (0U) //!< Bit position for CAU_AESIC_CASR_IC.
mbed_official	146:f64d43ff0c18	1295	#define BM_CAU_AESIC_CASR_IC (0x00000001U) //!< Bit mask for CAU_AESIC_CASR_IC.
mbed_official	146:f64d43ff0c18	1296	#define BS_CAU_AESIC_CASR_IC (1U) //!< Bit field size in bits for CAU_AESIC_CASR_IC.
mbed_official	146:f64d43ff0c18	1297
mbed_official	146:f64d43ff0c18	1298	//! @brief Format value for bitfield CAU_AESIC_CASR_IC.
mbed_official	146:f64d43ff0c18	1299	#define BF_CAU_AESIC_CASR_IC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_AESIC_CASR_IC), uint32_t) & BM_CAU_AESIC_CASR_IC)
mbed_official	146:f64d43ff0c18	1300	//@}
mbed_official	146:f64d43ff0c18	1301
mbed_official	146:f64d43ff0c18	1302	/*!
mbed_official	146:f64d43ff0c18	1303	* @name Register CAU_AESIC_CASR, field DPE[1] (WO)
mbed_official	146:f64d43ff0c18	1304	*
mbed_official	146:f64d43ff0c18	1305	* Values:
mbed_official	146:f64d43ff0c18	1306	* - 0 - No error detected
mbed_official	146:f64d43ff0c18	1307	* - 1 - DES key parity error detected
mbed_official	146:f64d43ff0c18	1308	*/
mbed_official	146:f64d43ff0c18	1309	//@{
mbed_official	146:f64d43ff0c18	1310	#define BP_CAU_AESIC_CASR_DPE (1U) //!< Bit position for CAU_AESIC_CASR_DPE.
mbed_official	146:f64d43ff0c18	1311	#define BM_CAU_AESIC_CASR_DPE (0x00000002U) //!< Bit mask for CAU_AESIC_CASR_DPE.
mbed_official	146:f64d43ff0c18	1312	#define BS_CAU_AESIC_CASR_DPE (1U) //!< Bit field size in bits for CAU_AESIC_CASR_DPE.
mbed_official	146:f64d43ff0c18	1313
mbed_official	146:f64d43ff0c18	1314	//! @brief Format value for bitfield CAU_AESIC_CASR_DPE.
mbed_official	146:f64d43ff0c18	1315	#define BF_CAU_AESIC_CASR_DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_AESIC_CASR_DPE), uint32_t) & BM_CAU_AESIC_CASR_DPE)
mbed_official	146:f64d43ff0c18	1316	//@}
mbed_official	146:f64d43ff0c18	1317
mbed_official	146:f64d43ff0c18	1318	/*!
mbed_official	146:f64d43ff0c18	1319	* @name Register CAU_AESIC_CASR, field VER[31:28] (WO)
mbed_official	146:f64d43ff0c18	1320	*
mbed_official	146:f64d43ff0c18	1321	* Values:
mbed_official	146:f64d43ff0c18	1322	* - 0001 - Initial CAU version
mbed_official	146:f64d43ff0c18	1323	* - 0010 - Second version, added support for SHA-256 algorithm.(This is the
mbed_official	146:f64d43ff0c18	1324	* value on this device)
mbed_official	146:f64d43ff0c18	1325	*/
mbed_official	146:f64d43ff0c18	1326	//@{
mbed_official	146:f64d43ff0c18	1327	#define BP_CAU_AESIC_CASR_VER (28U) //!< Bit position for CAU_AESIC_CASR_VER.
mbed_official	146:f64d43ff0c18	1328	#define BM_CAU_AESIC_CASR_VER (0xF0000000U) //!< Bit mask for CAU_AESIC_CASR_VER.
mbed_official	146:f64d43ff0c18	1329	#define BS_CAU_AESIC_CASR_VER (4U) //!< Bit field size in bits for CAU_AESIC_CASR_VER.
mbed_official	146:f64d43ff0c18	1330
mbed_official	146:f64d43ff0c18	1331	//! @brief Format value for bitfield CAU_AESIC_CASR_VER.
mbed_official	146:f64d43ff0c18	1332	#define BF_CAU_AESIC_CASR_VER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_AESIC_CASR_VER), uint32_t) & BM_CAU_AESIC_CASR_VER)
mbed_official	146:f64d43ff0c18	1333	//@}
mbed_official	146:f64d43ff0c18	1334
mbed_official	146:f64d43ff0c18	1335	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1336	// HW_CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command
mbed_official	146:f64d43ff0c18	1337	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1338
mbed_official	146:f64d43ff0c18	1339	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1340	/*!
mbed_official	146:f64d43ff0c18	1341	* @brief HW_CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command (WO)
mbed_official	146:f64d43ff0c18	1342	*
mbed_official	146:f64d43ff0c18	1343	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	1344	*/
mbed_official	146:f64d43ff0c18	1345	typedef union _hw_cau_aesic_caa
mbed_official	146:f64d43ff0c18	1346	{
mbed_official	146:f64d43ff0c18	1347	uint32_t U;
mbed_official	146:f64d43ff0c18	1348	struct _hw_cau_aesic_caa_bitfields
mbed_official	146:f64d43ff0c18	1349	{
mbed_official	146:f64d43ff0c18	1350	uint32_t RESERVED0 : 32; //!< [31:0]
mbed_official	146:f64d43ff0c18	1351	} B;
mbed_official	146:f64d43ff0c18	1352	} hw_cau_aesic_caa_t;
mbed_official	146:f64d43ff0c18	1353	#endif
mbed_official	146:f64d43ff0c18	1354
mbed_official	146:f64d43ff0c18	1355	/*!
mbed_official	146:f64d43ff0c18	1356	* @name Constants and macros for entire CAU_AESIC_CAA register
mbed_official	146:f64d43ff0c18	1357	*/
mbed_official	146:f64d43ff0c18	1358	//@{
mbed_official	146:f64d43ff0c18	1359	#define HW_CAU_AESIC_CAA_ADDR (REGS_CAU_BASE + 0xB44U)
mbed_official	146:f64d43ff0c18	1360
mbed_official	146:f64d43ff0c18	1361	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1362	#define HW_CAU_AESIC_CAA ((__O hw_cau_aesic_caa_t ) HW_CAU_AESIC_CAA_ADDR)
mbed_official	146:f64d43ff0c18	1363	#define HW_CAU_AESIC_CAA_WR(v) (HW_CAU_AESIC_CAA.U = (v))
mbed_official	146:f64d43ff0c18	1364	#endif
mbed_official	146:f64d43ff0c18	1365	//@}
mbed_official	146:f64d43ff0c18	1366
mbed_official	146:f64d43ff0c18	1367	/*
mbed_official	146:f64d43ff0c18	1368	* Constants & macros for individual CAU_AESIC_CAA bitfields
mbed_official	146:f64d43ff0c18	1369	*/
mbed_official	146:f64d43ff0c18	1370
mbed_official	146:f64d43ff0c18	1371	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1372	// HW_CAU_AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command
mbed_official	146:f64d43ff0c18	1373	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1374
mbed_official	146:f64d43ff0c18	1375	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1376	/*!
mbed_official	146:f64d43ff0c18	1377	* @brief HW_CAU_AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command (WO)
mbed_official	146:f64d43ff0c18	1378	*
mbed_official	146:f64d43ff0c18	1379	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	1380	*/
mbed_official	146:f64d43ff0c18	1381	typedef union _hw_cau_aesic_ca
mbed_official	146:f64d43ff0c18	1382	{
mbed_official	146:f64d43ff0c18	1383	uint32_t U;
mbed_official	146:f64d43ff0c18	1384	struct _hw_cau_aesic_ca_bitfields
mbed_official	146:f64d43ff0c18	1385	{
mbed_official	146:f64d43ff0c18	1386	uint32_t RESERVED0 : 32; //!< [31:0]
mbed_official	146:f64d43ff0c18	1387	} B;
mbed_official	146:f64d43ff0c18	1388	} hw_cau_aesic_ca_t;
mbed_official	146:f64d43ff0c18	1389	#endif
mbed_official	146:f64d43ff0c18	1390
mbed_official	146:f64d43ff0c18	1391	/*!
mbed_official	146:f64d43ff0c18	1392	* @name Constants and macros for entire CAU_AESIC_CA register
mbed_official	146:f64d43ff0c18	1393	*/
mbed_official	146:f64d43ff0c18	1394	//@{
mbed_official	146:f64d43ff0c18	1395	#define HW_CAU_AESIC_CA_COUNT (9U)
mbed_official	146:f64d43ff0c18	1396
mbed_official	146:f64d43ff0c18	1397	#define HW_CAU_AESIC_CA_ADDR(n) (REGS_CAU_BASE + 0xB48U + (0x4U * n))
mbed_official	146:f64d43ff0c18	1398
mbed_official	146:f64d43ff0c18	1399	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1400	#define HW_CAU_AESIC_CA(n) ((__O hw_cau_aesic_ca_t ) HW_CAU_AESIC_CA_ADDR(n))
mbed_official	146:f64d43ff0c18	1401	#define HW_CAU_AESIC_CA_WR(n, v) (HW_CAU_AESIC_CA(n).U = (v))
mbed_official	146:f64d43ff0c18	1402	#endif
mbed_official	146:f64d43ff0c18	1403	//@}
mbed_official	146:f64d43ff0c18	1404
mbed_official	146:f64d43ff0c18	1405	/*
mbed_official	146:f64d43ff0c18	1406	* Constants & macros for individual CAU_AESIC_CA bitfields
mbed_official	146:f64d43ff0c18	1407	*/
mbed_official	146:f64d43ff0c18	1408
mbed_official	146:f64d43ff0c18	1409	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1410	// hw_cau_t - module struct
mbed_official	146:f64d43ff0c18	1411	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1412	/*!
mbed_official	146:f64d43ff0c18	1413	* @brief All CAU module registers.
mbed_official	146:f64d43ff0c18	1414	*/
mbed_official	146:f64d43ff0c18	1415	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1416	#pragma pack(1)
mbed_official	146:f64d43ff0c18	1417	typedef struct _hw_cau
mbed_official	146:f64d43ff0c18	1418	{
mbed_official	146:f64d43ff0c18	1419	__O hw_cau_direct_t DIRECT[16]; //!< [0x0] Direct access register 0
mbed_official	146:f64d43ff0c18	1420	uint8_t _reserved0[2048];
mbed_official	146:f64d43ff0c18	1421	__O hw_cau_ldr_casr_t LDR_CASR; //!< [0x840] Status register - Load Register command
mbed_official	146:f64d43ff0c18	1422	__O hw_cau_ldr_caa_t LDR_CAA; //!< [0x844] Accumulator register - Load Register command
mbed_official	146:f64d43ff0c18	1423	__O hw_cau_ldr_ca_t LDR_CA[9]; //!< [0x848] General Purpose Register 0 - Load Register command
mbed_official	146:f64d43ff0c18	1424	uint8_t _reserved1[20];
mbed_official	146:f64d43ff0c18	1425	__I hw_cau_str_casr_t STR_CASR; //!< [0x880] Status register - Store Register command
mbed_official	146:f64d43ff0c18	1426	__I hw_cau_str_caa_t STR_CAA; //!< [0x884] Accumulator register - Store Register command
mbed_official	146:f64d43ff0c18	1427	__I hw_cau_str_ca_t STR_CA[9]; //!< [0x888] General Purpose Register 0 - Store Register command
mbed_official	146:f64d43ff0c18	1428	uint8_t _reserved2[20];
mbed_official	146:f64d43ff0c18	1429	__O hw_cau_adr_casr_t ADR_CASR; //!< [0x8C0] Status register - Add Register command
mbed_official	146:f64d43ff0c18	1430	__O hw_cau_adr_caa_t ADR_CAA; //!< [0x8C4] Accumulator register - Add to register command
mbed_official	146:f64d43ff0c18	1431	__O hw_cau_adr_ca_t ADR_CA[9]; //!< [0x8C8] General Purpose Register 0 - Add to register command
mbed_official	146:f64d43ff0c18	1432	uint8_t _reserved3[20];
mbed_official	146:f64d43ff0c18	1433	__O hw_cau_radr_casr_t RADR_CASR; //!< [0x900] Status register - Reverse and Add to Register command
mbed_official	146:f64d43ff0c18	1434	__O hw_cau_radr_caa_t RADR_CAA; //!< [0x904] Accumulator register - Reverse and Add to Register command
mbed_official	146:f64d43ff0c18	1435	__O hw_cau_radr_ca_t RADR_CA[9]; //!< [0x908] General Purpose Register 0 - Reverse and Add to Register command
mbed_official	146:f64d43ff0c18	1436	uint8_t _reserved4[84];
mbed_official	146:f64d43ff0c18	1437	__O hw_cau_xor_casr_t XOR_CASR; //!< [0x980] Status register - Exclusive Or command
mbed_official	146:f64d43ff0c18	1438	__O hw_cau_xor_caa_t XOR_CAA; //!< [0x984] Accumulator register - Exclusive Or command
mbed_official	146:f64d43ff0c18	1439	__O hw_cau_xor_ca_t XOR_CA[9]; //!< [0x988] General Purpose Register 0 - Exclusive Or command
mbed_official	146:f64d43ff0c18	1440	uint8_t _reserved5[20];
mbed_official	146:f64d43ff0c18	1441	__O hw_cau_rotl_casr_t ROTL_CASR; //!< [0x9C0] Status register - Rotate Left command
mbed_official	146:f64d43ff0c18	1442	__O hw_cau_rotl_caa_t ROTL_CAA; //!< [0x9C4] Accumulator register - Rotate Left command
mbed_official	146:f64d43ff0c18	1443	__O hw_cau_rotl_ca_t ROTL_CA[9]; //!< [0x9C8] General Purpose Register 0 - Rotate Left command
mbed_official	146:f64d43ff0c18	1444	uint8_t _reserved6[276];
mbed_official	146:f64d43ff0c18	1445	__O hw_cau_aesc_casr_t AESC_CASR; //!< [0xB00] Status register - AES Column Operation command
mbed_official	146:f64d43ff0c18	1446	__O hw_cau_aesc_caa_t AESC_CAA; //!< [0xB04] Accumulator register - AES Column Operation command
mbed_official	146:f64d43ff0c18	1447	__O hw_cau_aesc_ca_t AESC_CA[9]; //!< [0xB08] General Purpose Register 0 - AES Column Operation command
mbed_official	146:f64d43ff0c18	1448	uint8_t _reserved7[20];
mbed_official	146:f64d43ff0c18	1449	__O hw_cau_aesic_casr_t AESIC_CASR; //!< [0xB40] Status register - AES Inverse Column Operation command
mbed_official	146:f64d43ff0c18	1450	__O hw_cau_aesic_caa_t AESIC_CAA; //!< [0xB44] Accumulator register - AES Inverse Column Operation command
mbed_official	146:f64d43ff0c18	1451	__O hw_cau_aesic_ca_t AESIC_CA[9]; //!< [0xB48] General Purpose Register 0 - AES Inverse Column Operation command
mbed_official	146:f64d43ff0c18	1452	} hw_cau_t;
mbed_official	146:f64d43ff0c18	1453	#pragma pack()
mbed_official	146:f64d43ff0c18	1454
mbed_official	146:f64d43ff0c18	1455	//! @brief Macro to access all CAU registers.
mbed_official	146:f64d43ff0c18	1456	//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official	146:f64d43ff0c18	1457	//! use the '&' operator, like <code>&HW_CAU</code>.
mbed_official	146:f64d43ff0c18	1458	#define HW_CAU ((hw_cau_t ) REGS_CAU_BASE)
mbed_official	146:f64d43ff0c18	1459	#endif
mbed_official	146:f64d43ff0c18	1460
mbed_official	146:f64d43ff0c18	1461	#endif // __HW_CAU_REGISTERS_H__
mbed_official	146:f64d43ff0c18	1462	// v22/130726/0.9
mbed_official	146:f64d43ff0c18	1463	// EOF