mbed official / mbed-src

mbed library sources

Dependents:   Encrypted my_mbed lklk CyaSSL_DTLS_Cellular ... more

Superseded

This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

Import librarymbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_axbs.h@149:1fb5f62b92bd, 2014-04-03 (annotated)

Committer:
mbed_official
Date:
Thu Apr 03 11:45:06 2014 +0100
Revision:
149:1fb5f62b92bd
Parent:
targets/hal/TARGET_Freescale/TARGET_KSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_axbs.h@146:f64d43ff0c18 
Synchronized with git revision 220c0bb39ceee40016e1e86350c058963d01ed42



Full URL: https://github.com/mbedmicro/mbed/commit/220c0bb39ceee40016e1e86350c058963d01ed42/

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /*
mbed_official 146:f64d43ff0c18 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
mbed_official 146:f64d43ff0c18 3 * All rights reserved.
mbed_official 146:f64d43ff0c18 4 *
mbed_official 146:f64d43ff0c18 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official 146:f64d43ff0c18 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official 146:f64d43ff0c18 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
mbed_official 146:f64d43ff0c18 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
mbed_official 146:f64d43ff0c18 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
mbed_official 146:f64d43ff0c18 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 146:f64d43ff0c18 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 146:f64d43ff0c18 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
mbed_official 146:f64d43ff0c18 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
mbed_official 146:f64d43ff0c18 14 * OF SUCH DAMAGE.
mbed_official 146:f64d43ff0c18 15 */
mbed_official 146:f64d43ff0c18 16 /*
mbed_official 146:f64d43ff0c18 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 146:f64d43ff0c18 18 *
mbed_official 146:f64d43ff0c18 19 * This file was generated automatically and any changes may be lost.
mbed_official 146:f64d43ff0c18 20 */
mbed_official 146:f64d43ff0c18 21 #ifndef __HW_AXBS_REGISTERS_H__
mbed_official 146:f64d43ff0c18 22 #define __HW_AXBS_REGISTERS_H__
mbed_official 146:f64d43ff0c18 23
mbed_official 146:f64d43ff0c18 24 #include "regs.h"
mbed_official 146:f64d43ff0c18 25
mbed_official 146:f64d43ff0c18 26 /*
mbed_official 146:f64d43ff0c18 27 * MK64F12 AXBS
mbed_official 146:f64d43ff0c18 28 *
mbed_official 146:f64d43ff0c18 29 * Crossbar switch
mbed_official 146:f64d43ff0c18 30 *
mbed_official 146:f64d43ff0c18 31 * Registers defined in this header file:
mbed_official 146:f64d43ff0c18 32 * - HW_AXBS_PRSn - Priority Registers Slave
mbed_official 146:f64d43ff0c18 33 * - HW_AXBS_CRSn - Control Register
mbed_official 146:f64d43ff0c18 34 * - HW_AXBS_MGPCR0 - Master General Purpose Control Register
mbed_official 146:f64d43ff0c18 35 * - HW_AXBS_MGPCR1 - Master General Purpose Control Register
mbed_official 146:f64d43ff0c18 36 * - HW_AXBS_MGPCR2 - Master General Purpose Control Register
mbed_official 146:f64d43ff0c18 37 * - HW_AXBS_MGPCR3 - Master General Purpose Control Register
mbed_official 146:f64d43ff0c18 38 * - HW_AXBS_MGPCR4 - Master General Purpose Control Register
mbed_official 146:f64d43ff0c18 39 * - HW_AXBS_MGPCR5 - Master General Purpose Control Register
mbed_official 146:f64d43ff0c18 40 *
mbed_official 146:f64d43ff0c18 41 * - hw_axbs_t - Struct containing all module registers.
mbed_official 146:f64d43ff0c18 42 */
mbed_official 146:f64d43ff0c18 43
mbed_official 146:f64d43ff0c18 44 //! @name Module base addresses
mbed_official 146:f64d43ff0c18 45 //@{
mbed_official 146:f64d43ff0c18 46 #ifndef REGS_AXBS_BASE
mbed_official 146:f64d43ff0c18 47 #define HW_AXBS_INSTANCE_COUNT (1U) //!< Number of instances of the AXBS module.
mbed_official 146:f64d43ff0c18 48 #define REGS_AXBS_BASE (0x40004000U) //!< Base address for AXBS.
mbed_official 146:f64d43ff0c18 49 #endif
mbed_official 146:f64d43ff0c18 50 //@}
mbed_official 146:f64d43ff0c18 51
mbed_official 146:f64d43ff0c18 52 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 53 // HW_AXBS_PRSn - Priority Registers Slave
mbed_official 146:f64d43ff0c18 54 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 55
mbed_official 146:f64d43ff0c18 56 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 57 /*!
mbed_official 146:f64d43ff0c18 58 * @brief HW_AXBS_PRSn - Priority Registers Slave (RW)
mbed_official 146:f64d43ff0c18 59 *
mbed_official 146:f64d43ff0c18 60 * Reset value: 0x00543210U
mbed_official 146:f64d43ff0c18 61 *
mbed_official 146:f64d43ff0c18 62 * The priority registers (PRSn) set the priority of each master port on a per
mbed_official 146:f64d43ff0c18 63 * slave port basis and reside in each slave port. The priority register can be
mbed_official 146:f64d43ff0c18 64 * accessed only with 32-bit accesses. After the CRSn[RO] bit is set, the PRSn
mbed_official 146:f64d43ff0c18 65 * register can only be read; attempts to write to it have no effect on PRSn and
mbed_official 146:f64d43ff0c18 66 * result in a bus-error response to the master initiating the write. Two available
mbed_official 146:f64d43ff0c18 67 * masters must not be programmed with the same priority level. Attempts to
mbed_official 146:f64d43ff0c18 68 * program two or more masters with the same priority level result in a bus-error
mbed_official 146:f64d43ff0c18 69 * response and the PRSn is not updated. Valid values for the Mn priority fields
mbed_official 146:f64d43ff0c18 70 * depend on which masters are available on the chip. This information can be found in
mbed_official 146:f64d43ff0c18 71 * the chip-specific information for the crossbar. If the chip contains less
mbed_official 146:f64d43ff0c18 72 * than five masters, values 0 to 3 are valid. Writing other values will result in
mbed_official 146:f64d43ff0c18 73 * an error. If the chip contains five or more masters, valid values are 0 to n-1,
mbed_official 146:f64d43ff0c18 74 * where n is the number of masters attached to the AXBS module. Other values
mbed_official 146:f64d43ff0c18 75 * will result in an error.
mbed_official 146:f64d43ff0c18 76 */
mbed_official 146:f64d43ff0c18 77 typedef union _hw_axbs_prsn
mbed_official 146:f64d43ff0c18 78 {
mbed_official 146:f64d43ff0c18 79 uint32_t U;
mbed_official 146:f64d43ff0c18 80 struct _hw_axbs_prsn_bitfields
mbed_official 146:f64d43ff0c18 81 {
mbed_official 146:f64d43ff0c18 82 uint32_t M0 : 3; //!< [2:0] Master 0 Priority. Sets the arbitration
mbed_official 146:f64d43ff0c18 83 //! priority for this port on the associated slave port.
mbed_official 146:f64d43ff0c18 84 uint32_t RESERVED0 : 1; //!< [3]
mbed_official 146:f64d43ff0c18 85 uint32_t M1 : 3; //!< [6:4] Master 1 Priority. Sets the arbitration
mbed_official 146:f64d43ff0c18 86 //! priority for this port on the associated slave port.
mbed_official 146:f64d43ff0c18 87 uint32_t RESERVED1 : 1; //!< [7]
mbed_official 146:f64d43ff0c18 88 uint32_t M2 : 3; //!< [10:8] Master 2 Priority. Sets the arbitration
mbed_official 146:f64d43ff0c18 89 //! priority for this port on the associated slave port.
mbed_official 146:f64d43ff0c18 90 uint32_t RESERVED2 : 1; //!< [11]
mbed_official 146:f64d43ff0c18 91 uint32_t M3 : 3; //!< [14:12] Master 3 Priority. Sets the arbitration
mbed_official 146:f64d43ff0c18 92 //! priority for this port on the associated slave port.
mbed_official 146:f64d43ff0c18 93 uint32_t RESERVED3 : 1; //!< [15]
mbed_official 146:f64d43ff0c18 94 uint32_t M4 : 3; //!< [18:16] Master 4 Priority. Sets the arbitration
mbed_official 146:f64d43ff0c18 95 //! priority for this port on the associated slave port.
mbed_official 146:f64d43ff0c18 96 uint32_t RESERVED4 : 1; //!< [19]
mbed_official 146:f64d43ff0c18 97 uint32_t M5 : 3; //!< [22:20] Master 5 Priority. Sets the arbitration
mbed_official 146:f64d43ff0c18 98 //! priority for this port on the associated slave port.
mbed_official 146:f64d43ff0c18 99 uint32_t RESERVED5 : 9; //!< [31:23]
mbed_official 146:f64d43ff0c18 100 } B;
mbed_official 146:f64d43ff0c18 101 } hw_axbs_prsn_t;
mbed_official 146:f64d43ff0c18 102 #endif
mbed_official 146:f64d43ff0c18 103
mbed_official 146:f64d43ff0c18 104 /*!
mbed_official 146:f64d43ff0c18 105 * @name Constants and macros for entire AXBS_PRSn register
mbed_official 146:f64d43ff0c18 106 */
mbed_official 146:f64d43ff0c18 107 //@{
mbed_official 146:f64d43ff0c18 108 #define HW_AXBS_PRSn_COUNT (5U)
mbed_official 146:f64d43ff0c18 109
mbed_official 146:f64d43ff0c18 110 #define HW_AXBS_PRSn_ADDR(n) (REGS_AXBS_BASE + 0x0U + (0x100U * n))
mbed_official 146:f64d43ff0c18 111
mbed_official 146:f64d43ff0c18 112 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 113 #define HW_AXBS_PRSn(n) (*(__IO hw_axbs_prsn_t *) HW_AXBS_PRSn_ADDR(n))
mbed_official 146:f64d43ff0c18 114 #define HW_AXBS_PRSn_RD(n) (HW_AXBS_PRSn(n).U)
mbed_official 146:f64d43ff0c18 115 #define HW_AXBS_PRSn_WR(n, v) (HW_AXBS_PRSn(n).U = (v))
mbed_official 146:f64d43ff0c18 116 #define HW_AXBS_PRSn_SET(n, v) (HW_AXBS_PRSn_WR(n, HW_AXBS_PRSn_RD(n) | (v)))
mbed_official 146:f64d43ff0c18 117 #define HW_AXBS_PRSn_CLR(n, v) (HW_AXBS_PRSn_WR(n, HW_AXBS_PRSn_RD(n) & ~(v)))
mbed_official 146:f64d43ff0c18 118 #define HW_AXBS_PRSn_TOG(n, v) (HW_AXBS_PRSn_WR(n, HW_AXBS_PRSn_RD(n) ^ (v)))
mbed_official 146:f64d43ff0c18 119 #endif
mbed_official 146:f64d43ff0c18 120 //@}
mbed_official 146:f64d43ff0c18 121
mbed_official 146:f64d43ff0c18 122 /*
mbed_official 146:f64d43ff0c18 123 * Constants & macros for individual AXBS_PRSn bitfields
mbed_official 146:f64d43ff0c18 124 */
mbed_official 146:f64d43ff0c18 125
mbed_official 146:f64d43ff0c18 126 /*!
mbed_official 146:f64d43ff0c18 127 * @name Register AXBS_PRSn, field M0[2:0] (RW)
mbed_official 146:f64d43ff0c18 128 *
mbed_official 146:f64d43ff0c18 129 * Values:
mbed_official 146:f64d43ff0c18 130 * - 000 - This master has level 1, or highest, priority when accessing the
mbed_official 146:f64d43ff0c18 131 * slave port.
mbed_official 146:f64d43ff0c18 132 * - 001 - This master has level 2 priority when accessing the slave port.
mbed_official 146:f64d43ff0c18 133 * - 010 - This master has level 3 priority when accessing the slave port.
mbed_official 146:f64d43ff0c18 134 * - 011 - This master has level 4 priority when accessing the slave port.
mbed_official 146:f64d43ff0c18 135 * - 100 - This master has level 5 priority when accessing the slave port.
mbed_official 146:f64d43ff0c18 136 * - 101 - This master has level 6 priority when accessing the slave port.
mbed_official 146:f64d43ff0c18 137 * - 110 - This master has level 7 priority when accessing the slave port.
mbed_official 146:f64d43ff0c18 138 * - 111 - This master has level 8, or lowest, priority when accessing the slave
mbed_official 146:f64d43ff0c18 139 * port.
mbed_official 146:f64d43ff0c18 140 */
mbed_official 146:f64d43ff0c18 141 //@{
mbed_official 146:f64d43ff0c18 142 #define BP_AXBS_PRSn_M0 (0U) //!< Bit position for AXBS_PRSn_M0.
mbed_official 146:f64d43ff0c18 143 #define BM_AXBS_PRSn_M0 (0x00000007U) //!< Bit mask for AXBS_PRSn_M0.
mbed_official 146:f64d43ff0c18 144 #define BS_AXBS_PRSn_M0 (3U) //!< Bit field size in bits for AXBS_PRSn_M0.
mbed_official 146:f64d43ff0c18 145
mbed_official 146:f64d43ff0c18 146 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 147 //! @brief Read current value of the AXBS_PRSn_M0 field.
mbed_official 146:f64d43ff0c18 148 #define BR_AXBS_PRSn_M0(n) (HW_AXBS_PRSn(n).B.M0)
mbed_official 146:f64d43ff0c18 149 #endif
mbed_official 146:f64d43ff0c18 150
mbed_official 146:f64d43ff0c18 151 //! @brief Format value for bitfield AXBS_PRSn_M0.
mbed_official 146:f64d43ff0c18 152 #define BF_AXBS_PRSn_M0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_PRSn_M0), uint32_t) & BM_AXBS_PRSn_M0)
mbed_official 146:f64d43ff0c18 153
mbed_official 146:f64d43ff0c18 154 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 155 //! @brief Set the M0 field to a new value.
mbed_official 146:f64d43ff0c18 156 #define BW_AXBS_PRSn_M0(n, v) (HW_AXBS_PRSn_WR(n, (HW_AXBS_PRSn_RD(n) & ~BM_AXBS_PRSn_M0) | BF_AXBS_PRSn_M0(v)))
mbed_official 146:f64d43ff0c18 157 #endif
mbed_official 146:f64d43ff0c18 158 //@}
mbed_official 146:f64d43ff0c18 159
mbed_official 146:f64d43ff0c18 160 /*!
mbed_official 146:f64d43ff0c18 161 * @name Register AXBS_PRSn, field M1[6:4] (RW)
mbed_official 146:f64d43ff0c18 162 *
mbed_official 146:f64d43ff0c18 163 * Values:
mbed_official 146:f64d43ff0c18 164 * - 000 - This master has level 1, or highest, priority when accessing the
mbed_official 146:f64d43ff0c18 165 * slave port.
mbed_official 146:f64d43ff0c18 166 * - 001 - This master has level 2 priority when accessing the slave port.
mbed_official 146:f64d43ff0c18 167 * - 010 - This master has level 3 priority when accessing the slave port.
mbed_official 146:f64d43ff0c18 168 * - 011 - This master has level 4 priority when accessing the slave port.
mbed_official 146:f64d43ff0c18 169 * - 100 - This master has level 5 priority when accessing the slave port.
mbed_official 146:f64d43ff0c18 170 * - 101 - This master has level 6 priority when accessing the slave port.
mbed_official 146:f64d43ff0c18 171 * - 110 - This master has level 7 priority when accessing the slave port.
mbed_official 146:f64d43ff0c18 172 * - 111 - This master has level 8, or lowest, priority when accessing the slave
mbed_official 146:f64d43ff0c18 173 * port.
mbed_official 146:f64d43ff0c18 174 */
mbed_official 146:f64d43ff0c18 175 //@{
mbed_official 146:f64d43ff0c18 176 #define BP_AXBS_PRSn_M1 (4U) //!< Bit position for AXBS_PRSn_M1.
mbed_official 146:f64d43ff0c18 177 #define BM_AXBS_PRSn_M1 (0x00000070U) //!< Bit mask for AXBS_PRSn_M1.
mbed_official 146:f64d43ff0c18 178 #define BS_AXBS_PRSn_M1 (3U) //!< Bit field size in bits for AXBS_PRSn_M1.
mbed_official 146:f64d43ff0c18 179
mbed_official 146:f64d43ff0c18 180 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 181 //! @brief Read current value of the AXBS_PRSn_M1 field.
mbed_official 146:f64d43ff0c18 182 #define BR_AXBS_PRSn_M1(n) (HW_AXBS_PRSn(n).B.M1)
mbed_official 146:f64d43ff0c18 183 #endif
mbed_official 146:f64d43ff0c18 184
mbed_official 146:f64d43ff0c18 185 //! @brief Format value for bitfield AXBS_PRSn_M1.
mbed_official 146:f64d43ff0c18 186 #define BF_AXBS_PRSn_M1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_PRSn_M1), uint32_t) & BM_AXBS_PRSn_M1)
mbed_official 146:f64d43ff0c18 187
mbed_official 146:f64d43ff0c18 188 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 189 //! @brief Set the M1 field to a new value.
mbed_official 146:f64d43ff0c18 190 #define BW_AXBS_PRSn_M1(n, v) (HW_AXBS_PRSn_WR(n, (HW_AXBS_PRSn_RD(n) & ~BM_AXBS_PRSn_M1) | BF_AXBS_PRSn_M1(v)))
mbed_official 146:f64d43ff0c18 191 #endif
mbed_official 146:f64d43ff0c18 192 //@}
mbed_official 146:f64d43ff0c18 193
mbed_official 146:f64d43ff0c18 194 /*!
mbed_official 146:f64d43ff0c18 195 * @name Register AXBS_PRSn, field M2[10:8] (RW)
mbed_official 146:f64d43ff0c18 196 *
mbed_official 146:f64d43ff0c18 197 * Values:
mbed_official 146:f64d43ff0c18 198 * - 000 - This master has level 1, or highest, priority when accessing the
mbed_official 146:f64d43ff0c18 199 * slave port.
mbed_official 146:f64d43ff0c18 200 * - 001 - This master has level 2 priority when accessing the slave port.
mbed_official 146:f64d43ff0c18 201 * - 010 - This master has level 3 priority when accessing the slave port.
mbed_official 146:f64d43ff0c18 202 * - 011 - This master has level 4 priority when accessing the slave port.
mbed_official 146:f64d43ff0c18 203 * - 100 - This master has level 5 priority when accessing the slave port.
mbed_official 146:f64d43ff0c18 204 * - 101 - This master has level 6 priority when accessing the slave port.
mbed_official 146:f64d43ff0c18 205 * - 110 - This master has level 7 priority when accessing the slave port.
mbed_official 146:f64d43ff0c18 206 * - 111 - This master has level 8, or lowest, priority when accessing the slave
mbed_official 146:f64d43ff0c18 207 * port.
mbed_official 146:f64d43ff0c18 208 */
mbed_official 146:f64d43ff0c18 209 //@{
mbed_official 146:f64d43ff0c18 210 #define BP_AXBS_PRSn_M2 (8U) //!< Bit position for AXBS_PRSn_M2.
mbed_official 146:f64d43ff0c18 211 #define BM_AXBS_PRSn_M2 (0x00000700U) //!< Bit mask for AXBS_PRSn_M2.
mbed_official 146:f64d43ff0c18 212 #define BS_AXBS_PRSn_M2 (3U) //!< Bit field size in bits for AXBS_PRSn_M2.
mbed_official 146:f64d43ff0c18 213
mbed_official 146:f64d43ff0c18 214 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 215 //! @brief Read current value of the AXBS_PRSn_M2 field.
mbed_official 146:f64d43ff0c18 216 #define BR_AXBS_PRSn_M2(n) (HW_AXBS_PRSn(n).B.M2)
mbed_official 146:f64d43ff0c18 217 #endif
mbed_official 146:f64d43ff0c18 218
mbed_official 146:f64d43ff0c18 219 //! @brief Format value for bitfield AXBS_PRSn_M2.
mbed_official 146:f64d43ff0c18 220 #define BF_AXBS_PRSn_M2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_PRSn_M2), uint32_t) & BM_AXBS_PRSn_M2)
mbed_official 146:f64d43ff0c18 221
mbed_official 146:f64d43ff0c18 222 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 223 //! @brief Set the M2 field to a new value.
mbed_official 146:f64d43ff0c18 224 #define BW_AXBS_PRSn_M2(n, v) (HW_AXBS_PRSn_WR(n, (HW_AXBS_PRSn_RD(n) & ~BM_AXBS_PRSn_M2) | BF_AXBS_PRSn_M2(v)))
mbed_official 146:f64d43ff0c18 225 #endif
mbed_official 146:f64d43ff0c18 226 //@}
mbed_official 146:f64d43ff0c18 227
mbed_official 146:f64d43ff0c18 228 /*!
mbed_official 146:f64d43ff0c18 229 * @name Register AXBS_PRSn, field M3[14:12] (RW)
mbed_official 146:f64d43ff0c18 230 *
mbed_official 146:f64d43ff0c18 231 * Values:
mbed_official 146:f64d43ff0c18 232 * - 000 - This master has level 1, or highest, priority when accessing the
mbed_official 146:f64d43ff0c18 233 * slave port.
mbed_official 146:f64d43ff0c18 234 * - 001 - This master has level 2 priority when accessing the slave port.
mbed_official 146:f64d43ff0c18 235 * - 010 - This master has level 3 priority when accessing the slave port.
mbed_official 146:f64d43ff0c18 236 * - 011 - This master has level 4 priority when accessing the slave port.
mbed_official 146:f64d43ff0c18 237 * - 100 - This master has level 5 priority when accessing the slave port.
mbed_official 146:f64d43ff0c18 238 * - 101 - This master has level 6 priority when accessing the slave port.
mbed_official 146:f64d43ff0c18 239 * - 110 - This master has level 7 priority when accessing the slave port.
mbed_official 146:f64d43ff0c18 240 * - 111 - This master has level 8, or lowest, priority when accessing the slave
mbed_official 146:f64d43ff0c18 241 * port.
mbed_official 146:f64d43ff0c18 242 */
mbed_official 146:f64d43ff0c18 243 //@{
mbed_official 146:f64d43ff0c18 244 #define BP_AXBS_PRSn_M3 (12U) //!< Bit position for AXBS_PRSn_M3.
mbed_official 146:f64d43ff0c18 245 #define BM_AXBS_PRSn_M3 (0x00007000U) //!< Bit mask for AXBS_PRSn_M3.
mbed_official 146:f64d43ff0c18 246 #define BS_AXBS_PRSn_M3 (3U) //!< Bit field size in bits for AXBS_PRSn_M3.
mbed_official 146:f64d43ff0c18 247
mbed_official 146:f64d43ff0c18 248 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 249 //! @brief Read current value of the AXBS_PRSn_M3 field.
mbed_official 146:f64d43ff0c18 250 #define BR_AXBS_PRSn_M3(n) (HW_AXBS_PRSn(n).B.M3)
mbed_official 146:f64d43ff0c18 251 #endif
mbed_official 146:f64d43ff0c18 252
mbed_official 146:f64d43ff0c18 253 //! @brief Format value for bitfield AXBS_PRSn_M3.
mbed_official 146:f64d43ff0c18 254 #define BF_AXBS_PRSn_M3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_PRSn_M3), uint32_t) & BM_AXBS_PRSn_M3)
mbed_official 146:f64d43ff0c18 255
mbed_official 146:f64d43ff0c18 256 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 257 //! @brief Set the M3 field to a new value.
mbed_official 146:f64d43ff0c18 258 #define BW_AXBS_PRSn_M3(n, v) (HW_AXBS_PRSn_WR(n, (HW_AXBS_PRSn_RD(n) & ~BM_AXBS_PRSn_M3) | BF_AXBS_PRSn_M3(v)))
mbed_official 146:f64d43ff0c18 259 #endif
mbed_official 146:f64d43ff0c18 260 //@}
mbed_official 146:f64d43ff0c18 261
mbed_official 146:f64d43ff0c18 262 /*!
mbed_official 146:f64d43ff0c18 263 * @name Register AXBS_PRSn, field M4[18:16] (RW)
mbed_official 146:f64d43ff0c18 264 *
mbed_official 146:f64d43ff0c18 265 * Values:
mbed_official 146:f64d43ff0c18 266 * - 000 - This master has level 1, or highest, priority when accessing the
mbed_official 146:f64d43ff0c18 267 * slave port.
mbed_official 146:f64d43ff0c18 268 * - 001 - This master has level 2 priority when accessing the slave port.
mbed_official 146:f64d43ff0c18 269 * - 010 - This master has level 3 priority when accessing the slave port.
mbed_official 146:f64d43ff0c18 270 * - 011 - This master has level 4 priority when accessing the slave port.
mbed_official 146:f64d43ff0c18 271 * - 100 - This master has level 5 priority when accessing the slave port.
mbed_official 146:f64d43ff0c18 272 * - 101 - This master has level 6 priority when accessing the slave port.
mbed_official 146:f64d43ff0c18 273 * - 110 - This master has level 7 priority when accessing the slave port.
mbed_official 146:f64d43ff0c18 274 * - 111 - This master has level 8, or lowest, priority when accessing the slave
mbed_official 146:f64d43ff0c18 275 * port.
mbed_official 146:f64d43ff0c18 276 */
mbed_official 146:f64d43ff0c18 277 //@{
mbed_official 146:f64d43ff0c18 278 #define BP_AXBS_PRSn_M4 (16U) //!< Bit position for AXBS_PRSn_M4.
mbed_official 146:f64d43ff0c18 279 #define BM_AXBS_PRSn_M4 (0x00070000U) //!< Bit mask for AXBS_PRSn_M4.
mbed_official 146:f64d43ff0c18 280 #define BS_AXBS_PRSn_M4 (3U) //!< Bit field size in bits for AXBS_PRSn_M4.
mbed_official 146:f64d43ff0c18 281
mbed_official 146:f64d43ff0c18 282 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 283 //! @brief Read current value of the AXBS_PRSn_M4 field.
mbed_official 146:f64d43ff0c18 284 #define BR_AXBS_PRSn_M4(n) (HW_AXBS_PRSn(n).B.M4)
mbed_official 146:f64d43ff0c18 285 #endif
mbed_official 146:f64d43ff0c18 286
mbed_official 146:f64d43ff0c18 287 //! @brief Format value for bitfield AXBS_PRSn_M4.
mbed_official 146:f64d43ff0c18 288 #define BF_AXBS_PRSn_M4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_PRSn_M4), uint32_t) & BM_AXBS_PRSn_M4)
mbed_official 146:f64d43ff0c18 289
mbed_official 146:f64d43ff0c18 290 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 291 //! @brief Set the M4 field to a new value.
mbed_official 146:f64d43ff0c18 292 #define BW_AXBS_PRSn_M4(n, v) (HW_AXBS_PRSn_WR(n, (HW_AXBS_PRSn_RD(n) & ~BM_AXBS_PRSn_M4) | BF_AXBS_PRSn_M4(v)))
mbed_official 146:f64d43ff0c18 293 #endif
mbed_official 146:f64d43ff0c18 294 //@}
mbed_official 146:f64d43ff0c18 295
mbed_official 146:f64d43ff0c18 296 /*!
mbed_official 146:f64d43ff0c18 297 * @name Register AXBS_PRSn, field M5[22:20] (RW)
mbed_official 146:f64d43ff0c18 298 *
mbed_official 146:f64d43ff0c18 299 * Values:
mbed_official 146:f64d43ff0c18 300 * - 000 - This master has level 1, or highest, priority when accessing the
mbed_official 146:f64d43ff0c18 301 * slave port.
mbed_official 146:f64d43ff0c18 302 * - 001 - This master has level 2 priority when accessing the slave port.
mbed_official 146:f64d43ff0c18 303 * - 010 - This master has level 3 priority when accessing the slave port.
mbed_official 146:f64d43ff0c18 304 * - 011 - This master has level 4 priority when accessing the slave port.
mbed_official 146:f64d43ff0c18 305 * - 100 - This master has level 5 priority when accessing the slave port.
mbed_official 146:f64d43ff0c18 306 * - 101 - This master has level 6 priority when accessing the slave port.
mbed_official 146:f64d43ff0c18 307 * - 110 - This master has level 7 priority when accessing the slave port.
mbed_official 146:f64d43ff0c18 308 * - 111 - This master has level 8, or lowest, priority when accessing the slave
mbed_official 146:f64d43ff0c18 309 * port.
mbed_official 146:f64d43ff0c18 310 */
mbed_official 146:f64d43ff0c18 311 //@{
mbed_official 146:f64d43ff0c18 312 #define BP_AXBS_PRSn_M5 (20U) //!< Bit position for AXBS_PRSn_M5.
mbed_official 146:f64d43ff0c18 313 #define BM_AXBS_PRSn_M5 (0x00700000U) //!< Bit mask for AXBS_PRSn_M5.
mbed_official 146:f64d43ff0c18 314 #define BS_AXBS_PRSn_M5 (3U) //!< Bit field size in bits for AXBS_PRSn_M5.
mbed_official 146:f64d43ff0c18 315
mbed_official 146:f64d43ff0c18 316 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 317 //! @brief Read current value of the AXBS_PRSn_M5 field.
mbed_official 146:f64d43ff0c18 318 #define BR_AXBS_PRSn_M5(n) (HW_AXBS_PRSn(n).B.M5)
mbed_official 146:f64d43ff0c18 319 #endif
mbed_official 146:f64d43ff0c18 320
mbed_official 146:f64d43ff0c18 321 //! @brief Format value for bitfield AXBS_PRSn_M5.
mbed_official 146:f64d43ff0c18 322 #define BF_AXBS_PRSn_M5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_PRSn_M5), uint32_t) & BM_AXBS_PRSn_M5)
mbed_official 146:f64d43ff0c18 323
mbed_official 146:f64d43ff0c18 324 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 325 //! @brief Set the M5 field to a new value.
mbed_official 146:f64d43ff0c18 326 #define BW_AXBS_PRSn_M5(n, v) (HW_AXBS_PRSn_WR(n, (HW_AXBS_PRSn_RD(n) & ~BM_AXBS_PRSn_M5) | BF_AXBS_PRSn_M5(v)))
mbed_official 146:f64d43ff0c18 327 #endif
mbed_official 146:f64d43ff0c18 328 //@}
mbed_official 146:f64d43ff0c18 329 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 330 // HW_AXBS_CRSn - Control Register
mbed_official 146:f64d43ff0c18 331 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 332
mbed_official 146:f64d43ff0c18 333 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 334 /*!
mbed_official 146:f64d43ff0c18 335 * @brief HW_AXBS_CRSn - Control Register (RW)
mbed_official 146:f64d43ff0c18 336 *
mbed_official 146:f64d43ff0c18 337 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 338 *
mbed_official 146:f64d43ff0c18 339 * These registers control several features of each slave port and must be
mbed_official 146:f64d43ff0c18 340 * accessed using 32-bit accesses. After CRSn[RO] is set, the PRSn can only be read;
mbed_official 146:f64d43ff0c18 341 * attempts to write to it have no effect and result in an error response.
mbed_official 146:f64d43ff0c18 342 */
mbed_official 146:f64d43ff0c18 343 typedef union _hw_axbs_crsn
mbed_official 146:f64d43ff0c18 344 {
mbed_official 146:f64d43ff0c18 345 uint32_t U;
mbed_official 146:f64d43ff0c18 346 struct _hw_axbs_crsn_bitfields
mbed_official 146:f64d43ff0c18 347 {
mbed_official 146:f64d43ff0c18 348 uint32_t PARK : 3; //!< [2:0] Park
mbed_official 146:f64d43ff0c18 349 uint32_t RESERVED0 : 1; //!< [3]
mbed_official 146:f64d43ff0c18 350 uint32_t PCTL : 2; //!< [5:4] Parking Control
mbed_official 146:f64d43ff0c18 351 uint32_t RESERVED1 : 2; //!< [7:6]
mbed_official 146:f64d43ff0c18 352 uint32_t ARB : 2; //!< [9:8] Arbitration Mode
mbed_official 146:f64d43ff0c18 353 uint32_t RESERVED2 : 20; //!< [29:10]
mbed_official 146:f64d43ff0c18 354 uint32_t HLP : 1; //!< [30] Halt Low Priority
mbed_official 146:f64d43ff0c18 355 uint32_t RO : 1; //!< [31] Read Only
mbed_official 146:f64d43ff0c18 356 } B;
mbed_official 146:f64d43ff0c18 357 } hw_axbs_crsn_t;
mbed_official 146:f64d43ff0c18 358 #endif
mbed_official 146:f64d43ff0c18 359
mbed_official 146:f64d43ff0c18 360 /*!
mbed_official 146:f64d43ff0c18 361 * @name Constants and macros for entire AXBS_CRSn register
mbed_official 146:f64d43ff0c18 362 */
mbed_official 146:f64d43ff0c18 363 //@{
mbed_official 146:f64d43ff0c18 364 #define HW_AXBS_CRSn_COUNT (5U)
mbed_official 146:f64d43ff0c18 365
mbed_official 146:f64d43ff0c18 366 #define HW_AXBS_CRSn_ADDR(n) (REGS_AXBS_BASE + 0x10U + (0x100U * n))
mbed_official 146:f64d43ff0c18 367
mbed_official 146:f64d43ff0c18 368 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 369 #define HW_AXBS_CRSn(n) (*(__IO hw_axbs_crsn_t *) HW_AXBS_CRSn_ADDR(n))
mbed_official 146:f64d43ff0c18 370 #define HW_AXBS_CRSn_RD(n) (HW_AXBS_CRSn(n).U)
mbed_official 146:f64d43ff0c18 371 #define HW_AXBS_CRSn_WR(n, v) (HW_AXBS_CRSn(n).U = (v))
mbed_official 146:f64d43ff0c18 372 #define HW_AXBS_CRSn_SET(n, v) (HW_AXBS_CRSn_WR(n, HW_AXBS_CRSn_RD(n) | (v)))
mbed_official 146:f64d43ff0c18 373 #define HW_AXBS_CRSn_CLR(n, v) (HW_AXBS_CRSn_WR(n, HW_AXBS_CRSn_RD(n) & ~(v)))
mbed_official 146:f64d43ff0c18 374 #define HW_AXBS_CRSn_TOG(n, v) (HW_AXBS_CRSn_WR(n, HW_AXBS_CRSn_RD(n) ^ (v)))
mbed_official 146:f64d43ff0c18 375 #endif
mbed_official 146:f64d43ff0c18 376 //@}
mbed_official 146:f64d43ff0c18 377
mbed_official 146:f64d43ff0c18 378 /*
mbed_official 146:f64d43ff0c18 379 * Constants & macros for individual AXBS_CRSn bitfields
mbed_official 146:f64d43ff0c18 380 */
mbed_official 146:f64d43ff0c18 381
mbed_official 146:f64d43ff0c18 382 /*!
mbed_official 146:f64d43ff0c18 383 * @name Register AXBS_CRSn, field PARK[2:0] (RW)
mbed_official 146:f64d43ff0c18 384 *
mbed_official 146:f64d43ff0c18 385 * Determines which master port the current slave port parks on when no masters
mbed_official 146:f64d43ff0c18 386 * are actively making requests and the PCTL bits are cleared. Select only master
mbed_official 146:f64d43ff0c18 387 * ports that are present on the chip. Otherwise, undefined behavior might occur.
mbed_official 146:f64d43ff0c18 388 *
mbed_official 146:f64d43ff0c18 389 * Values:
mbed_official 146:f64d43ff0c18 390 * - 000 - Park on master port M0
mbed_official 146:f64d43ff0c18 391 * - 001 - Park on master port M1
mbed_official 146:f64d43ff0c18 392 * - 010 - Park on master port M2
mbed_official 146:f64d43ff0c18 393 * - 011 - Park on master port M3
mbed_official 146:f64d43ff0c18 394 * - 100 - Park on master port M4
mbed_official 146:f64d43ff0c18 395 * - 101 - Park on master port M5
mbed_official 146:f64d43ff0c18 396 * - 110 - Park on master port M6
mbed_official 146:f64d43ff0c18 397 * - 111 - Park on master port M7
mbed_official 146:f64d43ff0c18 398 */
mbed_official 146:f64d43ff0c18 399 //@{
mbed_official 146:f64d43ff0c18 400 #define BP_AXBS_CRSn_PARK (0U) //!< Bit position for AXBS_CRSn_PARK.
mbed_official 146:f64d43ff0c18 401 #define BM_AXBS_CRSn_PARK (0x00000007U) //!< Bit mask for AXBS_CRSn_PARK.
mbed_official 146:f64d43ff0c18 402 #define BS_AXBS_CRSn_PARK (3U) //!< Bit field size in bits for AXBS_CRSn_PARK.
mbed_official 146:f64d43ff0c18 403
mbed_official 146:f64d43ff0c18 404 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 405 //! @brief Read current value of the AXBS_CRSn_PARK field.
mbed_official 146:f64d43ff0c18 406 #define BR_AXBS_CRSn_PARK(n) (HW_AXBS_CRSn(n).B.PARK)
mbed_official 146:f64d43ff0c18 407 #endif
mbed_official 146:f64d43ff0c18 408
mbed_official 146:f64d43ff0c18 409 //! @brief Format value for bitfield AXBS_CRSn_PARK.
mbed_official 146:f64d43ff0c18 410 #define BF_AXBS_CRSn_PARK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_CRSn_PARK), uint32_t) & BM_AXBS_CRSn_PARK)
mbed_official 146:f64d43ff0c18 411
mbed_official 146:f64d43ff0c18 412 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 413 //! @brief Set the PARK field to a new value.
mbed_official 146:f64d43ff0c18 414 #define BW_AXBS_CRSn_PARK(n, v) (HW_AXBS_CRSn_WR(n, (HW_AXBS_CRSn_RD(n) & ~BM_AXBS_CRSn_PARK) | BF_AXBS_CRSn_PARK(v)))
mbed_official 146:f64d43ff0c18 415 #endif
mbed_official 146:f64d43ff0c18 416 //@}
mbed_official 146:f64d43ff0c18 417
mbed_official 146:f64d43ff0c18 418 /*!
mbed_official 146:f64d43ff0c18 419 * @name Register AXBS_CRSn, field PCTL[5:4] (RW)
mbed_official 146:f64d43ff0c18 420 *
mbed_official 146:f64d43ff0c18 421 * Determines the slave port's parking control. The low-power park feature
mbed_official 146:f64d43ff0c18 422 * results in an overall power savings if the slave port is not saturated. However,
mbed_official 146:f64d43ff0c18 423 * this forces an extra latency clock when any master tries to access the slave
mbed_official 146:f64d43ff0c18 424 * port while not in use because it is not parked on any master.
mbed_official 146:f64d43ff0c18 425 *
mbed_official 146:f64d43ff0c18 426 * Values:
mbed_official 146:f64d43ff0c18 427 * - 00 - When no master makes a request, the arbiter parks the slave port on
mbed_official 146:f64d43ff0c18 428 * the master port defined by the PARK field
mbed_official 146:f64d43ff0c18 429 * - 01 - When no master makes a request, the arbiter parks the slave port on
mbed_official 146:f64d43ff0c18 430 * the last master to be in control of the slave port
mbed_official 146:f64d43ff0c18 431 * - 10 - When no master makes a request, the slave port is not parked on a
mbed_official 146:f64d43ff0c18 432 * master and the arbiter drives all outputs to a constant safe state
mbed_official 146:f64d43ff0c18 433 * - 11 - Reserved
mbed_official 146:f64d43ff0c18 434 */
mbed_official 146:f64d43ff0c18 435 //@{
mbed_official 146:f64d43ff0c18 436 #define BP_AXBS_CRSn_PCTL (4U) //!< Bit position for AXBS_CRSn_PCTL.
mbed_official 146:f64d43ff0c18 437 #define BM_AXBS_CRSn_PCTL (0x00000030U) //!< Bit mask for AXBS_CRSn_PCTL.
mbed_official 146:f64d43ff0c18 438 #define BS_AXBS_CRSn_PCTL (2U) //!< Bit field size in bits for AXBS_CRSn_PCTL.
mbed_official 146:f64d43ff0c18 439
mbed_official 146:f64d43ff0c18 440 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 441 //! @brief Read current value of the AXBS_CRSn_PCTL field.
mbed_official 146:f64d43ff0c18 442 #define BR_AXBS_CRSn_PCTL(n) (HW_AXBS_CRSn(n).B.PCTL)
mbed_official 146:f64d43ff0c18 443 #endif
mbed_official 146:f64d43ff0c18 444
mbed_official 146:f64d43ff0c18 445 //! @brief Format value for bitfield AXBS_CRSn_PCTL.
mbed_official 146:f64d43ff0c18 446 #define BF_AXBS_CRSn_PCTL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_CRSn_PCTL), uint32_t) & BM_AXBS_CRSn_PCTL)
mbed_official 146:f64d43ff0c18 447
mbed_official 146:f64d43ff0c18 448 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 449 //! @brief Set the PCTL field to a new value.
mbed_official 146:f64d43ff0c18 450 #define BW_AXBS_CRSn_PCTL(n, v) (HW_AXBS_CRSn_WR(n, (HW_AXBS_CRSn_RD(n) & ~BM_AXBS_CRSn_PCTL) | BF_AXBS_CRSn_PCTL(v)))
mbed_official 146:f64d43ff0c18 451 #endif
mbed_official 146:f64d43ff0c18 452 //@}
mbed_official 146:f64d43ff0c18 453
mbed_official 146:f64d43ff0c18 454 /*!
mbed_official 146:f64d43ff0c18 455 * @name Register AXBS_CRSn, field ARB[9:8] (RW)
mbed_official 146:f64d43ff0c18 456 *
mbed_official 146:f64d43ff0c18 457 * Selects the arbitration policy for the slave port.
mbed_official 146:f64d43ff0c18 458 *
mbed_official 146:f64d43ff0c18 459 * Values:
mbed_official 146:f64d43ff0c18 460 * - 00 - Fixed priority
mbed_official 146:f64d43ff0c18 461 * - 01 - Round-robin, or rotating, priority
mbed_official 146:f64d43ff0c18 462 * - 10 - Reserved
mbed_official 146:f64d43ff0c18 463 * - 11 - Reserved
mbed_official 146:f64d43ff0c18 464 */
mbed_official 146:f64d43ff0c18 465 //@{
mbed_official 146:f64d43ff0c18 466 #define BP_AXBS_CRSn_ARB (8U) //!< Bit position for AXBS_CRSn_ARB.
mbed_official 146:f64d43ff0c18 467 #define BM_AXBS_CRSn_ARB (0x00000300U) //!< Bit mask for AXBS_CRSn_ARB.
mbed_official 146:f64d43ff0c18 468 #define BS_AXBS_CRSn_ARB (2U) //!< Bit field size in bits for AXBS_CRSn_ARB.
mbed_official 146:f64d43ff0c18 469
mbed_official 146:f64d43ff0c18 470 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 471 //! @brief Read current value of the AXBS_CRSn_ARB field.
mbed_official 146:f64d43ff0c18 472 #define BR_AXBS_CRSn_ARB(n) (HW_AXBS_CRSn(n).B.ARB)
mbed_official 146:f64d43ff0c18 473 #endif
mbed_official 146:f64d43ff0c18 474
mbed_official 146:f64d43ff0c18 475 //! @brief Format value for bitfield AXBS_CRSn_ARB.
mbed_official 146:f64d43ff0c18 476 #define BF_AXBS_CRSn_ARB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_CRSn_ARB), uint32_t) & BM_AXBS_CRSn_ARB)
mbed_official 146:f64d43ff0c18 477
mbed_official 146:f64d43ff0c18 478 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 479 //! @brief Set the ARB field to a new value.
mbed_official 146:f64d43ff0c18 480 #define BW_AXBS_CRSn_ARB(n, v) (HW_AXBS_CRSn_WR(n, (HW_AXBS_CRSn_RD(n) & ~BM_AXBS_CRSn_ARB) | BF_AXBS_CRSn_ARB(v)))
mbed_official 146:f64d43ff0c18 481 #endif
mbed_official 146:f64d43ff0c18 482 //@}
mbed_official 146:f64d43ff0c18 483
mbed_official 146:f64d43ff0c18 484 /*!
mbed_official 146:f64d43ff0c18 485 * @name Register AXBS_CRSn, field HLP[30] (RW)
mbed_official 146:f64d43ff0c18 486 *
mbed_official 146:f64d43ff0c18 487 * Sets the initial arbitration priority for low power mode requests . Setting
mbed_official 146:f64d43ff0c18 488 * this bit will not affect the request for low power mode from attaining highest
mbed_official 146:f64d43ff0c18 489 * priority once it has control of the slave ports.
mbed_official 146:f64d43ff0c18 490 *
mbed_official 146:f64d43ff0c18 491 * Values:
mbed_official 146:f64d43ff0c18 492 * - 0 - The low power mode request has the highest priority for arbitration on
mbed_official 146:f64d43ff0c18 493 * this slave port
mbed_official 146:f64d43ff0c18 494 * - 1 - The low power mode request has the lowest initial priority for
mbed_official 146:f64d43ff0c18 495 * arbitration on this slave port
mbed_official 146:f64d43ff0c18 496 */
mbed_official 146:f64d43ff0c18 497 //@{
mbed_official 146:f64d43ff0c18 498 #define BP_AXBS_CRSn_HLP (30U) //!< Bit position for AXBS_CRSn_HLP.
mbed_official 146:f64d43ff0c18 499 #define BM_AXBS_CRSn_HLP (0x40000000U) //!< Bit mask for AXBS_CRSn_HLP.
mbed_official 146:f64d43ff0c18 500 #define BS_AXBS_CRSn_HLP (1U) //!< Bit field size in bits for AXBS_CRSn_HLP.
mbed_official 146:f64d43ff0c18 501
mbed_official 146:f64d43ff0c18 502 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 503 //! @brief Read current value of the AXBS_CRSn_HLP field.
mbed_official 146:f64d43ff0c18 504 #define BR_AXBS_CRSn_HLP(n) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(n), BP_AXBS_CRSn_HLP))
mbed_official 146:f64d43ff0c18 505 #endif
mbed_official 146:f64d43ff0c18 506
mbed_official 146:f64d43ff0c18 507 //! @brief Format value for bitfield AXBS_CRSn_HLP.
mbed_official 146:f64d43ff0c18 508 #define BF_AXBS_CRSn_HLP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_CRSn_HLP), uint32_t) & BM_AXBS_CRSn_HLP)
mbed_official 146:f64d43ff0c18 509
mbed_official 146:f64d43ff0c18 510 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 511 //! @brief Set the HLP field to a new value.
mbed_official 146:f64d43ff0c18 512 #define BW_AXBS_CRSn_HLP(n, v) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(n), BP_AXBS_CRSn_HLP) = (v))
mbed_official 146:f64d43ff0c18 513 #endif
mbed_official 146:f64d43ff0c18 514 //@}
mbed_official 146:f64d43ff0c18 515
mbed_official 146:f64d43ff0c18 516 /*!
mbed_official 146:f64d43ff0c18 517 * @name Register AXBS_CRSn, field RO[31] (RW)
mbed_official 146:f64d43ff0c18 518 *
mbed_official 146:f64d43ff0c18 519 * Forces the slave port's CSRn and PRSn registers to be read-only. After set,
mbed_official 146:f64d43ff0c18 520 * only a hardware reset clears it.
mbed_official 146:f64d43ff0c18 521 *
mbed_official 146:f64d43ff0c18 522 * Values:
mbed_official 146:f64d43ff0c18 523 * - 0 - The slave port's registers are writeable
mbed_official 146:f64d43ff0c18 524 * - 1 - The slave port's registers are read-only and cannot be written.
mbed_official 146:f64d43ff0c18 525 * Attempted writes have no effect on the registers and result in a bus error
mbed_official 146:f64d43ff0c18 526 * response.
mbed_official 146:f64d43ff0c18 527 */
mbed_official 146:f64d43ff0c18 528 //@{
mbed_official 146:f64d43ff0c18 529 #define BP_AXBS_CRSn_RO (31U) //!< Bit position for AXBS_CRSn_RO.
mbed_official 146:f64d43ff0c18 530 #define BM_AXBS_CRSn_RO (0x80000000U) //!< Bit mask for AXBS_CRSn_RO.
mbed_official 146:f64d43ff0c18 531 #define BS_AXBS_CRSn_RO (1U) //!< Bit field size in bits for AXBS_CRSn_RO.
mbed_official 146:f64d43ff0c18 532
mbed_official 146:f64d43ff0c18 533 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 534 //! @brief Read current value of the AXBS_CRSn_RO field.
mbed_official 146:f64d43ff0c18 535 #define BR_AXBS_CRSn_RO(n) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(n), BP_AXBS_CRSn_RO))
mbed_official 146:f64d43ff0c18 536 #endif
mbed_official 146:f64d43ff0c18 537
mbed_official 146:f64d43ff0c18 538 //! @brief Format value for bitfield AXBS_CRSn_RO.
mbed_official 146:f64d43ff0c18 539 #define BF_AXBS_CRSn_RO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_CRSn_RO), uint32_t) & BM_AXBS_CRSn_RO)
mbed_official 146:f64d43ff0c18 540
mbed_official 146:f64d43ff0c18 541 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 542 //! @brief Set the RO field to a new value.
mbed_official 146:f64d43ff0c18 543 #define BW_AXBS_CRSn_RO(n, v) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(n), BP_AXBS_CRSn_RO) = (v))
mbed_official 146:f64d43ff0c18 544 #endif
mbed_official 146:f64d43ff0c18 545 //@}
mbed_official 146:f64d43ff0c18 546
mbed_official 146:f64d43ff0c18 547 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 548 // HW_AXBS_MGPCR0 - Master General Purpose Control Register
mbed_official 146:f64d43ff0c18 549 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 550
mbed_official 146:f64d43ff0c18 551 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 552 /*!
mbed_official 146:f64d43ff0c18 553 * @brief HW_AXBS_MGPCR0 - Master General Purpose Control Register (RW)
mbed_official 146:f64d43ff0c18 554 *
mbed_official 146:f64d43ff0c18 555 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 556 *
mbed_official 146:f64d43ff0c18 557 * The MGPCR controls only whether the master's undefined length burst accesses
mbed_official 146:f64d43ff0c18 558 * are allowed to complete uninterrupted or whether they can be broken by
mbed_official 146:f64d43ff0c18 559 * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
mbed_official 146:f64d43ff0c18 560 * mode with 32-bit accesses.
mbed_official 146:f64d43ff0c18 561 */
mbed_official 146:f64d43ff0c18 562 typedef union _hw_axbs_mgpcr0
mbed_official 146:f64d43ff0c18 563 {
mbed_official 146:f64d43ff0c18 564 uint32_t U;
mbed_official 146:f64d43ff0c18 565 struct _hw_axbs_mgpcr0_bitfields
mbed_official 146:f64d43ff0c18 566 {
mbed_official 146:f64d43ff0c18 567 uint32_t AULB : 3; //!< [2:0] Arbitrates On Undefined Length Bursts
mbed_official 146:f64d43ff0c18 568 uint32_t RESERVED0 : 29; //!< [31:3]
mbed_official 146:f64d43ff0c18 569 } B;
mbed_official 146:f64d43ff0c18 570 } hw_axbs_mgpcr0_t;
mbed_official 146:f64d43ff0c18 571 #endif
mbed_official 146:f64d43ff0c18 572
mbed_official 146:f64d43ff0c18 573 /*!
mbed_official 146:f64d43ff0c18 574 * @name Constants and macros for entire AXBS_MGPCR0 register
mbed_official 146:f64d43ff0c18 575 */
mbed_official 146:f64d43ff0c18 576 //@{
mbed_official 146:f64d43ff0c18 577 #define HW_AXBS_MGPCR0_ADDR (REGS_AXBS_BASE + 0x800U)
mbed_official 146:f64d43ff0c18 578
mbed_official 146:f64d43ff0c18 579 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 580 #define HW_AXBS_MGPCR0 (*(__IO hw_axbs_mgpcr0_t *) HW_AXBS_MGPCR0_ADDR)
mbed_official 146:f64d43ff0c18 581 #define HW_AXBS_MGPCR0_RD() (HW_AXBS_MGPCR0.U)
mbed_official 146:f64d43ff0c18 582 #define HW_AXBS_MGPCR0_WR(v) (HW_AXBS_MGPCR0.U = (v))
mbed_official 146:f64d43ff0c18 583 #define HW_AXBS_MGPCR0_SET(v) (HW_AXBS_MGPCR0_WR(HW_AXBS_MGPCR0_RD() | (v)))
mbed_official 146:f64d43ff0c18 584 #define HW_AXBS_MGPCR0_CLR(v) (HW_AXBS_MGPCR0_WR(HW_AXBS_MGPCR0_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 585 #define HW_AXBS_MGPCR0_TOG(v) (HW_AXBS_MGPCR0_WR(HW_AXBS_MGPCR0_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 586 #endif
mbed_official 146:f64d43ff0c18 587 //@}
mbed_official 146:f64d43ff0c18 588
mbed_official 146:f64d43ff0c18 589 /*
mbed_official 146:f64d43ff0c18 590 * Constants & macros for individual AXBS_MGPCR0 bitfields
mbed_official 146:f64d43ff0c18 591 */
mbed_official 146:f64d43ff0c18 592
mbed_official 146:f64d43ff0c18 593 /*!
mbed_official 146:f64d43ff0c18 594 * @name Register AXBS_MGPCR0, field AULB[2:0] (RW)
mbed_official 146:f64d43ff0c18 595 *
mbed_official 146:f64d43ff0c18 596 * Determines whether, and when, the crossbar switch arbitrates away the slave
mbed_official 146:f64d43ff0c18 597 * port the master owns when the master is performing undefined length burst
mbed_official 146:f64d43ff0c18 598 * accesses.
mbed_official 146:f64d43ff0c18 599 *
mbed_official 146:f64d43ff0c18 600 * Values:
mbed_official 146:f64d43ff0c18 601 * - 000 - No arbitration is allowed during an undefined length burst
mbed_official 146:f64d43ff0c18 602 * - 001 - Arbitration is allowed at any time during an undefined length burst
mbed_official 146:f64d43ff0c18 603 * - 010 - Arbitration is allowed after four beats of an undefined length burst
mbed_official 146:f64d43ff0c18 604 * - 011 - Arbitration is allowed after eight beats of an undefined length burst
mbed_official 146:f64d43ff0c18 605 * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
mbed_official 146:f64d43ff0c18 606 * - 101 - Reserved
mbed_official 146:f64d43ff0c18 607 * - 110 - Reserved
mbed_official 146:f64d43ff0c18 608 * - 111 - Reserved
mbed_official 146:f64d43ff0c18 609 */
mbed_official 146:f64d43ff0c18 610 //@{
mbed_official 146:f64d43ff0c18 611 #define BP_AXBS_MGPCR0_AULB (0U) //!< Bit position for AXBS_MGPCR0_AULB.
mbed_official 146:f64d43ff0c18 612 #define BM_AXBS_MGPCR0_AULB (0x00000007U) //!< Bit mask for AXBS_MGPCR0_AULB.
mbed_official 146:f64d43ff0c18 613 #define BS_AXBS_MGPCR0_AULB (3U) //!< Bit field size in bits for AXBS_MGPCR0_AULB.
mbed_official 146:f64d43ff0c18 614
mbed_official 146:f64d43ff0c18 615 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 616 //! @brief Read current value of the AXBS_MGPCR0_AULB field.
mbed_official 146:f64d43ff0c18 617 #define BR_AXBS_MGPCR0_AULB (HW_AXBS_MGPCR0.B.AULB)
mbed_official 146:f64d43ff0c18 618 #endif
mbed_official 146:f64d43ff0c18 619
mbed_official 146:f64d43ff0c18 620 //! @brief Format value for bitfield AXBS_MGPCR0_AULB.
mbed_official 146:f64d43ff0c18 621 #define BF_AXBS_MGPCR0_AULB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_MGPCR0_AULB), uint32_t) & BM_AXBS_MGPCR0_AULB)
mbed_official 146:f64d43ff0c18 622
mbed_official 146:f64d43ff0c18 623 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 624 //! @brief Set the AULB field to a new value.
mbed_official 146:f64d43ff0c18 625 #define BW_AXBS_MGPCR0_AULB(v) (HW_AXBS_MGPCR0_WR((HW_AXBS_MGPCR0_RD() & ~BM_AXBS_MGPCR0_AULB) | BF_AXBS_MGPCR0_AULB(v)))
mbed_official 146:f64d43ff0c18 626 #endif
mbed_official 146:f64d43ff0c18 627 //@}
mbed_official 146:f64d43ff0c18 628
mbed_official 146:f64d43ff0c18 629 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 630 // HW_AXBS_MGPCR1 - Master General Purpose Control Register
mbed_official 146:f64d43ff0c18 631 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 632
mbed_official 146:f64d43ff0c18 633 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 634 /*!
mbed_official 146:f64d43ff0c18 635 * @brief HW_AXBS_MGPCR1 - Master General Purpose Control Register (RW)
mbed_official 146:f64d43ff0c18 636 *
mbed_official 146:f64d43ff0c18 637 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 638 *
mbed_official 146:f64d43ff0c18 639 * The MGPCR controls only whether the master's undefined length burst accesses
mbed_official 146:f64d43ff0c18 640 * are allowed to complete uninterrupted or whether they can be broken by
mbed_official 146:f64d43ff0c18 641 * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
mbed_official 146:f64d43ff0c18 642 * mode with 32-bit accesses.
mbed_official 146:f64d43ff0c18 643 */
mbed_official 146:f64d43ff0c18 644 typedef union _hw_axbs_mgpcr1
mbed_official 146:f64d43ff0c18 645 {
mbed_official 146:f64d43ff0c18 646 uint32_t U;
mbed_official 146:f64d43ff0c18 647 struct _hw_axbs_mgpcr1_bitfields
mbed_official 146:f64d43ff0c18 648 {
mbed_official 146:f64d43ff0c18 649 uint32_t AULB : 3; //!< [2:0] Arbitrates On Undefined Length Bursts
mbed_official 146:f64d43ff0c18 650 uint32_t RESERVED0 : 29; //!< [31:3]
mbed_official 146:f64d43ff0c18 651 } B;
mbed_official 146:f64d43ff0c18 652 } hw_axbs_mgpcr1_t;
mbed_official 146:f64d43ff0c18 653 #endif
mbed_official 146:f64d43ff0c18 654
mbed_official 146:f64d43ff0c18 655 /*!
mbed_official 146:f64d43ff0c18 656 * @name Constants and macros for entire AXBS_MGPCR1 register
mbed_official 146:f64d43ff0c18 657 */
mbed_official 146:f64d43ff0c18 658 //@{
mbed_official 146:f64d43ff0c18 659 #define HW_AXBS_MGPCR1_ADDR (REGS_AXBS_BASE + 0x900U)
mbed_official 146:f64d43ff0c18 660
mbed_official 146:f64d43ff0c18 661 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 662 #define HW_AXBS_MGPCR1 (*(__IO hw_axbs_mgpcr1_t *) HW_AXBS_MGPCR1_ADDR)
mbed_official 146:f64d43ff0c18 663 #define HW_AXBS_MGPCR1_RD() (HW_AXBS_MGPCR1.U)
mbed_official 146:f64d43ff0c18 664 #define HW_AXBS_MGPCR1_WR(v) (HW_AXBS_MGPCR1.U = (v))
mbed_official 146:f64d43ff0c18 665 #define HW_AXBS_MGPCR1_SET(v) (HW_AXBS_MGPCR1_WR(HW_AXBS_MGPCR1_RD() | (v)))
mbed_official 146:f64d43ff0c18 666 #define HW_AXBS_MGPCR1_CLR(v) (HW_AXBS_MGPCR1_WR(HW_AXBS_MGPCR1_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 667 #define HW_AXBS_MGPCR1_TOG(v) (HW_AXBS_MGPCR1_WR(HW_AXBS_MGPCR1_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 668 #endif
mbed_official 146:f64d43ff0c18 669 //@}
mbed_official 146:f64d43ff0c18 670
mbed_official 146:f64d43ff0c18 671 /*
mbed_official 146:f64d43ff0c18 672 * Constants & macros for individual AXBS_MGPCR1 bitfields
mbed_official 146:f64d43ff0c18 673 */
mbed_official 146:f64d43ff0c18 674
mbed_official 146:f64d43ff0c18 675 /*!
mbed_official 146:f64d43ff0c18 676 * @name Register AXBS_MGPCR1, field AULB[2:0] (RW)
mbed_official 146:f64d43ff0c18 677 *
mbed_official 146:f64d43ff0c18 678 * Determines whether, and when, the crossbar switch arbitrates away the slave
mbed_official 146:f64d43ff0c18 679 * port the master owns when the master is performing undefined length burst
mbed_official 146:f64d43ff0c18 680 * accesses.
mbed_official 146:f64d43ff0c18 681 *
mbed_official 146:f64d43ff0c18 682 * Values:
mbed_official 146:f64d43ff0c18 683 * - 000 - No arbitration is allowed during an undefined length burst
mbed_official 146:f64d43ff0c18 684 * - 001 - Arbitration is allowed at any time during an undefined length burst
mbed_official 146:f64d43ff0c18 685 * - 010 - Arbitration is allowed after four beats of an undefined length burst
mbed_official 146:f64d43ff0c18 686 * - 011 - Arbitration is allowed after eight beats of an undefined length burst
mbed_official 146:f64d43ff0c18 687 * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
mbed_official 146:f64d43ff0c18 688 * - 101 - Reserved
mbed_official 146:f64d43ff0c18 689 * - 110 - Reserved
mbed_official 146:f64d43ff0c18 690 * - 111 - Reserved
mbed_official 146:f64d43ff0c18 691 */
mbed_official 146:f64d43ff0c18 692 //@{
mbed_official 146:f64d43ff0c18 693 #define BP_AXBS_MGPCR1_AULB (0U) //!< Bit position for AXBS_MGPCR1_AULB.
mbed_official 146:f64d43ff0c18 694 #define BM_AXBS_MGPCR1_AULB (0x00000007U) //!< Bit mask for AXBS_MGPCR1_AULB.
mbed_official 146:f64d43ff0c18 695 #define BS_AXBS_MGPCR1_AULB (3U) //!< Bit field size in bits for AXBS_MGPCR1_AULB.
mbed_official 146:f64d43ff0c18 696
mbed_official 146:f64d43ff0c18 697 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 698 //! @brief Read current value of the AXBS_MGPCR1_AULB field.
mbed_official 146:f64d43ff0c18 699 #define BR_AXBS_MGPCR1_AULB (HW_AXBS_MGPCR1.B.AULB)
mbed_official 146:f64d43ff0c18 700 #endif
mbed_official 146:f64d43ff0c18 701
mbed_official 146:f64d43ff0c18 702 //! @brief Format value for bitfield AXBS_MGPCR1_AULB.
mbed_official 146:f64d43ff0c18 703 #define BF_AXBS_MGPCR1_AULB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_MGPCR1_AULB), uint32_t) & BM_AXBS_MGPCR1_AULB)
mbed_official 146:f64d43ff0c18 704
mbed_official 146:f64d43ff0c18 705 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 706 //! @brief Set the AULB field to a new value.
mbed_official 146:f64d43ff0c18 707 #define BW_AXBS_MGPCR1_AULB(v) (HW_AXBS_MGPCR1_WR((HW_AXBS_MGPCR1_RD() & ~BM_AXBS_MGPCR1_AULB) | BF_AXBS_MGPCR1_AULB(v)))
mbed_official 146:f64d43ff0c18 708 #endif
mbed_official 146:f64d43ff0c18 709 //@}
mbed_official 146:f64d43ff0c18 710
mbed_official 146:f64d43ff0c18 711 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 712 // HW_AXBS_MGPCR2 - Master General Purpose Control Register
mbed_official 146:f64d43ff0c18 713 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 714
mbed_official 146:f64d43ff0c18 715 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 716 /*!
mbed_official 146:f64d43ff0c18 717 * @brief HW_AXBS_MGPCR2 - Master General Purpose Control Register (RW)
mbed_official 146:f64d43ff0c18 718 *
mbed_official 146:f64d43ff0c18 719 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 720 *
mbed_official 146:f64d43ff0c18 721 * The MGPCR controls only whether the master's undefined length burst accesses
mbed_official 146:f64d43ff0c18 722 * are allowed to complete uninterrupted or whether they can be broken by
mbed_official 146:f64d43ff0c18 723 * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
mbed_official 146:f64d43ff0c18 724 * mode with 32-bit accesses.
mbed_official 146:f64d43ff0c18 725 */
mbed_official 146:f64d43ff0c18 726 typedef union _hw_axbs_mgpcr2
mbed_official 146:f64d43ff0c18 727 {
mbed_official 146:f64d43ff0c18 728 uint32_t U;
mbed_official 146:f64d43ff0c18 729 struct _hw_axbs_mgpcr2_bitfields
mbed_official 146:f64d43ff0c18 730 {
mbed_official 146:f64d43ff0c18 731 uint32_t AULB : 3; //!< [2:0] Arbitrates On Undefined Length Bursts
mbed_official 146:f64d43ff0c18 732 uint32_t RESERVED0 : 29; //!< [31:3]
mbed_official 146:f64d43ff0c18 733 } B;
mbed_official 146:f64d43ff0c18 734 } hw_axbs_mgpcr2_t;
mbed_official 146:f64d43ff0c18 735 #endif
mbed_official 146:f64d43ff0c18 736
mbed_official 146:f64d43ff0c18 737 /*!
mbed_official 146:f64d43ff0c18 738 * @name Constants and macros for entire AXBS_MGPCR2 register
mbed_official 146:f64d43ff0c18 739 */
mbed_official 146:f64d43ff0c18 740 //@{
mbed_official 146:f64d43ff0c18 741 #define HW_AXBS_MGPCR2_ADDR (REGS_AXBS_BASE + 0xA00U)
mbed_official 146:f64d43ff0c18 742
mbed_official 146:f64d43ff0c18 743 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 744 #define HW_AXBS_MGPCR2 (*(__IO hw_axbs_mgpcr2_t *) HW_AXBS_MGPCR2_ADDR)
mbed_official 146:f64d43ff0c18 745 #define HW_AXBS_MGPCR2_RD() (HW_AXBS_MGPCR2.U)
mbed_official 146:f64d43ff0c18 746 #define HW_AXBS_MGPCR2_WR(v) (HW_AXBS_MGPCR2.U = (v))
mbed_official 146:f64d43ff0c18 747 #define HW_AXBS_MGPCR2_SET(v) (HW_AXBS_MGPCR2_WR(HW_AXBS_MGPCR2_RD() | (v)))
mbed_official 146:f64d43ff0c18 748 #define HW_AXBS_MGPCR2_CLR(v) (HW_AXBS_MGPCR2_WR(HW_AXBS_MGPCR2_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 749 #define HW_AXBS_MGPCR2_TOG(v) (HW_AXBS_MGPCR2_WR(HW_AXBS_MGPCR2_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 750 #endif
mbed_official 146:f64d43ff0c18 751 //@}
mbed_official 146:f64d43ff0c18 752
mbed_official 146:f64d43ff0c18 753 /*
mbed_official 146:f64d43ff0c18 754 * Constants & macros for individual AXBS_MGPCR2 bitfields
mbed_official 146:f64d43ff0c18 755 */
mbed_official 146:f64d43ff0c18 756
mbed_official 146:f64d43ff0c18 757 /*!
mbed_official 146:f64d43ff0c18 758 * @name Register AXBS_MGPCR2, field AULB[2:0] (RW)
mbed_official 146:f64d43ff0c18 759 *
mbed_official 146:f64d43ff0c18 760 * Determines whether, and when, the crossbar switch arbitrates away the slave
mbed_official 146:f64d43ff0c18 761 * port the master owns when the master is performing undefined length burst
mbed_official 146:f64d43ff0c18 762 * accesses.
mbed_official 146:f64d43ff0c18 763 *
mbed_official 146:f64d43ff0c18 764 * Values:
mbed_official 146:f64d43ff0c18 765 * - 000 - No arbitration is allowed during an undefined length burst
mbed_official 146:f64d43ff0c18 766 * - 001 - Arbitration is allowed at any time during an undefined length burst
mbed_official 146:f64d43ff0c18 767 * - 010 - Arbitration is allowed after four beats of an undefined length burst
mbed_official 146:f64d43ff0c18 768 * - 011 - Arbitration is allowed after eight beats of an undefined length burst
mbed_official 146:f64d43ff0c18 769 * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
mbed_official 146:f64d43ff0c18 770 * - 101 - Reserved
mbed_official 146:f64d43ff0c18 771 * - 110 - Reserved
mbed_official 146:f64d43ff0c18 772 * - 111 - Reserved
mbed_official 146:f64d43ff0c18 773 */
mbed_official 146:f64d43ff0c18 774 //@{
mbed_official 146:f64d43ff0c18 775 #define BP_AXBS_MGPCR2_AULB (0U) //!< Bit position for AXBS_MGPCR2_AULB.
mbed_official 146:f64d43ff0c18 776 #define BM_AXBS_MGPCR2_AULB (0x00000007U) //!< Bit mask for AXBS_MGPCR2_AULB.
mbed_official 146:f64d43ff0c18 777 #define BS_AXBS_MGPCR2_AULB (3U) //!< Bit field size in bits for AXBS_MGPCR2_AULB.
mbed_official 146:f64d43ff0c18 778
mbed_official 146:f64d43ff0c18 779 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 780 //! @brief Read current value of the AXBS_MGPCR2_AULB field.
mbed_official 146:f64d43ff0c18 781 #define BR_AXBS_MGPCR2_AULB (HW_AXBS_MGPCR2.B.AULB)
mbed_official 146:f64d43ff0c18 782 #endif
mbed_official 146:f64d43ff0c18 783
mbed_official 146:f64d43ff0c18 784 //! @brief Format value for bitfield AXBS_MGPCR2_AULB.
mbed_official 146:f64d43ff0c18 785 #define BF_AXBS_MGPCR2_AULB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_MGPCR2_AULB), uint32_t) & BM_AXBS_MGPCR2_AULB)
mbed_official 146:f64d43ff0c18 786
mbed_official 146:f64d43ff0c18 787 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 788 //! @brief Set the AULB field to a new value.
mbed_official 146:f64d43ff0c18 789 #define BW_AXBS_MGPCR2_AULB(v) (HW_AXBS_MGPCR2_WR((HW_AXBS_MGPCR2_RD() & ~BM_AXBS_MGPCR2_AULB) | BF_AXBS_MGPCR2_AULB(v)))
mbed_official 146:f64d43ff0c18 790 #endif
mbed_official 146:f64d43ff0c18 791 //@}
mbed_official 146:f64d43ff0c18 792
mbed_official 146:f64d43ff0c18 793 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 794 // HW_AXBS_MGPCR3 - Master General Purpose Control Register
mbed_official 146:f64d43ff0c18 795 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 796
mbed_official 146:f64d43ff0c18 797 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 798 /*!
mbed_official 146:f64d43ff0c18 799 * @brief HW_AXBS_MGPCR3 - Master General Purpose Control Register (RW)
mbed_official 146:f64d43ff0c18 800 *
mbed_official 146:f64d43ff0c18 801 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 802 *
mbed_official 146:f64d43ff0c18 803 * The MGPCR controls only whether the master's undefined length burst accesses
mbed_official 146:f64d43ff0c18 804 * are allowed to complete uninterrupted or whether they can be broken by
mbed_official 146:f64d43ff0c18 805 * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
mbed_official 146:f64d43ff0c18 806 * mode with 32-bit accesses.
mbed_official 146:f64d43ff0c18 807 */
mbed_official 146:f64d43ff0c18 808 typedef union _hw_axbs_mgpcr3
mbed_official 146:f64d43ff0c18 809 {
mbed_official 146:f64d43ff0c18 810 uint32_t U;
mbed_official 146:f64d43ff0c18 811 struct _hw_axbs_mgpcr3_bitfields
mbed_official 146:f64d43ff0c18 812 {
mbed_official 146:f64d43ff0c18 813 uint32_t AULB : 3; //!< [2:0] Arbitrates On Undefined Length Bursts
mbed_official 146:f64d43ff0c18 814 uint32_t RESERVED0 : 29; //!< [31:3]
mbed_official 146:f64d43ff0c18 815 } B;
mbed_official 146:f64d43ff0c18 816 } hw_axbs_mgpcr3_t;
mbed_official 146:f64d43ff0c18 817 #endif
mbed_official 146:f64d43ff0c18 818
mbed_official 146:f64d43ff0c18 819 /*!
mbed_official 146:f64d43ff0c18 820 * @name Constants and macros for entire AXBS_MGPCR3 register
mbed_official 146:f64d43ff0c18 821 */
mbed_official 146:f64d43ff0c18 822 //@{
mbed_official 146:f64d43ff0c18 823 #define HW_AXBS_MGPCR3_ADDR (REGS_AXBS_BASE + 0xB00U)
mbed_official 146:f64d43ff0c18 824
mbed_official 146:f64d43ff0c18 825 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 826 #define HW_AXBS_MGPCR3 (*(__IO hw_axbs_mgpcr3_t *) HW_AXBS_MGPCR3_ADDR)
mbed_official 146:f64d43ff0c18 827 #define HW_AXBS_MGPCR3_RD() (HW_AXBS_MGPCR3.U)
mbed_official 146:f64d43ff0c18 828 #define HW_AXBS_MGPCR3_WR(v) (HW_AXBS_MGPCR3.U = (v))
mbed_official 146:f64d43ff0c18 829 #define HW_AXBS_MGPCR3_SET(v) (HW_AXBS_MGPCR3_WR(HW_AXBS_MGPCR3_RD() | (v)))
mbed_official 146:f64d43ff0c18 830 #define HW_AXBS_MGPCR3_CLR(v) (HW_AXBS_MGPCR3_WR(HW_AXBS_MGPCR3_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 831 #define HW_AXBS_MGPCR3_TOG(v) (HW_AXBS_MGPCR3_WR(HW_AXBS_MGPCR3_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 832 #endif
mbed_official 146:f64d43ff0c18 833 //@}
mbed_official 146:f64d43ff0c18 834
mbed_official 146:f64d43ff0c18 835 /*
mbed_official 146:f64d43ff0c18 836 * Constants & macros for individual AXBS_MGPCR3 bitfields
mbed_official 146:f64d43ff0c18 837 */
mbed_official 146:f64d43ff0c18 838
mbed_official 146:f64d43ff0c18 839 /*!
mbed_official 146:f64d43ff0c18 840 * @name Register AXBS_MGPCR3, field AULB[2:0] (RW)
mbed_official 146:f64d43ff0c18 841 *
mbed_official 146:f64d43ff0c18 842 * Determines whether, and when, the crossbar switch arbitrates away the slave
mbed_official 146:f64d43ff0c18 843 * port the master owns when the master is performing undefined length burst
mbed_official 146:f64d43ff0c18 844 * accesses.
mbed_official 146:f64d43ff0c18 845 *
mbed_official 146:f64d43ff0c18 846 * Values:
mbed_official 146:f64d43ff0c18 847 * - 000 - No arbitration is allowed during an undefined length burst
mbed_official 146:f64d43ff0c18 848 * - 001 - Arbitration is allowed at any time during an undefined length burst
mbed_official 146:f64d43ff0c18 849 * - 010 - Arbitration is allowed after four beats of an undefined length burst
mbed_official 146:f64d43ff0c18 850 * - 011 - Arbitration is allowed after eight beats of an undefined length burst
mbed_official 146:f64d43ff0c18 851 * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
mbed_official 146:f64d43ff0c18 852 * - 101 - Reserved
mbed_official 146:f64d43ff0c18 853 * - 110 - Reserved
mbed_official 146:f64d43ff0c18 854 * - 111 - Reserved
mbed_official 146:f64d43ff0c18 855 */
mbed_official 146:f64d43ff0c18 856 //@{
mbed_official 146:f64d43ff0c18 857 #define BP_AXBS_MGPCR3_AULB (0U) //!< Bit position for AXBS_MGPCR3_AULB.
mbed_official 146:f64d43ff0c18 858 #define BM_AXBS_MGPCR3_AULB (0x00000007U) //!< Bit mask for AXBS_MGPCR3_AULB.
mbed_official 146:f64d43ff0c18 859 #define BS_AXBS_MGPCR3_AULB (3U) //!< Bit field size in bits for AXBS_MGPCR3_AULB.
mbed_official 146:f64d43ff0c18 860
mbed_official 146:f64d43ff0c18 861 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 862 //! @brief Read current value of the AXBS_MGPCR3_AULB field.
mbed_official 146:f64d43ff0c18 863 #define BR_AXBS_MGPCR3_AULB (HW_AXBS_MGPCR3.B.AULB)
mbed_official 146:f64d43ff0c18 864 #endif
mbed_official 146:f64d43ff0c18 865
mbed_official 146:f64d43ff0c18 866 //! @brief Format value for bitfield AXBS_MGPCR3_AULB.
mbed_official 146:f64d43ff0c18 867 #define BF_AXBS_MGPCR3_AULB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_MGPCR3_AULB), uint32_t) & BM_AXBS_MGPCR3_AULB)
mbed_official 146:f64d43ff0c18 868
mbed_official 146:f64d43ff0c18 869 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 870 //! @brief Set the AULB field to a new value.
mbed_official 146:f64d43ff0c18 871 #define BW_AXBS_MGPCR3_AULB(v) (HW_AXBS_MGPCR3_WR((HW_AXBS_MGPCR3_RD() & ~BM_AXBS_MGPCR3_AULB) | BF_AXBS_MGPCR3_AULB(v)))
mbed_official 146:f64d43ff0c18 872 #endif
mbed_official 146:f64d43ff0c18 873 //@}
mbed_official 146:f64d43ff0c18 874
mbed_official 146:f64d43ff0c18 875 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 876 // HW_AXBS_MGPCR4 - Master General Purpose Control Register
mbed_official 146:f64d43ff0c18 877 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 878
mbed_official 146:f64d43ff0c18 879 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 880 /*!
mbed_official 146:f64d43ff0c18 881 * @brief HW_AXBS_MGPCR4 - Master General Purpose Control Register (RW)
mbed_official 146:f64d43ff0c18 882 *
mbed_official 146:f64d43ff0c18 883 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 884 *
mbed_official 146:f64d43ff0c18 885 * The MGPCR controls only whether the master's undefined length burst accesses
mbed_official 146:f64d43ff0c18 886 * are allowed to complete uninterrupted or whether they can be broken by
mbed_official 146:f64d43ff0c18 887 * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
mbed_official 146:f64d43ff0c18 888 * mode with 32-bit accesses.
mbed_official 146:f64d43ff0c18 889 */
mbed_official 146:f64d43ff0c18 890 typedef union _hw_axbs_mgpcr4
mbed_official 146:f64d43ff0c18 891 {
mbed_official 146:f64d43ff0c18 892 uint32_t U;
mbed_official 146:f64d43ff0c18 893 struct _hw_axbs_mgpcr4_bitfields
mbed_official 146:f64d43ff0c18 894 {
mbed_official 146:f64d43ff0c18 895 uint32_t AULB : 3; //!< [2:0] Arbitrates On Undefined Length Bursts
mbed_official 146:f64d43ff0c18 896 uint32_t RESERVED0 : 29; //!< [31:3]
mbed_official 146:f64d43ff0c18 897 } B;
mbed_official 146:f64d43ff0c18 898 } hw_axbs_mgpcr4_t;
mbed_official 146:f64d43ff0c18 899 #endif
mbed_official 146:f64d43ff0c18 900
mbed_official 146:f64d43ff0c18 901 /*!
mbed_official 146:f64d43ff0c18 902 * @name Constants and macros for entire AXBS_MGPCR4 register
mbed_official 146:f64d43ff0c18 903 */
mbed_official 146:f64d43ff0c18 904 //@{
mbed_official 146:f64d43ff0c18 905 #define HW_AXBS_MGPCR4_ADDR (REGS_AXBS_BASE + 0xC00U)
mbed_official 146:f64d43ff0c18 906
mbed_official 146:f64d43ff0c18 907 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 908 #define HW_AXBS_MGPCR4 (*(__IO hw_axbs_mgpcr4_t *) HW_AXBS_MGPCR4_ADDR)
mbed_official 146:f64d43ff0c18 909 #define HW_AXBS_MGPCR4_RD() (HW_AXBS_MGPCR4.U)
mbed_official 146:f64d43ff0c18 910 #define HW_AXBS_MGPCR4_WR(v) (HW_AXBS_MGPCR4.U = (v))
mbed_official 146:f64d43ff0c18 911 #define HW_AXBS_MGPCR4_SET(v) (HW_AXBS_MGPCR4_WR(HW_AXBS_MGPCR4_RD() | (v)))
mbed_official 146:f64d43ff0c18 912 #define HW_AXBS_MGPCR4_CLR(v) (HW_AXBS_MGPCR4_WR(HW_AXBS_MGPCR4_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 913 #define HW_AXBS_MGPCR4_TOG(v) (HW_AXBS_MGPCR4_WR(HW_AXBS_MGPCR4_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 914 #endif
mbed_official 146:f64d43ff0c18 915 //@}
mbed_official 146:f64d43ff0c18 916
mbed_official 146:f64d43ff0c18 917 /*
mbed_official 146:f64d43ff0c18 918 * Constants & macros for individual AXBS_MGPCR4 bitfields
mbed_official 146:f64d43ff0c18 919 */
mbed_official 146:f64d43ff0c18 920
mbed_official 146:f64d43ff0c18 921 /*!
mbed_official 146:f64d43ff0c18 922 * @name Register AXBS_MGPCR4, field AULB[2:0] (RW)
mbed_official 146:f64d43ff0c18 923 *
mbed_official 146:f64d43ff0c18 924 * Determines whether, and when, the crossbar switch arbitrates away the slave
mbed_official 146:f64d43ff0c18 925 * port the master owns when the master is performing undefined length burst
mbed_official 146:f64d43ff0c18 926 * accesses.
mbed_official 146:f64d43ff0c18 927 *
mbed_official 146:f64d43ff0c18 928 * Values:
mbed_official 146:f64d43ff0c18 929 * - 000 - No arbitration is allowed during an undefined length burst
mbed_official 146:f64d43ff0c18 930 * - 001 - Arbitration is allowed at any time during an undefined length burst
mbed_official 146:f64d43ff0c18 931 * - 010 - Arbitration is allowed after four beats of an undefined length burst
mbed_official 146:f64d43ff0c18 932 * - 011 - Arbitration is allowed after eight beats of an undefined length burst
mbed_official 146:f64d43ff0c18 933 * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
mbed_official 146:f64d43ff0c18 934 * - 101 - Reserved
mbed_official 146:f64d43ff0c18 935 * - 110 - Reserved
mbed_official 146:f64d43ff0c18 936 * - 111 - Reserved
mbed_official 146:f64d43ff0c18 937 */
mbed_official 146:f64d43ff0c18 938 //@{
mbed_official 146:f64d43ff0c18 939 #define BP_AXBS_MGPCR4_AULB (0U) //!< Bit position for AXBS_MGPCR4_AULB.
mbed_official 146:f64d43ff0c18 940 #define BM_AXBS_MGPCR4_AULB (0x00000007U) //!< Bit mask for AXBS_MGPCR4_AULB.
mbed_official 146:f64d43ff0c18 941 #define BS_AXBS_MGPCR4_AULB (3U) //!< Bit field size in bits for AXBS_MGPCR4_AULB.
mbed_official 146:f64d43ff0c18 942
mbed_official 146:f64d43ff0c18 943 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 944 //! @brief Read current value of the AXBS_MGPCR4_AULB field.
mbed_official 146:f64d43ff0c18 945 #define BR_AXBS_MGPCR4_AULB (HW_AXBS_MGPCR4.B.AULB)
mbed_official 146:f64d43ff0c18 946 #endif
mbed_official 146:f64d43ff0c18 947
mbed_official 146:f64d43ff0c18 948 //! @brief Format value for bitfield AXBS_MGPCR4_AULB.
mbed_official 146:f64d43ff0c18 949 #define BF_AXBS_MGPCR4_AULB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_MGPCR4_AULB), uint32_t) & BM_AXBS_MGPCR4_AULB)
mbed_official 146:f64d43ff0c18 950
mbed_official 146:f64d43ff0c18 951 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 952 //! @brief Set the AULB field to a new value.
mbed_official 146:f64d43ff0c18 953 #define BW_AXBS_MGPCR4_AULB(v) (HW_AXBS_MGPCR4_WR((HW_AXBS_MGPCR4_RD() & ~BM_AXBS_MGPCR4_AULB) | BF_AXBS_MGPCR4_AULB(v)))
mbed_official 146:f64d43ff0c18 954 #endif
mbed_official 146:f64d43ff0c18 955 //@}
mbed_official 146:f64d43ff0c18 956
mbed_official 146:f64d43ff0c18 957 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 958 // HW_AXBS_MGPCR5 - Master General Purpose Control Register
mbed_official 146:f64d43ff0c18 959 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 960
mbed_official 146:f64d43ff0c18 961 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 962 /*!
mbed_official 146:f64d43ff0c18 963 * @brief HW_AXBS_MGPCR5 - Master General Purpose Control Register (RW)
mbed_official 146:f64d43ff0c18 964 *
mbed_official 146:f64d43ff0c18 965 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 966 *
mbed_official 146:f64d43ff0c18 967 * The MGPCR controls only whether the master's undefined length burst accesses
mbed_official 146:f64d43ff0c18 968 * are allowed to complete uninterrupted or whether they can be broken by
mbed_official 146:f64d43ff0c18 969 * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
mbed_official 146:f64d43ff0c18 970 * mode with 32-bit accesses.
mbed_official 146:f64d43ff0c18 971 */
mbed_official 146:f64d43ff0c18 972 typedef union _hw_axbs_mgpcr5
mbed_official 146:f64d43ff0c18 973 {
mbed_official 146:f64d43ff0c18 974 uint32_t U;
mbed_official 146:f64d43ff0c18 975 struct _hw_axbs_mgpcr5_bitfields
mbed_official 146:f64d43ff0c18 976 {
mbed_official 146:f64d43ff0c18 977 uint32_t AULB : 3; //!< [2:0] Arbitrates On Undefined Length Bursts
mbed_official 146:f64d43ff0c18 978 uint32_t RESERVED0 : 29; //!< [31:3]
mbed_official 146:f64d43ff0c18 979 } B;
mbed_official 146:f64d43ff0c18 980 } hw_axbs_mgpcr5_t;
mbed_official 146:f64d43ff0c18 981 #endif
mbed_official 146:f64d43ff0c18 982
mbed_official 146:f64d43ff0c18 983 /*!
mbed_official 146:f64d43ff0c18 984 * @name Constants and macros for entire AXBS_MGPCR5 register
mbed_official 146:f64d43ff0c18 985 */
mbed_official 146:f64d43ff0c18 986 //@{
mbed_official 146:f64d43ff0c18 987 #define HW_AXBS_MGPCR5_ADDR (REGS_AXBS_BASE + 0xD00U)
mbed_official 146:f64d43ff0c18 988
mbed_official 146:f64d43ff0c18 989 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 990 #define HW_AXBS_MGPCR5 (*(__IO hw_axbs_mgpcr5_t *) HW_AXBS_MGPCR5_ADDR)
mbed_official 146:f64d43ff0c18 991 #define HW_AXBS_MGPCR5_RD() (HW_AXBS_MGPCR5.U)
mbed_official 146:f64d43ff0c18 992 #define HW_AXBS_MGPCR5_WR(v) (HW_AXBS_MGPCR5.U = (v))
mbed_official 146:f64d43ff0c18 993 #define HW_AXBS_MGPCR5_SET(v) (HW_AXBS_MGPCR5_WR(HW_AXBS_MGPCR5_RD() | (v)))
mbed_official 146:f64d43ff0c18 994 #define HW_AXBS_MGPCR5_CLR(v) (HW_AXBS_MGPCR5_WR(HW_AXBS_MGPCR5_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 995 #define HW_AXBS_MGPCR5_TOG(v) (HW_AXBS_MGPCR5_WR(HW_AXBS_MGPCR5_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 996 #endif
mbed_official 146:f64d43ff0c18 997 //@}
mbed_official 146:f64d43ff0c18 998
mbed_official 146:f64d43ff0c18 999 /*
mbed_official 146:f64d43ff0c18 1000 * Constants & macros for individual AXBS_MGPCR5 bitfields
mbed_official 146:f64d43ff0c18 1001 */
mbed_official 146:f64d43ff0c18 1002
mbed_official 146:f64d43ff0c18 1003 /*!
mbed_official 146:f64d43ff0c18 1004 * @name Register AXBS_MGPCR5, field AULB[2:0] (RW)
mbed_official 146:f64d43ff0c18 1005 *
mbed_official 146:f64d43ff0c18 1006 * Determines whether, and when, the crossbar switch arbitrates away the slave
mbed_official 146:f64d43ff0c18 1007 * port the master owns when the master is performing undefined length burst
mbed_official 146:f64d43ff0c18 1008 * accesses.
mbed_official 146:f64d43ff0c18 1009 *
mbed_official 146:f64d43ff0c18 1010 * Values:
mbed_official 146:f64d43ff0c18 1011 * - 000 - No arbitration is allowed during an undefined length burst
mbed_official 146:f64d43ff0c18 1012 * - 001 - Arbitration is allowed at any time during an undefined length burst
mbed_official 146:f64d43ff0c18 1013 * - 010 - Arbitration is allowed after four beats of an undefined length burst
mbed_official 146:f64d43ff0c18 1014 * - 011 - Arbitration is allowed after eight beats of an undefined length burst
mbed_official 146:f64d43ff0c18 1015 * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
mbed_official 146:f64d43ff0c18 1016 * - 101 - Reserved
mbed_official 146:f64d43ff0c18 1017 * - 110 - Reserved
mbed_official 146:f64d43ff0c18 1018 * - 111 - Reserved
mbed_official 146:f64d43ff0c18 1019 */
mbed_official 146:f64d43ff0c18 1020 //@{
mbed_official 146:f64d43ff0c18 1021 #define BP_AXBS_MGPCR5_AULB (0U) //!< Bit position for AXBS_MGPCR5_AULB.
mbed_official 146:f64d43ff0c18 1022 #define BM_AXBS_MGPCR5_AULB (0x00000007U) //!< Bit mask for AXBS_MGPCR5_AULB.
mbed_official 146:f64d43ff0c18 1023 #define BS_AXBS_MGPCR5_AULB (3U) //!< Bit field size in bits for AXBS_MGPCR5_AULB.
mbed_official 146:f64d43ff0c18 1024
mbed_official 146:f64d43ff0c18 1025 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1026 //! @brief Read current value of the AXBS_MGPCR5_AULB field.
mbed_official 146:f64d43ff0c18 1027 #define BR_AXBS_MGPCR5_AULB (HW_AXBS_MGPCR5.B.AULB)
mbed_official 146:f64d43ff0c18 1028 #endif
mbed_official 146:f64d43ff0c18 1029
mbed_official 146:f64d43ff0c18 1030 //! @brief Format value for bitfield AXBS_MGPCR5_AULB.
mbed_official 146:f64d43ff0c18 1031 #define BF_AXBS_MGPCR5_AULB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_MGPCR5_AULB), uint32_t) & BM_AXBS_MGPCR5_AULB)
mbed_official 146:f64d43ff0c18 1032
mbed_official 146:f64d43ff0c18 1033 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1034 //! @brief Set the AULB field to a new value.
mbed_official 146:f64d43ff0c18 1035 #define BW_AXBS_MGPCR5_AULB(v) (HW_AXBS_MGPCR5_WR((HW_AXBS_MGPCR5_RD() & ~BM_AXBS_MGPCR5_AULB) | BF_AXBS_MGPCR5_AULB(v)))
mbed_official 146:f64d43ff0c18 1036 #endif
mbed_official 146:f64d43ff0c18 1037 //@}
mbed_official 146:f64d43ff0c18 1038
mbed_official 146:f64d43ff0c18 1039 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1040 // hw_axbs_t - module struct
mbed_official 146:f64d43ff0c18 1041 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1042 /*!
mbed_official 146:f64d43ff0c18 1043 * @brief All AXBS module registers.
mbed_official 146:f64d43ff0c18 1044 */
mbed_official 146:f64d43ff0c18 1045 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1046 #pragma pack(1)
mbed_official 146:f64d43ff0c18 1047 typedef struct _hw_axbs
mbed_official 146:f64d43ff0c18 1048 {
mbed_official 146:f64d43ff0c18 1049 struct {
mbed_official 146:f64d43ff0c18 1050 __IO hw_axbs_prsn_t PRSn; //!< [0x0] Priority Registers Slave
mbed_official 146:f64d43ff0c18 1051 uint8_t _reserved0[12];
mbed_official 146:f64d43ff0c18 1052 __IO hw_axbs_crsn_t CRSn; //!< [0x10] Control Register
mbed_official 146:f64d43ff0c18 1053 uint8_t _reserved1[236];
mbed_official 146:f64d43ff0c18 1054 } SLAVE[5];
mbed_official 146:f64d43ff0c18 1055 uint8_t _reserved0[768];
mbed_official 146:f64d43ff0c18 1056 __IO hw_axbs_mgpcr0_t MGPCR0; //!< [0x800] Master General Purpose Control Register
mbed_official 146:f64d43ff0c18 1057 uint8_t _reserved1[252];
mbed_official 146:f64d43ff0c18 1058 __IO hw_axbs_mgpcr1_t MGPCR1; //!< [0x900] Master General Purpose Control Register
mbed_official 146:f64d43ff0c18 1059 uint8_t _reserved2[252];
mbed_official 146:f64d43ff0c18 1060 __IO hw_axbs_mgpcr2_t MGPCR2; //!< [0xA00] Master General Purpose Control Register
mbed_official 146:f64d43ff0c18 1061 uint8_t _reserved3[252];
mbed_official 146:f64d43ff0c18 1062 __IO hw_axbs_mgpcr3_t MGPCR3; //!< [0xB00] Master General Purpose Control Register
mbed_official 146:f64d43ff0c18 1063 uint8_t _reserved4[252];
mbed_official 146:f64d43ff0c18 1064 __IO hw_axbs_mgpcr4_t MGPCR4; //!< [0xC00] Master General Purpose Control Register
mbed_official 146:f64d43ff0c18 1065 uint8_t _reserved5[252];
mbed_official 146:f64d43ff0c18 1066 __IO hw_axbs_mgpcr5_t MGPCR5; //!< [0xD00] Master General Purpose Control Register
mbed_official 146:f64d43ff0c18 1067 } hw_axbs_t;
mbed_official 146:f64d43ff0c18 1068 #pragma pack()
mbed_official 146:f64d43ff0c18 1069
mbed_official 146:f64d43ff0c18 1070 //! @brief Macro to access all AXBS registers.
mbed_official 146:f64d43ff0c18 1071 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 146:f64d43ff0c18 1072 //! use the '&' operator, like <code>&HW_AXBS</code>.
mbed_official 146:f64d43ff0c18 1073 #define HW_AXBS (*(hw_axbs_t *) REGS_AXBS_BASE)
mbed_official 146:f64d43ff0c18 1074 #endif
mbed_official 146:f64d43ff0c18 1075
mbed_official 146:f64d43ff0c18 1076 #endif // __HW_AXBS_REGISTERS_H__
mbed_official 146:f64d43ff0c18 1077 // v22/130726/0.9
mbed_official 146:f64d43ff0c18 1078 // EOF