mbed official / mbed-src

mbed library sources

Dependents:   Encrypted my_mbed lklk CyaSSL_DTLS_Cellular ... more

Superseded

This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

Import librarymbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12.h@149:1fb5f62b92bd, 2014-04-03 (annotated)

Committer:
mbed_official
Date:
Thu Apr 03 11:45:06 2014 +0100
Revision:
149:1fb5f62b92bd
Parent:
targets/hal/TARGET_Freescale/TARGET_KSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12.h@146:f64d43ff0c18 
Synchronized with git revision 220c0bb39ceee40016e1e86350c058963d01ed42



Full URL: https://github.com/mbedmicro/mbed/commit/220c0bb39ceee40016e1e86350c058963d01ed42/

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /*
mbed_official 146:f64d43ff0c18 2 ** ###################################################################
mbed_official 146:f64d43ff0c18 3 ** Processor: MK64FN1M0VMD12
mbed_official 146:f64d43ff0c18 4 ** Compilers: ARM Compiler
mbed_official 146:f64d43ff0c18 5 ** Freescale C/C++ for Embedded ARM
mbed_official 146:f64d43ff0c18 6 ** GNU C Compiler
mbed_official 146:f64d43ff0c18 7 ** GNU C Compiler - CodeSourcery Sourcery G++
mbed_official 146:f64d43ff0c18 8 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 146:f64d43ff0c18 9 **
mbed_official 146:f64d43ff0c18 10 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
mbed_official 146:f64d43ff0c18 11 ** Version: rev. 2.3, 2014-01-24
mbed_official 146:f64d43ff0c18 12 **
mbed_official 146:f64d43ff0c18 13 ** Abstract:
mbed_official 146:f64d43ff0c18 14 ** CMSIS Peripheral Access Layer for MK64F12
mbed_official 146:f64d43ff0c18 15 **
mbed_official 146:f64d43ff0c18 16 ** Copyright: 1997 - 2014 Freescale, Inc. All Rights Reserved.
mbed_official 146:f64d43ff0c18 17 **
mbed_official 146:f64d43ff0c18 18 ** http: www.freescale.com
mbed_official 146:f64d43ff0c18 19 ** mail: support@freescale.com
mbed_official 146:f64d43ff0c18 20 **
mbed_official 146:f64d43ff0c18 21 ** Revisions:
mbed_official 146:f64d43ff0c18 22 ** - rev. 1.0 (2013-08-12)
mbed_official 146:f64d43ff0c18 23 ** Initial version.
mbed_official 146:f64d43ff0c18 24 ** - rev. 2.0 (2013-10-29)
mbed_official 146:f64d43ff0c18 25 ** Register accessor macros added to the memory map.
mbed_official 146:f64d43ff0c18 26 ** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official 146:f64d43ff0c18 27 ** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official 146:f64d43ff0c18 28 ** System initialization updated.
mbed_official 146:f64d43ff0c18 29 ** MCG - registers updated.
mbed_official 146:f64d43ff0c18 30 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
mbed_official 146:f64d43ff0c18 31 ** - rev. 2.1 (2013-10-29)
mbed_official 146:f64d43ff0c18 32 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official 146:f64d43ff0c18 33 ** - rev. 2.2 (2013-12-09)
mbed_official 146:f64d43ff0c18 34 ** DMA - EARS register removed.
mbed_official 146:f64d43ff0c18 35 ** AIPS0, AIPS1 - MPRA register updated.
mbed_official 146:f64d43ff0c18 36 ** - rev. 2.3 (2014-01-24)
mbed_official 146:f64d43ff0c18 37 ** Update according to reference manual rev. 2
mbed_official 146:f64d43ff0c18 38 ** ENET, MCG, MCM, SIM, USB - registers updated
mbed_official 146:f64d43ff0c18 39 **
mbed_official 146:f64d43ff0c18 40 ** ###################################################################
mbed_official 146:f64d43ff0c18 41 */
mbed_official 146:f64d43ff0c18 42
mbed_official 146:f64d43ff0c18 43 /*!
mbed_official 146:f64d43ff0c18 44 * @file MK64F12.h
mbed_official 146:f64d43ff0c18 45 * @version 2.3
mbed_official 146:f64d43ff0c18 46 * @date 2014-01-24
mbed_official 146:f64d43ff0c18 47 * @brief CMSIS Peripheral Access Layer for MK64F12
mbed_official 146:f64d43ff0c18 48 *
mbed_official 146:f64d43ff0c18 49 * CMSIS Peripheral Access Layer for MK64F12
mbed_official 146:f64d43ff0c18 50 */
mbed_official 146:f64d43ff0c18 51
mbed_official 146:f64d43ff0c18 52 #if !defined(MK64F12_H_)
mbed_official 146:f64d43ff0c18 53 #define MK64F12_H_ /**< Symbol preventing repeated inclusion */
mbed_official 146:f64d43ff0c18 54
mbed_official 146:f64d43ff0c18 55
mbed_official 146:f64d43ff0c18 56 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 57 -- MCU activation
mbed_official 146:f64d43ff0c18 58 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 59
mbed_official 146:f64d43ff0c18 60 /* Prevention from multiple including the same memory map */
mbed_official 146:f64d43ff0c18 61 #if !defined(MCU_MK64F12) /* Check if memory map has not been already included */
mbed_official 146:f64d43ff0c18 62 #define MCU_MK64F12
mbed_official 146:f64d43ff0c18 63
mbed_official 146:f64d43ff0c18 64 /* Check if another memory map has not been also included */
mbed_official 146:f64d43ff0c18 65 #if (defined(MCU_ACTIVE))
mbed_official 146:f64d43ff0c18 66 #error MK64F12 memory map: There is already included another memory map. Only one memory map can be included.
mbed_official 146:f64d43ff0c18 67 #endif /* (defined(MCU_ACTIVE)) */
mbed_official 146:f64d43ff0c18 68 #define MCU_ACTIVE
mbed_official 146:f64d43ff0c18 69
mbed_official 146:f64d43ff0c18 70 #include <stdint.h>
mbed_official 146:f64d43ff0c18 71
mbed_official 146:f64d43ff0c18 72 /** Memory map major version (memory maps with equal major version number are
mbed_official 146:f64d43ff0c18 73 * compatible) */
mbed_official 146:f64d43ff0c18 74 #define MCU_MEM_MAP_VERSION 0x0200u
mbed_official 146:f64d43ff0c18 75 /** Memory map minor version */
mbed_official 146:f64d43ff0c18 76 #define MCU_MEM_MAP_VERSION_MINOR 0x0003u
mbed_official 146:f64d43ff0c18 77
mbed_official 146:f64d43ff0c18 78 /**
mbed_official 146:f64d43ff0c18 79 * @brief Macro to calculate address of an aliased word in the peripheral
mbed_official 146:f64d43ff0c18 80 * bitband area for a peripheral register and bit (bit band region 0x40000000 to
mbed_official 146:f64d43ff0c18 81 * 0x400FFFFF).
mbed_official 146:f64d43ff0c18 82 * @param Reg Register to access.
mbed_official 146:f64d43ff0c18 83 * @param Bit Bit number to access.
mbed_official 146:f64d43ff0c18 84 * @return Address of the aliased word in the peripheral bitband area.
mbed_official 146:f64d43ff0c18 85 */
mbed_official 146:f64d43ff0c18 86 #define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
mbed_official 146:f64d43ff0c18 87 /**
mbed_official 146:f64d43ff0c18 88 * @brief Macro to access a single bit of a peripheral register (bit band region
mbed_official 146:f64d43ff0c18 89 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
mbed_official 146:f64d43ff0c18 90 * be used for peripherals with 32bit access allowed.
mbed_official 146:f64d43ff0c18 91 * @param Reg Register to access.
mbed_official 146:f64d43ff0c18 92 * @param Bit Bit number to access.
mbed_official 146:f64d43ff0c18 93 * @return Value of the targeted bit in the bit band region.
mbed_official 146:f64d43ff0c18 94 */
mbed_official 146:f64d43ff0c18 95 #define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
mbed_official 146:f64d43ff0c18 96 #define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit))
mbed_official 146:f64d43ff0c18 97 /**
mbed_official 146:f64d43ff0c18 98 * @brief Macro to access a single bit of a peripheral register (bit band region
mbed_official 146:f64d43ff0c18 99 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
mbed_official 146:f64d43ff0c18 100 * be used for peripherals with 16bit access allowed.
mbed_official 146:f64d43ff0c18 101 * @param Reg Register to access.
mbed_official 146:f64d43ff0c18 102 * @param Bit Bit number to access.
mbed_official 146:f64d43ff0c18 103 * @return Value of the targeted bit in the bit band region.
mbed_official 146:f64d43ff0c18 104 */
mbed_official 146:f64d43ff0c18 105 #define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
mbed_official 146:f64d43ff0c18 106 /**
mbed_official 146:f64d43ff0c18 107 * @brief Macro to access a single bit of a peripheral register (bit band region
mbed_official 146:f64d43ff0c18 108 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
mbed_official 146:f64d43ff0c18 109 * be used for peripherals with 8bit access allowed.
mbed_official 146:f64d43ff0c18 110 * @param Reg Register to access.
mbed_official 146:f64d43ff0c18 111 * @param Bit Bit number to access.
mbed_official 146:f64d43ff0c18 112 * @return Value of the targeted bit in the bit band region.
mbed_official 146:f64d43ff0c18 113 */
mbed_official 146:f64d43ff0c18 114 #define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
mbed_official 146:f64d43ff0c18 115
mbed_official 146:f64d43ff0c18 116 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 117 -- Interrupt vector numbers
mbed_official 146:f64d43ff0c18 118 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 119
mbed_official 146:f64d43ff0c18 120 /*!
mbed_official 146:f64d43ff0c18 121 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
mbed_official 146:f64d43ff0c18 122 * @{
mbed_official 146:f64d43ff0c18 123 */
mbed_official 146:f64d43ff0c18 124
mbed_official 146:f64d43ff0c18 125 /** Interrupt Number Definitions */
mbed_official 146:f64d43ff0c18 126 typedef enum IRQn {
mbed_official 146:f64d43ff0c18 127 /* Core interrupts */
mbed_official 146:f64d43ff0c18 128 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
mbed_official 146:f64d43ff0c18 129 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
mbed_official 146:f64d43ff0c18 130 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
mbed_official 146:f64d43ff0c18 131 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
mbed_official 146:f64d43ff0c18 132 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
mbed_official 146:f64d43ff0c18 133 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
mbed_official 146:f64d43ff0c18 134 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
mbed_official 146:f64d43ff0c18 135 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
mbed_official 146:f64d43ff0c18 136 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
mbed_official 146:f64d43ff0c18 137
mbed_official 146:f64d43ff0c18 138 /* Device specific interrupts */
mbed_official 146:f64d43ff0c18 139 DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */
mbed_official 146:f64d43ff0c18 140 DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */
mbed_official 146:f64d43ff0c18 141 DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */
mbed_official 146:f64d43ff0c18 142 DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */
mbed_official 146:f64d43ff0c18 143 DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */
mbed_official 146:f64d43ff0c18 144 DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */
mbed_official 146:f64d43ff0c18 145 DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */
mbed_official 146:f64d43ff0c18 146 DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */
mbed_official 146:f64d43ff0c18 147 DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */
mbed_official 146:f64d43ff0c18 148 DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */
mbed_official 146:f64d43ff0c18 149 DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */
mbed_official 146:f64d43ff0c18 150 DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */
mbed_official 146:f64d43ff0c18 151 DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */
mbed_official 146:f64d43ff0c18 152 DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */
mbed_official 146:f64d43ff0c18 153 DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */
mbed_official 146:f64d43ff0c18 154 DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */
mbed_official 146:f64d43ff0c18 155 DMA_Error_IRQn = 16, /**< DMA Error Interrupt */
mbed_official 146:f64d43ff0c18 156 MCM_IRQn = 17, /**< Normal Interrupt */
mbed_official 146:f64d43ff0c18 157 FTFE_IRQn = 18, /**< FTFE Command complete interrupt */
mbed_official 146:f64d43ff0c18 158 Read_Collision_IRQn = 19, /**< Read Collision Interrupt */
mbed_official 146:f64d43ff0c18 159 LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
mbed_official 146:f64d43ff0c18 160 LLW_IRQn = 21, /**< Low Leakage Wakeup */
mbed_official 146:f64d43ff0c18 161 Watchdog_IRQn = 22, /**< WDOG Interrupt */
mbed_official 146:f64d43ff0c18 162 RNG_IRQn = 23, /**< RNG Interrupt */
mbed_official 146:f64d43ff0c18 163 I2C0_IRQn = 24, /**< I2C0 interrupt */
mbed_official 146:f64d43ff0c18 164 I2C1_IRQn = 25, /**< I2C1 interrupt */
mbed_official 146:f64d43ff0c18 165 SPI0_IRQn = 26, /**< SPI0 Interrupt */
mbed_official 146:f64d43ff0c18 166 SPI1_IRQn = 27, /**< SPI1 Interrupt */
mbed_official 146:f64d43ff0c18 167 I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */
mbed_official 146:f64d43ff0c18 168 I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */
mbed_official 146:f64d43ff0c18 169 UART0_LON_IRQn = 30, /**< UART0 LON interrupt */
mbed_official 146:f64d43ff0c18 170 UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */
mbed_official 146:f64d43ff0c18 171 UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */
mbed_official 146:f64d43ff0c18 172 UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */
mbed_official 146:f64d43ff0c18 173 UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */
mbed_official 146:f64d43ff0c18 174 UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */
mbed_official 146:f64d43ff0c18 175 UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */
mbed_official 146:f64d43ff0c18 176 UART3_RX_TX_IRQn = 37, /**< UART3 Receive/Transmit interrupt */
mbed_official 146:f64d43ff0c18 177 UART3_ERR_IRQn = 38, /**< UART3 Error interrupt */
mbed_official 146:f64d43ff0c18 178 ADC0_IRQn = 39, /**< ADC0 interrupt */
mbed_official 146:f64d43ff0c18 179 CMP0_IRQn = 40, /**< CMP0 interrupt */
mbed_official 146:f64d43ff0c18 180 CMP1_IRQn = 41, /**< CMP1 interrupt */
mbed_official 146:f64d43ff0c18 181 FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */
mbed_official 146:f64d43ff0c18 182 FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */
mbed_official 146:f64d43ff0c18 183 FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */
mbed_official 146:f64d43ff0c18 184 CMT_IRQn = 45, /**< CMT interrupt */
mbed_official 146:f64d43ff0c18 185 RTC_IRQn = 46, /**< RTC interrupt */
mbed_official 146:f64d43ff0c18 186 RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */
mbed_official 146:f64d43ff0c18 187 PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */
mbed_official 146:f64d43ff0c18 188 PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */
mbed_official 146:f64d43ff0c18 189 PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */
mbed_official 146:f64d43ff0c18 190 PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */
mbed_official 146:f64d43ff0c18 191 PDB0_IRQn = 52, /**< PDB0 Interrupt */
mbed_official 146:f64d43ff0c18 192 USB0_IRQn = 53, /**< USB0 interrupt */
mbed_official 146:f64d43ff0c18 193 USBDCD_IRQn = 54, /**< USBDCD Interrupt */
mbed_official 146:f64d43ff0c18 194 Reserved71_IRQn = 55, /**< Reserved interrupt 71 */
mbed_official 146:f64d43ff0c18 195 DAC0_IRQn = 56, /**< DAC0 interrupt */
mbed_official 146:f64d43ff0c18 196 MCG_IRQn = 57, /**< MCG Interrupt */
mbed_official 146:f64d43ff0c18 197 LPTimer_IRQn = 58, /**< LPTimer interrupt */
mbed_official 146:f64d43ff0c18 198 PORTA_IRQn = 59, /**< Port A interrupt */
mbed_official 146:f64d43ff0c18 199 PORTB_IRQn = 60, /**< Port B interrupt */
mbed_official 146:f64d43ff0c18 200 PORTC_IRQn = 61, /**< Port C interrupt */
mbed_official 146:f64d43ff0c18 201 PORTD_IRQn = 62, /**< Port D interrupt */
mbed_official 146:f64d43ff0c18 202 PORTE_IRQn = 63, /**< Port E interrupt */
mbed_official 146:f64d43ff0c18 203 SWI_IRQn = 64, /**< Software interrupt */
mbed_official 146:f64d43ff0c18 204 SPI2_IRQn = 65, /**< SPI2 Interrupt */
mbed_official 146:f64d43ff0c18 205 UART4_RX_TX_IRQn = 66, /**< UART4 Receive/Transmit interrupt */
mbed_official 146:f64d43ff0c18 206 UART4_ERR_IRQn = 67, /**< UART4 Error interrupt */
mbed_official 146:f64d43ff0c18 207 UART5_RX_TX_IRQn = 68, /**< UART5 Receive/Transmit interrupt */
mbed_official 146:f64d43ff0c18 208 UART5_ERR_IRQn = 69, /**< UART5 Error interrupt */
mbed_official 146:f64d43ff0c18 209 CMP2_IRQn = 70, /**< CMP2 interrupt */
mbed_official 146:f64d43ff0c18 210 FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */
mbed_official 146:f64d43ff0c18 211 DAC1_IRQn = 72, /**< DAC1 interrupt */
mbed_official 146:f64d43ff0c18 212 ADC1_IRQn = 73, /**< ADC1 interrupt */
mbed_official 146:f64d43ff0c18 213 I2C2_IRQn = 74, /**< I2C2 interrupt */
mbed_official 146:f64d43ff0c18 214 CAN0_ORed_Message_buffer_IRQn = 75, /**< CAN0 OR'd message buffers interrupt */
mbed_official 146:f64d43ff0c18 215 CAN0_Bus_Off_IRQn = 76, /**< CAN0 bus off interrupt */
mbed_official 146:f64d43ff0c18 216 CAN0_Error_IRQn = 77, /**< CAN0 error interrupt */
mbed_official 146:f64d43ff0c18 217 CAN0_Tx_Warning_IRQn = 78, /**< CAN0 Tx warning interrupt */
mbed_official 146:f64d43ff0c18 218 CAN0_Rx_Warning_IRQn = 79, /**< CAN0 Rx warning interrupt */
mbed_official 146:f64d43ff0c18 219 CAN0_Wake_Up_IRQn = 80, /**< CAN0 wake up interrupt */
mbed_official 146:f64d43ff0c18 220 SDHC_IRQn = 81, /**< SDHC interrupt */
mbed_official 146:f64d43ff0c18 221 ENET_1588_Timer_IRQn = 82, /**< Ethernet MAC IEEE 1588 Timer Interrupt */
mbed_official 146:f64d43ff0c18 222 ENET_Transmit_IRQn = 83, /**< Ethernet MAC Transmit Interrupt */
mbed_official 146:f64d43ff0c18 223 ENET_Receive_IRQn = 84, /**< Ethernet MAC Receive Interrupt */
mbed_official 146:f64d43ff0c18 224 ENET_Error_IRQn = 85 /**< Ethernet MAC Error and miscelaneous Interrupt */
mbed_official 146:f64d43ff0c18 225 } IRQn_Type;
mbed_official 146:f64d43ff0c18 226
mbed_official 146:f64d43ff0c18 227 /*!
mbed_official 146:f64d43ff0c18 228 * @}
mbed_official 146:f64d43ff0c18 229 */ /* end of group Interrupt_vector_numbers */
mbed_official 146:f64d43ff0c18 230
mbed_official 146:f64d43ff0c18 231
mbed_official 146:f64d43ff0c18 232 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 233 -- Cortex M4 Core Configuration
mbed_official 146:f64d43ff0c18 234 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 235
mbed_official 146:f64d43ff0c18 236 /*!
mbed_official 146:f64d43ff0c18 237 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
mbed_official 146:f64d43ff0c18 238 * @{
mbed_official 146:f64d43ff0c18 239 */
mbed_official 146:f64d43ff0c18 240
mbed_official 146:f64d43ff0c18 241 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
mbed_official 146:f64d43ff0c18 242 #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
mbed_official 146:f64d43ff0c18 243 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
mbed_official 146:f64d43ff0c18 244 #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
mbed_official 146:f64d43ff0c18 245
mbed_official 146:f64d43ff0c18 246 #include "core_cm4.h" /* Core Peripheral Access Layer */
mbed_official 146:f64d43ff0c18 247 #include "system_MK64F12.h" /* Device specific configuration file */
mbed_official 146:f64d43ff0c18 248
mbed_official 146:f64d43ff0c18 249 /*!
mbed_official 146:f64d43ff0c18 250 * @}
mbed_official 146:f64d43ff0c18 251 */ /* end of group Cortex_Core_Configuration */
mbed_official 146:f64d43ff0c18 252
mbed_official 146:f64d43ff0c18 253
mbed_official 146:f64d43ff0c18 254 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 255 -- Device Peripheral Access Layer
mbed_official 146:f64d43ff0c18 256 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 257
mbed_official 146:f64d43ff0c18 258 /*!
mbed_official 146:f64d43ff0c18 259 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
mbed_official 146:f64d43ff0c18 260 * @{
mbed_official 146:f64d43ff0c18 261 */
mbed_official 146:f64d43ff0c18 262
mbed_official 146:f64d43ff0c18 263
mbed_official 146:f64d43ff0c18 264 /*
mbed_official 146:f64d43ff0c18 265 ** Start of section using anonymous unions
mbed_official 146:f64d43ff0c18 266 */
mbed_official 146:f64d43ff0c18 267
mbed_official 146:f64d43ff0c18 268 #if defined(__ARMCC_VERSION)
mbed_official 146:f64d43ff0c18 269 #pragma push
mbed_official 146:f64d43ff0c18 270 #pragma anon_unions
mbed_official 146:f64d43ff0c18 271 #elif defined(__CWCC__)
mbed_official 146:f64d43ff0c18 272 #pragma push
mbed_official 146:f64d43ff0c18 273 #pragma cpp_extensions on
mbed_official 146:f64d43ff0c18 274 #elif defined(__GNUC__)
mbed_official 146:f64d43ff0c18 275 /* anonymous unions are enabled by default */
mbed_official 146:f64d43ff0c18 276 #elif defined(__IAR_SYSTEMS_ICC__)
mbed_official 146:f64d43ff0c18 277 #pragma language=extended
mbed_official 146:f64d43ff0c18 278 #else
mbed_official 146:f64d43ff0c18 279 #error Not supported compiler type
mbed_official 146:f64d43ff0c18 280 #endif
mbed_official 146:f64d43ff0c18 281
mbed_official 146:f64d43ff0c18 282 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 283 -- ADC Peripheral Access Layer
mbed_official 146:f64d43ff0c18 284 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 285
mbed_official 146:f64d43ff0c18 286 /*!
mbed_official 146:f64d43ff0c18 287 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
mbed_official 146:f64d43ff0c18 288 * @{
mbed_official 146:f64d43ff0c18 289 */
mbed_official 146:f64d43ff0c18 290
mbed_official 146:f64d43ff0c18 291 /** ADC - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 292 typedef struct {
mbed_official 146:f64d43ff0c18 293 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
mbed_official 146:f64d43ff0c18 294 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
mbed_official 146:f64d43ff0c18 295 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
mbed_official 146:f64d43ff0c18 296 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
mbed_official 146:f64d43ff0c18 297 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
mbed_official 146:f64d43ff0c18 298 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
mbed_official 146:f64d43ff0c18 299 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
mbed_official 146:f64d43ff0c18 300 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
mbed_official 146:f64d43ff0c18 301 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
mbed_official 146:f64d43ff0c18 302 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
mbed_official 146:f64d43ff0c18 303 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
mbed_official 146:f64d43ff0c18 304 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
mbed_official 146:f64d43ff0c18 305 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
mbed_official 146:f64d43ff0c18 306 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
mbed_official 146:f64d43ff0c18 307 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
mbed_official 146:f64d43ff0c18 308 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
mbed_official 146:f64d43ff0c18 309 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
mbed_official 146:f64d43ff0c18 310 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
mbed_official 146:f64d43ff0c18 311 uint8_t RESERVED_0[4];
mbed_official 146:f64d43ff0c18 312 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
mbed_official 146:f64d43ff0c18 313 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
mbed_official 146:f64d43ff0c18 314 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
mbed_official 146:f64d43ff0c18 315 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
mbed_official 146:f64d43ff0c18 316 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
mbed_official 146:f64d43ff0c18 317 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
mbed_official 146:f64d43ff0c18 318 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
mbed_official 146:f64d43ff0c18 319 } ADC_Type, *ADC_MemMapPtr;
mbed_official 146:f64d43ff0c18 320
mbed_official 146:f64d43ff0c18 321 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 322 -- ADC - Register accessor macros
mbed_official 146:f64d43ff0c18 323 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 324
mbed_official 146:f64d43ff0c18 325 /*!
mbed_official 146:f64d43ff0c18 326 * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
mbed_official 146:f64d43ff0c18 327 * @{
mbed_official 146:f64d43ff0c18 328 */
mbed_official 146:f64d43ff0c18 329
mbed_official 146:f64d43ff0c18 330
mbed_official 146:f64d43ff0c18 331 /* ADC - Register accessors */
mbed_official 146:f64d43ff0c18 332 #define ADC_SC1_REG(base,index) ((base)->SC1[index])
mbed_official 146:f64d43ff0c18 333 #define ADC_CFG1_REG(base) ((base)->CFG1)
mbed_official 146:f64d43ff0c18 334 #define ADC_CFG2_REG(base) ((base)->CFG2)
mbed_official 146:f64d43ff0c18 335 #define ADC_R_REG(base,index) ((base)->R[index])
mbed_official 146:f64d43ff0c18 336 #define ADC_CV1_REG(base) ((base)->CV1)
mbed_official 146:f64d43ff0c18 337 #define ADC_CV2_REG(base) ((base)->CV2)
mbed_official 146:f64d43ff0c18 338 #define ADC_SC2_REG(base) ((base)->SC2)
mbed_official 146:f64d43ff0c18 339 #define ADC_SC3_REG(base) ((base)->SC3)
mbed_official 146:f64d43ff0c18 340 #define ADC_OFS_REG(base) ((base)->OFS)
mbed_official 146:f64d43ff0c18 341 #define ADC_PG_REG(base) ((base)->PG)
mbed_official 146:f64d43ff0c18 342 #define ADC_MG_REG(base) ((base)->MG)
mbed_official 146:f64d43ff0c18 343 #define ADC_CLPD_REG(base) ((base)->CLPD)
mbed_official 146:f64d43ff0c18 344 #define ADC_CLPS_REG(base) ((base)->CLPS)
mbed_official 146:f64d43ff0c18 345 #define ADC_CLP4_REG(base) ((base)->CLP4)
mbed_official 146:f64d43ff0c18 346 #define ADC_CLP3_REG(base) ((base)->CLP3)
mbed_official 146:f64d43ff0c18 347 #define ADC_CLP2_REG(base) ((base)->CLP2)
mbed_official 146:f64d43ff0c18 348 #define ADC_CLP1_REG(base) ((base)->CLP1)
mbed_official 146:f64d43ff0c18 349 #define ADC_CLP0_REG(base) ((base)->CLP0)
mbed_official 146:f64d43ff0c18 350 #define ADC_CLMD_REG(base) ((base)->CLMD)
mbed_official 146:f64d43ff0c18 351 #define ADC_CLMS_REG(base) ((base)->CLMS)
mbed_official 146:f64d43ff0c18 352 #define ADC_CLM4_REG(base) ((base)->CLM4)
mbed_official 146:f64d43ff0c18 353 #define ADC_CLM3_REG(base) ((base)->CLM3)
mbed_official 146:f64d43ff0c18 354 #define ADC_CLM2_REG(base) ((base)->CLM2)
mbed_official 146:f64d43ff0c18 355 #define ADC_CLM1_REG(base) ((base)->CLM1)
mbed_official 146:f64d43ff0c18 356 #define ADC_CLM0_REG(base) ((base)->CLM0)
mbed_official 146:f64d43ff0c18 357
mbed_official 146:f64d43ff0c18 358 /*!
mbed_official 146:f64d43ff0c18 359 * @}
mbed_official 146:f64d43ff0c18 360 */ /* end of group ADC_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 361
mbed_official 146:f64d43ff0c18 362
mbed_official 146:f64d43ff0c18 363 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 364 -- ADC Register Masks
mbed_official 146:f64d43ff0c18 365 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 366
mbed_official 146:f64d43ff0c18 367 /*!
mbed_official 146:f64d43ff0c18 368 * @addtogroup ADC_Register_Masks ADC Register Masks
mbed_official 146:f64d43ff0c18 369 * @{
mbed_official 146:f64d43ff0c18 370 */
mbed_official 146:f64d43ff0c18 371
mbed_official 146:f64d43ff0c18 372 /* SC1 Bit Fields */
mbed_official 146:f64d43ff0c18 373 #define ADC_SC1_ADCH_MASK 0x1Fu
mbed_official 146:f64d43ff0c18 374 #define ADC_SC1_ADCH_SHIFT 0
mbed_official 146:f64d43ff0c18 375 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
mbed_official 146:f64d43ff0c18 376 #define ADC_SC1_DIFF_MASK 0x20u
mbed_official 146:f64d43ff0c18 377 #define ADC_SC1_DIFF_SHIFT 5
mbed_official 146:f64d43ff0c18 378 #define ADC_SC1_AIEN_MASK 0x40u
mbed_official 146:f64d43ff0c18 379 #define ADC_SC1_AIEN_SHIFT 6
mbed_official 146:f64d43ff0c18 380 #define ADC_SC1_COCO_MASK 0x80u
mbed_official 146:f64d43ff0c18 381 #define ADC_SC1_COCO_SHIFT 7
mbed_official 146:f64d43ff0c18 382 /* CFG1 Bit Fields */
mbed_official 146:f64d43ff0c18 383 #define ADC_CFG1_ADICLK_MASK 0x3u
mbed_official 146:f64d43ff0c18 384 #define ADC_CFG1_ADICLK_SHIFT 0
mbed_official 146:f64d43ff0c18 385 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
mbed_official 146:f64d43ff0c18 386 #define ADC_CFG1_MODE_MASK 0xCu
mbed_official 146:f64d43ff0c18 387 #define ADC_CFG1_MODE_SHIFT 2
mbed_official 146:f64d43ff0c18 388 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
mbed_official 146:f64d43ff0c18 389 #define ADC_CFG1_ADLSMP_MASK 0x10u
mbed_official 146:f64d43ff0c18 390 #define ADC_CFG1_ADLSMP_SHIFT 4
mbed_official 146:f64d43ff0c18 391 #define ADC_CFG1_ADIV_MASK 0x60u
mbed_official 146:f64d43ff0c18 392 #define ADC_CFG1_ADIV_SHIFT 5
mbed_official 146:f64d43ff0c18 393 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
mbed_official 146:f64d43ff0c18 394 #define ADC_CFG1_ADLPC_MASK 0x80u
mbed_official 146:f64d43ff0c18 395 #define ADC_CFG1_ADLPC_SHIFT 7
mbed_official 146:f64d43ff0c18 396 /* CFG2 Bit Fields */
mbed_official 146:f64d43ff0c18 397 #define ADC_CFG2_ADLSTS_MASK 0x3u
mbed_official 146:f64d43ff0c18 398 #define ADC_CFG2_ADLSTS_SHIFT 0
mbed_official 146:f64d43ff0c18 399 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
mbed_official 146:f64d43ff0c18 400 #define ADC_CFG2_ADHSC_MASK 0x4u
mbed_official 146:f64d43ff0c18 401 #define ADC_CFG2_ADHSC_SHIFT 2
mbed_official 146:f64d43ff0c18 402 #define ADC_CFG2_ADACKEN_MASK 0x8u
mbed_official 146:f64d43ff0c18 403 #define ADC_CFG2_ADACKEN_SHIFT 3
mbed_official 146:f64d43ff0c18 404 #define ADC_CFG2_MUXSEL_MASK 0x10u
mbed_official 146:f64d43ff0c18 405 #define ADC_CFG2_MUXSEL_SHIFT 4
mbed_official 146:f64d43ff0c18 406 /* R Bit Fields */
mbed_official 146:f64d43ff0c18 407 #define ADC_R_D_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 408 #define ADC_R_D_SHIFT 0
mbed_official 146:f64d43ff0c18 409 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
mbed_official 146:f64d43ff0c18 410 /* CV1 Bit Fields */
mbed_official 146:f64d43ff0c18 411 #define ADC_CV1_CV_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 412 #define ADC_CV1_CV_SHIFT 0
mbed_official 146:f64d43ff0c18 413 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
mbed_official 146:f64d43ff0c18 414 /* CV2 Bit Fields */
mbed_official 146:f64d43ff0c18 415 #define ADC_CV2_CV_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 416 #define ADC_CV2_CV_SHIFT 0
mbed_official 146:f64d43ff0c18 417 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
mbed_official 146:f64d43ff0c18 418 /* SC2 Bit Fields */
mbed_official 146:f64d43ff0c18 419 #define ADC_SC2_REFSEL_MASK 0x3u
mbed_official 146:f64d43ff0c18 420 #define ADC_SC2_REFSEL_SHIFT 0
mbed_official 146:f64d43ff0c18 421 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
mbed_official 146:f64d43ff0c18 422 #define ADC_SC2_DMAEN_MASK 0x4u
mbed_official 146:f64d43ff0c18 423 #define ADC_SC2_DMAEN_SHIFT 2
mbed_official 146:f64d43ff0c18 424 #define ADC_SC2_ACREN_MASK 0x8u
mbed_official 146:f64d43ff0c18 425 #define ADC_SC2_ACREN_SHIFT 3
mbed_official 146:f64d43ff0c18 426 #define ADC_SC2_ACFGT_MASK 0x10u
mbed_official 146:f64d43ff0c18 427 #define ADC_SC2_ACFGT_SHIFT 4
mbed_official 146:f64d43ff0c18 428 #define ADC_SC2_ACFE_MASK 0x20u
mbed_official 146:f64d43ff0c18 429 #define ADC_SC2_ACFE_SHIFT 5
mbed_official 146:f64d43ff0c18 430 #define ADC_SC2_ADTRG_MASK 0x40u
mbed_official 146:f64d43ff0c18 431 #define ADC_SC2_ADTRG_SHIFT 6
mbed_official 146:f64d43ff0c18 432 #define ADC_SC2_ADACT_MASK 0x80u
mbed_official 146:f64d43ff0c18 433 #define ADC_SC2_ADACT_SHIFT 7
mbed_official 146:f64d43ff0c18 434 /* SC3 Bit Fields */
mbed_official 146:f64d43ff0c18 435 #define ADC_SC3_AVGS_MASK 0x3u
mbed_official 146:f64d43ff0c18 436 #define ADC_SC3_AVGS_SHIFT 0
mbed_official 146:f64d43ff0c18 437 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
mbed_official 146:f64d43ff0c18 438 #define ADC_SC3_AVGE_MASK 0x4u
mbed_official 146:f64d43ff0c18 439 #define ADC_SC3_AVGE_SHIFT 2
mbed_official 146:f64d43ff0c18 440 #define ADC_SC3_ADCO_MASK 0x8u
mbed_official 146:f64d43ff0c18 441 #define ADC_SC3_ADCO_SHIFT 3
mbed_official 146:f64d43ff0c18 442 #define ADC_SC3_CALF_MASK 0x40u
mbed_official 146:f64d43ff0c18 443 #define ADC_SC3_CALF_SHIFT 6
mbed_official 146:f64d43ff0c18 444 #define ADC_SC3_CAL_MASK 0x80u
mbed_official 146:f64d43ff0c18 445 #define ADC_SC3_CAL_SHIFT 7
mbed_official 146:f64d43ff0c18 446 /* OFS Bit Fields */
mbed_official 146:f64d43ff0c18 447 #define ADC_OFS_OFS_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 448 #define ADC_OFS_OFS_SHIFT 0
mbed_official 146:f64d43ff0c18 449 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
mbed_official 146:f64d43ff0c18 450 /* PG Bit Fields */
mbed_official 146:f64d43ff0c18 451 #define ADC_PG_PG_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 452 #define ADC_PG_PG_SHIFT 0
mbed_official 146:f64d43ff0c18 453 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
mbed_official 146:f64d43ff0c18 454 /* MG Bit Fields */
mbed_official 146:f64d43ff0c18 455 #define ADC_MG_MG_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 456 #define ADC_MG_MG_SHIFT 0
mbed_official 146:f64d43ff0c18 457 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
mbed_official 146:f64d43ff0c18 458 /* CLPD Bit Fields */
mbed_official 146:f64d43ff0c18 459 #define ADC_CLPD_CLPD_MASK 0x3Fu
mbed_official 146:f64d43ff0c18 460 #define ADC_CLPD_CLPD_SHIFT 0
mbed_official 146:f64d43ff0c18 461 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
mbed_official 146:f64d43ff0c18 462 /* CLPS Bit Fields */
mbed_official 146:f64d43ff0c18 463 #define ADC_CLPS_CLPS_MASK 0x3Fu
mbed_official 146:f64d43ff0c18 464 #define ADC_CLPS_CLPS_SHIFT 0
mbed_official 146:f64d43ff0c18 465 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
mbed_official 146:f64d43ff0c18 466 /* CLP4 Bit Fields */
mbed_official 146:f64d43ff0c18 467 #define ADC_CLP4_CLP4_MASK 0x3FFu
mbed_official 146:f64d43ff0c18 468 #define ADC_CLP4_CLP4_SHIFT 0
mbed_official 146:f64d43ff0c18 469 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
mbed_official 146:f64d43ff0c18 470 /* CLP3 Bit Fields */
mbed_official 146:f64d43ff0c18 471 #define ADC_CLP3_CLP3_MASK 0x1FFu
mbed_official 146:f64d43ff0c18 472 #define ADC_CLP3_CLP3_SHIFT 0
mbed_official 146:f64d43ff0c18 473 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
mbed_official 146:f64d43ff0c18 474 /* CLP2 Bit Fields */
mbed_official 146:f64d43ff0c18 475 #define ADC_CLP2_CLP2_MASK 0xFFu
mbed_official 146:f64d43ff0c18 476 #define ADC_CLP2_CLP2_SHIFT 0
mbed_official 146:f64d43ff0c18 477 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
mbed_official 146:f64d43ff0c18 478 /* CLP1 Bit Fields */
mbed_official 146:f64d43ff0c18 479 #define ADC_CLP1_CLP1_MASK 0x7Fu
mbed_official 146:f64d43ff0c18 480 #define ADC_CLP1_CLP1_SHIFT 0
mbed_official 146:f64d43ff0c18 481 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
mbed_official 146:f64d43ff0c18 482 /* CLP0 Bit Fields */
mbed_official 146:f64d43ff0c18 483 #define ADC_CLP0_CLP0_MASK 0x3Fu
mbed_official 146:f64d43ff0c18 484 #define ADC_CLP0_CLP0_SHIFT 0
mbed_official 146:f64d43ff0c18 485 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
mbed_official 146:f64d43ff0c18 486 /* CLMD Bit Fields */
mbed_official 146:f64d43ff0c18 487 #define ADC_CLMD_CLMD_MASK 0x3Fu
mbed_official 146:f64d43ff0c18 488 #define ADC_CLMD_CLMD_SHIFT 0
mbed_official 146:f64d43ff0c18 489 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
mbed_official 146:f64d43ff0c18 490 /* CLMS Bit Fields */
mbed_official 146:f64d43ff0c18 491 #define ADC_CLMS_CLMS_MASK 0x3Fu
mbed_official 146:f64d43ff0c18 492 #define ADC_CLMS_CLMS_SHIFT 0
mbed_official 146:f64d43ff0c18 493 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
mbed_official 146:f64d43ff0c18 494 /* CLM4 Bit Fields */
mbed_official 146:f64d43ff0c18 495 #define ADC_CLM4_CLM4_MASK 0x3FFu
mbed_official 146:f64d43ff0c18 496 #define ADC_CLM4_CLM4_SHIFT 0
mbed_official 146:f64d43ff0c18 497 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
mbed_official 146:f64d43ff0c18 498 /* CLM3 Bit Fields */
mbed_official 146:f64d43ff0c18 499 #define ADC_CLM3_CLM3_MASK 0x1FFu
mbed_official 146:f64d43ff0c18 500 #define ADC_CLM3_CLM3_SHIFT 0
mbed_official 146:f64d43ff0c18 501 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
mbed_official 146:f64d43ff0c18 502 /* CLM2 Bit Fields */
mbed_official 146:f64d43ff0c18 503 #define ADC_CLM2_CLM2_MASK 0xFFu
mbed_official 146:f64d43ff0c18 504 #define ADC_CLM2_CLM2_SHIFT 0
mbed_official 146:f64d43ff0c18 505 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
mbed_official 146:f64d43ff0c18 506 /* CLM1 Bit Fields */
mbed_official 146:f64d43ff0c18 507 #define ADC_CLM1_CLM1_MASK 0x7Fu
mbed_official 146:f64d43ff0c18 508 #define ADC_CLM1_CLM1_SHIFT 0
mbed_official 146:f64d43ff0c18 509 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
mbed_official 146:f64d43ff0c18 510 /* CLM0 Bit Fields */
mbed_official 146:f64d43ff0c18 511 #define ADC_CLM0_CLM0_MASK 0x3Fu
mbed_official 146:f64d43ff0c18 512 #define ADC_CLM0_CLM0_SHIFT 0
mbed_official 146:f64d43ff0c18 513 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
mbed_official 146:f64d43ff0c18 514
mbed_official 146:f64d43ff0c18 515 /*!
mbed_official 146:f64d43ff0c18 516 * @}
mbed_official 146:f64d43ff0c18 517 */ /* end of group ADC_Register_Masks */
mbed_official 146:f64d43ff0c18 518
mbed_official 146:f64d43ff0c18 519
mbed_official 146:f64d43ff0c18 520 /* ADC - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 521 /** Peripheral ADC0 base address */
mbed_official 146:f64d43ff0c18 522 #define ADC0_BASE (0x4003B000u)
mbed_official 146:f64d43ff0c18 523 /** Peripheral ADC0 base pointer */
mbed_official 146:f64d43ff0c18 524 #define ADC0 ((ADC_Type *)ADC0_BASE)
mbed_official 146:f64d43ff0c18 525 #define ADC0_BASE_PTR (ADC0)
mbed_official 146:f64d43ff0c18 526 /** Peripheral ADC1 base address */
mbed_official 146:f64d43ff0c18 527 #define ADC1_BASE (0x400BB000u)
mbed_official 146:f64d43ff0c18 528 /** Peripheral ADC1 base pointer */
mbed_official 146:f64d43ff0c18 529 #define ADC1 ((ADC_Type *)ADC1_BASE)
mbed_official 146:f64d43ff0c18 530 #define ADC1_BASE_PTR (ADC1)
mbed_official 146:f64d43ff0c18 531 /** Array initializer of ADC peripheral base pointers */
mbed_official 146:f64d43ff0c18 532 #define ADC_BASES { ADC0, ADC1 }
mbed_official 146:f64d43ff0c18 533
mbed_official 146:f64d43ff0c18 534 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 535 -- ADC - Register accessor macros
mbed_official 146:f64d43ff0c18 536 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 537
mbed_official 146:f64d43ff0c18 538 /*!
mbed_official 146:f64d43ff0c18 539 * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
mbed_official 146:f64d43ff0c18 540 * @{
mbed_official 146:f64d43ff0c18 541 */
mbed_official 146:f64d43ff0c18 542
mbed_official 146:f64d43ff0c18 543
mbed_official 146:f64d43ff0c18 544 /* ADC - Register instance definitions */
mbed_official 146:f64d43ff0c18 545 /* ADC0 */
mbed_official 146:f64d43ff0c18 546 #define ADC0_SC1A ADC_SC1_REG(ADC0,0)
mbed_official 146:f64d43ff0c18 547 #define ADC0_SC1B ADC_SC1_REG(ADC0,1)
mbed_official 146:f64d43ff0c18 548 #define ADC0_CFG1 ADC_CFG1_REG(ADC0)
mbed_official 146:f64d43ff0c18 549 #define ADC0_CFG2 ADC_CFG2_REG(ADC0)
mbed_official 146:f64d43ff0c18 550 #define ADC0_RA ADC_R_REG(ADC0,0)
mbed_official 146:f64d43ff0c18 551 #define ADC0_RB ADC_R_REG(ADC0,1)
mbed_official 146:f64d43ff0c18 552 #define ADC0_CV1 ADC_CV1_REG(ADC0)
mbed_official 146:f64d43ff0c18 553 #define ADC0_CV2 ADC_CV2_REG(ADC0)
mbed_official 146:f64d43ff0c18 554 #define ADC0_SC2 ADC_SC2_REG(ADC0)
mbed_official 146:f64d43ff0c18 555 #define ADC0_SC3 ADC_SC3_REG(ADC0)
mbed_official 146:f64d43ff0c18 556 #define ADC0_OFS ADC_OFS_REG(ADC0)
mbed_official 146:f64d43ff0c18 557 #define ADC0_PG ADC_PG_REG(ADC0)
mbed_official 146:f64d43ff0c18 558 #define ADC0_MG ADC_MG_REG(ADC0)
mbed_official 146:f64d43ff0c18 559 #define ADC0_CLPD ADC_CLPD_REG(ADC0)
mbed_official 146:f64d43ff0c18 560 #define ADC0_CLPS ADC_CLPS_REG(ADC0)
mbed_official 146:f64d43ff0c18 561 #define ADC0_CLP4 ADC_CLP4_REG(ADC0)
mbed_official 146:f64d43ff0c18 562 #define ADC0_CLP3 ADC_CLP3_REG(ADC0)
mbed_official 146:f64d43ff0c18 563 #define ADC0_CLP2 ADC_CLP2_REG(ADC0)
mbed_official 146:f64d43ff0c18 564 #define ADC0_CLP1 ADC_CLP1_REG(ADC0)
mbed_official 146:f64d43ff0c18 565 #define ADC0_CLP0 ADC_CLP0_REG(ADC0)
mbed_official 146:f64d43ff0c18 566 #define ADC0_CLMD ADC_CLMD_REG(ADC0)
mbed_official 146:f64d43ff0c18 567 #define ADC0_CLMS ADC_CLMS_REG(ADC0)
mbed_official 146:f64d43ff0c18 568 #define ADC0_CLM4 ADC_CLM4_REG(ADC0)
mbed_official 146:f64d43ff0c18 569 #define ADC0_CLM3 ADC_CLM3_REG(ADC0)
mbed_official 146:f64d43ff0c18 570 #define ADC0_CLM2 ADC_CLM2_REG(ADC0)
mbed_official 146:f64d43ff0c18 571 #define ADC0_CLM1 ADC_CLM1_REG(ADC0)
mbed_official 146:f64d43ff0c18 572 #define ADC0_CLM0 ADC_CLM0_REG(ADC0)
mbed_official 146:f64d43ff0c18 573 /* ADC1 */
mbed_official 146:f64d43ff0c18 574 #define ADC1_SC1A ADC_SC1_REG(ADC1,0)
mbed_official 146:f64d43ff0c18 575 #define ADC1_SC1B ADC_SC1_REG(ADC1,1)
mbed_official 146:f64d43ff0c18 576 #define ADC1_CFG1 ADC_CFG1_REG(ADC1)
mbed_official 146:f64d43ff0c18 577 #define ADC1_CFG2 ADC_CFG2_REG(ADC1)
mbed_official 146:f64d43ff0c18 578 #define ADC1_RA ADC_R_REG(ADC1,0)
mbed_official 146:f64d43ff0c18 579 #define ADC1_RB ADC_R_REG(ADC1,1)
mbed_official 146:f64d43ff0c18 580 #define ADC1_CV1 ADC_CV1_REG(ADC1)
mbed_official 146:f64d43ff0c18 581 #define ADC1_CV2 ADC_CV2_REG(ADC1)
mbed_official 146:f64d43ff0c18 582 #define ADC1_SC2 ADC_SC2_REG(ADC1)
mbed_official 146:f64d43ff0c18 583 #define ADC1_SC3 ADC_SC3_REG(ADC1)
mbed_official 146:f64d43ff0c18 584 #define ADC1_OFS ADC_OFS_REG(ADC1)
mbed_official 146:f64d43ff0c18 585 #define ADC1_PG ADC_PG_REG(ADC1)
mbed_official 146:f64d43ff0c18 586 #define ADC1_MG ADC_MG_REG(ADC1)
mbed_official 146:f64d43ff0c18 587 #define ADC1_CLPD ADC_CLPD_REG(ADC1)
mbed_official 146:f64d43ff0c18 588 #define ADC1_CLPS ADC_CLPS_REG(ADC1)
mbed_official 146:f64d43ff0c18 589 #define ADC1_CLP4 ADC_CLP4_REG(ADC1)
mbed_official 146:f64d43ff0c18 590 #define ADC1_CLP3 ADC_CLP3_REG(ADC1)
mbed_official 146:f64d43ff0c18 591 #define ADC1_CLP2 ADC_CLP2_REG(ADC1)
mbed_official 146:f64d43ff0c18 592 #define ADC1_CLP1 ADC_CLP1_REG(ADC1)
mbed_official 146:f64d43ff0c18 593 #define ADC1_CLP0 ADC_CLP0_REG(ADC1)
mbed_official 146:f64d43ff0c18 594 #define ADC1_CLMD ADC_CLMD_REG(ADC1)
mbed_official 146:f64d43ff0c18 595 #define ADC1_CLMS ADC_CLMS_REG(ADC1)
mbed_official 146:f64d43ff0c18 596 #define ADC1_CLM4 ADC_CLM4_REG(ADC1)
mbed_official 146:f64d43ff0c18 597 #define ADC1_CLM3 ADC_CLM3_REG(ADC1)
mbed_official 146:f64d43ff0c18 598 #define ADC1_CLM2 ADC_CLM2_REG(ADC1)
mbed_official 146:f64d43ff0c18 599 #define ADC1_CLM1 ADC_CLM1_REG(ADC1)
mbed_official 146:f64d43ff0c18 600 #define ADC1_CLM0 ADC_CLM0_REG(ADC1)
mbed_official 146:f64d43ff0c18 601
mbed_official 146:f64d43ff0c18 602 /* ADC - Register array accessors */
mbed_official 146:f64d43ff0c18 603 #define ADC0_SC1(index) ADC_SC1_REG(ADC0,index)
mbed_official 146:f64d43ff0c18 604 #define ADC1_SC1(index) ADC_SC1_REG(ADC1,index)
mbed_official 146:f64d43ff0c18 605 #define ADC0_R(index) ADC_R_REG(ADC0,index)
mbed_official 146:f64d43ff0c18 606 #define ADC1_R(index) ADC_R_REG(ADC1,index)
mbed_official 146:f64d43ff0c18 607
mbed_official 146:f64d43ff0c18 608 /*!
mbed_official 146:f64d43ff0c18 609 * @}
mbed_official 146:f64d43ff0c18 610 */ /* end of group ADC_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 611
mbed_official 146:f64d43ff0c18 612
mbed_official 146:f64d43ff0c18 613 /*!
mbed_official 146:f64d43ff0c18 614 * @}
mbed_official 146:f64d43ff0c18 615 */ /* end of group ADC_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 616
mbed_official 146:f64d43ff0c18 617
mbed_official 146:f64d43ff0c18 618 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 619 -- AIPS Peripheral Access Layer
mbed_official 146:f64d43ff0c18 620 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 621
mbed_official 146:f64d43ff0c18 622 /*!
mbed_official 146:f64d43ff0c18 623 * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
mbed_official 146:f64d43ff0c18 624 * @{
mbed_official 146:f64d43ff0c18 625 */
mbed_official 146:f64d43ff0c18 626
mbed_official 146:f64d43ff0c18 627 /** AIPS - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 628 typedef struct {
mbed_official 146:f64d43ff0c18 629 __IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */
mbed_official 146:f64d43ff0c18 630 uint8_t RESERVED_0[28];
mbed_official 146:f64d43ff0c18 631 __IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */
mbed_official 146:f64d43ff0c18 632 __IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */
mbed_official 146:f64d43ff0c18 633 __IO uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */
mbed_official 146:f64d43ff0c18 634 __IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */
mbed_official 146:f64d43ff0c18 635 uint8_t RESERVED_1[16];
mbed_official 146:f64d43ff0c18 636 __IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */
mbed_official 146:f64d43ff0c18 637 __IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */
mbed_official 146:f64d43ff0c18 638 __IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */
mbed_official 146:f64d43ff0c18 639 __IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */
mbed_official 146:f64d43ff0c18 640 __IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */
mbed_official 146:f64d43ff0c18 641 __IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */
mbed_official 146:f64d43ff0c18 642 __IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */
mbed_official 146:f64d43ff0c18 643 __IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */
mbed_official 146:f64d43ff0c18 644 __IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */
mbed_official 146:f64d43ff0c18 645 __IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */
mbed_official 146:f64d43ff0c18 646 __IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */
mbed_official 146:f64d43ff0c18 647 __IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */
mbed_official 146:f64d43ff0c18 648 uint8_t RESERVED_2[16];
mbed_official 146:f64d43ff0c18 649 __IO uint32_t PACRU; /**< Peripheral Access Control Register, offset: 0x80 */
mbed_official 146:f64d43ff0c18 650 } AIPS_Type, *AIPS_MemMapPtr;
mbed_official 146:f64d43ff0c18 651
mbed_official 146:f64d43ff0c18 652 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 653 -- AIPS - Register accessor macros
mbed_official 146:f64d43ff0c18 654 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 655
mbed_official 146:f64d43ff0c18 656 /*!
mbed_official 146:f64d43ff0c18 657 * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
mbed_official 146:f64d43ff0c18 658 * @{
mbed_official 146:f64d43ff0c18 659 */
mbed_official 146:f64d43ff0c18 660
mbed_official 146:f64d43ff0c18 661
mbed_official 146:f64d43ff0c18 662 /* AIPS - Register accessors */
mbed_official 146:f64d43ff0c18 663 #define AIPS_MPRA_REG(base) ((base)->MPRA)
mbed_official 146:f64d43ff0c18 664 #define AIPS_PACRA_REG(base) ((base)->PACRA)
mbed_official 146:f64d43ff0c18 665 #define AIPS_PACRB_REG(base) ((base)->PACRB)
mbed_official 146:f64d43ff0c18 666 #define AIPS_PACRC_REG(base) ((base)->PACRC)
mbed_official 146:f64d43ff0c18 667 #define AIPS_PACRD_REG(base) ((base)->PACRD)
mbed_official 146:f64d43ff0c18 668 #define AIPS_PACRE_REG(base) ((base)->PACRE)
mbed_official 146:f64d43ff0c18 669 #define AIPS_PACRF_REG(base) ((base)->PACRF)
mbed_official 146:f64d43ff0c18 670 #define AIPS_PACRG_REG(base) ((base)->PACRG)
mbed_official 146:f64d43ff0c18 671 #define AIPS_PACRH_REG(base) ((base)->PACRH)
mbed_official 146:f64d43ff0c18 672 #define AIPS_PACRI_REG(base) ((base)->PACRI)
mbed_official 146:f64d43ff0c18 673 #define AIPS_PACRJ_REG(base) ((base)->PACRJ)
mbed_official 146:f64d43ff0c18 674 #define AIPS_PACRK_REG(base) ((base)->PACRK)
mbed_official 146:f64d43ff0c18 675 #define AIPS_PACRL_REG(base) ((base)->PACRL)
mbed_official 146:f64d43ff0c18 676 #define AIPS_PACRM_REG(base) ((base)->PACRM)
mbed_official 146:f64d43ff0c18 677 #define AIPS_PACRN_REG(base) ((base)->PACRN)
mbed_official 146:f64d43ff0c18 678 #define AIPS_PACRO_REG(base) ((base)->PACRO)
mbed_official 146:f64d43ff0c18 679 #define AIPS_PACRP_REG(base) ((base)->PACRP)
mbed_official 146:f64d43ff0c18 680 #define AIPS_PACRU_REG(base) ((base)->PACRU)
mbed_official 146:f64d43ff0c18 681
mbed_official 146:f64d43ff0c18 682 /*!
mbed_official 146:f64d43ff0c18 683 * @}
mbed_official 146:f64d43ff0c18 684 */ /* end of group AIPS_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 685
mbed_official 146:f64d43ff0c18 686
mbed_official 146:f64d43ff0c18 687 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 688 -- AIPS Register Masks
mbed_official 146:f64d43ff0c18 689 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 690
mbed_official 146:f64d43ff0c18 691 /*!
mbed_official 146:f64d43ff0c18 692 * @addtogroup AIPS_Register_Masks AIPS Register Masks
mbed_official 146:f64d43ff0c18 693 * @{
mbed_official 146:f64d43ff0c18 694 */
mbed_official 146:f64d43ff0c18 695
mbed_official 146:f64d43ff0c18 696 /* MPRA Bit Fields */
mbed_official 146:f64d43ff0c18 697 #define AIPS_MPRA_MPL5_MASK 0x100u
mbed_official 146:f64d43ff0c18 698 #define AIPS_MPRA_MPL5_SHIFT 8
mbed_official 146:f64d43ff0c18 699 #define AIPS_MPRA_MTW5_MASK 0x200u
mbed_official 146:f64d43ff0c18 700 #define AIPS_MPRA_MTW5_SHIFT 9
mbed_official 146:f64d43ff0c18 701 #define AIPS_MPRA_MTR5_MASK 0x400u
mbed_official 146:f64d43ff0c18 702 #define AIPS_MPRA_MTR5_SHIFT 10
mbed_official 146:f64d43ff0c18 703 #define AIPS_MPRA_MPL4_MASK 0x1000u
mbed_official 146:f64d43ff0c18 704 #define AIPS_MPRA_MPL4_SHIFT 12
mbed_official 146:f64d43ff0c18 705 #define AIPS_MPRA_MTW4_MASK 0x2000u
mbed_official 146:f64d43ff0c18 706 #define AIPS_MPRA_MTW4_SHIFT 13
mbed_official 146:f64d43ff0c18 707 #define AIPS_MPRA_MTR4_MASK 0x4000u
mbed_official 146:f64d43ff0c18 708 #define AIPS_MPRA_MTR4_SHIFT 14
mbed_official 146:f64d43ff0c18 709 #define AIPS_MPRA_MPL3_MASK 0x10000u
mbed_official 146:f64d43ff0c18 710 #define AIPS_MPRA_MPL3_SHIFT 16
mbed_official 146:f64d43ff0c18 711 #define AIPS_MPRA_MTW3_MASK 0x20000u
mbed_official 146:f64d43ff0c18 712 #define AIPS_MPRA_MTW3_SHIFT 17
mbed_official 146:f64d43ff0c18 713 #define AIPS_MPRA_MTR3_MASK 0x40000u
mbed_official 146:f64d43ff0c18 714 #define AIPS_MPRA_MTR3_SHIFT 18
mbed_official 146:f64d43ff0c18 715 #define AIPS_MPRA_MPL2_MASK 0x100000u
mbed_official 146:f64d43ff0c18 716 #define AIPS_MPRA_MPL2_SHIFT 20
mbed_official 146:f64d43ff0c18 717 #define AIPS_MPRA_MTW2_MASK 0x200000u
mbed_official 146:f64d43ff0c18 718 #define AIPS_MPRA_MTW2_SHIFT 21
mbed_official 146:f64d43ff0c18 719 #define AIPS_MPRA_MTR2_MASK 0x400000u
mbed_official 146:f64d43ff0c18 720 #define AIPS_MPRA_MTR2_SHIFT 22
mbed_official 146:f64d43ff0c18 721 #define AIPS_MPRA_MPL1_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 722 #define AIPS_MPRA_MPL1_SHIFT 24
mbed_official 146:f64d43ff0c18 723 #define AIPS_MPRA_MTW1_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 724 #define AIPS_MPRA_MTW1_SHIFT 25
mbed_official 146:f64d43ff0c18 725 #define AIPS_MPRA_MTR1_MASK 0x4000000u
mbed_official 146:f64d43ff0c18 726 #define AIPS_MPRA_MTR1_SHIFT 26
mbed_official 146:f64d43ff0c18 727 #define AIPS_MPRA_MPL0_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 728 #define AIPS_MPRA_MPL0_SHIFT 28
mbed_official 146:f64d43ff0c18 729 #define AIPS_MPRA_MTW0_MASK 0x20000000u
mbed_official 146:f64d43ff0c18 730 #define AIPS_MPRA_MTW0_SHIFT 29
mbed_official 146:f64d43ff0c18 731 #define AIPS_MPRA_MTR0_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 732 #define AIPS_MPRA_MTR0_SHIFT 30
mbed_official 146:f64d43ff0c18 733 /* PACRA Bit Fields */
mbed_official 146:f64d43ff0c18 734 #define AIPS_PACRA_TP7_MASK 0x1u
mbed_official 146:f64d43ff0c18 735 #define AIPS_PACRA_TP7_SHIFT 0
mbed_official 146:f64d43ff0c18 736 #define AIPS_PACRA_WP7_MASK 0x2u
mbed_official 146:f64d43ff0c18 737 #define AIPS_PACRA_WP7_SHIFT 1
mbed_official 146:f64d43ff0c18 738 #define AIPS_PACRA_SP7_MASK 0x4u
mbed_official 146:f64d43ff0c18 739 #define AIPS_PACRA_SP7_SHIFT 2
mbed_official 146:f64d43ff0c18 740 #define AIPS_PACRA_TP6_MASK 0x10u
mbed_official 146:f64d43ff0c18 741 #define AIPS_PACRA_TP6_SHIFT 4
mbed_official 146:f64d43ff0c18 742 #define AIPS_PACRA_WP6_MASK 0x20u
mbed_official 146:f64d43ff0c18 743 #define AIPS_PACRA_WP6_SHIFT 5
mbed_official 146:f64d43ff0c18 744 #define AIPS_PACRA_SP6_MASK 0x40u
mbed_official 146:f64d43ff0c18 745 #define AIPS_PACRA_SP6_SHIFT 6
mbed_official 146:f64d43ff0c18 746 #define AIPS_PACRA_TP5_MASK 0x100u
mbed_official 146:f64d43ff0c18 747 #define AIPS_PACRA_TP5_SHIFT 8
mbed_official 146:f64d43ff0c18 748 #define AIPS_PACRA_WP5_MASK 0x200u
mbed_official 146:f64d43ff0c18 749 #define AIPS_PACRA_WP5_SHIFT 9
mbed_official 146:f64d43ff0c18 750 #define AIPS_PACRA_SP5_MASK 0x400u
mbed_official 146:f64d43ff0c18 751 #define AIPS_PACRA_SP5_SHIFT 10
mbed_official 146:f64d43ff0c18 752 #define AIPS_PACRA_TP4_MASK 0x1000u
mbed_official 146:f64d43ff0c18 753 #define AIPS_PACRA_TP4_SHIFT 12
mbed_official 146:f64d43ff0c18 754 #define AIPS_PACRA_WP4_MASK 0x2000u
mbed_official 146:f64d43ff0c18 755 #define AIPS_PACRA_WP4_SHIFT 13
mbed_official 146:f64d43ff0c18 756 #define AIPS_PACRA_SP4_MASK 0x4000u
mbed_official 146:f64d43ff0c18 757 #define AIPS_PACRA_SP4_SHIFT 14
mbed_official 146:f64d43ff0c18 758 #define AIPS_PACRA_TP3_MASK 0x10000u
mbed_official 146:f64d43ff0c18 759 #define AIPS_PACRA_TP3_SHIFT 16
mbed_official 146:f64d43ff0c18 760 #define AIPS_PACRA_WP3_MASK 0x20000u
mbed_official 146:f64d43ff0c18 761 #define AIPS_PACRA_WP3_SHIFT 17
mbed_official 146:f64d43ff0c18 762 #define AIPS_PACRA_SP3_MASK 0x40000u
mbed_official 146:f64d43ff0c18 763 #define AIPS_PACRA_SP3_SHIFT 18
mbed_official 146:f64d43ff0c18 764 #define AIPS_PACRA_TP2_MASK 0x100000u
mbed_official 146:f64d43ff0c18 765 #define AIPS_PACRA_TP2_SHIFT 20
mbed_official 146:f64d43ff0c18 766 #define AIPS_PACRA_WP2_MASK 0x200000u
mbed_official 146:f64d43ff0c18 767 #define AIPS_PACRA_WP2_SHIFT 21
mbed_official 146:f64d43ff0c18 768 #define AIPS_PACRA_SP2_MASK 0x400000u
mbed_official 146:f64d43ff0c18 769 #define AIPS_PACRA_SP2_SHIFT 22
mbed_official 146:f64d43ff0c18 770 #define AIPS_PACRA_TP1_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 771 #define AIPS_PACRA_TP1_SHIFT 24
mbed_official 146:f64d43ff0c18 772 #define AIPS_PACRA_WP1_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 773 #define AIPS_PACRA_WP1_SHIFT 25
mbed_official 146:f64d43ff0c18 774 #define AIPS_PACRA_SP1_MASK 0x4000000u
mbed_official 146:f64d43ff0c18 775 #define AIPS_PACRA_SP1_SHIFT 26
mbed_official 146:f64d43ff0c18 776 #define AIPS_PACRA_TP0_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 777 #define AIPS_PACRA_TP0_SHIFT 28
mbed_official 146:f64d43ff0c18 778 #define AIPS_PACRA_WP0_MASK 0x20000000u
mbed_official 146:f64d43ff0c18 779 #define AIPS_PACRA_WP0_SHIFT 29
mbed_official 146:f64d43ff0c18 780 #define AIPS_PACRA_SP0_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 781 #define AIPS_PACRA_SP0_SHIFT 30
mbed_official 146:f64d43ff0c18 782 /* PACRB Bit Fields */
mbed_official 146:f64d43ff0c18 783 #define AIPS_PACRB_TP7_MASK 0x1u
mbed_official 146:f64d43ff0c18 784 #define AIPS_PACRB_TP7_SHIFT 0
mbed_official 146:f64d43ff0c18 785 #define AIPS_PACRB_WP7_MASK 0x2u
mbed_official 146:f64d43ff0c18 786 #define AIPS_PACRB_WP7_SHIFT 1
mbed_official 146:f64d43ff0c18 787 #define AIPS_PACRB_SP7_MASK 0x4u
mbed_official 146:f64d43ff0c18 788 #define AIPS_PACRB_SP7_SHIFT 2
mbed_official 146:f64d43ff0c18 789 #define AIPS_PACRB_TP6_MASK 0x10u
mbed_official 146:f64d43ff0c18 790 #define AIPS_PACRB_TP6_SHIFT 4
mbed_official 146:f64d43ff0c18 791 #define AIPS_PACRB_WP6_MASK 0x20u
mbed_official 146:f64d43ff0c18 792 #define AIPS_PACRB_WP6_SHIFT 5
mbed_official 146:f64d43ff0c18 793 #define AIPS_PACRB_SP6_MASK 0x40u
mbed_official 146:f64d43ff0c18 794 #define AIPS_PACRB_SP6_SHIFT 6
mbed_official 146:f64d43ff0c18 795 #define AIPS_PACRB_TP5_MASK 0x100u
mbed_official 146:f64d43ff0c18 796 #define AIPS_PACRB_TP5_SHIFT 8
mbed_official 146:f64d43ff0c18 797 #define AIPS_PACRB_WP5_MASK 0x200u
mbed_official 146:f64d43ff0c18 798 #define AIPS_PACRB_WP5_SHIFT 9
mbed_official 146:f64d43ff0c18 799 #define AIPS_PACRB_SP5_MASK 0x400u
mbed_official 146:f64d43ff0c18 800 #define AIPS_PACRB_SP5_SHIFT 10
mbed_official 146:f64d43ff0c18 801 #define AIPS_PACRB_TP4_MASK 0x1000u
mbed_official 146:f64d43ff0c18 802 #define AIPS_PACRB_TP4_SHIFT 12
mbed_official 146:f64d43ff0c18 803 #define AIPS_PACRB_WP4_MASK 0x2000u
mbed_official 146:f64d43ff0c18 804 #define AIPS_PACRB_WP4_SHIFT 13
mbed_official 146:f64d43ff0c18 805 #define AIPS_PACRB_SP4_MASK 0x4000u
mbed_official 146:f64d43ff0c18 806 #define AIPS_PACRB_SP4_SHIFT 14
mbed_official 146:f64d43ff0c18 807 #define AIPS_PACRB_TP3_MASK 0x10000u
mbed_official 146:f64d43ff0c18 808 #define AIPS_PACRB_TP3_SHIFT 16
mbed_official 146:f64d43ff0c18 809 #define AIPS_PACRB_WP3_MASK 0x20000u
mbed_official 146:f64d43ff0c18 810 #define AIPS_PACRB_WP3_SHIFT 17
mbed_official 146:f64d43ff0c18 811 #define AIPS_PACRB_SP3_MASK 0x40000u
mbed_official 146:f64d43ff0c18 812 #define AIPS_PACRB_SP3_SHIFT 18
mbed_official 146:f64d43ff0c18 813 #define AIPS_PACRB_TP2_MASK 0x100000u
mbed_official 146:f64d43ff0c18 814 #define AIPS_PACRB_TP2_SHIFT 20
mbed_official 146:f64d43ff0c18 815 #define AIPS_PACRB_WP2_MASK 0x200000u
mbed_official 146:f64d43ff0c18 816 #define AIPS_PACRB_WP2_SHIFT 21
mbed_official 146:f64d43ff0c18 817 #define AIPS_PACRB_SP2_MASK 0x400000u
mbed_official 146:f64d43ff0c18 818 #define AIPS_PACRB_SP2_SHIFT 22
mbed_official 146:f64d43ff0c18 819 #define AIPS_PACRB_TP1_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 820 #define AIPS_PACRB_TP1_SHIFT 24
mbed_official 146:f64d43ff0c18 821 #define AIPS_PACRB_WP1_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 822 #define AIPS_PACRB_WP1_SHIFT 25
mbed_official 146:f64d43ff0c18 823 #define AIPS_PACRB_SP1_MASK 0x4000000u
mbed_official 146:f64d43ff0c18 824 #define AIPS_PACRB_SP1_SHIFT 26
mbed_official 146:f64d43ff0c18 825 #define AIPS_PACRB_TP0_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 826 #define AIPS_PACRB_TP0_SHIFT 28
mbed_official 146:f64d43ff0c18 827 #define AIPS_PACRB_WP0_MASK 0x20000000u
mbed_official 146:f64d43ff0c18 828 #define AIPS_PACRB_WP0_SHIFT 29
mbed_official 146:f64d43ff0c18 829 #define AIPS_PACRB_SP0_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 830 #define AIPS_PACRB_SP0_SHIFT 30
mbed_official 146:f64d43ff0c18 831 /* PACRC Bit Fields */
mbed_official 146:f64d43ff0c18 832 #define AIPS_PACRC_TP7_MASK 0x1u
mbed_official 146:f64d43ff0c18 833 #define AIPS_PACRC_TP7_SHIFT 0
mbed_official 146:f64d43ff0c18 834 #define AIPS_PACRC_WP7_MASK 0x2u
mbed_official 146:f64d43ff0c18 835 #define AIPS_PACRC_WP7_SHIFT 1
mbed_official 146:f64d43ff0c18 836 #define AIPS_PACRC_SP7_MASK 0x4u
mbed_official 146:f64d43ff0c18 837 #define AIPS_PACRC_SP7_SHIFT 2
mbed_official 146:f64d43ff0c18 838 #define AIPS_PACRC_TP6_MASK 0x10u
mbed_official 146:f64d43ff0c18 839 #define AIPS_PACRC_TP6_SHIFT 4
mbed_official 146:f64d43ff0c18 840 #define AIPS_PACRC_WP6_MASK 0x20u
mbed_official 146:f64d43ff0c18 841 #define AIPS_PACRC_WP6_SHIFT 5
mbed_official 146:f64d43ff0c18 842 #define AIPS_PACRC_SP6_MASK 0x40u
mbed_official 146:f64d43ff0c18 843 #define AIPS_PACRC_SP6_SHIFT 6
mbed_official 146:f64d43ff0c18 844 #define AIPS_PACRC_TP5_MASK 0x100u
mbed_official 146:f64d43ff0c18 845 #define AIPS_PACRC_TP5_SHIFT 8
mbed_official 146:f64d43ff0c18 846 #define AIPS_PACRC_WP5_MASK 0x200u
mbed_official 146:f64d43ff0c18 847 #define AIPS_PACRC_WP5_SHIFT 9
mbed_official 146:f64d43ff0c18 848 #define AIPS_PACRC_SP5_MASK 0x400u
mbed_official 146:f64d43ff0c18 849 #define AIPS_PACRC_SP5_SHIFT 10
mbed_official 146:f64d43ff0c18 850 #define AIPS_PACRC_TP4_MASK 0x1000u
mbed_official 146:f64d43ff0c18 851 #define AIPS_PACRC_TP4_SHIFT 12
mbed_official 146:f64d43ff0c18 852 #define AIPS_PACRC_WP4_MASK 0x2000u
mbed_official 146:f64d43ff0c18 853 #define AIPS_PACRC_WP4_SHIFT 13
mbed_official 146:f64d43ff0c18 854 #define AIPS_PACRC_SP4_MASK 0x4000u
mbed_official 146:f64d43ff0c18 855 #define AIPS_PACRC_SP4_SHIFT 14
mbed_official 146:f64d43ff0c18 856 #define AIPS_PACRC_TP3_MASK 0x10000u
mbed_official 146:f64d43ff0c18 857 #define AIPS_PACRC_TP3_SHIFT 16
mbed_official 146:f64d43ff0c18 858 #define AIPS_PACRC_WP3_MASK 0x20000u
mbed_official 146:f64d43ff0c18 859 #define AIPS_PACRC_WP3_SHIFT 17
mbed_official 146:f64d43ff0c18 860 #define AIPS_PACRC_SP3_MASK 0x40000u
mbed_official 146:f64d43ff0c18 861 #define AIPS_PACRC_SP3_SHIFT 18
mbed_official 146:f64d43ff0c18 862 #define AIPS_PACRC_TP2_MASK 0x100000u
mbed_official 146:f64d43ff0c18 863 #define AIPS_PACRC_TP2_SHIFT 20
mbed_official 146:f64d43ff0c18 864 #define AIPS_PACRC_WP2_MASK 0x200000u
mbed_official 146:f64d43ff0c18 865 #define AIPS_PACRC_WP2_SHIFT 21
mbed_official 146:f64d43ff0c18 866 #define AIPS_PACRC_SP2_MASK 0x400000u
mbed_official 146:f64d43ff0c18 867 #define AIPS_PACRC_SP2_SHIFT 22
mbed_official 146:f64d43ff0c18 868 #define AIPS_PACRC_TP1_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 869 #define AIPS_PACRC_TP1_SHIFT 24
mbed_official 146:f64d43ff0c18 870 #define AIPS_PACRC_WP1_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 871 #define AIPS_PACRC_WP1_SHIFT 25
mbed_official 146:f64d43ff0c18 872 #define AIPS_PACRC_SP1_MASK 0x4000000u
mbed_official 146:f64d43ff0c18 873 #define AIPS_PACRC_SP1_SHIFT 26
mbed_official 146:f64d43ff0c18 874 #define AIPS_PACRC_TP0_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 875 #define AIPS_PACRC_TP0_SHIFT 28
mbed_official 146:f64d43ff0c18 876 #define AIPS_PACRC_WP0_MASK 0x20000000u
mbed_official 146:f64d43ff0c18 877 #define AIPS_PACRC_WP0_SHIFT 29
mbed_official 146:f64d43ff0c18 878 #define AIPS_PACRC_SP0_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 879 #define AIPS_PACRC_SP0_SHIFT 30
mbed_official 146:f64d43ff0c18 880 /* PACRD Bit Fields */
mbed_official 146:f64d43ff0c18 881 #define AIPS_PACRD_TP7_MASK 0x1u
mbed_official 146:f64d43ff0c18 882 #define AIPS_PACRD_TP7_SHIFT 0
mbed_official 146:f64d43ff0c18 883 #define AIPS_PACRD_WP7_MASK 0x2u
mbed_official 146:f64d43ff0c18 884 #define AIPS_PACRD_WP7_SHIFT 1
mbed_official 146:f64d43ff0c18 885 #define AIPS_PACRD_SP7_MASK 0x4u
mbed_official 146:f64d43ff0c18 886 #define AIPS_PACRD_SP7_SHIFT 2
mbed_official 146:f64d43ff0c18 887 #define AIPS_PACRD_TP6_MASK 0x10u
mbed_official 146:f64d43ff0c18 888 #define AIPS_PACRD_TP6_SHIFT 4
mbed_official 146:f64d43ff0c18 889 #define AIPS_PACRD_WP6_MASK 0x20u
mbed_official 146:f64d43ff0c18 890 #define AIPS_PACRD_WP6_SHIFT 5
mbed_official 146:f64d43ff0c18 891 #define AIPS_PACRD_SP6_MASK 0x40u
mbed_official 146:f64d43ff0c18 892 #define AIPS_PACRD_SP6_SHIFT 6
mbed_official 146:f64d43ff0c18 893 #define AIPS_PACRD_TP5_MASK 0x100u
mbed_official 146:f64d43ff0c18 894 #define AIPS_PACRD_TP5_SHIFT 8
mbed_official 146:f64d43ff0c18 895 #define AIPS_PACRD_WP5_MASK 0x200u
mbed_official 146:f64d43ff0c18 896 #define AIPS_PACRD_WP5_SHIFT 9
mbed_official 146:f64d43ff0c18 897 #define AIPS_PACRD_SP5_MASK 0x400u
mbed_official 146:f64d43ff0c18 898 #define AIPS_PACRD_SP5_SHIFT 10
mbed_official 146:f64d43ff0c18 899 #define AIPS_PACRD_TP4_MASK 0x1000u
mbed_official 146:f64d43ff0c18 900 #define AIPS_PACRD_TP4_SHIFT 12
mbed_official 146:f64d43ff0c18 901 #define AIPS_PACRD_WP4_MASK 0x2000u
mbed_official 146:f64d43ff0c18 902 #define AIPS_PACRD_WP4_SHIFT 13
mbed_official 146:f64d43ff0c18 903 #define AIPS_PACRD_SP4_MASK 0x4000u
mbed_official 146:f64d43ff0c18 904 #define AIPS_PACRD_SP4_SHIFT 14
mbed_official 146:f64d43ff0c18 905 #define AIPS_PACRD_TP3_MASK 0x10000u
mbed_official 146:f64d43ff0c18 906 #define AIPS_PACRD_TP3_SHIFT 16
mbed_official 146:f64d43ff0c18 907 #define AIPS_PACRD_WP3_MASK 0x20000u
mbed_official 146:f64d43ff0c18 908 #define AIPS_PACRD_WP3_SHIFT 17
mbed_official 146:f64d43ff0c18 909 #define AIPS_PACRD_SP3_MASK 0x40000u
mbed_official 146:f64d43ff0c18 910 #define AIPS_PACRD_SP3_SHIFT 18
mbed_official 146:f64d43ff0c18 911 #define AIPS_PACRD_TP2_MASK 0x100000u
mbed_official 146:f64d43ff0c18 912 #define AIPS_PACRD_TP2_SHIFT 20
mbed_official 146:f64d43ff0c18 913 #define AIPS_PACRD_WP2_MASK 0x200000u
mbed_official 146:f64d43ff0c18 914 #define AIPS_PACRD_WP2_SHIFT 21
mbed_official 146:f64d43ff0c18 915 #define AIPS_PACRD_SP2_MASK 0x400000u
mbed_official 146:f64d43ff0c18 916 #define AIPS_PACRD_SP2_SHIFT 22
mbed_official 146:f64d43ff0c18 917 #define AIPS_PACRD_TP1_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 918 #define AIPS_PACRD_TP1_SHIFT 24
mbed_official 146:f64d43ff0c18 919 #define AIPS_PACRD_WP1_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 920 #define AIPS_PACRD_WP1_SHIFT 25
mbed_official 146:f64d43ff0c18 921 #define AIPS_PACRD_SP1_MASK 0x4000000u
mbed_official 146:f64d43ff0c18 922 #define AIPS_PACRD_SP1_SHIFT 26
mbed_official 146:f64d43ff0c18 923 #define AIPS_PACRD_TP0_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 924 #define AIPS_PACRD_TP0_SHIFT 28
mbed_official 146:f64d43ff0c18 925 #define AIPS_PACRD_WP0_MASK 0x20000000u
mbed_official 146:f64d43ff0c18 926 #define AIPS_PACRD_WP0_SHIFT 29
mbed_official 146:f64d43ff0c18 927 #define AIPS_PACRD_SP0_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 928 #define AIPS_PACRD_SP0_SHIFT 30
mbed_official 146:f64d43ff0c18 929 /* PACRE Bit Fields */
mbed_official 146:f64d43ff0c18 930 #define AIPS_PACRE_TP7_MASK 0x1u
mbed_official 146:f64d43ff0c18 931 #define AIPS_PACRE_TP7_SHIFT 0
mbed_official 146:f64d43ff0c18 932 #define AIPS_PACRE_WP7_MASK 0x2u
mbed_official 146:f64d43ff0c18 933 #define AIPS_PACRE_WP7_SHIFT 1
mbed_official 146:f64d43ff0c18 934 #define AIPS_PACRE_SP7_MASK 0x4u
mbed_official 146:f64d43ff0c18 935 #define AIPS_PACRE_SP7_SHIFT 2
mbed_official 146:f64d43ff0c18 936 #define AIPS_PACRE_TP6_MASK 0x10u
mbed_official 146:f64d43ff0c18 937 #define AIPS_PACRE_TP6_SHIFT 4
mbed_official 146:f64d43ff0c18 938 #define AIPS_PACRE_WP6_MASK 0x20u
mbed_official 146:f64d43ff0c18 939 #define AIPS_PACRE_WP6_SHIFT 5
mbed_official 146:f64d43ff0c18 940 #define AIPS_PACRE_SP6_MASK 0x40u
mbed_official 146:f64d43ff0c18 941 #define AIPS_PACRE_SP6_SHIFT 6
mbed_official 146:f64d43ff0c18 942 #define AIPS_PACRE_TP5_MASK 0x100u
mbed_official 146:f64d43ff0c18 943 #define AIPS_PACRE_TP5_SHIFT 8
mbed_official 146:f64d43ff0c18 944 #define AIPS_PACRE_WP5_MASK 0x200u
mbed_official 146:f64d43ff0c18 945 #define AIPS_PACRE_WP5_SHIFT 9
mbed_official 146:f64d43ff0c18 946 #define AIPS_PACRE_SP5_MASK 0x400u
mbed_official 146:f64d43ff0c18 947 #define AIPS_PACRE_SP5_SHIFT 10
mbed_official 146:f64d43ff0c18 948 #define AIPS_PACRE_TP4_MASK 0x1000u
mbed_official 146:f64d43ff0c18 949 #define AIPS_PACRE_TP4_SHIFT 12
mbed_official 146:f64d43ff0c18 950 #define AIPS_PACRE_WP4_MASK 0x2000u
mbed_official 146:f64d43ff0c18 951 #define AIPS_PACRE_WP4_SHIFT 13
mbed_official 146:f64d43ff0c18 952 #define AIPS_PACRE_SP4_MASK 0x4000u
mbed_official 146:f64d43ff0c18 953 #define AIPS_PACRE_SP4_SHIFT 14
mbed_official 146:f64d43ff0c18 954 #define AIPS_PACRE_TP3_MASK 0x10000u
mbed_official 146:f64d43ff0c18 955 #define AIPS_PACRE_TP3_SHIFT 16
mbed_official 146:f64d43ff0c18 956 #define AIPS_PACRE_WP3_MASK 0x20000u
mbed_official 146:f64d43ff0c18 957 #define AIPS_PACRE_WP3_SHIFT 17
mbed_official 146:f64d43ff0c18 958 #define AIPS_PACRE_SP3_MASK 0x40000u
mbed_official 146:f64d43ff0c18 959 #define AIPS_PACRE_SP3_SHIFT 18
mbed_official 146:f64d43ff0c18 960 #define AIPS_PACRE_TP2_MASK 0x100000u
mbed_official 146:f64d43ff0c18 961 #define AIPS_PACRE_TP2_SHIFT 20
mbed_official 146:f64d43ff0c18 962 #define AIPS_PACRE_WP2_MASK 0x200000u
mbed_official 146:f64d43ff0c18 963 #define AIPS_PACRE_WP2_SHIFT 21
mbed_official 146:f64d43ff0c18 964 #define AIPS_PACRE_SP2_MASK 0x400000u
mbed_official 146:f64d43ff0c18 965 #define AIPS_PACRE_SP2_SHIFT 22
mbed_official 146:f64d43ff0c18 966 #define AIPS_PACRE_TP1_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 967 #define AIPS_PACRE_TP1_SHIFT 24
mbed_official 146:f64d43ff0c18 968 #define AIPS_PACRE_WP1_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 969 #define AIPS_PACRE_WP1_SHIFT 25
mbed_official 146:f64d43ff0c18 970 #define AIPS_PACRE_SP1_MASK 0x4000000u
mbed_official 146:f64d43ff0c18 971 #define AIPS_PACRE_SP1_SHIFT 26
mbed_official 146:f64d43ff0c18 972 #define AIPS_PACRE_TP0_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 973 #define AIPS_PACRE_TP0_SHIFT 28
mbed_official 146:f64d43ff0c18 974 #define AIPS_PACRE_WP0_MASK 0x20000000u
mbed_official 146:f64d43ff0c18 975 #define AIPS_PACRE_WP0_SHIFT 29
mbed_official 146:f64d43ff0c18 976 #define AIPS_PACRE_SP0_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 977 #define AIPS_PACRE_SP0_SHIFT 30
mbed_official 146:f64d43ff0c18 978 /* PACRF Bit Fields */
mbed_official 146:f64d43ff0c18 979 #define AIPS_PACRF_TP7_MASK 0x1u
mbed_official 146:f64d43ff0c18 980 #define AIPS_PACRF_TP7_SHIFT 0
mbed_official 146:f64d43ff0c18 981 #define AIPS_PACRF_WP7_MASK 0x2u
mbed_official 146:f64d43ff0c18 982 #define AIPS_PACRF_WP7_SHIFT 1
mbed_official 146:f64d43ff0c18 983 #define AIPS_PACRF_SP7_MASK 0x4u
mbed_official 146:f64d43ff0c18 984 #define AIPS_PACRF_SP7_SHIFT 2
mbed_official 146:f64d43ff0c18 985 #define AIPS_PACRF_TP6_MASK 0x10u
mbed_official 146:f64d43ff0c18 986 #define AIPS_PACRF_TP6_SHIFT 4
mbed_official 146:f64d43ff0c18 987 #define AIPS_PACRF_WP6_MASK 0x20u
mbed_official 146:f64d43ff0c18 988 #define AIPS_PACRF_WP6_SHIFT 5
mbed_official 146:f64d43ff0c18 989 #define AIPS_PACRF_SP6_MASK 0x40u
mbed_official 146:f64d43ff0c18 990 #define AIPS_PACRF_SP6_SHIFT 6
mbed_official 146:f64d43ff0c18 991 #define AIPS_PACRF_TP5_MASK 0x100u
mbed_official 146:f64d43ff0c18 992 #define AIPS_PACRF_TP5_SHIFT 8
mbed_official 146:f64d43ff0c18 993 #define AIPS_PACRF_WP5_MASK 0x200u
mbed_official 146:f64d43ff0c18 994 #define AIPS_PACRF_WP5_SHIFT 9
mbed_official 146:f64d43ff0c18 995 #define AIPS_PACRF_SP5_MASK 0x400u
mbed_official 146:f64d43ff0c18 996 #define AIPS_PACRF_SP5_SHIFT 10
mbed_official 146:f64d43ff0c18 997 #define AIPS_PACRF_TP4_MASK 0x1000u
mbed_official 146:f64d43ff0c18 998 #define AIPS_PACRF_TP4_SHIFT 12
mbed_official 146:f64d43ff0c18 999 #define AIPS_PACRF_WP4_MASK 0x2000u
mbed_official 146:f64d43ff0c18 1000 #define AIPS_PACRF_WP4_SHIFT 13
mbed_official 146:f64d43ff0c18 1001 #define AIPS_PACRF_SP4_MASK 0x4000u
mbed_official 146:f64d43ff0c18 1002 #define AIPS_PACRF_SP4_SHIFT 14
mbed_official 146:f64d43ff0c18 1003 #define AIPS_PACRF_TP3_MASK 0x10000u
mbed_official 146:f64d43ff0c18 1004 #define AIPS_PACRF_TP3_SHIFT 16
mbed_official 146:f64d43ff0c18 1005 #define AIPS_PACRF_WP3_MASK 0x20000u
mbed_official 146:f64d43ff0c18 1006 #define AIPS_PACRF_WP3_SHIFT 17
mbed_official 146:f64d43ff0c18 1007 #define AIPS_PACRF_SP3_MASK 0x40000u
mbed_official 146:f64d43ff0c18 1008 #define AIPS_PACRF_SP3_SHIFT 18
mbed_official 146:f64d43ff0c18 1009 #define AIPS_PACRF_TP2_MASK 0x100000u
mbed_official 146:f64d43ff0c18 1010 #define AIPS_PACRF_TP2_SHIFT 20
mbed_official 146:f64d43ff0c18 1011 #define AIPS_PACRF_WP2_MASK 0x200000u
mbed_official 146:f64d43ff0c18 1012 #define AIPS_PACRF_WP2_SHIFT 21
mbed_official 146:f64d43ff0c18 1013 #define AIPS_PACRF_SP2_MASK 0x400000u
mbed_official 146:f64d43ff0c18 1014 #define AIPS_PACRF_SP2_SHIFT 22
mbed_official 146:f64d43ff0c18 1015 #define AIPS_PACRF_TP1_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 1016 #define AIPS_PACRF_TP1_SHIFT 24
mbed_official 146:f64d43ff0c18 1017 #define AIPS_PACRF_WP1_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 1018 #define AIPS_PACRF_WP1_SHIFT 25
mbed_official 146:f64d43ff0c18 1019 #define AIPS_PACRF_SP1_MASK 0x4000000u
mbed_official 146:f64d43ff0c18 1020 #define AIPS_PACRF_SP1_SHIFT 26
mbed_official 146:f64d43ff0c18 1021 #define AIPS_PACRF_TP0_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 1022 #define AIPS_PACRF_TP0_SHIFT 28
mbed_official 146:f64d43ff0c18 1023 #define AIPS_PACRF_WP0_MASK 0x20000000u
mbed_official 146:f64d43ff0c18 1024 #define AIPS_PACRF_WP0_SHIFT 29
mbed_official 146:f64d43ff0c18 1025 #define AIPS_PACRF_SP0_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 1026 #define AIPS_PACRF_SP0_SHIFT 30
mbed_official 146:f64d43ff0c18 1027 /* PACRG Bit Fields */
mbed_official 146:f64d43ff0c18 1028 #define AIPS_PACRG_TP7_MASK 0x1u
mbed_official 146:f64d43ff0c18 1029 #define AIPS_PACRG_TP7_SHIFT 0
mbed_official 146:f64d43ff0c18 1030 #define AIPS_PACRG_WP7_MASK 0x2u
mbed_official 146:f64d43ff0c18 1031 #define AIPS_PACRG_WP7_SHIFT 1
mbed_official 146:f64d43ff0c18 1032 #define AIPS_PACRG_SP7_MASK 0x4u
mbed_official 146:f64d43ff0c18 1033 #define AIPS_PACRG_SP7_SHIFT 2
mbed_official 146:f64d43ff0c18 1034 #define AIPS_PACRG_TP6_MASK 0x10u
mbed_official 146:f64d43ff0c18 1035 #define AIPS_PACRG_TP6_SHIFT 4
mbed_official 146:f64d43ff0c18 1036 #define AIPS_PACRG_WP6_MASK 0x20u
mbed_official 146:f64d43ff0c18 1037 #define AIPS_PACRG_WP6_SHIFT 5
mbed_official 146:f64d43ff0c18 1038 #define AIPS_PACRG_SP6_MASK 0x40u
mbed_official 146:f64d43ff0c18 1039 #define AIPS_PACRG_SP6_SHIFT 6
mbed_official 146:f64d43ff0c18 1040 #define AIPS_PACRG_TP5_MASK 0x100u
mbed_official 146:f64d43ff0c18 1041 #define AIPS_PACRG_TP5_SHIFT 8
mbed_official 146:f64d43ff0c18 1042 #define AIPS_PACRG_WP5_MASK 0x200u
mbed_official 146:f64d43ff0c18 1043 #define AIPS_PACRG_WP5_SHIFT 9
mbed_official 146:f64d43ff0c18 1044 #define AIPS_PACRG_SP5_MASK 0x400u
mbed_official 146:f64d43ff0c18 1045 #define AIPS_PACRG_SP5_SHIFT 10
mbed_official 146:f64d43ff0c18 1046 #define AIPS_PACRG_TP4_MASK 0x1000u
mbed_official 146:f64d43ff0c18 1047 #define AIPS_PACRG_TP4_SHIFT 12
mbed_official 146:f64d43ff0c18 1048 #define AIPS_PACRG_WP4_MASK 0x2000u
mbed_official 146:f64d43ff0c18 1049 #define AIPS_PACRG_WP4_SHIFT 13
mbed_official 146:f64d43ff0c18 1050 #define AIPS_PACRG_SP4_MASK 0x4000u
mbed_official 146:f64d43ff0c18 1051 #define AIPS_PACRG_SP4_SHIFT 14
mbed_official 146:f64d43ff0c18 1052 #define AIPS_PACRG_TP3_MASK 0x10000u
mbed_official 146:f64d43ff0c18 1053 #define AIPS_PACRG_TP3_SHIFT 16
mbed_official 146:f64d43ff0c18 1054 #define AIPS_PACRG_WP3_MASK 0x20000u
mbed_official 146:f64d43ff0c18 1055 #define AIPS_PACRG_WP3_SHIFT 17
mbed_official 146:f64d43ff0c18 1056 #define AIPS_PACRG_SP3_MASK 0x40000u
mbed_official 146:f64d43ff0c18 1057 #define AIPS_PACRG_SP3_SHIFT 18
mbed_official 146:f64d43ff0c18 1058 #define AIPS_PACRG_TP2_MASK 0x100000u
mbed_official 146:f64d43ff0c18 1059 #define AIPS_PACRG_TP2_SHIFT 20
mbed_official 146:f64d43ff0c18 1060 #define AIPS_PACRG_WP2_MASK 0x200000u
mbed_official 146:f64d43ff0c18 1061 #define AIPS_PACRG_WP2_SHIFT 21
mbed_official 146:f64d43ff0c18 1062 #define AIPS_PACRG_SP2_MASK 0x400000u
mbed_official 146:f64d43ff0c18 1063 #define AIPS_PACRG_SP2_SHIFT 22
mbed_official 146:f64d43ff0c18 1064 #define AIPS_PACRG_TP1_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 1065 #define AIPS_PACRG_TP1_SHIFT 24
mbed_official 146:f64d43ff0c18 1066 #define AIPS_PACRG_WP1_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 1067 #define AIPS_PACRG_WP1_SHIFT 25
mbed_official 146:f64d43ff0c18 1068 #define AIPS_PACRG_SP1_MASK 0x4000000u
mbed_official 146:f64d43ff0c18 1069 #define AIPS_PACRG_SP1_SHIFT 26
mbed_official 146:f64d43ff0c18 1070 #define AIPS_PACRG_TP0_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 1071 #define AIPS_PACRG_TP0_SHIFT 28
mbed_official 146:f64d43ff0c18 1072 #define AIPS_PACRG_WP0_MASK 0x20000000u
mbed_official 146:f64d43ff0c18 1073 #define AIPS_PACRG_WP0_SHIFT 29
mbed_official 146:f64d43ff0c18 1074 #define AIPS_PACRG_SP0_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 1075 #define AIPS_PACRG_SP0_SHIFT 30
mbed_official 146:f64d43ff0c18 1076 /* PACRH Bit Fields */
mbed_official 146:f64d43ff0c18 1077 #define AIPS_PACRH_TP7_MASK 0x1u
mbed_official 146:f64d43ff0c18 1078 #define AIPS_PACRH_TP7_SHIFT 0
mbed_official 146:f64d43ff0c18 1079 #define AIPS_PACRH_WP7_MASK 0x2u
mbed_official 146:f64d43ff0c18 1080 #define AIPS_PACRH_WP7_SHIFT 1
mbed_official 146:f64d43ff0c18 1081 #define AIPS_PACRH_SP7_MASK 0x4u
mbed_official 146:f64d43ff0c18 1082 #define AIPS_PACRH_SP7_SHIFT 2
mbed_official 146:f64d43ff0c18 1083 #define AIPS_PACRH_TP6_MASK 0x10u
mbed_official 146:f64d43ff0c18 1084 #define AIPS_PACRH_TP6_SHIFT 4
mbed_official 146:f64d43ff0c18 1085 #define AIPS_PACRH_WP6_MASK 0x20u
mbed_official 146:f64d43ff0c18 1086 #define AIPS_PACRH_WP6_SHIFT 5
mbed_official 146:f64d43ff0c18 1087 #define AIPS_PACRH_SP6_MASK 0x40u
mbed_official 146:f64d43ff0c18 1088 #define AIPS_PACRH_SP6_SHIFT 6
mbed_official 146:f64d43ff0c18 1089 #define AIPS_PACRH_TP5_MASK 0x100u
mbed_official 146:f64d43ff0c18 1090 #define AIPS_PACRH_TP5_SHIFT 8
mbed_official 146:f64d43ff0c18 1091 #define AIPS_PACRH_WP5_MASK 0x200u
mbed_official 146:f64d43ff0c18 1092 #define AIPS_PACRH_WP5_SHIFT 9
mbed_official 146:f64d43ff0c18 1093 #define AIPS_PACRH_SP5_MASK 0x400u
mbed_official 146:f64d43ff0c18 1094 #define AIPS_PACRH_SP5_SHIFT 10
mbed_official 146:f64d43ff0c18 1095 #define AIPS_PACRH_TP4_MASK 0x1000u
mbed_official 146:f64d43ff0c18 1096 #define AIPS_PACRH_TP4_SHIFT 12
mbed_official 146:f64d43ff0c18 1097 #define AIPS_PACRH_WP4_MASK 0x2000u
mbed_official 146:f64d43ff0c18 1098 #define AIPS_PACRH_WP4_SHIFT 13
mbed_official 146:f64d43ff0c18 1099 #define AIPS_PACRH_SP4_MASK 0x4000u
mbed_official 146:f64d43ff0c18 1100 #define AIPS_PACRH_SP4_SHIFT 14
mbed_official 146:f64d43ff0c18 1101 #define AIPS_PACRH_TP3_MASK 0x10000u
mbed_official 146:f64d43ff0c18 1102 #define AIPS_PACRH_TP3_SHIFT 16
mbed_official 146:f64d43ff0c18 1103 #define AIPS_PACRH_WP3_MASK 0x20000u
mbed_official 146:f64d43ff0c18 1104 #define AIPS_PACRH_WP3_SHIFT 17
mbed_official 146:f64d43ff0c18 1105 #define AIPS_PACRH_SP3_MASK 0x40000u
mbed_official 146:f64d43ff0c18 1106 #define AIPS_PACRH_SP3_SHIFT 18
mbed_official 146:f64d43ff0c18 1107 #define AIPS_PACRH_TP2_MASK 0x100000u
mbed_official 146:f64d43ff0c18 1108 #define AIPS_PACRH_TP2_SHIFT 20
mbed_official 146:f64d43ff0c18 1109 #define AIPS_PACRH_WP2_MASK 0x200000u
mbed_official 146:f64d43ff0c18 1110 #define AIPS_PACRH_WP2_SHIFT 21
mbed_official 146:f64d43ff0c18 1111 #define AIPS_PACRH_SP2_MASK 0x400000u
mbed_official 146:f64d43ff0c18 1112 #define AIPS_PACRH_SP2_SHIFT 22
mbed_official 146:f64d43ff0c18 1113 #define AIPS_PACRH_TP1_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 1114 #define AIPS_PACRH_TP1_SHIFT 24
mbed_official 146:f64d43ff0c18 1115 #define AIPS_PACRH_WP1_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 1116 #define AIPS_PACRH_WP1_SHIFT 25
mbed_official 146:f64d43ff0c18 1117 #define AIPS_PACRH_SP1_MASK 0x4000000u
mbed_official 146:f64d43ff0c18 1118 #define AIPS_PACRH_SP1_SHIFT 26
mbed_official 146:f64d43ff0c18 1119 #define AIPS_PACRH_TP0_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 1120 #define AIPS_PACRH_TP0_SHIFT 28
mbed_official 146:f64d43ff0c18 1121 #define AIPS_PACRH_WP0_MASK 0x20000000u
mbed_official 146:f64d43ff0c18 1122 #define AIPS_PACRH_WP0_SHIFT 29
mbed_official 146:f64d43ff0c18 1123 #define AIPS_PACRH_SP0_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 1124 #define AIPS_PACRH_SP0_SHIFT 30
mbed_official 146:f64d43ff0c18 1125 /* PACRI Bit Fields */
mbed_official 146:f64d43ff0c18 1126 #define AIPS_PACRI_TP7_MASK 0x1u
mbed_official 146:f64d43ff0c18 1127 #define AIPS_PACRI_TP7_SHIFT 0
mbed_official 146:f64d43ff0c18 1128 #define AIPS_PACRI_WP7_MASK 0x2u
mbed_official 146:f64d43ff0c18 1129 #define AIPS_PACRI_WP7_SHIFT 1
mbed_official 146:f64d43ff0c18 1130 #define AIPS_PACRI_SP7_MASK 0x4u
mbed_official 146:f64d43ff0c18 1131 #define AIPS_PACRI_SP7_SHIFT 2
mbed_official 146:f64d43ff0c18 1132 #define AIPS_PACRI_TP6_MASK 0x10u
mbed_official 146:f64d43ff0c18 1133 #define AIPS_PACRI_TP6_SHIFT 4
mbed_official 146:f64d43ff0c18 1134 #define AIPS_PACRI_WP6_MASK 0x20u
mbed_official 146:f64d43ff0c18 1135 #define AIPS_PACRI_WP6_SHIFT 5
mbed_official 146:f64d43ff0c18 1136 #define AIPS_PACRI_SP6_MASK 0x40u
mbed_official 146:f64d43ff0c18 1137 #define AIPS_PACRI_SP6_SHIFT 6
mbed_official 146:f64d43ff0c18 1138 #define AIPS_PACRI_TP5_MASK 0x100u
mbed_official 146:f64d43ff0c18 1139 #define AIPS_PACRI_TP5_SHIFT 8
mbed_official 146:f64d43ff0c18 1140 #define AIPS_PACRI_WP5_MASK 0x200u
mbed_official 146:f64d43ff0c18 1141 #define AIPS_PACRI_WP5_SHIFT 9
mbed_official 146:f64d43ff0c18 1142 #define AIPS_PACRI_SP5_MASK 0x400u
mbed_official 146:f64d43ff0c18 1143 #define AIPS_PACRI_SP5_SHIFT 10
mbed_official 146:f64d43ff0c18 1144 #define AIPS_PACRI_TP4_MASK 0x1000u
mbed_official 146:f64d43ff0c18 1145 #define AIPS_PACRI_TP4_SHIFT 12
mbed_official 146:f64d43ff0c18 1146 #define AIPS_PACRI_WP4_MASK 0x2000u
mbed_official 146:f64d43ff0c18 1147 #define AIPS_PACRI_WP4_SHIFT 13
mbed_official 146:f64d43ff0c18 1148 #define AIPS_PACRI_SP4_MASK 0x4000u
mbed_official 146:f64d43ff0c18 1149 #define AIPS_PACRI_SP4_SHIFT 14
mbed_official 146:f64d43ff0c18 1150 #define AIPS_PACRI_TP3_MASK 0x10000u
mbed_official 146:f64d43ff0c18 1151 #define AIPS_PACRI_TP3_SHIFT 16
mbed_official 146:f64d43ff0c18 1152 #define AIPS_PACRI_WP3_MASK 0x20000u
mbed_official 146:f64d43ff0c18 1153 #define AIPS_PACRI_WP3_SHIFT 17
mbed_official 146:f64d43ff0c18 1154 #define AIPS_PACRI_SP3_MASK 0x40000u
mbed_official 146:f64d43ff0c18 1155 #define AIPS_PACRI_SP3_SHIFT 18
mbed_official 146:f64d43ff0c18 1156 #define AIPS_PACRI_TP2_MASK 0x100000u
mbed_official 146:f64d43ff0c18 1157 #define AIPS_PACRI_TP2_SHIFT 20
mbed_official 146:f64d43ff0c18 1158 #define AIPS_PACRI_WP2_MASK 0x200000u
mbed_official 146:f64d43ff0c18 1159 #define AIPS_PACRI_WP2_SHIFT 21
mbed_official 146:f64d43ff0c18 1160 #define AIPS_PACRI_SP2_MASK 0x400000u
mbed_official 146:f64d43ff0c18 1161 #define AIPS_PACRI_SP2_SHIFT 22
mbed_official 146:f64d43ff0c18 1162 #define AIPS_PACRI_TP1_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 1163 #define AIPS_PACRI_TP1_SHIFT 24
mbed_official 146:f64d43ff0c18 1164 #define AIPS_PACRI_WP1_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 1165 #define AIPS_PACRI_WP1_SHIFT 25
mbed_official 146:f64d43ff0c18 1166 #define AIPS_PACRI_SP1_MASK 0x4000000u
mbed_official 146:f64d43ff0c18 1167 #define AIPS_PACRI_SP1_SHIFT 26
mbed_official 146:f64d43ff0c18 1168 #define AIPS_PACRI_TP0_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 1169 #define AIPS_PACRI_TP0_SHIFT 28
mbed_official 146:f64d43ff0c18 1170 #define AIPS_PACRI_WP0_MASK 0x20000000u
mbed_official 146:f64d43ff0c18 1171 #define AIPS_PACRI_WP0_SHIFT 29
mbed_official 146:f64d43ff0c18 1172 #define AIPS_PACRI_SP0_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 1173 #define AIPS_PACRI_SP0_SHIFT 30
mbed_official 146:f64d43ff0c18 1174 /* PACRJ Bit Fields */
mbed_official 146:f64d43ff0c18 1175 #define AIPS_PACRJ_TP7_MASK 0x1u
mbed_official 146:f64d43ff0c18 1176 #define AIPS_PACRJ_TP7_SHIFT 0
mbed_official 146:f64d43ff0c18 1177 #define AIPS_PACRJ_WP7_MASK 0x2u
mbed_official 146:f64d43ff0c18 1178 #define AIPS_PACRJ_WP7_SHIFT 1
mbed_official 146:f64d43ff0c18 1179 #define AIPS_PACRJ_SP7_MASK 0x4u
mbed_official 146:f64d43ff0c18 1180 #define AIPS_PACRJ_SP7_SHIFT 2
mbed_official 146:f64d43ff0c18 1181 #define AIPS_PACRJ_TP6_MASK 0x10u
mbed_official 146:f64d43ff0c18 1182 #define AIPS_PACRJ_TP6_SHIFT 4
mbed_official 146:f64d43ff0c18 1183 #define AIPS_PACRJ_WP6_MASK 0x20u
mbed_official 146:f64d43ff0c18 1184 #define AIPS_PACRJ_WP6_SHIFT 5
mbed_official 146:f64d43ff0c18 1185 #define AIPS_PACRJ_SP6_MASK 0x40u
mbed_official 146:f64d43ff0c18 1186 #define AIPS_PACRJ_SP6_SHIFT 6
mbed_official 146:f64d43ff0c18 1187 #define AIPS_PACRJ_TP5_MASK 0x100u
mbed_official 146:f64d43ff0c18 1188 #define AIPS_PACRJ_TP5_SHIFT 8
mbed_official 146:f64d43ff0c18 1189 #define AIPS_PACRJ_WP5_MASK 0x200u
mbed_official 146:f64d43ff0c18 1190 #define AIPS_PACRJ_WP5_SHIFT 9
mbed_official 146:f64d43ff0c18 1191 #define AIPS_PACRJ_SP5_MASK 0x400u
mbed_official 146:f64d43ff0c18 1192 #define AIPS_PACRJ_SP5_SHIFT 10
mbed_official 146:f64d43ff0c18 1193 #define AIPS_PACRJ_TP4_MASK 0x1000u
mbed_official 146:f64d43ff0c18 1194 #define AIPS_PACRJ_TP4_SHIFT 12
mbed_official 146:f64d43ff0c18 1195 #define AIPS_PACRJ_WP4_MASK 0x2000u
mbed_official 146:f64d43ff0c18 1196 #define AIPS_PACRJ_WP4_SHIFT 13
mbed_official 146:f64d43ff0c18 1197 #define AIPS_PACRJ_SP4_MASK 0x4000u
mbed_official 146:f64d43ff0c18 1198 #define AIPS_PACRJ_SP4_SHIFT 14
mbed_official 146:f64d43ff0c18 1199 #define AIPS_PACRJ_TP3_MASK 0x10000u
mbed_official 146:f64d43ff0c18 1200 #define AIPS_PACRJ_TP3_SHIFT 16
mbed_official 146:f64d43ff0c18 1201 #define AIPS_PACRJ_WP3_MASK 0x20000u
mbed_official 146:f64d43ff0c18 1202 #define AIPS_PACRJ_WP3_SHIFT 17
mbed_official 146:f64d43ff0c18 1203 #define AIPS_PACRJ_SP3_MASK 0x40000u
mbed_official 146:f64d43ff0c18 1204 #define AIPS_PACRJ_SP3_SHIFT 18
mbed_official 146:f64d43ff0c18 1205 #define AIPS_PACRJ_TP2_MASK 0x100000u
mbed_official 146:f64d43ff0c18 1206 #define AIPS_PACRJ_TP2_SHIFT 20
mbed_official 146:f64d43ff0c18 1207 #define AIPS_PACRJ_WP2_MASK 0x200000u
mbed_official 146:f64d43ff0c18 1208 #define AIPS_PACRJ_WP2_SHIFT 21
mbed_official 146:f64d43ff0c18 1209 #define AIPS_PACRJ_SP2_MASK 0x400000u
mbed_official 146:f64d43ff0c18 1210 #define AIPS_PACRJ_SP2_SHIFT 22
mbed_official 146:f64d43ff0c18 1211 #define AIPS_PACRJ_TP1_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 1212 #define AIPS_PACRJ_TP1_SHIFT 24
mbed_official 146:f64d43ff0c18 1213 #define AIPS_PACRJ_WP1_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 1214 #define AIPS_PACRJ_WP1_SHIFT 25
mbed_official 146:f64d43ff0c18 1215 #define AIPS_PACRJ_SP1_MASK 0x4000000u
mbed_official 146:f64d43ff0c18 1216 #define AIPS_PACRJ_SP1_SHIFT 26
mbed_official 146:f64d43ff0c18 1217 #define AIPS_PACRJ_TP0_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 1218 #define AIPS_PACRJ_TP0_SHIFT 28
mbed_official 146:f64d43ff0c18 1219 #define AIPS_PACRJ_WP0_MASK 0x20000000u
mbed_official 146:f64d43ff0c18 1220 #define AIPS_PACRJ_WP0_SHIFT 29
mbed_official 146:f64d43ff0c18 1221 #define AIPS_PACRJ_SP0_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 1222 #define AIPS_PACRJ_SP0_SHIFT 30
mbed_official 146:f64d43ff0c18 1223 /* PACRK Bit Fields */
mbed_official 146:f64d43ff0c18 1224 #define AIPS_PACRK_TP7_MASK 0x1u
mbed_official 146:f64d43ff0c18 1225 #define AIPS_PACRK_TP7_SHIFT 0
mbed_official 146:f64d43ff0c18 1226 #define AIPS_PACRK_WP7_MASK 0x2u
mbed_official 146:f64d43ff0c18 1227 #define AIPS_PACRK_WP7_SHIFT 1
mbed_official 146:f64d43ff0c18 1228 #define AIPS_PACRK_SP7_MASK 0x4u
mbed_official 146:f64d43ff0c18 1229 #define AIPS_PACRK_SP7_SHIFT 2
mbed_official 146:f64d43ff0c18 1230 #define AIPS_PACRK_TP6_MASK 0x10u
mbed_official 146:f64d43ff0c18 1231 #define AIPS_PACRK_TP6_SHIFT 4
mbed_official 146:f64d43ff0c18 1232 #define AIPS_PACRK_WP6_MASK 0x20u
mbed_official 146:f64d43ff0c18 1233 #define AIPS_PACRK_WP6_SHIFT 5
mbed_official 146:f64d43ff0c18 1234 #define AIPS_PACRK_SP6_MASK 0x40u
mbed_official 146:f64d43ff0c18 1235 #define AIPS_PACRK_SP6_SHIFT 6
mbed_official 146:f64d43ff0c18 1236 #define AIPS_PACRK_TP5_MASK 0x100u
mbed_official 146:f64d43ff0c18 1237 #define AIPS_PACRK_TP5_SHIFT 8
mbed_official 146:f64d43ff0c18 1238 #define AIPS_PACRK_WP5_MASK 0x200u
mbed_official 146:f64d43ff0c18 1239 #define AIPS_PACRK_WP5_SHIFT 9
mbed_official 146:f64d43ff0c18 1240 #define AIPS_PACRK_SP5_MASK 0x400u
mbed_official 146:f64d43ff0c18 1241 #define AIPS_PACRK_SP5_SHIFT 10
mbed_official 146:f64d43ff0c18 1242 #define AIPS_PACRK_TP4_MASK 0x1000u
mbed_official 146:f64d43ff0c18 1243 #define AIPS_PACRK_TP4_SHIFT 12
mbed_official 146:f64d43ff0c18 1244 #define AIPS_PACRK_WP4_MASK 0x2000u
mbed_official 146:f64d43ff0c18 1245 #define AIPS_PACRK_WP4_SHIFT 13
mbed_official 146:f64d43ff0c18 1246 #define AIPS_PACRK_SP4_MASK 0x4000u
mbed_official 146:f64d43ff0c18 1247 #define AIPS_PACRK_SP4_SHIFT 14
mbed_official 146:f64d43ff0c18 1248 #define AIPS_PACRK_TP3_MASK 0x10000u
mbed_official 146:f64d43ff0c18 1249 #define AIPS_PACRK_TP3_SHIFT 16
mbed_official 146:f64d43ff0c18 1250 #define AIPS_PACRK_WP3_MASK 0x20000u
mbed_official 146:f64d43ff0c18 1251 #define AIPS_PACRK_WP3_SHIFT 17
mbed_official 146:f64d43ff0c18 1252 #define AIPS_PACRK_SP3_MASK 0x40000u
mbed_official 146:f64d43ff0c18 1253 #define AIPS_PACRK_SP3_SHIFT 18
mbed_official 146:f64d43ff0c18 1254 #define AIPS_PACRK_TP2_MASK 0x100000u
mbed_official 146:f64d43ff0c18 1255 #define AIPS_PACRK_TP2_SHIFT 20
mbed_official 146:f64d43ff0c18 1256 #define AIPS_PACRK_WP2_MASK 0x200000u
mbed_official 146:f64d43ff0c18 1257 #define AIPS_PACRK_WP2_SHIFT 21
mbed_official 146:f64d43ff0c18 1258 #define AIPS_PACRK_SP2_MASK 0x400000u
mbed_official 146:f64d43ff0c18 1259 #define AIPS_PACRK_SP2_SHIFT 22
mbed_official 146:f64d43ff0c18 1260 #define AIPS_PACRK_TP1_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 1261 #define AIPS_PACRK_TP1_SHIFT 24
mbed_official 146:f64d43ff0c18 1262 #define AIPS_PACRK_WP1_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 1263 #define AIPS_PACRK_WP1_SHIFT 25
mbed_official 146:f64d43ff0c18 1264 #define AIPS_PACRK_SP1_MASK 0x4000000u
mbed_official 146:f64d43ff0c18 1265 #define AIPS_PACRK_SP1_SHIFT 26
mbed_official 146:f64d43ff0c18 1266 #define AIPS_PACRK_TP0_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 1267 #define AIPS_PACRK_TP0_SHIFT 28
mbed_official 146:f64d43ff0c18 1268 #define AIPS_PACRK_WP0_MASK 0x20000000u
mbed_official 146:f64d43ff0c18 1269 #define AIPS_PACRK_WP0_SHIFT 29
mbed_official 146:f64d43ff0c18 1270 #define AIPS_PACRK_SP0_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 1271 #define AIPS_PACRK_SP0_SHIFT 30
mbed_official 146:f64d43ff0c18 1272 /* PACRL Bit Fields */
mbed_official 146:f64d43ff0c18 1273 #define AIPS_PACRL_TP7_MASK 0x1u
mbed_official 146:f64d43ff0c18 1274 #define AIPS_PACRL_TP7_SHIFT 0
mbed_official 146:f64d43ff0c18 1275 #define AIPS_PACRL_WP7_MASK 0x2u
mbed_official 146:f64d43ff0c18 1276 #define AIPS_PACRL_WP7_SHIFT 1
mbed_official 146:f64d43ff0c18 1277 #define AIPS_PACRL_SP7_MASK 0x4u
mbed_official 146:f64d43ff0c18 1278 #define AIPS_PACRL_SP7_SHIFT 2
mbed_official 146:f64d43ff0c18 1279 #define AIPS_PACRL_TP6_MASK 0x10u
mbed_official 146:f64d43ff0c18 1280 #define AIPS_PACRL_TP6_SHIFT 4
mbed_official 146:f64d43ff0c18 1281 #define AIPS_PACRL_WP6_MASK 0x20u
mbed_official 146:f64d43ff0c18 1282 #define AIPS_PACRL_WP6_SHIFT 5
mbed_official 146:f64d43ff0c18 1283 #define AIPS_PACRL_SP6_MASK 0x40u
mbed_official 146:f64d43ff0c18 1284 #define AIPS_PACRL_SP6_SHIFT 6
mbed_official 146:f64d43ff0c18 1285 #define AIPS_PACRL_TP5_MASK 0x100u
mbed_official 146:f64d43ff0c18 1286 #define AIPS_PACRL_TP5_SHIFT 8
mbed_official 146:f64d43ff0c18 1287 #define AIPS_PACRL_WP5_MASK 0x200u
mbed_official 146:f64d43ff0c18 1288 #define AIPS_PACRL_WP5_SHIFT 9
mbed_official 146:f64d43ff0c18 1289 #define AIPS_PACRL_SP5_MASK 0x400u
mbed_official 146:f64d43ff0c18 1290 #define AIPS_PACRL_SP5_SHIFT 10
mbed_official 146:f64d43ff0c18 1291 #define AIPS_PACRL_TP4_MASK 0x1000u
mbed_official 146:f64d43ff0c18 1292 #define AIPS_PACRL_TP4_SHIFT 12
mbed_official 146:f64d43ff0c18 1293 #define AIPS_PACRL_WP4_MASK 0x2000u
mbed_official 146:f64d43ff0c18 1294 #define AIPS_PACRL_WP4_SHIFT 13
mbed_official 146:f64d43ff0c18 1295 #define AIPS_PACRL_SP4_MASK 0x4000u
mbed_official 146:f64d43ff0c18 1296 #define AIPS_PACRL_SP4_SHIFT 14
mbed_official 146:f64d43ff0c18 1297 #define AIPS_PACRL_TP3_MASK 0x10000u
mbed_official 146:f64d43ff0c18 1298 #define AIPS_PACRL_TP3_SHIFT 16
mbed_official 146:f64d43ff0c18 1299 #define AIPS_PACRL_WP3_MASK 0x20000u
mbed_official 146:f64d43ff0c18 1300 #define AIPS_PACRL_WP3_SHIFT 17
mbed_official 146:f64d43ff0c18 1301 #define AIPS_PACRL_SP3_MASK 0x40000u
mbed_official 146:f64d43ff0c18 1302 #define AIPS_PACRL_SP3_SHIFT 18
mbed_official 146:f64d43ff0c18 1303 #define AIPS_PACRL_TP2_MASK 0x100000u
mbed_official 146:f64d43ff0c18 1304 #define AIPS_PACRL_TP2_SHIFT 20
mbed_official 146:f64d43ff0c18 1305 #define AIPS_PACRL_WP2_MASK 0x200000u
mbed_official 146:f64d43ff0c18 1306 #define AIPS_PACRL_WP2_SHIFT 21
mbed_official 146:f64d43ff0c18 1307 #define AIPS_PACRL_SP2_MASK 0x400000u
mbed_official 146:f64d43ff0c18 1308 #define AIPS_PACRL_SP2_SHIFT 22
mbed_official 146:f64d43ff0c18 1309 #define AIPS_PACRL_TP1_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 1310 #define AIPS_PACRL_TP1_SHIFT 24
mbed_official 146:f64d43ff0c18 1311 #define AIPS_PACRL_WP1_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 1312 #define AIPS_PACRL_WP1_SHIFT 25
mbed_official 146:f64d43ff0c18 1313 #define AIPS_PACRL_SP1_MASK 0x4000000u
mbed_official 146:f64d43ff0c18 1314 #define AIPS_PACRL_SP1_SHIFT 26
mbed_official 146:f64d43ff0c18 1315 #define AIPS_PACRL_TP0_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 1316 #define AIPS_PACRL_TP0_SHIFT 28
mbed_official 146:f64d43ff0c18 1317 #define AIPS_PACRL_WP0_MASK 0x20000000u
mbed_official 146:f64d43ff0c18 1318 #define AIPS_PACRL_WP0_SHIFT 29
mbed_official 146:f64d43ff0c18 1319 #define AIPS_PACRL_SP0_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 1320 #define AIPS_PACRL_SP0_SHIFT 30
mbed_official 146:f64d43ff0c18 1321 /* PACRM Bit Fields */
mbed_official 146:f64d43ff0c18 1322 #define AIPS_PACRM_TP7_MASK 0x1u
mbed_official 146:f64d43ff0c18 1323 #define AIPS_PACRM_TP7_SHIFT 0
mbed_official 146:f64d43ff0c18 1324 #define AIPS_PACRM_WP7_MASK 0x2u
mbed_official 146:f64d43ff0c18 1325 #define AIPS_PACRM_WP7_SHIFT 1
mbed_official 146:f64d43ff0c18 1326 #define AIPS_PACRM_SP7_MASK 0x4u
mbed_official 146:f64d43ff0c18 1327 #define AIPS_PACRM_SP7_SHIFT 2
mbed_official 146:f64d43ff0c18 1328 #define AIPS_PACRM_TP6_MASK 0x10u
mbed_official 146:f64d43ff0c18 1329 #define AIPS_PACRM_TP6_SHIFT 4
mbed_official 146:f64d43ff0c18 1330 #define AIPS_PACRM_WP6_MASK 0x20u
mbed_official 146:f64d43ff0c18 1331 #define AIPS_PACRM_WP6_SHIFT 5
mbed_official 146:f64d43ff0c18 1332 #define AIPS_PACRM_SP6_MASK 0x40u
mbed_official 146:f64d43ff0c18 1333 #define AIPS_PACRM_SP6_SHIFT 6
mbed_official 146:f64d43ff0c18 1334 #define AIPS_PACRM_TP5_MASK 0x100u
mbed_official 146:f64d43ff0c18 1335 #define AIPS_PACRM_TP5_SHIFT 8
mbed_official 146:f64d43ff0c18 1336 #define AIPS_PACRM_WP5_MASK 0x200u
mbed_official 146:f64d43ff0c18 1337 #define AIPS_PACRM_WP5_SHIFT 9
mbed_official 146:f64d43ff0c18 1338 #define AIPS_PACRM_SP5_MASK 0x400u
mbed_official 146:f64d43ff0c18 1339 #define AIPS_PACRM_SP5_SHIFT 10
mbed_official 146:f64d43ff0c18 1340 #define AIPS_PACRM_TP4_MASK 0x1000u
mbed_official 146:f64d43ff0c18 1341 #define AIPS_PACRM_TP4_SHIFT 12
mbed_official 146:f64d43ff0c18 1342 #define AIPS_PACRM_WP4_MASK 0x2000u
mbed_official 146:f64d43ff0c18 1343 #define AIPS_PACRM_WP4_SHIFT 13
mbed_official 146:f64d43ff0c18 1344 #define AIPS_PACRM_SP4_MASK 0x4000u
mbed_official 146:f64d43ff0c18 1345 #define AIPS_PACRM_SP4_SHIFT 14
mbed_official 146:f64d43ff0c18 1346 #define AIPS_PACRM_TP3_MASK 0x10000u
mbed_official 146:f64d43ff0c18 1347 #define AIPS_PACRM_TP3_SHIFT 16
mbed_official 146:f64d43ff0c18 1348 #define AIPS_PACRM_WP3_MASK 0x20000u
mbed_official 146:f64d43ff0c18 1349 #define AIPS_PACRM_WP3_SHIFT 17
mbed_official 146:f64d43ff0c18 1350 #define AIPS_PACRM_SP3_MASK 0x40000u
mbed_official 146:f64d43ff0c18 1351 #define AIPS_PACRM_SP3_SHIFT 18
mbed_official 146:f64d43ff0c18 1352 #define AIPS_PACRM_TP2_MASK 0x100000u
mbed_official 146:f64d43ff0c18 1353 #define AIPS_PACRM_TP2_SHIFT 20
mbed_official 146:f64d43ff0c18 1354 #define AIPS_PACRM_WP2_MASK 0x200000u
mbed_official 146:f64d43ff0c18 1355 #define AIPS_PACRM_WP2_SHIFT 21
mbed_official 146:f64d43ff0c18 1356 #define AIPS_PACRM_SP2_MASK 0x400000u
mbed_official 146:f64d43ff0c18 1357 #define AIPS_PACRM_SP2_SHIFT 22
mbed_official 146:f64d43ff0c18 1358 #define AIPS_PACRM_TP1_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 1359 #define AIPS_PACRM_TP1_SHIFT 24
mbed_official 146:f64d43ff0c18 1360 #define AIPS_PACRM_WP1_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 1361 #define AIPS_PACRM_WP1_SHIFT 25
mbed_official 146:f64d43ff0c18 1362 #define AIPS_PACRM_SP1_MASK 0x4000000u
mbed_official 146:f64d43ff0c18 1363 #define AIPS_PACRM_SP1_SHIFT 26
mbed_official 146:f64d43ff0c18 1364 #define AIPS_PACRM_TP0_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 1365 #define AIPS_PACRM_TP0_SHIFT 28
mbed_official 146:f64d43ff0c18 1366 #define AIPS_PACRM_WP0_MASK 0x20000000u
mbed_official 146:f64d43ff0c18 1367 #define AIPS_PACRM_WP0_SHIFT 29
mbed_official 146:f64d43ff0c18 1368 #define AIPS_PACRM_SP0_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 1369 #define AIPS_PACRM_SP0_SHIFT 30
mbed_official 146:f64d43ff0c18 1370 /* PACRN Bit Fields */
mbed_official 146:f64d43ff0c18 1371 #define AIPS_PACRN_TP7_MASK 0x1u
mbed_official 146:f64d43ff0c18 1372 #define AIPS_PACRN_TP7_SHIFT 0
mbed_official 146:f64d43ff0c18 1373 #define AIPS_PACRN_WP7_MASK 0x2u
mbed_official 146:f64d43ff0c18 1374 #define AIPS_PACRN_WP7_SHIFT 1
mbed_official 146:f64d43ff0c18 1375 #define AIPS_PACRN_SP7_MASK 0x4u
mbed_official 146:f64d43ff0c18 1376 #define AIPS_PACRN_SP7_SHIFT 2
mbed_official 146:f64d43ff0c18 1377 #define AIPS_PACRN_TP6_MASK 0x10u
mbed_official 146:f64d43ff0c18 1378 #define AIPS_PACRN_TP6_SHIFT 4
mbed_official 146:f64d43ff0c18 1379 #define AIPS_PACRN_WP6_MASK 0x20u
mbed_official 146:f64d43ff0c18 1380 #define AIPS_PACRN_WP6_SHIFT 5
mbed_official 146:f64d43ff0c18 1381 #define AIPS_PACRN_SP6_MASK 0x40u
mbed_official 146:f64d43ff0c18 1382 #define AIPS_PACRN_SP6_SHIFT 6
mbed_official 146:f64d43ff0c18 1383 #define AIPS_PACRN_TP5_MASK 0x100u
mbed_official 146:f64d43ff0c18 1384 #define AIPS_PACRN_TP5_SHIFT 8
mbed_official 146:f64d43ff0c18 1385 #define AIPS_PACRN_WP5_MASK 0x200u
mbed_official 146:f64d43ff0c18 1386 #define AIPS_PACRN_WP5_SHIFT 9
mbed_official 146:f64d43ff0c18 1387 #define AIPS_PACRN_SP5_MASK 0x400u
mbed_official 146:f64d43ff0c18 1388 #define AIPS_PACRN_SP5_SHIFT 10
mbed_official 146:f64d43ff0c18 1389 #define AIPS_PACRN_TP4_MASK 0x1000u
mbed_official 146:f64d43ff0c18 1390 #define AIPS_PACRN_TP4_SHIFT 12
mbed_official 146:f64d43ff0c18 1391 #define AIPS_PACRN_WP4_MASK 0x2000u
mbed_official 146:f64d43ff0c18 1392 #define AIPS_PACRN_WP4_SHIFT 13
mbed_official 146:f64d43ff0c18 1393 #define AIPS_PACRN_SP4_MASK 0x4000u
mbed_official 146:f64d43ff0c18 1394 #define AIPS_PACRN_SP4_SHIFT 14
mbed_official 146:f64d43ff0c18 1395 #define AIPS_PACRN_TP3_MASK 0x10000u
mbed_official 146:f64d43ff0c18 1396 #define AIPS_PACRN_TP3_SHIFT 16
mbed_official 146:f64d43ff0c18 1397 #define AIPS_PACRN_WP3_MASK 0x20000u
mbed_official 146:f64d43ff0c18 1398 #define AIPS_PACRN_WP3_SHIFT 17
mbed_official 146:f64d43ff0c18 1399 #define AIPS_PACRN_SP3_MASK 0x40000u
mbed_official 146:f64d43ff0c18 1400 #define AIPS_PACRN_SP3_SHIFT 18
mbed_official 146:f64d43ff0c18 1401 #define AIPS_PACRN_TP2_MASK 0x100000u
mbed_official 146:f64d43ff0c18 1402 #define AIPS_PACRN_TP2_SHIFT 20
mbed_official 146:f64d43ff0c18 1403 #define AIPS_PACRN_WP2_MASK 0x200000u
mbed_official 146:f64d43ff0c18 1404 #define AIPS_PACRN_WP2_SHIFT 21
mbed_official 146:f64d43ff0c18 1405 #define AIPS_PACRN_SP2_MASK 0x400000u
mbed_official 146:f64d43ff0c18 1406 #define AIPS_PACRN_SP2_SHIFT 22
mbed_official 146:f64d43ff0c18 1407 #define AIPS_PACRN_TP1_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 1408 #define AIPS_PACRN_TP1_SHIFT 24
mbed_official 146:f64d43ff0c18 1409 #define AIPS_PACRN_WP1_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 1410 #define AIPS_PACRN_WP1_SHIFT 25
mbed_official 146:f64d43ff0c18 1411 #define AIPS_PACRN_SP1_MASK 0x4000000u
mbed_official 146:f64d43ff0c18 1412 #define AIPS_PACRN_SP1_SHIFT 26
mbed_official 146:f64d43ff0c18 1413 #define AIPS_PACRN_TP0_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 1414 #define AIPS_PACRN_TP0_SHIFT 28
mbed_official 146:f64d43ff0c18 1415 #define AIPS_PACRN_WP0_MASK 0x20000000u
mbed_official 146:f64d43ff0c18 1416 #define AIPS_PACRN_WP0_SHIFT 29
mbed_official 146:f64d43ff0c18 1417 #define AIPS_PACRN_SP0_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 1418 #define AIPS_PACRN_SP0_SHIFT 30
mbed_official 146:f64d43ff0c18 1419 /* PACRO Bit Fields */
mbed_official 146:f64d43ff0c18 1420 #define AIPS_PACRO_TP7_MASK 0x1u
mbed_official 146:f64d43ff0c18 1421 #define AIPS_PACRO_TP7_SHIFT 0
mbed_official 146:f64d43ff0c18 1422 #define AIPS_PACRO_WP7_MASK 0x2u
mbed_official 146:f64d43ff0c18 1423 #define AIPS_PACRO_WP7_SHIFT 1
mbed_official 146:f64d43ff0c18 1424 #define AIPS_PACRO_SP7_MASK 0x4u
mbed_official 146:f64d43ff0c18 1425 #define AIPS_PACRO_SP7_SHIFT 2
mbed_official 146:f64d43ff0c18 1426 #define AIPS_PACRO_TP6_MASK 0x10u
mbed_official 146:f64d43ff0c18 1427 #define AIPS_PACRO_TP6_SHIFT 4
mbed_official 146:f64d43ff0c18 1428 #define AIPS_PACRO_WP6_MASK 0x20u
mbed_official 146:f64d43ff0c18 1429 #define AIPS_PACRO_WP6_SHIFT 5
mbed_official 146:f64d43ff0c18 1430 #define AIPS_PACRO_SP6_MASK 0x40u
mbed_official 146:f64d43ff0c18 1431 #define AIPS_PACRO_SP6_SHIFT 6
mbed_official 146:f64d43ff0c18 1432 #define AIPS_PACRO_TP5_MASK 0x100u
mbed_official 146:f64d43ff0c18 1433 #define AIPS_PACRO_TP5_SHIFT 8
mbed_official 146:f64d43ff0c18 1434 #define AIPS_PACRO_WP5_MASK 0x200u
mbed_official 146:f64d43ff0c18 1435 #define AIPS_PACRO_WP5_SHIFT 9
mbed_official 146:f64d43ff0c18 1436 #define AIPS_PACRO_SP5_MASK 0x400u
mbed_official 146:f64d43ff0c18 1437 #define AIPS_PACRO_SP5_SHIFT 10
mbed_official 146:f64d43ff0c18 1438 #define AIPS_PACRO_TP4_MASK 0x1000u
mbed_official 146:f64d43ff0c18 1439 #define AIPS_PACRO_TP4_SHIFT 12
mbed_official 146:f64d43ff0c18 1440 #define AIPS_PACRO_WP4_MASK 0x2000u
mbed_official 146:f64d43ff0c18 1441 #define AIPS_PACRO_WP4_SHIFT 13
mbed_official 146:f64d43ff0c18 1442 #define AIPS_PACRO_SP4_MASK 0x4000u
mbed_official 146:f64d43ff0c18 1443 #define AIPS_PACRO_SP4_SHIFT 14
mbed_official 146:f64d43ff0c18 1444 #define AIPS_PACRO_TP3_MASK 0x10000u
mbed_official 146:f64d43ff0c18 1445 #define AIPS_PACRO_TP3_SHIFT 16
mbed_official 146:f64d43ff0c18 1446 #define AIPS_PACRO_WP3_MASK 0x20000u
mbed_official 146:f64d43ff0c18 1447 #define AIPS_PACRO_WP3_SHIFT 17
mbed_official 146:f64d43ff0c18 1448 #define AIPS_PACRO_SP3_MASK 0x40000u
mbed_official 146:f64d43ff0c18 1449 #define AIPS_PACRO_SP3_SHIFT 18
mbed_official 146:f64d43ff0c18 1450 #define AIPS_PACRO_TP2_MASK 0x100000u
mbed_official 146:f64d43ff0c18 1451 #define AIPS_PACRO_TP2_SHIFT 20
mbed_official 146:f64d43ff0c18 1452 #define AIPS_PACRO_WP2_MASK 0x200000u
mbed_official 146:f64d43ff0c18 1453 #define AIPS_PACRO_WP2_SHIFT 21
mbed_official 146:f64d43ff0c18 1454 #define AIPS_PACRO_SP2_MASK 0x400000u
mbed_official 146:f64d43ff0c18 1455 #define AIPS_PACRO_SP2_SHIFT 22
mbed_official 146:f64d43ff0c18 1456 #define AIPS_PACRO_TP1_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 1457 #define AIPS_PACRO_TP1_SHIFT 24
mbed_official 146:f64d43ff0c18 1458 #define AIPS_PACRO_WP1_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 1459 #define AIPS_PACRO_WP1_SHIFT 25
mbed_official 146:f64d43ff0c18 1460 #define AIPS_PACRO_SP1_MASK 0x4000000u
mbed_official 146:f64d43ff0c18 1461 #define AIPS_PACRO_SP1_SHIFT 26
mbed_official 146:f64d43ff0c18 1462 #define AIPS_PACRO_TP0_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 1463 #define AIPS_PACRO_TP0_SHIFT 28
mbed_official 146:f64d43ff0c18 1464 #define AIPS_PACRO_WP0_MASK 0x20000000u
mbed_official 146:f64d43ff0c18 1465 #define AIPS_PACRO_WP0_SHIFT 29
mbed_official 146:f64d43ff0c18 1466 #define AIPS_PACRO_SP0_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 1467 #define AIPS_PACRO_SP0_SHIFT 30
mbed_official 146:f64d43ff0c18 1468 /* PACRP Bit Fields */
mbed_official 146:f64d43ff0c18 1469 #define AIPS_PACRP_TP7_MASK 0x1u
mbed_official 146:f64d43ff0c18 1470 #define AIPS_PACRP_TP7_SHIFT 0
mbed_official 146:f64d43ff0c18 1471 #define AIPS_PACRP_WP7_MASK 0x2u
mbed_official 146:f64d43ff0c18 1472 #define AIPS_PACRP_WP7_SHIFT 1
mbed_official 146:f64d43ff0c18 1473 #define AIPS_PACRP_SP7_MASK 0x4u
mbed_official 146:f64d43ff0c18 1474 #define AIPS_PACRP_SP7_SHIFT 2
mbed_official 146:f64d43ff0c18 1475 #define AIPS_PACRP_TP6_MASK 0x10u
mbed_official 146:f64d43ff0c18 1476 #define AIPS_PACRP_TP6_SHIFT 4
mbed_official 146:f64d43ff0c18 1477 #define AIPS_PACRP_WP6_MASK 0x20u
mbed_official 146:f64d43ff0c18 1478 #define AIPS_PACRP_WP6_SHIFT 5
mbed_official 146:f64d43ff0c18 1479 #define AIPS_PACRP_SP6_MASK 0x40u
mbed_official 146:f64d43ff0c18 1480 #define AIPS_PACRP_SP6_SHIFT 6
mbed_official 146:f64d43ff0c18 1481 #define AIPS_PACRP_TP5_MASK 0x100u
mbed_official 146:f64d43ff0c18 1482 #define AIPS_PACRP_TP5_SHIFT 8
mbed_official 146:f64d43ff0c18 1483 #define AIPS_PACRP_WP5_MASK 0x200u
mbed_official 146:f64d43ff0c18 1484 #define AIPS_PACRP_WP5_SHIFT 9
mbed_official 146:f64d43ff0c18 1485 #define AIPS_PACRP_SP5_MASK 0x400u
mbed_official 146:f64d43ff0c18 1486 #define AIPS_PACRP_SP5_SHIFT 10
mbed_official 146:f64d43ff0c18 1487 #define AIPS_PACRP_TP4_MASK 0x1000u
mbed_official 146:f64d43ff0c18 1488 #define AIPS_PACRP_TP4_SHIFT 12
mbed_official 146:f64d43ff0c18 1489 #define AIPS_PACRP_WP4_MASK 0x2000u
mbed_official 146:f64d43ff0c18 1490 #define AIPS_PACRP_WP4_SHIFT 13
mbed_official 146:f64d43ff0c18 1491 #define AIPS_PACRP_SP4_MASK 0x4000u
mbed_official 146:f64d43ff0c18 1492 #define AIPS_PACRP_SP4_SHIFT 14
mbed_official 146:f64d43ff0c18 1493 #define AIPS_PACRP_TP3_MASK 0x10000u
mbed_official 146:f64d43ff0c18 1494 #define AIPS_PACRP_TP3_SHIFT 16
mbed_official 146:f64d43ff0c18 1495 #define AIPS_PACRP_WP3_MASK 0x20000u
mbed_official 146:f64d43ff0c18 1496 #define AIPS_PACRP_WP3_SHIFT 17
mbed_official 146:f64d43ff0c18 1497 #define AIPS_PACRP_SP3_MASK 0x40000u
mbed_official 146:f64d43ff0c18 1498 #define AIPS_PACRP_SP3_SHIFT 18
mbed_official 146:f64d43ff0c18 1499 #define AIPS_PACRP_TP2_MASK 0x100000u
mbed_official 146:f64d43ff0c18 1500 #define AIPS_PACRP_TP2_SHIFT 20
mbed_official 146:f64d43ff0c18 1501 #define AIPS_PACRP_WP2_MASK 0x200000u
mbed_official 146:f64d43ff0c18 1502 #define AIPS_PACRP_WP2_SHIFT 21
mbed_official 146:f64d43ff0c18 1503 #define AIPS_PACRP_SP2_MASK 0x400000u
mbed_official 146:f64d43ff0c18 1504 #define AIPS_PACRP_SP2_SHIFT 22
mbed_official 146:f64d43ff0c18 1505 #define AIPS_PACRP_TP1_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 1506 #define AIPS_PACRP_TP1_SHIFT 24
mbed_official 146:f64d43ff0c18 1507 #define AIPS_PACRP_WP1_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 1508 #define AIPS_PACRP_WP1_SHIFT 25
mbed_official 146:f64d43ff0c18 1509 #define AIPS_PACRP_SP1_MASK 0x4000000u
mbed_official 146:f64d43ff0c18 1510 #define AIPS_PACRP_SP1_SHIFT 26
mbed_official 146:f64d43ff0c18 1511 #define AIPS_PACRP_TP0_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 1512 #define AIPS_PACRP_TP0_SHIFT 28
mbed_official 146:f64d43ff0c18 1513 #define AIPS_PACRP_WP0_MASK 0x20000000u
mbed_official 146:f64d43ff0c18 1514 #define AIPS_PACRP_WP0_SHIFT 29
mbed_official 146:f64d43ff0c18 1515 #define AIPS_PACRP_SP0_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 1516 #define AIPS_PACRP_SP0_SHIFT 30
mbed_official 146:f64d43ff0c18 1517 /* PACRU Bit Fields */
mbed_official 146:f64d43ff0c18 1518 #define AIPS_PACRU_TP1_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 1519 #define AIPS_PACRU_TP1_SHIFT 24
mbed_official 146:f64d43ff0c18 1520 #define AIPS_PACRU_WP1_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 1521 #define AIPS_PACRU_WP1_SHIFT 25
mbed_official 146:f64d43ff0c18 1522 #define AIPS_PACRU_SP1_MASK 0x4000000u
mbed_official 146:f64d43ff0c18 1523 #define AIPS_PACRU_SP1_SHIFT 26
mbed_official 146:f64d43ff0c18 1524 #define AIPS_PACRU_TP0_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 1525 #define AIPS_PACRU_TP0_SHIFT 28
mbed_official 146:f64d43ff0c18 1526 #define AIPS_PACRU_WP0_MASK 0x20000000u
mbed_official 146:f64d43ff0c18 1527 #define AIPS_PACRU_WP0_SHIFT 29
mbed_official 146:f64d43ff0c18 1528 #define AIPS_PACRU_SP0_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 1529 #define AIPS_PACRU_SP0_SHIFT 30
mbed_official 146:f64d43ff0c18 1530
mbed_official 146:f64d43ff0c18 1531 /*!
mbed_official 146:f64d43ff0c18 1532 * @}
mbed_official 146:f64d43ff0c18 1533 */ /* end of group AIPS_Register_Masks */
mbed_official 146:f64d43ff0c18 1534
mbed_official 146:f64d43ff0c18 1535
mbed_official 146:f64d43ff0c18 1536 /* AIPS - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 1537 /** Peripheral AIPS0 base address */
mbed_official 146:f64d43ff0c18 1538 #define AIPS0_BASE (0x40000000u)
mbed_official 146:f64d43ff0c18 1539 /** Peripheral AIPS0 base pointer */
mbed_official 146:f64d43ff0c18 1540 #define AIPS0 ((AIPS_Type *)AIPS0_BASE)
mbed_official 146:f64d43ff0c18 1541 #define AIPS0_BASE_PTR (AIPS0)
mbed_official 146:f64d43ff0c18 1542 /** Peripheral AIPS1 base address */
mbed_official 146:f64d43ff0c18 1543 #define AIPS1_BASE (0x40080000u)
mbed_official 146:f64d43ff0c18 1544 /** Peripheral AIPS1 base pointer */
mbed_official 146:f64d43ff0c18 1545 #define AIPS1 ((AIPS_Type *)AIPS1_BASE)
mbed_official 146:f64d43ff0c18 1546 #define AIPS1_BASE_PTR (AIPS1)
mbed_official 146:f64d43ff0c18 1547 /** Array initializer of AIPS peripheral base pointers */
mbed_official 146:f64d43ff0c18 1548 #define AIPS_BASES { AIPS0, AIPS1 }
mbed_official 146:f64d43ff0c18 1549
mbed_official 146:f64d43ff0c18 1550 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1551 -- AIPS - Register accessor macros
mbed_official 146:f64d43ff0c18 1552 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 1553
mbed_official 146:f64d43ff0c18 1554 /*!
mbed_official 146:f64d43ff0c18 1555 * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
mbed_official 146:f64d43ff0c18 1556 * @{
mbed_official 146:f64d43ff0c18 1557 */
mbed_official 146:f64d43ff0c18 1558
mbed_official 146:f64d43ff0c18 1559
mbed_official 146:f64d43ff0c18 1560 /* AIPS - Register instance definitions */
mbed_official 146:f64d43ff0c18 1561 /* AIPS0 */
mbed_official 146:f64d43ff0c18 1562 #define AIPS0_MPRA AIPS_MPRA_REG(AIPS0)
mbed_official 146:f64d43ff0c18 1563 #define AIPS0_PACRA AIPS_PACRA_REG(AIPS0)
mbed_official 146:f64d43ff0c18 1564 #define AIPS0_PACRB AIPS_PACRB_REG(AIPS0)
mbed_official 146:f64d43ff0c18 1565 #define AIPS0_PACRC AIPS_PACRC_REG(AIPS0)
mbed_official 146:f64d43ff0c18 1566 #define AIPS0_PACRD AIPS_PACRD_REG(AIPS0)
mbed_official 146:f64d43ff0c18 1567 #define AIPS0_PACRE AIPS_PACRE_REG(AIPS0)
mbed_official 146:f64d43ff0c18 1568 #define AIPS0_PACRF AIPS_PACRF_REG(AIPS0)
mbed_official 146:f64d43ff0c18 1569 #define AIPS0_PACRG AIPS_PACRG_REG(AIPS0)
mbed_official 146:f64d43ff0c18 1570 #define AIPS0_PACRH AIPS_PACRH_REG(AIPS0)
mbed_official 146:f64d43ff0c18 1571 #define AIPS0_PACRI AIPS_PACRI_REG(AIPS0)
mbed_official 146:f64d43ff0c18 1572 #define AIPS0_PACRJ AIPS_PACRJ_REG(AIPS0)
mbed_official 146:f64d43ff0c18 1573 #define AIPS0_PACRK AIPS_PACRK_REG(AIPS0)
mbed_official 146:f64d43ff0c18 1574 #define AIPS0_PACRL AIPS_PACRL_REG(AIPS0)
mbed_official 146:f64d43ff0c18 1575 #define AIPS0_PACRM AIPS_PACRM_REG(AIPS0)
mbed_official 146:f64d43ff0c18 1576 #define AIPS0_PACRN AIPS_PACRN_REG(AIPS0)
mbed_official 146:f64d43ff0c18 1577 #define AIPS0_PACRO AIPS_PACRO_REG(AIPS0)
mbed_official 146:f64d43ff0c18 1578 #define AIPS0_PACRP AIPS_PACRP_REG(AIPS0)
mbed_official 146:f64d43ff0c18 1579 #define AIPS0_PACRU AIPS_PACRU_REG(AIPS0)
mbed_official 146:f64d43ff0c18 1580 /* AIPS1 */
mbed_official 146:f64d43ff0c18 1581 #define AIPS1_MPRA AIPS_MPRA_REG(AIPS1)
mbed_official 146:f64d43ff0c18 1582 #define AIPS1_PACRA AIPS_PACRA_REG(AIPS1)
mbed_official 146:f64d43ff0c18 1583 #define AIPS1_PACRB AIPS_PACRB_REG(AIPS1)
mbed_official 146:f64d43ff0c18 1584 #define AIPS1_PACRC AIPS_PACRC_REG(AIPS1)
mbed_official 146:f64d43ff0c18 1585 #define AIPS1_PACRD AIPS_PACRD_REG(AIPS1)
mbed_official 146:f64d43ff0c18 1586 #define AIPS1_PACRE AIPS_PACRE_REG(AIPS1)
mbed_official 146:f64d43ff0c18 1587 #define AIPS1_PACRF AIPS_PACRF_REG(AIPS1)
mbed_official 146:f64d43ff0c18 1588 #define AIPS1_PACRG AIPS_PACRG_REG(AIPS1)
mbed_official 146:f64d43ff0c18 1589 #define AIPS1_PACRH AIPS_PACRH_REG(AIPS1)
mbed_official 146:f64d43ff0c18 1590 #define AIPS1_PACRI AIPS_PACRI_REG(AIPS1)
mbed_official 146:f64d43ff0c18 1591 #define AIPS1_PACRJ AIPS_PACRJ_REG(AIPS1)
mbed_official 146:f64d43ff0c18 1592 #define AIPS1_PACRK AIPS_PACRK_REG(AIPS1)
mbed_official 146:f64d43ff0c18 1593 #define AIPS1_PACRL AIPS_PACRL_REG(AIPS1)
mbed_official 146:f64d43ff0c18 1594 #define AIPS1_PACRM AIPS_PACRM_REG(AIPS1)
mbed_official 146:f64d43ff0c18 1595 #define AIPS1_PACRN AIPS_PACRN_REG(AIPS1)
mbed_official 146:f64d43ff0c18 1596 #define AIPS1_PACRO AIPS_PACRO_REG(AIPS1)
mbed_official 146:f64d43ff0c18 1597 #define AIPS1_PACRP AIPS_PACRP_REG(AIPS1)
mbed_official 146:f64d43ff0c18 1598 #define AIPS1_PACRU AIPS_PACRU_REG(AIPS1)
mbed_official 146:f64d43ff0c18 1599
mbed_official 146:f64d43ff0c18 1600 /*!
mbed_official 146:f64d43ff0c18 1601 * @}
mbed_official 146:f64d43ff0c18 1602 */ /* end of group AIPS_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 1603
mbed_official 146:f64d43ff0c18 1604
mbed_official 146:f64d43ff0c18 1605 /*!
mbed_official 146:f64d43ff0c18 1606 * @}
mbed_official 146:f64d43ff0c18 1607 */ /* end of group AIPS_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 1608
mbed_official 146:f64d43ff0c18 1609
mbed_official 146:f64d43ff0c18 1610 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1611 -- AXBS Peripheral Access Layer
mbed_official 146:f64d43ff0c18 1612 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 1613
mbed_official 146:f64d43ff0c18 1614 /*!
mbed_official 146:f64d43ff0c18 1615 * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
mbed_official 146:f64d43ff0c18 1616 * @{
mbed_official 146:f64d43ff0c18 1617 */
mbed_official 146:f64d43ff0c18 1618
mbed_official 146:f64d43ff0c18 1619 /** AXBS - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 1620 typedef struct {
mbed_official 146:f64d43ff0c18 1621 struct { /* offset: 0x0, array step: 0x100 */
mbed_official 146:f64d43ff0c18 1622 __IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
mbed_official 146:f64d43ff0c18 1623 uint8_t RESERVED_0[12];
mbed_official 146:f64d43ff0c18 1624 __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */
mbed_official 146:f64d43ff0c18 1625 uint8_t RESERVED_1[236];
mbed_official 146:f64d43ff0c18 1626 } SLAVE[5];
mbed_official 146:f64d43ff0c18 1627 uint8_t RESERVED_0[768];
mbed_official 146:f64d43ff0c18 1628 __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */
mbed_official 146:f64d43ff0c18 1629 uint8_t RESERVED_1[252];
mbed_official 146:f64d43ff0c18 1630 __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */
mbed_official 146:f64d43ff0c18 1631 uint8_t RESERVED_2[252];
mbed_official 146:f64d43ff0c18 1632 __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */
mbed_official 146:f64d43ff0c18 1633 uint8_t RESERVED_3[252];
mbed_official 146:f64d43ff0c18 1634 __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */
mbed_official 146:f64d43ff0c18 1635 uint8_t RESERVED_4[252];
mbed_official 146:f64d43ff0c18 1636 __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */
mbed_official 146:f64d43ff0c18 1637 uint8_t RESERVED_5[252];
mbed_official 146:f64d43ff0c18 1638 __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */
mbed_official 146:f64d43ff0c18 1639 } AXBS_Type, *AXBS_MemMapPtr;
mbed_official 146:f64d43ff0c18 1640
mbed_official 146:f64d43ff0c18 1641 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1642 -- AXBS - Register accessor macros
mbed_official 146:f64d43ff0c18 1643 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 1644
mbed_official 146:f64d43ff0c18 1645 /*!
mbed_official 146:f64d43ff0c18 1646 * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
mbed_official 146:f64d43ff0c18 1647 * @{
mbed_official 146:f64d43ff0c18 1648 */
mbed_official 146:f64d43ff0c18 1649
mbed_official 146:f64d43ff0c18 1650
mbed_official 146:f64d43ff0c18 1651 /* AXBS - Register accessors */
mbed_official 146:f64d43ff0c18 1652 #define AXBS_PRS_REG(base,index) ((base)->SLAVE[index].PRS)
mbed_official 146:f64d43ff0c18 1653 #define AXBS_CRS_REG(base,index) ((base)->SLAVE[index].CRS)
mbed_official 146:f64d43ff0c18 1654 #define AXBS_MGPCR0_REG(base) ((base)->MGPCR0)
mbed_official 146:f64d43ff0c18 1655 #define AXBS_MGPCR1_REG(base) ((base)->MGPCR1)
mbed_official 146:f64d43ff0c18 1656 #define AXBS_MGPCR2_REG(base) ((base)->MGPCR2)
mbed_official 146:f64d43ff0c18 1657 #define AXBS_MGPCR3_REG(base) ((base)->MGPCR3)
mbed_official 146:f64d43ff0c18 1658 #define AXBS_MGPCR4_REG(base) ((base)->MGPCR4)
mbed_official 146:f64d43ff0c18 1659 #define AXBS_MGPCR5_REG(base) ((base)->MGPCR5)
mbed_official 146:f64d43ff0c18 1660
mbed_official 146:f64d43ff0c18 1661 /*!
mbed_official 146:f64d43ff0c18 1662 * @}
mbed_official 146:f64d43ff0c18 1663 */ /* end of group AXBS_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 1664
mbed_official 146:f64d43ff0c18 1665
mbed_official 146:f64d43ff0c18 1666 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1667 -- AXBS Register Masks
mbed_official 146:f64d43ff0c18 1668 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 1669
mbed_official 146:f64d43ff0c18 1670 /*!
mbed_official 146:f64d43ff0c18 1671 * @addtogroup AXBS_Register_Masks AXBS Register Masks
mbed_official 146:f64d43ff0c18 1672 * @{
mbed_official 146:f64d43ff0c18 1673 */
mbed_official 146:f64d43ff0c18 1674
mbed_official 146:f64d43ff0c18 1675 /* PRS Bit Fields */
mbed_official 146:f64d43ff0c18 1676 #define AXBS_PRS_M0_MASK 0x7u
mbed_official 146:f64d43ff0c18 1677 #define AXBS_PRS_M0_SHIFT 0
mbed_official 146:f64d43ff0c18 1678 #define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M0_SHIFT))&AXBS_PRS_M0_MASK)
mbed_official 146:f64d43ff0c18 1679 #define AXBS_PRS_M1_MASK 0x70u
mbed_official 146:f64d43ff0c18 1680 #define AXBS_PRS_M1_SHIFT 4
mbed_official 146:f64d43ff0c18 1681 #define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M1_SHIFT))&AXBS_PRS_M1_MASK)
mbed_official 146:f64d43ff0c18 1682 #define AXBS_PRS_M2_MASK 0x700u
mbed_official 146:f64d43ff0c18 1683 #define AXBS_PRS_M2_SHIFT 8
mbed_official 146:f64d43ff0c18 1684 #define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M2_SHIFT))&AXBS_PRS_M2_MASK)
mbed_official 146:f64d43ff0c18 1685 #define AXBS_PRS_M3_MASK 0x7000u
mbed_official 146:f64d43ff0c18 1686 #define AXBS_PRS_M3_SHIFT 12
mbed_official 146:f64d43ff0c18 1687 #define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M3_SHIFT))&AXBS_PRS_M3_MASK)
mbed_official 146:f64d43ff0c18 1688 #define AXBS_PRS_M4_MASK 0x70000u
mbed_official 146:f64d43ff0c18 1689 #define AXBS_PRS_M4_SHIFT 16
mbed_official 146:f64d43ff0c18 1690 #define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M4_SHIFT))&AXBS_PRS_M4_MASK)
mbed_official 146:f64d43ff0c18 1691 #define AXBS_PRS_M5_MASK 0x700000u
mbed_official 146:f64d43ff0c18 1692 #define AXBS_PRS_M5_SHIFT 20
mbed_official 146:f64d43ff0c18 1693 #define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M5_SHIFT))&AXBS_PRS_M5_MASK)
mbed_official 146:f64d43ff0c18 1694 /* CRS Bit Fields */
mbed_official 146:f64d43ff0c18 1695 #define AXBS_CRS_PARK_MASK 0x7u
mbed_official 146:f64d43ff0c18 1696 #define AXBS_CRS_PARK_SHIFT 0
mbed_official 146:f64d43ff0c18 1697 #define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PARK_SHIFT))&AXBS_CRS_PARK_MASK)
mbed_official 146:f64d43ff0c18 1698 #define AXBS_CRS_PCTL_MASK 0x30u
mbed_official 146:f64d43ff0c18 1699 #define AXBS_CRS_PCTL_SHIFT 4
mbed_official 146:f64d43ff0c18 1700 #define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PCTL_SHIFT))&AXBS_CRS_PCTL_MASK)
mbed_official 146:f64d43ff0c18 1701 #define AXBS_CRS_ARB_MASK 0x300u
mbed_official 146:f64d43ff0c18 1702 #define AXBS_CRS_ARB_SHIFT 8
mbed_official 146:f64d43ff0c18 1703 #define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_ARB_SHIFT))&AXBS_CRS_ARB_MASK)
mbed_official 146:f64d43ff0c18 1704 #define AXBS_CRS_HLP_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 1705 #define AXBS_CRS_HLP_SHIFT 30
mbed_official 146:f64d43ff0c18 1706 #define AXBS_CRS_RO_MASK 0x80000000u
mbed_official 146:f64d43ff0c18 1707 #define AXBS_CRS_RO_SHIFT 31
mbed_official 146:f64d43ff0c18 1708 /* MGPCR0 Bit Fields */
mbed_official 146:f64d43ff0c18 1709 #define AXBS_MGPCR0_AULB_MASK 0x7u
mbed_official 146:f64d43ff0c18 1710 #define AXBS_MGPCR0_AULB_SHIFT 0
mbed_official 146:f64d43ff0c18 1711 #define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR0_AULB_SHIFT))&AXBS_MGPCR0_AULB_MASK)
mbed_official 146:f64d43ff0c18 1712 /* MGPCR1 Bit Fields */
mbed_official 146:f64d43ff0c18 1713 #define AXBS_MGPCR1_AULB_MASK 0x7u
mbed_official 146:f64d43ff0c18 1714 #define AXBS_MGPCR1_AULB_SHIFT 0
mbed_official 146:f64d43ff0c18 1715 #define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR1_AULB_SHIFT))&AXBS_MGPCR1_AULB_MASK)
mbed_official 146:f64d43ff0c18 1716 /* MGPCR2 Bit Fields */
mbed_official 146:f64d43ff0c18 1717 #define AXBS_MGPCR2_AULB_MASK 0x7u
mbed_official 146:f64d43ff0c18 1718 #define AXBS_MGPCR2_AULB_SHIFT 0
mbed_official 146:f64d43ff0c18 1719 #define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR2_AULB_SHIFT))&AXBS_MGPCR2_AULB_MASK)
mbed_official 146:f64d43ff0c18 1720 /* MGPCR3 Bit Fields */
mbed_official 146:f64d43ff0c18 1721 #define AXBS_MGPCR3_AULB_MASK 0x7u
mbed_official 146:f64d43ff0c18 1722 #define AXBS_MGPCR3_AULB_SHIFT 0
mbed_official 146:f64d43ff0c18 1723 #define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR3_AULB_SHIFT))&AXBS_MGPCR3_AULB_MASK)
mbed_official 146:f64d43ff0c18 1724 /* MGPCR4 Bit Fields */
mbed_official 146:f64d43ff0c18 1725 #define AXBS_MGPCR4_AULB_MASK 0x7u
mbed_official 146:f64d43ff0c18 1726 #define AXBS_MGPCR4_AULB_SHIFT 0
mbed_official 146:f64d43ff0c18 1727 #define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR4_AULB_SHIFT))&AXBS_MGPCR4_AULB_MASK)
mbed_official 146:f64d43ff0c18 1728 /* MGPCR5 Bit Fields */
mbed_official 146:f64d43ff0c18 1729 #define AXBS_MGPCR5_AULB_MASK 0x7u
mbed_official 146:f64d43ff0c18 1730 #define AXBS_MGPCR5_AULB_SHIFT 0
mbed_official 146:f64d43ff0c18 1731 #define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR5_AULB_SHIFT))&AXBS_MGPCR5_AULB_MASK)
mbed_official 146:f64d43ff0c18 1732
mbed_official 146:f64d43ff0c18 1733 /*!
mbed_official 146:f64d43ff0c18 1734 * @}
mbed_official 146:f64d43ff0c18 1735 */ /* end of group AXBS_Register_Masks */
mbed_official 146:f64d43ff0c18 1736
mbed_official 146:f64d43ff0c18 1737
mbed_official 146:f64d43ff0c18 1738 /* AXBS - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 1739 /** Peripheral AXBS base address */
mbed_official 146:f64d43ff0c18 1740 #define AXBS_BASE (0x40004000u)
mbed_official 146:f64d43ff0c18 1741 /** Peripheral AXBS base pointer */
mbed_official 146:f64d43ff0c18 1742 #define AXBS ((AXBS_Type *)AXBS_BASE)
mbed_official 146:f64d43ff0c18 1743 #define AXBS_BASE_PTR (AXBS)
mbed_official 146:f64d43ff0c18 1744 /** Array initializer of AXBS peripheral base pointers */
mbed_official 146:f64d43ff0c18 1745 #define AXBS_BASES { AXBS }
mbed_official 146:f64d43ff0c18 1746
mbed_official 146:f64d43ff0c18 1747 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1748 -- AXBS - Register accessor macros
mbed_official 146:f64d43ff0c18 1749 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 1750
mbed_official 146:f64d43ff0c18 1751 /*!
mbed_official 146:f64d43ff0c18 1752 * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
mbed_official 146:f64d43ff0c18 1753 * @{
mbed_official 146:f64d43ff0c18 1754 */
mbed_official 146:f64d43ff0c18 1755
mbed_official 146:f64d43ff0c18 1756
mbed_official 146:f64d43ff0c18 1757 /* AXBS - Register instance definitions */
mbed_official 146:f64d43ff0c18 1758 /* AXBS */
mbed_official 146:f64d43ff0c18 1759 #define AXBS_PRS0 AXBS_PRS_REG(AXBS,0)
mbed_official 146:f64d43ff0c18 1760 #define AXBS_CRS0 AXBS_CRS_REG(AXBS,0)
mbed_official 146:f64d43ff0c18 1761 #define AXBS_PRS1 AXBS_PRS_REG(AXBS,1)
mbed_official 146:f64d43ff0c18 1762 #define AXBS_CRS1 AXBS_CRS_REG(AXBS,1)
mbed_official 146:f64d43ff0c18 1763 #define AXBS_PRS2 AXBS_PRS_REG(AXBS,2)
mbed_official 146:f64d43ff0c18 1764 #define AXBS_CRS2 AXBS_CRS_REG(AXBS,2)
mbed_official 146:f64d43ff0c18 1765 #define AXBS_PRS3 AXBS_PRS_REG(AXBS,3)
mbed_official 146:f64d43ff0c18 1766 #define AXBS_CRS3 AXBS_CRS_REG(AXBS,3)
mbed_official 146:f64d43ff0c18 1767 #define AXBS_PRS4 AXBS_PRS_REG(AXBS,4)
mbed_official 146:f64d43ff0c18 1768 #define AXBS_CRS4 AXBS_CRS_REG(AXBS,4)
mbed_official 146:f64d43ff0c18 1769 #define AXBS_MGPCR0 AXBS_MGPCR0_REG(AXBS)
mbed_official 146:f64d43ff0c18 1770 #define AXBS_MGPCR1 AXBS_MGPCR1_REG(AXBS)
mbed_official 146:f64d43ff0c18 1771 #define AXBS_MGPCR2 AXBS_MGPCR2_REG(AXBS)
mbed_official 146:f64d43ff0c18 1772 #define AXBS_MGPCR3 AXBS_MGPCR3_REG(AXBS)
mbed_official 146:f64d43ff0c18 1773 #define AXBS_MGPCR4 AXBS_MGPCR4_REG(AXBS)
mbed_official 146:f64d43ff0c18 1774 #define AXBS_MGPCR5 AXBS_MGPCR5_REG(AXBS)
mbed_official 146:f64d43ff0c18 1775
mbed_official 146:f64d43ff0c18 1776 /* AXBS - Register array accessors */
mbed_official 146:f64d43ff0c18 1777 #define AXBS_PRS(index) AXBS_PRS_REG(AXBS,index)
mbed_official 146:f64d43ff0c18 1778 #define AXBS_CRS(index) AXBS_CRS_REG(AXBS,index)
mbed_official 146:f64d43ff0c18 1779
mbed_official 146:f64d43ff0c18 1780 /*!
mbed_official 146:f64d43ff0c18 1781 * @}
mbed_official 146:f64d43ff0c18 1782 */ /* end of group AXBS_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 1783
mbed_official 146:f64d43ff0c18 1784
mbed_official 146:f64d43ff0c18 1785 /*!
mbed_official 146:f64d43ff0c18 1786 * @}
mbed_official 146:f64d43ff0c18 1787 */ /* end of group AXBS_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 1788
mbed_official 146:f64d43ff0c18 1789
mbed_official 146:f64d43ff0c18 1790 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1791 -- CAN Peripheral Access Layer
mbed_official 146:f64d43ff0c18 1792 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 1793
mbed_official 146:f64d43ff0c18 1794 /*!
mbed_official 146:f64d43ff0c18 1795 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
mbed_official 146:f64d43ff0c18 1796 * @{
mbed_official 146:f64d43ff0c18 1797 */
mbed_official 146:f64d43ff0c18 1798
mbed_official 146:f64d43ff0c18 1799 /** CAN - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 1800 typedef struct {
mbed_official 146:f64d43ff0c18 1801 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
mbed_official 146:f64d43ff0c18 1802 __IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */
mbed_official 146:f64d43ff0c18 1803 __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */
mbed_official 146:f64d43ff0c18 1804 uint8_t RESERVED_0[4];
mbed_official 146:f64d43ff0c18 1805 __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
mbed_official 146:f64d43ff0c18 1806 __IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */
mbed_official 146:f64d43ff0c18 1807 __IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */
mbed_official 146:f64d43ff0c18 1808 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */
mbed_official 146:f64d43ff0c18 1809 __IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */
mbed_official 146:f64d43ff0c18 1810 uint8_t RESERVED_1[4];
mbed_official 146:f64d43ff0c18 1811 __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */
mbed_official 146:f64d43ff0c18 1812 uint8_t RESERVED_2[4];
mbed_official 146:f64d43ff0c18 1813 __IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */
mbed_official 146:f64d43ff0c18 1814 __IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */
mbed_official 146:f64d43ff0c18 1815 __I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */
mbed_official 146:f64d43ff0c18 1816 uint8_t RESERVED_3[8];
mbed_official 146:f64d43ff0c18 1817 __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */
mbed_official 146:f64d43ff0c18 1818 __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */
mbed_official 146:f64d43ff0c18 1819 __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */
mbed_official 146:f64d43ff0c18 1820 uint8_t RESERVED_4[48];
mbed_official 146:f64d43ff0c18 1821 struct { /* offset: 0x80, array step: 0x10 */
mbed_official 146:f64d43ff0c18 1822 __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
mbed_official 146:f64d43ff0c18 1823 __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
mbed_official 146:f64d43ff0c18 1824 __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
mbed_official 146:f64d43ff0c18 1825 __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
mbed_official 146:f64d43ff0c18 1826 } MB[16];
mbed_official 146:f64d43ff0c18 1827 uint8_t RESERVED_5[1792];
mbed_official 146:f64d43ff0c18 1828 __IO uint32_t RXIMR[16]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
mbed_official 146:f64d43ff0c18 1829 } CAN_Type, *CAN_MemMapPtr;
mbed_official 146:f64d43ff0c18 1830
mbed_official 146:f64d43ff0c18 1831 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1832 -- CAN - Register accessor macros
mbed_official 146:f64d43ff0c18 1833 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 1834
mbed_official 146:f64d43ff0c18 1835 /*!
mbed_official 146:f64d43ff0c18 1836 * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
mbed_official 146:f64d43ff0c18 1837 * @{
mbed_official 146:f64d43ff0c18 1838 */
mbed_official 146:f64d43ff0c18 1839
mbed_official 146:f64d43ff0c18 1840
mbed_official 146:f64d43ff0c18 1841 /* CAN - Register accessors */
mbed_official 146:f64d43ff0c18 1842 #define CAN_MCR_REG(base) ((base)->MCR)
mbed_official 146:f64d43ff0c18 1843 #define CAN_CTRL1_REG(base) ((base)->CTRL1)
mbed_official 146:f64d43ff0c18 1844 #define CAN_TIMER_REG(base) ((base)->TIMER)
mbed_official 146:f64d43ff0c18 1845 #define CAN_RXMGMASK_REG(base) ((base)->RXMGMASK)
mbed_official 146:f64d43ff0c18 1846 #define CAN_RX14MASK_REG(base) ((base)->RX14MASK)
mbed_official 146:f64d43ff0c18 1847 #define CAN_RX15MASK_REG(base) ((base)->RX15MASK)
mbed_official 146:f64d43ff0c18 1848 #define CAN_ECR_REG(base) ((base)->ECR)
mbed_official 146:f64d43ff0c18 1849 #define CAN_ESR1_REG(base) ((base)->ESR1)
mbed_official 146:f64d43ff0c18 1850 #define CAN_IMASK1_REG(base) ((base)->IMASK1)
mbed_official 146:f64d43ff0c18 1851 #define CAN_IFLAG1_REG(base) ((base)->IFLAG1)
mbed_official 146:f64d43ff0c18 1852 #define CAN_CTRL2_REG(base) ((base)->CTRL2)
mbed_official 146:f64d43ff0c18 1853 #define CAN_ESR2_REG(base) ((base)->ESR2)
mbed_official 146:f64d43ff0c18 1854 #define CAN_CRCR_REG(base) ((base)->CRCR)
mbed_official 146:f64d43ff0c18 1855 #define CAN_RXFGMASK_REG(base) ((base)->RXFGMASK)
mbed_official 146:f64d43ff0c18 1856 #define CAN_RXFIR_REG(base) ((base)->RXFIR)
mbed_official 146:f64d43ff0c18 1857 #define CAN_CS_REG(base,index) ((base)->MB[index].CS)
mbed_official 146:f64d43ff0c18 1858 #define CAN_ID_REG(base,index) ((base)->MB[index].ID)
mbed_official 146:f64d43ff0c18 1859 #define CAN_WORD0_REG(base,index) ((base)->MB[index].WORD0)
mbed_official 146:f64d43ff0c18 1860 #define CAN_WORD1_REG(base,index) ((base)->MB[index].WORD1)
mbed_official 146:f64d43ff0c18 1861 #define CAN_RXIMR_REG(base,index) ((base)->RXIMR[index])
mbed_official 146:f64d43ff0c18 1862
mbed_official 146:f64d43ff0c18 1863 /*!
mbed_official 146:f64d43ff0c18 1864 * @}
mbed_official 146:f64d43ff0c18 1865 */ /* end of group CAN_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 1866
mbed_official 146:f64d43ff0c18 1867
mbed_official 146:f64d43ff0c18 1868 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1869 -- CAN Register Masks
mbed_official 146:f64d43ff0c18 1870 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 1871
mbed_official 146:f64d43ff0c18 1872 /*!
mbed_official 146:f64d43ff0c18 1873 * @addtogroup CAN_Register_Masks CAN Register Masks
mbed_official 146:f64d43ff0c18 1874 * @{
mbed_official 146:f64d43ff0c18 1875 */
mbed_official 146:f64d43ff0c18 1876
mbed_official 146:f64d43ff0c18 1877 /* MCR Bit Fields */
mbed_official 146:f64d43ff0c18 1878 #define CAN_MCR_MAXMB_MASK 0x7Fu
mbed_official 146:f64d43ff0c18 1879 #define CAN_MCR_MAXMB_SHIFT 0
mbed_official 146:f64d43ff0c18 1880 #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
mbed_official 146:f64d43ff0c18 1881 #define CAN_MCR_IDAM_MASK 0x300u
mbed_official 146:f64d43ff0c18 1882 #define CAN_MCR_IDAM_SHIFT 8
mbed_official 146:f64d43ff0c18 1883 #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
mbed_official 146:f64d43ff0c18 1884 #define CAN_MCR_AEN_MASK 0x1000u
mbed_official 146:f64d43ff0c18 1885 #define CAN_MCR_AEN_SHIFT 12
mbed_official 146:f64d43ff0c18 1886 #define CAN_MCR_LPRIOEN_MASK 0x2000u
mbed_official 146:f64d43ff0c18 1887 #define CAN_MCR_LPRIOEN_SHIFT 13
mbed_official 146:f64d43ff0c18 1888 #define CAN_MCR_IRMQ_MASK 0x10000u
mbed_official 146:f64d43ff0c18 1889 #define CAN_MCR_IRMQ_SHIFT 16
mbed_official 146:f64d43ff0c18 1890 #define CAN_MCR_SRXDIS_MASK 0x20000u
mbed_official 146:f64d43ff0c18 1891 #define CAN_MCR_SRXDIS_SHIFT 17
mbed_official 146:f64d43ff0c18 1892 #define CAN_MCR_WAKSRC_MASK 0x80000u
mbed_official 146:f64d43ff0c18 1893 #define CAN_MCR_WAKSRC_SHIFT 19
mbed_official 146:f64d43ff0c18 1894 #define CAN_MCR_LPMACK_MASK 0x100000u
mbed_official 146:f64d43ff0c18 1895 #define CAN_MCR_LPMACK_SHIFT 20
mbed_official 146:f64d43ff0c18 1896 #define CAN_MCR_WRNEN_MASK 0x200000u
mbed_official 146:f64d43ff0c18 1897 #define CAN_MCR_WRNEN_SHIFT 21
mbed_official 146:f64d43ff0c18 1898 #define CAN_MCR_SLFWAK_MASK 0x400000u
mbed_official 146:f64d43ff0c18 1899 #define CAN_MCR_SLFWAK_SHIFT 22
mbed_official 146:f64d43ff0c18 1900 #define CAN_MCR_SUPV_MASK 0x800000u
mbed_official 146:f64d43ff0c18 1901 #define CAN_MCR_SUPV_SHIFT 23
mbed_official 146:f64d43ff0c18 1902 #define CAN_MCR_FRZACK_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 1903 #define CAN_MCR_FRZACK_SHIFT 24
mbed_official 146:f64d43ff0c18 1904 #define CAN_MCR_SOFTRST_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 1905 #define CAN_MCR_SOFTRST_SHIFT 25
mbed_official 146:f64d43ff0c18 1906 #define CAN_MCR_WAKMSK_MASK 0x4000000u
mbed_official 146:f64d43ff0c18 1907 #define CAN_MCR_WAKMSK_SHIFT 26
mbed_official 146:f64d43ff0c18 1908 #define CAN_MCR_NOTRDY_MASK 0x8000000u
mbed_official 146:f64d43ff0c18 1909 #define CAN_MCR_NOTRDY_SHIFT 27
mbed_official 146:f64d43ff0c18 1910 #define CAN_MCR_HALT_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 1911 #define CAN_MCR_HALT_SHIFT 28
mbed_official 146:f64d43ff0c18 1912 #define CAN_MCR_RFEN_MASK 0x20000000u
mbed_official 146:f64d43ff0c18 1913 #define CAN_MCR_RFEN_SHIFT 29
mbed_official 146:f64d43ff0c18 1914 #define CAN_MCR_FRZ_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 1915 #define CAN_MCR_FRZ_SHIFT 30
mbed_official 146:f64d43ff0c18 1916 #define CAN_MCR_MDIS_MASK 0x80000000u
mbed_official 146:f64d43ff0c18 1917 #define CAN_MCR_MDIS_SHIFT 31
mbed_official 146:f64d43ff0c18 1918 /* CTRL1 Bit Fields */
mbed_official 146:f64d43ff0c18 1919 #define CAN_CTRL1_PROPSEG_MASK 0x7u
mbed_official 146:f64d43ff0c18 1920 #define CAN_CTRL1_PROPSEG_SHIFT 0
mbed_official 146:f64d43ff0c18 1921 #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK)
mbed_official 146:f64d43ff0c18 1922 #define CAN_CTRL1_LOM_MASK 0x8u
mbed_official 146:f64d43ff0c18 1923 #define CAN_CTRL1_LOM_SHIFT 3
mbed_official 146:f64d43ff0c18 1924 #define CAN_CTRL1_LBUF_MASK 0x10u
mbed_official 146:f64d43ff0c18 1925 #define CAN_CTRL1_LBUF_SHIFT 4
mbed_official 146:f64d43ff0c18 1926 #define CAN_CTRL1_TSYN_MASK 0x20u
mbed_official 146:f64d43ff0c18 1927 #define CAN_CTRL1_TSYN_SHIFT 5
mbed_official 146:f64d43ff0c18 1928 #define CAN_CTRL1_BOFFREC_MASK 0x40u
mbed_official 146:f64d43ff0c18 1929 #define CAN_CTRL1_BOFFREC_SHIFT 6
mbed_official 146:f64d43ff0c18 1930 #define CAN_CTRL1_SMP_MASK 0x80u
mbed_official 146:f64d43ff0c18 1931 #define CAN_CTRL1_SMP_SHIFT 7
mbed_official 146:f64d43ff0c18 1932 #define CAN_CTRL1_RWRNMSK_MASK 0x400u
mbed_official 146:f64d43ff0c18 1933 #define CAN_CTRL1_RWRNMSK_SHIFT 10
mbed_official 146:f64d43ff0c18 1934 #define CAN_CTRL1_TWRNMSK_MASK 0x800u
mbed_official 146:f64d43ff0c18 1935 #define CAN_CTRL1_TWRNMSK_SHIFT 11
mbed_official 146:f64d43ff0c18 1936 #define CAN_CTRL1_LPB_MASK 0x1000u
mbed_official 146:f64d43ff0c18 1937 #define CAN_CTRL1_LPB_SHIFT 12
mbed_official 146:f64d43ff0c18 1938 #define CAN_CTRL1_CLKSRC_MASK 0x2000u
mbed_official 146:f64d43ff0c18 1939 #define CAN_CTRL1_CLKSRC_SHIFT 13
mbed_official 146:f64d43ff0c18 1940 #define CAN_CTRL1_ERRMSK_MASK 0x4000u
mbed_official 146:f64d43ff0c18 1941 #define CAN_CTRL1_ERRMSK_SHIFT 14
mbed_official 146:f64d43ff0c18 1942 #define CAN_CTRL1_BOFFMSK_MASK 0x8000u
mbed_official 146:f64d43ff0c18 1943 #define CAN_CTRL1_BOFFMSK_SHIFT 15
mbed_official 146:f64d43ff0c18 1944 #define CAN_CTRL1_PSEG2_MASK 0x70000u
mbed_official 146:f64d43ff0c18 1945 #define CAN_CTRL1_PSEG2_SHIFT 16
mbed_official 146:f64d43ff0c18 1946 #define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
mbed_official 146:f64d43ff0c18 1947 #define CAN_CTRL1_PSEG1_MASK 0x380000u
mbed_official 146:f64d43ff0c18 1948 #define CAN_CTRL1_PSEG1_SHIFT 19
mbed_official 146:f64d43ff0c18 1949 #define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
mbed_official 146:f64d43ff0c18 1950 #define CAN_CTRL1_RJW_MASK 0xC00000u
mbed_official 146:f64d43ff0c18 1951 #define CAN_CTRL1_RJW_SHIFT 22
mbed_official 146:f64d43ff0c18 1952 #define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
mbed_official 146:f64d43ff0c18 1953 #define CAN_CTRL1_PRESDIV_MASK 0xFF000000u
mbed_official 146:f64d43ff0c18 1954 #define CAN_CTRL1_PRESDIV_SHIFT 24
mbed_official 146:f64d43ff0c18 1955 #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
mbed_official 146:f64d43ff0c18 1956 /* TIMER Bit Fields */
mbed_official 146:f64d43ff0c18 1957 #define CAN_TIMER_TIMER_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 1958 #define CAN_TIMER_TIMER_SHIFT 0
mbed_official 146:f64d43ff0c18 1959 #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
mbed_official 146:f64d43ff0c18 1960 /* RXMGMASK Bit Fields */
mbed_official 146:f64d43ff0c18 1961 #define CAN_RXMGMASK_MG_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 1962 #define CAN_RXMGMASK_MG_SHIFT 0
mbed_official 146:f64d43ff0c18 1963 #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)
mbed_official 146:f64d43ff0c18 1964 /* RX14MASK Bit Fields */
mbed_official 146:f64d43ff0c18 1965 #define CAN_RX14MASK_RX14M_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 1966 #define CAN_RX14MASK_RX14M_SHIFT 0
mbed_official 146:f64d43ff0c18 1967 #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)
mbed_official 146:f64d43ff0c18 1968 /* RX15MASK Bit Fields */
mbed_official 146:f64d43ff0c18 1969 #define CAN_RX15MASK_RX15M_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 1970 #define CAN_RX15MASK_RX15M_SHIFT 0
mbed_official 146:f64d43ff0c18 1971 #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)
mbed_official 146:f64d43ff0c18 1972 /* ECR Bit Fields */
mbed_official 146:f64d43ff0c18 1973 #define CAN_ECR_TXERRCNT_MASK 0xFFu
mbed_official 146:f64d43ff0c18 1974 #define CAN_ECR_TXERRCNT_SHIFT 0
mbed_official 146:f64d43ff0c18 1975 #define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK)
mbed_official 146:f64d43ff0c18 1976 #define CAN_ECR_RXERRCNT_MASK 0xFF00u
mbed_official 146:f64d43ff0c18 1977 #define CAN_ECR_RXERRCNT_SHIFT 8
mbed_official 146:f64d43ff0c18 1978 #define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK)
mbed_official 146:f64d43ff0c18 1979 /* ESR1 Bit Fields */
mbed_official 146:f64d43ff0c18 1980 #define CAN_ESR1_WAKINT_MASK 0x1u
mbed_official 146:f64d43ff0c18 1981 #define CAN_ESR1_WAKINT_SHIFT 0
mbed_official 146:f64d43ff0c18 1982 #define CAN_ESR1_ERRINT_MASK 0x2u
mbed_official 146:f64d43ff0c18 1983 #define CAN_ESR1_ERRINT_SHIFT 1
mbed_official 146:f64d43ff0c18 1984 #define CAN_ESR1_BOFFINT_MASK 0x4u
mbed_official 146:f64d43ff0c18 1985 #define CAN_ESR1_BOFFINT_SHIFT 2
mbed_official 146:f64d43ff0c18 1986 #define CAN_ESR1_RX_MASK 0x8u
mbed_official 146:f64d43ff0c18 1987 #define CAN_ESR1_RX_SHIFT 3
mbed_official 146:f64d43ff0c18 1988 #define CAN_ESR1_FLTCONF_MASK 0x30u
mbed_official 146:f64d43ff0c18 1989 #define CAN_ESR1_FLTCONF_SHIFT 4
mbed_official 146:f64d43ff0c18 1990 #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)
mbed_official 146:f64d43ff0c18 1991 #define CAN_ESR1_TX_MASK 0x40u
mbed_official 146:f64d43ff0c18 1992 #define CAN_ESR1_TX_SHIFT 6
mbed_official 146:f64d43ff0c18 1993 #define CAN_ESR1_IDLE_MASK 0x80u
mbed_official 146:f64d43ff0c18 1994 #define CAN_ESR1_IDLE_SHIFT 7
mbed_official 146:f64d43ff0c18 1995 #define CAN_ESR1_RXWRN_MASK 0x100u
mbed_official 146:f64d43ff0c18 1996 #define CAN_ESR1_RXWRN_SHIFT 8
mbed_official 146:f64d43ff0c18 1997 #define CAN_ESR1_TXWRN_MASK 0x200u
mbed_official 146:f64d43ff0c18 1998 #define CAN_ESR1_TXWRN_SHIFT 9
mbed_official 146:f64d43ff0c18 1999 #define CAN_ESR1_STFERR_MASK 0x400u
mbed_official 146:f64d43ff0c18 2000 #define CAN_ESR1_STFERR_SHIFT 10
mbed_official 146:f64d43ff0c18 2001 #define CAN_ESR1_FRMERR_MASK 0x800u
mbed_official 146:f64d43ff0c18 2002 #define CAN_ESR1_FRMERR_SHIFT 11
mbed_official 146:f64d43ff0c18 2003 #define CAN_ESR1_CRCERR_MASK 0x1000u
mbed_official 146:f64d43ff0c18 2004 #define CAN_ESR1_CRCERR_SHIFT 12
mbed_official 146:f64d43ff0c18 2005 #define CAN_ESR1_ACKERR_MASK 0x2000u
mbed_official 146:f64d43ff0c18 2006 #define CAN_ESR1_ACKERR_SHIFT 13
mbed_official 146:f64d43ff0c18 2007 #define CAN_ESR1_BIT0ERR_MASK 0x4000u
mbed_official 146:f64d43ff0c18 2008 #define CAN_ESR1_BIT0ERR_SHIFT 14
mbed_official 146:f64d43ff0c18 2009 #define CAN_ESR1_BIT1ERR_MASK 0x8000u
mbed_official 146:f64d43ff0c18 2010 #define CAN_ESR1_BIT1ERR_SHIFT 15
mbed_official 146:f64d43ff0c18 2011 #define CAN_ESR1_RWRNINT_MASK 0x10000u
mbed_official 146:f64d43ff0c18 2012 #define CAN_ESR1_RWRNINT_SHIFT 16
mbed_official 146:f64d43ff0c18 2013 #define CAN_ESR1_TWRNINT_MASK 0x20000u
mbed_official 146:f64d43ff0c18 2014 #define CAN_ESR1_TWRNINT_SHIFT 17
mbed_official 146:f64d43ff0c18 2015 #define CAN_ESR1_SYNCH_MASK 0x40000u
mbed_official 146:f64d43ff0c18 2016 #define CAN_ESR1_SYNCH_SHIFT 18
mbed_official 146:f64d43ff0c18 2017 /* IMASK1 Bit Fields */
mbed_official 146:f64d43ff0c18 2018 #define CAN_IMASK1_BUFLM_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 2019 #define CAN_IMASK1_BUFLM_SHIFT 0
mbed_official 146:f64d43ff0c18 2020 #define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUFLM_SHIFT))&CAN_IMASK1_BUFLM_MASK)
mbed_official 146:f64d43ff0c18 2021 /* IFLAG1 Bit Fields */
mbed_official 146:f64d43ff0c18 2022 #define CAN_IFLAG1_BUF0I_MASK 0x1u
mbed_official 146:f64d43ff0c18 2023 #define CAN_IFLAG1_BUF0I_SHIFT 0
mbed_official 146:f64d43ff0c18 2024 #define CAN_IFLAG1_BUF4TO1I_MASK 0x1Eu
mbed_official 146:f64d43ff0c18 2025 #define CAN_IFLAG1_BUF4TO1I_SHIFT 1
mbed_official 146:f64d43ff0c18 2026 #define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO1I_SHIFT))&CAN_IFLAG1_BUF4TO1I_MASK)
mbed_official 146:f64d43ff0c18 2027 #define CAN_IFLAG1_BUF5I_MASK 0x20u
mbed_official 146:f64d43ff0c18 2028 #define CAN_IFLAG1_BUF5I_SHIFT 5
mbed_official 146:f64d43ff0c18 2029 #define CAN_IFLAG1_BUF6I_MASK 0x40u
mbed_official 146:f64d43ff0c18 2030 #define CAN_IFLAG1_BUF6I_SHIFT 6
mbed_official 146:f64d43ff0c18 2031 #define CAN_IFLAG1_BUF7I_MASK 0x80u
mbed_official 146:f64d43ff0c18 2032 #define CAN_IFLAG1_BUF7I_SHIFT 7
mbed_official 146:f64d43ff0c18 2033 #define CAN_IFLAG1_BUF31TO8I_MASK 0xFFFFFF00u
mbed_official 146:f64d43ff0c18 2034 #define CAN_IFLAG1_BUF31TO8I_SHIFT 8
mbed_official 146:f64d43ff0c18 2035 #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)
mbed_official 146:f64d43ff0c18 2036 /* CTRL2 Bit Fields */
mbed_official 146:f64d43ff0c18 2037 #define CAN_CTRL2_EACEN_MASK 0x10000u
mbed_official 146:f64d43ff0c18 2038 #define CAN_CTRL2_EACEN_SHIFT 16
mbed_official 146:f64d43ff0c18 2039 #define CAN_CTRL2_RRS_MASK 0x20000u
mbed_official 146:f64d43ff0c18 2040 #define CAN_CTRL2_RRS_SHIFT 17
mbed_official 146:f64d43ff0c18 2041 #define CAN_CTRL2_MRP_MASK 0x40000u
mbed_official 146:f64d43ff0c18 2042 #define CAN_CTRL2_MRP_SHIFT 18
mbed_official 146:f64d43ff0c18 2043 #define CAN_CTRL2_TASD_MASK 0xF80000u
mbed_official 146:f64d43ff0c18 2044 #define CAN_CTRL2_TASD_SHIFT 19
mbed_official 146:f64d43ff0c18 2045 #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
mbed_official 146:f64d43ff0c18 2046 #define CAN_CTRL2_RFFN_MASK 0xF000000u
mbed_official 146:f64d43ff0c18 2047 #define CAN_CTRL2_RFFN_SHIFT 24
mbed_official 146:f64d43ff0c18 2048 #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
mbed_official 146:f64d43ff0c18 2049 #define CAN_CTRL2_WRMFRZ_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 2050 #define CAN_CTRL2_WRMFRZ_SHIFT 28
mbed_official 146:f64d43ff0c18 2051 /* ESR2 Bit Fields */
mbed_official 146:f64d43ff0c18 2052 #define CAN_ESR2_IMB_MASK 0x2000u
mbed_official 146:f64d43ff0c18 2053 #define CAN_ESR2_IMB_SHIFT 13
mbed_official 146:f64d43ff0c18 2054 #define CAN_ESR2_VPS_MASK 0x4000u
mbed_official 146:f64d43ff0c18 2055 #define CAN_ESR2_VPS_SHIFT 14
mbed_official 146:f64d43ff0c18 2056 #define CAN_ESR2_LPTM_MASK 0x7F0000u
mbed_official 146:f64d43ff0c18 2057 #define CAN_ESR2_LPTM_SHIFT 16
mbed_official 146:f64d43ff0c18 2058 #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
mbed_official 146:f64d43ff0c18 2059 /* CRCR Bit Fields */
mbed_official 146:f64d43ff0c18 2060 #define CAN_CRCR_TXCRC_MASK 0x7FFFu
mbed_official 146:f64d43ff0c18 2061 #define CAN_CRCR_TXCRC_SHIFT 0
mbed_official 146:f64d43ff0c18 2062 #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
mbed_official 146:f64d43ff0c18 2063 #define CAN_CRCR_MBCRC_MASK 0x7F0000u
mbed_official 146:f64d43ff0c18 2064 #define CAN_CRCR_MBCRC_SHIFT 16
mbed_official 146:f64d43ff0c18 2065 #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
mbed_official 146:f64d43ff0c18 2066 /* RXFGMASK Bit Fields */
mbed_official 146:f64d43ff0c18 2067 #define CAN_RXFGMASK_FGM_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 2068 #define CAN_RXFGMASK_FGM_SHIFT 0
mbed_official 146:f64d43ff0c18 2069 #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)
mbed_official 146:f64d43ff0c18 2070 /* RXFIR Bit Fields */
mbed_official 146:f64d43ff0c18 2071 #define CAN_RXFIR_IDHIT_MASK 0x1FFu
mbed_official 146:f64d43ff0c18 2072 #define CAN_RXFIR_IDHIT_SHIFT 0
mbed_official 146:f64d43ff0c18 2073 #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
mbed_official 146:f64d43ff0c18 2074 /* CS Bit Fields */
mbed_official 146:f64d43ff0c18 2075 #define CAN_CS_TIME_STAMP_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 2076 #define CAN_CS_TIME_STAMP_SHIFT 0
mbed_official 146:f64d43ff0c18 2077 #define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_TIME_STAMP_SHIFT))&CAN_CS_TIME_STAMP_MASK)
mbed_official 146:f64d43ff0c18 2078 #define CAN_CS_DLC_MASK 0xF0000u
mbed_official 146:f64d43ff0c18 2079 #define CAN_CS_DLC_SHIFT 16
mbed_official 146:f64d43ff0c18 2080 #define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_DLC_SHIFT))&CAN_CS_DLC_MASK)
mbed_official 146:f64d43ff0c18 2081 #define CAN_CS_RTR_MASK 0x100000u
mbed_official 146:f64d43ff0c18 2082 #define CAN_CS_RTR_SHIFT 20
mbed_official 146:f64d43ff0c18 2083 #define CAN_CS_IDE_MASK 0x200000u
mbed_official 146:f64d43ff0c18 2084 #define CAN_CS_IDE_SHIFT 21
mbed_official 146:f64d43ff0c18 2085 #define CAN_CS_SRR_MASK 0x400000u
mbed_official 146:f64d43ff0c18 2086 #define CAN_CS_SRR_SHIFT 22
mbed_official 146:f64d43ff0c18 2087 #define CAN_CS_CODE_MASK 0xF000000u
mbed_official 146:f64d43ff0c18 2088 #define CAN_CS_CODE_SHIFT 24
mbed_official 146:f64d43ff0c18 2089 #define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_CODE_SHIFT))&CAN_CS_CODE_MASK)
mbed_official 146:f64d43ff0c18 2090 /* ID Bit Fields */
mbed_official 146:f64d43ff0c18 2091 #define CAN_ID_EXT_MASK 0x3FFFFu
mbed_official 146:f64d43ff0c18 2092 #define CAN_ID_EXT_SHIFT 0
mbed_official 146:f64d43ff0c18 2093 #define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK)
mbed_official 146:f64d43ff0c18 2094 #define CAN_ID_STD_MASK 0x1FFC0000u
mbed_official 146:f64d43ff0c18 2095 #define CAN_ID_STD_SHIFT 18
mbed_official 146:f64d43ff0c18 2096 #define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK)
mbed_official 146:f64d43ff0c18 2097 #define CAN_ID_PRIO_MASK 0xE0000000u
mbed_official 146:f64d43ff0c18 2098 #define CAN_ID_PRIO_SHIFT 29
mbed_official 146:f64d43ff0c18 2099 #define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_PRIO_SHIFT))&CAN_ID_PRIO_MASK)
mbed_official 146:f64d43ff0c18 2100 /* WORD0 Bit Fields */
mbed_official 146:f64d43ff0c18 2101 #define CAN_WORD0_DATA_BYTE_3_MASK 0xFFu
mbed_official 146:f64d43ff0c18 2102 #define CAN_WORD0_DATA_BYTE_3_SHIFT 0
mbed_official 146:f64d43ff0c18 2103 #define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_3_SHIFT))&CAN_WORD0_DATA_BYTE_3_MASK)
mbed_official 146:f64d43ff0c18 2104 #define CAN_WORD0_DATA_BYTE_2_MASK 0xFF00u
mbed_official 146:f64d43ff0c18 2105 #define CAN_WORD0_DATA_BYTE_2_SHIFT 8
mbed_official 146:f64d43ff0c18 2106 #define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_2_SHIFT))&CAN_WORD0_DATA_BYTE_2_MASK)
mbed_official 146:f64d43ff0c18 2107 #define CAN_WORD0_DATA_BYTE_1_MASK 0xFF0000u
mbed_official 146:f64d43ff0c18 2108 #define CAN_WORD0_DATA_BYTE_1_SHIFT 16
mbed_official 146:f64d43ff0c18 2109 #define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_1_SHIFT))&CAN_WORD0_DATA_BYTE_1_MASK)
mbed_official 146:f64d43ff0c18 2110 #define CAN_WORD0_DATA_BYTE_0_MASK 0xFF000000u
mbed_official 146:f64d43ff0c18 2111 #define CAN_WORD0_DATA_BYTE_0_SHIFT 24
mbed_official 146:f64d43ff0c18 2112 #define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_0_SHIFT))&CAN_WORD0_DATA_BYTE_0_MASK)
mbed_official 146:f64d43ff0c18 2113 /* WORD1 Bit Fields */
mbed_official 146:f64d43ff0c18 2114 #define CAN_WORD1_DATA_BYTE_7_MASK 0xFFu
mbed_official 146:f64d43ff0c18 2115 #define CAN_WORD1_DATA_BYTE_7_SHIFT 0
mbed_official 146:f64d43ff0c18 2116 #define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_7_SHIFT))&CAN_WORD1_DATA_BYTE_7_MASK)
mbed_official 146:f64d43ff0c18 2117 #define CAN_WORD1_DATA_BYTE_6_MASK 0xFF00u
mbed_official 146:f64d43ff0c18 2118 #define CAN_WORD1_DATA_BYTE_6_SHIFT 8
mbed_official 146:f64d43ff0c18 2119 #define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_6_SHIFT))&CAN_WORD1_DATA_BYTE_6_MASK)
mbed_official 146:f64d43ff0c18 2120 #define CAN_WORD1_DATA_BYTE_5_MASK 0xFF0000u
mbed_official 146:f64d43ff0c18 2121 #define CAN_WORD1_DATA_BYTE_5_SHIFT 16
mbed_official 146:f64d43ff0c18 2122 #define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_5_SHIFT))&CAN_WORD1_DATA_BYTE_5_MASK)
mbed_official 146:f64d43ff0c18 2123 #define CAN_WORD1_DATA_BYTE_4_MASK 0xFF000000u
mbed_official 146:f64d43ff0c18 2124 #define CAN_WORD1_DATA_BYTE_4_SHIFT 24
mbed_official 146:f64d43ff0c18 2125 #define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_4_SHIFT))&CAN_WORD1_DATA_BYTE_4_MASK)
mbed_official 146:f64d43ff0c18 2126 /* RXIMR Bit Fields */
mbed_official 146:f64d43ff0c18 2127 #define CAN_RXIMR_MI_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 2128 #define CAN_RXIMR_MI_SHIFT 0
mbed_official 146:f64d43ff0c18 2129 #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)
mbed_official 146:f64d43ff0c18 2130
mbed_official 146:f64d43ff0c18 2131 /*!
mbed_official 146:f64d43ff0c18 2132 * @}
mbed_official 146:f64d43ff0c18 2133 */ /* end of group CAN_Register_Masks */
mbed_official 146:f64d43ff0c18 2134
mbed_official 146:f64d43ff0c18 2135
mbed_official 146:f64d43ff0c18 2136 /* CAN - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 2137 /** Peripheral CAN0 base address */
mbed_official 146:f64d43ff0c18 2138 #define CAN0_BASE (0x40024000u)
mbed_official 146:f64d43ff0c18 2139 /** Peripheral CAN0 base pointer */
mbed_official 146:f64d43ff0c18 2140 #define CAN0 ((CAN_Type *)CAN0_BASE)
mbed_official 146:f64d43ff0c18 2141 #define CAN0_BASE_PTR (CAN0)
mbed_official 146:f64d43ff0c18 2142 /** Array initializer of CAN peripheral base pointers */
mbed_official 146:f64d43ff0c18 2143 #define CAN_BASES { CAN0 }
mbed_official 146:f64d43ff0c18 2144
mbed_official 146:f64d43ff0c18 2145 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2146 -- CAN - Register accessor macros
mbed_official 146:f64d43ff0c18 2147 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 2148
mbed_official 146:f64d43ff0c18 2149 /*!
mbed_official 146:f64d43ff0c18 2150 * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
mbed_official 146:f64d43ff0c18 2151 * @{
mbed_official 146:f64d43ff0c18 2152 */
mbed_official 146:f64d43ff0c18 2153
mbed_official 146:f64d43ff0c18 2154
mbed_official 146:f64d43ff0c18 2155 /* CAN - Register instance definitions */
mbed_official 146:f64d43ff0c18 2156 /* CAN0 */
mbed_official 146:f64d43ff0c18 2157 #define CAN0_MCR CAN_MCR_REG(CAN0)
mbed_official 146:f64d43ff0c18 2158 #define CAN0_CTRL1 CAN_CTRL1_REG(CAN0)
mbed_official 146:f64d43ff0c18 2159 #define CAN0_TIMER CAN_TIMER_REG(CAN0)
mbed_official 146:f64d43ff0c18 2160 #define CAN0_RXMGMASK CAN_RXMGMASK_REG(CAN0)
mbed_official 146:f64d43ff0c18 2161 #define CAN0_RX14MASK CAN_RX14MASK_REG(CAN0)
mbed_official 146:f64d43ff0c18 2162 #define CAN0_RX15MASK CAN_RX15MASK_REG(CAN0)
mbed_official 146:f64d43ff0c18 2163 #define CAN0_ECR CAN_ECR_REG(CAN0)
mbed_official 146:f64d43ff0c18 2164 #define CAN0_ESR1 CAN_ESR1_REG(CAN0)
mbed_official 146:f64d43ff0c18 2165 #define CAN0_IMASK1 CAN_IMASK1_REG(CAN0)
mbed_official 146:f64d43ff0c18 2166 #define CAN0_IFLAG1 CAN_IFLAG1_REG(CAN0)
mbed_official 146:f64d43ff0c18 2167 #define CAN0_CTRL2 CAN_CTRL2_REG(CAN0)
mbed_official 146:f64d43ff0c18 2168 #define CAN0_ESR2 CAN_ESR2_REG(CAN0)
mbed_official 146:f64d43ff0c18 2169 #define CAN0_CRCR CAN_CRCR_REG(CAN0)
mbed_official 146:f64d43ff0c18 2170 #define CAN0_RXFGMASK CAN_RXFGMASK_REG(CAN0)
mbed_official 146:f64d43ff0c18 2171 #define CAN0_RXFIR CAN_RXFIR_REG(CAN0)
mbed_official 146:f64d43ff0c18 2172 #define CAN0_CS0 CAN_CS_REG(CAN0,0)
mbed_official 146:f64d43ff0c18 2173 #define CAN0_ID0 CAN_ID_REG(CAN0,0)
mbed_official 146:f64d43ff0c18 2174 #define CAN0_WORD00 CAN_WORD0_REG(CAN0,0)
mbed_official 146:f64d43ff0c18 2175 #define CAN0_WORD10 CAN_WORD1_REG(CAN0,0)
mbed_official 146:f64d43ff0c18 2176 #define CAN0_CS1 CAN_CS_REG(CAN0,1)
mbed_official 146:f64d43ff0c18 2177 #define CAN0_ID1 CAN_ID_REG(CAN0,1)
mbed_official 146:f64d43ff0c18 2178 #define CAN0_WORD01 CAN_WORD0_REG(CAN0,1)
mbed_official 146:f64d43ff0c18 2179 #define CAN0_WORD11 CAN_WORD1_REG(CAN0,1)
mbed_official 146:f64d43ff0c18 2180 #define CAN0_CS2 CAN_CS_REG(CAN0,2)
mbed_official 146:f64d43ff0c18 2181 #define CAN0_ID2 CAN_ID_REG(CAN0,2)
mbed_official 146:f64d43ff0c18 2182 #define CAN0_WORD02 CAN_WORD0_REG(CAN0,2)
mbed_official 146:f64d43ff0c18 2183 #define CAN0_WORD12 CAN_WORD1_REG(CAN0,2)
mbed_official 146:f64d43ff0c18 2184 #define CAN0_CS3 CAN_CS_REG(CAN0,3)
mbed_official 146:f64d43ff0c18 2185 #define CAN0_ID3 CAN_ID_REG(CAN0,3)
mbed_official 146:f64d43ff0c18 2186 #define CAN0_WORD03 CAN_WORD0_REG(CAN0,3)
mbed_official 146:f64d43ff0c18 2187 #define CAN0_WORD13 CAN_WORD1_REG(CAN0,3)
mbed_official 146:f64d43ff0c18 2188 #define CAN0_CS4 CAN_CS_REG(CAN0,4)
mbed_official 146:f64d43ff0c18 2189 #define CAN0_ID4 CAN_ID_REG(CAN0,4)
mbed_official 146:f64d43ff0c18 2190 #define CAN0_WORD04 CAN_WORD0_REG(CAN0,4)
mbed_official 146:f64d43ff0c18 2191 #define CAN0_WORD14 CAN_WORD1_REG(CAN0,4)
mbed_official 146:f64d43ff0c18 2192 #define CAN0_CS5 CAN_CS_REG(CAN0,5)
mbed_official 146:f64d43ff0c18 2193 #define CAN0_ID5 CAN_ID_REG(CAN0,5)
mbed_official 146:f64d43ff0c18 2194 #define CAN0_WORD05 CAN_WORD0_REG(CAN0,5)
mbed_official 146:f64d43ff0c18 2195 #define CAN0_WORD15 CAN_WORD1_REG(CAN0,5)
mbed_official 146:f64d43ff0c18 2196 #define CAN0_CS6 CAN_CS_REG(CAN0,6)
mbed_official 146:f64d43ff0c18 2197 #define CAN0_ID6 CAN_ID_REG(CAN0,6)
mbed_official 146:f64d43ff0c18 2198 #define CAN0_WORD06 CAN_WORD0_REG(CAN0,6)
mbed_official 146:f64d43ff0c18 2199 #define CAN0_WORD16 CAN_WORD1_REG(CAN0,6)
mbed_official 146:f64d43ff0c18 2200 #define CAN0_CS7 CAN_CS_REG(CAN0,7)
mbed_official 146:f64d43ff0c18 2201 #define CAN0_ID7 CAN_ID_REG(CAN0,7)
mbed_official 146:f64d43ff0c18 2202 #define CAN0_WORD07 CAN_WORD0_REG(CAN0,7)
mbed_official 146:f64d43ff0c18 2203 #define CAN0_WORD17 CAN_WORD1_REG(CAN0,7)
mbed_official 146:f64d43ff0c18 2204 #define CAN0_CS8 CAN_CS_REG(CAN0,8)
mbed_official 146:f64d43ff0c18 2205 #define CAN0_ID8 CAN_ID_REG(CAN0,8)
mbed_official 146:f64d43ff0c18 2206 #define CAN0_WORD08 CAN_WORD0_REG(CAN0,8)
mbed_official 146:f64d43ff0c18 2207 #define CAN0_WORD18 CAN_WORD1_REG(CAN0,8)
mbed_official 146:f64d43ff0c18 2208 #define CAN0_CS9 CAN_CS_REG(CAN0,9)
mbed_official 146:f64d43ff0c18 2209 #define CAN0_ID9 CAN_ID_REG(CAN0,9)
mbed_official 146:f64d43ff0c18 2210 #define CAN0_WORD09 CAN_WORD0_REG(CAN0,9)
mbed_official 146:f64d43ff0c18 2211 #define CAN0_WORD19 CAN_WORD1_REG(CAN0,9)
mbed_official 146:f64d43ff0c18 2212 #define CAN0_CS10 CAN_CS_REG(CAN0,10)
mbed_official 146:f64d43ff0c18 2213 #define CAN0_ID10 CAN_ID_REG(CAN0,10)
mbed_official 146:f64d43ff0c18 2214 #define CAN0_WORD010 CAN_WORD0_REG(CAN0,10)
mbed_official 146:f64d43ff0c18 2215 #define CAN0_WORD110 CAN_WORD1_REG(CAN0,10)
mbed_official 146:f64d43ff0c18 2216 #define CAN0_CS11 CAN_CS_REG(CAN0,11)
mbed_official 146:f64d43ff0c18 2217 #define CAN0_ID11 CAN_ID_REG(CAN0,11)
mbed_official 146:f64d43ff0c18 2218 #define CAN0_WORD011 CAN_WORD0_REG(CAN0,11)
mbed_official 146:f64d43ff0c18 2219 #define CAN0_WORD111 CAN_WORD1_REG(CAN0,11)
mbed_official 146:f64d43ff0c18 2220 #define CAN0_CS12 CAN_CS_REG(CAN0,12)
mbed_official 146:f64d43ff0c18 2221 #define CAN0_ID12 CAN_ID_REG(CAN0,12)
mbed_official 146:f64d43ff0c18 2222 #define CAN0_WORD012 CAN_WORD0_REG(CAN0,12)
mbed_official 146:f64d43ff0c18 2223 #define CAN0_WORD112 CAN_WORD1_REG(CAN0,12)
mbed_official 146:f64d43ff0c18 2224 #define CAN0_CS13 CAN_CS_REG(CAN0,13)
mbed_official 146:f64d43ff0c18 2225 #define CAN0_ID13 CAN_ID_REG(CAN0,13)
mbed_official 146:f64d43ff0c18 2226 #define CAN0_WORD013 CAN_WORD0_REG(CAN0,13)
mbed_official 146:f64d43ff0c18 2227 #define CAN0_WORD113 CAN_WORD1_REG(CAN0,13)
mbed_official 146:f64d43ff0c18 2228 #define CAN0_CS14 CAN_CS_REG(CAN0,14)
mbed_official 146:f64d43ff0c18 2229 #define CAN0_ID14 CAN_ID_REG(CAN0,14)
mbed_official 146:f64d43ff0c18 2230 #define CAN0_WORD014 CAN_WORD0_REG(CAN0,14)
mbed_official 146:f64d43ff0c18 2231 #define CAN0_WORD114 CAN_WORD1_REG(CAN0,14)
mbed_official 146:f64d43ff0c18 2232 #define CAN0_CS15 CAN_CS_REG(CAN0,15)
mbed_official 146:f64d43ff0c18 2233 #define CAN0_ID15 CAN_ID_REG(CAN0,15)
mbed_official 146:f64d43ff0c18 2234 #define CAN0_WORD015 CAN_WORD0_REG(CAN0,15)
mbed_official 146:f64d43ff0c18 2235 #define CAN0_WORD115 CAN_WORD1_REG(CAN0,15)
mbed_official 146:f64d43ff0c18 2236 #define CAN0_RXIMR0 CAN_RXIMR_REG(CAN0,0)
mbed_official 146:f64d43ff0c18 2237 #define CAN0_RXIMR1 CAN_RXIMR_REG(CAN0,1)
mbed_official 146:f64d43ff0c18 2238 #define CAN0_RXIMR2 CAN_RXIMR_REG(CAN0,2)
mbed_official 146:f64d43ff0c18 2239 #define CAN0_RXIMR3 CAN_RXIMR_REG(CAN0,3)
mbed_official 146:f64d43ff0c18 2240 #define CAN0_RXIMR4 CAN_RXIMR_REG(CAN0,4)
mbed_official 146:f64d43ff0c18 2241 #define CAN0_RXIMR5 CAN_RXIMR_REG(CAN0,5)
mbed_official 146:f64d43ff0c18 2242 #define CAN0_RXIMR6 CAN_RXIMR_REG(CAN0,6)
mbed_official 146:f64d43ff0c18 2243 #define CAN0_RXIMR7 CAN_RXIMR_REG(CAN0,7)
mbed_official 146:f64d43ff0c18 2244 #define CAN0_RXIMR8 CAN_RXIMR_REG(CAN0,8)
mbed_official 146:f64d43ff0c18 2245 #define CAN0_RXIMR9 CAN_RXIMR_REG(CAN0,9)
mbed_official 146:f64d43ff0c18 2246 #define CAN0_RXIMR10 CAN_RXIMR_REG(CAN0,10)
mbed_official 146:f64d43ff0c18 2247 #define CAN0_RXIMR11 CAN_RXIMR_REG(CAN0,11)
mbed_official 146:f64d43ff0c18 2248 #define CAN0_RXIMR12 CAN_RXIMR_REG(CAN0,12)
mbed_official 146:f64d43ff0c18 2249 #define CAN0_RXIMR13 CAN_RXIMR_REG(CAN0,13)
mbed_official 146:f64d43ff0c18 2250 #define CAN0_RXIMR14 CAN_RXIMR_REG(CAN0,14)
mbed_official 146:f64d43ff0c18 2251 #define CAN0_RXIMR15 CAN_RXIMR_REG(CAN0,15)
mbed_official 146:f64d43ff0c18 2252
mbed_official 146:f64d43ff0c18 2253 /* CAN - Register array accessors */
mbed_official 146:f64d43ff0c18 2254 #define CAN0_CS(index) CAN_CS_REG(CAN0,index)
mbed_official 146:f64d43ff0c18 2255 #define CAN0_ID(index) CAN_ID_REG(CAN0,index)
mbed_official 146:f64d43ff0c18 2256 #define CAN0_WORD0(index) CAN_WORD0_REG(CAN0,index)
mbed_official 146:f64d43ff0c18 2257 #define CAN0_WORD1(index) CAN_WORD1_REG(CAN0,index)
mbed_official 146:f64d43ff0c18 2258 #define CAN0_RXIMR(index) CAN_RXIMR_REG(CAN0,index)
mbed_official 146:f64d43ff0c18 2259
mbed_official 146:f64d43ff0c18 2260 /*!
mbed_official 146:f64d43ff0c18 2261 * @}
mbed_official 146:f64d43ff0c18 2262 */ /* end of group CAN_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 2263
mbed_official 146:f64d43ff0c18 2264
mbed_official 146:f64d43ff0c18 2265 /*!
mbed_official 146:f64d43ff0c18 2266 * @}
mbed_official 146:f64d43ff0c18 2267 */ /* end of group CAN_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 2268
mbed_official 146:f64d43ff0c18 2269
mbed_official 146:f64d43ff0c18 2270 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2271 -- CAU Peripheral Access Layer
mbed_official 146:f64d43ff0c18 2272 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 2273
mbed_official 146:f64d43ff0c18 2274 /*!
mbed_official 146:f64d43ff0c18 2275 * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
mbed_official 146:f64d43ff0c18 2276 * @{
mbed_official 146:f64d43ff0c18 2277 */
mbed_official 146:f64d43ff0c18 2278
mbed_official 146:f64d43ff0c18 2279 /** CAU - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 2280 typedef struct {
mbed_official 146:f64d43ff0c18 2281 __O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
mbed_official 146:f64d43ff0c18 2282 uint8_t RESERVED_0[2048];
mbed_official 146:f64d43ff0c18 2283 __O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */
mbed_official 146:f64d43ff0c18 2284 __O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */
mbed_official 146:f64d43ff0c18 2285 __O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
mbed_official 146:f64d43ff0c18 2286 uint8_t RESERVED_1[20];
mbed_official 146:f64d43ff0c18 2287 __I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */
mbed_official 146:f64d43ff0c18 2288 __I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */
mbed_official 146:f64d43ff0c18 2289 __I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
mbed_official 146:f64d43ff0c18 2290 uint8_t RESERVED_2[20];
mbed_official 146:f64d43ff0c18 2291 __O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */
mbed_official 146:f64d43ff0c18 2292 __O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */
mbed_official 146:f64d43ff0c18 2293 __O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
mbed_official 146:f64d43ff0c18 2294 uint8_t RESERVED_3[20];
mbed_official 146:f64d43ff0c18 2295 __O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */
mbed_official 146:f64d43ff0c18 2296 __O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
mbed_official 146:f64d43ff0c18 2297 __O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
mbed_official 146:f64d43ff0c18 2298 uint8_t RESERVED_4[84];
mbed_official 146:f64d43ff0c18 2299 __O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */
mbed_official 146:f64d43ff0c18 2300 __O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */
mbed_official 146:f64d43ff0c18 2301 __O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
mbed_official 146:f64d43ff0c18 2302 uint8_t RESERVED_5[20];
mbed_official 146:f64d43ff0c18 2303 __O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */
mbed_official 146:f64d43ff0c18 2304 __O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
mbed_official 146:f64d43ff0c18 2305 __O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
mbed_official 146:f64d43ff0c18 2306 uint8_t RESERVED_6[276];
mbed_official 146:f64d43ff0c18 2307 __O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */
mbed_official 146:f64d43ff0c18 2308 __O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
mbed_official 146:f64d43ff0c18 2309 __O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
mbed_official 146:f64d43ff0c18 2310 uint8_t RESERVED_7[20];
mbed_official 146:f64d43ff0c18 2311 __O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
mbed_official 146:f64d43ff0c18 2312 __O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
mbed_official 146:f64d43ff0c18 2313 __O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
mbed_official 146:f64d43ff0c18 2314 } CAU_Type, *CAU_MemMapPtr;
mbed_official 146:f64d43ff0c18 2315
mbed_official 146:f64d43ff0c18 2316 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2317 -- CAU - Register accessor macros
mbed_official 146:f64d43ff0c18 2318 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 2319
mbed_official 146:f64d43ff0c18 2320 /*!
mbed_official 146:f64d43ff0c18 2321 * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
mbed_official 146:f64d43ff0c18 2322 * @{
mbed_official 146:f64d43ff0c18 2323 */
mbed_official 146:f64d43ff0c18 2324
mbed_official 146:f64d43ff0c18 2325
mbed_official 146:f64d43ff0c18 2326 /* CAU - Register accessors */
mbed_official 146:f64d43ff0c18 2327 #define CAU_DIRECT_REG(base,index) ((base)->DIRECT[index])
mbed_official 146:f64d43ff0c18 2328 #define CAU_LDR_CASR_REG(base) ((base)->LDR_CASR)
mbed_official 146:f64d43ff0c18 2329 #define CAU_LDR_CAA_REG(base) ((base)->LDR_CAA)
mbed_official 146:f64d43ff0c18 2330 #define CAU_LDR_CA_REG(base,index) ((base)->LDR_CA[index])
mbed_official 146:f64d43ff0c18 2331 #define CAU_STR_CASR_REG(base) ((base)->STR_CASR)
mbed_official 146:f64d43ff0c18 2332 #define CAU_STR_CAA_REG(base) ((base)->STR_CAA)
mbed_official 146:f64d43ff0c18 2333 #define CAU_STR_CA_REG(base,index) ((base)->STR_CA[index])
mbed_official 146:f64d43ff0c18 2334 #define CAU_ADR_CASR_REG(base) ((base)->ADR_CASR)
mbed_official 146:f64d43ff0c18 2335 #define CAU_ADR_CAA_REG(base) ((base)->ADR_CAA)
mbed_official 146:f64d43ff0c18 2336 #define CAU_ADR_CA_REG(base,index) ((base)->ADR_CA[index])
mbed_official 146:f64d43ff0c18 2337 #define CAU_RADR_CASR_REG(base) ((base)->RADR_CASR)
mbed_official 146:f64d43ff0c18 2338 #define CAU_RADR_CAA_REG(base) ((base)->RADR_CAA)
mbed_official 146:f64d43ff0c18 2339 #define CAU_RADR_CA_REG(base,index) ((base)->RADR_CA[index])
mbed_official 146:f64d43ff0c18 2340 #define CAU_XOR_CASR_REG(base) ((base)->XOR_CASR)
mbed_official 146:f64d43ff0c18 2341 #define CAU_XOR_CAA_REG(base) ((base)->XOR_CAA)
mbed_official 146:f64d43ff0c18 2342 #define CAU_XOR_CA_REG(base,index) ((base)->XOR_CA[index])
mbed_official 146:f64d43ff0c18 2343 #define CAU_ROTL_CASR_REG(base) ((base)->ROTL_CASR)
mbed_official 146:f64d43ff0c18 2344 #define CAU_ROTL_CAA_REG(base) ((base)->ROTL_CAA)
mbed_official 146:f64d43ff0c18 2345 #define CAU_ROTL_CA_REG(base,index) ((base)->ROTL_CA[index])
mbed_official 146:f64d43ff0c18 2346 #define CAU_AESC_CASR_REG(base) ((base)->AESC_CASR)
mbed_official 146:f64d43ff0c18 2347 #define CAU_AESC_CAA_REG(base) ((base)->AESC_CAA)
mbed_official 146:f64d43ff0c18 2348 #define CAU_AESC_CA_REG(base,index) ((base)->AESC_CA[index])
mbed_official 146:f64d43ff0c18 2349 #define CAU_AESIC_CASR_REG(base) ((base)->AESIC_CASR)
mbed_official 146:f64d43ff0c18 2350 #define CAU_AESIC_CAA_REG(base) ((base)->AESIC_CAA)
mbed_official 146:f64d43ff0c18 2351 #define CAU_AESIC_CA_REG(base,index) ((base)->AESIC_CA[index])
mbed_official 146:f64d43ff0c18 2352
mbed_official 146:f64d43ff0c18 2353 /*!
mbed_official 146:f64d43ff0c18 2354 * @}
mbed_official 146:f64d43ff0c18 2355 */ /* end of group CAU_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 2356
mbed_official 146:f64d43ff0c18 2357
mbed_official 146:f64d43ff0c18 2358 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2359 -- CAU Register Masks
mbed_official 146:f64d43ff0c18 2360 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 2361
mbed_official 146:f64d43ff0c18 2362 /*!
mbed_official 146:f64d43ff0c18 2363 * @addtogroup CAU_Register_Masks CAU Register Masks
mbed_official 146:f64d43ff0c18 2364 * @{
mbed_official 146:f64d43ff0c18 2365 */
mbed_official 146:f64d43ff0c18 2366
mbed_official 146:f64d43ff0c18 2367 /* LDR_CASR Bit Fields */
mbed_official 146:f64d43ff0c18 2368 #define CAU_LDR_CASR_IC_MASK 0x1u
mbed_official 146:f64d43ff0c18 2369 #define CAU_LDR_CASR_IC_SHIFT 0
mbed_official 146:f64d43ff0c18 2370 #define CAU_LDR_CASR_DPE_MASK 0x2u
mbed_official 146:f64d43ff0c18 2371 #define CAU_LDR_CASR_DPE_SHIFT 1
mbed_official 146:f64d43ff0c18 2372 #define CAU_LDR_CASR_VER_MASK 0xF0000000u
mbed_official 146:f64d43ff0c18 2373 #define CAU_LDR_CASR_VER_SHIFT 28
mbed_official 146:f64d43ff0c18 2374 #define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_VER_SHIFT))&CAU_LDR_CASR_VER_MASK)
mbed_official 146:f64d43ff0c18 2375 /* STR_CASR Bit Fields */
mbed_official 146:f64d43ff0c18 2376 #define CAU_STR_CASR_IC_MASK 0x1u
mbed_official 146:f64d43ff0c18 2377 #define CAU_STR_CASR_IC_SHIFT 0
mbed_official 146:f64d43ff0c18 2378 #define CAU_STR_CASR_DPE_MASK 0x2u
mbed_official 146:f64d43ff0c18 2379 #define CAU_STR_CASR_DPE_SHIFT 1
mbed_official 146:f64d43ff0c18 2380 #define CAU_STR_CASR_VER_MASK 0xF0000000u
mbed_official 146:f64d43ff0c18 2381 #define CAU_STR_CASR_VER_SHIFT 28
mbed_official 146:f64d43ff0c18 2382 #define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_VER_SHIFT))&CAU_STR_CASR_VER_MASK)
mbed_official 146:f64d43ff0c18 2383 /* ADR_CASR Bit Fields */
mbed_official 146:f64d43ff0c18 2384 #define CAU_ADR_CASR_IC_MASK 0x1u
mbed_official 146:f64d43ff0c18 2385 #define CAU_ADR_CASR_IC_SHIFT 0
mbed_official 146:f64d43ff0c18 2386 #define CAU_ADR_CASR_DPE_MASK 0x2u
mbed_official 146:f64d43ff0c18 2387 #define CAU_ADR_CASR_DPE_SHIFT 1
mbed_official 146:f64d43ff0c18 2388 #define CAU_ADR_CASR_VER_MASK 0xF0000000u
mbed_official 146:f64d43ff0c18 2389 #define CAU_ADR_CASR_VER_SHIFT 28
mbed_official 146:f64d43ff0c18 2390 #define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_VER_SHIFT))&CAU_ADR_CASR_VER_MASK)
mbed_official 146:f64d43ff0c18 2391 /* RADR_CASR Bit Fields */
mbed_official 146:f64d43ff0c18 2392 #define CAU_RADR_CASR_IC_MASK 0x1u
mbed_official 146:f64d43ff0c18 2393 #define CAU_RADR_CASR_IC_SHIFT 0
mbed_official 146:f64d43ff0c18 2394 #define CAU_RADR_CASR_DPE_MASK 0x2u
mbed_official 146:f64d43ff0c18 2395 #define CAU_RADR_CASR_DPE_SHIFT 1
mbed_official 146:f64d43ff0c18 2396 #define CAU_RADR_CASR_VER_MASK 0xF0000000u
mbed_official 146:f64d43ff0c18 2397 #define CAU_RADR_CASR_VER_SHIFT 28
mbed_official 146:f64d43ff0c18 2398 #define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_VER_SHIFT))&CAU_RADR_CASR_VER_MASK)
mbed_official 146:f64d43ff0c18 2399 /* XOR_CASR Bit Fields */
mbed_official 146:f64d43ff0c18 2400 #define CAU_XOR_CASR_IC_MASK 0x1u
mbed_official 146:f64d43ff0c18 2401 #define CAU_XOR_CASR_IC_SHIFT 0
mbed_official 146:f64d43ff0c18 2402 #define CAU_XOR_CASR_DPE_MASK 0x2u
mbed_official 146:f64d43ff0c18 2403 #define CAU_XOR_CASR_DPE_SHIFT 1
mbed_official 146:f64d43ff0c18 2404 #define CAU_XOR_CASR_VER_MASK 0xF0000000u
mbed_official 146:f64d43ff0c18 2405 #define CAU_XOR_CASR_VER_SHIFT 28
mbed_official 146:f64d43ff0c18 2406 #define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_VER_SHIFT))&CAU_XOR_CASR_VER_MASK)
mbed_official 146:f64d43ff0c18 2407 /* ROTL_CASR Bit Fields */
mbed_official 146:f64d43ff0c18 2408 #define CAU_ROTL_CASR_IC_MASK 0x1u
mbed_official 146:f64d43ff0c18 2409 #define CAU_ROTL_CASR_IC_SHIFT 0
mbed_official 146:f64d43ff0c18 2410 #define CAU_ROTL_CASR_DPE_MASK 0x2u
mbed_official 146:f64d43ff0c18 2411 #define CAU_ROTL_CASR_DPE_SHIFT 1
mbed_official 146:f64d43ff0c18 2412 #define CAU_ROTL_CASR_VER_MASK 0xF0000000u
mbed_official 146:f64d43ff0c18 2413 #define CAU_ROTL_CASR_VER_SHIFT 28
mbed_official 146:f64d43ff0c18 2414 #define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_VER_SHIFT))&CAU_ROTL_CASR_VER_MASK)
mbed_official 146:f64d43ff0c18 2415 /* AESC_CASR Bit Fields */
mbed_official 146:f64d43ff0c18 2416 #define CAU_AESC_CASR_IC_MASK 0x1u
mbed_official 146:f64d43ff0c18 2417 #define CAU_AESC_CASR_IC_SHIFT 0
mbed_official 146:f64d43ff0c18 2418 #define CAU_AESC_CASR_DPE_MASK 0x2u
mbed_official 146:f64d43ff0c18 2419 #define CAU_AESC_CASR_DPE_SHIFT 1
mbed_official 146:f64d43ff0c18 2420 #define CAU_AESC_CASR_VER_MASK 0xF0000000u
mbed_official 146:f64d43ff0c18 2421 #define CAU_AESC_CASR_VER_SHIFT 28
mbed_official 146:f64d43ff0c18 2422 #define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_VER_SHIFT))&CAU_AESC_CASR_VER_MASK)
mbed_official 146:f64d43ff0c18 2423 /* AESIC_CASR Bit Fields */
mbed_official 146:f64d43ff0c18 2424 #define CAU_AESIC_CASR_IC_MASK 0x1u
mbed_official 146:f64d43ff0c18 2425 #define CAU_AESIC_CASR_IC_SHIFT 0
mbed_official 146:f64d43ff0c18 2426 #define CAU_AESIC_CASR_DPE_MASK 0x2u
mbed_official 146:f64d43ff0c18 2427 #define CAU_AESIC_CASR_DPE_SHIFT 1
mbed_official 146:f64d43ff0c18 2428 #define CAU_AESIC_CASR_VER_MASK 0xF0000000u
mbed_official 146:f64d43ff0c18 2429 #define CAU_AESIC_CASR_VER_SHIFT 28
mbed_official 146:f64d43ff0c18 2430 #define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_VER_SHIFT))&CAU_AESIC_CASR_VER_MASK)
mbed_official 146:f64d43ff0c18 2431
mbed_official 146:f64d43ff0c18 2432 /*!
mbed_official 146:f64d43ff0c18 2433 * @}
mbed_official 146:f64d43ff0c18 2434 */ /* end of group CAU_Register_Masks */
mbed_official 146:f64d43ff0c18 2435
mbed_official 146:f64d43ff0c18 2436
mbed_official 146:f64d43ff0c18 2437 /* CAU - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 2438 /** Peripheral CAU base address */
mbed_official 146:f64d43ff0c18 2439 #define CAU_BASE (0xE0081000u)
mbed_official 146:f64d43ff0c18 2440 /** Peripheral CAU base pointer */
mbed_official 146:f64d43ff0c18 2441 #define CAU ((CAU_Type *)CAU_BASE)
mbed_official 146:f64d43ff0c18 2442 #define CAU_BASE_PTR (CAU)
mbed_official 146:f64d43ff0c18 2443 /** Array initializer of CAU peripheral base pointers */
mbed_official 146:f64d43ff0c18 2444 #define CAU_BASES { CAU }
mbed_official 146:f64d43ff0c18 2445
mbed_official 146:f64d43ff0c18 2446 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2447 -- CAU - Register accessor macros
mbed_official 146:f64d43ff0c18 2448 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 2449
mbed_official 146:f64d43ff0c18 2450 /*!
mbed_official 146:f64d43ff0c18 2451 * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
mbed_official 146:f64d43ff0c18 2452 * @{
mbed_official 146:f64d43ff0c18 2453 */
mbed_official 146:f64d43ff0c18 2454
mbed_official 146:f64d43ff0c18 2455
mbed_official 146:f64d43ff0c18 2456 /* CAU - Register instance definitions */
mbed_official 146:f64d43ff0c18 2457 /* CAU */
mbed_official 146:f64d43ff0c18 2458 #define CAU_DIRECT0 CAU_DIRECT_REG(CAU,0)
mbed_official 146:f64d43ff0c18 2459 #define CAU_DIRECT1 CAU_DIRECT_REG(CAU,1)
mbed_official 146:f64d43ff0c18 2460 #define CAU_DIRECT2 CAU_DIRECT_REG(CAU,2)
mbed_official 146:f64d43ff0c18 2461 #define CAU_DIRECT3 CAU_DIRECT_REG(CAU,3)
mbed_official 146:f64d43ff0c18 2462 #define CAU_DIRECT4 CAU_DIRECT_REG(CAU,4)
mbed_official 146:f64d43ff0c18 2463 #define CAU_DIRECT5 CAU_DIRECT_REG(CAU,5)
mbed_official 146:f64d43ff0c18 2464 #define CAU_DIRECT6 CAU_DIRECT_REG(CAU,6)
mbed_official 146:f64d43ff0c18 2465 #define CAU_DIRECT7 CAU_DIRECT_REG(CAU,7)
mbed_official 146:f64d43ff0c18 2466 #define CAU_DIRECT8 CAU_DIRECT_REG(CAU,8)
mbed_official 146:f64d43ff0c18 2467 #define CAU_DIRECT9 CAU_DIRECT_REG(CAU,9)
mbed_official 146:f64d43ff0c18 2468 #define CAU_DIRECT10 CAU_DIRECT_REG(CAU,10)
mbed_official 146:f64d43ff0c18 2469 #define CAU_DIRECT11 CAU_DIRECT_REG(CAU,11)
mbed_official 146:f64d43ff0c18 2470 #define CAU_DIRECT12 CAU_DIRECT_REG(CAU,12)
mbed_official 146:f64d43ff0c18 2471 #define CAU_DIRECT13 CAU_DIRECT_REG(CAU,13)
mbed_official 146:f64d43ff0c18 2472 #define CAU_DIRECT14 CAU_DIRECT_REG(CAU,14)
mbed_official 146:f64d43ff0c18 2473 #define CAU_DIRECT15 CAU_DIRECT_REG(CAU,15)
mbed_official 146:f64d43ff0c18 2474 #define CAU_LDR_CASR CAU_LDR_CASR_REG(CAU)
mbed_official 146:f64d43ff0c18 2475 #define CAU_LDR_CAA CAU_LDR_CAA_REG(CAU)
mbed_official 146:f64d43ff0c18 2476 #define CAU_LDR_CA0 CAU_LDR_CA_REG(CAU,0)
mbed_official 146:f64d43ff0c18 2477 #define CAU_LDR_CA1 CAU_LDR_CA_REG(CAU,1)
mbed_official 146:f64d43ff0c18 2478 #define CAU_LDR_CA2 CAU_LDR_CA_REG(CAU,2)
mbed_official 146:f64d43ff0c18 2479 #define CAU_LDR_CA3 CAU_LDR_CA_REG(CAU,3)
mbed_official 146:f64d43ff0c18 2480 #define CAU_LDR_CA4 CAU_LDR_CA_REG(CAU,4)
mbed_official 146:f64d43ff0c18 2481 #define CAU_LDR_CA5 CAU_LDR_CA_REG(CAU,5)
mbed_official 146:f64d43ff0c18 2482 #define CAU_LDR_CA6 CAU_LDR_CA_REG(CAU,6)
mbed_official 146:f64d43ff0c18 2483 #define CAU_LDR_CA7 CAU_LDR_CA_REG(CAU,7)
mbed_official 146:f64d43ff0c18 2484 #define CAU_LDR_CA8 CAU_LDR_CA_REG(CAU,8)
mbed_official 146:f64d43ff0c18 2485 #define CAU_STR_CASR CAU_STR_CASR_REG(CAU)
mbed_official 146:f64d43ff0c18 2486 #define CAU_STR_CAA CAU_STR_CAA_REG(CAU)
mbed_official 146:f64d43ff0c18 2487 #define CAU_STR_CA0 CAU_STR_CA_REG(CAU,0)
mbed_official 146:f64d43ff0c18 2488 #define CAU_STR_CA1 CAU_STR_CA_REG(CAU,1)
mbed_official 146:f64d43ff0c18 2489 #define CAU_STR_CA2 CAU_STR_CA_REG(CAU,2)
mbed_official 146:f64d43ff0c18 2490 #define CAU_STR_CA3 CAU_STR_CA_REG(CAU,3)
mbed_official 146:f64d43ff0c18 2491 #define CAU_STR_CA4 CAU_STR_CA_REG(CAU,4)
mbed_official 146:f64d43ff0c18 2492 #define CAU_STR_CA5 CAU_STR_CA_REG(CAU,5)
mbed_official 146:f64d43ff0c18 2493 #define CAU_STR_CA6 CAU_STR_CA_REG(CAU,6)
mbed_official 146:f64d43ff0c18 2494 #define CAU_STR_CA7 CAU_STR_CA_REG(CAU,7)
mbed_official 146:f64d43ff0c18 2495 #define CAU_STR_CA8 CAU_STR_CA_REG(CAU,8)
mbed_official 146:f64d43ff0c18 2496 #define CAU_ADR_CASR CAU_ADR_CASR_REG(CAU)
mbed_official 146:f64d43ff0c18 2497 #define CAU_ADR_CAA CAU_ADR_CAA_REG(CAU)
mbed_official 146:f64d43ff0c18 2498 #define CAU_ADR_CA0 CAU_ADR_CA_REG(CAU,0)
mbed_official 146:f64d43ff0c18 2499 #define CAU_ADR_CA1 CAU_ADR_CA_REG(CAU,1)
mbed_official 146:f64d43ff0c18 2500 #define CAU_ADR_CA2 CAU_ADR_CA_REG(CAU,2)
mbed_official 146:f64d43ff0c18 2501 #define CAU_ADR_CA3 CAU_ADR_CA_REG(CAU,3)
mbed_official 146:f64d43ff0c18 2502 #define CAU_ADR_CA4 CAU_ADR_CA_REG(CAU,4)
mbed_official 146:f64d43ff0c18 2503 #define CAU_ADR_CA5 CAU_ADR_CA_REG(CAU,5)
mbed_official 146:f64d43ff0c18 2504 #define CAU_ADR_CA6 CAU_ADR_CA_REG(CAU,6)
mbed_official 146:f64d43ff0c18 2505 #define CAU_ADR_CA7 CAU_ADR_CA_REG(CAU,7)
mbed_official 146:f64d43ff0c18 2506 #define CAU_ADR_CA8 CAU_ADR_CA_REG(CAU,8)
mbed_official 146:f64d43ff0c18 2507 #define CAU_RADR_CASR CAU_RADR_CASR_REG(CAU)
mbed_official 146:f64d43ff0c18 2508 #define CAU_RADR_CAA CAU_RADR_CAA_REG(CAU)
mbed_official 146:f64d43ff0c18 2509 #define CAU_RADR_CA0 CAU_RADR_CA_REG(CAU,0)
mbed_official 146:f64d43ff0c18 2510 #define CAU_RADR_CA1 CAU_RADR_CA_REG(CAU,1)
mbed_official 146:f64d43ff0c18 2511 #define CAU_RADR_CA2 CAU_RADR_CA_REG(CAU,2)
mbed_official 146:f64d43ff0c18 2512 #define CAU_RADR_CA3 CAU_RADR_CA_REG(CAU,3)
mbed_official 146:f64d43ff0c18 2513 #define CAU_RADR_CA4 CAU_RADR_CA_REG(CAU,4)
mbed_official 146:f64d43ff0c18 2514 #define CAU_RADR_CA5 CAU_RADR_CA_REG(CAU,5)
mbed_official 146:f64d43ff0c18 2515 #define CAU_RADR_CA6 CAU_RADR_CA_REG(CAU,6)
mbed_official 146:f64d43ff0c18 2516 #define CAU_RADR_CA7 CAU_RADR_CA_REG(CAU,7)
mbed_official 146:f64d43ff0c18 2517 #define CAU_RADR_CA8 CAU_RADR_CA_REG(CAU,8)
mbed_official 146:f64d43ff0c18 2518 #define CAU_XOR_CASR CAU_XOR_CASR_REG(CAU)
mbed_official 146:f64d43ff0c18 2519 #define CAU_XOR_CAA CAU_XOR_CAA_REG(CAU)
mbed_official 146:f64d43ff0c18 2520 #define CAU_XOR_CA0 CAU_XOR_CA_REG(CAU,0)
mbed_official 146:f64d43ff0c18 2521 #define CAU_XOR_CA1 CAU_XOR_CA_REG(CAU,1)
mbed_official 146:f64d43ff0c18 2522 #define CAU_XOR_CA2 CAU_XOR_CA_REG(CAU,2)
mbed_official 146:f64d43ff0c18 2523 #define CAU_XOR_CA3 CAU_XOR_CA_REG(CAU,3)
mbed_official 146:f64d43ff0c18 2524 #define CAU_XOR_CA4 CAU_XOR_CA_REG(CAU,4)
mbed_official 146:f64d43ff0c18 2525 #define CAU_XOR_CA5 CAU_XOR_CA_REG(CAU,5)
mbed_official 146:f64d43ff0c18 2526 #define CAU_XOR_CA6 CAU_XOR_CA_REG(CAU,6)
mbed_official 146:f64d43ff0c18 2527 #define CAU_XOR_CA7 CAU_XOR_CA_REG(CAU,7)
mbed_official 146:f64d43ff0c18 2528 #define CAU_XOR_CA8 CAU_XOR_CA_REG(CAU,8)
mbed_official 146:f64d43ff0c18 2529 #define CAU_ROTL_CASR CAU_ROTL_CASR_REG(CAU)
mbed_official 146:f64d43ff0c18 2530 #define CAU_ROTL_CAA CAU_ROTL_CAA_REG(CAU)
mbed_official 146:f64d43ff0c18 2531 #define CAU_ROTL_CA0 CAU_ROTL_CA_REG(CAU,0)
mbed_official 146:f64d43ff0c18 2532 #define CAU_ROTL_CA1 CAU_ROTL_CA_REG(CAU,1)
mbed_official 146:f64d43ff0c18 2533 #define CAU_ROTL_CA2 CAU_ROTL_CA_REG(CAU,2)
mbed_official 146:f64d43ff0c18 2534 #define CAU_ROTL_CA3 CAU_ROTL_CA_REG(CAU,3)
mbed_official 146:f64d43ff0c18 2535 #define CAU_ROTL_CA4 CAU_ROTL_CA_REG(CAU,4)
mbed_official 146:f64d43ff0c18 2536 #define CAU_ROTL_CA5 CAU_ROTL_CA_REG(CAU,5)
mbed_official 146:f64d43ff0c18 2537 #define CAU_ROTL_CA6 CAU_ROTL_CA_REG(CAU,6)
mbed_official 146:f64d43ff0c18 2538 #define CAU_ROTL_CA7 CAU_ROTL_CA_REG(CAU,7)
mbed_official 146:f64d43ff0c18 2539 #define CAU_ROTL_CA8 CAU_ROTL_CA_REG(CAU,8)
mbed_official 146:f64d43ff0c18 2540 #define CAU_AESC_CASR CAU_AESC_CASR_REG(CAU)
mbed_official 146:f64d43ff0c18 2541 #define CAU_AESC_CAA CAU_AESC_CAA_REG(CAU)
mbed_official 146:f64d43ff0c18 2542 #define CAU_AESC_CA0 CAU_AESC_CA_REG(CAU,0)
mbed_official 146:f64d43ff0c18 2543 #define CAU_AESC_CA1 CAU_AESC_CA_REG(CAU,1)
mbed_official 146:f64d43ff0c18 2544 #define CAU_AESC_CA2 CAU_AESC_CA_REG(CAU,2)
mbed_official 146:f64d43ff0c18 2545 #define CAU_AESC_CA3 CAU_AESC_CA_REG(CAU,3)
mbed_official 146:f64d43ff0c18 2546 #define CAU_AESC_CA4 CAU_AESC_CA_REG(CAU,4)
mbed_official 146:f64d43ff0c18 2547 #define CAU_AESC_CA5 CAU_AESC_CA_REG(CAU,5)
mbed_official 146:f64d43ff0c18 2548 #define CAU_AESC_CA6 CAU_AESC_CA_REG(CAU,6)
mbed_official 146:f64d43ff0c18 2549 #define CAU_AESC_CA7 CAU_AESC_CA_REG(CAU,7)
mbed_official 146:f64d43ff0c18 2550 #define CAU_AESC_CA8 CAU_AESC_CA_REG(CAU,8)
mbed_official 146:f64d43ff0c18 2551 #define CAU_AESIC_CASR CAU_AESIC_CASR_REG(CAU)
mbed_official 146:f64d43ff0c18 2552 #define CAU_AESIC_CAA CAU_AESIC_CAA_REG(CAU)
mbed_official 146:f64d43ff0c18 2553 #define CAU_AESIC_CA0 CAU_AESIC_CA_REG(CAU,0)
mbed_official 146:f64d43ff0c18 2554 #define CAU_AESIC_CA1 CAU_AESIC_CA_REG(CAU,1)
mbed_official 146:f64d43ff0c18 2555 #define CAU_AESIC_CA2 CAU_AESIC_CA_REG(CAU,2)
mbed_official 146:f64d43ff0c18 2556 #define CAU_AESIC_CA3 CAU_AESIC_CA_REG(CAU,3)
mbed_official 146:f64d43ff0c18 2557 #define CAU_AESIC_CA4 CAU_AESIC_CA_REG(CAU,4)
mbed_official 146:f64d43ff0c18 2558 #define CAU_AESIC_CA5 CAU_AESIC_CA_REG(CAU,5)
mbed_official 146:f64d43ff0c18 2559 #define CAU_AESIC_CA6 CAU_AESIC_CA_REG(CAU,6)
mbed_official 146:f64d43ff0c18 2560 #define CAU_AESIC_CA7 CAU_AESIC_CA_REG(CAU,7)
mbed_official 146:f64d43ff0c18 2561 #define CAU_AESIC_CA8 CAU_AESIC_CA_REG(CAU,8)
mbed_official 146:f64d43ff0c18 2562
mbed_official 146:f64d43ff0c18 2563 /* CAU - Register array accessors */
mbed_official 146:f64d43ff0c18 2564 #define CAU_DIRECT(index) CAU_DIRECT_REG(CAU,index)
mbed_official 146:f64d43ff0c18 2565 #define CAU_LDR_CA(index) CAU_LDR_CA_REG(CAU,index)
mbed_official 146:f64d43ff0c18 2566 #define CAU_STR_CA(index) CAU_STR_CA_REG(CAU,index)
mbed_official 146:f64d43ff0c18 2567 #define CAU_ADR_CA(index) CAU_ADR_CA_REG(CAU,index)
mbed_official 146:f64d43ff0c18 2568 #define CAU_RADR_CA(index) CAU_RADR_CA_REG(CAU,index)
mbed_official 146:f64d43ff0c18 2569 #define CAU_XOR_CA(index) CAU_XOR_CA_REG(CAU,index)
mbed_official 146:f64d43ff0c18 2570 #define CAU_ROTL_CA(index) CAU_ROTL_CA_REG(CAU,index)
mbed_official 146:f64d43ff0c18 2571 #define CAU_AESC_CA(index) CAU_AESC_CA_REG(CAU,index)
mbed_official 146:f64d43ff0c18 2572 #define CAU_AESIC_CA(index) CAU_AESIC_CA_REG(CAU,index)
mbed_official 146:f64d43ff0c18 2573
mbed_official 146:f64d43ff0c18 2574 /*!
mbed_official 146:f64d43ff0c18 2575 * @}
mbed_official 146:f64d43ff0c18 2576 */ /* end of group CAU_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 2577
mbed_official 146:f64d43ff0c18 2578
mbed_official 146:f64d43ff0c18 2579 /*!
mbed_official 146:f64d43ff0c18 2580 * @}
mbed_official 146:f64d43ff0c18 2581 */ /* end of group CAU_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 2582
mbed_official 146:f64d43ff0c18 2583
mbed_official 146:f64d43ff0c18 2584 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2585 -- CMP Peripheral Access Layer
mbed_official 146:f64d43ff0c18 2586 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 2587
mbed_official 146:f64d43ff0c18 2588 /*!
mbed_official 146:f64d43ff0c18 2589 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
mbed_official 146:f64d43ff0c18 2590 * @{
mbed_official 146:f64d43ff0c18 2591 */
mbed_official 146:f64d43ff0c18 2592
mbed_official 146:f64d43ff0c18 2593 /** CMP - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 2594 typedef struct {
mbed_official 146:f64d43ff0c18 2595 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
mbed_official 146:f64d43ff0c18 2596 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
mbed_official 146:f64d43ff0c18 2597 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
mbed_official 146:f64d43ff0c18 2598 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
mbed_official 146:f64d43ff0c18 2599 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
mbed_official 146:f64d43ff0c18 2600 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
mbed_official 146:f64d43ff0c18 2601 } CMP_Type, *CMP_MemMapPtr;
mbed_official 146:f64d43ff0c18 2602
mbed_official 146:f64d43ff0c18 2603 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2604 -- CMP - Register accessor macros
mbed_official 146:f64d43ff0c18 2605 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 2606
mbed_official 146:f64d43ff0c18 2607 /*!
mbed_official 146:f64d43ff0c18 2608 * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
mbed_official 146:f64d43ff0c18 2609 * @{
mbed_official 146:f64d43ff0c18 2610 */
mbed_official 146:f64d43ff0c18 2611
mbed_official 146:f64d43ff0c18 2612
mbed_official 146:f64d43ff0c18 2613 /* CMP - Register accessors */
mbed_official 146:f64d43ff0c18 2614 #define CMP_CR0_REG(base) ((base)->CR0)
mbed_official 146:f64d43ff0c18 2615 #define CMP_CR1_REG(base) ((base)->CR1)
mbed_official 146:f64d43ff0c18 2616 #define CMP_FPR_REG(base) ((base)->FPR)
mbed_official 146:f64d43ff0c18 2617 #define CMP_SCR_REG(base) ((base)->SCR)
mbed_official 146:f64d43ff0c18 2618 #define CMP_DACCR_REG(base) ((base)->DACCR)
mbed_official 146:f64d43ff0c18 2619 #define CMP_MUXCR_REG(base) ((base)->MUXCR)
mbed_official 146:f64d43ff0c18 2620
mbed_official 146:f64d43ff0c18 2621 /*!
mbed_official 146:f64d43ff0c18 2622 * @}
mbed_official 146:f64d43ff0c18 2623 */ /* end of group CMP_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 2624
mbed_official 146:f64d43ff0c18 2625
mbed_official 146:f64d43ff0c18 2626 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2627 -- CMP Register Masks
mbed_official 146:f64d43ff0c18 2628 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 2629
mbed_official 146:f64d43ff0c18 2630 /*!
mbed_official 146:f64d43ff0c18 2631 * @addtogroup CMP_Register_Masks CMP Register Masks
mbed_official 146:f64d43ff0c18 2632 * @{
mbed_official 146:f64d43ff0c18 2633 */
mbed_official 146:f64d43ff0c18 2634
mbed_official 146:f64d43ff0c18 2635 /* CR0 Bit Fields */
mbed_official 146:f64d43ff0c18 2636 #define CMP_CR0_HYSTCTR_MASK 0x3u
mbed_official 146:f64d43ff0c18 2637 #define CMP_CR0_HYSTCTR_SHIFT 0
mbed_official 146:f64d43ff0c18 2638 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
mbed_official 146:f64d43ff0c18 2639 #define CMP_CR0_FILTER_CNT_MASK 0x70u
mbed_official 146:f64d43ff0c18 2640 #define CMP_CR0_FILTER_CNT_SHIFT 4
mbed_official 146:f64d43ff0c18 2641 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
mbed_official 146:f64d43ff0c18 2642 /* CR1 Bit Fields */
mbed_official 146:f64d43ff0c18 2643 #define CMP_CR1_EN_MASK 0x1u
mbed_official 146:f64d43ff0c18 2644 #define CMP_CR1_EN_SHIFT 0
mbed_official 146:f64d43ff0c18 2645 #define CMP_CR1_OPE_MASK 0x2u
mbed_official 146:f64d43ff0c18 2646 #define CMP_CR1_OPE_SHIFT 1
mbed_official 146:f64d43ff0c18 2647 #define CMP_CR1_COS_MASK 0x4u
mbed_official 146:f64d43ff0c18 2648 #define CMP_CR1_COS_SHIFT 2
mbed_official 146:f64d43ff0c18 2649 #define CMP_CR1_INV_MASK 0x8u
mbed_official 146:f64d43ff0c18 2650 #define CMP_CR1_INV_SHIFT 3
mbed_official 146:f64d43ff0c18 2651 #define CMP_CR1_PMODE_MASK 0x10u
mbed_official 146:f64d43ff0c18 2652 #define CMP_CR1_PMODE_SHIFT 4
mbed_official 146:f64d43ff0c18 2653 #define CMP_CR1_WE_MASK 0x40u
mbed_official 146:f64d43ff0c18 2654 #define CMP_CR1_WE_SHIFT 6
mbed_official 146:f64d43ff0c18 2655 #define CMP_CR1_SE_MASK 0x80u
mbed_official 146:f64d43ff0c18 2656 #define CMP_CR1_SE_SHIFT 7
mbed_official 146:f64d43ff0c18 2657 /* FPR Bit Fields */
mbed_official 146:f64d43ff0c18 2658 #define CMP_FPR_FILT_PER_MASK 0xFFu
mbed_official 146:f64d43ff0c18 2659 #define CMP_FPR_FILT_PER_SHIFT 0
mbed_official 146:f64d43ff0c18 2660 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
mbed_official 146:f64d43ff0c18 2661 /* SCR Bit Fields */
mbed_official 146:f64d43ff0c18 2662 #define CMP_SCR_COUT_MASK 0x1u
mbed_official 146:f64d43ff0c18 2663 #define CMP_SCR_COUT_SHIFT 0
mbed_official 146:f64d43ff0c18 2664 #define CMP_SCR_CFF_MASK 0x2u
mbed_official 146:f64d43ff0c18 2665 #define CMP_SCR_CFF_SHIFT 1
mbed_official 146:f64d43ff0c18 2666 #define CMP_SCR_CFR_MASK 0x4u
mbed_official 146:f64d43ff0c18 2667 #define CMP_SCR_CFR_SHIFT 2
mbed_official 146:f64d43ff0c18 2668 #define CMP_SCR_IEF_MASK 0x8u
mbed_official 146:f64d43ff0c18 2669 #define CMP_SCR_IEF_SHIFT 3
mbed_official 146:f64d43ff0c18 2670 #define CMP_SCR_IER_MASK 0x10u
mbed_official 146:f64d43ff0c18 2671 #define CMP_SCR_IER_SHIFT 4
mbed_official 146:f64d43ff0c18 2672 #define CMP_SCR_DMAEN_MASK 0x40u
mbed_official 146:f64d43ff0c18 2673 #define CMP_SCR_DMAEN_SHIFT 6
mbed_official 146:f64d43ff0c18 2674 /* DACCR Bit Fields */
mbed_official 146:f64d43ff0c18 2675 #define CMP_DACCR_VOSEL_MASK 0x3Fu
mbed_official 146:f64d43ff0c18 2676 #define CMP_DACCR_VOSEL_SHIFT 0
mbed_official 146:f64d43ff0c18 2677 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
mbed_official 146:f64d43ff0c18 2678 #define CMP_DACCR_VRSEL_MASK 0x40u
mbed_official 146:f64d43ff0c18 2679 #define CMP_DACCR_VRSEL_SHIFT 6
mbed_official 146:f64d43ff0c18 2680 #define CMP_DACCR_DACEN_MASK 0x80u
mbed_official 146:f64d43ff0c18 2681 #define CMP_DACCR_DACEN_SHIFT 7
mbed_official 146:f64d43ff0c18 2682 /* MUXCR Bit Fields */
mbed_official 146:f64d43ff0c18 2683 #define CMP_MUXCR_MSEL_MASK 0x7u
mbed_official 146:f64d43ff0c18 2684 #define CMP_MUXCR_MSEL_SHIFT 0
mbed_official 146:f64d43ff0c18 2685 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
mbed_official 146:f64d43ff0c18 2686 #define CMP_MUXCR_PSEL_MASK 0x38u
mbed_official 146:f64d43ff0c18 2687 #define CMP_MUXCR_PSEL_SHIFT 3
mbed_official 146:f64d43ff0c18 2688 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
mbed_official 146:f64d43ff0c18 2689 #define CMP_MUXCR_PSTM_MASK 0x80u
mbed_official 146:f64d43ff0c18 2690 #define CMP_MUXCR_PSTM_SHIFT 7
mbed_official 146:f64d43ff0c18 2691
mbed_official 146:f64d43ff0c18 2692 /*!
mbed_official 146:f64d43ff0c18 2693 * @}
mbed_official 146:f64d43ff0c18 2694 */ /* end of group CMP_Register_Masks */
mbed_official 146:f64d43ff0c18 2695
mbed_official 146:f64d43ff0c18 2696
mbed_official 146:f64d43ff0c18 2697 /* CMP - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 2698 /** Peripheral CMP0 base address */
mbed_official 146:f64d43ff0c18 2699 #define CMP0_BASE (0x40073000u)
mbed_official 146:f64d43ff0c18 2700 /** Peripheral CMP0 base pointer */
mbed_official 146:f64d43ff0c18 2701 #define CMP0 ((CMP_Type *)CMP0_BASE)
mbed_official 146:f64d43ff0c18 2702 #define CMP0_BASE_PTR (CMP0)
mbed_official 146:f64d43ff0c18 2703 /** Peripheral CMP1 base address */
mbed_official 146:f64d43ff0c18 2704 #define CMP1_BASE (0x40073008u)
mbed_official 146:f64d43ff0c18 2705 /** Peripheral CMP1 base pointer */
mbed_official 146:f64d43ff0c18 2706 #define CMP1 ((CMP_Type *)CMP1_BASE)
mbed_official 146:f64d43ff0c18 2707 #define CMP1_BASE_PTR (CMP1)
mbed_official 146:f64d43ff0c18 2708 /** Peripheral CMP2 base address */
mbed_official 146:f64d43ff0c18 2709 #define CMP2_BASE (0x40073010u)
mbed_official 146:f64d43ff0c18 2710 /** Peripheral CMP2 base pointer */
mbed_official 146:f64d43ff0c18 2711 #define CMP2 ((CMP_Type *)CMP2_BASE)
mbed_official 146:f64d43ff0c18 2712 #define CMP2_BASE_PTR (CMP2)
mbed_official 146:f64d43ff0c18 2713 /** Array initializer of CMP peripheral base pointers */
mbed_official 146:f64d43ff0c18 2714 #define CMP_BASES { CMP0, CMP1, CMP2 }
mbed_official 146:f64d43ff0c18 2715
mbed_official 146:f64d43ff0c18 2716 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2717 -- CMP - Register accessor macros
mbed_official 146:f64d43ff0c18 2718 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 2719
mbed_official 146:f64d43ff0c18 2720 /*!
mbed_official 146:f64d43ff0c18 2721 * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
mbed_official 146:f64d43ff0c18 2722 * @{
mbed_official 146:f64d43ff0c18 2723 */
mbed_official 146:f64d43ff0c18 2724
mbed_official 146:f64d43ff0c18 2725
mbed_official 146:f64d43ff0c18 2726 /* CMP - Register instance definitions */
mbed_official 146:f64d43ff0c18 2727 /* CMP0 */
mbed_official 146:f64d43ff0c18 2728 #define CMP0_CR0 CMP_CR0_REG(CMP0)
mbed_official 146:f64d43ff0c18 2729 #define CMP0_CR1 CMP_CR1_REG(CMP0)
mbed_official 146:f64d43ff0c18 2730 #define CMP0_FPR CMP_FPR_REG(CMP0)
mbed_official 146:f64d43ff0c18 2731 #define CMP0_SCR CMP_SCR_REG(CMP0)
mbed_official 146:f64d43ff0c18 2732 #define CMP0_DACCR CMP_DACCR_REG(CMP0)
mbed_official 146:f64d43ff0c18 2733 #define CMP0_MUXCR CMP_MUXCR_REG(CMP0)
mbed_official 146:f64d43ff0c18 2734 /* CMP1 */
mbed_official 146:f64d43ff0c18 2735 #define CMP1_CR0 CMP_CR0_REG(CMP1)
mbed_official 146:f64d43ff0c18 2736 #define CMP1_CR1 CMP_CR1_REG(CMP1)
mbed_official 146:f64d43ff0c18 2737 #define CMP1_FPR CMP_FPR_REG(CMP1)
mbed_official 146:f64d43ff0c18 2738 #define CMP1_SCR CMP_SCR_REG(CMP1)
mbed_official 146:f64d43ff0c18 2739 #define CMP1_DACCR CMP_DACCR_REG(CMP1)
mbed_official 146:f64d43ff0c18 2740 #define CMP1_MUXCR CMP_MUXCR_REG(CMP1)
mbed_official 146:f64d43ff0c18 2741 /* CMP2 */
mbed_official 146:f64d43ff0c18 2742 #define CMP2_CR0 CMP_CR0_REG(CMP2)
mbed_official 146:f64d43ff0c18 2743 #define CMP2_CR1 CMP_CR1_REG(CMP2)
mbed_official 146:f64d43ff0c18 2744 #define CMP2_FPR CMP_FPR_REG(CMP2)
mbed_official 146:f64d43ff0c18 2745 #define CMP2_SCR CMP_SCR_REG(CMP2)
mbed_official 146:f64d43ff0c18 2746 #define CMP2_DACCR CMP_DACCR_REG(CMP2)
mbed_official 146:f64d43ff0c18 2747 #define CMP2_MUXCR CMP_MUXCR_REG(CMP2)
mbed_official 146:f64d43ff0c18 2748
mbed_official 146:f64d43ff0c18 2749 /*!
mbed_official 146:f64d43ff0c18 2750 * @}
mbed_official 146:f64d43ff0c18 2751 */ /* end of group CMP_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 2752
mbed_official 146:f64d43ff0c18 2753
mbed_official 146:f64d43ff0c18 2754 /*!
mbed_official 146:f64d43ff0c18 2755 * @}
mbed_official 146:f64d43ff0c18 2756 */ /* end of group CMP_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 2757
mbed_official 146:f64d43ff0c18 2758
mbed_official 146:f64d43ff0c18 2759 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2760 -- CMT Peripheral Access Layer
mbed_official 146:f64d43ff0c18 2761 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 2762
mbed_official 146:f64d43ff0c18 2763 /*!
mbed_official 146:f64d43ff0c18 2764 * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
mbed_official 146:f64d43ff0c18 2765 * @{
mbed_official 146:f64d43ff0c18 2766 */
mbed_official 146:f64d43ff0c18 2767
mbed_official 146:f64d43ff0c18 2768 /** CMT - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 2769 typedef struct {
mbed_official 146:f64d43ff0c18 2770 __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
mbed_official 146:f64d43ff0c18 2771 __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
mbed_official 146:f64d43ff0c18 2772 __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
mbed_official 146:f64d43ff0c18 2773 __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
mbed_official 146:f64d43ff0c18 2774 __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
mbed_official 146:f64d43ff0c18 2775 __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
mbed_official 146:f64d43ff0c18 2776 __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
mbed_official 146:f64d43ff0c18 2777 __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
mbed_official 146:f64d43ff0c18 2778 __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
mbed_official 146:f64d43ff0c18 2779 __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
mbed_official 146:f64d43ff0c18 2780 __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
mbed_official 146:f64d43ff0c18 2781 __IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0xB */
mbed_official 146:f64d43ff0c18 2782 } CMT_Type, *CMT_MemMapPtr;
mbed_official 146:f64d43ff0c18 2783
mbed_official 146:f64d43ff0c18 2784 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2785 -- CMT - Register accessor macros
mbed_official 146:f64d43ff0c18 2786 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 2787
mbed_official 146:f64d43ff0c18 2788 /*!
mbed_official 146:f64d43ff0c18 2789 * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
mbed_official 146:f64d43ff0c18 2790 * @{
mbed_official 146:f64d43ff0c18 2791 */
mbed_official 146:f64d43ff0c18 2792
mbed_official 146:f64d43ff0c18 2793
mbed_official 146:f64d43ff0c18 2794 /* CMT - Register accessors */
mbed_official 146:f64d43ff0c18 2795 #define CMT_CGH1_REG(base) ((base)->CGH1)
mbed_official 146:f64d43ff0c18 2796 #define CMT_CGL1_REG(base) ((base)->CGL1)
mbed_official 146:f64d43ff0c18 2797 #define CMT_CGH2_REG(base) ((base)->CGH2)
mbed_official 146:f64d43ff0c18 2798 #define CMT_CGL2_REG(base) ((base)->CGL2)
mbed_official 146:f64d43ff0c18 2799 #define CMT_OC_REG(base) ((base)->OC)
mbed_official 146:f64d43ff0c18 2800 #define CMT_MSC_REG(base) ((base)->MSC)
mbed_official 146:f64d43ff0c18 2801 #define CMT_CMD1_REG(base) ((base)->CMD1)
mbed_official 146:f64d43ff0c18 2802 #define CMT_CMD2_REG(base) ((base)->CMD2)
mbed_official 146:f64d43ff0c18 2803 #define CMT_CMD3_REG(base) ((base)->CMD3)
mbed_official 146:f64d43ff0c18 2804 #define CMT_CMD4_REG(base) ((base)->CMD4)
mbed_official 146:f64d43ff0c18 2805 #define CMT_PPS_REG(base) ((base)->PPS)
mbed_official 146:f64d43ff0c18 2806 #define CMT_DMA_REG(base) ((base)->DMA)
mbed_official 146:f64d43ff0c18 2807
mbed_official 146:f64d43ff0c18 2808 /*!
mbed_official 146:f64d43ff0c18 2809 * @}
mbed_official 146:f64d43ff0c18 2810 */ /* end of group CMT_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 2811
mbed_official 146:f64d43ff0c18 2812
mbed_official 146:f64d43ff0c18 2813 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2814 -- CMT Register Masks
mbed_official 146:f64d43ff0c18 2815 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 2816
mbed_official 146:f64d43ff0c18 2817 /*!
mbed_official 146:f64d43ff0c18 2818 * @addtogroup CMT_Register_Masks CMT Register Masks
mbed_official 146:f64d43ff0c18 2819 * @{
mbed_official 146:f64d43ff0c18 2820 */
mbed_official 146:f64d43ff0c18 2821
mbed_official 146:f64d43ff0c18 2822 /* CGH1 Bit Fields */
mbed_official 146:f64d43ff0c18 2823 #define CMT_CGH1_PH_MASK 0xFFu
mbed_official 146:f64d43ff0c18 2824 #define CMT_CGH1_PH_SHIFT 0
mbed_official 146:f64d43ff0c18 2825 #define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
mbed_official 146:f64d43ff0c18 2826 /* CGL1 Bit Fields */
mbed_official 146:f64d43ff0c18 2827 #define CMT_CGL1_PL_MASK 0xFFu
mbed_official 146:f64d43ff0c18 2828 #define CMT_CGL1_PL_SHIFT 0
mbed_official 146:f64d43ff0c18 2829 #define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
mbed_official 146:f64d43ff0c18 2830 /* CGH2 Bit Fields */
mbed_official 146:f64d43ff0c18 2831 #define CMT_CGH2_SH_MASK 0xFFu
mbed_official 146:f64d43ff0c18 2832 #define CMT_CGH2_SH_SHIFT 0
mbed_official 146:f64d43ff0c18 2833 #define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
mbed_official 146:f64d43ff0c18 2834 /* CGL2 Bit Fields */
mbed_official 146:f64d43ff0c18 2835 #define CMT_CGL2_SL_MASK 0xFFu
mbed_official 146:f64d43ff0c18 2836 #define CMT_CGL2_SL_SHIFT 0
mbed_official 146:f64d43ff0c18 2837 #define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
mbed_official 146:f64d43ff0c18 2838 /* OC Bit Fields */
mbed_official 146:f64d43ff0c18 2839 #define CMT_OC_IROPEN_MASK 0x20u
mbed_official 146:f64d43ff0c18 2840 #define CMT_OC_IROPEN_SHIFT 5
mbed_official 146:f64d43ff0c18 2841 #define CMT_OC_CMTPOL_MASK 0x40u
mbed_official 146:f64d43ff0c18 2842 #define CMT_OC_CMTPOL_SHIFT 6
mbed_official 146:f64d43ff0c18 2843 #define CMT_OC_IROL_MASK 0x80u
mbed_official 146:f64d43ff0c18 2844 #define CMT_OC_IROL_SHIFT 7
mbed_official 146:f64d43ff0c18 2845 /* MSC Bit Fields */
mbed_official 146:f64d43ff0c18 2846 #define CMT_MSC_MCGEN_MASK 0x1u
mbed_official 146:f64d43ff0c18 2847 #define CMT_MSC_MCGEN_SHIFT 0
mbed_official 146:f64d43ff0c18 2848 #define CMT_MSC_EOCIE_MASK 0x2u
mbed_official 146:f64d43ff0c18 2849 #define CMT_MSC_EOCIE_SHIFT 1
mbed_official 146:f64d43ff0c18 2850 #define CMT_MSC_FSK_MASK 0x4u
mbed_official 146:f64d43ff0c18 2851 #define CMT_MSC_FSK_SHIFT 2
mbed_official 146:f64d43ff0c18 2852 #define CMT_MSC_BASE_MASK 0x8u
mbed_official 146:f64d43ff0c18 2853 #define CMT_MSC_BASE_SHIFT 3
mbed_official 146:f64d43ff0c18 2854 #define CMT_MSC_EXSPC_MASK 0x10u
mbed_official 146:f64d43ff0c18 2855 #define CMT_MSC_EXSPC_SHIFT 4
mbed_official 146:f64d43ff0c18 2856 #define CMT_MSC_CMTDIV_MASK 0x60u
mbed_official 146:f64d43ff0c18 2857 #define CMT_MSC_CMTDIV_SHIFT 5
mbed_official 146:f64d43ff0c18 2858 #define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
mbed_official 146:f64d43ff0c18 2859 #define CMT_MSC_EOCF_MASK 0x80u
mbed_official 146:f64d43ff0c18 2860 #define CMT_MSC_EOCF_SHIFT 7
mbed_official 146:f64d43ff0c18 2861 /* CMD1 Bit Fields */
mbed_official 146:f64d43ff0c18 2862 #define CMT_CMD1_MB_MASK 0xFFu
mbed_official 146:f64d43ff0c18 2863 #define CMT_CMD1_MB_SHIFT 0
mbed_official 146:f64d43ff0c18 2864 #define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
mbed_official 146:f64d43ff0c18 2865 /* CMD2 Bit Fields */
mbed_official 146:f64d43ff0c18 2866 #define CMT_CMD2_MB_MASK 0xFFu
mbed_official 146:f64d43ff0c18 2867 #define CMT_CMD2_MB_SHIFT 0
mbed_official 146:f64d43ff0c18 2868 #define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
mbed_official 146:f64d43ff0c18 2869 /* CMD3 Bit Fields */
mbed_official 146:f64d43ff0c18 2870 #define CMT_CMD3_SB_MASK 0xFFu
mbed_official 146:f64d43ff0c18 2871 #define CMT_CMD3_SB_SHIFT 0
mbed_official 146:f64d43ff0c18 2872 #define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
mbed_official 146:f64d43ff0c18 2873 /* CMD4 Bit Fields */
mbed_official 146:f64d43ff0c18 2874 #define CMT_CMD4_SB_MASK 0xFFu
mbed_official 146:f64d43ff0c18 2875 #define CMT_CMD4_SB_SHIFT 0
mbed_official 146:f64d43ff0c18 2876 #define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
mbed_official 146:f64d43ff0c18 2877 /* PPS Bit Fields */
mbed_official 146:f64d43ff0c18 2878 #define CMT_PPS_PPSDIV_MASK 0xFu
mbed_official 146:f64d43ff0c18 2879 #define CMT_PPS_PPSDIV_SHIFT 0
mbed_official 146:f64d43ff0c18 2880 #define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
mbed_official 146:f64d43ff0c18 2881 /* DMA Bit Fields */
mbed_official 146:f64d43ff0c18 2882 #define CMT_DMA_DMA_MASK 0x1u
mbed_official 146:f64d43ff0c18 2883 #define CMT_DMA_DMA_SHIFT 0
mbed_official 146:f64d43ff0c18 2884
mbed_official 146:f64d43ff0c18 2885 /*!
mbed_official 146:f64d43ff0c18 2886 * @}
mbed_official 146:f64d43ff0c18 2887 */ /* end of group CMT_Register_Masks */
mbed_official 146:f64d43ff0c18 2888
mbed_official 146:f64d43ff0c18 2889
mbed_official 146:f64d43ff0c18 2890 /* CMT - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 2891 /** Peripheral CMT base address */
mbed_official 146:f64d43ff0c18 2892 #define CMT_BASE (0x40062000u)
mbed_official 146:f64d43ff0c18 2893 /** Peripheral CMT base pointer */
mbed_official 146:f64d43ff0c18 2894 #define CMT ((CMT_Type *)CMT_BASE)
mbed_official 146:f64d43ff0c18 2895 #define CMT_BASE_PTR (CMT)
mbed_official 146:f64d43ff0c18 2896 /** Array initializer of CMT peripheral base pointers */
mbed_official 146:f64d43ff0c18 2897 #define CMT_BASES { CMT }
mbed_official 146:f64d43ff0c18 2898
mbed_official 146:f64d43ff0c18 2899 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2900 -- CMT - Register accessor macros
mbed_official 146:f64d43ff0c18 2901 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 2902
mbed_official 146:f64d43ff0c18 2903 /*!
mbed_official 146:f64d43ff0c18 2904 * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
mbed_official 146:f64d43ff0c18 2905 * @{
mbed_official 146:f64d43ff0c18 2906 */
mbed_official 146:f64d43ff0c18 2907
mbed_official 146:f64d43ff0c18 2908
mbed_official 146:f64d43ff0c18 2909 /* CMT - Register instance definitions */
mbed_official 146:f64d43ff0c18 2910 /* CMT */
mbed_official 146:f64d43ff0c18 2911 #define CMT_CGH1 CMT_CGH1_REG(CMT)
mbed_official 146:f64d43ff0c18 2912 #define CMT_CGL1 CMT_CGL1_REG(CMT)
mbed_official 146:f64d43ff0c18 2913 #define CMT_CGH2 CMT_CGH2_REG(CMT)
mbed_official 146:f64d43ff0c18 2914 #define CMT_CGL2 CMT_CGL2_REG(CMT)
mbed_official 146:f64d43ff0c18 2915 #define CMT_OC CMT_OC_REG(CMT)
mbed_official 146:f64d43ff0c18 2916 #define CMT_MSC CMT_MSC_REG(CMT)
mbed_official 146:f64d43ff0c18 2917 #define CMT_CMD1 CMT_CMD1_REG(CMT)
mbed_official 146:f64d43ff0c18 2918 #define CMT_CMD2 CMT_CMD2_REG(CMT)
mbed_official 146:f64d43ff0c18 2919 #define CMT_CMD3 CMT_CMD3_REG(CMT)
mbed_official 146:f64d43ff0c18 2920 #define CMT_CMD4 CMT_CMD4_REG(CMT)
mbed_official 146:f64d43ff0c18 2921 #define CMT_PPS CMT_PPS_REG(CMT)
mbed_official 146:f64d43ff0c18 2922 #define CMT_DMA CMT_DMA_REG(CMT)
mbed_official 146:f64d43ff0c18 2923
mbed_official 146:f64d43ff0c18 2924 /*!
mbed_official 146:f64d43ff0c18 2925 * @}
mbed_official 146:f64d43ff0c18 2926 */ /* end of group CMT_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 2927
mbed_official 146:f64d43ff0c18 2928
mbed_official 146:f64d43ff0c18 2929 /*!
mbed_official 146:f64d43ff0c18 2930 * @}
mbed_official 146:f64d43ff0c18 2931 */ /* end of group CMT_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 2932
mbed_official 146:f64d43ff0c18 2933
mbed_official 146:f64d43ff0c18 2934 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2935 -- CRC Peripheral Access Layer
mbed_official 146:f64d43ff0c18 2936 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 2937
mbed_official 146:f64d43ff0c18 2938 /*!
mbed_official 146:f64d43ff0c18 2939 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
mbed_official 146:f64d43ff0c18 2940 * @{
mbed_official 146:f64d43ff0c18 2941 */
mbed_official 146:f64d43ff0c18 2942
mbed_official 146:f64d43ff0c18 2943 /** CRC - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 2944 typedef struct {
mbed_official 146:f64d43ff0c18 2945 union { /* offset: 0x0 */
mbed_official 146:f64d43ff0c18 2946 struct { /* offset: 0x0 */
mbed_official 146:f64d43ff0c18 2947 __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
mbed_official 146:f64d43ff0c18 2948 __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
mbed_official 146:f64d43ff0c18 2949 } ACCESS16BIT;
mbed_official 146:f64d43ff0c18 2950 __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
mbed_official 146:f64d43ff0c18 2951 struct { /* offset: 0x0 */
mbed_official 146:f64d43ff0c18 2952 __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
mbed_official 146:f64d43ff0c18 2953 __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
mbed_official 146:f64d43ff0c18 2954 __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
mbed_official 146:f64d43ff0c18 2955 __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
mbed_official 146:f64d43ff0c18 2956 } ACCESS8BIT;
mbed_official 146:f64d43ff0c18 2957 };
mbed_official 146:f64d43ff0c18 2958 union { /* offset: 0x4 */
mbed_official 146:f64d43ff0c18 2959 struct { /* offset: 0x4 */
mbed_official 146:f64d43ff0c18 2960 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
mbed_official 146:f64d43ff0c18 2961 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
mbed_official 146:f64d43ff0c18 2962 } GPOLY_ACCESS16BIT;
mbed_official 146:f64d43ff0c18 2963 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
mbed_official 146:f64d43ff0c18 2964 struct { /* offset: 0x4 */
mbed_official 146:f64d43ff0c18 2965 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
mbed_official 146:f64d43ff0c18 2966 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
mbed_official 146:f64d43ff0c18 2967 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
mbed_official 146:f64d43ff0c18 2968 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
mbed_official 146:f64d43ff0c18 2969 } GPOLY_ACCESS8BIT;
mbed_official 146:f64d43ff0c18 2970 };
mbed_official 146:f64d43ff0c18 2971 union { /* offset: 0x8 */
mbed_official 146:f64d43ff0c18 2972 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
mbed_official 146:f64d43ff0c18 2973 struct { /* offset: 0x8 */
mbed_official 146:f64d43ff0c18 2974 uint8_t RESERVED_0[3];
mbed_official 146:f64d43ff0c18 2975 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
mbed_official 146:f64d43ff0c18 2976 } CTRL_ACCESS8BIT;
mbed_official 146:f64d43ff0c18 2977 };
mbed_official 146:f64d43ff0c18 2978 } CRC_Type, *CRC_MemMapPtr;
mbed_official 146:f64d43ff0c18 2979
mbed_official 146:f64d43ff0c18 2980 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2981 -- CRC - Register accessor macros
mbed_official 146:f64d43ff0c18 2982 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 2983
mbed_official 146:f64d43ff0c18 2984 /*!
mbed_official 146:f64d43ff0c18 2985 * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
mbed_official 146:f64d43ff0c18 2986 * @{
mbed_official 146:f64d43ff0c18 2987 */
mbed_official 146:f64d43ff0c18 2988
mbed_official 146:f64d43ff0c18 2989
mbed_official 146:f64d43ff0c18 2990 /* CRC - Register accessors */
mbed_official 146:f64d43ff0c18 2991 #define CRC_DATAL_REG(base) ((base)->ACCESS16BIT.DATAL)
mbed_official 146:f64d43ff0c18 2992 #define CRC_DATAH_REG(base) ((base)->ACCESS16BIT.DATAH)
mbed_official 146:f64d43ff0c18 2993 #define CRC_DATA_REG(base) ((base)->DATA)
mbed_official 146:f64d43ff0c18 2994 #define CRC_DATALL_REG(base) ((base)->ACCESS8BIT.DATALL)
mbed_official 146:f64d43ff0c18 2995 #define CRC_DATALU_REG(base) ((base)->ACCESS8BIT.DATALU)
mbed_official 146:f64d43ff0c18 2996 #define CRC_DATAHL_REG(base) ((base)->ACCESS8BIT.DATAHL)
mbed_official 146:f64d43ff0c18 2997 #define CRC_DATAHU_REG(base) ((base)->ACCESS8BIT.DATAHU)
mbed_official 146:f64d43ff0c18 2998 #define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL)
mbed_official 146:f64d43ff0c18 2999 #define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH)
mbed_official 146:f64d43ff0c18 3000 #define CRC_GPOLY_REG(base) ((base)->GPOLY)
mbed_official 146:f64d43ff0c18 3001 #define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL)
mbed_official 146:f64d43ff0c18 3002 #define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU)
mbed_official 146:f64d43ff0c18 3003 #define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL)
mbed_official 146:f64d43ff0c18 3004 #define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU)
mbed_official 146:f64d43ff0c18 3005 #define CRC_CTRL_REG(base) ((base)->CTRL)
mbed_official 146:f64d43ff0c18 3006 #define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU)
mbed_official 146:f64d43ff0c18 3007
mbed_official 146:f64d43ff0c18 3008 /*!
mbed_official 146:f64d43ff0c18 3009 * @}
mbed_official 146:f64d43ff0c18 3010 */ /* end of group CRC_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 3011
mbed_official 146:f64d43ff0c18 3012
mbed_official 146:f64d43ff0c18 3013 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3014 -- CRC Register Masks
mbed_official 146:f64d43ff0c18 3015 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 3016
mbed_official 146:f64d43ff0c18 3017 /*!
mbed_official 146:f64d43ff0c18 3018 * @addtogroup CRC_Register_Masks CRC Register Masks
mbed_official 146:f64d43ff0c18 3019 * @{
mbed_official 146:f64d43ff0c18 3020 */
mbed_official 146:f64d43ff0c18 3021
mbed_official 146:f64d43ff0c18 3022 /* DATAL Bit Fields */
mbed_official 146:f64d43ff0c18 3023 #define CRC_DATAL_DATAL_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 3024 #define CRC_DATAL_DATAL_SHIFT 0
mbed_official 146:f64d43ff0c18 3025 #define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAL_DATAL_SHIFT))&CRC_DATAL_DATAL_MASK)
mbed_official 146:f64d43ff0c18 3026 /* DATAH Bit Fields */
mbed_official 146:f64d43ff0c18 3027 #define CRC_DATAH_DATAH_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 3028 #define CRC_DATAH_DATAH_SHIFT 0
mbed_official 146:f64d43ff0c18 3029 #define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAH_DATAH_SHIFT))&CRC_DATAH_DATAH_MASK)
mbed_official 146:f64d43ff0c18 3030 /* DATA Bit Fields */
mbed_official 146:f64d43ff0c18 3031 #define CRC_DATA_LL_MASK 0xFFu
mbed_official 146:f64d43ff0c18 3032 #define CRC_DATA_LL_SHIFT 0
mbed_official 146:f64d43ff0c18 3033 #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LL_SHIFT))&CRC_DATA_LL_MASK)
mbed_official 146:f64d43ff0c18 3034 #define CRC_DATA_LU_MASK 0xFF00u
mbed_official 146:f64d43ff0c18 3035 #define CRC_DATA_LU_SHIFT 8
mbed_official 146:f64d43ff0c18 3036 #define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LU_SHIFT))&CRC_DATA_LU_MASK)
mbed_official 146:f64d43ff0c18 3037 #define CRC_DATA_HL_MASK 0xFF0000u
mbed_official 146:f64d43ff0c18 3038 #define CRC_DATA_HL_SHIFT 16
mbed_official 146:f64d43ff0c18 3039 #define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HL_SHIFT))&CRC_DATA_HL_MASK)
mbed_official 146:f64d43ff0c18 3040 #define CRC_DATA_HU_MASK 0xFF000000u
mbed_official 146:f64d43ff0c18 3041 #define CRC_DATA_HU_SHIFT 24
mbed_official 146:f64d43ff0c18 3042 #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HU_SHIFT))&CRC_DATA_HU_MASK)
mbed_official 146:f64d43ff0c18 3043 /* DATALL Bit Fields */
mbed_official 146:f64d43ff0c18 3044 #define CRC_DATALL_DATALL_MASK 0xFFu
mbed_official 146:f64d43ff0c18 3045 #define CRC_DATALL_DATALL_SHIFT 0
mbed_official 146:f64d43ff0c18 3046 #define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALL_DATALL_SHIFT))&CRC_DATALL_DATALL_MASK)
mbed_official 146:f64d43ff0c18 3047 /* DATALU Bit Fields */
mbed_official 146:f64d43ff0c18 3048 #define CRC_DATALU_DATALU_MASK 0xFFu
mbed_official 146:f64d43ff0c18 3049 #define CRC_DATALU_DATALU_SHIFT 0
mbed_official 146:f64d43ff0c18 3050 #define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALU_DATALU_SHIFT))&CRC_DATALU_DATALU_MASK)
mbed_official 146:f64d43ff0c18 3051 /* DATAHL Bit Fields */
mbed_official 146:f64d43ff0c18 3052 #define CRC_DATAHL_DATAHL_MASK 0xFFu
mbed_official 146:f64d43ff0c18 3053 #define CRC_DATAHL_DATAHL_SHIFT 0
mbed_official 146:f64d43ff0c18 3054 #define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHL_DATAHL_SHIFT))&CRC_DATAHL_DATAHL_MASK)
mbed_official 146:f64d43ff0c18 3055 /* DATAHU Bit Fields */
mbed_official 146:f64d43ff0c18 3056 #define CRC_DATAHU_DATAHU_MASK 0xFFu
mbed_official 146:f64d43ff0c18 3057 #define CRC_DATAHU_DATAHU_SHIFT 0
mbed_official 146:f64d43ff0c18 3058 #define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHU_DATAHU_SHIFT))&CRC_DATAHU_DATAHU_MASK)
mbed_official 146:f64d43ff0c18 3059 /* GPOLYL Bit Fields */
mbed_official 146:f64d43ff0c18 3060 #define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 3061 #define CRC_GPOLYL_GPOLYL_SHIFT 0
mbed_official 146:f64d43ff0c18 3062 #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
mbed_official 146:f64d43ff0c18 3063 /* GPOLYH Bit Fields */
mbed_official 146:f64d43ff0c18 3064 #define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 3065 #define CRC_GPOLYH_GPOLYH_SHIFT 0
mbed_official 146:f64d43ff0c18 3066 #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
mbed_official 146:f64d43ff0c18 3067 /* GPOLY Bit Fields */
mbed_official 146:f64d43ff0c18 3068 #define CRC_GPOLY_LOW_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 3069 #define CRC_GPOLY_LOW_SHIFT 0
mbed_official 146:f64d43ff0c18 3070 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
mbed_official 146:f64d43ff0c18 3071 #define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
mbed_official 146:f64d43ff0c18 3072 #define CRC_GPOLY_HIGH_SHIFT 16
mbed_official 146:f64d43ff0c18 3073 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
mbed_official 146:f64d43ff0c18 3074 /* GPOLYLL Bit Fields */
mbed_official 146:f64d43ff0c18 3075 #define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
mbed_official 146:f64d43ff0c18 3076 #define CRC_GPOLYLL_GPOLYLL_SHIFT 0
mbed_official 146:f64d43ff0c18 3077 #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
mbed_official 146:f64d43ff0c18 3078 /* GPOLYLU Bit Fields */
mbed_official 146:f64d43ff0c18 3079 #define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
mbed_official 146:f64d43ff0c18 3080 #define CRC_GPOLYLU_GPOLYLU_SHIFT 0
mbed_official 146:f64d43ff0c18 3081 #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
mbed_official 146:f64d43ff0c18 3082 /* GPOLYHL Bit Fields */
mbed_official 146:f64d43ff0c18 3083 #define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
mbed_official 146:f64d43ff0c18 3084 #define CRC_GPOLYHL_GPOLYHL_SHIFT 0
mbed_official 146:f64d43ff0c18 3085 #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
mbed_official 146:f64d43ff0c18 3086 /* GPOLYHU Bit Fields */
mbed_official 146:f64d43ff0c18 3087 #define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
mbed_official 146:f64d43ff0c18 3088 #define CRC_GPOLYHU_GPOLYHU_SHIFT 0
mbed_official 146:f64d43ff0c18 3089 #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
mbed_official 146:f64d43ff0c18 3090 /* CTRL Bit Fields */
mbed_official 146:f64d43ff0c18 3091 #define CRC_CTRL_TCRC_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 3092 #define CRC_CTRL_TCRC_SHIFT 24
mbed_official 146:f64d43ff0c18 3093 #define CRC_CTRL_WAS_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 3094 #define CRC_CTRL_WAS_SHIFT 25
mbed_official 146:f64d43ff0c18 3095 #define CRC_CTRL_FXOR_MASK 0x4000000u
mbed_official 146:f64d43ff0c18 3096 #define CRC_CTRL_FXOR_SHIFT 26
mbed_official 146:f64d43ff0c18 3097 #define CRC_CTRL_TOTR_MASK 0x30000000u
mbed_official 146:f64d43ff0c18 3098 #define CRC_CTRL_TOTR_SHIFT 28
mbed_official 146:f64d43ff0c18 3099 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
mbed_official 146:f64d43ff0c18 3100 #define CRC_CTRL_TOT_MASK 0xC0000000u
mbed_official 146:f64d43ff0c18 3101 #define CRC_CTRL_TOT_SHIFT 30
mbed_official 146:f64d43ff0c18 3102 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
mbed_official 146:f64d43ff0c18 3103 /* CTRLHU Bit Fields */
mbed_official 146:f64d43ff0c18 3104 #define CRC_CTRLHU_TCRC_MASK 0x1u
mbed_official 146:f64d43ff0c18 3105 #define CRC_CTRLHU_TCRC_SHIFT 0
mbed_official 146:f64d43ff0c18 3106 #define CRC_CTRLHU_WAS_MASK 0x2u
mbed_official 146:f64d43ff0c18 3107 #define CRC_CTRLHU_WAS_SHIFT 1
mbed_official 146:f64d43ff0c18 3108 #define CRC_CTRLHU_FXOR_MASK 0x4u
mbed_official 146:f64d43ff0c18 3109 #define CRC_CTRLHU_FXOR_SHIFT 2
mbed_official 146:f64d43ff0c18 3110 #define CRC_CTRLHU_TOTR_MASK 0x30u
mbed_official 146:f64d43ff0c18 3111 #define CRC_CTRLHU_TOTR_SHIFT 4
mbed_official 146:f64d43ff0c18 3112 #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
mbed_official 146:f64d43ff0c18 3113 #define CRC_CTRLHU_TOT_MASK 0xC0u
mbed_official 146:f64d43ff0c18 3114 #define CRC_CTRLHU_TOT_SHIFT 6
mbed_official 146:f64d43ff0c18 3115 #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
mbed_official 146:f64d43ff0c18 3116
mbed_official 146:f64d43ff0c18 3117 /*!
mbed_official 146:f64d43ff0c18 3118 * @}
mbed_official 146:f64d43ff0c18 3119 */ /* end of group CRC_Register_Masks */
mbed_official 146:f64d43ff0c18 3120
mbed_official 146:f64d43ff0c18 3121
mbed_official 146:f64d43ff0c18 3122 /* CRC - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 3123 /** Peripheral CRC base address */
mbed_official 146:f64d43ff0c18 3124 #define CRC_BASE (0x40032000u)
mbed_official 146:f64d43ff0c18 3125 /** Peripheral CRC base pointer */
mbed_official 146:f64d43ff0c18 3126 #define CRC0 ((CRC_Type *)CRC_BASE)
mbed_official 146:f64d43ff0c18 3127 #define CRC_BASE_PTR (CRC0)
mbed_official 146:f64d43ff0c18 3128 /** Array initializer of CRC peripheral base pointers */
mbed_official 146:f64d43ff0c18 3129 #define CRC_BASES { CRC0 }
mbed_official 146:f64d43ff0c18 3130
mbed_official 146:f64d43ff0c18 3131 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3132 -- CRC - Register accessor macros
mbed_official 146:f64d43ff0c18 3133 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 3134
mbed_official 146:f64d43ff0c18 3135 /*!
mbed_official 146:f64d43ff0c18 3136 * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
mbed_official 146:f64d43ff0c18 3137 * @{
mbed_official 146:f64d43ff0c18 3138 */
mbed_official 146:f64d43ff0c18 3139
mbed_official 146:f64d43ff0c18 3140
mbed_official 146:f64d43ff0c18 3141 /* CRC - Register instance definitions */
mbed_official 146:f64d43ff0c18 3142 /* CRC */
mbed_official 146:f64d43ff0c18 3143 #define CRC_DATA CRC_DATA_REG(CRC0)
mbed_official 146:f64d43ff0c18 3144 #define CRC_DATAL CRC_DATAL_REG(CRC0)
mbed_official 146:f64d43ff0c18 3145 #define CRC_DATALL CRC_DATALL_REG(CRC0)
mbed_official 146:f64d43ff0c18 3146 #define CRC_DATALU CRC_DATALU_REG(CRC0)
mbed_official 146:f64d43ff0c18 3147 #define CRC_DATAH CRC_DATAH_REG(CRC0)
mbed_official 146:f64d43ff0c18 3148 #define CRC_DATAHL CRC_DATAHL_REG(CRC0)
mbed_official 146:f64d43ff0c18 3149 #define CRC_DATAHU CRC_DATAHU_REG(CRC0)
mbed_official 146:f64d43ff0c18 3150 #define CRC_GPOLY CRC_GPOLY_REG(CRC0)
mbed_official 146:f64d43ff0c18 3151 #define CRC_GPOLYL CRC_GPOLYL_REG(CRC0)
mbed_official 146:f64d43ff0c18 3152 #define CRC_GPOLYLL CRC_GPOLYLL_REG(CRC0)
mbed_official 146:f64d43ff0c18 3153 #define CRC_GPOLYLU CRC_GPOLYLU_REG(CRC0)
mbed_official 146:f64d43ff0c18 3154 #define CRC_GPOLYH CRC_GPOLYH_REG(CRC0)
mbed_official 146:f64d43ff0c18 3155 #define CRC_GPOLYHL CRC_GPOLYHL_REG(CRC0)
mbed_official 146:f64d43ff0c18 3156 #define CRC_GPOLYHU CRC_GPOLYHU_REG(CRC0)
mbed_official 146:f64d43ff0c18 3157 #define CRC_CTRL CRC_CTRL_REG(CRC0)
mbed_official 146:f64d43ff0c18 3158 #define CRC_CTRLHU CRC_CTRLHU_REG(CRC0)
mbed_official 146:f64d43ff0c18 3159
mbed_official 146:f64d43ff0c18 3160 /*!
mbed_official 146:f64d43ff0c18 3161 * @}
mbed_official 146:f64d43ff0c18 3162 */ /* end of group CRC_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 3163
mbed_official 146:f64d43ff0c18 3164
mbed_official 146:f64d43ff0c18 3165 /*!
mbed_official 146:f64d43ff0c18 3166 * @}
mbed_official 146:f64d43ff0c18 3167 */ /* end of group CRC_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 3168
mbed_official 146:f64d43ff0c18 3169
mbed_official 146:f64d43ff0c18 3170 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3171 -- DAC Peripheral Access Layer
mbed_official 146:f64d43ff0c18 3172 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 3173
mbed_official 146:f64d43ff0c18 3174 /*!
mbed_official 146:f64d43ff0c18 3175 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
mbed_official 146:f64d43ff0c18 3176 * @{
mbed_official 146:f64d43ff0c18 3177 */
mbed_official 146:f64d43ff0c18 3178
mbed_official 146:f64d43ff0c18 3179 /** DAC - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 3180 typedef struct {
mbed_official 146:f64d43ff0c18 3181 struct { /* offset: 0x0, array step: 0x2 */
mbed_official 146:f64d43ff0c18 3182 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
mbed_official 146:f64d43ff0c18 3183 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
mbed_official 146:f64d43ff0c18 3184 } DAT[16];
mbed_official 146:f64d43ff0c18 3185 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
mbed_official 146:f64d43ff0c18 3186 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
mbed_official 146:f64d43ff0c18 3187 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
mbed_official 146:f64d43ff0c18 3188 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
mbed_official 146:f64d43ff0c18 3189 } DAC_Type, *DAC_MemMapPtr;
mbed_official 146:f64d43ff0c18 3190
mbed_official 146:f64d43ff0c18 3191 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3192 -- DAC - Register accessor macros
mbed_official 146:f64d43ff0c18 3193 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 3194
mbed_official 146:f64d43ff0c18 3195 /*!
mbed_official 146:f64d43ff0c18 3196 * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
mbed_official 146:f64d43ff0c18 3197 * @{
mbed_official 146:f64d43ff0c18 3198 */
mbed_official 146:f64d43ff0c18 3199
mbed_official 146:f64d43ff0c18 3200
mbed_official 146:f64d43ff0c18 3201 /* DAC - Register accessors */
mbed_official 146:f64d43ff0c18 3202 #define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL)
mbed_official 146:f64d43ff0c18 3203 #define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH)
mbed_official 146:f64d43ff0c18 3204 #define DAC_SR_REG(base) ((base)->SR)
mbed_official 146:f64d43ff0c18 3205 #define DAC_C0_REG(base) ((base)->C0)
mbed_official 146:f64d43ff0c18 3206 #define DAC_C1_REG(base) ((base)->C1)
mbed_official 146:f64d43ff0c18 3207 #define DAC_C2_REG(base) ((base)->C2)
mbed_official 146:f64d43ff0c18 3208
mbed_official 146:f64d43ff0c18 3209 /*!
mbed_official 146:f64d43ff0c18 3210 * @}
mbed_official 146:f64d43ff0c18 3211 */ /* end of group DAC_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 3212
mbed_official 146:f64d43ff0c18 3213
mbed_official 146:f64d43ff0c18 3214 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3215 -- DAC Register Masks
mbed_official 146:f64d43ff0c18 3216 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 3217
mbed_official 146:f64d43ff0c18 3218 /*!
mbed_official 146:f64d43ff0c18 3219 * @addtogroup DAC_Register_Masks DAC Register Masks
mbed_official 146:f64d43ff0c18 3220 * @{
mbed_official 146:f64d43ff0c18 3221 */
mbed_official 146:f64d43ff0c18 3222
mbed_official 146:f64d43ff0c18 3223 /* DATL Bit Fields */
mbed_official 146:f64d43ff0c18 3224 #define DAC_DATL_DATA0_MASK 0xFFu
mbed_official 146:f64d43ff0c18 3225 #define DAC_DATL_DATA0_SHIFT 0
mbed_official 146:f64d43ff0c18 3226 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
mbed_official 146:f64d43ff0c18 3227 /* DATH Bit Fields */
mbed_official 146:f64d43ff0c18 3228 #define DAC_DATH_DATA1_MASK 0xFu
mbed_official 146:f64d43ff0c18 3229 #define DAC_DATH_DATA1_SHIFT 0
mbed_official 146:f64d43ff0c18 3230 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
mbed_official 146:f64d43ff0c18 3231 /* SR Bit Fields */
mbed_official 146:f64d43ff0c18 3232 #define DAC_SR_DACBFRPBF_MASK 0x1u
mbed_official 146:f64d43ff0c18 3233 #define DAC_SR_DACBFRPBF_SHIFT 0
mbed_official 146:f64d43ff0c18 3234 #define DAC_SR_DACBFRPTF_MASK 0x2u
mbed_official 146:f64d43ff0c18 3235 #define DAC_SR_DACBFRPTF_SHIFT 1
mbed_official 146:f64d43ff0c18 3236 #define DAC_SR_DACBFWMF_MASK 0x4u
mbed_official 146:f64d43ff0c18 3237 #define DAC_SR_DACBFWMF_SHIFT 2
mbed_official 146:f64d43ff0c18 3238 /* C0 Bit Fields */
mbed_official 146:f64d43ff0c18 3239 #define DAC_C0_DACBBIEN_MASK 0x1u
mbed_official 146:f64d43ff0c18 3240 #define DAC_C0_DACBBIEN_SHIFT 0
mbed_official 146:f64d43ff0c18 3241 #define DAC_C0_DACBTIEN_MASK 0x2u
mbed_official 146:f64d43ff0c18 3242 #define DAC_C0_DACBTIEN_SHIFT 1
mbed_official 146:f64d43ff0c18 3243 #define DAC_C0_DACBWIEN_MASK 0x4u
mbed_official 146:f64d43ff0c18 3244 #define DAC_C0_DACBWIEN_SHIFT 2
mbed_official 146:f64d43ff0c18 3245 #define DAC_C0_LPEN_MASK 0x8u
mbed_official 146:f64d43ff0c18 3246 #define DAC_C0_LPEN_SHIFT 3
mbed_official 146:f64d43ff0c18 3247 #define DAC_C0_DACSWTRG_MASK 0x10u
mbed_official 146:f64d43ff0c18 3248 #define DAC_C0_DACSWTRG_SHIFT 4
mbed_official 146:f64d43ff0c18 3249 #define DAC_C0_DACTRGSEL_MASK 0x20u
mbed_official 146:f64d43ff0c18 3250 #define DAC_C0_DACTRGSEL_SHIFT 5
mbed_official 146:f64d43ff0c18 3251 #define DAC_C0_DACRFS_MASK 0x40u
mbed_official 146:f64d43ff0c18 3252 #define DAC_C0_DACRFS_SHIFT 6
mbed_official 146:f64d43ff0c18 3253 #define DAC_C0_DACEN_MASK 0x80u
mbed_official 146:f64d43ff0c18 3254 #define DAC_C0_DACEN_SHIFT 7
mbed_official 146:f64d43ff0c18 3255 /* C1 Bit Fields */
mbed_official 146:f64d43ff0c18 3256 #define DAC_C1_DACBFEN_MASK 0x1u
mbed_official 146:f64d43ff0c18 3257 #define DAC_C1_DACBFEN_SHIFT 0
mbed_official 146:f64d43ff0c18 3258 #define DAC_C1_DACBFMD_MASK 0x6u
mbed_official 146:f64d43ff0c18 3259 #define DAC_C1_DACBFMD_SHIFT 1
mbed_official 146:f64d43ff0c18 3260 #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
mbed_official 146:f64d43ff0c18 3261 #define DAC_C1_DACBFWM_MASK 0x18u
mbed_official 146:f64d43ff0c18 3262 #define DAC_C1_DACBFWM_SHIFT 3
mbed_official 146:f64d43ff0c18 3263 #define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
mbed_official 146:f64d43ff0c18 3264 #define DAC_C1_DMAEN_MASK 0x80u
mbed_official 146:f64d43ff0c18 3265 #define DAC_C1_DMAEN_SHIFT 7
mbed_official 146:f64d43ff0c18 3266 /* C2 Bit Fields */
mbed_official 146:f64d43ff0c18 3267 #define DAC_C2_DACBFUP_MASK 0xFu
mbed_official 146:f64d43ff0c18 3268 #define DAC_C2_DACBFUP_SHIFT 0
mbed_official 146:f64d43ff0c18 3269 #define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
mbed_official 146:f64d43ff0c18 3270 #define DAC_C2_DACBFRP_MASK 0xF0u
mbed_official 146:f64d43ff0c18 3271 #define DAC_C2_DACBFRP_SHIFT 4
mbed_official 146:f64d43ff0c18 3272 #define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
mbed_official 146:f64d43ff0c18 3273
mbed_official 146:f64d43ff0c18 3274 /*!
mbed_official 146:f64d43ff0c18 3275 * @}
mbed_official 146:f64d43ff0c18 3276 */ /* end of group DAC_Register_Masks */
mbed_official 146:f64d43ff0c18 3277
mbed_official 146:f64d43ff0c18 3278
mbed_official 146:f64d43ff0c18 3279 /* DAC - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 3280 /** Peripheral DAC0 base address */
mbed_official 146:f64d43ff0c18 3281 #define DAC0_BASE (0x400CC000u)
mbed_official 146:f64d43ff0c18 3282 /** Peripheral DAC0 base pointer */
mbed_official 146:f64d43ff0c18 3283 #define DAC0 ((DAC_Type *)DAC0_BASE)
mbed_official 146:f64d43ff0c18 3284 #define DAC0_BASE_PTR (DAC0)
mbed_official 146:f64d43ff0c18 3285 /** Peripheral DAC1 base address */
mbed_official 146:f64d43ff0c18 3286 #define DAC1_BASE (0x400CD000u)
mbed_official 146:f64d43ff0c18 3287 /** Peripheral DAC1 base pointer */
mbed_official 146:f64d43ff0c18 3288 #define DAC1 ((DAC_Type *)DAC1_BASE)
mbed_official 146:f64d43ff0c18 3289 #define DAC1_BASE_PTR (DAC1)
mbed_official 146:f64d43ff0c18 3290 /** Array initializer of DAC peripheral base pointers */
mbed_official 146:f64d43ff0c18 3291 #define DAC_BASES { DAC0, DAC1 }
mbed_official 146:f64d43ff0c18 3292
mbed_official 146:f64d43ff0c18 3293 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3294 -- DAC - Register accessor macros
mbed_official 146:f64d43ff0c18 3295 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 3296
mbed_official 146:f64d43ff0c18 3297 /*!
mbed_official 146:f64d43ff0c18 3298 * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
mbed_official 146:f64d43ff0c18 3299 * @{
mbed_official 146:f64d43ff0c18 3300 */
mbed_official 146:f64d43ff0c18 3301
mbed_official 146:f64d43ff0c18 3302
mbed_official 146:f64d43ff0c18 3303 /* DAC - Register instance definitions */
mbed_official 146:f64d43ff0c18 3304 /* DAC0 */
mbed_official 146:f64d43ff0c18 3305 #define DAC0_DAT0L DAC_DATL_REG(DAC0,0)
mbed_official 146:f64d43ff0c18 3306 #define DAC0_DAT0H DAC_DATH_REG(DAC0,0)
mbed_official 146:f64d43ff0c18 3307 #define DAC0_DAT1L DAC_DATL_REG(DAC0,1)
mbed_official 146:f64d43ff0c18 3308 #define DAC0_DAT1H DAC_DATH_REG(DAC0,1)
mbed_official 146:f64d43ff0c18 3309 #define DAC0_DAT2L DAC_DATL_REG(DAC0,2)
mbed_official 146:f64d43ff0c18 3310 #define DAC0_DAT2H DAC_DATH_REG(DAC0,2)
mbed_official 146:f64d43ff0c18 3311 #define DAC0_DAT3L DAC_DATL_REG(DAC0,3)
mbed_official 146:f64d43ff0c18 3312 #define DAC0_DAT3H DAC_DATH_REG(DAC0,3)
mbed_official 146:f64d43ff0c18 3313 #define DAC0_DAT4L DAC_DATL_REG(DAC0,4)
mbed_official 146:f64d43ff0c18 3314 #define DAC0_DAT4H DAC_DATH_REG(DAC0,4)
mbed_official 146:f64d43ff0c18 3315 #define DAC0_DAT5L DAC_DATL_REG(DAC0,5)
mbed_official 146:f64d43ff0c18 3316 #define DAC0_DAT5H DAC_DATH_REG(DAC0,5)
mbed_official 146:f64d43ff0c18 3317 #define DAC0_DAT6L DAC_DATL_REG(DAC0,6)
mbed_official 146:f64d43ff0c18 3318 #define DAC0_DAT6H DAC_DATH_REG(DAC0,6)
mbed_official 146:f64d43ff0c18 3319 #define DAC0_DAT7L DAC_DATL_REG(DAC0,7)
mbed_official 146:f64d43ff0c18 3320 #define DAC0_DAT7H DAC_DATH_REG(DAC0,7)
mbed_official 146:f64d43ff0c18 3321 #define DAC0_DAT8L DAC_DATL_REG(DAC0,8)
mbed_official 146:f64d43ff0c18 3322 #define DAC0_DAT8H DAC_DATH_REG(DAC0,8)
mbed_official 146:f64d43ff0c18 3323 #define DAC0_DAT9L DAC_DATL_REG(DAC0,9)
mbed_official 146:f64d43ff0c18 3324 #define DAC0_DAT9H DAC_DATH_REG(DAC0,9)
mbed_official 146:f64d43ff0c18 3325 #define DAC0_DAT10L DAC_DATL_REG(DAC0,10)
mbed_official 146:f64d43ff0c18 3326 #define DAC0_DAT10H DAC_DATH_REG(DAC0,10)
mbed_official 146:f64d43ff0c18 3327 #define DAC0_DAT11L DAC_DATL_REG(DAC0,11)
mbed_official 146:f64d43ff0c18 3328 #define DAC0_DAT11H DAC_DATH_REG(DAC0,11)
mbed_official 146:f64d43ff0c18 3329 #define DAC0_DAT12L DAC_DATL_REG(DAC0,12)
mbed_official 146:f64d43ff0c18 3330 #define DAC0_DAT12H DAC_DATH_REG(DAC0,12)
mbed_official 146:f64d43ff0c18 3331 #define DAC0_DAT13L DAC_DATL_REG(DAC0,13)
mbed_official 146:f64d43ff0c18 3332 #define DAC0_DAT13H DAC_DATH_REG(DAC0,13)
mbed_official 146:f64d43ff0c18 3333 #define DAC0_DAT14L DAC_DATL_REG(DAC0,14)
mbed_official 146:f64d43ff0c18 3334 #define DAC0_DAT14H DAC_DATH_REG(DAC0,14)
mbed_official 146:f64d43ff0c18 3335 #define DAC0_DAT15L DAC_DATL_REG(DAC0,15)
mbed_official 146:f64d43ff0c18 3336 #define DAC0_DAT15H DAC_DATH_REG(DAC0,15)
mbed_official 146:f64d43ff0c18 3337 #define DAC0_SR DAC_SR_REG(DAC0)
mbed_official 146:f64d43ff0c18 3338 #define DAC0_C0 DAC_C0_REG(DAC0)
mbed_official 146:f64d43ff0c18 3339 #define DAC0_C1 DAC_C1_REG(DAC0)
mbed_official 146:f64d43ff0c18 3340 #define DAC0_C2 DAC_C2_REG(DAC0)
mbed_official 146:f64d43ff0c18 3341 /* DAC1 */
mbed_official 146:f64d43ff0c18 3342 #define DAC1_DAT0L DAC_DATL_REG(DAC1,0)
mbed_official 146:f64d43ff0c18 3343 #define DAC1_DAT0H DAC_DATH_REG(DAC1,0)
mbed_official 146:f64d43ff0c18 3344 #define DAC1_DAT1L DAC_DATL_REG(DAC1,1)
mbed_official 146:f64d43ff0c18 3345 #define DAC1_DAT1H DAC_DATH_REG(DAC1,1)
mbed_official 146:f64d43ff0c18 3346 #define DAC1_DAT2L DAC_DATL_REG(DAC1,2)
mbed_official 146:f64d43ff0c18 3347 #define DAC1_DAT2H DAC_DATH_REG(DAC1,2)
mbed_official 146:f64d43ff0c18 3348 #define DAC1_DAT3L DAC_DATL_REG(DAC1,3)
mbed_official 146:f64d43ff0c18 3349 #define DAC1_DAT3H DAC_DATH_REG(DAC1,3)
mbed_official 146:f64d43ff0c18 3350 #define DAC1_DAT4L DAC_DATL_REG(DAC1,4)
mbed_official 146:f64d43ff0c18 3351 #define DAC1_DAT4H DAC_DATH_REG(DAC1,4)
mbed_official 146:f64d43ff0c18 3352 #define DAC1_DAT5L DAC_DATL_REG(DAC1,5)
mbed_official 146:f64d43ff0c18 3353 #define DAC1_DAT5H DAC_DATH_REG(DAC1,5)
mbed_official 146:f64d43ff0c18 3354 #define DAC1_DAT6L DAC_DATL_REG(DAC1,6)
mbed_official 146:f64d43ff0c18 3355 #define DAC1_DAT6H DAC_DATH_REG(DAC1,6)
mbed_official 146:f64d43ff0c18 3356 #define DAC1_DAT7L DAC_DATL_REG(DAC1,7)
mbed_official 146:f64d43ff0c18 3357 #define DAC1_DAT7H DAC_DATH_REG(DAC1,7)
mbed_official 146:f64d43ff0c18 3358 #define DAC1_DAT8L DAC_DATL_REG(DAC1,8)
mbed_official 146:f64d43ff0c18 3359 #define DAC1_DAT8H DAC_DATH_REG(DAC1,8)
mbed_official 146:f64d43ff0c18 3360 #define DAC1_DAT9L DAC_DATL_REG(DAC1,9)
mbed_official 146:f64d43ff0c18 3361 #define DAC1_DAT9H DAC_DATH_REG(DAC1,9)
mbed_official 146:f64d43ff0c18 3362 #define DAC1_DAT10L DAC_DATL_REG(DAC1,10)
mbed_official 146:f64d43ff0c18 3363 #define DAC1_DAT10H DAC_DATH_REG(DAC1,10)
mbed_official 146:f64d43ff0c18 3364 #define DAC1_DAT11L DAC_DATL_REG(DAC1,11)
mbed_official 146:f64d43ff0c18 3365 #define DAC1_DAT11H DAC_DATH_REG(DAC1,11)
mbed_official 146:f64d43ff0c18 3366 #define DAC1_DAT12L DAC_DATL_REG(DAC1,12)
mbed_official 146:f64d43ff0c18 3367 #define DAC1_DAT12H DAC_DATH_REG(DAC1,12)
mbed_official 146:f64d43ff0c18 3368 #define DAC1_DAT13L DAC_DATL_REG(DAC1,13)
mbed_official 146:f64d43ff0c18 3369 #define DAC1_DAT13H DAC_DATH_REG(DAC1,13)
mbed_official 146:f64d43ff0c18 3370 #define DAC1_DAT14L DAC_DATL_REG(DAC1,14)
mbed_official 146:f64d43ff0c18 3371 #define DAC1_DAT14H DAC_DATH_REG(DAC1,14)
mbed_official 146:f64d43ff0c18 3372 #define DAC1_DAT15L DAC_DATL_REG(DAC1,15)
mbed_official 146:f64d43ff0c18 3373 #define DAC1_DAT15H DAC_DATH_REG(DAC1,15)
mbed_official 146:f64d43ff0c18 3374 #define DAC1_SR DAC_SR_REG(DAC1)
mbed_official 146:f64d43ff0c18 3375 #define DAC1_C0 DAC_C0_REG(DAC1)
mbed_official 146:f64d43ff0c18 3376 #define DAC1_C1 DAC_C1_REG(DAC1)
mbed_official 146:f64d43ff0c18 3377 #define DAC1_C2 DAC_C2_REG(DAC1)
mbed_official 146:f64d43ff0c18 3378
mbed_official 146:f64d43ff0c18 3379 /* DAC - Register array accessors */
mbed_official 146:f64d43ff0c18 3380 #define DAC0_DATL(index) DAC_DATL_REG(DAC0,index)
mbed_official 146:f64d43ff0c18 3381 #define DAC1_DATL(index) DAC_DATL_REG(DAC1,index)
mbed_official 146:f64d43ff0c18 3382 #define DAC0_DATH(index) DAC_DATH_REG(DAC0,index)
mbed_official 146:f64d43ff0c18 3383 #define DAC1_DATH(index) DAC_DATH_REG(DAC1,index)
mbed_official 146:f64d43ff0c18 3384
mbed_official 146:f64d43ff0c18 3385 /*!
mbed_official 146:f64d43ff0c18 3386 * @}
mbed_official 146:f64d43ff0c18 3387 */ /* end of group DAC_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 3388
mbed_official 146:f64d43ff0c18 3389
mbed_official 146:f64d43ff0c18 3390 /*!
mbed_official 146:f64d43ff0c18 3391 * @}
mbed_official 146:f64d43ff0c18 3392 */ /* end of group DAC_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 3393
mbed_official 146:f64d43ff0c18 3394
mbed_official 146:f64d43ff0c18 3395 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3396 -- DMA Peripheral Access Layer
mbed_official 146:f64d43ff0c18 3397 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 3398
mbed_official 146:f64d43ff0c18 3399 /*!
mbed_official 146:f64d43ff0c18 3400 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
mbed_official 146:f64d43ff0c18 3401 * @{
mbed_official 146:f64d43ff0c18 3402 */
mbed_official 146:f64d43ff0c18 3403
mbed_official 146:f64d43ff0c18 3404 /** DMA - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 3405 typedef struct {
mbed_official 146:f64d43ff0c18 3406 __IO uint32_t CR; /**< Control Register, offset: 0x0 */
mbed_official 146:f64d43ff0c18 3407 __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
mbed_official 146:f64d43ff0c18 3408 uint8_t RESERVED_0[4];
mbed_official 146:f64d43ff0c18 3409 __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
mbed_official 146:f64d43ff0c18 3410 uint8_t RESERVED_1[4];
mbed_official 146:f64d43ff0c18 3411 __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
mbed_official 146:f64d43ff0c18 3412 __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
mbed_official 146:f64d43ff0c18 3413 __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
mbed_official 146:f64d43ff0c18 3414 __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
mbed_official 146:f64d43ff0c18 3415 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
mbed_official 146:f64d43ff0c18 3416 __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
mbed_official 146:f64d43ff0c18 3417 __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
mbed_official 146:f64d43ff0c18 3418 __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
mbed_official 146:f64d43ff0c18 3419 __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
mbed_official 146:f64d43ff0c18 3420 uint8_t RESERVED_2[4];
mbed_official 146:f64d43ff0c18 3421 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
mbed_official 146:f64d43ff0c18 3422 uint8_t RESERVED_3[4];
mbed_official 146:f64d43ff0c18 3423 __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
mbed_official 146:f64d43ff0c18 3424 uint8_t RESERVED_4[4];
mbed_official 146:f64d43ff0c18 3425 __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
mbed_official 146:f64d43ff0c18 3426 uint8_t RESERVED_5[200];
mbed_official 146:f64d43ff0c18 3427 __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
mbed_official 146:f64d43ff0c18 3428 __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
mbed_official 146:f64d43ff0c18 3429 __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
mbed_official 146:f64d43ff0c18 3430 __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
mbed_official 146:f64d43ff0c18 3431 __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
mbed_official 146:f64d43ff0c18 3432 __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
mbed_official 146:f64d43ff0c18 3433 __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
mbed_official 146:f64d43ff0c18 3434 __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
mbed_official 146:f64d43ff0c18 3435 __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
mbed_official 146:f64d43ff0c18 3436 __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
mbed_official 146:f64d43ff0c18 3437 __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
mbed_official 146:f64d43ff0c18 3438 __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
mbed_official 146:f64d43ff0c18 3439 __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
mbed_official 146:f64d43ff0c18 3440 __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
mbed_official 146:f64d43ff0c18 3441 __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
mbed_official 146:f64d43ff0c18 3442 __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
mbed_official 146:f64d43ff0c18 3443 uint8_t RESERVED_6[3824];
mbed_official 146:f64d43ff0c18 3444 struct { /* offset: 0x1000, array step: 0x20 */
mbed_official 146:f64d43ff0c18 3445 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
mbed_official 146:f64d43ff0c18 3446 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
mbed_official 146:f64d43ff0c18 3447 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
mbed_official 146:f64d43ff0c18 3448 union { /* offset: 0x1008, array step: 0x20 */
mbed_official 146:f64d43ff0c18 3449 __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
mbed_official 146:f64d43ff0c18 3450 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
mbed_official 146:f64d43ff0c18 3451 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
mbed_official 146:f64d43ff0c18 3452 };
mbed_official 146:f64d43ff0c18 3453 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
mbed_official 146:f64d43ff0c18 3454 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
mbed_official 146:f64d43ff0c18 3455 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
mbed_official 146:f64d43ff0c18 3456 union { /* offset: 0x1016, array step: 0x20 */
mbed_official 146:f64d43ff0c18 3457 __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
mbed_official 146:f64d43ff0c18 3458 __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
mbed_official 146:f64d43ff0c18 3459 };
mbed_official 146:f64d43ff0c18 3460 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
mbed_official 146:f64d43ff0c18 3461 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
mbed_official 146:f64d43ff0c18 3462 union { /* offset: 0x101E, array step: 0x20 */
mbed_official 146:f64d43ff0c18 3463 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
mbed_official 146:f64d43ff0c18 3464 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
mbed_official 146:f64d43ff0c18 3465 };
mbed_official 146:f64d43ff0c18 3466 } TCD[16];
mbed_official 146:f64d43ff0c18 3467 } DMA_Type, *DMA_MemMapPtr;
mbed_official 146:f64d43ff0c18 3468
mbed_official 146:f64d43ff0c18 3469 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3470 -- DMA - Register accessor macros
mbed_official 146:f64d43ff0c18 3471 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 3472
mbed_official 146:f64d43ff0c18 3473 /*!
mbed_official 146:f64d43ff0c18 3474 * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
mbed_official 146:f64d43ff0c18 3475 * @{
mbed_official 146:f64d43ff0c18 3476 */
mbed_official 146:f64d43ff0c18 3477
mbed_official 146:f64d43ff0c18 3478
mbed_official 146:f64d43ff0c18 3479 /* DMA - Register accessors */
mbed_official 146:f64d43ff0c18 3480 #define DMA_CR_REG(base) ((base)->CR)
mbed_official 146:f64d43ff0c18 3481 #define DMA_ES_REG(base) ((base)->ES)
mbed_official 146:f64d43ff0c18 3482 #define DMA_ERQ_REG(base) ((base)->ERQ)
mbed_official 146:f64d43ff0c18 3483 #define DMA_EEI_REG(base) ((base)->EEI)
mbed_official 146:f64d43ff0c18 3484 #define DMA_CEEI_REG(base) ((base)->CEEI)
mbed_official 146:f64d43ff0c18 3485 #define DMA_SEEI_REG(base) ((base)->SEEI)
mbed_official 146:f64d43ff0c18 3486 #define DMA_CERQ_REG(base) ((base)->CERQ)
mbed_official 146:f64d43ff0c18 3487 #define DMA_SERQ_REG(base) ((base)->SERQ)
mbed_official 146:f64d43ff0c18 3488 #define DMA_CDNE_REG(base) ((base)->CDNE)
mbed_official 146:f64d43ff0c18 3489 #define DMA_SSRT_REG(base) ((base)->SSRT)
mbed_official 146:f64d43ff0c18 3490 #define DMA_CERR_REG(base) ((base)->CERR)
mbed_official 146:f64d43ff0c18 3491 #define DMA_CINT_REG(base) ((base)->CINT)
mbed_official 146:f64d43ff0c18 3492 #define DMA_INT_REG(base) ((base)->INT)
mbed_official 146:f64d43ff0c18 3493 #define DMA_ERR_REG(base) ((base)->ERR)
mbed_official 146:f64d43ff0c18 3494 #define DMA_HRS_REG(base) ((base)->HRS)
mbed_official 146:f64d43ff0c18 3495 #define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3)
mbed_official 146:f64d43ff0c18 3496 #define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2)
mbed_official 146:f64d43ff0c18 3497 #define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1)
mbed_official 146:f64d43ff0c18 3498 #define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0)
mbed_official 146:f64d43ff0c18 3499 #define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7)
mbed_official 146:f64d43ff0c18 3500 #define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6)
mbed_official 146:f64d43ff0c18 3501 #define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5)
mbed_official 146:f64d43ff0c18 3502 #define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4)
mbed_official 146:f64d43ff0c18 3503 #define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11)
mbed_official 146:f64d43ff0c18 3504 #define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10)
mbed_official 146:f64d43ff0c18 3505 #define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9)
mbed_official 146:f64d43ff0c18 3506 #define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8)
mbed_official 146:f64d43ff0c18 3507 #define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15)
mbed_official 146:f64d43ff0c18 3508 #define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14)
mbed_official 146:f64d43ff0c18 3509 #define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13)
mbed_official 146:f64d43ff0c18 3510 #define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12)
mbed_official 146:f64d43ff0c18 3511 #define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR)
mbed_official 146:f64d43ff0c18 3512 #define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF)
mbed_official 146:f64d43ff0c18 3513 #define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR)
mbed_official 146:f64d43ff0c18 3514 #define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO)
mbed_official 146:f64d43ff0c18 3515 #define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO)
mbed_official 146:f64d43ff0c18 3516 #define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES)
mbed_official 146:f64d43ff0c18 3517 #define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST)
mbed_official 146:f64d43ff0c18 3518 #define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR)
mbed_official 146:f64d43ff0c18 3519 #define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF)
mbed_official 146:f64d43ff0c18 3520 #define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO)
mbed_official 146:f64d43ff0c18 3521 #define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES)
mbed_official 146:f64d43ff0c18 3522 #define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA)
mbed_official 146:f64d43ff0c18 3523 #define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR)
mbed_official 146:f64d43ff0c18 3524 #define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO)
mbed_official 146:f64d43ff0c18 3525 #define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES)
mbed_official 146:f64d43ff0c18 3526
mbed_official 146:f64d43ff0c18 3527 /*!
mbed_official 146:f64d43ff0c18 3528 * @}
mbed_official 146:f64d43ff0c18 3529 */ /* end of group DMA_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 3530
mbed_official 146:f64d43ff0c18 3531
mbed_official 146:f64d43ff0c18 3532 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3533 -- DMA Register Masks
mbed_official 146:f64d43ff0c18 3534 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 3535
mbed_official 146:f64d43ff0c18 3536 /*!
mbed_official 146:f64d43ff0c18 3537 * @addtogroup DMA_Register_Masks DMA Register Masks
mbed_official 146:f64d43ff0c18 3538 * @{
mbed_official 146:f64d43ff0c18 3539 */
mbed_official 146:f64d43ff0c18 3540
mbed_official 146:f64d43ff0c18 3541 /* CR Bit Fields */
mbed_official 146:f64d43ff0c18 3542 #define DMA_CR_EDBG_MASK 0x2u
mbed_official 146:f64d43ff0c18 3543 #define DMA_CR_EDBG_SHIFT 1
mbed_official 146:f64d43ff0c18 3544 #define DMA_CR_ERCA_MASK 0x4u
mbed_official 146:f64d43ff0c18 3545 #define DMA_CR_ERCA_SHIFT 2
mbed_official 146:f64d43ff0c18 3546 #define DMA_CR_HOE_MASK 0x10u
mbed_official 146:f64d43ff0c18 3547 #define DMA_CR_HOE_SHIFT 4
mbed_official 146:f64d43ff0c18 3548 #define DMA_CR_HALT_MASK 0x20u
mbed_official 146:f64d43ff0c18 3549 #define DMA_CR_HALT_SHIFT 5
mbed_official 146:f64d43ff0c18 3550 #define DMA_CR_CLM_MASK 0x40u
mbed_official 146:f64d43ff0c18 3551 #define DMA_CR_CLM_SHIFT 6
mbed_official 146:f64d43ff0c18 3552 #define DMA_CR_EMLM_MASK 0x80u
mbed_official 146:f64d43ff0c18 3553 #define DMA_CR_EMLM_SHIFT 7
mbed_official 146:f64d43ff0c18 3554 #define DMA_CR_ECX_MASK 0x10000u
mbed_official 146:f64d43ff0c18 3555 #define DMA_CR_ECX_SHIFT 16
mbed_official 146:f64d43ff0c18 3556 #define DMA_CR_CX_MASK 0x20000u
mbed_official 146:f64d43ff0c18 3557 #define DMA_CR_CX_SHIFT 17
mbed_official 146:f64d43ff0c18 3558 /* ES Bit Fields */
mbed_official 146:f64d43ff0c18 3559 #define DMA_ES_DBE_MASK 0x1u
mbed_official 146:f64d43ff0c18 3560 #define DMA_ES_DBE_SHIFT 0
mbed_official 146:f64d43ff0c18 3561 #define DMA_ES_SBE_MASK 0x2u
mbed_official 146:f64d43ff0c18 3562 #define DMA_ES_SBE_SHIFT 1
mbed_official 146:f64d43ff0c18 3563 #define DMA_ES_SGE_MASK 0x4u
mbed_official 146:f64d43ff0c18 3564 #define DMA_ES_SGE_SHIFT 2
mbed_official 146:f64d43ff0c18 3565 #define DMA_ES_NCE_MASK 0x8u
mbed_official 146:f64d43ff0c18 3566 #define DMA_ES_NCE_SHIFT 3
mbed_official 146:f64d43ff0c18 3567 #define DMA_ES_DOE_MASK 0x10u
mbed_official 146:f64d43ff0c18 3568 #define DMA_ES_DOE_SHIFT 4
mbed_official 146:f64d43ff0c18 3569 #define DMA_ES_DAE_MASK 0x20u
mbed_official 146:f64d43ff0c18 3570 #define DMA_ES_DAE_SHIFT 5
mbed_official 146:f64d43ff0c18 3571 #define DMA_ES_SOE_MASK 0x40u
mbed_official 146:f64d43ff0c18 3572 #define DMA_ES_SOE_SHIFT 6
mbed_official 146:f64d43ff0c18 3573 #define DMA_ES_SAE_MASK 0x80u
mbed_official 146:f64d43ff0c18 3574 #define DMA_ES_SAE_SHIFT 7
mbed_official 146:f64d43ff0c18 3575 #define DMA_ES_ERRCHN_MASK 0xF00u
mbed_official 146:f64d43ff0c18 3576 #define DMA_ES_ERRCHN_SHIFT 8
mbed_official 146:f64d43ff0c18 3577 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
mbed_official 146:f64d43ff0c18 3578 #define DMA_ES_CPE_MASK 0x4000u
mbed_official 146:f64d43ff0c18 3579 #define DMA_ES_CPE_SHIFT 14
mbed_official 146:f64d43ff0c18 3580 #define DMA_ES_ECX_MASK 0x10000u
mbed_official 146:f64d43ff0c18 3581 #define DMA_ES_ECX_SHIFT 16
mbed_official 146:f64d43ff0c18 3582 #define DMA_ES_VLD_MASK 0x80000000u
mbed_official 146:f64d43ff0c18 3583 #define DMA_ES_VLD_SHIFT 31
mbed_official 146:f64d43ff0c18 3584 /* ERQ Bit Fields */
mbed_official 146:f64d43ff0c18 3585 #define DMA_ERQ_ERQ0_MASK 0x1u
mbed_official 146:f64d43ff0c18 3586 #define DMA_ERQ_ERQ0_SHIFT 0
mbed_official 146:f64d43ff0c18 3587 #define DMA_ERQ_ERQ1_MASK 0x2u
mbed_official 146:f64d43ff0c18 3588 #define DMA_ERQ_ERQ1_SHIFT 1
mbed_official 146:f64d43ff0c18 3589 #define DMA_ERQ_ERQ2_MASK 0x4u
mbed_official 146:f64d43ff0c18 3590 #define DMA_ERQ_ERQ2_SHIFT 2
mbed_official 146:f64d43ff0c18 3591 #define DMA_ERQ_ERQ3_MASK 0x8u
mbed_official 146:f64d43ff0c18 3592 #define DMA_ERQ_ERQ3_SHIFT 3
mbed_official 146:f64d43ff0c18 3593 #define DMA_ERQ_ERQ4_MASK 0x10u
mbed_official 146:f64d43ff0c18 3594 #define DMA_ERQ_ERQ4_SHIFT 4
mbed_official 146:f64d43ff0c18 3595 #define DMA_ERQ_ERQ5_MASK 0x20u
mbed_official 146:f64d43ff0c18 3596 #define DMA_ERQ_ERQ5_SHIFT 5
mbed_official 146:f64d43ff0c18 3597 #define DMA_ERQ_ERQ6_MASK 0x40u
mbed_official 146:f64d43ff0c18 3598 #define DMA_ERQ_ERQ6_SHIFT 6
mbed_official 146:f64d43ff0c18 3599 #define DMA_ERQ_ERQ7_MASK 0x80u
mbed_official 146:f64d43ff0c18 3600 #define DMA_ERQ_ERQ7_SHIFT 7
mbed_official 146:f64d43ff0c18 3601 #define DMA_ERQ_ERQ8_MASK 0x100u
mbed_official 146:f64d43ff0c18 3602 #define DMA_ERQ_ERQ8_SHIFT 8
mbed_official 146:f64d43ff0c18 3603 #define DMA_ERQ_ERQ9_MASK 0x200u
mbed_official 146:f64d43ff0c18 3604 #define DMA_ERQ_ERQ9_SHIFT 9
mbed_official 146:f64d43ff0c18 3605 #define DMA_ERQ_ERQ10_MASK 0x400u
mbed_official 146:f64d43ff0c18 3606 #define DMA_ERQ_ERQ10_SHIFT 10
mbed_official 146:f64d43ff0c18 3607 #define DMA_ERQ_ERQ11_MASK 0x800u
mbed_official 146:f64d43ff0c18 3608 #define DMA_ERQ_ERQ11_SHIFT 11
mbed_official 146:f64d43ff0c18 3609 #define DMA_ERQ_ERQ12_MASK 0x1000u
mbed_official 146:f64d43ff0c18 3610 #define DMA_ERQ_ERQ12_SHIFT 12
mbed_official 146:f64d43ff0c18 3611 #define DMA_ERQ_ERQ13_MASK 0x2000u
mbed_official 146:f64d43ff0c18 3612 #define DMA_ERQ_ERQ13_SHIFT 13
mbed_official 146:f64d43ff0c18 3613 #define DMA_ERQ_ERQ14_MASK 0x4000u
mbed_official 146:f64d43ff0c18 3614 #define DMA_ERQ_ERQ14_SHIFT 14
mbed_official 146:f64d43ff0c18 3615 #define DMA_ERQ_ERQ15_MASK 0x8000u
mbed_official 146:f64d43ff0c18 3616 #define DMA_ERQ_ERQ15_SHIFT 15
mbed_official 146:f64d43ff0c18 3617 /* EEI Bit Fields */
mbed_official 146:f64d43ff0c18 3618 #define DMA_EEI_EEI0_MASK 0x1u
mbed_official 146:f64d43ff0c18 3619 #define DMA_EEI_EEI0_SHIFT 0
mbed_official 146:f64d43ff0c18 3620 #define DMA_EEI_EEI1_MASK 0x2u
mbed_official 146:f64d43ff0c18 3621 #define DMA_EEI_EEI1_SHIFT 1
mbed_official 146:f64d43ff0c18 3622 #define DMA_EEI_EEI2_MASK 0x4u
mbed_official 146:f64d43ff0c18 3623 #define DMA_EEI_EEI2_SHIFT 2
mbed_official 146:f64d43ff0c18 3624 #define DMA_EEI_EEI3_MASK 0x8u
mbed_official 146:f64d43ff0c18 3625 #define DMA_EEI_EEI3_SHIFT 3
mbed_official 146:f64d43ff0c18 3626 #define DMA_EEI_EEI4_MASK 0x10u
mbed_official 146:f64d43ff0c18 3627 #define DMA_EEI_EEI4_SHIFT 4
mbed_official 146:f64d43ff0c18 3628 #define DMA_EEI_EEI5_MASK 0x20u
mbed_official 146:f64d43ff0c18 3629 #define DMA_EEI_EEI5_SHIFT 5
mbed_official 146:f64d43ff0c18 3630 #define DMA_EEI_EEI6_MASK 0x40u
mbed_official 146:f64d43ff0c18 3631 #define DMA_EEI_EEI6_SHIFT 6
mbed_official 146:f64d43ff0c18 3632 #define DMA_EEI_EEI7_MASK 0x80u
mbed_official 146:f64d43ff0c18 3633 #define DMA_EEI_EEI7_SHIFT 7
mbed_official 146:f64d43ff0c18 3634 #define DMA_EEI_EEI8_MASK 0x100u
mbed_official 146:f64d43ff0c18 3635 #define DMA_EEI_EEI8_SHIFT 8
mbed_official 146:f64d43ff0c18 3636 #define DMA_EEI_EEI9_MASK 0x200u
mbed_official 146:f64d43ff0c18 3637 #define DMA_EEI_EEI9_SHIFT 9
mbed_official 146:f64d43ff0c18 3638 #define DMA_EEI_EEI10_MASK 0x400u
mbed_official 146:f64d43ff0c18 3639 #define DMA_EEI_EEI10_SHIFT 10
mbed_official 146:f64d43ff0c18 3640 #define DMA_EEI_EEI11_MASK 0x800u
mbed_official 146:f64d43ff0c18 3641 #define DMA_EEI_EEI11_SHIFT 11
mbed_official 146:f64d43ff0c18 3642 #define DMA_EEI_EEI12_MASK 0x1000u
mbed_official 146:f64d43ff0c18 3643 #define DMA_EEI_EEI12_SHIFT 12
mbed_official 146:f64d43ff0c18 3644 #define DMA_EEI_EEI13_MASK 0x2000u
mbed_official 146:f64d43ff0c18 3645 #define DMA_EEI_EEI13_SHIFT 13
mbed_official 146:f64d43ff0c18 3646 #define DMA_EEI_EEI14_MASK 0x4000u
mbed_official 146:f64d43ff0c18 3647 #define DMA_EEI_EEI14_SHIFT 14
mbed_official 146:f64d43ff0c18 3648 #define DMA_EEI_EEI15_MASK 0x8000u
mbed_official 146:f64d43ff0c18 3649 #define DMA_EEI_EEI15_SHIFT 15
mbed_official 146:f64d43ff0c18 3650 /* CEEI Bit Fields */
mbed_official 146:f64d43ff0c18 3651 #define DMA_CEEI_CEEI_MASK 0xFu
mbed_official 146:f64d43ff0c18 3652 #define DMA_CEEI_CEEI_SHIFT 0
mbed_official 146:f64d43ff0c18 3653 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
mbed_official 146:f64d43ff0c18 3654 #define DMA_CEEI_CAEE_MASK 0x40u
mbed_official 146:f64d43ff0c18 3655 #define DMA_CEEI_CAEE_SHIFT 6
mbed_official 146:f64d43ff0c18 3656 #define DMA_CEEI_NOP_MASK 0x80u
mbed_official 146:f64d43ff0c18 3657 #define DMA_CEEI_NOP_SHIFT 7
mbed_official 146:f64d43ff0c18 3658 /* SEEI Bit Fields */
mbed_official 146:f64d43ff0c18 3659 #define DMA_SEEI_SEEI_MASK 0xFu
mbed_official 146:f64d43ff0c18 3660 #define DMA_SEEI_SEEI_SHIFT 0
mbed_official 146:f64d43ff0c18 3661 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
mbed_official 146:f64d43ff0c18 3662 #define DMA_SEEI_SAEE_MASK 0x40u
mbed_official 146:f64d43ff0c18 3663 #define DMA_SEEI_SAEE_SHIFT 6
mbed_official 146:f64d43ff0c18 3664 #define DMA_SEEI_NOP_MASK 0x80u
mbed_official 146:f64d43ff0c18 3665 #define DMA_SEEI_NOP_SHIFT 7
mbed_official 146:f64d43ff0c18 3666 /* CERQ Bit Fields */
mbed_official 146:f64d43ff0c18 3667 #define DMA_CERQ_CERQ_MASK 0xFu
mbed_official 146:f64d43ff0c18 3668 #define DMA_CERQ_CERQ_SHIFT 0
mbed_official 146:f64d43ff0c18 3669 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
mbed_official 146:f64d43ff0c18 3670 #define DMA_CERQ_CAER_MASK 0x40u
mbed_official 146:f64d43ff0c18 3671 #define DMA_CERQ_CAER_SHIFT 6
mbed_official 146:f64d43ff0c18 3672 #define DMA_CERQ_NOP_MASK 0x80u
mbed_official 146:f64d43ff0c18 3673 #define DMA_CERQ_NOP_SHIFT 7
mbed_official 146:f64d43ff0c18 3674 /* SERQ Bit Fields */
mbed_official 146:f64d43ff0c18 3675 #define DMA_SERQ_SERQ_MASK 0xFu
mbed_official 146:f64d43ff0c18 3676 #define DMA_SERQ_SERQ_SHIFT 0
mbed_official 146:f64d43ff0c18 3677 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
mbed_official 146:f64d43ff0c18 3678 #define DMA_SERQ_SAER_MASK 0x40u
mbed_official 146:f64d43ff0c18 3679 #define DMA_SERQ_SAER_SHIFT 6
mbed_official 146:f64d43ff0c18 3680 #define DMA_SERQ_NOP_MASK 0x80u
mbed_official 146:f64d43ff0c18 3681 #define DMA_SERQ_NOP_SHIFT 7
mbed_official 146:f64d43ff0c18 3682 /* CDNE Bit Fields */
mbed_official 146:f64d43ff0c18 3683 #define DMA_CDNE_CDNE_MASK 0xFu
mbed_official 146:f64d43ff0c18 3684 #define DMA_CDNE_CDNE_SHIFT 0
mbed_official 146:f64d43ff0c18 3685 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
mbed_official 146:f64d43ff0c18 3686 #define DMA_CDNE_CADN_MASK 0x40u
mbed_official 146:f64d43ff0c18 3687 #define DMA_CDNE_CADN_SHIFT 6
mbed_official 146:f64d43ff0c18 3688 #define DMA_CDNE_NOP_MASK 0x80u
mbed_official 146:f64d43ff0c18 3689 #define DMA_CDNE_NOP_SHIFT 7
mbed_official 146:f64d43ff0c18 3690 /* SSRT Bit Fields */
mbed_official 146:f64d43ff0c18 3691 #define DMA_SSRT_SSRT_MASK 0xFu
mbed_official 146:f64d43ff0c18 3692 #define DMA_SSRT_SSRT_SHIFT 0
mbed_official 146:f64d43ff0c18 3693 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
mbed_official 146:f64d43ff0c18 3694 #define DMA_SSRT_SAST_MASK 0x40u
mbed_official 146:f64d43ff0c18 3695 #define DMA_SSRT_SAST_SHIFT 6
mbed_official 146:f64d43ff0c18 3696 #define DMA_SSRT_NOP_MASK 0x80u
mbed_official 146:f64d43ff0c18 3697 #define DMA_SSRT_NOP_SHIFT 7
mbed_official 146:f64d43ff0c18 3698 /* CERR Bit Fields */
mbed_official 146:f64d43ff0c18 3699 #define DMA_CERR_CERR_MASK 0xFu
mbed_official 146:f64d43ff0c18 3700 #define DMA_CERR_CERR_SHIFT 0
mbed_official 146:f64d43ff0c18 3701 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
mbed_official 146:f64d43ff0c18 3702 #define DMA_CERR_CAEI_MASK 0x40u
mbed_official 146:f64d43ff0c18 3703 #define DMA_CERR_CAEI_SHIFT 6
mbed_official 146:f64d43ff0c18 3704 #define DMA_CERR_NOP_MASK 0x80u
mbed_official 146:f64d43ff0c18 3705 #define DMA_CERR_NOP_SHIFT 7
mbed_official 146:f64d43ff0c18 3706 /* CINT Bit Fields */
mbed_official 146:f64d43ff0c18 3707 #define DMA_CINT_CINT_MASK 0xFu
mbed_official 146:f64d43ff0c18 3708 #define DMA_CINT_CINT_SHIFT 0
mbed_official 146:f64d43ff0c18 3709 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
mbed_official 146:f64d43ff0c18 3710 #define DMA_CINT_CAIR_MASK 0x40u
mbed_official 146:f64d43ff0c18 3711 #define DMA_CINT_CAIR_SHIFT 6
mbed_official 146:f64d43ff0c18 3712 #define DMA_CINT_NOP_MASK 0x80u
mbed_official 146:f64d43ff0c18 3713 #define DMA_CINT_NOP_SHIFT 7
mbed_official 146:f64d43ff0c18 3714 /* INT Bit Fields */
mbed_official 146:f64d43ff0c18 3715 #define DMA_INT_INT0_MASK 0x1u
mbed_official 146:f64d43ff0c18 3716 #define DMA_INT_INT0_SHIFT 0
mbed_official 146:f64d43ff0c18 3717 #define DMA_INT_INT1_MASK 0x2u
mbed_official 146:f64d43ff0c18 3718 #define DMA_INT_INT1_SHIFT 1
mbed_official 146:f64d43ff0c18 3719 #define DMA_INT_INT2_MASK 0x4u
mbed_official 146:f64d43ff0c18 3720 #define DMA_INT_INT2_SHIFT 2
mbed_official 146:f64d43ff0c18 3721 #define DMA_INT_INT3_MASK 0x8u
mbed_official 146:f64d43ff0c18 3722 #define DMA_INT_INT3_SHIFT 3
mbed_official 146:f64d43ff0c18 3723 #define DMA_INT_INT4_MASK 0x10u
mbed_official 146:f64d43ff0c18 3724 #define DMA_INT_INT4_SHIFT 4
mbed_official 146:f64d43ff0c18 3725 #define DMA_INT_INT5_MASK 0x20u
mbed_official 146:f64d43ff0c18 3726 #define DMA_INT_INT5_SHIFT 5
mbed_official 146:f64d43ff0c18 3727 #define DMA_INT_INT6_MASK 0x40u
mbed_official 146:f64d43ff0c18 3728 #define DMA_INT_INT6_SHIFT 6
mbed_official 146:f64d43ff0c18 3729 #define DMA_INT_INT7_MASK 0x80u
mbed_official 146:f64d43ff0c18 3730 #define DMA_INT_INT7_SHIFT 7
mbed_official 146:f64d43ff0c18 3731 #define DMA_INT_INT8_MASK 0x100u
mbed_official 146:f64d43ff0c18 3732 #define DMA_INT_INT8_SHIFT 8
mbed_official 146:f64d43ff0c18 3733 #define DMA_INT_INT9_MASK 0x200u
mbed_official 146:f64d43ff0c18 3734 #define DMA_INT_INT9_SHIFT 9
mbed_official 146:f64d43ff0c18 3735 #define DMA_INT_INT10_MASK 0x400u
mbed_official 146:f64d43ff0c18 3736 #define DMA_INT_INT10_SHIFT 10
mbed_official 146:f64d43ff0c18 3737 #define DMA_INT_INT11_MASK 0x800u
mbed_official 146:f64d43ff0c18 3738 #define DMA_INT_INT11_SHIFT 11
mbed_official 146:f64d43ff0c18 3739 #define DMA_INT_INT12_MASK 0x1000u
mbed_official 146:f64d43ff0c18 3740 #define DMA_INT_INT12_SHIFT 12
mbed_official 146:f64d43ff0c18 3741 #define DMA_INT_INT13_MASK 0x2000u
mbed_official 146:f64d43ff0c18 3742 #define DMA_INT_INT13_SHIFT 13
mbed_official 146:f64d43ff0c18 3743 #define DMA_INT_INT14_MASK 0x4000u
mbed_official 146:f64d43ff0c18 3744 #define DMA_INT_INT14_SHIFT 14
mbed_official 146:f64d43ff0c18 3745 #define DMA_INT_INT15_MASK 0x8000u
mbed_official 146:f64d43ff0c18 3746 #define DMA_INT_INT15_SHIFT 15
mbed_official 146:f64d43ff0c18 3747 /* ERR Bit Fields */
mbed_official 146:f64d43ff0c18 3748 #define DMA_ERR_ERR0_MASK 0x1u
mbed_official 146:f64d43ff0c18 3749 #define DMA_ERR_ERR0_SHIFT 0
mbed_official 146:f64d43ff0c18 3750 #define DMA_ERR_ERR1_MASK 0x2u
mbed_official 146:f64d43ff0c18 3751 #define DMA_ERR_ERR1_SHIFT 1
mbed_official 146:f64d43ff0c18 3752 #define DMA_ERR_ERR2_MASK 0x4u
mbed_official 146:f64d43ff0c18 3753 #define DMA_ERR_ERR2_SHIFT 2
mbed_official 146:f64d43ff0c18 3754 #define DMA_ERR_ERR3_MASK 0x8u
mbed_official 146:f64d43ff0c18 3755 #define DMA_ERR_ERR3_SHIFT 3
mbed_official 146:f64d43ff0c18 3756 #define DMA_ERR_ERR4_MASK 0x10u
mbed_official 146:f64d43ff0c18 3757 #define DMA_ERR_ERR4_SHIFT 4
mbed_official 146:f64d43ff0c18 3758 #define DMA_ERR_ERR5_MASK 0x20u
mbed_official 146:f64d43ff0c18 3759 #define DMA_ERR_ERR5_SHIFT 5
mbed_official 146:f64d43ff0c18 3760 #define DMA_ERR_ERR6_MASK 0x40u
mbed_official 146:f64d43ff0c18 3761 #define DMA_ERR_ERR6_SHIFT 6
mbed_official 146:f64d43ff0c18 3762 #define DMA_ERR_ERR7_MASK 0x80u
mbed_official 146:f64d43ff0c18 3763 #define DMA_ERR_ERR7_SHIFT 7
mbed_official 146:f64d43ff0c18 3764 #define DMA_ERR_ERR8_MASK 0x100u
mbed_official 146:f64d43ff0c18 3765 #define DMA_ERR_ERR8_SHIFT 8
mbed_official 146:f64d43ff0c18 3766 #define DMA_ERR_ERR9_MASK 0x200u
mbed_official 146:f64d43ff0c18 3767 #define DMA_ERR_ERR9_SHIFT 9
mbed_official 146:f64d43ff0c18 3768 #define DMA_ERR_ERR10_MASK 0x400u
mbed_official 146:f64d43ff0c18 3769 #define DMA_ERR_ERR10_SHIFT 10
mbed_official 146:f64d43ff0c18 3770 #define DMA_ERR_ERR11_MASK 0x800u
mbed_official 146:f64d43ff0c18 3771 #define DMA_ERR_ERR11_SHIFT 11
mbed_official 146:f64d43ff0c18 3772 #define DMA_ERR_ERR12_MASK 0x1000u
mbed_official 146:f64d43ff0c18 3773 #define DMA_ERR_ERR12_SHIFT 12
mbed_official 146:f64d43ff0c18 3774 #define DMA_ERR_ERR13_MASK 0x2000u
mbed_official 146:f64d43ff0c18 3775 #define DMA_ERR_ERR13_SHIFT 13
mbed_official 146:f64d43ff0c18 3776 #define DMA_ERR_ERR14_MASK 0x4000u
mbed_official 146:f64d43ff0c18 3777 #define DMA_ERR_ERR14_SHIFT 14
mbed_official 146:f64d43ff0c18 3778 #define DMA_ERR_ERR15_MASK 0x8000u
mbed_official 146:f64d43ff0c18 3779 #define DMA_ERR_ERR15_SHIFT 15
mbed_official 146:f64d43ff0c18 3780 /* HRS Bit Fields */
mbed_official 146:f64d43ff0c18 3781 #define DMA_HRS_HRS0_MASK 0x1u
mbed_official 146:f64d43ff0c18 3782 #define DMA_HRS_HRS0_SHIFT 0
mbed_official 146:f64d43ff0c18 3783 #define DMA_HRS_HRS1_MASK 0x2u
mbed_official 146:f64d43ff0c18 3784 #define DMA_HRS_HRS1_SHIFT 1
mbed_official 146:f64d43ff0c18 3785 #define DMA_HRS_HRS2_MASK 0x4u
mbed_official 146:f64d43ff0c18 3786 #define DMA_HRS_HRS2_SHIFT 2
mbed_official 146:f64d43ff0c18 3787 #define DMA_HRS_HRS3_MASK 0x8u
mbed_official 146:f64d43ff0c18 3788 #define DMA_HRS_HRS3_SHIFT 3
mbed_official 146:f64d43ff0c18 3789 #define DMA_HRS_HRS4_MASK 0x10u
mbed_official 146:f64d43ff0c18 3790 #define DMA_HRS_HRS4_SHIFT 4
mbed_official 146:f64d43ff0c18 3791 #define DMA_HRS_HRS5_MASK 0x20u
mbed_official 146:f64d43ff0c18 3792 #define DMA_HRS_HRS5_SHIFT 5
mbed_official 146:f64d43ff0c18 3793 #define DMA_HRS_HRS6_MASK 0x40u
mbed_official 146:f64d43ff0c18 3794 #define DMA_HRS_HRS6_SHIFT 6
mbed_official 146:f64d43ff0c18 3795 #define DMA_HRS_HRS7_MASK 0x80u
mbed_official 146:f64d43ff0c18 3796 #define DMA_HRS_HRS7_SHIFT 7
mbed_official 146:f64d43ff0c18 3797 #define DMA_HRS_HRS8_MASK 0x100u
mbed_official 146:f64d43ff0c18 3798 #define DMA_HRS_HRS8_SHIFT 8
mbed_official 146:f64d43ff0c18 3799 #define DMA_HRS_HRS9_MASK 0x200u
mbed_official 146:f64d43ff0c18 3800 #define DMA_HRS_HRS9_SHIFT 9
mbed_official 146:f64d43ff0c18 3801 #define DMA_HRS_HRS10_MASK 0x400u
mbed_official 146:f64d43ff0c18 3802 #define DMA_HRS_HRS10_SHIFT 10
mbed_official 146:f64d43ff0c18 3803 #define DMA_HRS_HRS11_MASK 0x800u
mbed_official 146:f64d43ff0c18 3804 #define DMA_HRS_HRS11_SHIFT 11
mbed_official 146:f64d43ff0c18 3805 #define DMA_HRS_HRS12_MASK 0x1000u
mbed_official 146:f64d43ff0c18 3806 #define DMA_HRS_HRS12_SHIFT 12
mbed_official 146:f64d43ff0c18 3807 #define DMA_HRS_HRS13_MASK 0x2000u
mbed_official 146:f64d43ff0c18 3808 #define DMA_HRS_HRS13_SHIFT 13
mbed_official 146:f64d43ff0c18 3809 #define DMA_HRS_HRS14_MASK 0x4000u
mbed_official 146:f64d43ff0c18 3810 #define DMA_HRS_HRS14_SHIFT 14
mbed_official 146:f64d43ff0c18 3811 #define DMA_HRS_HRS15_MASK 0x8000u
mbed_official 146:f64d43ff0c18 3812 #define DMA_HRS_HRS15_SHIFT 15
mbed_official 146:f64d43ff0c18 3813 /* DCHPRI3 Bit Fields */
mbed_official 146:f64d43ff0c18 3814 #define DMA_DCHPRI3_CHPRI_MASK 0xFu
mbed_official 146:f64d43ff0c18 3815 #define DMA_DCHPRI3_CHPRI_SHIFT 0
mbed_official 146:f64d43ff0c18 3816 #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
mbed_official 146:f64d43ff0c18 3817 #define DMA_DCHPRI3_DPA_MASK 0x40u
mbed_official 146:f64d43ff0c18 3818 #define DMA_DCHPRI3_DPA_SHIFT 6
mbed_official 146:f64d43ff0c18 3819 #define DMA_DCHPRI3_ECP_MASK 0x80u
mbed_official 146:f64d43ff0c18 3820 #define DMA_DCHPRI3_ECP_SHIFT 7
mbed_official 146:f64d43ff0c18 3821 /* DCHPRI2 Bit Fields */
mbed_official 146:f64d43ff0c18 3822 #define DMA_DCHPRI2_CHPRI_MASK 0xFu
mbed_official 146:f64d43ff0c18 3823 #define DMA_DCHPRI2_CHPRI_SHIFT 0
mbed_official 146:f64d43ff0c18 3824 #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
mbed_official 146:f64d43ff0c18 3825 #define DMA_DCHPRI2_DPA_MASK 0x40u
mbed_official 146:f64d43ff0c18 3826 #define DMA_DCHPRI2_DPA_SHIFT 6
mbed_official 146:f64d43ff0c18 3827 #define DMA_DCHPRI2_ECP_MASK 0x80u
mbed_official 146:f64d43ff0c18 3828 #define DMA_DCHPRI2_ECP_SHIFT 7
mbed_official 146:f64d43ff0c18 3829 /* DCHPRI1 Bit Fields */
mbed_official 146:f64d43ff0c18 3830 #define DMA_DCHPRI1_CHPRI_MASK 0xFu
mbed_official 146:f64d43ff0c18 3831 #define DMA_DCHPRI1_CHPRI_SHIFT 0
mbed_official 146:f64d43ff0c18 3832 #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
mbed_official 146:f64d43ff0c18 3833 #define DMA_DCHPRI1_DPA_MASK 0x40u
mbed_official 146:f64d43ff0c18 3834 #define DMA_DCHPRI1_DPA_SHIFT 6
mbed_official 146:f64d43ff0c18 3835 #define DMA_DCHPRI1_ECP_MASK 0x80u
mbed_official 146:f64d43ff0c18 3836 #define DMA_DCHPRI1_ECP_SHIFT 7
mbed_official 146:f64d43ff0c18 3837 /* DCHPRI0 Bit Fields */
mbed_official 146:f64d43ff0c18 3838 #define DMA_DCHPRI0_CHPRI_MASK 0xFu
mbed_official 146:f64d43ff0c18 3839 #define DMA_DCHPRI0_CHPRI_SHIFT 0
mbed_official 146:f64d43ff0c18 3840 #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
mbed_official 146:f64d43ff0c18 3841 #define DMA_DCHPRI0_DPA_MASK 0x40u
mbed_official 146:f64d43ff0c18 3842 #define DMA_DCHPRI0_DPA_SHIFT 6
mbed_official 146:f64d43ff0c18 3843 #define DMA_DCHPRI0_ECP_MASK 0x80u
mbed_official 146:f64d43ff0c18 3844 #define DMA_DCHPRI0_ECP_SHIFT 7
mbed_official 146:f64d43ff0c18 3845 /* DCHPRI7 Bit Fields */
mbed_official 146:f64d43ff0c18 3846 #define DMA_DCHPRI7_CHPRI_MASK 0xFu
mbed_official 146:f64d43ff0c18 3847 #define DMA_DCHPRI7_CHPRI_SHIFT 0
mbed_official 146:f64d43ff0c18 3848 #define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_CHPRI_SHIFT))&DMA_DCHPRI7_CHPRI_MASK)
mbed_official 146:f64d43ff0c18 3849 #define DMA_DCHPRI7_DPA_MASK 0x40u
mbed_official 146:f64d43ff0c18 3850 #define DMA_DCHPRI7_DPA_SHIFT 6
mbed_official 146:f64d43ff0c18 3851 #define DMA_DCHPRI7_ECP_MASK 0x80u
mbed_official 146:f64d43ff0c18 3852 #define DMA_DCHPRI7_ECP_SHIFT 7
mbed_official 146:f64d43ff0c18 3853 /* DCHPRI6 Bit Fields */
mbed_official 146:f64d43ff0c18 3854 #define DMA_DCHPRI6_CHPRI_MASK 0xFu
mbed_official 146:f64d43ff0c18 3855 #define DMA_DCHPRI6_CHPRI_SHIFT 0
mbed_official 146:f64d43ff0c18 3856 #define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_CHPRI_SHIFT))&DMA_DCHPRI6_CHPRI_MASK)
mbed_official 146:f64d43ff0c18 3857 #define DMA_DCHPRI6_DPA_MASK 0x40u
mbed_official 146:f64d43ff0c18 3858 #define DMA_DCHPRI6_DPA_SHIFT 6
mbed_official 146:f64d43ff0c18 3859 #define DMA_DCHPRI6_ECP_MASK 0x80u
mbed_official 146:f64d43ff0c18 3860 #define DMA_DCHPRI6_ECP_SHIFT 7
mbed_official 146:f64d43ff0c18 3861 /* DCHPRI5 Bit Fields */
mbed_official 146:f64d43ff0c18 3862 #define DMA_DCHPRI5_CHPRI_MASK 0xFu
mbed_official 146:f64d43ff0c18 3863 #define DMA_DCHPRI5_CHPRI_SHIFT 0
mbed_official 146:f64d43ff0c18 3864 #define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_CHPRI_SHIFT))&DMA_DCHPRI5_CHPRI_MASK)
mbed_official 146:f64d43ff0c18 3865 #define DMA_DCHPRI5_DPA_MASK 0x40u
mbed_official 146:f64d43ff0c18 3866 #define DMA_DCHPRI5_DPA_SHIFT 6
mbed_official 146:f64d43ff0c18 3867 #define DMA_DCHPRI5_ECP_MASK 0x80u
mbed_official 146:f64d43ff0c18 3868 #define DMA_DCHPRI5_ECP_SHIFT 7
mbed_official 146:f64d43ff0c18 3869 /* DCHPRI4 Bit Fields */
mbed_official 146:f64d43ff0c18 3870 #define DMA_DCHPRI4_CHPRI_MASK 0xFu
mbed_official 146:f64d43ff0c18 3871 #define DMA_DCHPRI4_CHPRI_SHIFT 0
mbed_official 146:f64d43ff0c18 3872 #define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_CHPRI_SHIFT))&DMA_DCHPRI4_CHPRI_MASK)
mbed_official 146:f64d43ff0c18 3873 #define DMA_DCHPRI4_DPA_MASK 0x40u
mbed_official 146:f64d43ff0c18 3874 #define DMA_DCHPRI4_DPA_SHIFT 6
mbed_official 146:f64d43ff0c18 3875 #define DMA_DCHPRI4_ECP_MASK 0x80u
mbed_official 146:f64d43ff0c18 3876 #define DMA_DCHPRI4_ECP_SHIFT 7
mbed_official 146:f64d43ff0c18 3877 /* DCHPRI11 Bit Fields */
mbed_official 146:f64d43ff0c18 3878 #define DMA_DCHPRI11_CHPRI_MASK 0xFu
mbed_official 146:f64d43ff0c18 3879 #define DMA_DCHPRI11_CHPRI_SHIFT 0
mbed_official 146:f64d43ff0c18 3880 #define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_CHPRI_SHIFT))&DMA_DCHPRI11_CHPRI_MASK)
mbed_official 146:f64d43ff0c18 3881 #define DMA_DCHPRI11_DPA_MASK 0x40u
mbed_official 146:f64d43ff0c18 3882 #define DMA_DCHPRI11_DPA_SHIFT 6
mbed_official 146:f64d43ff0c18 3883 #define DMA_DCHPRI11_ECP_MASK 0x80u
mbed_official 146:f64d43ff0c18 3884 #define DMA_DCHPRI11_ECP_SHIFT 7
mbed_official 146:f64d43ff0c18 3885 /* DCHPRI10 Bit Fields */
mbed_official 146:f64d43ff0c18 3886 #define DMA_DCHPRI10_CHPRI_MASK 0xFu
mbed_official 146:f64d43ff0c18 3887 #define DMA_DCHPRI10_CHPRI_SHIFT 0
mbed_official 146:f64d43ff0c18 3888 #define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_CHPRI_SHIFT))&DMA_DCHPRI10_CHPRI_MASK)
mbed_official 146:f64d43ff0c18 3889 #define DMA_DCHPRI10_DPA_MASK 0x40u
mbed_official 146:f64d43ff0c18 3890 #define DMA_DCHPRI10_DPA_SHIFT 6
mbed_official 146:f64d43ff0c18 3891 #define DMA_DCHPRI10_ECP_MASK 0x80u
mbed_official 146:f64d43ff0c18 3892 #define DMA_DCHPRI10_ECP_SHIFT 7
mbed_official 146:f64d43ff0c18 3893 /* DCHPRI9 Bit Fields */
mbed_official 146:f64d43ff0c18 3894 #define DMA_DCHPRI9_CHPRI_MASK 0xFu
mbed_official 146:f64d43ff0c18 3895 #define DMA_DCHPRI9_CHPRI_SHIFT 0
mbed_official 146:f64d43ff0c18 3896 #define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_CHPRI_SHIFT))&DMA_DCHPRI9_CHPRI_MASK)
mbed_official 146:f64d43ff0c18 3897 #define DMA_DCHPRI9_DPA_MASK 0x40u
mbed_official 146:f64d43ff0c18 3898 #define DMA_DCHPRI9_DPA_SHIFT 6
mbed_official 146:f64d43ff0c18 3899 #define DMA_DCHPRI9_ECP_MASK 0x80u
mbed_official 146:f64d43ff0c18 3900 #define DMA_DCHPRI9_ECP_SHIFT 7
mbed_official 146:f64d43ff0c18 3901 /* DCHPRI8 Bit Fields */
mbed_official 146:f64d43ff0c18 3902 #define DMA_DCHPRI8_CHPRI_MASK 0xFu
mbed_official 146:f64d43ff0c18 3903 #define DMA_DCHPRI8_CHPRI_SHIFT 0
mbed_official 146:f64d43ff0c18 3904 #define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_CHPRI_SHIFT))&DMA_DCHPRI8_CHPRI_MASK)
mbed_official 146:f64d43ff0c18 3905 #define DMA_DCHPRI8_DPA_MASK 0x40u
mbed_official 146:f64d43ff0c18 3906 #define DMA_DCHPRI8_DPA_SHIFT 6
mbed_official 146:f64d43ff0c18 3907 #define DMA_DCHPRI8_ECP_MASK 0x80u
mbed_official 146:f64d43ff0c18 3908 #define DMA_DCHPRI8_ECP_SHIFT 7
mbed_official 146:f64d43ff0c18 3909 /* DCHPRI15 Bit Fields */
mbed_official 146:f64d43ff0c18 3910 #define DMA_DCHPRI15_CHPRI_MASK 0xFu
mbed_official 146:f64d43ff0c18 3911 #define DMA_DCHPRI15_CHPRI_SHIFT 0
mbed_official 146:f64d43ff0c18 3912 #define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_CHPRI_SHIFT))&DMA_DCHPRI15_CHPRI_MASK)
mbed_official 146:f64d43ff0c18 3913 #define DMA_DCHPRI15_DPA_MASK 0x40u
mbed_official 146:f64d43ff0c18 3914 #define DMA_DCHPRI15_DPA_SHIFT 6
mbed_official 146:f64d43ff0c18 3915 #define DMA_DCHPRI15_ECP_MASK 0x80u
mbed_official 146:f64d43ff0c18 3916 #define DMA_DCHPRI15_ECP_SHIFT 7
mbed_official 146:f64d43ff0c18 3917 /* DCHPRI14 Bit Fields */
mbed_official 146:f64d43ff0c18 3918 #define DMA_DCHPRI14_CHPRI_MASK 0xFu
mbed_official 146:f64d43ff0c18 3919 #define DMA_DCHPRI14_CHPRI_SHIFT 0
mbed_official 146:f64d43ff0c18 3920 #define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_CHPRI_SHIFT))&DMA_DCHPRI14_CHPRI_MASK)
mbed_official 146:f64d43ff0c18 3921 #define DMA_DCHPRI14_DPA_MASK 0x40u
mbed_official 146:f64d43ff0c18 3922 #define DMA_DCHPRI14_DPA_SHIFT 6
mbed_official 146:f64d43ff0c18 3923 #define DMA_DCHPRI14_ECP_MASK 0x80u
mbed_official 146:f64d43ff0c18 3924 #define DMA_DCHPRI14_ECP_SHIFT 7
mbed_official 146:f64d43ff0c18 3925 /* DCHPRI13 Bit Fields */
mbed_official 146:f64d43ff0c18 3926 #define DMA_DCHPRI13_CHPRI_MASK 0xFu
mbed_official 146:f64d43ff0c18 3927 #define DMA_DCHPRI13_CHPRI_SHIFT 0
mbed_official 146:f64d43ff0c18 3928 #define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_CHPRI_SHIFT))&DMA_DCHPRI13_CHPRI_MASK)
mbed_official 146:f64d43ff0c18 3929 #define DMA_DCHPRI13_DPA_MASK 0x40u
mbed_official 146:f64d43ff0c18 3930 #define DMA_DCHPRI13_DPA_SHIFT 6
mbed_official 146:f64d43ff0c18 3931 #define DMA_DCHPRI13_ECP_MASK 0x80u
mbed_official 146:f64d43ff0c18 3932 #define DMA_DCHPRI13_ECP_SHIFT 7
mbed_official 146:f64d43ff0c18 3933 /* DCHPRI12 Bit Fields */
mbed_official 146:f64d43ff0c18 3934 #define DMA_DCHPRI12_CHPRI_MASK 0xFu
mbed_official 146:f64d43ff0c18 3935 #define DMA_DCHPRI12_CHPRI_SHIFT 0
mbed_official 146:f64d43ff0c18 3936 #define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_CHPRI_SHIFT))&DMA_DCHPRI12_CHPRI_MASK)
mbed_official 146:f64d43ff0c18 3937 #define DMA_DCHPRI12_DPA_MASK 0x40u
mbed_official 146:f64d43ff0c18 3938 #define DMA_DCHPRI12_DPA_SHIFT 6
mbed_official 146:f64d43ff0c18 3939 #define DMA_DCHPRI12_ECP_MASK 0x80u
mbed_official 146:f64d43ff0c18 3940 #define DMA_DCHPRI12_ECP_SHIFT 7
mbed_official 146:f64d43ff0c18 3941 /* SADDR Bit Fields */
mbed_official 146:f64d43ff0c18 3942 #define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 3943 #define DMA_SADDR_SADDR_SHIFT 0
mbed_official 146:f64d43ff0c18 3944 #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
mbed_official 146:f64d43ff0c18 3945 /* SOFF Bit Fields */
mbed_official 146:f64d43ff0c18 3946 #define DMA_SOFF_SOFF_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 3947 #define DMA_SOFF_SOFF_SHIFT 0
mbed_official 146:f64d43ff0c18 3948 #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
mbed_official 146:f64d43ff0c18 3949 /* ATTR Bit Fields */
mbed_official 146:f64d43ff0c18 3950 #define DMA_ATTR_DSIZE_MASK 0x7u
mbed_official 146:f64d43ff0c18 3951 #define DMA_ATTR_DSIZE_SHIFT 0
mbed_official 146:f64d43ff0c18 3952 #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
mbed_official 146:f64d43ff0c18 3953 #define DMA_ATTR_DMOD_MASK 0xF8u
mbed_official 146:f64d43ff0c18 3954 #define DMA_ATTR_DMOD_SHIFT 3
mbed_official 146:f64d43ff0c18 3955 #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
mbed_official 146:f64d43ff0c18 3956 #define DMA_ATTR_SSIZE_MASK 0x700u
mbed_official 146:f64d43ff0c18 3957 #define DMA_ATTR_SSIZE_SHIFT 8
mbed_official 146:f64d43ff0c18 3958 #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
mbed_official 146:f64d43ff0c18 3959 #define DMA_ATTR_SMOD_MASK 0xF800u
mbed_official 146:f64d43ff0c18 3960 #define DMA_ATTR_SMOD_SHIFT 11
mbed_official 146:f64d43ff0c18 3961 #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
mbed_official 146:f64d43ff0c18 3962 /* NBYTES_MLNO Bit Fields */
mbed_official 146:f64d43ff0c18 3963 #define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 3964 #define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
mbed_official 146:f64d43ff0c18 3965 #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
mbed_official 146:f64d43ff0c18 3966 /* NBYTES_MLOFFNO Bit Fields */
mbed_official 146:f64d43ff0c18 3967 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
mbed_official 146:f64d43ff0c18 3968 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
mbed_official 146:f64d43ff0c18 3969 #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
mbed_official 146:f64d43ff0c18 3970 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 3971 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
mbed_official 146:f64d43ff0c18 3972 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
mbed_official 146:f64d43ff0c18 3973 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
mbed_official 146:f64d43ff0c18 3974 /* NBYTES_MLOFFYES Bit Fields */
mbed_official 146:f64d43ff0c18 3975 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
mbed_official 146:f64d43ff0c18 3976 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
mbed_official 146:f64d43ff0c18 3977 #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
mbed_official 146:f64d43ff0c18 3978 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
mbed_official 146:f64d43ff0c18 3979 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
mbed_official 146:f64d43ff0c18 3980 #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
mbed_official 146:f64d43ff0c18 3981 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 3982 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
mbed_official 146:f64d43ff0c18 3983 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
mbed_official 146:f64d43ff0c18 3984 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
mbed_official 146:f64d43ff0c18 3985 /* SLAST Bit Fields */
mbed_official 146:f64d43ff0c18 3986 #define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 3987 #define DMA_SLAST_SLAST_SHIFT 0
mbed_official 146:f64d43ff0c18 3988 #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
mbed_official 146:f64d43ff0c18 3989 /* DADDR Bit Fields */
mbed_official 146:f64d43ff0c18 3990 #define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 3991 #define DMA_DADDR_DADDR_SHIFT 0
mbed_official 146:f64d43ff0c18 3992 #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
mbed_official 146:f64d43ff0c18 3993 /* DOFF Bit Fields */
mbed_official 146:f64d43ff0c18 3994 #define DMA_DOFF_DOFF_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 3995 #define DMA_DOFF_DOFF_SHIFT 0
mbed_official 146:f64d43ff0c18 3996 #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
mbed_official 146:f64d43ff0c18 3997 /* CITER_ELINKNO Bit Fields */
mbed_official 146:f64d43ff0c18 3998 #define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
mbed_official 146:f64d43ff0c18 3999 #define DMA_CITER_ELINKNO_CITER_SHIFT 0
mbed_official 146:f64d43ff0c18 4000 #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
mbed_official 146:f64d43ff0c18 4001 #define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
mbed_official 146:f64d43ff0c18 4002 #define DMA_CITER_ELINKNO_ELINK_SHIFT 15
mbed_official 146:f64d43ff0c18 4003 /* CITER_ELINKYES Bit Fields */
mbed_official 146:f64d43ff0c18 4004 #define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
mbed_official 146:f64d43ff0c18 4005 #define DMA_CITER_ELINKYES_CITER_SHIFT 0
mbed_official 146:f64d43ff0c18 4006 #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
mbed_official 146:f64d43ff0c18 4007 #define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u
mbed_official 146:f64d43ff0c18 4008 #define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
mbed_official 146:f64d43ff0c18 4009 #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
mbed_official 146:f64d43ff0c18 4010 #define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
mbed_official 146:f64d43ff0c18 4011 #define DMA_CITER_ELINKYES_ELINK_SHIFT 15
mbed_official 146:f64d43ff0c18 4012 /* DLAST_SGA Bit Fields */
mbed_official 146:f64d43ff0c18 4013 #define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 4014 #define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
mbed_official 146:f64d43ff0c18 4015 #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
mbed_official 146:f64d43ff0c18 4016 /* CSR Bit Fields */
mbed_official 146:f64d43ff0c18 4017 #define DMA_CSR_START_MASK 0x1u
mbed_official 146:f64d43ff0c18 4018 #define DMA_CSR_START_SHIFT 0
mbed_official 146:f64d43ff0c18 4019 #define DMA_CSR_INTMAJOR_MASK 0x2u
mbed_official 146:f64d43ff0c18 4020 #define DMA_CSR_INTMAJOR_SHIFT 1
mbed_official 146:f64d43ff0c18 4021 #define DMA_CSR_INTHALF_MASK 0x4u
mbed_official 146:f64d43ff0c18 4022 #define DMA_CSR_INTHALF_SHIFT 2
mbed_official 146:f64d43ff0c18 4023 #define DMA_CSR_DREQ_MASK 0x8u
mbed_official 146:f64d43ff0c18 4024 #define DMA_CSR_DREQ_SHIFT 3
mbed_official 146:f64d43ff0c18 4025 #define DMA_CSR_ESG_MASK 0x10u
mbed_official 146:f64d43ff0c18 4026 #define DMA_CSR_ESG_SHIFT 4
mbed_official 146:f64d43ff0c18 4027 #define DMA_CSR_MAJORELINK_MASK 0x20u
mbed_official 146:f64d43ff0c18 4028 #define DMA_CSR_MAJORELINK_SHIFT 5
mbed_official 146:f64d43ff0c18 4029 #define DMA_CSR_ACTIVE_MASK 0x40u
mbed_official 146:f64d43ff0c18 4030 #define DMA_CSR_ACTIVE_SHIFT 6
mbed_official 146:f64d43ff0c18 4031 #define DMA_CSR_DONE_MASK 0x80u
mbed_official 146:f64d43ff0c18 4032 #define DMA_CSR_DONE_SHIFT 7
mbed_official 146:f64d43ff0c18 4033 #define DMA_CSR_MAJORLINKCH_MASK 0xF00u
mbed_official 146:f64d43ff0c18 4034 #define DMA_CSR_MAJORLINKCH_SHIFT 8
mbed_official 146:f64d43ff0c18 4035 #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
mbed_official 146:f64d43ff0c18 4036 #define DMA_CSR_BWC_MASK 0xC000u
mbed_official 146:f64d43ff0c18 4037 #define DMA_CSR_BWC_SHIFT 14
mbed_official 146:f64d43ff0c18 4038 #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
mbed_official 146:f64d43ff0c18 4039 /* BITER_ELINKNO Bit Fields */
mbed_official 146:f64d43ff0c18 4040 #define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
mbed_official 146:f64d43ff0c18 4041 #define DMA_BITER_ELINKNO_BITER_SHIFT 0
mbed_official 146:f64d43ff0c18 4042 #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
mbed_official 146:f64d43ff0c18 4043 #define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
mbed_official 146:f64d43ff0c18 4044 #define DMA_BITER_ELINKNO_ELINK_SHIFT 15
mbed_official 146:f64d43ff0c18 4045 /* BITER_ELINKYES Bit Fields */
mbed_official 146:f64d43ff0c18 4046 #define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
mbed_official 146:f64d43ff0c18 4047 #define DMA_BITER_ELINKYES_BITER_SHIFT 0
mbed_official 146:f64d43ff0c18 4048 #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
mbed_official 146:f64d43ff0c18 4049 #define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u
mbed_official 146:f64d43ff0c18 4050 #define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
mbed_official 146:f64d43ff0c18 4051 #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
mbed_official 146:f64d43ff0c18 4052 #define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
mbed_official 146:f64d43ff0c18 4053 #define DMA_BITER_ELINKYES_ELINK_SHIFT 15
mbed_official 146:f64d43ff0c18 4054
mbed_official 146:f64d43ff0c18 4055 /*!
mbed_official 146:f64d43ff0c18 4056 * @}
mbed_official 146:f64d43ff0c18 4057 */ /* end of group DMA_Register_Masks */
mbed_official 146:f64d43ff0c18 4058
mbed_official 146:f64d43ff0c18 4059
mbed_official 146:f64d43ff0c18 4060 /* DMA - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 4061 /** Peripheral DMA base address */
mbed_official 146:f64d43ff0c18 4062 #define DMA_BASE (0x40008000u)
mbed_official 146:f64d43ff0c18 4063 /** Peripheral DMA base pointer */
mbed_official 146:f64d43ff0c18 4064 #define DMA0 ((DMA_Type *)DMA_BASE)
mbed_official 146:f64d43ff0c18 4065 #define DMA_BASE_PTR (DMA0)
mbed_official 146:f64d43ff0c18 4066 /** Array initializer of DMA peripheral base pointers */
mbed_official 146:f64d43ff0c18 4067 #define DMA_BASES { DMA0 }
mbed_official 146:f64d43ff0c18 4068
mbed_official 146:f64d43ff0c18 4069 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4070 -- DMA - Register accessor macros
mbed_official 146:f64d43ff0c18 4071 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 4072
mbed_official 146:f64d43ff0c18 4073 /*!
mbed_official 146:f64d43ff0c18 4074 * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
mbed_official 146:f64d43ff0c18 4075 * @{
mbed_official 146:f64d43ff0c18 4076 */
mbed_official 146:f64d43ff0c18 4077
mbed_official 146:f64d43ff0c18 4078
mbed_official 146:f64d43ff0c18 4079 /* DMA - Register instance definitions */
mbed_official 146:f64d43ff0c18 4080 /* DMA */
mbed_official 146:f64d43ff0c18 4081 #define DMA_CR DMA_CR_REG(DMA0)
mbed_official 146:f64d43ff0c18 4082 #define DMA_ES DMA_ES_REG(DMA0)
mbed_official 146:f64d43ff0c18 4083 #define DMA_ERQ DMA_ERQ_REG(DMA0)
mbed_official 146:f64d43ff0c18 4084 #define DMA_EEI DMA_EEI_REG(DMA0)
mbed_official 146:f64d43ff0c18 4085 #define DMA_CEEI DMA_CEEI_REG(DMA0)
mbed_official 146:f64d43ff0c18 4086 #define DMA_SEEI DMA_SEEI_REG(DMA0)
mbed_official 146:f64d43ff0c18 4087 #define DMA_CERQ DMA_CERQ_REG(DMA0)
mbed_official 146:f64d43ff0c18 4088 #define DMA_SERQ DMA_SERQ_REG(DMA0)
mbed_official 146:f64d43ff0c18 4089 #define DMA_CDNE DMA_CDNE_REG(DMA0)
mbed_official 146:f64d43ff0c18 4090 #define DMA_SSRT DMA_SSRT_REG(DMA0)
mbed_official 146:f64d43ff0c18 4091 #define DMA_CERR DMA_CERR_REG(DMA0)
mbed_official 146:f64d43ff0c18 4092 #define DMA_CINT DMA_CINT_REG(DMA0)
mbed_official 146:f64d43ff0c18 4093 #define DMA_INT DMA_INT_REG(DMA0)
mbed_official 146:f64d43ff0c18 4094 #define DMA_ERR DMA_ERR_REG(DMA0)
mbed_official 146:f64d43ff0c18 4095 #define DMA_HRS DMA_HRS_REG(DMA0)
mbed_official 146:f64d43ff0c18 4096 #define DMA_DCHPRI3 DMA_DCHPRI3_REG(DMA0)
mbed_official 146:f64d43ff0c18 4097 #define DMA_DCHPRI2 DMA_DCHPRI2_REG(DMA0)
mbed_official 146:f64d43ff0c18 4098 #define DMA_DCHPRI1 DMA_DCHPRI1_REG(DMA0)
mbed_official 146:f64d43ff0c18 4099 #define DMA_DCHPRI0 DMA_DCHPRI0_REG(DMA0)
mbed_official 146:f64d43ff0c18 4100 #define DMA_DCHPRI7 DMA_DCHPRI7_REG(DMA0)
mbed_official 146:f64d43ff0c18 4101 #define DMA_DCHPRI6 DMA_DCHPRI6_REG(DMA0)
mbed_official 146:f64d43ff0c18 4102 #define DMA_DCHPRI5 DMA_DCHPRI5_REG(DMA0)
mbed_official 146:f64d43ff0c18 4103 #define DMA_DCHPRI4 DMA_DCHPRI4_REG(DMA0)
mbed_official 146:f64d43ff0c18 4104 #define DMA_DCHPRI11 DMA_DCHPRI11_REG(DMA0)
mbed_official 146:f64d43ff0c18 4105 #define DMA_DCHPRI10 DMA_DCHPRI10_REG(DMA0)
mbed_official 146:f64d43ff0c18 4106 #define DMA_DCHPRI9 DMA_DCHPRI9_REG(DMA0)
mbed_official 146:f64d43ff0c18 4107 #define DMA_DCHPRI8 DMA_DCHPRI8_REG(DMA0)
mbed_official 146:f64d43ff0c18 4108 #define DMA_DCHPRI15 DMA_DCHPRI15_REG(DMA0)
mbed_official 146:f64d43ff0c18 4109 #define DMA_DCHPRI14 DMA_DCHPRI14_REG(DMA0)
mbed_official 146:f64d43ff0c18 4110 #define DMA_DCHPRI13 DMA_DCHPRI13_REG(DMA0)
mbed_official 146:f64d43ff0c18 4111 #define DMA_DCHPRI12 DMA_DCHPRI12_REG(DMA0)
mbed_official 146:f64d43ff0c18 4112 #define DMA_TCD0_SADDR DMA_SADDR_REG(DMA0,0)
mbed_official 146:f64d43ff0c18 4113 #define DMA_TCD0_SOFF DMA_SOFF_REG(DMA0,0)
mbed_official 146:f64d43ff0c18 4114 #define DMA_TCD0_ATTR DMA_ATTR_REG(DMA0,0)
mbed_official 146:f64d43ff0c18 4115 #define DMA_TCD0_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,0)
mbed_official 146:f64d43ff0c18 4116 #define DMA_TCD0_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,0)
mbed_official 146:f64d43ff0c18 4117 #define DMA_TCD0_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,0)
mbed_official 146:f64d43ff0c18 4118 #define DMA_TCD0_SLAST DMA_SLAST_REG(DMA0,0)
mbed_official 146:f64d43ff0c18 4119 #define DMA_TCD0_DADDR DMA_DADDR_REG(DMA0,0)
mbed_official 146:f64d43ff0c18 4120 #define DMA_TCD0_DOFF DMA_DOFF_REG(DMA0,0)
mbed_official 146:f64d43ff0c18 4121 #define DMA_TCD0_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,0)
mbed_official 146:f64d43ff0c18 4122 #define DMA_TCD0_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,0)
mbed_official 146:f64d43ff0c18 4123 #define DMA_TCD0_DLASTSGA DMA_DLAST_SGA_REG(DMA0,0)
mbed_official 146:f64d43ff0c18 4124 #define DMA_TCD0_CSR DMA_CSR_REG(DMA0,0)
mbed_official 146:f64d43ff0c18 4125 #define DMA_TCD0_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,0)
mbed_official 146:f64d43ff0c18 4126 #define DMA_TCD0_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,0)
mbed_official 146:f64d43ff0c18 4127 #define DMA_TCD1_SADDR DMA_SADDR_REG(DMA0,1)
mbed_official 146:f64d43ff0c18 4128 #define DMA_TCD1_SOFF DMA_SOFF_REG(DMA0,1)
mbed_official 146:f64d43ff0c18 4129 #define DMA_TCD1_ATTR DMA_ATTR_REG(DMA0,1)
mbed_official 146:f64d43ff0c18 4130 #define DMA_TCD1_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,1)
mbed_official 146:f64d43ff0c18 4131 #define DMA_TCD1_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,1)
mbed_official 146:f64d43ff0c18 4132 #define DMA_TCD1_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,1)
mbed_official 146:f64d43ff0c18 4133 #define DMA_TCD1_SLAST DMA_SLAST_REG(DMA0,1)
mbed_official 146:f64d43ff0c18 4134 #define DMA_TCD1_DADDR DMA_DADDR_REG(DMA0,1)
mbed_official 146:f64d43ff0c18 4135 #define DMA_TCD1_DOFF DMA_DOFF_REG(DMA0,1)
mbed_official 146:f64d43ff0c18 4136 #define DMA_TCD1_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,1)
mbed_official 146:f64d43ff0c18 4137 #define DMA_TCD1_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,1)
mbed_official 146:f64d43ff0c18 4138 #define DMA_TCD1_DLASTSGA DMA_DLAST_SGA_REG(DMA0,1)
mbed_official 146:f64d43ff0c18 4139 #define DMA_TCD1_CSR DMA_CSR_REG(DMA0,1)
mbed_official 146:f64d43ff0c18 4140 #define DMA_TCD1_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,1)
mbed_official 146:f64d43ff0c18 4141 #define DMA_TCD1_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,1)
mbed_official 146:f64d43ff0c18 4142 #define DMA_TCD2_SADDR DMA_SADDR_REG(DMA0,2)
mbed_official 146:f64d43ff0c18 4143 #define DMA_TCD2_SOFF DMA_SOFF_REG(DMA0,2)
mbed_official 146:f64d43ff0c18 4144 #define DMA_TCD2_ATTR DMA_ATTR_REG(DMA0,2)
mbed_official 146:f64d43ff0c18 4145 #define DMA_TCD2_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,2)
mbed_official 146:f64d43ff0c18 4146 #define DMA_TCD2_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,2)
mbed_official 146:f64d43ff0c18 4147 #define DMA_TCD2_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,2)
mbed_official 146:f64d43ff0c18 4148 #define DMA_TCD2_SLAST DMA_SLAST_REG(DMA0,2)
mbed_official 146:f64d43ff0c18 4149 #define DMA_TCD2_DADDR DMA_DADDR_REG(DMA0,2)
mbed_official 146:f64d43ff0c18 4150 #define DMA_TCD2_DOFF DMA_DOFF_REG(DMA0,2)
mbed_official 146:f64d43ff0c18 4151 #define DMA_TCD2_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,2)
mbed_official 146:f64d43ff0c18 4152 #define DMA_TCD2_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,2)
mbed_official 146:f64d43ff0c18 4153 #define DMA_TCD2_DLASTSGA DMA_DLAST_SGA_REG(DMA0,2)
mbed_official 146:f64d43ff0c18 4154 #define DMA_TCD2_CSR DMA_CSR_REG(DMA0,2)
mbed_official 146:f64d43ff0c18 4155 #define DMA_TCD2_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,2)
mbed_official 146:f64d43ff0c18 4156 #define DMA_TCD2_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,2)
mbed_official 146:f64d43ff0c18 4157 #define DMA_TCD3_SADDR DMA_SADDR_REG(DMA0,3)
mbed_official 146:f64d43ff0c18 4158 #define DMA_TCD3_SOFF DMA_SOFF_REG(DMA0,3)
mbed_official 146:f64d43ff0c18 4159 #define DMA_TCD3_ATTR DMA_ATTR_REG(DMA0,3)
mbed_official 146:f64d43ff0c18 4160 #define DMA_TCD3_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,3)
mbed_official 146:f64d43ff0c18 4161 #define DMA_TCD3_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,3)
mbed_official 146:f64d43ff0c18 4162 #define DMA_TCD3_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,3)
mbed_official 146:f64d43ff0c18 4163 #define DMA_TCD3_SLAST DMA_SLAST_REG(DMA0,3)
mbed_official 146:f64d43ff0c18 4164 #define DMA_TCD3_DADDR DMA_DADDR_REG(DMA0,3)
mbed_official 146:f64d43ff0c18 4165 #define DMA_TCD3_DOFF DMA_DOFF_REG(DMA0,3)
mbed_official 146:f64d43ff0c18 4166 #define DMA_TCD3_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,3)
mbed_official 146:f64d43ff0c18 4167 #define DMA_TCD3_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,3)
mbed_official 146:f64d43ff0c18 4168 #define DMA_TCD3_DLASTSGA DMA_DLAST_SGA_REG(DMA0,3)
mbed_official 146:f64d43ff0c18 4169 #define DMA_TCD3_CSR DMA_CSR_REG(DMA0,3)
mbed_official 146:f64d43ff0c18 4170 #define DMA_TCD3_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,3)
mbed_official 146:f64d43ff0c18 4171 #define DMA_TCD3_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,3)
mbed_official 146:f64d43ff0c18 4172 #define DMA_TCD4_SADDR DMA_SADDR_REG(DMA0,4)
mbed_official 146:f64d43ff0c18 4173 #define DMA_TCD4_SOFF DMA_SOFF_REG(DMA0,4)
mbed_official 146:f64d43ff0c18 4174 #define DMA_TCD4_ATTR DMA_ATTR_REG(DMA0,4)
mbed_official 146:f64d43ff0c18 4175 #define DMA_TCD4_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,4)
mbed_official 146:f64d43ff0c18 4176 #define DMA_TCD4_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,4)
mbed_official 146:f64d43ff0c18 4177 #define DMA_TCD4_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,4)
mbed_official 146:f64d43ff0c18 4178 #define DMA_TCD4_SLAST DMA_SLAST_REG(DMA0,4)
mbed_official 146:f64d43ff0c18 4179 #define DMA_TCD4_DADDR DMA_DADDR_REG(DMA0,4)
mbed_official 146:f64d43ff0c18 4180 #define DMA_TCD4_DOFF DMA_DOFF_REG(DMA0,4)
mbed_official 146:f64d43ff0c18 4181 #define DMA_TCD4_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,4)
mbed_official 146:f64d43ff0c18 4182 #define DMA_TCD4_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,4)
mbed_official 146:f64d43ff0c18 4183 #define DMA_TCD4_DLASTSGA DMA_DLAST_SGA_REG(DMA0,4)
mbed_official 146:f64d43ff0c18 4184 #define DMA_TCD4_CSR DMA_CSR_REG(DMA0,4)
mbed_official 146:f64d43ff0c18 4185 #define DMA_TCD4_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,4)
mbed_official 146:f64d43ff0c18 4186 #define DMA_TCD4_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,4)
mbed_official 146:f64d43ff0c18 4187 #define DMA_TCD5_SADDR DMA_SADDR_REG(DMA0,5)
mbed_official 146:f64d43ff0c18 4188 #define DMA_TCD5_SOFF DMA_SOFF_REG(DMA0,5)
mbed_official 146:f64d43ff0c18 4189 #define DMA_TCD5_ATTR DMA_ATTR_REG(DMA0,5)
mbed_official 146:f64d43ff0c18 4190 #define DMA_TCD5_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,5)
mbed_official 146:f64d43ff0c18 4191 #define DMA_TCD5_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,5)
mbed_official 146:f64d43ff0c18 4192 #define DMA_TCD5_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,5)
mbed_official 146:f64d43ff0c18 4193 #define DMA_TCD5_SLAST DMA_SLAST_REG(DMA0,5)
mbed_official 146:f64d43ff0c18 4194 #define DMA_TCD5_DADDR DMA_DADDR_REG(DMA0,5)
mbed_official 146:f64d43ff0c18 4195 #define DMA_TCD5_DOFF DMA_DOFF_REG(DMA0,5)
mbed_official 146:f64d43ff0c18 4196 #define DMA_TCD5_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,5)
mbed_official 146:f64d43ff0c18 4197 #define DMA_TCD5_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,5)
mbed_official 146:f64d43ff0c18 4198 #define DMA_TCD5_DLASTSGA DMA_DLAST_SGA_REG(DMA0,5)
mbed_official 146:f64d43ff0c18 4199 #define DMA_TCD5_CSR DMA_CSR_REG(DMA0,5)
mbed_official 146:f64d43ff0c18 4200 #define DMA_TCD5_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,5)
mbed_official 146:f64d43ff0c18 4201 #define DMA_TCD5_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,5)
mbed_official 146:f64d43ff0c18 4202 #define DMA_TCD6_SADDR DMA_SADDR_REG(DMA0,6)
mbed_official 146:f64d43ff0c18 4203 #define DMA_TCD6_SOFF DMA_SOFF_REG(DMA0,6)
mbed_official 146:f64d43ff0c18 4204 #define DMA_TCD6_ATTR DMA_ATTR_REG(DMA0,6)
mbed_official 146:f64d43ff0c18 4205 #define DMA_TCD6_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,6)
mbed_official 146:f64d43ff0c18 4206 #define DMA_TCD6_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,6)
mbed_official 146:f64d43ff0c18 4207 #define DMA_TCD6_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,6)
mbed_official 146:f64d43ff0c18 4208 #define DMA_TCD6_SLAST DMA_SLAST_REG(DMA0,6)
mbed_official 146:f64d43ff0c18 4209 #define DMA_TCD6_DADDR DMA_DADDR_REG(DMA0,6)
mbed_official 146:f64d43ff0c18 4210 #define DMA_TCD6_DOFF DMA_DOFF_REG(DMA0,6)
mbed_official 146:f64d43ff0c18 4211 #define DMA_TCD6_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,6)
mbed_official 146:f64d43ff0c18 4212 #define DMA_TCD6_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,6)
mbed_official 146:f64d43ff0c18 4213 #define DMA_TCD6_DLASTSGA DMA_DLAST_SGA_REG(DMA0,6)
mbed_official 146:f64d43ff0c18 4214 #define DMA_TCD6_CSR DMA_CSR_REG(DMA0,6)
mbed_official 146:f64d43ff0c18 4215 #define DMA_TCD6_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,6)
mbed_official 146:f64d43ff0c18 4216 #define DMA_TCD6_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,6)
mbed_official 146:f64d43ff0c18 4217 #define DMA_TCD7_SADDR DMA_SADDR_REG(DMA0,7)
mbed_official 146:f64d43ff0c18 4218 #define DMA_TCD7_SOFF DMA_SOFF_REG(DMA0,7)
mbed_official 146:f64d43ff0c18 4219 #define DMA_TCD7_ATTR DMA_ATTR_REG(DMA0,7)
mbed_official 146:f64d43ff0c18 4220 #define DMA_TCD7_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,7)
mbed_official 146:f64d43ff0c18 4221 #define DMA_TCD7_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,7)
mbed_official 146:f64d43ff0c18 4222 #define DMA_TCD7_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,7)
mbed_official 146:f64d43ff0c18 4223 #define DMA_TCD7_SLAST DMA_SLAST_REG(DMA0,7)
mbed_official 146:f64d43ff0c18 4224 #define DMA_TCD7_DADDR DMA_DADDR_REG(DMA0,7)
mbed_official 146:f64d43ff0c18 4225 #define DMA_TCD7_DOFF DMA_DOFF_REG(DMA0,7)
mbed_official 146:f64d43ff0c18 4226 #define DMA_TCD7_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,7)
mbed_official 146:f64d43ff0c18 4227 #define DMA_TCD7_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,7)
mbed_official 146:f64d43ff0c18 4228 #define DMA_TCD7_DLASTSGA DMA_DLAST_SGA_REG(DMA0,7)
mbed_official 146:f64d43ff0c18 4229 #define DMA_TCD7_CSR DMA_CSR_REG(DMA0,7)
mbed_official 146:f64d43ff0c18 4230 #define DMA_TCD7_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,7)
mbed_official 146:f64d43ff0c18 4231 #define DMA_TCD7_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,7)
mbed_official 146:f64d43ff0c18 4232 #define DMA_TCD8_SADDR DMA_SADDR_REG(DMA0,8)
mbed_official 146:f64d43ff0c18 4233 #define DMA_TCD8_SOFF DMA_SOFF_REG(DMA0,8)
mbed_official 146:f64d43ff0c18 4234 #define DMA_TCD8_ATTR DMA_ATTR_REG(DMA0,8)
mbed_official 146:f64d43ff0c18 4235 #define DMA_TCD8_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,8)
mbed_official 146:f64d43ff0c18 4236 #define DMA_TCD8_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,8)
mbed_official 146:f64d43ff0c18 4237 #define DMA_TCD8_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,8)
mbed_official 146:f64d43ff0c18 4238 #define DMA_TCD8_SLAST DMA_SLAST_REG(DMA0,8)
mbed_official 146:f64d43ff0c18 4239 #define DMA_TCD8_DADDR DMA_DADDR_REG(DMA0,8)
mbed_official 146:f64d43ff0c18 4240 #define DMA_TCD8_DOFF DMA_DOFF_REG(DMA0,8)
mbed_official 146:f64d43ff0c18 4241 #define DMA_TCD8_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,8)
mbed_official 146:f64d43ff0c18 4242 #define DMA_TCD8_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,8)
mbed_official 146:f64d43ff0c18 4243 #define DMA_TCD8_DLASTSGA DMA_DLAST_SGA_REG(DMA0,8)
mbed_official 146:f64d43ff0c18 4244 #define DMA_TCD8_CSR DMA_CSR_REG(DMA0,8)
mbed_official 146:f64d43ff0c18 4245 #define DMA_TCD8_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,8)
mbed_official 146:f64d43ff0c18 4246 #define DMA_TCD8_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,8)
mbed_official 146:f64d43ff0c18 4247 #define DMA_TCD9_SADDR DMA_SADDR_REG(DMA0,9)
mbed_official 146:f64d43ff0c18 4248 #define DMA_TCD9_SOFF DMA_SOFF_REG(DMA0,9)
mbed_official 146:f64d43ff0c18 4249 #define DMA_TCD9_ATTR DMA_ATTR_REG(DMA0,9)
mbed_official 146:f64d43ff0c18 4250 #define DMA_TCD9_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,9)
mbed_official 146:f64d43ff0c18 4251 #define DMA_TCD9_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,9)
mbed_official 146:f64d43ff0c18 4252 #define DMA_TCD9_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,9)
mbed_official 146:f64d43ff0c18 4253 #define DMA_TCD9_SLAST DMA_SLAST_REG(DMA0,9)
mbed_official 146:f64d43ff0c18 4254 #define DMA_TCD9_DADDR DMA_DADDR_REG(DMA0,9)
mbed_official 146:f64d43ff0c18 4255 #define DMA_TCD9_DOFF DMA_DOFF_REG(DMA0,9)
mbed_official 146:f64d43ff0c18 4256 #define DMA_TCD9_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,9)
mbed_official 146:f64d43ff0c18 4257 #define DMA_TCD9_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,9)
mbed_official 146:f64d43ff0c18 4258 #define DMA_TCD9_DLASTSGA DMA_DLAST_SGA_REG(DMA0,9)
mbed_official 146:f64d43ff0c18 4259 #define DMA_TCD9_CSR DMA_CSR_REG(DMA0,9)
mbed_official 146:f64d43ff0c18 4260 #define DMA_TCD9_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,9)
mbed_official 146:f64d43ff0c18 4261 #define DMA_TCD9_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,9)
mbed_official 146:f64d43ff0c18 4262 #define DMA_TCD10_SADDR DMA_SADDR_REG(DMA0,10)
mbed_official 146:f64d43ff0c18 4263 #define DMA_TCD10_SOFF DMA_SOFF_REG(DMA0,10)
mbed_official 146:f64d43ff0c18 4264 #define DMA_TCD10_ATTR DMA_ATTR_REG(DMA0,10)
mbed_official 146:f64d43ff0c18 4265 #define DMA_TCD10_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,10)
mbed_official 146:f64d43ff0c18 4266 #define DMA_TCD10_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,10)
mbed_official 146:f64d43ff0c18 4267 #define DMA_TCD10_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,10)
mbed_official 146:f64d43ff0c18 4268 #define DMA_TCD10_SLAST DMA_SLAST_REG(DMA0,10)
mbed_official 146:f64d43ff0c18 4269 #define DMA_TCD10_DADDR DMA_DADDR_REG(DMA0,10)
mbed_official 146:f64d43ff0c18 4270 #define DMA_TCD10_DOFF DMA_DOFF_REG(DMA0,10)
mbed_official 146:f64d43ff0c18 4271 #define DMA_TCD10_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,10)
mbed_official 146:f64d43ff0c18 4272 #define DMA_TCD10_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,10)
mbed_official 146:f64d43ff0c18 4273 #define DMA_TCD10_DLASTSGA DMA_DLAST_SGA_REG(DMA0,10)
mbed_official 146:f64d43ff0c18 4274 #define DMA_TCD10_CSR DMA_CSR_REG(DMA0,10)
mbed_official 146:f64d43ff0c18 4275 #define DMA_TCD10_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,10)
mbed_official 146:f64d43ff0c18 4276 #define DMA_TCD10_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,10)
mbed_official 146:f64d43ff0c18 4277 #define DMA_TCD11_SADDR DMA_SADDR_REG(DMA0,11)
mbed_official 146:f64d43ff0c18 4278 #define DMA_TCD11_SOFF DMA_SOFF_REG(DMA0,11)
mbed_official 146:f64d43ff0c18 4279 #define DMA_TCD11_ATTR DMA_ATTR_REG(DMA0,11)
mbed_official 146:f64d43ff0c18 4280 #define DMA_TCD11_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,11)
mbed_official 146:f64d43ff0c18 4281 #define DMA_TCD11_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,11)
mbed_official 146:f64d43ff0c18 4282 #define DMA_TCD11_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,11)
mbed_official 146:f64d43ff0c18 4283 #define DMA_TCD11_SLAST DMA_SLAST_REG(DMA0,11)
mbed_official 146:f64d43ff0c18 4284 #define DMA_TCD11_DADDR DMA_DADDR_REG(DMA0,11)
mbed_official 146:f64d43ff0c18 4285 #define DMA_TCD11_DOFF DMA_DOFF_REG(DMA0,11)
mbed_official 146:f64d43ff0c18 4286 #define DMA_TCD11_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,11)
mbed_official 146:f64d43ff0c18 4287 #define DMA_TCD11_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,11)
mbed_official 146:f64d43ff0c18 4288 #define DMA_TCD11_DLASTSGA DMA_DLAST_SGA_REG(DMA0,11)
mbed_official 146:f64d43ff0c18 4289 #define DMA_TCD11_CSR DMA_CSR_REG(DMA0,11)
mbed_official 146:f64d43ff0c18 4290 #define DMA_TCD11_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,11)
mbed_official 146:f64d43ff0c18 4291 #define DMA_TCD11_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,11)
mbed_official 146:f64d43ff0c18 4292 #define DMA_TCD12_SADDR DMA_SADDR_REG(DMA0,12)
mbed_official 146:f64d43ff0c18 4293 #define DMA_TCD12_SOFF DMA_SOFF_REG(DMA0,12)
mbed_official 146:f64d43ff0c18 4294 #define DMA_TCD12_ATTR DMA_ATTR_REG(DMA0,12)
mbed_official 146:f64d43ff0c18 4295 #define DMA_TCD12_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,12)
mbed_official 146:f64d43ff0c18 4296 #define DMA_TCD12_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,12)
mbed_official 146:f64d43ff0c18 4297 #define DMA_TCD12_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,12)
mbed_official 146:f64d43ff0c18 4298 #define DMA_TCD12_SLAST DMA_SLAST_REG(DMA0,12)
mbed_official 146:f64d43ff0c18 4299 #define DMA_TCD12_DADDR DMA_DADDR_REG(DMA0,12)
mbed_official 146:f64d43ff0c18 4300 #define DMA_TCD12_DOFF DMA_DOFF_REG(DMA0,12)
mbed_official 146:f64d43ff0c18 4301 #define DMA_TCD12_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,12)
mbed_official 146:f64d43ff0c18 4302 #define DMA_TCD12_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,12)
mbed_official 146:f64d43ff0c18 4303 #define DMA_TCD12_DLASTSGA DMA_DLAST_SGA_REG(DMA0,12)
mbed_official 146:f64d43ff0c18 4304 #define DMA_TCD12_CSR DMA_CSR_REG(DMA0,12)
mbed_official 146:f64d43ff0c18 4305 #define DMA_TCD12_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,12)
mbed_official 146:f64d43ff0c18 4306 #define DMA_TCD12_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,12)
mbed_official 146:f64d43ff0c18 4307 #define DMA_TCD13_SADDR DMA_SADDR_REG(DMA0,13)
mbed_official 146:f64d43ff0c18 4308 #define DMA_TCD13_SOFF DMA_SOFF_REG(DMA0,13)
mbed_official 146:f64d43ff0c18 4309 #define DMA_TCD13_ATTR DMA_ATTR_REG(DMA0,13)
mbed_official 146:f64d43ff0c18 4310 #define DMA_TCD13_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,13)
mbed_official 146:f64d43ff0c18 4311 #define DMA_TCD13_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,13)
mbed_official 146:f64d43ff0c18 4312 #define DMA_TCD13_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,13)
mbed_official 146:f64d43ff0c18 4313 #define DMA_TCD13_SLAST DMA_SLAST_REG(DMA0,13)
mbed_official 146:f64d43ff0c18 4314 #define DMA_TCD13_DADDR DMA_DADDR_REG(DMA0,13)
mbed_official 146:f64d43ff0c18 4315 #define DMA_TCD13_DOFF DMA_DOFF_REG(DMA0,13)
mbed_official 146:f64d43ff0c18 4316 #define DMA_TCD13_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,13)
mbed_official 146:f64d43ff0c18 4317 #define DMA_TCD13_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,13)
mbed_official 146:f64d43ff0c18 4318 #define DMA_TCD13_DLASTSGA DMA_DLAST_SGA_REG(DMA0,13)
mbed_official 146:f64d43ff0c18 4319 #define DMA_TCD13_CSR DMA_CSR_REG(DMA0,13)
mbed_official 146:f64d43ff0c18 4320 #define DMA_TCD13_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,13)
mbed_official 146:f64d43ff0c18 4321 #define DMA_TCD13_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,13)
mbed_official 146:f64d43ff0c18 4322 #define DMA_TCD14_SADDR DMA_SADDR_REG(DMA0,14)
mbed_official 146:f64d43ff0c18 4323 #define DMA_TCD14_SOFF DMA_SOFF_REG(DMA0,14)
mbed_official 146:f64d43ff0c18 4324 #define DMA_TCD14_ATTR DMA_ATTR_REG(DMA0,14)
mbed_official 146:f64d43ff0c18 4325 #define DMA_TCD14_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,14)
mbed_official 146:f64d43ff0c18 4326 #define DMA_TCD14_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,14)
mbed_official 146:f64d43ff0c18 4327 #define DMA_TCD14_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,14)
mbed_official 146:f64d43ff0c18 4328 #define DMA_TCD14_SLAST DMA_SLAST_REG(DMA0,14)
mbed_official 146:f64d43ff0c18 4329 #define DMA_TCD14_DADDR DMA_DADDR_REG(DMA0,14)
mbed_official 146:f64d43ff0c18 4330 #define DMA_TCD14_DOFF DMA_DOFF_REG(DMA0,14)
mbed_official 146:f64d43ff0c18 4331 #define DMA_TCD14_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,14)
mbed_official 146:f64d43ff0c18 4332 #define DMA_TCD14_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,14)
mbed_official 146:f64d43ff0c18 4333 #define DMA_TCD14_DLASTSGA DMA_DLAST_SGA_REG(DMA0,14)
mbed_official 146:f64d43ff0c18 4334 #define DMA_TCD14_CSR DMA_CSR_REG(DMA0,14)
mbed_official 146:f64d43ff0c18 4335 #define DMA_TCD14_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,14)
mbed_official 146:f64d43ff0c18 4336 #define DMA_TCD14_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,14)
mbed_official 146:f64d43ff0c18 4337 #define DMA_TCD15_SADDR DMA_SADDR_REG(DMA0,15)
mbed_official 146:f64d43ff0c18 4338 #define DMA_TCD15_SOFF DMA_SOFF_REG(DMA0,15)
mbed_official 146:f64d43ff0c18 4339 #define DMA_TCD15_ATTR DMA_ATTR_REG(DMA0,15)
mbed_official 146:f64d43ff0c18 4340 #define DMA_TCD15_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,15)
mbed_official 146:f64d43ff0c18 4341 #define DMA_TCD15_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,15)
mbed_official 146:f64d43ff0c18 4342 #define DMA_TCD15_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,15)
mbed_official 146:f64d43ff0c18 4343 #define DMA_TCD15_SLAST DMA_SLAST_REG(DMA0,15)
mbed_official 146:f64d43ff0c18 4344 #define DMA_TCD15_DADDR DMA_DADDR_REG(DMA0,15)
mbed_official 146:f64d43ff0c18 4345 #define DMA_TCD15_DOFF DMA_DOFF_REG(DMA0,15)
mbed_official 146:f64d43ff0c18 4346 #define DMA_TCD15_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,15)
mbed_official 146:f64d43ff0c18 4347 #define DMA_TCD15_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,15)
mbed_official 146:f64d43ff0c18 4348 #define DMA_TCD15_DLASTSGA DMA_DLAST_SGA_REG(DMA0,15)
mbed_official 146:f64d43ff0c18 4349 #define DMA_TCD15_CSR DMA_CSR_REG(DMA0,15)
mbed_official 146:f64d43ff0c18 4350 #define DMA_TCD15_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,15)
mbed_official 146:f64d43ff0c18 4351 #define DMA_TCD15_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,15)
mbed_official 146:f64d43ff0c18 4352
mbed_official 146:f64d43ff0c18 4353 /* DMA - Register array accessors */
mbed_official 146:f64d43ff0c18 4354 #define DMA_SADDR(index) DMA_SADDR_REG(DMA0,index)
mbed_official 146:f64d43ff0c18 4355 #define DMA_SOFF(index) DMA_SOFF_REG(DMA0,index)
mbed_official 146:f64d43ff0c18 4356 #define DMA_ATTR(index) DMA_ATTR_REG(DMA0,index)
mbed_official 146:f64d43ff0c18 4357 #define DMA_NBYTES_MLNO(index) DMA_NBYTES_MLNO_REG(DMA0,index)
mbed_official 146:f64d43ff0c18 4358 #define DMA_NBYTES_MLOFFNO(index) DMA_NBYTES_MLOFFNO_REG(DMA0,index)
mbed_official 146:f64d43ff0c18 4359 #define DMA_NBYTES_MLOFFYES(index) DMA_NBYTES_MLOFFYES_REG(DMA0,index)
mbed_official 146:f64d43ff0c18 4360 #define DMA_SLAST(index) DMA_SLAST_REG(DMA0,index)
mbed_official 146:f64d43ff0c18 4361 #define DMA_DADDR(index) DMA_DADDR_REG(DMA0,index)
mbed_official 146:f64d43ff0c18 4362 #define DMA_DOFF(index) DMA_DOFF_REG(DMA0,index)
mbed_official 146:f64d43ff0c18 4363 #define DMA_CITER_ELINKNO(index) DMA_CITER_ELINKNO_REG(DMA0,index)
mbed_official 146:f64d43ff0c18 4364 #define DMA_CITER_ELINKYES(index) DMA_CITER_ELINKYES_REG(DMA0,index)
mbed_official 146:f64d43ff0c18 4365 #define DMA_DLAST_SGA(index) DMA_DLAST_SGA_REG(DMA0,index)
mbed_official 146:f64d43ff0c18 4366 #define DMA_CSR(index) DMA_CSR_REG(DMA0,index)
mbed_official 146:f64d43ff0c18 4367 #define DMA_BITER_ELINKNO(index) DMA_BITER_ELINKNO_REG(DMA0,index)
mbed_official 146:f64d43ff0c18 4368 #define DMA_BITER_ELINKYES(index) DMA_BITER_ELINKYES_REG(DMA0,index)
mbed_official 146:f64d43ff0c18 4369
mbed_official 146:f64d43ff0c18 4370 /*!
mbed_official 146:f64d43ff0c18 4371 * @}
mbed_official 146:f64d43ff0c18 4372 */ /* end of group DMA_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 4373
mbed_official 146:f64d43ff0c18 4374
mbed_official 146:f64d43ff0c18 4375 /*!
mbed_official 146:f64d43ff0c18 4376 * @}
mbed_official 146:f64d43ff0c18 4377 */ /* end of group DMA_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 4378
mbed_official 146:f64d43ff0c18 4379
mbed_official 146:f64d43ff0c18 4380 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4381 -- DMAMUX Peripheral Access Layer
mbed_official 146:f64d43ff0c18 4382 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 4383
mbed_official 146:f64d43ff0c18 4384 /*!
mbed_official 146:f64d43ff0c18 4385 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
mbed_official 146:f64d43ff0c18 4386 * @{
mbed_official 146:f64d43ff0c18 4387 */
mbed_official 146:f64d43ff0c18 4388
mbed_official 146:f64d43ff0c18 4389 /** DMAMUX - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 4390 typedef struct {
mbed_official 146:f64d43ff0c18 4391 __IO uint8_t CHCFG[16]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
mbed_official 146:f64d43ff0c18 4392 } DMAMUX_Type, *DMAMUX_MemMapPtr;
mbed_official 146:f64d43ff0c18 4393
mbed_official 146:f64d43ff0c18 4394 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4395 -- DMAMUX - Register accessor macros
mbed_official 146:f64d43ff0c18 4396 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 4397
mbed_official 146:f64d43ff0c18 4398 /*!
mbed_official 146:f64d43ff0c18 4399 * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
mbed_official 146:f64d43ff0c18 4400 * @{
mbed_official 146:f64d43ff0c18 4401 */
mbed_official 146:f64d43ff0c18 4402
mbed_official 146:f64d43ff0c18 4403
mbed_official 146:f64d43ff0c18 4404 /* DMAMUX - Register accessors */
mbed_official 146:f64d43ff0c18 4405 #define DMAMUX_CHCFG_REG(base,index) ((base)->CHCFG[index])
mbed_official 146:f64d43ff0c18 4406
mbed_official 146:f64d43ff0c18 4407 /*!
mbed_official 146:f64d43ff0c18 4408 * @}
mbed_official 146:f64d43ff0c18 4409 */ /* end of group DMAMUX_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 4410
mbed_official 146:f64d43ff0c18 4411
mbed_official 146:f64d43ff0c18 4412 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4413 -- DMAMUX Register Masks
mbed_official 146:f64d43ff0c18 4414 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 4415
mbed_official 146:f64d43ff0c18 4416 /*!
mbed_official 146:f64d43ff0c18 4417 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
mbed_official 146:f64d43ff0c18 4418 * @{
mbed_official 146:f64d43ff0c18 4419 */
mbed_official 146:f64d43ff0c18 4420
mbed_official 146:f64d43ff0c18 4421 /* CHCFG Bit Fields */
mbed_official 146:f64d43ff0c18 4422 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
mbed_official 146:f64d43ff0c18 4423 #define DMAMUX_CHCFG_SOURCE_SHIFT 0
mbed_official 146:f64d43ff0c18 4424 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
mbed_official 146:f64d43ff0c18 4425 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
mbed_official 146:f64d43ff0c18 4426 #define DMAMUX_CHCFG_TRIG_SHIFT 6
mbed_official 146:f64d43ff0c18 4427 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
mbed_official 146:f64d43ff0c18 4428 #define DMAMUX_CHCFG_ENBL_SHIFT 7
mbed_official 146:f64d43ff0c18 4429
mbed_official 146:f64d43ff0c18 4430 /*!
mbed_official 146:f64d43ff0c18 4431 * @}
mbed_official 146:f64d43ff0c18 4432 */ /* end of group DMAMUX_Register_Masks */
mbed_official 146:f64d43ff0c18 4433
mbed_official 146:f64d43ff0c18 4434
mbed_official 146:f64d43ff0c18 4435 /* DMAMUX - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 4436 /** Peripheral DMAMUX base address */
mbed_official 146:f64d43ff0c18 4437 #define DMAMUX_BASE (0x40021000u)
mbed_official 146:f64d43ff0c18 4438 /** Peripheral DMAMUX base pointer */
mbed_official 146:f64d43ff0c18 4439 #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
mbed_official 146:f64d43ff0c18 4440 #define DMAMUX_BASE_PTR (DMAMUX)
mbed_official 146:f64d43ff0c18 4441 /** Array initializer of DMAMUX peripheral base pointers */
mbed_official 146:f64d43ff0c18 4442 #define DMAMUX_BASES { DMAMUX }
mbed_official 146:f64d43ff0c18 4443
mbed_official 146:f64d43ff0c18 4444 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4445 -- DMAMUX - Register accessor macros
mbed_official 146:f64d43ff0c18 4446 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 4447
mbed_official 146:f64d43ff0c18 4448 /*!
mbed_official 146:f64d43ff0c18 4449 * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
mbed_official 146:f64d43ff0c18 4450 * @{
mbed_official 146:f64d43ff0c18 4451 */
mbed_official 146:f64d43ff0c18 4452
mbed_official 146:f64d43ff0c18 4453
mbed_official 146:f64d43ff0c18 4454 /* DMAMUX - Register instance definitions */
mbed_official 146:f64d43ff0c18 4455 /* DMAMUX */
mbed_official 146:f64d43ff0c18 4456 #define DMAMUX_CHCFG0 DMAMUX_CHCFG_REG(DMAMUX,0)
mbed_official 146:f64d43ff0c18 4457 #define DMAMUX_CHCFG1 DMAMUX_CHCFG_REG(DMAMUX,1)
mbed_official 146:f64d43ff0c18 4458 #define DMAMUX_CHCFG2 DMAMUX_CHCFG_REG(DMAMUX,2)
mbed_official 146:f64d43ff0c18 4459 #define DMAMUX_CHCFG3 DMAMUX_CHCFG_REG(DMAMUX,3)
mbed_official 146:f64d43ff0c18 4460 #define DMAMUX_CHCFG4 DMAMUX_CHCFG_REG(DMAMUX,4)
mbed_official 146:f64d43ff0c18 4461 #define DMAMUX_CHCFG5 DMAMUX_CHCFG_REG(DMAMUX,5)
mbed_official 146:f64d43ff0c18 4462 #define DMAMUX_CHCFG6 DMAMUX_CHCFG_REG(DMAMUX,6)
mbed_official 146:f64d43ff0c18 4463 #define DMAMUX_CHCFG7 DMAMUX_CHCFG_REG(DMAMUX,7)
mbed_official 146:f64d43ff0c18 4464 #define DMAMUX_CHCFG8 DMAMUX_CHCFG_REG(DMAMUX,8)
mbed_official 146:f64d43ff0c18 4465 #define DMAMUX_CHCFG9 DMAMUX_CHCFG_REG(DMAMUX,9)
mbed_official 146:f64d43ff0c18 4466 #define DMAMUX_CHCFG10 DMAMUX_CHCFG_REG(DMAMUX,10)
mbed_official 146:f64d43ff0c18 4467 #define DMAMUX_CHCFG11 DMAMUX_CHCFG_REG(DMAMUX,11)
mbed_official 146:f64d43ff0c18 4468 #define DMAMUX_CHCFG12 DMAMUX_CHCFG_REG(DMAMUX,12)
mbed_official 146:f64d43ff0c18 4469 #define DMAMUX_CHCFG13 DMAMUX_CHCFG_REG(DMAMUX,13)
mbed_official 146:f64d43ff0c18 4470 #define DMAMUX_CHCFG14 DMAMUX_CHCFG_REG(DMAMUX,14)
mbed_official 146:f64d43ff0c18 4471 #define DMAMUX_CHCFG15 DMAMUX_CHCFG_REG(DMAMUX,15)
mbed_official 146:f64d43ff0c18 4472
mbed_official 146:f64d43ff0c18 4473 /* DMAMUX - Register array accessors */
mbed_official 146:f64d43ff0c18 4474 #define DMAMUX_CHCFG(index) DMAMUX_CHCFG_REG(DMAMUX,index)
mbed_official 146:f64d43ff0c18 4475
mbed_official 146:f64d43ff0c18 4476 /*!
mbed_official 146:f64d43ff0c18 4477 * @}
mbed_official 146:f64d43ff0c18 4478 */ /* end of group DMAMUX_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 4479
mbed_official 146:f64d43ff0c18 4480
mbed_official 146:f64d43ff0c18 4481 /*!
mbed_official 146:f64d43ff0c18 4482 * @}
mbed_official 146:f64d43ff0c18 4483 */ /* end of group DMAMUX_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 4484
mbed_official 146:f64d43ff0c18 4485
mbed_official 146:f64d43ff0c18 4486 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4487 -- ENET Peripheral Access Layer
mbed_official 146:f64d43ff0c18 4488 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 4489
mbed_official 146:f64d43ff0c18 4490 /*!
mbed_official 146:f64d43ff0c18 4491 * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
mbed_official 146:f64d43ff0c18 4492 * @{
mbed_official 146:f64d43ff0c18 4493 */
mbed_official 146:f64d43ff0c18 4494
mbed_official 146:f64d43ff0c18 4495 /** ENET - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 4496 typedef struct {
mbed_official 146:f64d43ff0c18 4497 uint8_t RESERVED_0[4];
mbed_official 146:f64d43ff0c18 4498 __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */
mbed_official 146:f64d43ff0c18 4499 __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */
mbed_official 146:f64d43ff0c18 4500 uint8_t RESERVED_1[4];
mbed_official 146:f64d43ff0c18 4501 __IO uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */
mbed_official 146:f64d43ff0c18 4502 __IO uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */
mbed_official 146:f64d43ff0c18 4503 uint8_t RESERVED_2[12];
mbed_official 146:f64d43ff0c18 4504 __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */
mbed_official 146:f64d43ff0c18 4505 uint8_t RESERVED_3[24];
mbed_official 146:f64d43ff0c18 4506 __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */
mbed_official 146:f64d43ff0c18 4507 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */
mbed_official 146:f64d43ff0c18 4508 uint8_t RESERVED_4[28];
mbed_official 146:f64d43ff0c18 4509 __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */
mbed_official 146:f64d43ff0c18 4510 uint8_t RESERVED_5[28];
mbed_official 146:f64d43ff0c18 4511 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */
mbed_official 146:f64d43ff0c18 4512 uint8_t RESERVED_6[60];
mbed_official 146:f64d43ff0c18 4513 __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */
mbed_official 146:f64d43ff0c18 4514 uint8_t RESERVED_7[28];
mbed_official 146:f64d43ff0c18 4515 __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */
mbed_official 146:f64d43ff0c18 4516 __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */
mbed_official 146:f64d43ff0c18 4517 __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */
mbed_official 146:f64d43ff0c18 4518 uint8_t RESERVED_8[40];
mbed_official 146:f64d43ff0c18 4519 __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */
mbed_official 146:f64d43ff0c18 4520 __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */
mbed_official 146:f64d43ff0c18 4521 __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */
mbed_official 146:f64d43ff0c18 4522 __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */
mbed_official 146:f64d43ff0c18 4523 uint8_t RESERVED_9[28];
mbed_official 146:f64d43ff0c18 4524 __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */
mbed_official 146:f64d43ff0c18 4525 uint8_t RESERVED_10[56];
mbed_official 146:f64d43ff0c18 4526 __IO uint32_t RDSR; /**< Receive Descriptor Ring Start Register, offset: 0x180 */
mbed_official 146:f64d43ff0c18 4527 __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */
mbed_official 146:f64d43ff0c18 4528 __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */
mbed_official 146:f64d43ff0c18 4529 uint8_t RESERVED_11[4];
mbed_official 146:f64d43ff0c18 4530 __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */
mbed_official 146:f64d43ff0c18 4531 __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
mbed_official 146:f64d43ff0c18 4532 __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
mbed_official 146:f64d43ff0c18 4533 __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
mbed_official 146:f64d43ff0c18 4534 __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
mbed_official 146:f64d43ff0c18 4535 __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
mbed_official 146:f64d43ff0c18 4536 __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
mbed_official 146:f64d43ff0c18 4537 __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */
mbed_official 146:f64d43ff0c18 4538 __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */
mbed_official 146:f64d43ff0c18 4539 uint8_t RESERVED_12[12];
mbed_official 146:f64d43ff0c18 4540 __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
mbed_official 146:f64d43ff0c18 4541 __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
mbed_official 146:f64d43ff0c18 4542 uint8_t RESERVED_13[60];
mbed_official 146:f64d43ff0c18 4543 __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */
mbed_official 146:f64d43ff0c18 4544 __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
mbed_official 146:f64d43ff0c18 4545 __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
mbed_official 146:f64d43ff0c18 4546 __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
mbed_official 146:f64d43ff0c18 4547 __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
mbed_official 146:f64d43ff0c18 4548 __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
mbed_official 146:f64d43ff0c18 4549 __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
mbed_official 146:f64d43ff0c18 4550 __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
mbed_official 146:f64d43ff0c18 4551 __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */
mbed_official 146:f64d43ff0c18 4552 __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
mbed_official 146:f64d43ff0c18 4553 __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
mbed_official 146:f64d43ff0c18 4554 __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
mbed_official 146:f64d43ff0c18 4555 __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
mbed_official 146:f64d43ff0c18 4556 __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
mbed_official 146:f64d43ff0c18 4557 __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
mbed_official 146:f64d43ff0c18 4558 __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
mbed_official 146:f64d43ff0c18 4559 __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */
mbed_official 146:f64d43ff0c18 4560 uint8_t RESERVED_14[4];
mbed_official 146:f64d43ff0c18 4561 __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
mbed_official 146:f64d43ff0c18 4562 __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
mbed_official 146:f64d43ff0c18 4563 __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
mbed_official 146:f64d43ff0c18 4564 __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
mbed_official 146:f64d43ff0c18 4565 __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
mbed_official 146:f64d43ff0c18 4566 __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
mbed_official 146:f64d43ff0c18 4567 __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
mbed_official 146:f64d43ff0c18 4568 __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
mbed_official 146:f64d43ff0c18 4569 uint8_t RESERVED_15[4];
mbed_official 146:f64d43ff0c18 4570 __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
mbed_official 146:f64d43ff0c18 4571 __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
mbed_official 146:f64d43ff0c18 4572 uint8_t RESERVED_16[12];
mbed_official 146:f64d43ff0c18 4573 __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */
mbed_official 146:f64d43ff0c18 4574 __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
mbed_official 146:f64d43ff0c18 4575 __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
mbed_official 146:f64d43ff0c18 4576 __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
mbed_official 146:f64d43ff0c18 4577 __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
mbed_official 146:f64d43ff0c18 4578 __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
mbed_official 146:f64d43ff0c18 4579 __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
mbed_official 146:f64d43ff0c18 4580 __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
mbed_official 146:f64d43ff0c18 4581 uint8_t RESERVED_17[4];
mbed_official 146:f64d43ff0c18 4582 __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
mbed_official 146:f64d43ff0c18 4583 __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
mbed_official 146:f64d43ff0c18 4584 __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
mbed_official 146:f64d43ff0c18 4585 __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
mbed_official 146:f64d43ff0c18 4586 __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
mbed_official 146:f64d43ff0c18 4587 __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
mbed_official 146:f64d43ff0c18 4588 __I uint32_t RMON_R_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
mbed_official 146:f64d43ff0c18 4589 __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */
mbed_official 146:f64d43ff0c18 4590 __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
mbed_official 146:f64d43ff0c18 4591 __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */
mbed_official 146:f64d43ff0c18 4592 __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
mbed_official 146:f64d43ff0c18 4593 __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
mbed_official 146:f64d43ff0c18 4594 __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
mbed_official 146:f64d43ff0c18 4595 __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
mbed_official 146:f64d43ff0c18 4596 __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
mbed_official 146:f64d43ff0c18 4597 uint8_t RESERVED_18[284];
mbed_official 146:f64d43ff0c18 4598 __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */
mbed_official 146:f64d43ff0c18 4599 __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */
mbed_official 146:f64d43ff0c18 4600 __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */
mbed_official 146:f64d43ff0c18 4601 __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */
mbed_official 146:f64d43ff0c18 4602 __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */
mbed_official 146:f64d43ff0c18 4603 __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */
mbed_official 146:f64d43ff0c18 4604 __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
mbed_official 146:f64d43ff0c18 4605 uint8_t RESERVED_19[488];
mbed_official 146:f64d43ff0c18 4606 __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */
mbed_official 146:f64d43ff0c18 4607 struct { /* offset: 0x608, array step: 0x8 */
mbed_official 146:f64d43ff0c18 4608 __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
mbed_official 146:f64d43ff0c18 4609 __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
mbed_official 146:f64d43ff0c18 4610 } CHANNEL[4];
mbed_official 146:f64d43ff0c18 4611 } ENET_Type, *ENET_MemMapPtr;
mbed_official 146:f64d43ff0c18 4612
mbed_official 146:f64d43ff0c18 4613 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4614 -- ENET - Register accessor macros
mbed_official 146:f64d43ff0c18 4615 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 4616
mbed_official 146:f64d43ff0c18 4617 /*!
mbed_official 146:f64d43ff0c18 4618 * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
mbed_official 146:f64d43ff0c18 4619 * @{
mbed_official 146:f64d43ff0c18 4620 */
mbed_official 146:f64d43ff0c18 4621
mbed_official 146:f64d43ff0c18 4622
mbed_official 146:f64d43ff0c18 4623 /* ENET - Register accessors */
mbed_official 146:f64d43ff0c18 4624 #define ENET_EIR_REG(base) ((base)->EIR)
mbed_official 146:f64d43ff0c18 4625 #define ENET_EIMR_REG(base) ((base)->EIMR)
mbed_official 146:f64d43ff0c18 4626 #define ENET_RDAR_REG(base) ((base)->RDAR)
mbed_official 146:f64d43ff0c18 4627 #define ENET_TDAR_REG(base) ((base)->TDAR)
mbed_official 146:f64d43ff0c18 4628 #define ENET_ECR_REG(base) ((base)->ECR)
mbed_official 146:f64d43ff0c18 4629 #define ENET_MMFR_REG(base) ((base)->MMFR)
mbed_official 146:f64d43ff0c18 4630 #define ENET_MSCR_REG(base) ((base)->MSCR)
mbed_official 146:f64d43ff0c18 4631 #define ENET_MIBC_REG(base) ((base)->MIBC)
mbed_official 146:f64d43ff0c18 4632 #define ENET_RCR_REG(base) ((base)->RCR)
mbed_official 146:f64d43ff0c18 4633 #define ENET_TCR_REG(base) ((base)->TCR)
mbed_official 146:f64d43ff0c18 4634 #define ENET_PALR_REG(base) ((base)->PALR)
mbed_official 146:f64d43ff0c18 4635 #define ENET_PAUR_REG(base) ((base)->PAUR)
mbed_official 146:f64d43ff0c18 4636 #define ENET_OPD_REG(base) ((base)->OPD)
mbed_official 146:f64d43ff0c18 4637 #define ENET_IAUR_REG(base) ((base)->IAUR)
mbed_official 146:f64d43ff0c18 4638 #define ENET_IALR_REG(base) ((base)->IALR)
mbed_official 146:f64d43ff0c18 4639 #define ENET_GAUR_REG(base) ((base)->GAUR)
mbed_official 146:f64d43ff0c18 4640 #define ENET_GALR_REG(base) ((base)->GALR)
mbed_official 146:f64d43ff0c18 4641 #define ENET_TFWR_REG(base) ((base)->TFWR)
mbed_official 146:f64d43ff0c18 4642 #define ENET_RDSR_REG(base) ((base)->RDSR)
mbed_official 146:f64d43ff0c18 4643 #define ENET_TDSR_REG(base) ((base)->TDSR)
mbed_official 146:f64d43ff0c18 4644 #define ENET_MRBR_REG(base) ((base)->MRBR)
mbed_official 146:f64d43ff0c18 4645 #define ENET_RSFL_REG(base) ((base)->RSFL)
mbed_official 146:f64d43ff0c18 4646 #define ENET_RSEM_REG(base) ((base)->RSEM)
mbed_official 146:f64d43ff0c18 4647 #define ENET_RAEM_REG(base) ((base)->RAEM)
mbed_official 146:f64d43ff0c18 4648 #define ENET_RAFL_REG(base) ((base)->RAFL)
mbed_official 146:f64d43ff0c18 4649 #define ENET_TSEM_REG(base) ((base)->TSEM)
mbed_official 146:f64d43ff0c18 4650 #define ENET_TAEM_REG(base) ((base)->TAEM)
mbed_official 146:f64d43ff0c18 4651 #define ENET_TAFL_REG(base) ((base)->TAFL)
mbed_official 146:f64d43ff0c18 4652 #define ENET_TIPG_REG(base) ((base)->TIPG)
mbed_official 146:f64d43ff0c18 4653 #define ENET_FTRL_REG(base) ((base)->FTRL)
mbed_official 146:f64d43ff0c18 4654 #define ENET_TACC_REG(base) ((base)->TACC)
mbed_official 146:f64d43ff0c18 4655 #define ENET_RACC_REG(base) ((base)->RACC)
mbed_official 146:f64d43ff0c18 4656 #define ENET_RMON_T_PACKETS_REG(base) ((base)->RMON_T_PACKETS)
mbed_official 146:f64d43ff0c18 4657 #define ENET_RMON_T_BC_PKT_REG(base) ((base)->RMON_T_BC_PKT)
mbed_official 146:f64d43ff0c18 4658 #define ENET_RMON_T_MC_PKT_REG(base) ((base)->RMON_T_MC_PKT)
mbed_official 146:f64d43ff0c18 4659 #define ENET_RMON_T_CRC_ALIGN_REG(base) ((base)->RMON_T_CRC_ALIGN)
mbed_official 146:f64d43ff0c18 4660 #define ENET_RMON_T_UNDERSIZE_REG(base) ((base)->RMON_T_UNDERSIZE)
mbed_official 146:f64d43ff0c18 4661 #define ENET_RMON_T_OVERSIZE_REG(base) ((base)->RMON_T_OVERSIZE)
mbed_official 146:f64d43ff0c18 4662 #define ENET_RMON_T_FRAG_REG(base) ((base)->RMON_T_FRAG)
mbed_official 146:f64d43ff0c18 4663 #define ENET_RMON_T_JAB_REG(base) ((base)->RMON_T_JAB)
mbed_official 146:f64d43ff0c18 4664 #define ENET_RMON_T_COL_REG(base) ((base)->RMON_T_COL)
mbed_official 146:f64d43ff0c18 4665 #define ENET_RMON_T_P64_REG(base) ((base)->RMON_T_P64)
mbed_official 146:f64d43ff0c18 4666 #define ENET_RMON_T_P65TO127_REG(base) ((base)->RMON_T_P65TO127)
mbed_official 146:f64d43ff0c18 4667 #define ENET_RMON_T_P128TO255_REG(base) ((base)->RMON_T_P128TO255)
mbed_official 146:f64d43ff0c18 4668 #define ENET_RMON_T_P256TO511_REG(base) ((base)->RMON_T_P256TO511)
mbed_official 146:f64d43ff0c18 4669 #define ENET_RMON_T_P512TO1023_REG(base) ((base)->RMON_T_P512TO1023)
mbed_official 146:f64d43ff0c18 4670 #define ENET_RMON_T_P1024TO2047_REG(base) ((base)->RMON_T_P1024TO2047)
mbed_official 146:f64d43ff0c18 4671 #define ENET_RMON_T_P_GTE2048_REG(base) ((base)->RMON_T_P_GTE2048)
mbed_official 146:f64d43ff0c18 4672 #define ENET_RMON_T_OCTETS_REG(base) ((base)->RMON_T_OCTETS)
mbed_official 146:f64d43ff0c18 4673 #define ENET_IEEE_T_FRAME_OK_REG(base) ((base)->IEEE_T_FRAME_OK)
mbed_official 146:f64d43ff0c18 4674 #define ENET_IEEE_T_1COL_REG(base) ((base)->IEEE_T_1COL)
mbed_official 146:f64d43ff0c18 4675 #define ENET_IEEE_T_MCOL_REG(base) ((base)->IEEE_T_MCOL)
mbed_official 146:f64d43ff0c18 4676 #define ENET_IEEE_T_DEF_REG(base) ((base)->IEEE_T_DEF)
mbed_official 146:f64d43ff0c18 4677 #define ENET_IEEE_T_LCOL_REG(base) ((base)->IEEE_T_LCOL)
mbed_official 146:f64d43ff0c18 4678 #define ENET_IEEE_T_EXCOL_REG(base) ((base)->IEEE_T_EXCOL)
mbed_official 146:f64d43ff0c18 4679 #define ENET_IEEE_T_MACERR_REG(base) ((base)->IEEE_T_MACERR)
mbed_official 146:f64d43ff0c18 4680 #define ENET_IEEE_T_CSERR_REG(base) ((base)->IEEE_T_CSERR)
mbed_official 146:f64d43ff0c18 4681 #define ENET_IEEE_T_FDXFC_REG(base) ((base)->IEEE_T_FDXFC)
mbed_official 146:f64d43ff0c18 4682 #define ENET_IEEE_T_OCTETS_OK_REG(base) ((base)->IEEE_T_OCTETS_OK)
mbed_official 146:f64d43ff0c18 4683 #define ENET_RMON_R_PACKETS_REG(base) ((base)->RMON_R_PACKETS)
mbed_official 146:f64d43ff0c18 4684 #define ENET_RMON_R_BC_PKT_REG(base) ((base)->RMON_R_BC_PKT)
mbed_official 146:f64d43ff0c18 4685 #define ENET_RMON_R_MC_PKT_REG(base) ((base)->RMON_R_MC_PKT)
mbed_official 146:f64d43ff0c18 4686 #define ENET_RMON_R_CRC_ALIGN_REG(base) ((base)->RMON_R_CRC_ALIGN)
mbed_official 146:f64d43ff0c18 4687 #define ENET_RMON_R_UNDERSIZE_REG(base) ((base)->RMON_R_UNDERSIZE)
mbed_official 146:f64d43ff0c18 4688 #define ENET_RMON_R_OVERSIZE_REG(base) ((base)->RMON_R_OVERSIZE)
mbed_official 146:f64d43ff0c18 4689 #define ENET_RMON_R_FRAG_REG(base) ((base)->RMON_R_FRAG)
mbed_official 146:f64d43ff0c18 4690 #define ENET_RMON_R_JAB_REG(base) ((base)->RMON_R_JAB)
mbed_official 146:f64d43ff0c18 4691 #define ENET_RMON_R_P64_REG(base) ((base)->RMON_R_P64)
mbed_official 146:f64d43ff0c18 4692 #define ENET_RMON_R_P65TO127_REG(base) ((base)->RMON_R_P65TO127)
mbed_official 146:f64d43ff0c18 4693 #define ENET_RMON_R_P128TO255_REG(base) ((base)->RMON_R_P128TO255)
mbed_official 146:f64d43ff0c18 4694 #define ENET_RMON_R_P256TO511_REG(base) ((base)->RMON_R_P256TO511)
mbed_official 146:f64d43ff0c18 4695 #define ENET_RMON_R_P512TO1023_REG(base) ((base)->RMON_R_P512TO1023)
mbed_official 146:f64d43ff0c18 4696 #define ENET_RMON_R_P1024TO2047_REG(base) ((base)->RMON_R_P1024TO2047)
mbed_official 146:f64d43ff0c18 4697 #define ENET_RMON_R_GTE2048_REG(base) ((base)->RMON_R_GTE2048)
mbed_official 146:f64d43ff0c18 4698 #define ENET_RMON_R_OCTETS_REG(base) ((base)->RMON_R_OCTETS)
mbed_official 146:f64d43ff0c18 4699 #define ENET_IEEE_R_DROP_REG(base) ((base)->IEEE_R_DROP)
mbed_official 146:f64d43ff0c18 4700 #define ENET_IEEE_R_FRAME_OK_REG(base) ((base)->IEEE_R_FRAME_OK)
mbed_official 146:f64d43ff0c18 4701 #define ENET_IEEE_R_CRC_REG(base) ((base)->IEEE_R_CRC)
mbed_official 146:f64d43ff0c18 4702 #define ENET_IEEE_R_ALIGN_REG(base) ((base)->IEEE_R_ALIGN)
mbed_official 146:f64d43ff0c18 4703 #define ENET_IEEE_R_MACERR_REG(base) ((base)->IEEE_R_MACERR)
mbed_official 146:f64d43ff0c18 4704 #define ENET_IEEE_R_FDXFC_REG(base) ((base)->IEEE_R_FDXFC)
mbed_official 146:f64d43ff0c18 4705 #define ENET_IEEE_R_OCTETS_OK_REG(base) ((base)->IEEE_R_OCTETS_OK)
mbed_official 146:f64d43ff0c18 4706 #define ENET_ATCR_REG(base) ((base)->ATCR)
mbed_official 146:f64d43ff0c18 4707 #define ENET_ATVR_REG(base) ((base)->ATVR)
mbed_official 146:f64d43ff0c18 4708 #define ENET_ATOFF_REG(base) ((base)->ATOFF)
mbed_official 146:f64d43ff0c18 4709 #define ENET_ATPER_REG(base) ((base)->ATPER)
mbed_official 146:f64d43ff0c18 4710 #define ENET_ATCOR_REG(base) ((base)->ATCOR)
mbed_official 146:f64d43ff0c18 4711 #define ENET_ATINC_REG(base) ((base)->ATINC)
mbed_official 146:f64d43ff0c18 4712 #define ENET_ATSTMP_REG(base) ((base)->ATSTMP)
mbed_official 146:f64d43ff0c18 4713 #define ENET_TGSR_REG(base) ((base)->TGSR)
mbed_official 146:f64d43ff0c18 4714 #define ENET_TCSR_REG(base,index) ((base)->CHANNEL[index].TCSR)
mbed_official 146:f64d43ff0c18 4715 #define ENET_TCCR_REG(base,index) ((base)->CHANNEL[index].TCCR)
mbed_official 146:f64d43ff0c18 4716
mbed_official 146:f64d43ff0c18 4717 /*!
mbed_official 146:f64d43ff0c18 4718 * @}
mbed_official 146:f64d43ff0c18 4719 */ /* end of group ENET_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 4720
mbed_official 146:f64d43ff0c18 4721
mbed_official 146:f64d43ff0c18 4722 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4723 -- ENET Register Masks
mbed_official 146:f64d43ff0c18 4724 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 4725
mbed_official 146:f64d43ff0c18 4726 /*!
mbed_official 146:f64d43ff0c18 4727 * @addtogroup ENET_Register_Masks ENET Register Masks
mbed_official 146:f64d43ff0c18 4728 * @{
mbed_official 146:f64d43ff0c18 4729 */
mbed_official 146:f64d43ff0c18 4730
mbed_official 146:f64d43ff0c18 4731 /* EIR Bit Fields */
mbed_official 146:f64d43ff0c18 4732 #define ENET_EIR_TS_TIMER_MASK 0x8000u
mbed_official 146:f64d43ff0c18 4733 #define ENET_EIR_TS_TIMER_SHIFT 15
mbed_official 146:f64d43ff0c18 4734 #define ENET_EIR_TS_AVAIL_MASK 0x10000u
mbed_official 146:f64d43ff0c18 4735 #define ENET_EIR_TS_AVAIL_SHIFT 16
mbed_official 146:f64d43ff0c18 4736 #define ENET_EIR_WAKEUP_MASK 0x20000u
mbed_official 146:f64d43ff0c18 4737 #define ENET_EIR_WAKEUP_SHIFT 17
mbed_official 146:f64d43ff0c18 4738 #define ENET_EIR_PLR_MASK 0x40000u
mbed_official 146:f64d43ff0c18 4739 #define ENET_EIR_PLR_SHIFT 18
mbed_official 146:f64d43ff0c18 4740 #define ENET_EIR_UN_MASK 0x80000u
mbed_official 146:f64d43ff0c18 4741 #define ENET_EIR_UN_SHIFT 19
mbed_official 146:f64d43ff0c18 4742 #define ENET_EIR_RL_MASK 0x100000u
mbed_official 146:f64d43ff0c18 4743 #define ENET_EIR_RL_SHIFT 20
mbed_official 146:f64d43ff0c18 4744 #define ENET_EIR_LC_MASK 0x200000u
mbed_official 146:f64d43ff0c18 4745 #define ENET_EIR_LC_SHIFT 21
mbed_official 146:f64d43ff0c18 4746 #define ENET_EIR_EBERR_MASK 0x400000u
mbed_official 146:f64d43ff0c18 4747 #define ENET_EIR_EBERR_SHIFT 22
mbed_official 146:f64d43ff0c18 4748 #define ENET_EIR_MII_MASK 0x800000u
mbed_official 146:f64d43ff0c18 4749 #define ENET_EIR_MII_SHIFT 23
mbed_official 146:f64d43ff0c18 4750 #define ENET_EIR_RXB_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 4751 #define ENET_EIR_RXB_SHIFT 24
mbed_official 146:f64d43ff0c18 4752 #define ENET_EIR_RXF_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 4753 #define ENET_EIR_RXF_SHIFT 25
mbed_official 146:f64d43ff0c18 4754 #define ENET_EIR_TXB_MASK 0x4000000u
mbed_official 146:f64d43ff0c18 4755 #define ENET_EIR_TXB_SHIFT 26
mbed_official 146:f64d43ff0c18 4756 #define ENET_EIR_TXF_MASK 0x8000000u
mbed_official 146:f64d43ff0c18 4757 #define ENET_EIR_TXF_SHIFT 27
mbed_official 146:f64d43ff0c18 4758 #define ENET_EIR_GRA_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 4759 #define ENET_EIR_GRA_SHIFT 28
mbed_official 146:f64d43ff0c18 4760 #define ENET_EIR_BABT_MASK 0x20000000u
mbed_official 146:f64d43ff0c18 4761 #define ENET_EIR_BABT_SHIFT 29
mbed_official 146:f64d43ff0c18 4762 #define ENET_EIR_BABR_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 4763 #define ENET_EIR_BABR_SHIFT 30
mbed_official 146:f64d43ff0c18 4764 /* EIMR Bit Fields */
mbed_official 146:f64d43ff0c18 4765 #define ENET_EIMR_TS_TIMER_MASK 0x8000u
mbed_official 146:f64d43ff0c18 4766 #define ENET_EIMR_TS_TIMER_SHIFT 15
mbed_official 146:f64d43ff0c18 4767 #define ENET_EIMR_TS_AVAIL_MASK 0x10000u
mbed_official 146:f64d43ff0c18 4768 #define ENET_EIMR_TS_AVAIL_SHIFT 16
mbed_official 146:f64d43ff0c18 4769 #define ENET_EIMR_WAKEUP_MASK 0x20000u
mbed_official 146:f64d43ff0c18 4770 #define ENET_EIMR_WAKEUP_SHIFT 17
mbed_official 146:f64d43ff0c18 4771 #define ENET_EIMR_PLR_MASK 0x40000u
mbed_official 146:f64d43ff0c18 4772 #define ENET_EIMR_PLR_SHIFT 18
mbed_official 146:f64d43ff0c18 4773 #define ENET_EIMR_UN_MASK 0x80000u
mbed_official 146:f64d43ff0c18 4774 #define ENET_EIMR_UN_SHIFT 19
mbed_official 146:f64d43ff0c18 4775 #define ENET_EIMR_RL_MASK 0x100000u
mbed_official 146:f64d43ff0c18 4776 #define ENET_EIMR_RL_SHIFT 20
mbed_official 146:f64d43ff0c18 4777 #define ENET_EIMR_LC_MASK 0x200000u
mbed_official 146:f64d43ff0c18 4778 #define ENET_EIMR_LC_SHIFT 21
mbed_official 146:f64d43ff0c18 4779 #define ENET_EIMR_EBERR_MASK 0x400000u
mbed_official 146:f64d43ff0c18 4780 #define ENET_EIMR_EBERR_SHIFT 22
mbed_official 146:f64d43ff0c18 4781 #define ENET_EIMR_MII_MASK 0x800000u
mbed_official 146:f64d43ff0c18 4782 #define ENET_EIMR_MII_SHIFT 23
mbed_official 146:f64d43ff0c18 4783 #define ENET_EIMR_RXB_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 4784 #define ENET_EIMR_RXB_SHIFT 24
mbed_official 146:f64d43ff0c18 4785 #define ENET_EIMR_RXF_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 4786 #define ENET_EIMR_RXF_SHIFT 25
mbed_official 146:f64d43ff0c18 4787 #define ENET_EIMR_TXB_MASK 0x4000000u
mbed_official 146:f64d43ff0c18 4788 #define ENET_EIMR_TXB_SHIFT 26
mbed_official 146:f64d43ff0c18 4789 #define ENET_EIMR_TXF_MASK 0x8000000u
mbed_official 146:f64d43ff0c18 4790 #define ENET_EIMR_TXF_SHIFT 27
mbed_official 146:f64d43ff0c18 4791 #define ENET_EIMR_GRA_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 4792 #define ENET_EIMR_GRA_SHIFT 28
mbed_official 146:f64d43ff0c18 4793 #define ENET_EIMR_BABT_MASK 0x20000000u
mbed_official 146:f64d43ff0c18 4794 #define ENET_EIMR_BABT_SHIFT 29
mbed_official 146:f64d43ff0c18 4795 #define ENET_EIMR_BABR_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 4796 #define ENET_EIMR_BABR_SHIFT 30
mbed_official 146:f64d43ff0c18 4797 /* RDAR Bit Fields */
mbed_official 146:f64d43ff0c18 4798 #define ENET_RDAR_RDAR_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 4799 #define ENET_RDAR_RDAR_SHIFT 24
mbed_official 146:f64d43ff0c18 4800 /* TDAR Bit Fields */
mbed_official 146:f64d43ff0c18 4801 #define ENET_TDAR_TDAR_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 4802 #define ENET_TDAR_TDAR_SHIFT 24
mbed_official 146:f64d43ff0c18 4803 /* ECR Bit Fields */
mbed_official 146:f64d43ff0c18 4804 #define ENET_ECR_RESET_MASK 0x1u
mbed_official 146:f64d43ff0c18 4805 #define ENET_ECR_RESET_SHIFT 0
mbed_official 146:f64d43ff0c18 4806 #define ENET_ECR_ETHEREN_MASK 0x2u
mbed_official 146:f64d43ff0c18 4807 #define ENET_ECR_ETHEREN_SHIFT 1
mbed_official 146:f64d43ff0c18 4808 #define ENET_ECR_MAGICEN_MASK 0x4u
mbed_official 146:f64d43ff0c18 4809 #define ENET_ECR_MAGICEN_SHIFT 2
mbed_official 146:f64d43ff0c18 4810 #define ENET_ECR_SLEEP_MASK 0x8u
mbed_official 146:f64d43ff0c18 4811 #define ENET_ECR_SLEEP_SHIFT 3
mbed_official 146:f64d43ff0c18 4812 #define ENET_ECR_EN1588_MASK 0x10u
mbed_official 146:f64d43ff0c18 4813 #define ENET_ECR_EN1588_SHIFT 4
mbed_official 146:f64d43ff0c18 4814 #define ENET_ECR_DBGEN_MASK 0x40u
mbed_official 146:f64d43ff0c18 4815 #define ENET_ECR_DBGEN_SHIFT 6
mbed_official 146:f64d43ff0c18 4816 #define ENET_ECR_STOPEN_MASK 0x80u
mbed_official 146:f64d43ff0c18 4817 #define ENET_ECR_STOPEN_SHIFT 7
mbed_official 146:f64d43ff0c18 4818 #define ENET_ECR_DBSWP_MASK 0x100u
mbed_official 146:f64d43ff0c18 4819 #define ENET_ECR_DBSWP_SHIFT 8
mbed_official 146:f64d43ff0c18 4820 /* MMFR Bit Fields */
mbed_official 146:f64d43ff0c18 4821 #define ENET_MMFR_DATA_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 4822 #define ENET_MMFR_DATA_SHIFT 0
mbed_official 146:f64d43ff0c18 4823 #define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_DATA_SHIFT))&ENET_MMFR_DATA_MASK)
mbed_official 146:f64d43ff0c18 4824 #define ENET_MMFR_TA_MASK 0x30000u
mbed_official 146:f64d43ff0c18 4825 #define ENET_MMFR_TA_SHIFT 16
mbed_official 146:f64d43ff0c18 4826 #define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_TA_SHIFT))&ENET_MMFR_TA_MASK)
mbed_official 146:f64d43ff0c18 4827 #define ENET_MMFR_RA_MASK 0x7C0000u
mbed_official 146:f64d43ff0c18 4828 #define ENET_MMFR_RA_SHIFT 18
mbed_official 146:f64d43ff0c18 4829 #define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_RA_SHIFT))&ENET_MMFR_RA_MASK)
mbed_official 146:f64d43ff0c18 4830 #define ENET_MMFR_PA_MASK 0xF800000u
mbed_official 146:f64d43ff0c18 4831 #define ENET_MMFR_PA_SHIFT 23
mbed_official 146:f64d43ff0c18 4832 #define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_PA_SHIFT))&ENET_MMFR_PA_MASK)
mbed_official 146:f64d43ff0c18 4833 #define ENET_MMFR_OP_MASK 0x30000000u
mbed_official 146:f64d43ff0c18 4834 #define ENET_MMFR_OP_SHIFT 28
mbed_official 146:f64d43ff0c18 4835 #define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_OP_SHIFT))&ENET_MMFR_OP_MASK)
mbed_official 146:f64d43ff0c18 4836 #define ENET_MMFR_ST_MASK 0xC0000000u
mbed_official 146:f64d43ff0c18 4837 #define ENET_MMFR_ST_SHIFT 30
mbed_official 146:f64d43ff0c18 4838 #define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_ST_SHIFT))&ENET_MMFR_ST_MASK)
mbed_official 146:f64d43ff0c18 4839 /* MSCR Bit Fields */
mbed_official 146:f64d43ff0c18 4840 #define ENET_MSCR_MII_SPEED_MASK 0x7Eu
mbed_official 146:f64d43ff0c18 4841 #define ENET_MSCR_MII_SPEED_SHIFT 1
mbed_official 146:f64d43ff0c18 4842 #define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_MII_SPEED_SHIFT))&ENET_MSCR_MII_SPEED_MASK)
mbed_official 146:f64d43ff0c18 4843 #define ENET_MSCR_DIS_PRE_MASK 0x80u
mbed_official 146:f64d43ff0c18 4844 #define ENET_MSCR_DIS_PRE_SHIFT 7
mbed_official 146:f64d43ff0c18 4845 #define ENET_MSCR_HOLDTIME_MASK 0x700u
mbed_official 146:f64d43ff0c18 4846 #define ENET_MSCR_HOLDTIME_SHIFT 8
mbed_official 146:f64d43ff0c18 4847 #define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_HOLDTIME_SHIFT))&ENET_MSCR_HOLDTIME_MASK)
mbed_official 146:f64d43ff0c18 4848 /* MIBC Bit Fields */
mbed_official 146:f64d43ff0c18 4849 #define ENET_MIBC_MIB_CLEAR_MASK 0x20000000u
mbed_official 146:f64d43ff0c18 4850 #define ENET_MIBC_MIB_CLEAR_SHIFT 29
mbed_official 146:f64d43ff0c18 4851 #define ENET_MIBC_MIB_IDLE_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 4852 #define ENET_MIBC_MIB_IDLE_SHIFT 30
mbed_official 146:f64d43ff0c18 4853 #define ENET_MIBC_MIB_DIS_MASK 0x80000000u
mbed_official 146:f64d43ff0c18 4854 #define ENET_MIBC_MIB_DIS_SHIFT 31
mbed_official 146:f64d43ff0c18 4855 /* RCR Bit Fields */
mbed_official 146:f64d43ff0c18 4856 #define ENET_RCR_LOOP_MASK 0x1u
mbed_official 146:f64d43ff0c18 4857 #define ENET_RCR_LOOP_SHIFT 0
mbed_official 146:f64d43ff0c18 4858 #define ENET_RCR_DRT_MASK 0x2u
mbed_official 146:f64d43ff0c18 4859 #define ENET_RCR_DRT_SHIFT 1
mbed_official 146:f64d43ff0c18 4860 #define ENET_RCR_MII_MODE_MASK 0x4u
mbed_official 146:f64d43ff0c18 4861 #define ENET_RCR_MII_MODE_SHIFT 2
mbed_official 146:f64d43ff0c18 4862 #define ENET_RCR_PROM_MASK 0x8u
mbed_official 146:f64d43ff0c18 4863 #define ENET_RCR_PROM_SHIFT 3
mbed_official 146:f64d43ff0c18 4864 #define ENET_RCR_BC_REJ_MASK 0x10u
mbed_official 146:f64d43ff0c18 4865 #define ENET_RCR_BC_REJ_SHIFT 4
mbed_official 146:f64d43ff0c18 4866 #define ENET_RCR_FCE_MASK 0x20u
mbed_official 146:f64d43ff0c18 4867 #define ENET_RCR_FCE_SHIFT 5
mbed_official 146:f64d43ff0c18 4868 #define ENET_RCR_RMII_MODE_MASK 0x100u
mbed_official 146:f64d43ff0c18 4869 #define ENET_RCR_RMII_MODE_SHIFT 8
mbed_official 146:f64d43ff0c18 4870 #define ENET_RCR_RMII_10T_MASK 0x200u
mbed_official 146:f64d43ff0c18 4871 #define ENET_RCR_RMII_10T_SHIFT 9
mbed_official 146:f64d43ff0c18 4872 #define ENET_RCR_PADEN_MASK 0x1000u
mbed_official 146:f64d43ff0c18 4873 #define ENET_RCR_PADEN_SHIFT 12
mbed_official 146:f64d43ff0c18 4874 #define ENET_RCR_PAUFWD_MASK 0x2000u
mbed_official 146:f64d43ff0c18 4875 #define ENET_RCR_PAUFWD_SHIFT 13
mbed_official 146:f64d43ff0c18 4876 #define ENET_RCR_CRCFWD_MASK 0x4000u
mbed_official 146:f64d43ff0c18 4877 #define ENET_RCR_CRCFWD_SHIFT 14
mbed_official 146:f64d43ff0c18 4878 #define ENET_RCR_CFEN_MASK 0x8000u
mbed_official 146:f64d43ff0c18 4879 #define ENET_RCR_CFEN_SHIFT 15
mbed_official 146:f64d43ff0c18 4880 #define ENET_RCR_MAX_FL_MASK 0x3FFF0000u
mbed_official 146:f64d43ff0c18 4881 #define ENET_RCR_MAX_FL_SHIFT 16
mbed_official 146:f64d43ff0c18 4882 #define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MAX_FL_SHIFT))&ENET_RCR_MAX_FL_MASK)
mbed_official 146:f64d43ff0c18 4883 #define ENET_RCR_NLC_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 4884 #define ENET_RCR_NLC_SHIFT 30
mbed_official 146:f64d43ff0c18 4885 #define ENET_RCR_GRS_MASK 0x80000000u
mbed_official 146:f64d43ff0c18 4886 #define ENET_RCR_GRS_SHIFT 31
mbed_official 146:f64d43ff0c18 4887 /* TCR Bit Fields */
mbed_official 146:f64d43ff0c18 4888 #define ENET_TCR_GTS_MASK 0x1u
mbed_official 146:f64d43ff0c18 4889 #define ENET_TCR_GTS_SHIFT 0
mbed_official 146:f64d43ff0c18 4890 #define ENET_TCR_FDEN_MASK 0x4u
mbed_official 146:f64d43ff0c18 4891 #define ENET_TCR_FDEN_SHIFT 2
mbed_official 146:f64d43ff0c18 4892 #define ENET_TCR_TFC_PAUSE_MASK 0x8u
mbed_official 146:f64d43ff0c18 4893 #define ENET_TCR_TFC_PAUSE_SHIFT 3
mbed_official 146:f64d43ff0c18 4894 #define ENET_TCR_RFC_PAUSE_MASK 0x10u
mbed_official 146:f64d43ff0c18 4895 #define ENET_TCR_RFC_PAUSE_SHIFT 4
mbed_official 146:f64d43ff0c18 4896 #define ENET_TCR_ADDSEL_MASK 0xE0u
mbed_official 146:f64d43ff0c18 4897 #define ENET_TCR_ADDSEL_SHIFT 5
mbed_official 146:f64d43ff0c18 4898 #define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDSEL_SHIFT))&ENET_TCR_ADDSEL_MASK)
mbed_official 146:f64d43ff0c18 4899 #define ENET_TCR_ADDINS_MASK 0x100u
mbed_official 146:f64d43ff0c18 4900 #define ENET_TCR_ADDINS_SHIFT 8
mbed_official 146:f64d43ff0c18 4901 #define ENET_TCR_CRCFWD_MASK 0x200u
mbed_official 146:f64d43ff0c18 4902 #define ENET_TCR_CRCFWD_SHIFT 9
mbed_official 146:f64d43ff0c18 4903 /* PALR Bit Fields */
mbed_official 146:f64d43ff0c18 4904 #define ENET_PALR_PADDR1_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 4905 #define ENET_PALR_PADDR1_SHIFT 0
mbed_official 146:f64d43ff0c18 4906 #define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_PALR_PADDR1_SHIFT))&ENET_PALR_PADDR1_MASK)
mbed_official 146:f64d43ff0c18 4907 /* PAUR Bit Fields */
mbed_official 146:f64d43ff0c18 4908 #define ENET_PAUR_TYPE_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 4909 #define ENET_PAUR_TYPE_SHIFT 0
mbed_official 146:f64d43ff0c18 4910 #define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_TYPE_SHIFT))&ENET_PAUR_TYPE_MASK)
mbed_official 146:f64d43ff0c18 4911 #define ENET_PAUR_PADDR2_MASK 0xFFFF0000u
mbed_official 146:f64d43ff0c18 4912 #define ENET_PAUR_PADDR2_SHIFT 16
mbed_official 146:f64d43ff0c18 4913 #define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_PADDR2_SHIFT))&ENET_PAUR_PADDR2_MASK)
mbed_official 146:f64d43ff0c18 4914 /* OPD Bit Fields */
mbed_official 146:f64d43ff0c18 4915 #define ENET_OPD_PAUSE_DUR_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 4916 #define ENET_OPD_PAUSE_DUR_SHIFT 0
mbed_official 146:f64d43ff0c18 4917 #define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x))<<ENET_OPD_PAUSE_DUR_SHIFT))&ENET_OPD_PAUSE_DUR_MASK)
mbed_official 146:f64d43ff0c18 4918 #define ENET_OPD_OPCODE_MASK 0xFFFF0000u
mbed_official 146:f64d43ff0c18 4919 #define ENET_OPD_OPCODE_SHIFT 16
mbed_official 146:f64d43ff0c18 4920 #define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_OPD_OPCODE_SHIFT))&ENET_OPD_OPCODE_MASK)
mbed_official 146:f64d43ff0c18 4921 /* IAUR Bit Fields */
mbed_official 146:f64d43ff0c18 4922 #define ENET_IAUR_IADDR1_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 4923 #define ENET_IAUR_IADDR1_SHIFT 0
mbed_official 146:f64d43ff0c18 4924 #define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_IAUR_IADDR1_SHIFT))&ENET_IAUR_IADDR1_MASK)
mbed_official 146:f64d43ff0c18 4925 /* IALR Bit Fields */
mbed_official 146:f64d43ff0c18 4926 #define ENET_IALR_IADDR2_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 4927 #define ENET_IALR_IADDR2_SHIFT 0
mbed_official 146:f64d43ff0c18 4928 #define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_IALR_IADDR2_SHIFT))&ENET_IALR_IADDR2_MASK)
mbed_official 146:f64d43ff0c18 4929 /* GAUR Bit Fields */
mbed_official 146:f64d43ff0c18 4930 #define ENET_GAUR_GADDR1_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 4931 #define ENET_GAUR_GADDR1_SHIFT 0
mbed_official 146:f64d43ff0c18 4932 #define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_GAUR_GADDR1_SHIFT))&ENET_GAUR_GADDR1_MASK)
mbed_official 146:f64d43ff0c18 4933 /* GALR Bit Fields */
mbed_official 146:f64d43ff0c18 4934 #define ENET_GALR_GADDR2_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 4935 #define ENET_GALR_GADDR2_SHIFT 0
mbed_official 146:f64d43ff0c18 4936 #define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_GALR_GADDR2_SHIFT))&ENET_GALR_GADDR2_MASK)
mbed_official 146:f64d43ff0c18 4937 /* TFWR Bit Fields */
mbed_official 146:f64d43ff0c18 4938 #define ENET_TFWR_TFWR_MASK 0x3Fu
mbed_official 146:f64d43ff0c18 4939 #define ENET_TFWR_TFWR_SHIFT 0
mbed_official 146:f64d43ff0c18 4940 #define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_TFWR_SHIFT))&ENET_TFWR_TFWR_MASK)
mbed_official 146:f64d43ff0c18 4941 #define ENET_TFWR_STRFWD_MASK 0x100u
mbed_official 146:f64d43ff0c18 4942 #define ENET_TFWR_STRFWD_SHIFT 8
mbed_official 146:f64d43ff0c18 4943 /* RDSR Bit Fields */
mbed_official 146:f64d43ff0c18 4944 #define ENET_RDSR_R_DES_START_MASK 0xFFFFFFF8u
mbed_official 146:f64d43ff0c18 4945 #define ENET_RDSR_R_DES_START_SHIFT 3
mbed_official 146:f64d43ff0c18 4946 #define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_RDSR_R_DES_START_SHIFT))&ENET_RDSR_R_DES_START_MASK)
mbed_official 146:f64d43ff0c18 4947 /* TDSR Bit Fields */
mbed_official 146:f64d43ff0c18 4948 #define ENET_TDSR_X_DES_START_MASK 0xFFFFFFF8u
mbed_official 146:f64d43ff0c18 4949 #define ENET_TDSR_X_DES_START_SHIFT 3
mbed_official 146:f64d43ff0c18 4950 #define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_TDSR_X_DES_START_SHIFT))&ENET_TDSR_X_DES_START_MASK)
mbed_official 146:f64d43ff0c18 4951 /* MRBR Bit Fields */
mbed_official 146:f64d43ff0c18 4952 #define ENET_MRBR_R_BUF_SIZE_MASK 0x3FF0u
mbed_official 146:f64d43ff0c18 4953 #define ENET_MRBR_R_BUF_SIZE_SHIFT 4
mbed_official 146:f64d43ff0c18 4954 #define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x))<<ENET_MRBR_R_BUF_SIZE_SHIFT))&ENET_MRBR_R_BUF_SIZE_MASK)
mbed_official 146:f64d43ff0c18 4955 /* RSFL Bit Fields */
mbed_official 146:f64d43ff0c18 4956 #define ENET_RSFL_RX_SECTION_FULL_MASK 0xFFu
mbed_official 146:f64d43ff0c18 4957 #define ENET_RSFL_RX_SECTION_FULL_SHIFT 0
mbed_official 146:f64d43ff0c18 4958 #define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSFL_RX_SECTION_FULL_SHIFT))&ENET_RSFL_RX_SECTION_FULL_MASK)
mbed_official 146:f64d43ff0c18 4959 /* RSEM Bit Fields */
mbed_official 146:f64d43ff0c18 4960 #define ENET_RSEM_RX_SECTION_EMPTY_MASK 0xFFu
mbed_official 146:f64d43ff0c18 4961 #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT 0
mbed_official 146:f64d43ff0c18 4962 #define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_RX_SECTION_EMPTY_SHIFT))&ENET_RSEM_RX_SECTION_EMPTY_MASK)
mbed_official 146:f64d43ff0c18 4963 #define ENET_RSEM_STAT_SECTION_EMPTY_MASK 0x1F0000u
mbed_official 146:f64d43ff0c18 4964 #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT 16
mbed_official 146:f64d43ff0c18 4965 #define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_STAT_SECTION_EMPTY_SHIFT))&ENET_RSEM_STAT_SECTION_EMPTY_MASK)
mbed_official 146:f64d43ff0c18 4966 /* RAEM Bit Fields */
mbed_official 146:f64d43ff0c18 4967 #define ENET_RAEM_RX_ALMOST_EMPTY_MASK 0xFFu
mbed_official 146:f64d43ff0c18 4968 #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT 0
mbed_official 146:f64d43ff0c18 4969 #define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RAEM_RX_ALMOST_EMPTY_SHIFT))&ENET_RAEM_RX_ALMOST_EMPTY_MASK)
mbed_official 146:f64d43ff0c18 4970 /* RAFL Bit Fields */
mbed_official 146:f64d43ff0c18 4971 #define ENET_RAFL_RX_ALMOST_FULL_MASK 0xFFu
mbed_official 146:f64d43ff0c18 4972 #define ENET_RAFL_RX_ALMOST_FULL_SHIFT 0
mbed_official 146:f64d43ff0c18 4973 #define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RAFL_RX_ALMOST_FULL_SHIFT))&ENET_RAFL_RX_ALMOST_FULL_MASK)
mbed_official 146:f64d43ff0c18 4974 /* TSEM Bit Fields */
mbed_official 146:f64d43ff0c18 4975 #define ENET_TSEM_TX_SECTION_EMPTY_MASK 0xFFu
mbed_official 146:f64d43ff0c18 4976 #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT 0
mbed_official 146:f64d43ff0c18 4977 #define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_TSEM_TX_SECTION_EMPTY_SHIFT))&ENET_TSEM_TX_SECTION_EMPTY_MASK)
mbed_official 146:f64d43ff0c18 4978 /* TAEM Bit Fields */
mbed_official 146:f64d43ff0c18 4979 #define ENET_TAEM_TX_ALMOST_EMPTY_MASK 0xFFu
mbed_official 146:f64d43ff0c18 4980 #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT 0
mbed_official 146:f64d43ff0c18 4981 #define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_TAEM_TX_ALMOST_EMPTY_SHIFT))&ENET_TAEM_TX_ALMOST_EMPTY_MASK)
mbed_official 146:f64d43ff0c18 4982 /* TAFL Bit Fields */
mbed_official 146:f64d43ff0c18 4983 #define ENET_TAFL_TX_ALMOST_FULL_MASK 0xFFu
mbed_official 146:f64d43ff0c18 4984 #define ENET_TAFL_TX_ALMOST_FULL_SHIFT 0
mbed_official 146:f64d43ff0c18 4985 #define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TAFL_TX_ALMOST_FULL_SHIFT))&ENET_TAFL_TX_ALMOST_FULL_MASK)
mbed_official 146:f64d43ff0c18 4986 /* TIPG Bit Fields */
mbed_official 146:f64d43ff0c18 4987 #define ENET_TIPG_IPG_MASK 0x1Fu
mbed_official 146:f64d43ff0c18 4988 #define ENET_TIPG_IPG_SHIFT 0
mbed_official 146:f64d43ff0c18 4989 #define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x))<<ENET_TIPG_IPG_SHIFT))&ENET_TIPG_IPG_MASK)
mbed_official 146:f64d43ff0c18 4990 /* FTRL Bit Fields */
mbed_official 146:f64d43ff0c18 4991 #define ENET_FTRL_TRUNC_FL_MASK 0x3FFFu
mbed_official 146:f64d43ff0c18 4992 #define ENET_FTRL_TRUNC_FL_SHIFT 0
mbed_official 146:f64d43ff0c18 4993 #define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_FTRL_TRUNC_FL_SHIFT))&ENET_FTRL_TRUNC_FL_MASK)
mbed_official 146:f64d43ff0c18 4994 /* TACC Bit Fields */
mbed_official 146:f64d43ff0c18 4995 #define ENET_TACC_SHIFT16_MASK 0x1u
mbed_official 146:f64d43ff0c18 4996 #define ENET_TACC_SHIFT16_SHIFT 0
mbed_official 146:f64d43ff0c18 4997 #define ENET_TACC_IPCHK_MASK 0x8u
mbed_official 146:f64d43ff0c18 4998 #define ENET_TACC_IPCHK_SHIFT 3
mbed_official 146:f64d43ff0c18 4999 #define ENET_TACC_PROCHK_MASK 0x10u
mbed_official 146:f64d43ff0c18 5000 #define ENET_TACC_PROCHK_SHIFT 4
mbed_official 146:f64d43ff0c18 5001 /* RACC Bit Fields */
mbed_official 146:f64d43ff0c18 5002 #define ENET_RACC_PADREM_MASK 0x1u
mbed_official 146:f64d43ff0c18 5003 #define ENET_RACC_PADREM_SHIFT 0
mbed_official 146:f64d43ff0c18 5004 #define ENET_RACC_IPDIS_MASK 0x2u
mbed_official 146:f64d43ff0c18 5005 #define ENET_RACC_IPDIS_SHIFT 1
mbed_official 146:f64d43ff0c18 5006 #define ENET_RACC_PRODIS_MASK 0x4u
mbed_official 146:f64d43ff0c18 5007 #define ENET_RACC_PRODIS_SHIFT 2
mbed_official 146:f64d43ff0c18 5008 #define ENET_RACC_LINEDIS_MASK 0x40u
mbed_official 146:f64d43ff0c18 5009 #define ENET_RACC_LINEDIS_SHIFT 6
mbed_official 146:f64d43ff0c18 5010 #define ENET_RACC_SHIFT16_MASK 0x80u
mbed_official 146:f64d43ff0c18 5011 #define ENET_RACC_SHIFT16_SHIFT 7
mbed_official 146:f64d43ff0c18 5012 /* RMON_T_PACKETS Bit Fields */
mbed_official 146:f64d43ff0c18 5013 #define ENET_RMON_T_PACKETS_TXPKTS_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5014 #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT 0
mbed_official 146:f64d43ff0c18 5015 #define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_PACKETS_TXPKTS_SHIFT))&ENET_RMON_T_PACKETS_TXPKTS_MASK)
mbed_official 146:f64d43ff0c18 5016 /* RMON_T_BC_PKT Bit Fields */
mbed_official 146:f64d43ff0c18 5017 #define ENET_RMON_T_BC_PKT_TXPKTS_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5018 #define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT 0
mbed_official 146:f64d43ff0c18 5019 #define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_BC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_BC_PKT_TXPKTS_MASK)
mbed_official 146:f64d43ff0c18 5020 /* RMON_T_MC_PKT Bit Fields */
mbed_official 146:f64d43ff0c18 5021 #define ENET_RMON_T_MC_PKT_TXPKTS_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5022 #define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT 0
mbed_official 146:f64d43ff0c18 5023 #define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_MC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_MC_PKT_TXPKTS_MASK)
mbed_official 146:f64d43ff0c18 5024 /* RMON_T_CRC_ALIGN Bit Fields */
mbed_official 146:f64d43ff0c18 5025 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5026 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT 0
mbed_official 146:f64d43ff0c18 5027 #define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT))&ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
mbed_official 146:f64d43ff0c18 5028 /* RMON_T_UNDERSIZE Bit Fields */
mbed_official 146:f64d43ff0c18 5029 #define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5030 #define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT 0
mbed_official 146:f64d43ff0c18 5031 #define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
mbed_official 146:f64d43ff0c18 5032 /* RMON_T_OVERSIZE Bit Fields */
mbed_official 146:f64d43ff0c18 5033 #define ENET_RMON_T_OVERSIZE_TXPKTS_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5034 #define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT 0
mbed_official 146:f64d43ff0c18 5035 #define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
mbed_official 146:f64d43ff0c18 5036 /* RMON_T_FRAG Bit Fields */
mbed_official 146:f64d43ff0c18 5037 #define ENET_RMON_T_FRAG_TXPKTS_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5038 #define ENET_RMON_T_FRAG_TXPKTS_SHIFT 0
mbed_official 146:f64d43ff0c18 5039 #define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_FRAG_TXPKTS_SHIFT))&ENET_RMON_T_FRAG_TXPKTS_MASK)
mbed_official 146:f64d43ff0c18 5040 /* RMON_T_JAB Bit Fields */
mbed_official 146:f64d43ff0c18 5041 #define ENET_RMON_T_JAB_TXPKTS_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5042 #define ENET_RMON_T_JAB_TXPKTS_SHIFT 0
mbed_official 146:f64d43ff0c18 5043 #define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_JAB_TXPKTS_SHIFT))&ENET_RMON_T_JAB_TXPKTS_MASK)
mbed_official 146:f64d43ff0c18 5044 /* RMON_T_COL Bit Fields */
mbed_official 146:f64d43ff0c18 5045 #define ENET_RMON_T_COL_TXPKTS_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5046 #define ENET_RMON_T_COL_TXPKTS_SHIFT 0
mbed_official 146:f64d43ff0c18 5047 #define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_COL_TXPKTS_SHIFT))&ENET_RMON_T_COL_TXPKTS_MASK)
mbed_official 146:f64d43ff0c18 5048 /* RMON_T_P64 Bit Fields */
mbed_official 146:f64d43ff0c18 5049 #define ENET_RMON_T_P64_TXPKTS_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5050 #define ENET_RMON_T_P64_TXPKTS_SHIFT 0
mbed_official 146:f64d43ff0c18 5051 #define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P64_TXPKTS_SHIFT))&ENET_RMON_T_P64_TXPKTS_MASK)
mbed_official 146:f64d43ff0c18 5052 /* RMON_T_P65TO127 Bit Fields */
mbed_official 146:f64d43ff0c18 5053 #define ENET_RMON_T_P65TO127_TXPKTS_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5054 #define ENET_RMON_T_P65TO127_TXPKTS_SHIFT 0
mbed_official 146:f64d43ff0c18 5055 #define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P65TO127_TXPKTS_SHIFT))&ENET_RMON_T_P65TO127_TXPKTS_MASK)
mbed_official 146:f64d43ff0c18 5056 /* RMON_T_P128TO255 Bit Fields */
mbed_official 146:f64d43ff0c18 5057 #define ENET_RMON_T_P128TO255_TXPKTS_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5058 #define ENET_RMON_T_P128TO255_TXPKTS_SHIFT 0
mbed_official 146:f64d43ff0c18 5059 #define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P128TO255_TXPKTS_SHIFT))&ENET_RMON_T_P128TO255_TXPKTS_MASK)
mbed_official 146:f64d43ff0c18 5060 /* RMON_T_P256TO511 Bit Fields */
mbed_official 146:f64d43ff0c18 5061 #define ENET_RMON_T_P256TO511_TXPKTS_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5062 #define ENET_RMON_T_P256TO511_TXPKTS_SHIFT 0
mbed_official 146:f64d43ff0c18 5063 #define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P256TO511_TXPKTS_SHIFT))&ENET_RMON_T_P256TO511_TXPKTS_MASK)
mbed_official 146:f64d43ff0c18 5064 /* RMON_T_P512TO1023 Bit Fields */
mbed_official 146:f64d43ff0c18 5065 #define ENET_RMON_T_P512TO1023_TXPKTS_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5066 #define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT 0
mbed_official 146:f64d43ff0c18 5067 #define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P512TO1023_TXPKTS_SHIFT))&ENET_RMON_T_P512TO1023_TXPKTS_MASK)
mbed_official 146:f64d43ff0c18 5068 /* RMON_T_P1024TO2047 Bit Fields */
mbed_official 146:f64d43ff0c18 5069 #define ENET_RMON_T_P1024TO2047_TXPKTS_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5070 #define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT 0
mbed_official 146:f64d43ff0c18 5071 #define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT))&ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
mbed_official 146:f64d43ff0c18 5072 /* RMON_T_P_GTE2048 Bit Fields */
mbed_official 146:f64d43ff0c18 5073 #define ENET_RMON_T_P_GTE2048_TXPKTS_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5074 #define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT 0
mbed_official 146:f64d43ff0c18 5075 #define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT))&ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
mbed_official 146:f64d43ff0c18 5076 /* RMON_T_OCTETS Bit Fields */
mbed_official 146:f64d43ff0c18 5077 #define ENET_RMON_T_OCTETS_TXOCTS_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 5078 #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT 0
mbed_official 146:f64d43ff0c18 5079 #define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OCTETS_TXOCTS_SHIFT))&ENET_RMON_T_OCTETS_TXOCTS_MASK)
mbed_official 146:f64d43ff0c18 5080 /* IEEE_T_FRAME_OK Bit Fields */
mbed_official 146:f64d43ff0c18 5081 #define ENET_IEEE_T_FRAME_OK_COUNT_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5082 #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT 0
mbed_official 146:f64d43ff0c18 5083 #define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_T_FRAME_OK_COUNT_MASK)
mbed_official 146:f64d43ff0c18 5084 /* IEEE_T_1COL Bit Fields */
mbed_official 146:f64d43ff0c18 5085 #define ENET_IEEE_T_1COL_COUNT_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5086 #define ENET_IEEE_T_1COL_COUNT_SHIFT 0
mbed_official 146:f64d43ff0c18 5087 #define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_1COL_COUNT_SHIFT))&ENET_IEEE_T_1COL_COUNT_MASK)
mbed_official 146:f64d43ff0c18 5088 /* IEEE_T_MCOL Bit Fields */
mbed_official 146:f64d43ff0c18 5089 #define ENET_IEEE_T_MCOL_COUNT_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5090 #define ENET_IEEE_T_MCOL_COUNT_SHIFT 0
mbed_official 146:f64d43ff0c18 5091 #define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MCOL_COUNT_SHIFT))&ENET_IEEE_T_MCOL_COUNT_MASK)
mbed_official 146:f64d43ff0c18 5092 /* IEEE_T_DEF Bit Fields */
mbed_official 146:f64d43ff0c18 5093 #define ENET_IEEE_T_DEF_COUNT_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5094 #define ENET_IEEE_T_DEF_COUNT_SHIFT 0
mbed_official 146:f64d43ff0c18 5095 #define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_DEF_COUNT_SHIFT))&ENET_IEEE_T_DEF_COUNT_MASK)
mbed_official 146:f64d43ff0c18 5096 /* IEEE_T_LCOL Bit Fields */
mbed_official 146:f64d43ff0c18 5097 #define ENET_IEEE_T_LCOL_COUNT_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5098 #define ENET_IEEE_T_LCOL_COUNT_SHIFT 0
mbed_official 146:f64d43ff0c18 5099 #define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_LCOL_COUNT_SHIFT))&ENET_IEEE_T_LCOL_COUNT_MASK)
mbed_official 146:f64d43ff0c18 5100 /* IEEE_T_EXCOL Bit Fields */
mbed_official 146:f64d43ff0c18 5101 #define ENET_IEEE_T_EXCOL_COUNT_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5102 #define ENET_IEEE_T_EXCOL_COUNT_SHIFT 0
mbed_official 146:f64d43ff0c18 5103 #define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_EXCOL_COUNT_SHIFT))&ENET_IEEE_T_EXCOL_COUNT_MASK)
mbed_official 146:f64d43ff0c18 5104 /* IEEE_T_MACERR Bit Fields */
mbed_official 146:f64d43ff0c18 5105 #define ENET_IEEE_T_MACERR_COUNT_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5106 #define ENET_IEEE_T_MACERR_COUNT_SHIFT 0
mbed_official 146:f64d43ff0c18 5107 #define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MACERR_COUNT_SHIFT))&ENET_IEEE_T_MACERR_COUNT_MASK)
mbed_official 146:f64d43ff0c18 5108 /* IEEE_T_CSERR Bit Fields */
mbed_official 146:f64d43ff0c18 5109 #define ENET_IEEE_T_CSERR_COUNT_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5110 #define ENET_IEEE_T_CSERR_COUNT_SHIFT 0
mbed_official 146:f64d43ff0c18 5111 #define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_CSERR_COUNT_SHIFT))&ENET_IEEE_T_CSERR_COUNT_MASK)
mbed_official 146:f64d43ff0c18 5112 /* IEEE_T_FDXFC Bit Fields */
mbed_official 146:f64d43ff0c18 5113 #define ENET_IEEE_T_FDXFC_COUNT_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5114 #define ENET_IEEE_T_FDXFC_COUNT_SHIFT 0
mbed_official 146:f64d43ff0c18 5115 #define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FDXFC_COUNT_SHIFT))&ENET_IEEE_T_FDXFC_COUNT_MASK)
mbed_official 146:f64d43ff0c18 5116 /* IEEE_T_OCTETS_OK Bit Fields */
mbed_official 146:f64d43ff0c18 5117 #define ENET_IEEE_T_OCTETS_OK_COUNT_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 5118 #define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT 0
mbed_official 146:f64d43ff0c18 5119 #define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
mbed_official 146:f64d43ff0c18 5120 /* RMON_R_PACKETS Bit Fields */
mbed_official 146:f64d43ff0c18 5121 #define ENET_RMON_R_PACKETS_COUNT_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5122 #define ENET_RMON_R_PACKETS_COUNT_SHIFT 0
mbed_official 146:f64d43ff0c18 5123 #define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_PACKETS_COUNT_SHIFT))&ENET_RMON_R_PACKETS_COUNT_MASK)
mbed_official 146:f64d43ff0c18 5124 /* RMON_R_BC_PKT Bit Fields */
mbed_official 146:f64d43ff0c18 5125 #define ENET_RMON_R_BC_PKT_COUNT_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5126 #define ENET_RMON_R_BC_PKT_COUNT_SHIFT 0
mbed_official 146:f64d43ff0c18 5127 #define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_BC_PKT_COUNT_SHIFT))&ENET_RMON_R_BC_PKT_COUNT_MASK)
mbed_official 146:f64d43ff0c18 5128 /* RMON_R_MC_PKT Bit Fields */
mbed_official 146:f64d43ff0c18 5129 #define ENET_RMON_R_MC_PKT_COUNT_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5130 #define ENET_RMON_R_MC_PKT_COUNT_SHIFT 0
mbed_official 146:f64d43ff0c18 5131 #define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_MC_PKT_COUNT_SHIFT))&ENET_RMON_R_MC_PKT_COUNT_MASK)
mbed_official 146:f64d43ff0c18 5132 /* RMON_R_CRC_ALIGN Bit Fields */
mbed_official 146:f64d43ff0c18 5133 #define ENET_RMON_R_CRC_ALIGN_COUNT_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5134 #define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT 0
mbed_official 146:f64d43ff0c18 5135 #define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT))&ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
mbed_official 146:f64d43ff0c18 5136 /* RMON_R_UNDERSIZE Bit Fields */
mbed_official 146:f64d43ff0c18 5137 #define ENET_RMON_R_UNDERSIZE_COUNT_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5138 #define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT 0
mbed_official 146:f64d43ff0c18 5139 #define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_UNDERSIZE_COUNT_SHIFT))&ENET_RMON_R_UNDERSIZE_COUNT_MASK)
mbed_official 146:f64d43ff0c18 5140 /* RMON_R_OVERSIZE Bit Fields */
mbed_official 146:f64d43ff0c18 5141 #define ENET_RMON_R_OVERSIZE_COUNT_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5142 #define ENET_RMON_R_OVERSIZE_COUNT_SHIFT 0
mbed_official 146:f64d43ff0c18 5143 #define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OVERSIZE_COUNT_SHIFT))&ENET_RMON_R_OVERSIZE_COUNT_MASK)
mbed_official 146:f64d43ff0c18 5144 /* RMON_R_FRAG Bit Fields */
mbed_official 146:f64d43ff0c18 5145 #define ENET_RMON_R_FRAG_COUNT_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5146 #define ENET_RMON_R_FRAG_COUNT_SHIFT 0
mbed_official 146:f64d43ff0c18 5147 #define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_FRAG_COUNT_SHIFT))&ENET_RMON_R_FRAG_COUNT_MASK)
mbed_official 146:f64d43ff0c18 5148 /* RMON_R_JAB Bit Fields */
mbed_official 146:f64d43ff0c18 5149 #define ENET_RMON_R_JAB_COUNT_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5150 #define ENET_RMON_R_JAB_COUNT_SHIFT 0
mbed_official 146:f64d43ff0c18 5151 #define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_JAB_COUNT_SHIFT))&ENET_RMON_R_JAB_COUNT_MASK)
mbed_official 146:f64d43ff0c18 5152 /* RMON_R_P64 Bit Fields */
mbed_official 146:f64d43ff0c18 5153 #define ENET_RMON_R_P64_COUNT_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5154 #define ENET_RMON_R_P64_COUNT_SHIFT 0
mbed_official 146:f64d43ff0c18 5155 #define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P64_COUNT_SHIFT))&ENET_RMON_R_P64_COUNT_MASK)
mbed_official 146:f64d43ff0c18 5156 /* RMON_R_P65TO127 Bit Fields */
mbed_official 146:f64d43ff0c18 5157 #define ENET_RMON_R_P65TO127_COUNT_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5158 #define ENET_RMON_R_P65TO127_COUNT_SHIFT 0
mbed_official 146:f64d43ff0c18 5159 #define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P65TO127_COUNT_SHIFT))&ENET_RMON_R_P65TO127_COUNT_MASK)
mbed_official 146:f64d43ff0c18 5160 /* RMON_R_P128TO255 Bit Fields */
mbed_official 146:f64d43ff0c18 5161 #define ENET_RMON_R_P128TO255_COUNT_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5162 #define ENET_RMON_R_P128TO255_COUNT_SHIFT 0
mbed_official 146:f64d43ff0c18 5163 #define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P128TO255_COUNT_SHIFT))&ENET_RMON_R_P128TO255_COUNT_MASK)
mbed_official 146:f64d43ff0c18 5164 /* RMON_R_P256TO511 Bit Fields */
mbed_official 146:f64d43ff0c18 5165 #define ENET_RMON_R_P256TO511_COUNT_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5166 #define ENET_RMON_R_P256TO511_COUNT_SHIFT 0
mbed_official 146:f64d43ff0c18 5167 #define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P256TO511_COUNT_SHIFT))&ENET_RMON_R_P256TO511_COUNT_MASK)
mbed_official 146:f64d43ff0c18 5168 /* RMON_R_P512TO1023 Bit Fields */
mbed_official 146:f64d43ff0c18 5169 #define ENET_RMON_R_P512TO1023_COUNT_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5170 #define ENET_RMON_R_P512TO1023_COUNT_SHIFT 0
mbed_official 146:f64d43ff0c18 5171 #define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P512TO1023_COUNT_SHIFT))&ENET_RMON_R_P512TO1023_COUNT_MASK)
mbed_official 146:f64d43ff0c18 5172 /* RMON_R_P1024TO2047 Bit Fields */
mbed_official 146:f64d43ff0c18 5173 #define ENET_RMON_R_P1024TO2047_COUNT_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5174 #define ENET_RMON_R_P1024TO2047_COUNT_SHIFT 0
mbed_official 146:f64d43ff0c18 5175 #define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P1024TO2047_COUNT_SHIFT))&ENET_RMON_R_P1024TO2047_COUNT_MASK)
mbed_official 146:f64d43ff0c18 5176 /* RMON_R_GTE2048 Bit Fields */
mbed_official 146:f64d43ff0c18 5177 #define ENET_RMON_R_GTE2048_COUNT_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5178 #define ENET_RMON_R_GTE2048_COUNT_SHIFT 0
mbed_official 146:f64d43ff0c18 5179 #define ENET_RMON_R_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_GTE2048_COUNT_SHIFT))&ENET_RMON_R_GTE2048_COUNT_MASK)
mbed_official 146:f64d43ff0c18 5180 /* RMON_R_OCTETS Bit Fields */
mbed_official 146:f64d43ff0c18 5181 #define ENET_RMON_R_OCTETS_COUNT_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 5182 #define ENET_RMON_R_OCTETS_COUNT_SHIFT 0
mbed_official 146:f64d43ff0c18 5183 #define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OCTETS_COUNT_SHIFT))&ENET_RMON_R_OCTETS_COUNT_MASK)
mbed_official 146:f64d43ff0c18 5184 /* IEEE_R_DROP Bit Fields */
mbed_official 146:f64d43ff0c18 5185 #define ENET_IEEE_R_DROP_COUNT_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5186 #define ENET_IEEE_R_DROP_COUNT_SHIFT 0
mbed_official 146:f64d43ff0c18 5187 #define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_DROP_COUNT_SHIFT))&ENET_IEEE_R_DROP_COUNT_MASK)
mbed_official 146:f64d43ff0c18 5188 /* IEEE_R_FRAME_OK Bit Fields */
mbed_official 146:f64d43ff0c18 5189 #define ENET_IEEE_R_FRAME_OK_COUNT_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5190 #define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT 0
mbed_official 146:f64d43ff0c18 5191 #define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_R_FRAME_OK_COUNT_MASK)
mbed_official 146:f64d43ff0c18 5192 /* IEEE_R_CRC Bit Fields */
mbed_official 146:f64d43ff0c18 5193 #define ENET_IEEE_R_CRC_COUNT_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5194 #define ENET_IEEE_R_CRC_COUNT_SHIFT 0
mbed_official 146:f64d43ff0c18 5195 #define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_CRC_COUNT_SHIFT))&ENET_IEEE_R_CRC_COUNT_MASK)
mbed_official 146:f64d43ff0c18 5196 /* IEEE_R_ALIGN Bit Fields */
mbed_official 146:f64d43ff0c18 5197 #define ENET_IEEE_R_ALIGN_COUNT_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5198 #define ENET_IEEE_R_ALIGN_COUNT_SHIFT 0
mbed_official 146:f64d43ff0c18 5199 #define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_ALIGN_COUNT_SHIFT))&ENET_IEEE_R_ALIGN_COUNT_MASK)
mbed_official 146:f64d43ff0c18 5200 /* IEEE_R_MACERR Bit Fields */
mbed_official 146:f64d43ff0c18 5201 #define ENET_IEEE_R_MACERR_COUNT_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5202 #define ENET_IEEE_R_MACERR_COUNT_SHIFT 0
mbed_official 146:f64d43ff0c18 5203 #define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_MACERR_COUNT_SHIFT))&ENET_IEEE_R_MACERR_COUNT_MASK)
mbed_official 146:f64d43ff0c18 5204 /* IEEE_R_FDXFC Bit Fields */
mbed_official 146:f64d43ff0c18 5205 #define ENET_IEEE_R_FDXFC_COUNT_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 5206 #define ENET_IEEE_R_FDXFC_COUNT_SHIFT 0
mbed_official 146:f64d43ff0c18 5207 #define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FDXFC_COUNT_SHIFT))&ENET_IEEE_R_FDXFC_COUNT_MASK)
mbed_official 146:f64d43ff0c18 5208 /* IEEE_R_OCTETS_OK Bit Fields */
mbed_official 146:f64d43ff0c18 5209 #define ENET_IEEE_R_OCTETS_OK_COUNT_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 5210 #define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT 0
mbed_official 146:f64d43ff0c18 5211 #define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
mbed_official 146:f64d43ff0c18 5212 /* ATCR Bit Fields */
mbed_official 146:f64d43ff0c18 5213 #define ENET_ATCR_EN_MASK 0x1u
mbed_official 146:f64d43ff0c18 5214 #define ENET_ATCR_EN_SHIFT 0
mbed_official 146:f64d43ff0c18 5215 #define ENET_ATCR_OFFEN_MASK 0x4u
mbed_official 146:f64d43ff0c18 5216 #define ENET_ATCR_OFFEN_SHIFT 2
mbed_official 146:f64d43ff0c18 5217 #define ENET_ATCR_OFFRST_MASK 0x8u
mbed_official 146:f64d43ff0c18 5218 #define ENET_ATCR_OFFRST_SHIFT 3
mbed_official 146:f64d43ff0c18 5219 #define ENET_ATCR_PEREN_MASK 0x10u
mbed_official 146:f64d43ff0c18 5220 #define ENET_ATCR_PEREN_SHIFT 4
mbed_official 146:f64d43ff0c18 5221 #define ENET_ATCR_PINPER_MASK 0x80u
mbed_official 146:f64d43ff0c18 5222 #define ENET_ATCR_PINPER_SHIFT 7
mbed_official 146:f64d43ff0c18 5223 #define ENET_ATCR_RESTART_MASK 0x200u
mbed_official 146:f64d43ff0c18 5224 #define ENET_ATCR_RESTART_SHIFT 9
mbed_official 146:f64d43ff0c18 5225 #define ENET_ATCR_CAPTURE_MASK 0x800u
mbed_official 146:f64d43ff0c18 5226 #define ENET_ATCR_CAPTURE_SHIFT 11
mbed_official 146:f64d43ff0c18 5227 #define ENET_ATCR_SLAVE_MASK 0x2000u
mbed_official 146:f64d43ff0c18 5228 #define ENET_ATCR_SLAVE_SHIFT 13
mbed_official 146:f64d43ff0c18 5229 /* ATVR Bit Fields */
mbed_official 146:f64d43ff0c18 5230 #define ENET_ATVR_ATIME_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 5231 #define ENET_ATVR_ATIME_SHIFT 0
mbed_official 146:f64d43ff0c18 5232 #define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATVR_ATIME_SHIFT))&ENET_ATVR_ATIME_MASK)
mbed_official 146:f64d43ff0c18 5233 /* ATOFF Bit Fields */
mbed_official 146:f64d43ff0c18 5234 #define ENET_ATOFF_OFFSET_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 5235 #define ENET_ATOFF_OFFSET_SHIFT 0
mbed_official 146:f64d43ff0c18 5236 #define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATOFF_OFFSET_SHIFT))&ENET_ATOFF_OFFSET_MASK)
mbed_official 146:f64d43ff0c18 5237 /* ATPER Bit Fields */
mbed_official 146:f64d43ff0c18 5238 #define ENET_ATPER_PERIOD_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 5239 #define ENET_ATPER_PERIOD_SHIFT 0
mbed_official 146:f64d43ff0c18 5240 #define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATPER_PERIOD_SHIFT))&ENET_ATPER_PERIOD_MASK)
mbed_official 146:f64d43ff0c18 5241 /* ATCOR Bit Fields */
mbed_official 146:f64d43ff0c18 5242 #define ENET_ATCOR_COR_MASK 0x7FFFFFFFu
mbed_official 146:f64d43ff0c18 5243 #define ENET_ATCOR_COR_SHIFT 0
mbed_official 146:f64d43ff0c18 5244 #define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATCOR_COR_SHIFT))&ENET_ATCOR_COR_MASK)
mbed_official 146:f64d43ff0c18 5245 /* ATINC Bit Fields */
mbed_official 146:f64d43ff0c18 5246 #define ENET_ATINC_INC_MASK 0x7Fu
mbed_official 146:f64d43ff0c18 5247 #define ENET_ATINC_INC_SHIFT 0
mbed_official 146:f64d43ff0c18 5248 #define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_SHIFT))&ENET_ATINC_INC_MASK)
mbed_official 146:f64d43ff0c18 5249 #define ENET_ATINC_INC_CORR_MASK 0x7F00u
mbed_official 146:f64d43ff0c18 5250 #define ENET_ATINC_INC_CORR_SHIFT 8
mbed_official 146:f64d43ff0c18 5251 #define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_CORR_SHIFT))&ENET_ATINC_INC_CORR_MASK)
mbed_official 146:f64d43ff0c18 5252 /* ATSTMP Bit Fields */
mbed_official 146:f64d43ff0c18 5253 #define ENET_ATSTMP_TIMESTAMP_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 5254 #define ENET_ATSTMP_TIMESTAMP_SHIFT 0
mbed_official 146:f64d43ff0c18 5255 #define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATSTMP_TIMESTAMP_SHIFT))&ENET_ATSTMP_TIMESTAMP_MASK)
mbed_official 146:f64d43ff0c18 5256 /* TGSR Bit Fields */
mbed_official 146:f64d43ff0c18 5257 #define ENET_TGSR_TF0_MASK 0x1u
mbed_official 146:f64d43ff0c18 5258 #define ENET_TGSR_TF0_SHIFT 0
mbed_official 146:f64d43ff0c18 5259 #define ENET_TGSR_TF1_MASK 0x2u
mbed_official 146:f64d43ff0c18 5260 #define ENET_TGSR_TF1_SHIFT 1
mbed_official 146:f64d43ff0c18 5261 #define ENET_TGSR_TF2_MASK 0x4u
mbed_official 146:f64d43ff0c18 5262 #define ENET_TGSR_TF2_SHIFT 2
mbed_official 146:f64d43ff0c18 5263 #define ENET_TGSR_TF3_MASK 0x8u
mbed_official 146:f64d43ff0c18 5264 #define ENET_TGSR_TF3_SHIFT 3
mbed_official 146:f64d43ff0c18 5265 /* TCSR Bit Fields */
mbed_official 146:f64d43ff0c18 5266 #define ENET_TCSR_TDRE_MASK 0x1u
mbed_official 146:f64d43ff0c18 5267 #define ENET_TCSR_TDRE_SHIFT 0
mbed_official 146:f64d43ff0c18 5268 #define ENET_TCSR_TMODE_MASK 0x3Cu
mbed_official 146:f64d43ff0c18 5269 #define ENET_TCSR_TMODE_SHIFT 2
mbed_official 146:f64d43ff0c18 5270 #define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TMODE_SHIFT))&ENET_TCSR_TMODE_MASK)
mbed_official 146:f64d43ff0c18 5271 #define ENET_TCSR_TIE_MASK 0x40u
mbed_official 146:f64d43ff0c18 5272 #define ENET_TCSR_TIE_SHIFT 6
mbed_official 146:f64d43ff0c18 5273 #define ENET_TCSR_TF_MASK 0x80u
mbed_official 146:f64d43ff0c18 5274 #define ENET_TCSR_TF_SHIFT 7
mbed_official 146:f64d43ff0c18 5275 /* TCCR Bit Fields */
mbed_official 146:f64d43ff0c18 5276 #define ENET_TCCR_TCC_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 5277 #define ENET_TCCR_TCC_SHIFT 0
mbed_official 146:f64d43ff0c18 5278 #define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCCR_TCC_SHIFT))&ENET_TCCR_TCC_MASK)
mbed_official 146:f64d43ff0c18 5279
mbed_official 146:f64d43ff0c18 5280 /*!
mbed_official 146:f64d43ff0c18 5281 * @}
mbed_official 146:f64d43ff0c18 5282 */ /* end of group ENET_Register_Masks */
mbed_official 146:f64d43ff0c18 5283
mbed_official 146:f64d43ff0c18 5284
mbed_official 146:f64d43ff0c18 5285 /* ENET - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 5286 /** Peripheral ENET base address */
mbed_official 146:f64d43ff0c18 5287 #define ENET_BASE (0x400C0000u)
mbed_official 146:f64d43ff0c18 5288 /** Peripheral ENET base pointer */
mbed_official 146:f64d43ff0c18 5289 #define ENET ((ENET_Type *)ENET_BASE)
mbed_official 146:f64d43ff0c18 5290 #define ENET_BASE_PTR (ENET)
mbed_official 146:f64d43ff0c18 5291 /** Array initializer of ENET peripheral base pointers */
mbed_official 146:f64d43ff0c18 5292 #define ENET_BASES { ENET }
mbed_official 146:f64d43ff0c18 5293
mbed_official 146:f64d43ff0c18 5294 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5295 -- ENET - Register accessor macros
mbed_official 146:f64d43ff0c18 5296 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 5297
mbed_official 146:f64d43ff0c18 5298 /*!
mbed_official 146:f64d43ff0c18 5299 * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
mbed_official 146:f64d43ff0c18 5300 * @{
mbed_official 146:f64d43ff0c18 5301 */
mbed_official 146:f64d43ff0c18 5302
mbed_official 146:f64d43ff0c18 5303
mbed_official 146:f64d43ff0c18 5304 /* ENET - Register instance definitions */
mbed_official 146:f64d43ff0c18 5305 /* ENET */
mbed_official 146:f64d43ff0c18 5306 #define ENET_EIR ENET_EIR_REG(ENET)
mbed_official 146:f64d43ff0c18 5307 #define ENET_EIMR ENET_EIMR_REG(ENET)
mbed_official 146:f64d43ff0c18 5308 #define ENET_RDAR ENET_RDAR_REG(ENET)
mbed_official 146:f64d43ff0c18 5309 #define ENET_TDAR ENET_TDAR_REG(ENET)
mbed_official 146:f64d43ff0c18 5310 #define ENET_ECR ENET_ECR_REG(ENET)
mbed_official 146:f64d43ff0c18 5311 #define ENET_MMFR ENET_MMFR_REG(ENET)
mbed_official 146:f64d43ff0c18 5312 #define ENET_MSCR ENET_MSCR_REG(ENET)
mbed_official 146:f64d43ff0c18 5313 #define ENET_MIBC ENET_MIBC_REG(ENET)
mbed_official 146:f64d43ff0c18 5314 #define ENET_RCR ENET_RCR_REG(ENET)
mbed_official 146:f64d43ff0c18 5315 #define ENET_TCR ENET_TCR_REG(ENET)
mbed_official 146:f64d43ff0c18 5316 #define ENET_PALR ENET_PALR_REG(ENET)
mbed_official 146:f64d43ff0c18 5317 #define ENET_PAUR ENET_PAUR_REG(ENET)
mbed_official 146:f64d43ff0c18 5318 #define ENET_OPD ENET_OPD_REG(ENET)
mbed_official 146:f64d43ff0c18 5319 #define ENET_IAUR ENET_IAUR_REG(ENET)
mbed_official 146:f64d43ff0c18 5320 #define ENET_IALR ENET_IALR_REG(ENET)
mbed_official 146:f64d43ff0c18 5321 #define ENET_GAUR ENET_GAUR_REG(ENET)
mbed_official 146:f64d43ff0c18 5322 #define ENET_GALR ENET_GALR_REG(ENET)
mbed_official 146:f64d43ff0c18 5323 #define ENET_TFWR ENET_TFWR_REG(ENET)
mbed_official 146:f64d43ff0c18 5324 #define ENET_RDSR ENET_RDSR_REG(ENET)
mbed_official 146:f64d43ff0c18 5325 #define ENET_TDSR ENET_TDSR_REG(ENET)
mbed_official 146:f64d43ff0c18 5326 #define ENET_MRBR ENET_MRBR_REG(ENET)
mbed_official 146:f64d43ff0c18 5327 #define ENET_RSFL ENET_RSFL_REG(ENET)
mbed_official 146:f64d43ff0c18 5328 #define ENET_RSEM ENET_RSEM_REG(ENET)
mbed_official 146:f64d43ff0c18 5329 #define ENET_RAEM ENET_RAEM_REG(ENET)
mbed_official 146:f64d43ff0c18 5330 #define ENET_RAFL ENET_RAFL_REG(ENET)
mbed_official 146:f64d43ff0c18 5331 #define ENET_TSEM ENET_TSEM_REG(ENET)
mbed_official 146:f64d43ff0c18 5332 #define ENET_TAEM ENET_TAEM_REG(ENET)
mbed_official 146:f64d43ff0c18 5333 #define ENET_TAFL ENET_TAFL_REG(ENET)
mbed_official 146:f64d43ff0c18 5334 #define ENET_TIPG ENET_TIPG_REG(ENET)
mbed_official 146:f64d43ff0c18 5335 #define ENET_FTRL ENET_FTRL_REG(ENET)
mbed_official 146:f64d43ff0c18 5336 #define ENET_TACC ENET_TACC_REG(ENET)
mbed_official 146:f64d43ff0c18 5337 #define ENET_RACC ENET_RACC_REG(ENET)
mbed_official 146:f64d43ff0c18 5338 #define ENET_RMON_T_PACKETS ENET_RMON_T_PACKETS_REG(ENET)
mbed_official 146:f64d43ff0c18 5339 #define ENET_RMON_T_BC_PKT ENET_RMON_T_BC_PKT_REG(ENET)
mbed_official 146:f64d43ff0c18 5340 #define ENET_RMON_T_MC_PKT ENET_RMON_T_MC_PKT_REG(ENET)
mbed_official 146:f64d43ff0c18 5341 #define ENET_RMON_T_CRC_ALIGN ENET_RMON_T_CRC_ALIGN_REG(ENET)
mbed_official 146:f64d43ff0c18 5342 #define ENET_RMON_T_UNDERSIZE ENET_RMON_T_UNDERSIZE_REG(ENET)
mbed_official 146:f64d43ff0c18 5343 #define ENET_RMON_T_OVERSIZE ENET_RMON_T_OVERSIZE_REG(ENET)
mbed_official 146:f64d43ff0c18 5344 #define ENET_RMON_T_FRAG ENET_RMON_T_FRAG_REG(ENET)
mbed_official 146:f64d43ff0c18 5345 #define ENET_RMON_T_JAB ENET_RMON_T_JAB_REG(ENET)
mbed_official 146:f64d43ff0c18 5346 #define ENET_RMON_T_COL ENET_RMON_T_COL_REG(ENET)
mbed_official 146:f64d43ff0c18 5347 #define ENET_RMON_T_P64 ENET_RMON_T_P64_REG(ENET)
mbed_official 146:f64d43ff0c18 5348 #define ENET_RMON_T_P65TO127 ENET_RMON_T_P65TO127_REG(ENET)
mbed_official 146:f64d43ff0c18 5349 #define ENET_RMON_T_P128TO255 ENET_RMON_T_P128TO255_REG(ENET)
mbed_official 146:f64d43ff0c18 5350 #define ENET_RMON_T_P256TO511 ENET_RMON_T_P256TO511_REG(ENET)
mbed_official 146:f64d43ff0c18 5351 #define ENET_RMON_T_P512TO1023 ENET_RMON_T_P512TO1023_REG(ENET)
mbed_official 146:f64d43ff0c18 5352 #define ENET_RMON_T_P1024TO2047 ENET_RMON_T_P1024TO2047_REG(ENET)
mbed_official 146:f64d43ff0c18 5353 #define ENET_RMON_T_P_GTE2048 ENET_RMON_T_P_GTE2048_REG(ENET)
mbed_official 146:f64d43ff0c18 5354 #define ENET_RMON_T_OCTETS ENET_RMON_T_OCTETS_REG(ENET)
mbed_official 146:f64d43ff0c18 5355 #define ENET_IEEE_T_FRAME_OK ENET_IEEE_T_FRAME_OK_REG(ENET)
mbed_official 146:f64d43ff0c18 5356 #define ENET_IEEE_T_1COL ENET_IEEE_T_1COL_REG(ENET)
mbed_official 146:f64d43ff0c18 5357 #define ENET_IEEE_T_MCOL ENET_IEEE_T_MCOL_REG(ENET)
mbed_official 146:f64d43ff0c18 5358 #define ENET_IEEE_T_DEF ENET_IEEE_T_DEF_REG(ENET)
mbed_official 146:f64d43ff0c18 5359 #define ENET_IEEE_T_LCOL ENET_IEEE_T_LCOL_REG(ENET)
mbed_official 146:f64d43ff0c18 5360 #define ENET_IEEE_T_EXCOL ENET_IEEE_T_EXCOL_REG(ENET)
mbed_official 146:f64d43ff0c18 5361 #define ENET_IEEE_T_MACERR ENET_IEEE_T_MACERR_REG(ENET)
mbed_official 146:f64d43ff0c18 5362 #define ENET_IEEE_T_CSERR ENET_IEEE_T_CSERR_REG(ENET)
mbed_official 146:f64d43ff0c18 5363 #define ENET_IEEE_T_FDXFC ENET_IEEE_T_FDXFC_REG(ENET)
mbed_official 146:f64d43ff0c18 5364 #define ENET_IEEE_T_OCTETS_OK ENET_IEEE_T_OCTETS_OK_REG(ENET)
mbed_official 146:f64d43ff0c18 5365 #define ENET_RMON_R_PACKETS ENET_RMON_R_PACKETS_REG(ENET)
mbed_official 146:f64d43ff0c18 5366 #define ENET_RMON_R_BC_PKT ENET_RMON_R_BC_PKT_REG(ENET)
mbed_official 146:f64d43ff0c18 5367 #define ENET_RMON_R_MC_PKT ENET_RMON_R_MC_PKT_REG(ENET)
mbed_official 146:f64d43ff0c18 5368 #define ENET_RMON_R_CRC_ALIGN ENET_RMON_R_CRC_ALIGN_REG(ENET)
mbed_official 146:f64d43ff0c18 5369 #define ENET_RMON_R_UNDERSIZE ENET_RMON_R_UNDERSIZE_REG(ENET)
mbed_official 146:f64d43ff0c18 5370 #define ENET_RMON_R_OVERSIZE ENET_RMON_R_OVERSIZE_REG(ENET)
mbed_official 146:f64d43ff0c18 5371 #define ENET_RMON_R_FRAG ENET_RMON_R_FRAG_REG(ENET)
mbed_official 146:f64d43ff0c18 5372 #define ENET_RMON_R_JAB ENET_RMON_R_JAB_REG(ENET)
mbed_official 146:f64d43ff0c18 5373 #define ENET_RMON_R_P64 ENET_RMON_R_P64_REG(ENET)
mbed_official 146:f64d43ff0c18 5374 #define ENET_RMON_R_P65TO127 ENET_RMON_R_P65TO127_REG(ENET)
mbed_official 146:f64d43ff0c18 5375 #define ENET_RMON_R_P128TO255 ENET_RMON_R_P128TO255_REG(ENET)
mbed_official 146:f64d43ff0c18 5376 #define ENET_RMON_R_P256TO511 ENET_RMON_R_P256TO511_REG(ENET)
mbed_official 146:f64d43ff0c18 5377 #define ENET_RMON_R_P512TO1023 ENET_RMON_R_P512TO1023_REG(ENET)
mbed_official 146:f64d43ff0c18 5378 #define ENET_RMON_R_P1024TO2047 ENET_RMON_R_P1024TO2047_REG(ENET)
mbed_official 146:f64d43ff0c18 5379 #define ENET_RMON_R_GTE2048 ENET_RMON_R_GTE2048_REG(ENET)
mbed_official 146:f64d43ff0c18 5380 #define ENET_RMON_R_OCTETS ENET_RMON_R_OCTETS_REG(ENET)
mbed_official 146:f64d43ff0c18 5381 #define ENET_IEEE_R_DROP ENET_IEEE_R_DROP_REG(ENET)
mbed_official 146:f64d43ff0c18 5382 #define ENET_IEEE_R_FRAME_OK ENET_IEEE_R_FRAME_OK_REG(ENET)
mbed_official 146:f64d43ff0c18 5383 #define ENET_IEEE_R_CRC ENET_IEEE_R_CRC_REG(ENET)
mbed_official 146:f64d43ff0c18 5384 #define ENET_IEEE_R_ALIGN ENET_IEEE_R_ALIGN_REG(ENET)
mbed_official 146:f64d43ff0c18 5385 #define ENET_IEEE_R_MACERR ENET_IEEE_R_MACERR_REG(ENET)
mbed_official 146:f64d43ff0c18 5386 #define ENET_IEEE_R_FDXFC ENET_IEEE_R_FDXFC_REG(ENET)
mbed_official 146:f64d43ff0c18 5387 #define ENET_IEEE_R_OCTETS_OK ENET_IEEE_R_OCTETS_OK_REG(ENET)
mbed_official 146:f64d43ff0c18 5388 #define ENET_ATCR ENET_ATCR_REG(ENET)
mbed_official 146:f64d43ff0c18 5389 #define ENET_ATVR ENET_ATVR_REG(ENET)
mbed_official 146:f64d43ff0c18 5390 #define ENET_ATOFF ENET_ATOFF_REG(ENET)
mbed_official 146:f64d43ff0c18 5391 #define ENET_ATPER ENET_ATPER_REG(ENET)
mbed_official 146:f64d43ff0c18 5392 #define ENET_ATCOR ENET_ATCOR_REG(ENET)
mbed_official 146:f64d43ff0c18 5393 #define ENET_ATINC ENET_ATINC_REG(ENET)
mbed_official 146:f64d43ff0c18 5394 #define ENET_ATSTMP ENET_ATSTMP_REG(ENET)
mbed_official 146:f64d43ff0c18 5395 #define ENET_TGSR ENET_TGSR_REG(ENET)
mbed_official 146:f64d43ff0c18 5396 #define ENET_TCSR0 ENET_TCSR_REG(ENET,0)
mbed_official 146:f64d43ff0c18 5397 #define ENET_TCCR0 ENET_TCCR_REG(ENET,0)
mbed_official 146:f64d43ff0c18 5398 #define ENET_TCSR1 ENET_TCSR_REG(ENET,1)
mbed_official 146:f64d43ff0c18 5399 #define ENET_TCCR1 ENET_TCCR_REG(ENET,1)
mbed_official 146:f64d43ff0c18 5400 #define ENET_TCSR2 ENET_TCSR_REG(ENET,2)
mbed_official 146:f64d43ff0c18 5401 #define ENET_TCCR2 ENET_TCCR_REG(ENET,2)
mbed_official 146:f64d43ff0c18 5402 #define ENET_TCSR3 ENET_TCSR_REG(ENET,3)
mbed_official 146:f64d43ff0c18 5403 #define ENET_TCCR3 ENET_TCCR_REG(ENET,3)
mbed_official 146:f64d43ff0c18 5404
mbed_official 146:f64d43ff0c18 5405 /* ENET - Register array accessors */
mbed_official 146:f64d43ff0c18 5406 #define ENET_TCSR(index) ENET_TCSR_REG(ENET,index)
mbed_official 146:f64d43ff0c18 5407 #define ENET_TCCR(index) ENET_TCCR_REG(ENET,index)
mbed_official 146:f64d43ff0c18 5408
mbed_official 146:f64d43ff0c18 5409 /*!
mbed_official 146:f64d43ff0c18 5410 * @}
mbed_official 146:f64d43ff0c18 5411 */ /* end of group ENET_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 5412
mbed_official 146:f64d43ff0c18 5413
mbed_official 146:f64d43ff0c18 5414 /*!
mbed_official 146:f64d43ff0c18 5415 * @}
mbed_official 146:f64d43ff0c18 5416 */ /* end of group ENET_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 5417
mbed_official 146:f64d43ff0c18 5418
mbed_official 146:f64d43ff0c18 5419 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5420 -- EWM Peripheral Access Layer
mbed_official 146:f64d43ff0c18 5421 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 5422
mbed_official 146:f64d43ff0c18 5423 /*!
mbed_official 146:f64d43ff0c18 5424 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
mbed_official 146:f64d43ff0c18 5425 * @{
mbed_official 146:f64d43ff0c18 5426 */
mbed_official 146:f64d43ff0c18 5427
mbed_official 146:f64d43ff0c18 5428 /** EWM - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 5429 typedef struct {
mbed_official 146:f64d43ff0c18 5430 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
mbed_official 146:f64d43ff0c18 5431 __O uint8_t SERV; /**< Service Register, offset: 0x1 */
mbed_official 146:f64d43ff0c18 5432 __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
mbed_official 146:f64d43ff0c18 5433 __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
mbed_official 146:f64d43ff0c18 5434 } EWM_Type, *EWM_MemMapPtr;
mbed_official 146:f64d43ff0c18 5435
mbed_official 146:f64d43ff0c18 5436 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5437 -- EWM - Register accessor macros
mbed_official 146:f64d43ff0c18 5438 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 5439
mbed_official 146:f64d43ff0c18 5440 /*!
mbed_official 146:f64d43ff0c18 5441 * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
mbed_official 146:f64d43ff0c18 5442 * @{
mbed_official 146:f64d43ff0c18 5443 */
mbed_official 146:f64d43ff0c18 5444
mbed_official 146:f64d43ff0c18 5445
mbed_official 146:f64d43ff0c18 5446 /* EWM - Register accessors */
mbed_official 146:f64d43ff0c18 5447 #define EWM_CTRL_REG(base) ((base)->CTRL)
mbed_official 146:f64d43ff0c18 5448 #define EWM_SERV_REG(base) ((base)->SERV)
mbed_official 146:f64d43ff0c18 5449 #define EWM_CMPL_REG(base) ((base)->CMPL)
mbed_official 146:f64d43ff0c18 5450 #define EWM_CMPH_REG(base) ((base)->CMPH)
mbed_official 146:f64d43ff0c18 5451
mbed_official 146:f64d43ff0c18 5452 /*!
mbed_official 146:f64d43ff0c18 5453 * @}
mbed_official 146:f64d43ff0c18 5454 */ /* end of group EWM_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 5455
mbed_official 146:f64d43ff0c18 5456
mbed_official 146:f64d43ff0c18 5457 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5458 -- EWM Register Masks
mbed_official 146:f64d43ff0c18 5459 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 5460
mbed_official 146:f64d43ff0c18 5461 /*!
mbed_official 146:f64d43ff0c18 5462 * @addtogroup EWM_Register_Masks EWM Register Masks
mbed_official 146:f64d43ff0c18 5463 * @{
mbed_official 146:f64d43ff0c18 5464 */
mbed_official 146:f64d43ff0c18 5465
mbed_official 146:f64d43ff0c18 5466 /* CTRL Bit Fields */
mbed_official 146:f64d43ff0c18 5467 #define EWM_CTRL_EWMEN_MASK 0x1u
mbed_official 146:f64d43ff0c18 5468 #define EWM_CTRL_EWMEN_SHIFT 0
mbed_official 146:f64d43ff0c18 5469 #define EWM_CTRL_ASSIN_MASK 0x2u
mbed_official 146:f64d43ff0c18 5470 #define EWM_CTRL_ASSIN_SHIFT 1
mbed_official 146:f64d43ff0c18 5471 #define EWM_CTRL_INEN_MASK 0x4u
mbed_official 146:f64d43ff0c18 5472 #define EWM_CTRL_INEN_SHIFT 2
mbed_official 146:f64d43ff0c18 5473 #define EWM_CTRL_INTEN_MASK 0x8u
mbed_official 146:f64d43ff0c18 5474 #define EWM_CTRL_INTEN_SHIFT 3
mbed_official 146:f64d43ff0c18 5475 /* SERV Bit Fields */
mbed_official 146:f64d43ff0c18 5476 #define EWM_SERV_SERVICE_MASK 0xFFu
mbed_official 146:f64d43ff0c18 5477 #define EWM_SERV_SERVICE_SHIFT 0
mbed_official 146:f64d43ff0c18 5478 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
mbed_official 146:f64d43ff0c18 5479 /* CMPL Bit Fields */
mbed_official 146:f64d43ff0c18 5480 #define EWM_CMPL_COMPAREL_MASK 0xFFu
mbed_official 146:f64d43ff0c18 5481 #define EWM_CMPL_COMPAREL_SHIFT 0
mbed_official 146:f64d43ff0c18 5482 #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
mbed_official 146:f64d43ff0c18 5483 /* CMPH Bit Fields */
mbed_official 146:f64d43ff0c18 5484 #define EWM_CMPH_COMPAREH_MASK 0xFFu
mbed_official 146:f64d43ff0c18 5485 #define EWM_CMPH_COMPAREH_SHIFT 0
mbed_official 146:f64d43ff0c18 5486 #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
mbed_official 146:f64d43ff0c18 5487
mbed_official 146:f64d43ff0c18 5488 /*!
mbed_official 146:f64d43ff0c18 5489 * @}
mbed_official 146:f64d43ff0c18 5490 */ /* end of group EWM_Register_Masks */
mbed_official 146:f64d43ff0c18 5491
mbed_official 146:f64d43ff0c18 5492
mbed_official 146:f64d43ff0c18 5493 /* EWM - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 5494 /** Peripheral EWM base address */
mbed_official 146:f64d43ff0c18 5495 #define EWM_BASE (0x40061000u)
mbed_official 146:f64d43ff0c18 5496 /** Peripheral EWM base pointer */
mbed_official 146:f64d43ff0c18 5497 #define EWM ((EWM_Type *)EWM_BASE)
mbed_official 146:f64d43ff0c18 5498 #define EWM_BASE_PTR (EWM)
mbed_official 146:f64d43ff0c18 5499 /** Array initializer of EWM peripheral base pointers */
mbed_official 146:f64d43ff0c18 5500 #define EWM_BASES { EWM }
mbed_official 146:f64d43ff0c18 5501
mbed_official 146:f64d43ff0c18 5502 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5503 -- EWM - Register accessor macros
mbed_official 146:f64d43ff0c18 5504 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 5505
mbed_official 146:f64d43ff0c18 5506 /*!
mbed_official 146:f64d43ff0c18 5507 * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
mbed_official 146:f64d43ff0c18 5508 * @{
mbed_official 146:f64d43ff0c18 5509 */
mbed_official 146:f64d43ff0c18 5510
mbed_official 146:f64d43ff0c18 5511
mbed_official 146:f64d43ff0c18 5512 /* EWM - Register instance definitions */
mbed_official 146:f64d43ff0c18 5513 /* EWM */
mbed_official 146:f64d43ff0c18 5514 #define EWM_CTRL EWM_CTRL_REG(EWM)
mbed_official 146:f64d43ff0c18 5515 #define EWM_SERV EWM_SERV_REG(EWM)
mbed_official 146:f64d43ff0c18 5516 #define EWM_CMPL EWM_CMPL_REG(EWM)
mbed_official 146:f64d43ff0c18 5517 #define EWM_CMPH EWM_CMPH_REG(EWM)
mbed_official 146:f64d43ff0c18 5518
mbed_official 146:f64d43ff0c18 5519 /*!
mbed_official 146:f64d43ff0c18 5520 * @}
mbed_official 146:f64d43ff0c18 5521 */ /* end of group EWM_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 5522
mbed_official 146:f64d43ff0c18 5523
mbed_official 146:f64d43ff0c18 5524 /*!
mbed_official 146:f64d43ff0c18 5525 * @}
mbed_official 146:f64d43ff0c18 5526 */ /* end of group EWM_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 5527
mbed_official 146:f64d43ff0c18 5528
mbed_official 146:f64d43ff0c18 5529 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5530 -- FB Peripheral Access Layer
mbed_official 146:f64d43ff0c18 5531 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 5532
mbed_official 146:f64d43ff0c18 5533 /*!
mbed_official 146:f64d43ff0c18 5534 * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
mbed_official 146:f64d43ff0c18 5535 * @{
mbed_official 146:f64d43ff0c18 5536 */
mbed_official 146:f64d43ff0c18 5537
mbed_official 146:f64d43ff0c18 5538 /** FB - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 5539 typedef struct {
mbed_official 146:f64d43ff0c18 5540 struct { /* offset: 0x0, array step: 0xC */
mbed_official 146:f64d43ff0c18 5541 __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
mbed_official 146:f64d43ff0c18 5542 __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
mbed_official 146:f64d43ff0c18 5543 __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
mbed_official 146:f64d43ff0c18 5544 } CS[6];
mbed_official 146:f64d43ff0c18 5545 uint8_t RESERVED_0[24];
mbed_official 146:f64d43ff0c18 5546 __IO uint32_t CSPMCR; /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
mbed_official 146:f64d43ff0c18 5547 } FB_Type, *FB_MemMapPtr;
mbed_official 146:f64d43ff0c18 5548
mbed_official 146:f64d43ff0c18 5549 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5550 -- FB - Register accessor macros
mbed_official 146:f64d43ff0c18 5551 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 5552
mbed_official 146:f64d43ff0c18 5553 /*!
mbed_official 146:f64d43ff0c18 5554 * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
mbed_official 146:f64d43ff0c18 5555 * @{
mbed_official 146:f64d43ff0c18 5556 */
mbed_official 146:f64d43ff0c18 5557
mbed_official 146:f64d43ff0c18 5558
mbed_official 146:f64d43ff0c18 5559 /* FB - Register accessors */
mbed_official 146:f64d43ff0c18 5560 #define FB_CSAR_REG(base,index) ((base)->CS[index].CSAR)
mbed_official 146:f64d43ff0c18 5561 #define FB_CSMR_REG(base,index) ((base)->CS[index].CSMR)
mbed_official 146:f64d43ff0c18 5562 #define FB_CSCR_REG(base,index) ((base)->CS[index].CSCR)
mbed_official 146:f64d43ff0c18 5563 #define FB_CSPMCR_REG(base) ((base)->CSPMCR)
mbed_official 146:f64d43ff0c18 5564
mbed_official 146:f64d43ff0c18 5565 /*!
mbed_official 146:f64d43ff0c18 5566 * @}
mbed_official 146:f64d43ff0c18 5567 */ /* end of group FB_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 5568
mbed_official 146:f64d43ff0c18 5569
mbed_official 146:f64d43ff0c18 5570 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5571 -- FB Register Masks
mbed_official 146:f64d43ff0c18 5572 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 5573
mbed_official 146:f64d43ff0c18 5574 /*!
mbed_official 146:f64d43ff0c18 5575 * @addtogroup FB_Register_Masks FB Register Masks
mbed_official 146:f64d43ff0c18 5576 * @{
mbed_official 146:f64d43ff0c18 5577 */
mbed_official 146:f64d43ff0c18 5578
mbed_official 146:f64d43ff0c18 5579 /* CSAR Bit Fields */
mbed_official 146:f64d43ff0c18 5580 #define FB_CSAR_BA_MASK 0xFFFF0000u
mbed_official 146:f64d43ff0c18 5581 #define FB_CSAR_BA_SHIFT 16
mbed_official 146:f64d43ff0c18 5582 #define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x))<<FB_CSAR_BA_SHIFT))&FB_CSAR_BA_MASK)
mbed_official 146:f64d43ff0c18 5583 /* CSMR Bit Fields */
mbed_official 146:f64d43ff0c18 5584 #define FB_CSMR_V_MASK 0x1u
mbed_official 146:f64d43ff0c18 5585 #define FB_CSMR_V_SHIFT 0
mbed_official 146:f64d43ff0c18 5586 #define FB_CSMR_WP_MASK 0x100u
mbed_official 146:f64d43ff0c18 5587 #define FB_CSMR_WP_SHIFT 8
mbed_official 146:f64d43ff0c18 5588 #define FB_CSMR_BAM_MASK 0xFFFF0000u
mbed_official 146:f64d43ff0c18 5589 #define FB_CSMR_BAM_SHIFT 16
mbed_official 146:f64d43ff0c18 5590 #define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x))<<FB_CSMR_BAM_SHIFT))&FB_CSMR_BAM_MASK)
mbed_official 146:f64d43ff0c18 5591 /* CSCR Bit Fields */
mbed_official 146:f64d43ff0c18 5592 #define FB_CSCR_BSTW_MASK 0x8u
mbed_official 146:f64d43ff0c18 5593 #define FB_CSCR_BSTW_SHIFT 3
mbed_official 146:f64d43ff0c18 5594 #define FB_CSCR_BSTR_MASK 0x10u
mbed_official 146:f64d43ff0c18 5595 #define FB_CSCR_BSTR_SHIFT 4
mbed_official 146:f64d43ff0c18 5596 #define FB_CSCR_BEM_MASK 0x20u
mbed_official 146:f64d43ff0c18 5597 #define FB_CSCR_BEM_SHIFT 5
mbed_official 146:f64d43ff0c18 5598 #define FB_CSCR_PS_MASK 0xC0u
mbed_official 146:f64d43ff0c18 5599 #define FB_CSCR_PS_SHIFT 6
mbed_official 146:f64d43ff0c18 5600 #define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_PS_SHIFT))&FB_CSCR_PS_MASK)
mbed_official 146:f64d43ff0c18 5601 #define FB_CSCR_AA_MASK 0x100u
mbed_official 146:f64d43ff0c18 5602 #define FB_CSCR_AA_SHIFT 8
mbed_official 146:f64d43ff0c18 5603 #define FB_CSCR_BLS_MASK 0x200u
mbed_official 146:f64d43ff0c18 5604 #define FB_CSCR_BLS_SHIFT 9
mbed_official 146:f64d43ff0c18 5605 #define FB_CSCR_WS_MASK 0xFC00u
mbed_official 146:f64d43ff0c18 5606 #define FB_CSCR_WS_SHIFT 10
mbed_official 146:f64d43ff0c18 5607 #define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WS_SHIFT))&FB_CSCR_WS_MASK)
mbed_official 146:f64d43ff0c18 5608 #define FB_CSCR_WRAH_MASK 0x30000u
mbed_official 146:f64d43ff0c18 5609 #define FB_CSCR_WRAH_SHIFT 16
mbed_official 146:f64d43ff0c18 5610 #define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WRAH_SHIFT))&FB_CSCR_WRAH_MASK)
mbed_official 146:f64d43ff0c18 5611 #define FB_CSCR_RDAH_MASK 0xC0000u
mbed_official 146:f64d43ff0c18 5612 #define FB_CSCR_RDAH_SHIFT 18
mbed_official 146:f64d43ff0c18 5613 #define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_RDAH_SHIFT))&FB_CSCR_RDAH_MASK)
mbed_official 146:f64d43ff0c18 5614 #define FB_CSCR_ASET_MASK 0x300000u
mbed_official 146:f64d43ff0c18 5615 #define FB_CSCR_ASET_SHIFT 20
mbed_official 146:f64d43ff0c18 5616 #define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_ASET_SHIFT))&FB_CSCR_ASET_MASK)
mbed_official 146:f64d43ff0c18 5617 #define FB_CSCR_EXTS_MASK 0x400000u
mbed_official 146:f64d43ff0c18 5618 #define FB_CSCR_EXTS_SHIFT 22
mbed_official 146:f64d43ff0c18 5619 #define FB_CSCR_SWSEN_MASK 0x800000u
mbed_official 146:f64d43ff0c18 5620 #define FB_CSCR_SWSEN_SHIFT 23
mbed_official 146:f64d43ff0c18 5621 #define FB_CSCR_SWS_MASK 0xFC000000u
mbed_official 146:f64d43ff0c18 5622 #define FB_CSCR_SWS_SHIFT 26
mbed_official 146:f64d43ff0c18 5623 #define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWS_SHIFT))&FB_CSCR_SWS_MASK)
mbed_official 146:f64d43ff0c18 5624 /* CSPMCR Bit Fields */
mbed_official 146:f64d43ff0c18 5625 #define FB_CSPMCR_GROUP5_MASK 0xF000u
mbed_official 146:f64d43ff0c18 5626 #define FB_CSPMCR_GROUP5_SHIFT 12
mbed_official 146:f64d43ff0c18 5627 #define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP5_SHIFT))&FB_CSPMCR_GROUP5_MASK)
mbed_official 146:f64d43ff0c18 5628 #define FB_CSPMCR_GROUP4_MASK 0xF0000u
mbed_official 146:f64d43ff0c18 5629 #define FB_CSPMCR_GROUP4_SHIFT 16
mbed_official 146:f64d43ff0c18 5630 #define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP4_SHIFT))&FB_CSPMCR_GROUP4_MASK)
mbed_official 146:f64d43ff0c18 5631 #define FB_CSPMCR_GROUP3_MASK 0xF00000u
mbed_official 146:f64d43ff0c18 5632 #define FB_CSPMCR_GROUP3_SHIFT 20
mbed_official 146:f64d43ff0c18 5633 #define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP3_SHIFT))&FB_CSPMCR_GROUP3_MASK)
mbed_official 146:f64d43ff0c18 5634 #define FB_CSPMCR_GROUP2_MASK 0xF000000u
mbed_official 146:f64d43ff0c18 5635 #define FB_CSPMCR_GROUP2_SHIFT 24
mbed_official 146:f64d43ff0c18 5636 #define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP2_SHIFT))&FB_CSPMCR_GROUP2_MASK)
mbed_official 146:f64d43ff0c18 5637 #define FB_CSPMCR_GROUP1_MASK 0xF0000000u
mbed_official 146:f64d43ff0c18 5638 #define FB_CSPMCR_GROUP1_SHIFT 28
mbed_official 146:f64d43ff0c18 5639 #define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP1_SHIFT))&FB_CSPMCR_GROUP1_MASK)
mbed_official 146:f64d43ff0c18 5640
mbed_official 146:f64d43ff0c18 5641 /*!
mbed_official 146:f64d43ff0c18 5642 * @}
mbed_official 146:f64d43ff0c18 5643 */ /* end of group FB_Register_Masks */
mbed_official 146:f64d43ff0c18 5644
mbed_official 146:f64d43ff0c18 5645
mbed_official 146:f64d43ff0c18 5646 /* FB - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 5647 /** Peripheral FB base address */
mbed_official 146:f64d43ff0c18 5648 #define FB_BASE (0x4000C000u)
mbed_official 146:f64d43ff0c18 5649 /** Peripheral FB base pointer */
mbed_official 146:f64d43ff0c18 5650 #define FB ((FB_Type *)FB_BASE)
mbed_official 146:f64d43ff0c18 5651 #define FB_BASE_PTR (FB)
mbed_official 146:f64d43ff0c18 5652 /** Array initializer of FB peripheral base pointers */
mbed_official 146:f64d43ff0c18 5653 #define FB_BASES { FB }
mbed_official 146:f64d43ff0c18 5654
mbed_official 146:f64d43ff0c18 5655 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5656 -- FB - Register accessor macros
mbed_official 146:f64d43ff0c18 5657 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 5658
mbed_official 146:f64d43ff0c18 5659 /*!
mbed_official 146:f64d43ff0c18 5660 * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
mbed_official 146:f64d43ff0c18 5661 * @{
mbed_official 146:f64d43ff0c18 5662 */
mbed_official 146:f64d43ff0c18 5663
mbed_official 146:f64d43ff0c18 5664
mbed_official 146:f64d43ff0c18 5665 /* FB - Register instance definitions */
mbed_official 146:f64d43ff0c18 5666 /* FB */
mbed_official 146:f64d43ff0c18 5667 #define FB_CSAR0 FB_CSAR_REG(FB,0)
mbed_official 146:f64d43ff0c18 5668 #define FB_CSMR0 FB_CSMR_REG(FB,0)
mbed_official 146:f64d43ff0c18 5669 #define FB_CSCR0 FB_CSCR_REG(FB,0)
mbed_official 146:f64d43ff0c18 5670 #define FB_CSAR1 FB_CSAR_REG(FB,1)
mbed_official 146:f64d43ff0c18 5671 #define FB_CSMR1 FB_CSMR_REG(FB,1)
mbed_official 146:f64d43ff0c18 5672 #define FB_CSCR1 FB_CSCR_REG(FB,1)
mbed_official 146:f64d43ff0c18 5673 #define FB_CSAR2 FB_CSAR_REG(FB,2)
mbed_official 146:f64d43ff0c18 5674 #define FB_CSMR2 FB_CSMR_REG(FB,2)
mbed_official 146:f64d43ff0c18 5675 #define FB_CSCR2 FB_CSCR_REG(FB,2)
mbed_official 146:f64d43ff0c18 5676 #define FB_CSAR3 FB_CSAR_REG(FB,3)
mbed_official 146:f64d43ff0c18 5677 #define FB_CSMR3 FB_CSMR_REG(FB,3)
mbed_official 146:f64d43ff0c18 5678 #define FB_CSCR3 FB_CSCR_REG(FB,3)
mbed_official 146:f64d43ff0c18 5679 #define FB_CSAR4 FB_CSAR_REG(FB,4)
mbed_official 146:f64d43ff0c18 5680 #define FB_CSMR4 FB_CSMR_REG(FB,4)
mbed_official 146:f64d43ff0c18 5681 #define FB_CSCR4 FB_CSCR_REG(FB,4)
mbed_official 146:f64d43ff0c18 5682 #define FB_CSAR5 FB_CSAR_REG(FB,5)
mbed_official 146:f64d43ff0c18 5683 #define FB_CSMR5 FB_CSMR_REG(FB,5)
mbed_official 146:f64d43ff0c18 5684 #define FB_CSCR5 FB_CSCR_REG(FB,5)
mbed_official 146:f64d43ff0c18 5685 #define FB_CSPMCR FB_CSPMCR_REG(FB)
mbed_official 146:f64d43ff0c18 5686
mbed_official 146:f64d43ff0c18 5687 /* FB - Register array accessors */
mbed_official 146:f64d43ff0c18 5688 #define FB_CSAR(index) FB_CSAR_REG(FB,index)
mbed_official 146:f64d43ff0c18 5689 #define FB_CSMR(index) FB_CSMR_REG(FB,index)
mbed_official 146:f64d43ff0c18 5690 #define FB_CSCR(index) FB_CSCR_REG(FB,index)
mbed_official 146:f64d43ff0c18 5691
mbed_official 146:f64d43ff0c18 5692 /*!
mbed_official 146:f64d43ff0c18 5693 * @}
mbed_official 146:f64d43ff0c18 5694 */ /* end of group FB_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 5695
mbed_official 146:f64d43ff0c18 5696
mbed_official 146:f64d43ff0c18 5697 /*!
mbed_official 146:f64d43ff0c18 5698 * @}
mbed_official 146:f64d43ff0c18 5699 */ /* end of group FB_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 5700
mbed_official 146:f64d43ff0c18 5701
mbed_official 146:f64d43ff0c18 5702 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5703 -- FMC Peripheral Access Layer
mbed_official 146:f64d43ff0c18 5704 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 5705
mbed_official 146:f64d43ff0c18 5706 /*!
mbed_official 146:f64d43ff0c18 5707 * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
mbed_official 146:f64d43ff0c18 5708 * @{
mbed_official 146:f64d43ff0c18 5709 */
mbed_official 146:f64d43ff0c18 5710
mbed_official 146:f64d43ff0c18 5711 /** FMC - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 5712 typedef struct {
mbed_official 146:f64d43ff0c18 5713 __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
mbed_official 146:f64d43ff0c18 5714 __IO uint32_t PFB0CR; /**< Flash Bank 0 Control Register, offset: 0x4 */
mbed_official 146:f64d43ff0c18 5715 __IO uint32_t PFB1CR; /**< Flash Bank 1 Control Register, offset: 0x8 */
mbed_official 146:f64d43ff0c18 5716 uint8_t RESERVED_0[244];
mbed_official 146:f64d43ff0c18 5717 __IO uint32_t TAGVDW0S[4]; /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
mbed_official 146:f64d43ff0c18 5718 __IO uint32_t TAGVDW1S[4]; /**< Cache Tag Storage, array offset: 0x110, array step: 0x4 */
mbed_official 146:f64d43ff0c18 5719 __IO uint32_t TAGVDW2S[4]; /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
mbed_official 146:f64d43ff0c18 5720 __IO uint32_t TAGVDW3S[4]; /**< Cache Tag Storage, array offset: 0x130, array step: 0x4 */
mbed_official 146:f64d43ff0c18 5721 uint8_t RESERVED_1[192];
mbed_official 146:f64d43ff0c18 5722 struct { /* offset: 0x200, array step: index*0x20, index2*0x8 */
mbed_official 146:f64d43ff0c18 5723 __IO uint32_t DATA_U; /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x20, index2*0x8 */
mbed_official 146:f64d43ff0c18 5724 __IO uint32_t DATA_L; /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x20, index2*0x8 */
mbed_official 146:f64d43ff0c18 5725 } SET[4][4];
mbed_official 146:f64d43ff0c18 5726 } FMC_Type, *FMC_MemMapPtr;
mbed_official 146:f64d43ff0c18 5727
mbed_official 146:f64d43ff0c18 5728 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5729 -- FMC - Register accessor macros
mbed_official 146:f64d43ff0c18 5730 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 5731
mbed_official 146:f64d43ff0c18 5732 /*!
mbed_official 146:f64d43ff0c18 5733 * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
mbed_official 146:f64d43ff0c18 5734 * @{
mbed_official 146:f64d43ff0c18 5735 */
mbed_official 146:f64d43ff0c18 5736
mbed_official 146:f64d43ff0c18 5737
mbed_official 146:f64d43ff0c18 5738 /* FMC - Register accessors */
mbed_official 146:f64d43ff0c18 5739 #define FMC_PFAPR_REG(base) ((base)->PFAPR)
mbed_official 146:f64d43ff0c18 5740 #define FMC_PFB0CR_REG(base) ((base)->PFB0CR)
mbed_official 146:f64d43ff0c18 5741 #define FMC_PFB1CR_REG(base) ((base)->PFB1CR)
mbed_official 146:f64d43ff0c18 5742 #define FMC_TAGVDW0S_REG(base,index) ((base)->TAGVDW0S[index])
mbed_official 146:f64d43ff0c18 5743 #define FMC_TAGVDW1S_REG(base,index) ((base)->TAGVDW1S[index])
mbed_official 146:f64d43ff0c18 5744 #define FMC_TAGVDW2S_REG(base,index) ((base)->TAGVDW2S[index])
mbed_official 146:f64d43ff0c18 5745 #define FMC_TAGVDW3S_REG(base,index) ((base)->TAGVDW3S[index])
mbed_official 146:f64d43ff0c18 5746 #define FMC_DATA_U_REG(base,index,index2) ((base)->SET[index][index2].DATA_U)
mbed_official 146:f64d43ff0c18 5747 #define FMC_DATA_L_REG(base,index,index2) ((base)->SET[index][index2].DATA_L)
mbed_official 146:f64d43ff0c18 5748
mbed_official 146:f64d43ff0c18 5749 /*!
mbed_official 146:f64d43ff0c18 5750 * @}
mbed_official 146:f64d43ff0c18 5751 */ /* end of group FMC_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 5752
mbed_official 146:f64d43ff0c18 5753
mbed_official 146:f64d43ff0c18 5754 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5755 -- FMC Register Masks
mbed_official 146:f64d43ff0c18 5756 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 5757
mbed_official 146:f64d43ff0c18 5758 /*!
mbed_official 146:f64d43ff0c18 5759 * @addtogroup FMC_Register_Masks FMC Register Masks
mbed_official 146:f64d43ff0c18 5760 * @{
mbed_official 146:f64d43ff0c18 5761 */
mbed_official 146:f64d43ff0c18 5762
mbed_official 146:f64d43ff0c18 5763 /* PFAPR Bit Fields */
mbed_official 146:f64d43ff0c18 5764 #define FMC_PFAPR_M0AP_MASK 0x3u
mbed_official 146:f64d43ff0c18 5765 #define FMC_PFAPR_M0AP_SHIFT 0
mbed_official 146:f64d43ff0c18 5766 #define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
mbed_official 146:f64d43ff0c18 5767 #define FMC_PFAPR_M1AP_MASK 0xCu
mbed_official 146:f64d43ff0c18 5768 #define FMC_PFAPR_M1AP_SHIFT 2
mbed_official 146:f64d43ff0c18 5769 #define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
mbed_official 146:f64d43ff0c18 5770 #define FMC_PFAPR_M2AP_MASK 0x30u
mbed_official 146:f64d43ff0c18 5771 #define FMC_PFAPR_M2AP_SHIFT 4
mbed_official 146:f64d43ff0c18 5772 #define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
mbed_official 146:f64d43ff0c18 5773 #define FMC_PFAPR_M3AP_MASK 0xC0u
mbed_official 146:f64d43ff0c18 5774 #define FMC_PFAPR_M3AP_SHIFT 6
mbed_official 146:f64d43ff0c18 5775 #define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
mbed_official 146:f64d43ff0c18 5776 #define FMC_PFAPR_M4AP_MASK 0x300u
mbed_official 146:f64d43ff0c18 5777 #define FMC_PFAPR_M4AP_SHIFT 8
mbed_official 146:f64d43ff0c18 5778 #define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4AP_SHIFT))&FMC_PFAPR_M4AP_MASK)
mbed_official 146:f64d43ff0c18 5779 #define FMC_PFAPR_M5AP_MASK 0xC00u
mbed_official 146:f64d43ff0c18 5780 #define FMC_PFAPR_M5AP_SHIFT 10
mbed_official 146:f64d43ff0c18 5781 #define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5AP_SHIFT))&FMC_PFAPR_M5AP_MASK)
mbed_official 146:f64d43ff0c18 5782 #define FMC_PFAPR_M6AP_MASK 0x3000u
mbed_official 146:f64d43ff0c18 5783 #define FMC_PFAPR_M6AP_SHIFT 12
mbed_official 146:f64d43ff0c18 5784 #define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6AP_SHIFT))&FMC_PFAPR_M6AP_MASK)
mbed_official 146:f64d43ff0c18 5785 #define FMC_PFAPR_M7AP_MASK 0xC000u
mbed_official 146:f64d43ff0c18 5786 #define FMC_PFAPR_M7AP_SHIFT 14
mbed_official 146:f64d43ff0c18 5787 #define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7AP_SHIFT))&FMC_PFAPR_M7AP_MASK)
mbed_official 146:f64d43ff0c18 5788 #define FMC_PFAPR_M0PFD_MASK 0x10000u
mbed_official 146:f64d43ff0c18 5789 #define FMC_PFAPR_M0PFD_SHIFT 16
mbed_official 146:f64d43ff0c18 5790 #define FMC_PFAPR_M1PFD_MASK 0x20000u
mbed_official 146:f64d43ff0c18 5791 #define FMC_PFAPR_M1PFD_SHIFT 17
mbed_official 146:f64d43ff0c18 5792 #define FMC_PFAPR_M2PFD_MASK 0x40000u
mbed_official 146:f64d43ff0c18 5793 #define FMC_PFAPR_M2PFD_SHIFT 18
mbed_official 146:f64d43ff0c18 5794 #define FMC_PFAPR_M3PFD_MASK 0x80000u
mbed_official 146:f64d43ff0c18 5795 #define FMC_PFAPR_M3PFD_SHIFT 19
mbed_official 146:f64d43ff0c18 5796 #define FMC_PFAPR_M4PFD_MASK 0x100000u
mbed_official 146:f64d43ff0c18 5797 #define FMC_PFAPR_M4PFD_SHIFT 20
mbed_official 146:f64d43ff0c18 5798 #define FMC_PFAPR_M5PFD_MASK 0x200000u
mbed_official 146:f64d43ff0c18 5799 #define FMC_PFAPR_M5PFD_SHIFT 21
mbed_official 146:f64d43ff0c18 5800 #define FMC_PFAPR_M6PFD_MASK 0x400000u
mbed_official 146:f64d43ff0c18 5801 #define FMC_PFAPR_M6PFD_SHIFT 22
mbed_official 146:f64d43ff0c18 5802 #define FMC_PFAPR_M7PFD_MASK 0x800000u
mbed_official 146:f64d43ff0c18 5803 #define FMC_PFAPR_M7PFD_SHIFT 23
mbed_official 146:f64d43ff0c18 5804 /* PFB0CR Bit Fields */
mbed_official 146:f64d43ff0c18 5805 #define FMC_PFB0CR_B0SEBE_MASK 0x1u
mbed_official 146:f64d43ff0c18 5806 #define FMC_PFB0CR_B0SEBE_SHIFT 0
mbed_official 146:f64d43ff0c18 5807 #define FMC_PFB0CR_B0IPE_MASK 0x2u
mbed_official 146:f64d43ff0c18 5808 #define FMC_PFB0CR_B0IPE_SHIFT 1
mbed_official 146:f64d43ff0c18 5809 #define FMC_PFB0CR_B0DPE_MASK 0x4u
mbed_official 146:f64d43ff0c18 5810 #define FMC_PFB0CR_B0DPE_SHIFT 2
mbed_official 146:f64d43ff0c18 5811 #define FMC_PFB0CR_B0ICE_MASK 0x8u
mbed_official 146:f64d43ff0c18 5812 #define FMC_PFB0CR_B0ICE_SHIFT 3
mbed_official 146:f64d43ff0c18 5813 #define FMC_PFB0CR_B0DCE_MASK 0x10u
mbed_official 146:f64d43ff0c18 5814 #define FMC_PFB0CR_B0DCE_SHIFT 4
mbed_official 146:f64d43ff0c18 5815 #define FMC_PFB0CR_CRC_MASK 0xE0u
mbed_official 146:f64d43ff0c18 5816 #define FMC_PFB0CR_CRC_SHIFT 5
mbed_official 146:f64d43ff0c18 5817 #define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
mbed_official 146:f64d43ff0c18 5818 #define FMC_PFB0CR_B0MW_MASK 0x60000u
mbed_official 146:f64d43ff0c18 5819 #define FMC_PFB0CR_B0MW_SHIFT 17
mbed_official 146:f64d43ff0c18 5820 #define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
mbed_official 146:f64d43ff0c18 5821 #define FMC_PFB0CR_S_B_INV_MASK 0x80000u
mbed_official 146:f64d43ff0c18 5822 #define FMC_PFB0CR_S_B_INV_SHIFT 19
mbed_official 146:f64d43ff0c18 5823 #define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u
mbed_official 146:f64d43ff0c18 5824 #define FMC_PFB0CR_CINV_WAY_SHIFT 20
mbed_official 146:f64d43ff0c18 5825 #define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
mbed_official 146:f64d43ff0c18 5826 #define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u
mbed_official 146:f64d43ff0c18 5827 #define FMC_PFB0CR_CLCK_WAY_SHIFT 24
mbed_official 146:f64d43ff0c18 5828 #define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
mbed_official 146:f64d43ff0c18 5829 #define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u
mbed_official 146:f64d43ff0c18 5830 #define FMC_PFB0CR_B0RWSC_SHIFT 28
mbed_official 146:f64d43ff0c18 5831 #define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
mbed_official 146:f64d43ff0c18 5832 /* PFB1CR Bit Fields */
mbed_official 146:f64d43ff0c18 5833 #define FMC_PFB1CR_B1SEBE_MASK 0x1u
mbed_official 146:f64d43ff0c18 5834 #define FMC_PFB1CR_B1SEBE_SHIFT 0
mbed_official 146:f64d43ff0c18 5835 #define FMC_PFB1CR_B1IPE_MASK 0x2u
mbed_official 146:f64d43ff0c18 5836 #define FMC_PFB1CR_B1IPE_SHIFT 1
mbed_official 146:f64d43ff0c18 5837 #define FMC_PFB1CR_B1DPE_MASK 0x4u
mbed_official 146:f64d43ff0c18 5838 #define FMC_PFB1CR_B1DPE_SHIFT 2
mbed_official 146:f64d43ff0c18 5839 #define FMC_PFB1CR_B1ICE_MASK 0x8u
mbed_official 146:f64d43ff0c18 5840 #define FMC_PFB1CR_B1ICE_SHIFT 3
mbed_official 146:f64d43ff0c18 5841 #define FMC_PFB1CR_B1DCE_MASK 0x10u
mbed_official 146:f64d43ff0c18 5842 #define FMC_PFB1CR_B1DCE_SHIFT 4
mbed_official 146:f64d43ff0c18 5843 #define FMC_PFB1CR_B1MW_MASK 0x60000u
mbed_official 146:f64d43ff0c18 5844 #define FMC_PFB1CR_B1MW_SHIFT 17
mbed_official 146:f64d43ff0c18 5845 #define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1MW_SHIFT))&FMC_PFB1CR_B1MW_MASK)
mbed_official 146:f64d43ff0c18 5846 #define FMC_PFB1CR_B1RWSC_MASK 0xF0000000u
mbed_official 146:f64d43ff0c18 5847 #define FMC_PFB1CR_B1RWSC_SHIFT 28
mbed_official 146:f64d43ff0c18 5848 #define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1RWSC_SHIFT))&FMC_PFB1CR_B1RWSC_MASK)
mbed_official 146:f64d43ff0c18 5849 /* TAGVDW0S Bit Fields */
mbed_official 146:f64d43ff0c18 5850 #define FMC_TAGVDW0S_valid_MASK 0x1u
mbed_official 146:f64d43ff0c18 5851 #define FMC_TAGVDW0S_valid_SHIFT 0
mbed_official 146:f64d43ff0c18 5852 #define FMC_TAGVDW0S_tag_MASK 0x7FFE0u
mbed_official 146:f64d43ff0c18 5853 #define FMC_TAGVDW0S_tag_SHIFT 5
mbed_official 146:f64d43ff0c18 5854 #define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_tag_SHIFT))&FMC_TAGVDW0S_tag_MASK)
mbed_official 146:f64d43ff0c18 5855 /* TAGVDW1S Bit Fields */
mbed_official 146:f64d43ff0c18 5856 #define FMC_TAGVDW1S_valid_MASK 0x1u
mbed_official 146:f64d43ff0c18 5857 #define FMC_TAGVDW1S_valid_SHIFT 0
mbed_official 146:f64d43ff0c18 5858 #define FMC_TAGVDW1S_tag_MASK 0x7FFE0u
mbed_official 146:f64d43ff0c18 5859 #define FMC_TAGVDW1S_tag_SHIFT 5
mbed_official 146:f64d43ff0c18 5860 #define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_tag_SHIFT))&FMC_TAGVDW1S_tag_MASK)
mbed_official 146:f64d43ff0c18 5861 /* TAGVDW2S Bit Fields */
mbed_official 146:f64d43ff0c18 5862 #define FMC_TAGVDW2S_valid_MASK 0x1u
mbed_official 146:f64d43ff0c18 5863 #define FMC_TAGVDW2S_valid_SHIFT 0
mbed_official 146:f64d43ff0c18 5864 #define FMC_TAGVDW2S_tag_MASK 0x7FFE0u
mbed_official 146:f64d43ff0c18 5865 #define FMC_TAGVDW2S_tag_SHIFT 5
mbed_official 146:f64d43ff0c18 5866 #define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_tag_SHIFT))&FMC_TAGVDW2S_tag_MASK)
mbed_official 146:f64d43ff0c18 5867 /* TAGVDW3S Bit Fields */
mbed_official 146:f64d43ff0c18 5868 #define FMC_TAGVDW3S_valid_MASK 0x1u
mbed_official 146:f64d43ff0c18 5869 #define FMC_TAGVDW3S_valid_SHIFT 0
mbed_official 146:f64d43ff0c18 5870 #define FMC_TAGVDW3S_tag_MASK 0x7FFE0u
mbed_official 146:f64d43ff0c18 5871 #define FMC_TAGVDW3S_tag_SHIFT 5
mbed_official 146:f64d43ff0c18 5872 #define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_tag_SHIFT))&FMC_TAGVDW3S_tag_MASK)
mbed_official 146:f64d43ff0c18 5873 /* DATA_U Bit Fields */
mbed_official 146:f64d43ff0c18 5874 #define FMC_DATA_U_data_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 5875 #define FMC_DATA_U_data_SHIFT 0
mbed_official 146:f64d43ff0c18 5876 #define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_U_data_SHIFT))&FMC_DATA_U_data_MASK)
mbed_official 146:f64d43ff0c18 5877 /* DATA_L Bit Fields */
mbed_official 146:f64d43ff0c18 5878 #define FMC_DATA_L_data_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 5879 #define FMC_DATA_L_data_SHIFT 0
mbed_official 146:f64d43ff0c18 5880 #define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_L_data_SHIFT))&FMC_DATA_L_data_MASK)
mbed_official 146:f64d43ff0c18 5881
mbed_official 146:f64d43ff0c18 5882 /*!
mbed_official 146:f64d43ff0c18 5883 * @}
mbed_official 146:f64d43ff0c18 5884 */ /* end of group FMC_Register_Masks */
mbed_official 146:f64d43ff0c18 5885
mbed_official 146:f64d43ff0c18 5886
mbed_official 146:f64d43ff0c18 5887 /* FMC - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 5888 /** Peripheral FMC base address */
mbed_official 146:f64d43ff0c18 5889 #define FMC_BASE (0x4001F000u)
mbed_official 146:f64d43ff0c18 5890 /** Peripheral FMC base pointer */
mbed_official 146:f64d43ff0c18 5891 #define FMC ((FMC_Type *)FMC_BASE)
mbed_official 146:f64d43ff0c18 5892 #define FMC_BASE_PTR (FMC)
mbed_official 146:f64d43ff0c18 5893 /** Array initializer of FMC peripheral base pointers */
mbed_official 146:f64d43ff0c18 5894 #define FMC_BASES { FMC }
mbed_official 146:f64d43ff0c18 5895
mbed_official 146:f64d43ff0c18 5896 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5897 -- FMC - Register accessor macros
mbed_official 146:f64d43ff0c18 5898 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 5899
mbed_official 146:f64d43ff0c18 5900 /*!
mbed_official 146:f64d43ff0c18 5901 * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
mbed_official 146:f64d43ff0c18 5902 * @{
mbed_official 146:f64d43ff0c18 5903 */
mbed_official 146:f64d43ff0c18 5904
mbed_official 146:f64d43ff0c18 5905
mbed_official 146:f64d43ff0c18 5906 /* FMC - Register instance definitions */
mbed_official 146:f64d43ff0c18 5907 /* FMC */
mbed_official 146:f64d43ff0c18 5908 #define FMC_PFAPR FMC_PFAPR_REG(FMC)
mbed_official 146:f64d43ff0c18 5909 #define FMC_PFB0CR FMC_PFB0CR_REG(FMC)
mbed_official 146:f64d43ff0c18 5910 #define FMC_PFB1CR FMC_PFB1CR_REG(FMC)
mbed_official 146:f64d43ff0c18 5911 #define FMC_TAGVDW0S0 FMC_TAGVDW0S_REG(FMC,0)
mbed_official 146:f64d43ff0c18 5912 #define FMC_TAGVDW0S1 FMC_TAGVDW0S_REG(FMC,1)
mbed_official 146:f64d43ff0c18 5913 #define FMC_TAGVDW0S2 FMC_TAGVDW0S_REG(FMC,2)
mbed_official 146:f64d43ff0c18 5914 #define FMC_TAGVDW0S3 FMC_TAGVDW0S_REG(FMC,3)
mbed_official 146:f64d43ff0c18 5915 #define FMC_TAGVDW1S0 FMC_TAGVDW1S_REG(FMC,0)
mbed_official 146:f64d43ff0c18 5916 #define FMC_TAGVDW1S1 FMC_TAGVDW1S_REG(FMC,1)
mbed_official 146:f64d43ff0c18 5917 #define FMC_TAGVDW1S2 FMC_TAGVDW1S_REG(FMC,2)
mbed_official 146:f64d43ff0c18 5918 #define FMC_TAGVDW1S3 FMC_TAGVDW1S_REG(FMC,3)
mbed_official 146:f64d43ff0c18 5919 #define FMC_TAGVDW2S0 FMC_TAGVDW2S_REG(FMC,0)
mbed_official 146:f64d43ff0c18 5920 #define FMC_TAGVDW2S1 FMC_TAGVDW2S_REG(FMC,1)
mbed_official 146:f64d43ff0c18 5921 #define FMC_TAGVDW2S2 FMC_TAGVDW2S_REG(FMC,2)
mbed_official 146:f64d43ff0c18 5922 #define FMC_TAGVDW2S3 FMC_TAGVDW2S_REG(FMC,3)
mbed_official 146:f64d43ff0c18 5923 #define FMC_TAGVDW3S0 FMC_TAGVDW3S_REG(FMC,0)
mbed_official 146:f64d43ff0c18 5924 #define FMC_TAGVDW3S1 FMC_TAGVDW3S_REG(FMC,1)
mbed_official 146:f64d43ff0c18 5925 #define FMC_TAGVDW3S2 FMC_TAGVDW3S_REG(FMC,2)
mbed_official 146:f64d43ff0c18 5926 #define FMC_TAGVDW3S3 FMC_TAGVDW3S_REG(FMC,3)
mbed_official 146:f64d43ff0c18 5927 #define FMC_DATAW0S0U FMC_DATA_U_REG(FMC,0,0)
mbed_official 146:f64d43ff0c18 5928 #define FMC_DATAW0S0L FMC_DATA_L_REG(FMC,0,0)
mbed_official 146:f64d43ff0c18 5929 #define FMC_DATAW0S1U FMC_DATA_U_REG(FMC,0,1)
mbed_official 146:f64d43ff0c18 5930 #define FMC_DATAW0S1L FMC_DATA_L_REG(FMC,0,1)
mbed_official 146:f64d43ff0c18 5931 #define FMC_DATAW0S2U FMC_DATA_U_REG(FMC,0,2)
mbed_official 146:f64d43ff0c18 5932 #define FMC_DATAW0S2L FMC_DATA_L_REG(FMC,0,2)
mbed_official 146:f64d43ff0c18 5933 #define FMC_DATAW0S3U FMC_DATA_U_REG(FMC,0,3)
mbed_official 146:f64d43ff0c18 5934 #define FMC_DATAW0S3L FMC_DATA_L_REG(FMC,0,3)
mbed_official 146:f64d43ff0c18 5935 #define FMC_DATAW1S0U FMC_DATA_U_REG(FMC,1,0)
mbed_official 146:f64d43ff0c18 5936 #define FMC_DATAW1S0L FMC_DATA_L_REG(FMC,1,0)
mbed_official 146:f64d43ff0c18 5937 #define FMC_DATAW1S1U FMC_DATA_U_REG(FMC,1,1)
mbed_official 146:f64d43ff0c18 5938 #define FMC_DATAW1S1L FMC_DATA_L_REG(FMC,1,1)
mbed_official 146:f64d43ff0c18 5939 #define FMC_DATAW1S2U FMC_DATA_U_REG(FMC,1,2)
mbed_official 146:f64d43ff0c18 5940 #define FMC_DATAW1S2L FMC_DATA_L_REG(FMC,1,2)
mbed_official 146:f64d43ff0c18 5941 #define FMC_DATAW1S3U FMC_DATA_U_REG(FMC,1,3)
mbed_official 146:f64d43ff0c18 5942 #define FMC_DATAW1S3L FMC_DATA_L_REG(FMC,1,3)
mbed_official 146:f64d43ff0c18 5943 #define FMC_DATAW2S0U FMC_DATA_U_REG(FMC,2,0)
mbed_official 146:f64d43ff0c18 5944 #define FMC_DATAW2S0L FMC_DATA_L_REG(FMC,2,0)
mbed_official 146:f64d43ff0c18 5945 #define FMC_DATAW2S1U FMC_DATA_U_REG(FMC,2,1)
mbed_official 146:f64d43ff0c18 5946 #define FMC_DATAW2S1L FMC_DATA_L_REG(FMC,2,1)
mbed_official 146:f64d43ff0c18 5947 #define FMC_DATAW2S2U FMC_DATA_U_REG(FMC,2,2)
mbed_official 146:f64d43ff0c18 5948 #define FMC_DATAW2S2L FMC_DATA_L_REG(FMC,2,2)
mbed_official 146:f64d43ff0c18 5949 #define FMC_DATAW2S3U FMC_DATA_U_REG(FMC,2,3)
mbed_official 146:f64d43ff0c18 5950 #define FMC_DATAW2S3L FMC_DATA_L_REG(FMC,2,3)
mbed_official 146:f64d43ff0c18 5951 #define FMC_DATAW3S0U FMC_DATA_U_REG(FMC,3,0)
mbed_official 146:f64d43ff0c18 5952 #define FMC_DATAW3S0L FMC_DATA_L_REG(FMC,3,0)
mbed_official 146:f64d43ff0c18 5953 #define FMC_DATAW3S1U FMC_DATA_U_REG(FMC,3,1)
mbed_official 146:f64d43ff0c18 5954 #define FMC_DATAW3S1L FMC_DATA_L_REG(FMC,3,1)
mbed_official 146:f64d43ff0c18 5955 #define FMC_DATAW3S2U FMC_DATA_U_REG(FMC,3,2)
mbed_official 146:f64d43ff0c18 5956 #define FMC_DATAW3S2L FMC_DATA_L_REG(FMC,3,2)
mbed_official 146:f64d43ff0c18 5957 #define FMC_DATAW3S3U FMC_DATA_U_REG(FMC,3,3)
mbed_official 146:f64d43ff0c18 5958 #define FMC_DATAW3S3L FMC_DATA_L_REG(FMC,3,3)
mbed_official 146:f64d43ff0c18 5959
mbed_official 146:f64d43ff0c18 5960 /* FMC - Register array accessors */
mbed_official 146:f64d43ff0c18 5961 #define FMC_TAGVDW0S(index) FMC_TAGVDW0S_REG(FMC,index)
mbed_official 146:f64d43ff0c18 5962 #define FMC_TAGVDW1S(index) FMC_TAGVDW1S_REG(FMC,index)
mbed_official 146:f64d43ff0c18 5963 #define FMC_TAGVDW2S(index) FMC_TAGVDW2S_REG(FMC,index)
mbed_official 146:f64d43ff0c18 5964 #define FMC_TAGVDW3S(index) FMC_TAGVDW3S_REG(FMC,index)
mbed_official 146:f64d43ff0c18 5965 #define FMC_DATA_U(index,index2) FMC_DATA_U_REG(FMC,index,index2)
mbed_official 146:f64d43ff0c18 5966 #define FMC_DATA_L(index,index2) FMC_DATA_L_REG(FMC,index,index2)
mbed_official 146:f64d43ff0c18 5967
mbed_official 146:f64d43ff0c18 5968 /*!
mbed_official 146:f64d43ff0c18 5969 * @}
mbed_official 146:f64d43ff0c18 5970 */ /* end of group FMC_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 5971
mbed_official 146:f64d43ff0c18 5972
mbed_official 146:f64d43ff0c18 5973 /*!
mbed_official 146:f64d43ff0c18 5974 * @}
mbed_official 146:f64d43ff0c18 5975 */ /* end of group FMC_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 5976
mbed_official 146:f64d43ff0c18 5977
mbed_official 146:f64d43ff0c18 5978 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5979 -- FTFE Peripheral Access Layer
mbed_official 146:f64d43ff0c18 5980 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 5981
mbed_official 146:f64d43ff0c18 5982 /*!
mbed_official 146:f64d43ff0c18 5983 * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer
mbed_official 146:f64d43ff0c18 5984 * @{
mbed_official 146:f64d43ff0c18 5985 */
mbed_official 146:f64d43ff0c18 5986
mbed_official 146:f64d43ff0c18 5987 /** FTFE - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 5988 typedef struct {
mbed_official 146:f64d43ff0c18 5989 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
mbed_official 146:f64d43ff0c18 5990 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
mbed_official 146:f64d43ff0c18 5991 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
mbed_official 146:f64d43ff0c18 5992 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
mbed_official 146:f64d43ff0c18 5993 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
mbed_official 146:f64d43ff0c18 5994 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
mbed_official 146:f64d43ff0c18 5995 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
mbed_official 146:f64d43ff0c18 5996 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
mbed_official 146:f64d43ff0c18 5997 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
mbed_official 146:f64d43ff0c18 5998 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
mbed_official 146:f64d43ff0c18 5999 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
mbed_official 146:f64d43ff0c18 6000 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
mbed_official 146:f64d43ff0c18 6001 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
mbed_official 146:f64d43ff0c18 6002 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
mbed_official 146:f64d43ff0c18 6003 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
mbed_official 146:f64d43ff0c18 6004 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
mbed_official 146:f64d43ff0c18 6005 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
mbed_official 146:f64d43ff0c18 6006 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
mbed_official 146:f64d43ff0c18 6007 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
mbed_official 146:f64d43ff0c18 6008 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
mbed_official 146:f64d43ff0c18 6009 uint8_t RESERVED_0[2];
mbed_official 146:f64d43ff0c18 6010 __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */
mbed_official 146:f64d43ff0c18 6011 __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */
mbed_official 146:f64d43ff0c18 6012 } FTFE_Type, *FTFE_MemMapPtr;
mbed_official 146:f64d43ff0c18 6013
mbed_official 146:f64d43ff0c18 6014 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6015 -- FTFE - Register accessor macros
mbed_official 146:f64d43ff0c18 6016 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 6017
mbed_official 146:f64d43ff0c18 6018 /*!
mbed_official 146:f64d43ff0c18 6019 * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
mbed_official 146:f64d43ff0c18 6020 * @{
mbed_official 146:f64d43ff0c18 6021 */
mbed_official 146:f64d43ff0c18 6022
mbed_official 146:f64d43ff0c18 6023
mbed_official 146:f64d43ff0c18 6024 /* FTFE - Register accessors */
mbed_official 146:f64d43ff0c18 6025 #define FTFE_FSTAT_REG(base) ((base)->FSTAT)
mbed_official 146:f64d43ff0c18 6026 #define FTFE_FCNFG_REG(base) ((base)->FCNFG)
mbed_official 146:f64d43ff0c18 6027 #define FTFE_FSEC_REG(base) ((base)->FSEC)
mbed_official 146:f64d43ff0c18 6028 #define FTFE_FOPT_REG(base) ((base)->FOPT)
mbed_official 146:f64d43ff0c18 6029 #define FTFE_FCCOB3_REG(base) ((base)->FCCOB3)
mbed_official 146:f64d43ff0c18 6030 #define FTFE_FCCOB2_REG(base) ((base)->FCCOB2)
mbed_official 146:f64d43ff0c18 6031 #define FTFE_FCCOB1_REG(base) ((base)->FCCOB1)
mbed_official 146:f64d43ff0c18 6032 #define FTFE_FCCOB0_REG(base) ((base)->FCCOB0)
mbed_official 146:f64d43ff0c18 6033 #define FTFE_FCCOB7_REG(base) ((base)->FCCOB7)
mbed_official 146:f64d43ff0c18 6034 #define FTFE_FCCOB6_REG(base) ((base)->FCCOB6)
mbed_official 146:f64d43ff0c18 6035 #define FTFE_FCCOB5_REG(base) ((base)->FCCOB5)
mbed_official 146:f64d43ff0c18 6036 #define FTFE_FCCOB4_REG(base) ((base)->FCCOB4)
mbed_official 146:f64d43ff0c18 6037 #define FTFE_FCCOBB_REG(base) ((base)->FCCOBB)
mbed_official 146:f64d43ff0c18 6038 #define FTFE_FCCOBA_REG(base) ((base)->FCCOBA)
mbed_official 146:f64d43ff0c18 6039 #define FTFE_FCCOB9_REG(base) ((base)->FCCOB9)
mbed_official 146:f64d43ff0c18 6040 #define FTFE_FCCOB8_REG(base) ((base)->FCCOB8)
mbed_official 146:f64d43ff0c18 6041 #define FTFE_FPROT3_REG(base) ((base)->FPROT3)
mbed_official 146:f64d43ff0c18 6042 #define FTFE_FPROT2_REG(base) ((base)->FPROT2)
mbed_official 146:f64d43ff0c18 6043 #define FTFE_FPROT1_REG(base) ((base)->FPROT1)
mbed_official 146:f64d43ff0c18 6044 #define FTFE_FPROT0_REG(base) ((base)->FPROT0)
mbed_official 146:f64d43ff0c18 6045 #define FTFE_FEPROT_REG(base) ((base)->FEPROT)
mbed_official 146:f64d43ff0c18 6046 #define FTFE_FDPROT_REG(base) ((base)->FDPROT)
mbed_official 146:f64d43ff0c18 6047
mbed_official 146:f64d43ff0c18 6048 /*!
mbed_official 146:f64d43ff0c18 6049 * @}
mbed_official 146:f64d43ff0c18 6050 */ /* end of group FTFE_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 6051
mbed_official 146:f64d43ff0c18 6052
mbed_official 146:f64d43ff0c18 6053 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6054 -- FTFE Register Masks
mbed_official 146:f64d43ff0c18 6055 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 6056
mbed_official 146:f64d43ff0c18 6057 /*!
mbed_official 146:f64d43ff0c18 6058 * @addtogroup FTFE_Register_Masks FTFE Register Masks
mbed_official 146:f64d43ff0c18 6059 * @{
mbed_official 146:f64d43ff0c18 6060 */
mbed_official 146:f64d43ff0c18 6061
mbed_official 146:f64d43ff0c18 6062 /* FSTAT Bit Fields */
mbed_official 146:f64d43ff0c18 6063 #define FTFE_FSTAT_MGSTAT0_MASK 0x1u
mbed_official 146:f64d43ff0c18 6064 #define FTFE_FSTAT_MGSTAT0_SHIFT 0
mbed_official 146:f64d43ff0c18 6065 #define FTFE_FSTAT_FPVIOL_MASK 0x10u
mbed_official 146:f64d43ff0c18 6066 #define FTFE_FSTAT_FPVIOL_SHIFT 4
mbed_official 146:f64d43ff0c18 6067 #define FTFE_FSTAT_ACCERR_MASK 0x20u
mbed_official 146:f64d43ff0c18 6068 #define FTFE_FSTAT_ACCERR_SHIFT 5
mbed_official 146:f64d43ff0c18 6069 #define FTFE_FSTAT_RDCOLERR_MASK 0x40u
mbed_official 146:f64d43ff0c18 6070 #define FTFE_FSTAT_RDCOLERR_SHIFT 6
mbed_official 146:f64d43ff0c18 6071 #define FTFE_FSTAT_CCIF_MASK 0x80u
mbed_official 146:f64d43ff0c18 6072 #define FTFE_FSTAT_CCIF_SHIFT 7
mbed_official 146:f64d43ff0c18 6073 /* FCNFG Bit Fields */
mbed_official 146:f64d43ff0c18 6074 #define FTFE_FCNFG_EEERDY_MASK 0x1u
mbed_official 146:f64d43ff0c18 6075 #define FTFE_FCNFG_EEERDY_SHIFT 0
mbed_official 146:f64d43ff0c18 6076 #define FTFE_FCNFG_RAMRDY_MASK 0x2u
mbed_official 146:f64d43ff0c18 6077 #define FTFE_FCNFG_RAMRDY_SHIFT 1
mbed_official 146:f64d43ff0c18 6078 #define FTFE_FCNFG_PFLSH_MASK 0x4u
mbed_official 146:f64d43ff0c18 6079 #define FTFE_FCNFG_PFLSH_SHIFT 2
mbed_official 146:f64d43ff0c18 6080 #define FTFE_FCNFG_SWAP_MASK 0x8u
mbed_official 146:f64d43ff0c18 6081 #define FTFE_FCNFG_SWAP_SHIFT 3
mbed_official 146:f64d43ff0c18 6082 #define FTFE_FCNFG_ERSSUSP_MASK 0x10u
mbed_official 146:f64d43ff0c18 6083 #define FTFE_FCNFG_ERSSUSP_SHIFT 4
mbed_official 146:f64d43ff0c18 6084 #define FTFE_FCNFG_ERSAREQ_MASK 0x20u
mbed_official 146:f64d43ff0c18 6085 #define FTFE_FCNFG_ERSAREQ_SHIFT 5
mbed_official 146:f64d43ff0c18 6086 #define FTFE_FCNFG_RDCOLLIE_MASK 0x40u
mbed_official 146:f64d43ff0c18 6087 #define FTFE_FCNFG_RDCOLLIE_SHIFT 6
mbed_official 146:f64d43ff0c18 6088 #define FTFE_FCNFG_CCIE_MASK 0x80u
mbed_official 146:f64d43ff0c18 6089 #define FTFE_FCNFG_CCIE_SHIFT 7
mbed_official 146:f64d43ff0c18 6090 /* FSEC Bit Fields */
mbed_official 146:f64d43ff0c18 6091 #define FTFE_FSEC_SEC_MASK 0x3u
mbed_official 146:f64d43ff0c18 6092 #define FTFE_FSEC_SEC_SHIFT 0
mbed_official 146:f64d43ff0c18 6093 #define FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_SEC_SHIFT))&FTFE_FSEC_SEC_MASK)
mbed_official 146:f64d43ff0c18 6094 #define FTFE_FSEC_FSLACC_MASK 0xCu
mbed_official 146:f64d43ff0c18 6095 #define FTFE_FSEC_FSLACC_SHIFT 2
mbed_official 146:f64d43ff0c18 6096 #define FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_FSLACC_SHIFT))&FTFE_FSEC_FSLACC_MASK)
mbed_official 146:f64d43ff0c18 6097 #define FTFE_FSEC_MEEN_MASK 0x30u
mbed_official 146:f64d43ff0c18 6098 #define FTFE_FSEC_MEEN_SHIFT 4
mbed_official 146:f64d43ff0c18 6099 #define FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_MEEN_SHIFT))&FTFE_FSEC_MEEN_MASK)
mbed_official 146:f64d43ff0c18 6100 #define FTFE_FSEC_KEYEN_MASK 0xC0u
mbed_official 146:f64d43ff0c18 6101 #define FTFE_FSEC_KEYEN_SHIFT 6
mbed_official 146:f64d43ff0c18 6102 #define FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_KEYEN_SHIFT))&FTFE_FSEC_KEYEN_MASK)
mbed_official 146:f64d43ff0c18 6103 /* FOPT Bit Fields */
mbed_official 146:f64d43ff0c18 6104 #define FTFE_FOPT_OPT_MASK 0xFFu
mbed_official 146:f64d43ff0c18 6105 #define FTFE_FOPT_OPT_SHIFT 0
mbed_official 146:f64d43ff0c18 6106 #define FTFE_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FOPT_OPT_SHIFT))&FTFE_FOPT_OPT_MASK)
mbed_official 146:f64d43ff0c18 6107 /* FCCOB3 Bit Fields */
mbed_official 146:f64d43ff0c18 6108 #define FTFE_FCCOB3_CCOBn_MASK 0xFFu
mbed_official 146:f64d43ff0c18 6109 #define FTFE_FCCOB3_CCOBn_SHIFT 0
mbed_official 146:f64d43ff0c18 6110 #define FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB3_CCOBn_SHIFT))&FTFE_FCCOB3_CCOBn_MASK)
mbed_official 146:f64d43ff0c18 6111 /* FCCOB2 Bit Fields */
mbed_official 146:f64d43ff0c18 6112 #define FTFE_FCCOB2_CCOBn_MASK 0xFFu
mbed_official 146:f64d43ff0c18 6113 #define FTFE_FCCOB2_CCOBn_SHIFT 0
mbed_official 146:f64d43ff0c18 6114 #define FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB2_CCOBn_SHIFT))&FTFE_FCCOB2_CCOBn_MASK)
mbed_official 146:f64d43ff0c18 6115 /* FCCOB1 Bit Fields */
mbed_official 146:f64d43ff0c18 6116 #define FTFE_FCCOB1_CCOBn_MASK 0xFFu
mbed_official 146:f64d43ff0c18 6117 #define FTFE_FCCOB1_CCOBn_SHIFT 0
mbed_official 146:f64d43ff0c18 6118 #define FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB1_CCOBn_SHIFT))&FTFE_FCCOB1_CCOBn_MASK)
mbed_official 146:f64d43ff0c18 6119 /* FCCOB0 Bit Fields */
mbed_official 146:f64d43ff0c18 6120 #define FTFE_FCCOB0_CCOBn_MASK 0xFFu
mbed_official 146:f64d43ff0c18 6121 #define FTFE_FCCOB0_CCOBn_SHIFT 0
mbed_official 146:f64d43ff0c18 6122 #define FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB0_CCOBn_SHIFT))&FTFE_FCCOB0_CCOBn_MASK)
mbed_official 146:f64d43ff0c18 6123 /* FCCOB7 Bit Fields */
mbed_official 146:f64d43ff0c18 6124 #define FTFE_FCCOB7_CCOBn_MASK 0xFFu
mbed_official 146:f64d43ff0c18 6125 #define FTFE_FCCOB7_CCOBn_SHIFT 0
mbed_official 146:f64d43ff0c18 6126 #define FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB7_CCOBn_SHIFT))&FTFE_FCCOB7_CCOBn_MASK)
mbed_official 146:f64d43ff0c18 6127 /* FCCOB6 Bit Fields */
mbed_official 146:f64d43ff0c18 6128 #define FTFE_FCCOB6_CCOBn_MASK 0xFFu
mbed_official 146:f64d43ff0c18 6129 #define FTFE_FCCOB6_CCOBn_SHIFT 0
mbed_official 146:f64d43ff0c18 6130 #define FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB6_CCOBn_SHIFT))&FTFE_FCCOB6_CCOBn_MASK)
mbed_official 146:f64d43ff0c18 6131 /* FCCOB5 Bit Fields */
mbed_official 146:f64d43ff0c18 6132 #define FTFE_FCCOB5_CCOBn_MASK 0xFFu
mbed_official 146:f64d43ff0c18 6133 #define FTFE_FCCOB5_CCOBn_SHIFT 0
mbed_official 146:f64d43ff0c18 6134 #define FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB5_CCOBn_SHIFT))&FTFE_FCCOB5_CCOBn_MASK)
mbed_official 146:f64d43ff0c18 6135 /* FCCOB4 Bit Fields */
mbed_official 146:f64d43ff0c18 6136 #define FTFE_FCCOB4_CCOBn_MASK 0xFFu
mbed_official 146:f64d43ff0c18 6137 #define FTFE_FCCOB4_CCOBn_SHIFT 0
mbed_official 146:f64d43ff0c18 6138 #define FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB4_CCOBn_SHIFT))&FTFE_FCCOB4_CCOBn_MASK)
mbed_official 146:f64d43ff0c18 6139 /* FCCOBB Bit Fields */
mbed_official 146:f64d43ff0c18 6140 #define FTFE_FCCOBB_CCOBn_MASK 0xFFu
mbed_official 146:f64d43ff0c18 6141 #define FTFE_FCCOBB_CCOBn_SHIFT 0
mbed_official 146:f64d43ff0c18 6142 #define FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBB_CCOBn_SHIFT))&FTFE_FCCOBB_CCOBn_MASK)
mbed_official 146:f64d43ff0c18 6143 /* FCCOBA Bit Fields */
mbed_official 146:f64d43ff0c18 6144 #define FTFE_FCCOBA_CCOBn_MASK 0xFFu
mbed_official 146:f64d43ff0c18 6145 #define FTFE_FCCOBA_CCOBn_SHIFT 0
mbed_official 146:f64d43ff0c18 6146 #define FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBA_CCOBn_SHIFT))&FTFE_FCCOBA_CCOBn_MASK)
mbed_official 146:f64d43ff0c18 6147 /* FCCOB9 Bit Fields */
mbed_official 146:f64d43ff0c18 6148 #define FTFE_FCCOB9_CCOBn_MASK 0xFFu
mbed_official 146:f64d43ff0c18 6149 #define FTFE_FCCOB9_CCOBn_SHIFT 0
mbed_official 146:f64d43ff0c18 6150 #define FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB9_CCOBn_SHIFT))&FTFE_FCCOB9_CCOBn_MASK)
mbed_official 146:f64d43ff0c18 6151 /* FCCOB8 Bit Fields */
mbed_official 146:f64d43ff0c18 6152 #define FTFE_FCCOB8_CCOBn_MASK 0xFFu
mbed_official 146:f64d43ff0c18 6153 #define FTFE_FCCOB8_CCOBn_SHIFT 0
mbed_official 146:f64d43ff0c18 6154 #define FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB8_CCOBn_SHIFT))&FTFE_FCCOB8_CCOBn_MASK)
mbed_official 146:f64d43ff0c18 6155 /* FPROT3 Bit Fields */
mbed_official 146:f64d43ff0c18 6156 #define FTFE_FPROT3_PROT_MASK 0xFFu
mbed_official 146:f64d43ff0c18 6157 #define FTFE_FPROT3_PROT_SHIFT 0
mbed_official 146:f64d43ff0c18 6158 #define FTFE_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT3_PROT_SHIFT))&FTFE_FPROT3_PROT_MASK)
mbed_official 146:f64d43ff0c18 6159 /* FPROT2 Bit Fields */
mbed_official 146:f64d43ff0c18 6160 #define FTFE_FPROT2_PROT_MASK 0xFFu
mbed_official 146:f64d43ff0c18 6161 #define FTFE_FPROT2_PROT_SHIFT 0
mbed_official 146:f64d43ff0c18 6162 #define FTFE_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT2_PROT_SHIFT))&FTFE_FPROT2_PROT_MASK)
mbed_official 146:f64d43ff0c18 6163 /* FPROT1 Bit Fields */
mbed_official 146:f64d43ff0c18 6164 #define FTFE_FPROT1_PROT_MASK 0xFFu
mbed_official 146:f64d43ff0c18 6165 #define FTFE_FPROT1_PROT_SHIFT 0
mbed_official 146:f64d43ff0c18 6166 #define FTFE_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT1_PROT_SHIFT))&FTFE_FPROT1_PROT_MASK)
mbed_official 146:f64d43ff0c18 6167 /* FPROT0 Bit Fields */
mbed_official 146:f64d43ff0c18 6168 #define FTFE_FPROT0_PROT_MASK 0xFFu
mbed_official 146:f64d43ff0c18 6169 #define FTFE_FPROT0_PROT_SHIFT 0
mbed_official 146:f64d43ff0c18 6170 #define FTFE_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT0_PROT_SHIFT))&FTFE_FPROT0_PROT_MASK)
mbed_official 146:f64d43ff0c18 6171 /* FEPROT Bit Fields */
mbed_official 146:f64d43ff0c18 6172 #define FTFE_FEPROT_EPROT_MASK 0xFFu
mbed_official 146:f64d43ff0c18 6173 #define FTFE_FEPROT_EPROT_SHIFT 0
mbed_official 146:f64d43ff0c18 6174 #define FTFE_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FEPROT_EPROT_SHIFT))&FTFE_FEPROT_EPROT_MASK)
mbed_official 146:f64d43ff0c18 6175 /* FDPROT Bit Fields */
mbed_official 146:f64d43ff0c18 6176 #define FTFE_FDPROT_DPROT_MASK 0xFFu
mbed_official 146:f64d43ff0c18 6177 #define FTFE_FDPROT_DPROT_SHIFT 0
mbed_official 146:f64d43ff0c18 6178 #define FTFE_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FDPROT_DPROT_SHIFT))&FTFE_FDPROT_DPROT_MASK)
mbed_official 146:f64d43ff0c18 6179
mbed_official 146:f64d43ff0c18 6180 /*!
mbed_official 146:f64d43ff0c18 6181 * @}
mbed_official 146:f64d43ff0c18 6182 */ /* end of group FTFE_Register_Masks */
mbed_official 146:f64d43ff0c18 6183
mbed_official 146:f64d43ff0c18 6184
mbed_official 146:f64d43ff0c18 6185 /* FTFE - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 6186 /** Peripheral FTFE base address */
mbed_official 146:f64d43ff0c18 6187 #define FTFE_BASE (0x40020000u)
mbed_official 146:f64d43ff0c18 6188 /** Peripheral FTFE base pointer */
mbed_official 146:f64d43ff0c18 6189 #define FTFE ((FTFE_Type *)FTFE_BASE)
mbed_official 146:f64d43ff0c18 6190 #define FTFE_BASE_PTR (FTFE)
mbed_official 146:f64d43ff0c18 6191 /** Array initializer of FTFE peripheral base pointers */
mbed_official 146:f64d43ff0c18 6192 #define FTFE_BASES { FTFE }
mbed_official 146:f64d43ff0c18 6193
mbed_official 146:f64d43ff0c18 6194 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6195 -- FTFE - Register accessor macros
mbed_official 146:f64d43ff0c18 6196 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 6197
mbed_official 146:f64d43ff0c18 6198 /*!
mbed_official 146:f64d43ff0c18 6199 * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
mbed_official 146:f64d43ff0c18 6200 * @{
mbed_official 146:f64d43ff0c18 6201 */
mbed_official 146:f64d43ff0c18 6202
mbed_official 146:f64d43ff0c18 6203
mbed_official 146:f64d43ff0c18 6204 /* FTFE - Register instance definitions */
mbed_official 146:f64d43ff0c18 6205 /* FTFE */
mbed_official 146:f64d43ff0c18 6206 #define FTFE_FSTAT FTFE_FSTAT_REG(FTFE)
mbed_official 146:f64d43ff0c18 6207 #define FTFE_FCNFG FTFE_FCNFG_REG(FTFE)
mbed_official 146:f64d43ff0c18 6208 #define FTFE_FSEC FTFE_FSEC_REG(FTFE)
mbed_official 146:f64d43ff0c18 6209 #define FTFE_FOPT FTFE_FOPT_REG(FTFE)
mbed_official 146:f64d43ff0c18 6210 #define FTFE_FCCOB3 FTFE_FCCOB3_REG(FTFE)
mbed_official 146:f64d43ff0c18 6211 #define FTFE_FCCOB2 FTFE_FCCOB2_REG(FTFE)
mbed_official 146:f64d43ff0c18 6212 #define FTFE_FCCOB1 FTFE_FCCOB1_REG(FTFE)
mbed_official 146:f64d43ff0c18 6213 #define FTFE_FCCOB0 FTFE_FCCOB0_REG(FTFE)
mbed_official 146:f64d43ff0c18 6214 #define FTFE_FCCOB7 FTFE_FCCOB7_REG(FTFE)
mbed_official 146:f64d43ff0c18 6215 #define FTFE_FCCOB6 FTFE_FCCOB6_REG(FTFE)
mbed_official 146:f64d43ff0c18 6216 #define FTFE_FCCOB5 FTFE_FCCOB5_REG(FTFE)
mbed_official 146:f64d43ff0c18 6217 #define FTFE_FCCOB4 FTFE_FCCOB4_REG(FTFE)
mbed_official 146:f64d43ff0c18 6218 #define FTFE_FCCOBB FTFE_FCCOBB_REG(FTFE)
mbed_official 146:f64d43ff0c18 6219 #define FTFE_FCCOBA FTFE_FCCOBA_REG(FTFE)
mbed_official 146:f64d43ff0c18 6220 #define FTFE_FCCOB9 FTFE_FCCOB9_REG(FTFE)
mbed_official 146:f64d43ff0c18 6221 #define FTFE_FCCOB8 FTFE_FCCOB8_REG(FTFE)
mbed_official 146:f64d43ff0c18 6222 #define FTFE_FPROT3 FTFE_FPROT3_REG(FTFE)
mbed_official 146:f64d43ff0c18 6223 #define FTFE_FPROT2 FTFE_FPROT2_REG(FTFE)
mbed_official 146:f64d43ff0c18 6224 #define FTFE_FPROT1 FTFE_FPROT1_REG(FTFE)
mbed_official 146:f64d43ff0c18 6225 #define FTFE_FPROT0 FTFE_FPROT0_REG(FTFE)
mbed_official 146:f64d43ff0c18 6226 #define FTFE_FEPROT FTFE_FEPROT_REG(FTFE)
mbed_official 146:f64d43ff0c18 6227 #define FTFE_FDPROT FTFE_FDPROT_REG(FTFE)
mbed_official 146:f64d43ff0c18 6228
mbed_official 146:f64d43ff0c18 6229 /*!
mbed_official 146:f64d43ff0c18 6230 * @}
mbed_official 146:f64d43ff0c18 6231 */ /* end of group FTFE_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 6232
mbed_official 146:f64d43ff0c18 6233
mbed_official 146:f64d43ff0c18 6234 /*!
mbed_official 146:f64d43ff0c18 6235 * @}
mbed_official 146:f64d43ff0c18 6236 */ /* end of group FTFE_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 6237
mbed_official 146:f64d43ff0c18 6238
mbed_official 146:f64d43ff0c18 6239 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6240 -- FTM Peripheral Access Layer
mbed_official 146:f64d43ff0c18 6241 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 6242
mbed_official 146:f64d43ff0c18 6243 /*!
mbed_official 146:f64d43ff0c18 6244 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
mbed_official 146:f64d43ff0c18 6245 * @{
mbed_official 146:f64d43ff0c18 6246 */
mbed_official 146:f64d43ff0c18 6247
mbed_official 146:f64d43ff0c18 6248 /** FTM - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 6249 typedef struct {
mbed_official 146:f64d43ff0c18 6250 __IO uint32_t SC; /**< Status And Control, offset: 0x0 */
mbed_official 146:f64d43ff0c18 6251 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
mbed_official 146:f64d43ff0c18 6252 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
mbed_official 146:f64d43ff0c18 6253 struct { /* offset: 0xC, array step: 0x8 */
mbed_official 146:f64d43ff0c18 6254 __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
mbed_official 146:f64d43ff0c18 6255 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
mbed_official 146:f64d43ff0c18 6256 } CONTROLS[8];
mbed_official 146:f64d43ff0c18 6257 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
mbed_official 146:f64d43ff0c18 6258 __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */
mbed_official 146:f64d43ff0c18 6259 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
mbed_official 146:f64d43ff0c18 6260 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
mbed_official 146:f64d43ff0c18 6261 __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */
mbed_official 146:f64d43ff0c18 6262 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
mbed_official 146:f64d43ff0c18 6263 __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */
mbed_official 146:f64d43ff0c18 6264 __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
mbed_official 146:f64d43ff0c18 6265 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
mbed_official 146:f64d43ff0c18 6266 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
mbed_official 146:f64d43ff0c18 6267 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
mbed_official 146:f64d43ff0c18 6268 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
mbed_official 146:f64d43ff0c18 6269 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
mbed_official 146:f64d43ff0c18 6270 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */
mbed_official 146:f64d43ff0c18 6271 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
mbed_official 146:f64d43ff0c18 6272 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
mbed_official 146:f64d43ff0c18 6273 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
mbed_official 146:f64d43ff0c18 6274 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
mbed_official 146:f64d43ff0c18 6275 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
mbed_official 146:f64d43ff0c18 6276 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
mbed_official 146:f64d43ff0c18 6277 } FTM_Type, *FTM_MemMapPtr;
mbed_official 146:f64d43ff0c18 6278
mbed_official 146:f64d43ff0c18 6279 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6280 -- FTM - Register accessor macros
mbed_official 146:f64d43ff0c18 6281 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 6282
mbed_official 146:f64d43ff0c18 6283 /*!
mbed_official 146:f64d43ff0c18 6284 * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
mbed_official 146:f64d43ff0c18 6285 * @{
mbed_official 146:f64d43ff0c18 6286 */
mbed_official 146:f64d43ff0c18 6287
mbed_official 146:f64d43ff0c18 6288
mbed_official 146:f64d43ff0c18 6289 /* FTM - Register accessors */
mbed_official 146:f64d43ff0c18 6290 #define FTM_SC_REG(base) ((base)->SC)
mbed_official 146:f64d43ff0c18 6291 #define FTM_CNT_REG(base) ((base)->CNT)
mbed_official 146:f64d43ff0c18 6292 #define FTM_MOD_REG(base) ((base)->MOD)
mbed_official 146:f64d43ff0c18 6293 #define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC)
mbed_official 146:f64d43ff0c18 6294 #define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV)
mbed_official 146:f64d43ff0c18 6295 #define FTM_CNTIN_REG(base) ((base)->CNTIN)
mbed_official 146:f64d43ff0c18 6296 #define FTM_STATUS_REG(base) ((base)->STATUS)
mbed_official 146:f64d43ff0c18 6297 #define FTM_MODE_REG(base) ((base)->MODE)
mbed_official 146:f64d43ff0c18 6298 #define FTM_SYNC_REG(base) ((base)->SYNC)
mbed_official 146:f64d43ff0c18 6299 #define FTM_OUTINIT_REG(base) ((base)->OUTINIT)
mbed_official 146:f64d43ff0c18 6300 #define FTM_OUTMASK_REG(base) ((base)->OUTMASK)
mbed_official 146:f64d43ff0c18 6301 #define FTM_COMBINE_REG(base) ((base)->COMBINE)
mbed_official 146:f64d43ff0c18 6302 #define FTM_DEADTIME_REG(base) ((base)->DEADTIME)
mbed_official 146:f64d43ff0c18 6303 #define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG)
mbed_official 146:f64d43ff0c18 6304 #define FTM_POL_REG(base) ((base)->POL)
mbed_official 146:f64d43ff0c18 6305 #define FTM_FMS_REG(base) ((base)->FMS)
mbed_official 146:f64d43ff0c18 6306 #define FTM_FILTER_REG(base) ((base)->FILTER)
mbed_official 146:f64d43ff0c18 6307 #define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL)
mbed_official 146:f64d43ff0c18 6308 #define FTM_QDCTRL_REG(base) ((base)->QDCTRL)
mbed_official 146:f64d43ff0c18 6309 #define FTM_CONF_REG(base) ((base)->CONF)
mbed_official 146:f64d43ff0c18 6310 #define FTM_FLTPOL_REG(base) ((base)->FLTPOL)
mbed_official 146:f64d43ff0c18 6311 #define FTM_SYNCONF_REG(base) ((base)->SYNCONF)
mbed_official 146:f64d43ff0c18 6312 #define FTM_INVCTRL_REG(base) ((base)->INVCTRL)
mbed_official 146:f64d43ff0c18 6313 #define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL)
mbed_official 146:f64d43ff0c18 6314 #define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD)
mbed_official 146:f64d43ff0c18 6315
mbed_official 146:f64d43ff0c18 6316 /*!
mbed_official 146:f64d43ff0c18 6317 * @}
mbed_official 146:f64d43ff0c18 6318 */ /* end of group FTM_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 6319
mbed_official 146:f64d43ff0c18 6320
mbed_official 146:f64d43ff0c18 6321 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6322 -- FTM Register Masks
mbed_official 146:f64d43ff0c18 6323 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 6324
mbed_official 146:f64d43ff0c18 6325 /*!
mbed_official 146:f64d43ff0c18 6326 * @addtogroup FTM_Register_Masks FTM Register Masks
mbed_official 146:f64d43ff0c18 6327 * @{
mbed_official 146:f64d43ff0c18 6328 */
mbed_official 146:f64d43ff0c18 6329
mbed_official 146:f64d43ff0c18 6330 /* SC Bit Fields */
mbed_official 146:f64d43ff0c18 6331 #define FTM_SC_PS_MASK 0x7u
mbed_official 146:f64d43ff0c18 6332 #define FTM_SC_PS_SHIFT 0
mbed_official 146:f64d43ff0c18 6333 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
mbed_official 146:f64d43ff0c18 6334 #define FTM_SC_CLKS_MASK 0x18u
mbed_official 146:f64d43ff0c18 6335 #define FTM_SC_CLKS_SHIFT 3
mbed_official 146:f64d43ff0c18 6336 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
mbed_official 146:f64d43ff0c18 6337 #define FTM_SC_CPWMS_MASK 0x20u
mbed_official 146:f64d43ff0c18 6338 #define FTM_SC_CPWMS_SHIFT 5
mbed_official 146:f64d43ff0c18 6339 #define FTM_SC_TOIE_MASK 0x40u
mbed_official 146:f64d43ff0c18 6340 #define FTM_SC_TOIE_SHIFT 6
mbed_official 146:f64d43ff0c18 6341 #define FTM_SC_TOF_MASK 0x80u
mbed_official 146:f64d43ff0c18 6342 #define FTM_SC_TOF_SHIFT 7
mbed_official 146:f64d43ff0c18 6343 /* CNT Bit Fields */
mbed_official 146:f64d43ff0c18 6344 #define FTM_CNT_COUNT_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 6345 #define FTM_CNT_COUNT_SHIFT 0
mbed_official 146:f64d43ff0c18 6346 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
mbed_official 146:f64d43ff0c18 6347 /* MOD Bit Fields */
mbed_official 146:f64d43ff0c18 6348 #define FTM_MOD_MOD_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 6349 #define FTM_MOD_MOD_SHIFT 0
mbed_official 146:f64d43ff0c18 6350 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
mbed_official 146:f64d43ff0c18 6351 /* CnSC Bit Fields */
mbed_official 146:f64d43ff0c18 6352 #define FTM_CnSC_DMA_MASK 0x1u
mbed_official 146:f64d43ff0c18 6353 #define FTM_CnSC_DMA_SHIFT 0
mbed_official 146:f64d43ff0c18 6354 #define FTM_CnSC_ELSA_MASK 0x4u
mbed_official 146:f64d43ff0c18 6355 #define FTM_CnSC_ELSA_SHIFT 2
mbed_official 146:f64d43ff0c18 6356 #define FTM_CnSC_ELSB_MASK 0x8u
mbed_official 146:f64d43ff0c18 6357 #define FTM_CnSC_ELSB_SHIFT 3
mbed_official 146:f64d43ff0c18 6358 #define FTM_CnSC_MSA_MASK 0x10u
mbed_official 146:f64d43ff0c18 6359 #define FTM_CnSC_MSA_SHIFT 4
mbed_official 146:f64d43ff0c18 6360 #define FTM_CnSC_MSB_MASK 0x20u
mbed_official 146:f64d43ff0c18 6361 #define FTM_CnSC_MSB_SHIFT 5
mbed_official 146:f64d43ff0c18 6362 #define FTM_CnSC_CHIE_MASK 0x40u
mbed_official 146:f64d43ff0c18 6363 #define FTM_CnSC_CHIE_SHIFT 6
mbed_official 146:f64d43ff0c18 6364 #define FTM_CnSC_CHF_MASK 0x80u
mbed_official 146:f64d43ff0c18 6365 #define FTM_CnSC_CHF_SHIFT 7
mbed_official 146:f64d43ff0c18 6366 /* CnV Bit Fields */
mbed_official 146:f64d43ff0c18 6367 #define FTM_CnV_VAL_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 6368 #define FTM_CnV_VAL_SHIFT 0
mbed_official 146:f64d43ff0c18 6369 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
mbed_official 146:f64d43ff0c18 6370 /* CNTIN Bit Fields */
mbed_official 146:f64d43ff0c18 6371 #define FTM_CNTIN_INIT_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 6372 #define FTM_CNTIN_INIT_SHIFT 0
mbed_official 146:f64d43ff0c18 6373 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
mbed_official 146:f64d43ff0c18 6374 /* STATUS Bit Fields */
mbed_official 146:f64d43ff0c18 6375 #define FTM_STATUS_CH0F_MASK 0x1u
mbed_official 146:f64d43ff0c18 6376 #define FTM_STATUS_CH0F_SHIFT 0
mbed_official 146:f64d43ff0c18 6377 #define FTM_STATUS_CH1F_MASK 0x2u
mbed_official 146:f64d43ff0c18 6378 #define FTM_STATUS_CH1F_SHIFT 1
mbed_official 146:f64d43ff0c18 6379 #define FTM_STATUS_CH2F_MASK 0x4u
mbed_official 146:f64d43ff0c18 6380 #define FTM_STATUS_CH2F_SHIFT 2
mbed_official 146:f64d43ff0c18 6381 #define FTM_STATUS_CH3F_MASK 0x8u
mbed_official 146:f64d43ff0c18 6382 #define FTM_STATUS_CH3F_SHIFT 3
mbed_official 146:f64d43ff0c18 6383 #define FTM_STATUS_CH4F_MASK 0x10u
mbed_official 146:f64d43ff0c18 6384 #define FTM_STATUS_CH4F_SHIFT 4
mbed_official 146:f64d43ff0c18 6385 #define FTM_STATUS_CH5F_MASK 0x20u
mbed_official 146:f64d43ff0c18 6386 #define FTM_STATUS_CH5F_SHIFT 5
mbed_official 146:f64d43ff0c18 6387 #define FTM_STATUS_CH6F_MASK 0x40u
mbed_official 146:f64d43ff0c18 6388 #define FTM_STATUS_CH6F_SHIFT 6
mbed_official 146:f64d43ff0c18 6389 #define FTM_STATUS_CH7F_MASK 0x80u
mbed_official 146:f64d43ff0c18 6390 #define FTM_STATUS_CH7F_SHIFT 7
mbed_official 146:f64d43ff0c18 6391 /* MODE Bit Fields */
mbed_official 146:f64d43ff0c18 6392 #define FTM_MODE_FTMEN_MASK 0x1u
mbed_official 146:f64d43ff0c18 6393 #define FTM_MODE_FTMEN_SHIFT 0
mbed_official 146:f64d43ff0c18 6394 #define FTM_MODE_INIT_MASK 0x2u
mbed_official 146:f64d43ff0c18 6395 #define FTM_MODE_INIT_SHIFT 1
mbed_official 146:f64d43ff0c18 6396 #define FTM_MODE_WPDIS_MASK 0x4u
mbed_official 146:f64d43ff0c18 6397 #define FTM_MODE_WPDIS_SHIFT 2
mbed_official 146:f64d43ff0c18 6398 #define FTM_MODE_PWMSYNC_MASK 0x8u
mbed_official 146:f64d43ff0c18 6399 #define FTM_MODE_PWMSYNC_SHIFT 3
mbed_official 146:f64d43ff0c18 6400 #define FTM_MODE_CAPTEST_MASK 0x10u
mbed_official 146:f64d43ff0c18 6401 #define FTM_MODE_CAPTEST_SHIFT 4
mbed_official 146:f64d43ff0c18 6402 #define FTM_MODE_FAULTM_MASK 0x60u
mbed_official 146:f64d43ff0c18 6403 #define FTM_MODE_FAULTM_SHIFT 5
mbed_official 146:f64d43ff0c18 6404 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
mbed_official 146:f64d43ff0c18 6405 #define FTM_MODE_FAULTIE_MASK 0x80u
mbed_official 146:f64d43ff0c18 6406 #define FTM_MODE_FAULTIE_SHIFT 7
mbed_official 146:f64d43ff0c18 6407 /* SYNC Bit Fields */
mbed_official 146:f64d43ff0c18 6408 #define FTM_SYNC_CNTMIN_MASK 0x1u
mbed_official 146:f64d43ff0c18 6409 #define FTM_SYNC_CNTMIN_SHIFT 0
mbed_official 146:f64d43ff0c18 6410 #define FTM_SYNC_CNTMAX_MASK 0x2u
mbed_official 146:f64d43ff0c18 6411 #define FTM_SYNC_CNTMAX_SHIFT 1
mbed_official 146:f64d43ff0c18 6412 #define FTM_SYNC_REINIT_MASK 0x4u
mbed_official 146:f64d43ff0c18 6413 #define FTM_SYNC_REINIT_SHIFT 2
mbed_official 146:f64d43ff0c18 6414 #define FTM_SYNC_SYNCHOM_MASK 0x8u
mbed_official 146:f64d43ff0c18 6415 #define FTM_SYNC_SYNCHOM_SHIFT 3
mbed_official 146:f64d43ff0c18 6416 #define FTM_SYNC_TRIG0_MASK 0x10u
mbed_official 146:f64d43ff0c18 6417 #define FTM_SYNC_TRIG0_SHIFT 4
mbed_official 146:f64d43ff0c18 6418 #define FTM_SYNC_TRIG1_MASK 0x20u
mbed_official 146:f64d43ff0c18 6419 #define FTM_SYNC_TRIG1_SHIFT 5
mbed_official 146:f64d43ff0c18 6420 #define FTM_SYNC_TRIG2_MASK 0x40u
mbed_official 146:f64d43ff0c18 6421 #define FTM_SYNC_TRIG2_SHIFT 6
mbed_official 146:f64d43ff0c18 6422 #define FTM_SYNC_SWSYNC_MASK 0x80u
mbed_official 146:f64d43ff0c18 6423 #define FTM_SYNC_SWSYNC_SHIFT 7
mbed_official 146:f64d43ff0c18 6424 /* OUTINIT Bit Fields */
mbed_official 146:f64d43ff0c18 6425 #define FTM_OUTINIT_CH0OI_MASK 0x1u
mbed_official 146:f64d43ff0c18 6426 #define FTM_OUTINIT_CH0OI_SHIFT 0
mbed_official 146:f64d43ff0c18 6427 #define FTM_OUTINIT_CH1OI_MASK 0x2u
mbed_official 146:f64d43ff0c18 6428 #define FTM_OUTINIT_CH1OI_SHIFT 1
mbed_official 146:f64d43ff0c18 6429 #define FTM_OUTINIT_CH2OI_MASK 0x4u
mbed_official 146:f64d43ff0c18 6430 #define FTM_OUTINIT_CH2OI_SHIFT 2
mbed_official 146:f64d43ff0c18 6431 #define FTM_OUTINIT_CH3OI_MASK 0x8u
mbed_official 146:f64d43ff0c18 6432 #define FTM_OUTINIT_CH3OI_SHIFT 3
mbed_official 146:f64d43ff0c18 6433 #define FTM_OUTINIT_CH4OI_MASK 0x10u
mbed_official 146:f64d43ff0c18 6434 #define FTM_OUTINIT_CH4OI_SHIFT 4
mbed_official 146:f64d43ff0c18 6435 #define FTM_OUTINIT_CH5OI_MASK 0x20u
mbed_official 146:f64d43ff0c18 6436 #define FTM_OUTINIT_CH5OI_SHIFT 5
mbed_official 146:f64d43ff0c18 6437 #define FTM_OUTINIT_CH6OI_MASK 0x40u
mbed_official 146:f64d43ff0c18 6438 #define FTM_OUTINIT_CH6OI_SHIFT 6
mbed_official 146:f64d43ff0c18 6439 #define FTM_OUTINIT_CH7OI_MASK 0x80u
mbed_official 146:f64d43ff0c18 6440 #define FTM_OUTINIT_CH7OI_SHIFT 7
mbed_official 146:f64d43ff0c18 6441 /* OUTMASK Bit Fields */
mbed_official 146:f64d43ff0c18 6442 #define FTM_OUTMASK_CH0OM_MASK 0x1u
mbed_official 146:f64d43ff0c18 6443 #define FTM_OUTMASK_CH0OM_SHIFT 0
mbed_official 146:f64d43ff0c18 6444 #define FTM_OUTMASK_CH1OM_MASK 0x2u
mbed_official 146:f64d43ff0c18 6445 #define FTM_OUTMASK_CH1OM_SHIFT 1
mbed_official 146:f64d43ff0c18 6446 #define FTM_OUTMASK_CH2OM_MASK 0x4u
mbed_official 146:f64d43ff0c18 6447 #define FTM_OUTMASK_CH2OM_SHIFT 2
mbed_official 146:f64d43ff0c18 6448 #define FTM_OUTMASK_CH3OM_MASK 0x8u
mbed_official 146:f64d43ff0c18 6449 #define FTM_OUTMASK_CH3OM_SHIFT 3
mbed_official 146:f64d43ff0c18 6450 #define FTM_OUTMASK_CH4OM_MASK 0x10u
mbed_official 146:f64d43ff0c18 6451 #define FTM_OUTMASK_CH4OM_SHIFT 4
mbed_official 146:f64d43ff0c18 6452 #define FTM_OUTMASK_CH5OM_MASK 0x20u
mbed_official 146:f64d43ff0c18 6453 #define FTM_OUTMASK_CH5OM_SHIFT 5
mbed_official 146:f64d43ff0c18 6454 #define FTM_OUTMASK_CH6OM_MASK 0x40u
mbed_official 146:f64d43ff0c18 6455 #define FTM_OUTMASK_CH6OM_SHIFT 6
mbed_official 146:f64d43ff0c18 6456 #define FTM_OUTMASK_CH7OM_MASK 0x80u
mbed_official 146:f64d43ff0c18 6457 #define FTM_OUTMASK_CH7OM_SHIFT 7
mbed_official 146:f64d43ff0c18 6458 /* COMBINE Bit Fields */
mbed_official 146:f64d43ff0c18 6459 #define FTM_COMBINE_COMBINE0_MASK 0x1u
mbed_official 146:f64d43ff0c18 6460 #define FTM_COMBINE_COMBINE0_SHIFT 0
mbed_official 146:f64d43ff0c18 6461 #define FTM_COMBINE_COMP0_MASK 0x2u
mbed_official 146:f64d43ff0c18 6462 #define FTM_COMBINE_COMP0_SHIFT 1
mbed_official 146:f64d43ff0c18 6463 #define FTM_COMBINE_DECAPEN0_MASK 0x4u
mbed_official 146:f64d43ff0c18 6464 #define FTM_COMBINE_DECAPEN0_SHIFT 2
mbed_official 146:f64d43ff0c18 6465 #define FTM_COMBINE_DECAP0_MASK 0x8u
mbed_official 146:f64d43ff0c18 6466 #define FTM_COMBINE_DECAP0_SHIFT 3
mbed_official 146:f64d43ff0c18 6467 #define FTM_COMBINE_DTEN0_MASK 0x10u
mbed_official 146:f64d43ff0c18 6468 #define FTM_COMBINE_DTEN0_SHIFT 4
mbed_official 146:f64d43ff0c18 6469 #define FTM_COMBINE_SYNCEN0_MASK 0x20u
mbed_official 146:f64d43ff0c18 6470 #define FTM_COMBINE_SYNCEN0_SHIFT 5
mbed_official 146:f64d43ff0c18 6471 #define FTM_COMBINE_FAULTEN0_MASK 0x40u
mbed_official 146:f64d43ff0c18 6472 #define FTM_COMBINE_FAULTEN0_SHIFT 6
mbed_official 146:f64d43ff0c18 6473 #define FTM_COMBINE_COMBINE1_MASK 0x100u
mbed_official 146:f64d43ff0c18 6474 #define FTM_COMBINE_COMBINE1_SHIFT 8
mbed_official 146:f64d43ff0c18 6475 #define FTM_COMBINE_COMP1_MASK 0x200u
mbed_official 146:f64d43ff0c18 6476 #define FTM_COMBINE_COMP1_SHIFT 9
mbed_official 146:f64d43ff0c18 6477 #define FTM_COMBINE_DECAPEN1_MASK 0x400u
mbed_official 146:f64d43ff0c18 6478 #define FTM_COMBINE_DECAPEN1_SHIFT 10
mbed_official 146:f64d43ff0c18 6479 #define FTM_COMBINE_DECAP1_MASK 0x800u
mbed_official 146:f64d43ff0c18 6480 #define FTM_COMBINE_DECAP1_SHIFT 11
mbed_official 146:f64d43ff0c18 6481 #define FTM_COMBINE_DTEN1_MASK 0x1000u
mbed_official 146:f64d43ff0c18 6482 #define FTM_COMBINE_DTEN1_SHIFT 12
mbed_official 146:f64d43ff0c18 6483 #define FTM_COMBINE_SYNCEN1_MASK 0x2000u
mbed_official 146:f64d43ff0c18 6484 #define FTM_COMBINE_SYNCEN1_SHIFT 13
mbed_official 146:f64d43ff0c18 6485 #define FTM_COMBINE_FAULTEN1_MASK 0x4000u
mbed_official 146:f64d43ff0c18 6486 #define FTM_COMBINE_FAULTEN1_SHIFT 14
mbed_official 146:f64d43ff0c18 6487 #define FTM_COMBINE_COMBINE2_MASK 0x10000u
mbed_official 146:f64d43ff0c18 6488 #define FTM_COMBINE_COMBINE2_SHIFT 16
mbed_official 146:f64d43ff0c18 6489 #define FTM_COMBINE_COMP2_MASK 0x20000u
mbed_official 146:f64d43ff0c18 6490 #define FTM_COMBINE_COMP2_SHIFT 17
mbed_official 146:f64d43ff0c18 6491 #define FTM_COMBINE_DECAPEN2_MASK 0x40000u
mbed_official 146:f64d43ff0c18 6492 #define FTM_COMBINE_DECAPEN2_SHIFT 18
mbed_official 146:f64d43ff0c18 6493 #define FTM_COMBINE_DECAP2_MASK 0x80000u
mbed_official 146:f64d43ff0c18 6494 #define FTM_COMBINE_DECAP2_SHIFT 19
mbed_official 146:f64d43ff0c18 6495 #define FTM_COMBINE_DTEN2_MASK 0x100000u
mbed_official 146:f64d43ff0c18 6496 #define FTM_COMBINE_DTEN2_SHIFT 20
mbed_official 146:f64d43ff0c18 6497 #define FTM_COMBINE_SYNCEN2_MASK 0x200000u
mbed_official 146:f64d43ff0c18 6498 #define FTM_COMBINE_SYNCEN2_SHIFT 21
mbed_official 146:f64d43ff0c18 6499 #define FTM_COMBINE_FAULTEN2_MASK 0x400000u
mbed_official 146:f64d43ff0c18 6500 #define FTM_COMBINE_FAULTEN2_SHIFT 22
mbed_official 146:f64d43ff0c18 6501 #define FTM_COMBINE_COMBINE3_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 6502 #define FTM_COMBINE_COMBINE3_SHIFT 24
mbed_official 146:f64d43ff0c18 6503 #define FTM_COMBINE_COMP3_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 6504 #define FTM_COMBINE_COMP3_SHIFT 25
mbed_official 146:f64d43ff0c18 6505 #define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
mbed_official 146:f64d43ff0c18 6506 #define FTM_COMBINE_DECAPEN3_SHIFT 26
mbed_official 146:f64d43ff0c18 6507 #define FTM_COMBINE_DECAP3_MASK 0x8000000u
mbed_official 146:f64d43ff0c18 6508 #define FTM_COMBINE_DECAP3_SHIFT 27
mbed_official 146:f64d43ff0c18 6509 #define FTM_COMBINE_DTEN3_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 6510 #define FTM_COMBINE_DTEN3_SHIFT 28
mbed_official 146:f64d43ff0c18 6511 #define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
mbed_official 146:f64d43ff0c18 6512 #define FTM_COMBINE_SYNCEN3_SHIFT 29
mbed_official 146:f64d43ff0c18 6513 #define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 6514 #define FTM_COMBINE_FAULTEN3_SHIFT 30
mbed_official 146:f64d43ff0c18 6515 /* DEADTIME Bit Fields */
mbed_official 146:f64d43ff0c18 6516 #define FTM_DEADTIME_DTVAL_MASK 0x3Fu
mbed_official 146:f64d43ff0c18 6517 #define FTM_DEADTIME_DTVAL_SHIFT 0
mbed_official 146:f64d43ff0c18 6518 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
mbed_official 146:f64d43ff0c18 6519 #define FTM_DEADTIME_DTPS_MASK 0xC0u
mbed_official 146:f64d43ff0c18 6520 #define FTM_DEADTIME_DTPS_SHIFT 6
mbed_official 146:f64d43ff0c18 6521 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
mbed_official 146:f64d43ff0c18 6522 /* EXTTRIG Bit Fields */
mbed_official 146:f64d43ff0c18 6523 #define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
mbed_official 146:f64d43ff0c18 6524 #define FTM_EXTTRIG_CH2TRIG_SHIFT 0
mbed_official 146:f64d43ff0c18 6525 #define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
mbed_official 146:f64d43ff0c18 6526 #define FTM_EXTTRIG_CH3TRIG_SHIFT 1
mbed_official 146:f64d43ff0c18 6527 #define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
mbed_official 146:f64d43ff0c18 6528 #define FTM_EXTTRIG_CH4TRIG_SHIFT 2
mbed_official 146:f64d43ff0c18 6529 #define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
mbed_official 146:f64d43ff0c18 6530 #define FTM_EXTTRIG_CH5TRIG_SHIFT 3
mbed_official 146:f64d43ff0c18 6531 #define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
mbed_official 146:f64d43ff0c18 6532 #define FTM_EXTTRIG_CH0TRIG_SHIFT 4
mbed_official 146:f64d43ff0c18 6533 #define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
mbed_official 146:f64d43ff0c18 6534 #define FTM_EXTTRIG_CH1TRIG_SHIFT 5
mbed_official 146:f64d43ff0c18 6535 #define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
mbed_official 146:f64d43ff0c18 6536 #define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
mbed_official 146:f64d43ff0c18 6537 #define FTM_EXTTRIG_TRIGF_MASK 0x80u
mbed_official 146:f64d43ff0c18 6538 #define FTM_EXTTRIG_TRIGF_SHIFT 7
mbed_official 146:f64d43ff0c18 6539 /* POL Bit Fields */
mbed_official 146:f64d43ff0c18 6540 #define FTM_POL_POL0_MASK 0x1u
mbed_official 146:f64d43ff0c18 6541 #define FTM_POL_POL0_SHIFT 0
mbed_official 146:f64d43ff0c18 6542 #define FTM_POL_POL1_MASK 0x2u
mbed_official 146:f64d43ff0c18 6543 #define FTM_POL_POL1_SHIFT 1
mbed_official 146:f64d43ff0c18 6544 #define FTM_POL_POL2_MASK 0x4u
mbed_official 146:f64d43ff0c18 6545 #define FTM_POL_POL2_SHIFT 2
mbed_official 146:f64d43ff0c18 6546 #define FTM_POL_POL3_MASK 0x8u
mbed_official 146:f64d43ff0c18 6547 #define FTM_POL_POL3_SHIFT 3
mbed_official 146:f64d43ff0c18 6548 #define FTM_POL_POL4_MASK 0x10u
mbed_official 146:f64d43ff0c18 6549 #define FTM_POL_POL4_SHIFT 4
mbed_official 146:f64d43ff0c18 6550 #define FTM_POL_POL5_MASK 0x20u
mbed_official 146:f64d43ff0c18 6551 #define FTM_POL_POL5_SHIFT 5
mbed_official 146:f64d43ff0c18 6552 #define FTM_POL_POL6_MASK 0x40u
mbed_official 146:f64d43ff0c18 6553 #define FTM_POL_POL6_SHIFT 6
mbed_official 146:f64d43ff0c18 6554 #define FTM_POL_POL7_MASK 0x80u
mbed_official 146:f64d43ff0c18 6555 #define FTM_POL_POL7_SHIFT 7
mbed_official 146:f64d43ff0c18 6556 /* FMS Bit Fields */
mbed_official 146:f64d43ff0c18 6557 #define FTM_FMS_FAULTF0_MASK 0x1u
mbed_official 146:f64d43ff0c18 6558 #define FTM_FMS_FAULTF0_SHIFT 0
mbed_official 146:f64d43ff0c18 6559 #define FTM_FMS_FAULTF1_MASK 0x2u
mbed_official 146:f64d43ff0c18 6560 #define FTM_FMS_FAULTF1_SHIFT 1
mbed_official 146:f64d43ff0c18 6561 #define FTM_FMS_FAULTF2_MASK 0x4u
mbed_official 146:f64d43ff0c18 6562 #define FTM_FMS_FAULTF2_SHIFT 2
mbed_official 146:f64d43ff0c18 6563 #define FTM_FMS_FAULTF3_MASK 0x8u
mbed_official 146:f64d43ff0c18 6564 #define FTM_FMS_FAULTF3_SHIFT 3
mbed_official 146:f64d43ff0c18 6565 #define FTM_FMS_FAULTIN_MASK 0x20u
mbed_official 146:f64d43ff0c18 6566 #define FTM_FMS_FAULTIN_SHIFT 5
mbed_official 146:f64d43ff0c18 6567 #define FTM_FMS_WPEN_MASK 0x40u
mbed_official 146:f64d43ff0c18 6568 #define FTM_FMS_WPEN_SHIFT 6
mbed_official 146:f64d43ff0c18 6569 #define FTM_FMS_FAULTF_MASK 0x80u
mbed_official 146:f64d43ff0c18 6570 #define FTM_FMS_FAULTF_SHIFT 7
mbed_official 146:f64d43ff0c18 6571 /* FILTER Bit Fields */
mbed_official 146:f64d43ff0c18 6572 #define FTM_FILTER_CH0FVAL_MASK 0xFu
mbed_official 146:f64d43ff0c18 6573 #define FTM_FILTER_CH0FVAL_SHIFT 0
mbed_official 146:f64d43ff0c18 6574 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
mbed_official 146:f64d43ff0c18 6575 #define FTM_FILTER_CH1FVAL_MASK 0xF0u
mbed_official 146:f64d43ff0c18 6576 #define FTM_FILTER_CH1FVAL_SHIFT 4
mbed_official 146:f64d43ff0c18 6577 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
mbed_official 146:f64d43ff0c18 6578 #define FTM_FILTER_CH2FVAL_MASK 0xF00u
mbed_official 146:f64d43ff0c18 6579 #define FTM_FILTER_CH2FVAL_SHIFT 8
mbed_official 146:f64d43ff0c18 6580 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
mbed_official 146:f64d43ff0c18 6581 #define FTM_FILTER_CH3FVAL_MASK 0xF000u
mbed_official 146:f64d43ff0c18 6582 #define FTM_FILTER_CH3FVAL_SHIFT 12
mbed_official 146:f64d43ff0c18 6583 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
mbed_official 146:f64d43ff0c18 6584 /* FLTCTRL Bit Fields */
mbed_official 146:f64d43ff0c18 6585 #define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
mbed_official 146:f64d43ff0c18 6586 #define FTM_FLTCTRL_FAULT0EN_SHIFT 0
mbed_official 146:f64d43ff0c18 6587 #define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
mbed_official 146:f64d43ff0c18 6588 #define FTM_FLTCTRL_FAULT1EN_SHIFT 1
mbed_official 146:f64d43ff0c18 6589 #define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
mbed_official 146:f64d43ff0c18 6590 #define FTM_FLTCTRL_FAULT2EN_SHIFT 2
mbed_official 146:f64d43ff0c18 6591 #define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
mbed_official 146:f64d43ff0c18 6592 #define FTM_FLTCTRL_FAULT3EN_SHIFT 3
mbed_official 146:f64d43ff0c18 6593 #define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
mbed_official 146:f64d43ff0c18 6594 #define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
mbed_official 146:f64d43ff0c18 6595 #define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
mbed_official 146:f64d43ff0c18 6596 #define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
mbed_official 146:f64d43ff0c18 6597 #define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
mbed_official 146:f64d43ff0c18 6598 #define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
mbed_official 146:f64d43ff0c18 6599 #define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
mbed_official 146:f64d43ff0c18 6600 #define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
mbed_official 146:f64d43ff0c18 6601 #define FTM_FLTCTRL_FFVAL_MASK 0xF00u
mbed_official 146:f64d43ff0c18 6602 #define FTM_FLTCTRL_FFVAL_SHIFT 8
mbed_official 146:f64d43ff0c18 6603 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
mbed_official 146:f64d43ff0c18 6604 /* QDCTRL Bit Fields */
mbed_official 146:f64d43ff0c18 6605 #define FTM_QDCTRL_QUADEN_MASK 0x1u
mbed_official 146:f64d43ff0c18 6606 #define FTM_QDCTRL_QUADEN_SHIFT 0
mbed_official 146:f64d43ff0c18 6607 #define FTM_QDCTRL_TOFDIR_MASK 0x2u
mbed_official 146:f64d43ff0c18 6608 #define FTM_QDCTRL_TOFDIR_SHIFT 1
mbed_official 146:f64d43ff0c18 6609 #define FTM_QDCTRL_QUADIR_MASK 0x4u
mbed_official 146:f64d43ff0c18 6610 #define FTM_QDCTRL_QUADIR_SHIFT 2
mbed_official 146:f64d43ff0c18 6611 #define FTM_QDCTRL_QUADMODE_MASK 0x8u
mbed_official 146:f64d43ff0c18 6612 #define FTM_QDCTRL_QUADMODE_SHIFT 3
mbed_official 146:f64d43ff0c18 6613 #define FTM_QDCTRL_PHBPOL_MASK 0x10u
mbed_official 146:f64d43ff0c18 6614 #define FTM_QDCTRL_PHBPOL_SHIFT 4
mbed_official 146:f64d43ff0c18 6615 #define FTM_QDCTRL_PHAPOL_MASK 0x20u
mbed_official 146:f64d43ff0c18 6616 #define FTM_QDCTRL_PHAPOL_SHIFT 5
mbed_official 146:f64d43ff0c18 6617 #define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
mbed_official 146:f64d43ff0c18 6618 #define FTM_QDCTRL_PHBFLTREN_SHIFT 6
mbed_official 146:f64d43ff0c18 6619 #define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
mbed_official 146:f64d43ff0c18 6620 #define FTM_QDCTRL_PHAFLTREN_SHIFT 7
mbed_official 146:f64d43ff0c18 6621 /* CONF Bit Fields */
mbed_official 146:f64d43ff0c18 6622 #define FTM_CONF_NUMTOF_MASK 0x1Fu
mbed_official 146:f64d43ff0c18 6623 #define FTM_CONF_NUMTOF_SHIFT 0
mbed_official 146:f64d43ff0c18 6624 #define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
mbed_official 146:f64d43ff0c18 6625 #define FTM_CONF_BDMMODE_MASK 0xC0u
mbed_official 146:f64d43ff0c18 6626 #define FTM_CONF_BDMMODE_SHIFT 6
mbed_official 146:f64d43ff0c18 6627 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
mbed_official 146:f64d43ff0c18 6628 #define FTM_CONF_GTBEEN_MASK 0x200u
mbed_official 146:f64d43ff0c18 6629 #define FTM_CONF_GTBEEN_SHIFT 9
mbed_official 146:f64d43ff0c18 6630 #define FTM_CONF_GTBEOUT_MASK 0x400u
mbed_official 146:f64d43ff0c18 6631 #define FTM_CONF_GTBEOUT_SHIFT 10
mbed_official 146:f64d43ff0c18 6632 /* FLTPOL Bit Fields */
mbed_official 146:f64d43ff0c18 6633 #define FTM_FLTPOL_FLT0POL_MASK 0x1u
mbed_official 146:f64d43ff0c18 6634 #define FTM_FLTPOL_FLT0POL_SHIFT 0
mbed_official 146:f64d43ff0c18 6635 #define FTM_FLTPOL_FLT1POL_MASK 0x2u
mbed_official 146:f64d43ff0c18 6636 #define FTM_FLTPOL_FLT1POL_SHIFT 1
mbed_official 146:f64d43ff0c18 6637 #define FTM_FLTPOL_FLT2POL_MASK 0x4u
mbed_official 146:f64d43ff0c18 6638 #define FTM_FLTPOL_FLT2POL_SHIFT 2
mbed_official 146:f64d43ff0c18 6639 #define FTM_FLTPOL_FLT3POL_MASK 0x8u
mbed_official 146:f64d43ff0c18 6640 #define FTM_FLTPOL_FLT3POL_SHIFT 3
mbed_official 146:f64d43ff0c18 6641 /* SYNCONF Bit Fields */
mbed_official 146:f64d43ff0c18 6642 #define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
mbed_official 146:f64d43ff0c18 6643 #define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
mbed_official 146:f64d43ff0c18 6644 #define FTM_SYNCONF_CNTINC_MASK 0x4u
mbed_official 146:f64d43ff0c18 6645 #define FTM_SYNCONF_CNTINC_SHIFT 2
mbed_official 146:f64d43ff0c18 6646 #define FTM_SYNCONF_INVC_MASK 0x10u
mbed_official 146:f64d43ff0c18 6647 #define FTM_SYNCONF_INVC_SHIFT 4
mbed_official 146:f64d43ff0c18 6648 #define FTM_SYNCONF_SWOC_MASK 0x20u
mbed_official 146:f64d43ff0c18 6649 #define FTM_SYNCONF_SWOC_SHIFT 5
mbed_official 146:f64d43ff0c18 6650 #define FTM_SYNCONF_SYNCMODE_MASK 0x80u
mbed_official 146:f64d43ff0c18 6651 #define FTM_SYNCONF_SYNCMODE_SHIFT 7
mbed_official 146:f64d43ff0c18 6652 #define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
mbed_official 146:f64d43ff0c18 6653 #define FTM_SYNCONF_SWRSTCNT_SHIFT 8
mbed_official 146:f64d43ff0c18 6654 #define FTM_SYNCONF_SWWRBUF_MASK 0x200u
mbed_official 146:f64d43ff0c18 6655 #define FTM_SYNCONF_SWWRBUF_SHIFT 9
mbed_official 146:f64d43ff0c18 6656 #define FTM_SYNCONF_SWOM_MASK 0x400u
mbed_official 146:f64d43ff0c18 6657 #define FTM_SYNCONF_SWOM_SHIFT 10
mbed_official 146:f64d43ff0c18 6658 #define FTM_SYNCONF_SWINVC_MASK 0x800u
mbed_official 146:f64d43ff0c18 6659 #define FTM_SYNCONF_SWINVC_SHIFT 11
mbed_official 146:f64d43ff0c18 6660 #define FTM_SYNCONF_SWSOC_MASK 0x1000u
mbed_official 146:f64d43ff0c18 6661 #define FTM_SYNCONF_SWSOC_SHIFT 12
mbed_official 146:f64d43ff0c18 6662 #define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
mbed_official 146:f64d43ff0c18 6663 #define FTM_SYNCONF_HWRSTCNT_SHIFT 16
mbed_official 146:f64d43ff0c18 6664 #define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
mbed_official 146:f64d43ff0c18 6665 #define FTM_SYNCONF_HWWRBUF_SHIFT 17
mbed_official 146:f64d43ff0c18 6666 #define FTM_SYNCONF_HWOM_MASK 0x40000u
mbed_official 146:f64d43ff0c18 6667 #define FTM_SYNCONF_HWOM_SHIFT 18
mbed_official 146:f64d43ff0c18 6668 #define FTM_SYNCONF_HWINVC_MASK 0x80000u
mbed_official 146:f64d43ff0c18 6669 #define FTM_SYNCONF_HWINVC_SHIFT 19
mbed_official 146:f64d43ff0c18 6670 #define FTM_SYNCONF_HWSOC_MASK 0x100000u
mbed_official 146:f64d43ff0c18 6671 #define FTM_SYNCONF_HWSOC_SHIFT 20
mbed_official 146:f64d43ff0c18 6672 /* INVCTRL Bit Fields */
mbed_official 146:f64d43ff0c18 6673 #define FTM_INVCTRL_INV0EN_MASK 0x1u
mbed_official 146:f64d43ff0c18 6674 #define FTM_INVCTRL_INV0EN_SHIFT 0
mbed_official 146:f64d43ff0c18 6675 #define FTM_INVCTRL_INV1EN_MASK 0x2u
mbed_official 146:f64d43ff0c18 6676 #define FTM_INVCTRL_INV1EN_SHIFT 1
mbed_official 146:f64d43ff0c18 6677 #define FTM_INVCTRL_INV2EN_MASK 0x4u
mbed_official 146:f64d43ff0c18 6678 #define FTM_INVCTRL_INV2EN_SHIFT 2
mbed_official 146:f64d43ff0c18 6679 #define FTM_INVCTRL_INV3EN_MASK 0x8u
mbed_official 146:f64d43ff0c18 6680 #define FTM_INVCTRL_INV3EN_SHIFT 3
mbed_official 146:f64d43ff0c18 6681 /* SWOCTRL Bit Fields */
mbed_official 146:f64d43ff0c18 6682 #define FTM_SWOCTRL_CH0OC_MASK 0x1u
mbed_official 146:f64d43ff0c18 6683 #define FTM_SWOCTRL_CH0OC_SHIFT 0
mbed_official 146:f64d43ff0c18 6684 #define FTM_SWOCTRL_CH1OC_MASK 0x2u
mbed_official 146:f64d43ff0c18 6685 #define FTM_SWOCTRL_CH1OC_SHIFT 1
mbed_official 146:f64d43ff0c18 6686 #define FTM_SWOCTRL_CH2OC_MASK 0x4u
mbed_official 146:f64d43ff0c18 6687 #define FTM_SWOCTRL_CH2OC_SHIFT 2
mbed_official 146:f64d43ff0c18 6688 #define FTM_SWOCTRL_CH3OC_MASK 0x8u
mbed_official 146:f64d43ff0c18 6689 #define FTM_SWOCTRL_CH3OC_SHIFT 3
mbed_official 146:f64d43ff0c18 6690 #define FTM_SWOCTRL_CH4OC_MASK 0x10u
mbed_official 146:f64d43ff0c18 6691 #define FTM_SWOCTRL_CH4OC_SHIFT 4
mbed_official 146:f64d43ff0c18 6692 #define FTM_SWOCTRL_CH5OC_MASK 0x20u
mbed_official 146:f64d43ff0c18 6693 #define FTM_SWOCTRL_CH5OC_SHIFT 5
mbed_official 146:f64d43ff0c18 6694 #define FTM_SWOCTRL_CH6OC_MASK 0x40u
mbed_official 146:f64d43ff0c18 6695 #define FTM_SWOCTRL_CH6OC_SHIFT 6
mbed_official 146:f64d43ff0c18 6696 #define FTM_SWOCTRL_CH7OC_MASK 0x80u
mbed_official 146:f64d43ff0c18 6697 #define FTM_SWOCTRL_CH7OC_SHIFT 7
mbed_official 146:f64d43ff0c18 6698 #define FTM_SWOCTRL_CH0OCV_MASK 0x100u
mbed_official 146:f64d43ff0c18 6699 #define FTM_SWOCTRL_CH0OCV_SHIFT 8
mbed_official 146:f64d43ff0c18 6700 #define FTM_SWOCTRL_CH1OCV_MASK 0x200u
mbed_official 146:f64d43ff0c18 6701 #define FTM_SWOCTRL_CH1OCV_SHIFT 9
mbed_official 146:f64d43ff0c18 6702 #define FTM_SWOCTRL_CH2OCV_MASK 0x400u
mbed_official 146:f64d43ff0c18 6703 #define FTM_SWOCTRL_CH2OCV_SHIFT 10
mbed_official 146:f64d43ff0c18 6704 #define FTM_SWOCTRL_CH3OCV_MASK 0x800u
mbed_official 146:f64d43ff0c18 6705 #define FTM_SWOCTRL_CH3OCV_SHIFT 11
mbed_official 146:f64d43ff0c18 6706 #define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
mbed_official 146:f64d43ff0c18 6707 #define FTM_SWOCTRL_CH4OCV_SHIFT 12
mbed_official 146:f64d43ff0c18 6708 #define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
mbed_official 146:f64d43ff0c18 6709 #define FTM_SWOCTRL_CH5OCV_SHIFT 13
mbed_official 146:f64d43ff0c18 6710 #define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
mbed_official 146:f64d43ff0c18 6711 #define FTM_SWOCTRL_CH6OCV_SHIFT 14
mbed_official 146:f64d43ff0c18 6712 #define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
mbed_official 146:f64d43ff0c18 6713 #define FTM_SWOCTRL_CH7OCV_SHIFT 15
mbed_official 146:f64d43ff0c18 6714 /* PWMLOAD Bit Fields */
mbed_official 146:f64d43ff0c18 6715 #define FTM_PWMLOAD_CH0SEL_MASK 0x1u
mbed_official 146:f64d43ff0c18 6716 #define FTM_PWMLOAD_CH0SEL_SHIFT 0
mbed_official 146:f64d43ff0c18 6717 #define FTM_PWMLOAD_CH1SEL_MASK 0x2u
mbed_official 146:f64d43ff0c18 6718 #define FTM_PWMLOAD_CH1SEL_SHIFT 1
mbed_official 146:f64d43ff0c18 6719 #define FTM_PWMLOAD_CH2SEL_MASK 0x4u
mbed_official 146:f64d43ff0c18 6720 #define FTM_PWMLOAD_CH2SEL_SHIFT 2
mbed_official 146:f64d43ff0c18 6721 #define FTM_PWMLOAD_CH3SEL_MASK 0x8u
mbed_official 146:f64d43ff0c18 6722 #define FTM_PWMLOAD_CH3SEL_SHIFT 3
mbed_official 146:f64d43ff0c18 6723 #define FTM_PWMLOAD_CH4SEL_MASK 0x10u
mbed_official 146:f64d43ff0c18 6724 #define FTM_PWMLOAD_CH4SEL_SHIFT 4
mbed_official 146:f64d43ff0c18 6725 #define FTM_PWMLOAD_CH5SEL_MASK 0x20u
mbed_official 146:f64d43ff0c18 6726 #define FTM_PWMLOAD_CH5SEL_SHIFT 5
mbed_official 146:f64d43ff0c18 6727 #define FTM_PWMLOAD_CH6SEL_MASK 0x40u
mbed_official 146:f64d43ff0c18 6728 #define FTM_PWMLOAD_CH6SEL_SHIFT 6
mbed_official 146:f64d43ff0c18 6729 #define FTM_PWMLOAD_CH7SEL_MASK 0x80u
mbed_official 146:f64d43ff0c18 6730 #define FTM_PWMLOAD_CH7SEL_SHIFT 7
mbed_official 146:f64d43ff0c18 6731 #define FTM_PWMLOAD_LDOK_MASK 0x200u
mbed_official 146:f64d43ff0c18 6732 #define FTM_PWMLOAD_LDOK_SHIFT 9
mbed_official 146:f64d43ff0c18 6733
mbed_official 146:f64d43ff0c18 6734 /*!
mbed_official 146:f64d43ff0c18 6735 * @}
mbed_official 146:f64d43ff0c18 6736 */ /* end of group FTM_Register_Masks */
mbed_official 146:f64d43ff0c18 6737
mbed_official 146:f64d43ff0c18 6738
mbed_official 146:f64d43ff0c18 6739 /* FTM - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 6740 /** Peripheral FTM0 base address */
mbed_official 146:f64d43ff0c18 6741 #define FTM0_BASE (0x40038000u)
mbed_official 146:f64d43ff0c18 6742 /** Peripheral FTM0 base pointer */
mbed_official 146:f64d43ff0c18 6743 #define FTM0 ((FTM_Type *)FTM0_BASE)
mbed_official 146:f64d43ff0c18 6744 #define FTM0_BASE_PTR (FTM0)
mbed_official 146:f64d43ff0c18 6745 /** Peripheral FTM1 base address */
mbed_official 146:f64d43ff0c18 6746 #define FTM1_BASE (0x40039000u)
mbed_official 146:f64d43ff0c18 6747 /** Peripheral FTM1 base pointer */
mbed_official 146:f64d43ff0c18 6748 #define FTM1 ((FTM_Type *)FTM1_BASE)
mbed_official 146:f64d43ff0c18 6749 #define FTM1_BASE_PTR (FTM1)
mbed_official 146:f64d43ff0c18 6750 /** Peripheral FTM2 base address */
mbed_official 146:f64d43ff0c18 6751 #define FTM2_BASE (0x4003A000u)
mbed_official 146:f64d43ff0c18 6752 /** Peripheral FTM2 base pointer */
mbed_official 146:f64d43ff0c18 6753 #define FTM2 ((FTM_Type *)FTM2_BASE)
mbed_official 146:f64d43ff0c18 6754 #define FTM2_BASE_PTR (FTM2)
mbed_official 146:f64d43ff0c18 6755 /** Peripheral FTM3 base address */
mbed_official 146:f64d43ff0c18 6756 #define FTM3_BASE (0x400B9000u)
mbed_official 146:f64d43ff0c18 6757 /** Peripheral FTM3 base pointer */
mbed_official 146:f64d43ff0c18 6758 #define FTM3 ((FTM_Type *)FTM3_BASE)
mbed_official 146:f64d43ff0c18 6759 #define FTM3_BASE_PTR (FTM3)
mbed_official 146:f64d43ff0c18 6760 /** Array initializer of FTM peripheral base pointers */
mbed_official 146:f64d43ff0c18 6761 #define FTM_BASES { FTM0, FTM1, FTM2, FTM3 }
mbed_official 146:f64d43ff0c18 6762
mbed_official 146:f64d43ff0c18 6763 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6764 -- FTM - Register accessor macros
mbed_official 146:f64d43ff0c18 6765 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 6766
mbed_official 146:f64d43ff0c18 6767 /*!
mbed_official 146:f64d43ff0c18 6768 * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
mbed_official 146:f64d43ff0c18 6769 * @{
mbed_official 146:f64d43ff0c18 6770 */
mbed_official 146:f64d43ff0c18 6771
mbed_official 146:f64d43ff0c18 6772
mbed_official 146:f64d43ff0c18 6773 /* FTM - Register instance definitions */
mbed_official 146:f64d43ff0c18 6774 /* FTM0 */
mbed_official 146:f64d43ff0c18 6775 #define FTM0_SC FTM_SC_REG(FTM0)
mbed_official 146:f64d43ff0c18 6776 #define FTM0_CNT FTM_CNT_REG(FTM0)
mbed_official 146:f64d43ff0c18 6777 #define FTM0_MOD FTM_MOD_REG(FTM0)
mbed_official 146:f64d43ff0c18 6778 #define FTM0_C0SC FTM_CnSC_REG(FTM0,0)
mbed_official 146:f64d43ff0c18 6779 #define FTM0_C0V FTM_CnV_REG(FTM0,0)
mbed_official 146:f64d43ff0c18 6780 #define FTM0_C1SC FTM_CnSC_REG(FTM0,1)
mbed_official 146:f64d43ff0c18 6781 #define FTM0_C1V FTM_CnV_REG(FTM0,1)
mbed_official 146:f64d43ff0c18 6782 #define FTM0_C2SC FTM_CnSC_REG(FTM0,2)
mbed_official 146:f64d43ff0c18 6783 #define FTM0_C2V FTM_CnV_REG(FTM0,2)
mbed_official 146:f64d43ff0c18 6784 #define FTM0_C3SC FTM_CnSC_REG(FTM0,3)
mbed_official 146:f64d43ff0c18 6785 #define FTM0_C3V FTM_CnV_REG(FTM0,3)
mbed_official 146:f64d43ff0c18 6786 #define FTM0_C4SC FTM_CnSC_REG(FTM0,4)
mbed_official 146:f64d43ff0c18 6787 #define FTM0_C4V FTM_CnV_REG(FTM0,4)
mbed_official 146:f64d43ff0c18 6788 #define FTM0_C5SC FTM_CnSC_REG(FTM0,5)
mbed_official 146:f64d43ff0c18 6789 #define FTM0_C5V FTM_CnV_REG(FTM0,5)
mbed_official 146:f64d43ff0c18 6790 #define FTM0_C6SC FTM_CnSC_REG(FTM0,6)
mbed_official 146:f64d43ff0c18 6791 #define FTM0_C6V FTM_CnV_REG(FTM0,6)
mbed_official 146:f64d43ff0c18 6792 #define FTM0_C7SC FTM_CnSC_REG(FTM0,7)
mbed_official 146:f64d43ff0c18 6793 #define FTM0_C7V FTM_CnV_REG(FTM0,7)
mbed_official 146:f64d43ff0c18 6794 #define FTM0_CNTIN FTM_CNTIN_REG(FTM0)
mbed_official 146:f64d43ff0c18 6795 #define FTM0_STATUS FTM_STATUS_REG(FTM0)
mbed_official 146:f64d43ff0c18 6796 #define FTM0_MODE FTM_MODE_REG(FTM0)
mbed_official 146:f64d43ff0c18 6797 #define FTM0_SYNC FTM_SYNC_REG(FTM0)
mbed_official 146:f64d43ff0c18 6798 #define FTM0_OUTINIT FTM_OUTINIT_REG(FTM0)
mbed_official 146:f64d43ff0c18 6799 #define FTM0_OUTMASK FTM_OUTMASK_REG(FTM0)
mbed_official 146:f64d43ff0c18 6800 #define FTM0_COMBINE FTM_COMBINE_REG(FTM0)
mbed_official 146:f64d43ff0c18 6801 #define FTM0_DEADTIME FTM_DEADTIME_REG(FTM0)
mbed_official 146:f64d43ff0c18 6802 #define FTM0_EXTTRIG FTM_EXTTRIG_REG(FTM0)
mbed_official 146:f64d43ff0c18 6803 #define FTM0_POL FTM_POL_REG(FTM0)
mbed_official 146:f64d43ff0c18 6804 #define FTM0_FMS FTM_FMS_REG(FTM0)
mbed_official 146:f64d43ff0c18 6805 #define FTM0_FILTER FTM_FILTER_REG(FTM0)
mbed_official 146:f64d43ff0c18 6806 #define FTM0_FLTCTRL FTM_FLTCTRL_REG(FTM0)
mbed_official 146:f64d43ff0c18 6807 #define FTM0_QDCTRL FTM_QDCTRL_REG(FTM0)
mbed_official 146:f64d43ff0c18 6808 #define FTM0_CONF FTM_CONF_REG(FTM0)
mbed_official 146:f64d43ff0c18 6809 #define FTM0_FLTPOL FTM_FLTPOL_REG(FTM0)
mbed_official 146:f64d43ff0c18 6810 #define FTM0_SYNCONF FTM_SYNCONF_REG(FTM0)
mbed_official 146:f64d43ff0c18 6811 #define FTM0_INVCTRL FTM_INVCTRL_REG(FTM0)
mbed_official 146:f64d43ff0c18 6812 #define FTM0_SWOCTRL FTM_SWOCTRL_REG(FTM0)
mbed_official 146:f64d43ff0c18 6813 #define FTM0_PWMLOAD FTM_PWMLOAD_REG(FTM0)
mbed_official 146:f64d43ff0c18 6814 /* FTM1 */
mbed_official 146:f64d43ff0c18 6815 #define FTM1_SC FTM_SC_REG(FTM1)
mbed_official 146:f64d43ff0c18 6816 #define FTM1_CNT FTM_CNT_REG(FTM1)
mbed_official 146:f64d43ff0c18 6817 #define FTM1_MOD FTM_MOD_REG(FTM1)
mbed_official 146:f64d43ff0c18 6818 #define FTM1_C0SC FTM_CnSC_REG(FTM1,0)
mbed_official 146:f64d43ff0c18 6819 #define FTM1_C0V FTM_CnV_REG(FTM1,0)
mbed_official 146:f64d43ff0c18 6820 #define FTM1_C1SC FTM_CnSC_REG(FTM1,1)
mbed_official 146:f64d43ff0c18 6821 #define FTM1_C1V FTM_CnV_REG(FTM1,1)
mbed_official 146:f64d43ff0c18 6822 #define FTM1_CNTIN FTM_CNTIN_REG(FTM1)
mbed_official 146:f64d43ff0c18 6823 #define FTM1_STATUS FTM_STATUS_REG(FTM1)
mbed_official 146:f64d43ff0c18 6824 #define FTM1_MODE FTM_MODE_REG(FTM1)
mbed_official 146:f64d43ff0c18 6825 #define FTM1_SYNC FTM_SYNC_REG(FTM1)
mbed_official 146:f64d43ff0c18 6826 #define FTM1_OUTINIT FTM_OUTINIT_REG(FTM1)
mbed_official 146:f64d43ff0c18 6827 #define FTM1_OUTMASK FTM_OUTMASK_REG(FTM1)
mbed_official 146:f64d43ff0c18 6828 #define FTM1_COMBINE FTM_COMBINE_REG(FTM1)
mbed_official 146:f64d43ff0c18 6829 #define FTM1_DEADTIME FTM_DEADTIME_REG(FTM1)
mbed_official 146:f64d43ff0c18 6830 #define FTM1_EXTTRIG FTM_EXTTRIG_REG(FTM1)
mbed_official 146:f64d43ff0c18 6831 #define FTM1_POL FTM_POL_REG(FTM1)
mbed_official 146:f64d43ff0c18 6832 #define FTM1_FMS FTM_FMS_REG(FTM1)
mbed_official 146:f64d43ff0c18 6833 #define FTM1_FILTER FTM_FILTER_REG(FTM1)
mbed_official 146:f64d43ff0c18 6834 #define FTM1_FLTCTRL FTM_FLTCTRL_REG(FTM1)
mbed_official 146:f64d43ff0c18 6835 #define FTM1_QDCTRL FTM_QDCTRL_REG(FTM1)
mbed_official 146:f64d43ff0c18 6836 #define FTM1_CONF FTM_CONF_REG(FTM1)
mbed_official 146:f64d43ff0c18 6837 #define FTM1_FLTPOL FTM_FLTPOL_REG(FTM1)
mbed_official 146:f64d43ff0c18 6838 #define FTM1_SYNCONF FTM_SYNCONF_REG(FTM1)
mbed_official 146:f64d43ff0c18 6839 #define FTM1_INVCTRL FTM_INVCTRL_REG(FTM1)
mbed_official 146:f64d43ff0c18 6840 #define FTM1_SWOCTRL FTM_SWOCTRL_REG(FTM1)
mbed_official 146:f64d43ff0c18 6841 #define FTM1_PWMLOAD FTM_PWMLOAD_REG(FTM1)
mbed_official 146:f64d43ff0c18 6842 /* FTM2 */
mbed_official 146:f64d43ff0c18 6843 #define FTM2_SC FTM_SC_REG(FTM2)
mbed_official 146:f64d43ff0c18 6844 #define FTM2_CNT FTM_CNT_REG(FTM2)
mbed_official 146:f64d43ff0c18 6845 #define FTM2_MOD FTM_MOD_REG(FTM2)
mbed_official 146:f64d43ff0c18 6846 #define FTM2_C0SC FTM_CnSC_REG(FTM2,0)
mbed_official 146:f64d43ff0c18 6847 #define FTM2_C0V FTM_CnV_REG(FTM2,0)
mbed_official 146:f64d43ff0c18 6848 #define FTM2_C1SC FTM_CnSC_REG(FTM2,1)
mbed_official 146:f64d43ff0c18 6849 #define FTM2_C1V FTM_CnV_REG(FTM2,1)
mbed_official 146:f64d43ff0c18 6850 #define FTM2_CNTIN FTM_CNTIN_REG(FTM2)
mbed_official 146:f64d43ff0c18 6851 #define FTM2_STATUS FTM_STATUS_REG(FTM2)
mbed_official 146:f64d43ff0c18 6852 #define FTM2_MODE FTM_MODE_REG(FTM2)
mbed_official 146:f64d43ff0c18 6853 #define FTM2_SYNC FTM_SYNC_REG(FTM2)
mbed_official 146:f64d43ff0c18 6854 #define FTM2_OUTINIT FTM_OUTINIT_REG(FTM2)
mbed_official 146:f64d43ff0c18 6855 #define FTM2_OUTMASK FTM_OUTMASK_REG(FTM2)
mbed_official 146:f64d43ff0c18 6856 #define FTM2_COMBINE FTM_COMBINE_REG(FTM2)
mbed_official 146:f64d43ff0c18 6857 #define FTM2_DEADTIME FTM_DEADTIME_REG(FTM2)
mbed_official 146:f64d43ff0c18 6858 #define FTM2_EXTTRIG FTM_EXTTRIG_REG(FTM2)
mbed_official 146:f64d43ff0c18 6859 #define FTM2_POL FTM_POL_REG(FTM2)
mbed_official 146:f64d43ff0c18 6860 #define FTM2_FMS FTM_FMS_REG(FTM2)
mbed_official 146:f64d43ff0c18 6861 #define FTM2_FILTER FTM_FILTER_REG(FTM2)
mbed_official 146:f64d43ff0c18 6862 #define FTM2_FLTCTRL FTM_FLTCTRL_REG(FTM2)
mbed_official 146:f64d43ff0c18 6863 #define FTM2_QDCTRL FTM_QDCTRL_REG(FTM2)
mbed_official 146:f64d43ff0c18 6864 #define FTM2_CONF FTM_CONF_REG(FTM2)
mbed_official 146:f64d43ff0c18 6865 #define FTM2_FLTPOL FTM_FLTPOL_REG(FTM2)
mbed_official 146:f64d43ff0c18 6866 #define FTM2_SYNCONF FTM_SYNCONF_REG(FTM2)
mbed_official 146:f64d43ff0c18 6867 #define FTM2_INVCTRL FTM_INVCTRL_REG(FTM2)
mbed_official 146:f64d43ff0c18 6868 #define FTM2_SWOCTRL FTM_SWOCTRL_REG(FTM2)
mbed_official 146:f64d43ff0c18 6869 #define FTM2_PWMLOAD FTM_PWMLOAD_REG(FTM2)
mbed_official 146:f64d43ff0c18 6870 /* FTM3 */
mbed_official 146:f64d43ff0c18 6871 #define FTM3_SC FTM_SC_REG(FTM3)
mbed_official 146:f64d43ff0c18 6872 #define FTM3_CNT FTM_CNT_REG(FTM3)
mbed_official 146:f64d43ff0c18 6873 #define FTM3_MOD FTM_MOD_REG(FTM3)
mbed_official 146:f64d43ff0c18 6874 #define FTM3_C0SC FTM_CnSC_REG(FTM3,0)
mbed_official 146:f64d43ff0c18 6875 #define FTM3_C0V FTM_CnV_REG(FTM3,0)
mbed_official 146:f64d43ff0c18 6876 #define FTM3_C1SC FTM_CnSC_REG(FTM3,1)
mbed_official 146:f64d43ff0c18 6877 #define FTM3_C1V FTM_CnV_REG(FTM3,1)
mbed_official 146:f64d43ff0c18 6878 #define FTM3_C2SC FTM_CnSC_REG(FTM3,2)
mbed_official 146:f64d43ff0c18 6879 #define FTM3_C2V FTM_CnV_REG(FTM3,2)
mbed_official 146:f64d43ff0c18 6880 #define FTM3_C3SC FTM_CnSC_REG(FTM3,3)
mbed_official 146:f64d43ff0c18 6881 #define FTM3_C3V FTM_CnV_REG(FTM3,3)
mbed_official 146:f64d43ff0c18 6882 #define FTM3_C4SC FTM_CnSC_REG(FTM3,4)
mbed_official 146:f64d43ff0c18 6883 #define FTM3_C4V FTM_CnV_REG(FTM3,4)
mbed_official 146:f64d43ff0c18 6884 #define FTM3_C5SC FTM_CnSC_REG(FTM3,5)
mbed_official 146:f64d43ff0c18 6885 #define FTM3_C5V FTM_CnV_REG(FTM3,5)
mbed_official 146:f64d43ff0c18 6886 #define FTM3_C6SC FTM_CnSC_REG(FTM3,6)
mbed_official 146:f64d43ff0c18 6887 #define FTM3_C6V FTM_CnV_REG(FTM3,6)
mbed_official 146:f64d43ff0c18 6888 #define FTM3_C7SC FTM_CnSC_REG(FTM3,7)
mbed_official 146:f64d43ff0c18 6889 #define FTM3_C7V FTM_CnV_REG(FTM3,7)
mbed_official 146:f64d43ff0c18 6890 #define FTM3_CNTIN FTM_CNTIN_REG(FTM3)
mbed_official 146:f64d43ff0c18 6891 #define FTM3_STATUS FTM_STATUS_REG(FTM3)
mbed_official 146:f64d43ff0c18 6892 #define FTM3_MODE FTM_MODE_REG(FTM3)
mbed_official 146:f64d43ff0c18 6893 #define FTM3_SYNC FTM_SYNC_REG(FTM3)
mbed_official 146:f64d43ff0c18 6894 #define FTM3_OUTINIT FTM_OUTINIT_REG(FTM3)
mbed_official 146:f64d43ff0c18 6895 #define FTM3_OUTMASK FTM_OUTMASK_REG(FTM3)
mbed_official 146:f64d43ff0c18 6896 #define FTM3_COMBINE FTM_COMBINE_REG(FTM3)
mbed_official 146:f64d43ff0c18 6897 #define FTM3_DEADTIME FTM_DEADTIME_REG(FTM3)
mbed_official 146:f64d43ff0c18 6898 #define FTM3_EXTTRIG FTM_EXTTRIG_REG(FTM3)
mbed_official 146:f64d43ff0c18 6899 #define FTM3_POL FTM_POL_REG(FTM3)
mbed_official 146:f64d43ff0c18 6900 #define FTM3_FMS FTM_FMS_REG(FTM3)
mbed_official 146:f64d43ff0c18 6901 #define FTM3_FILTER FTM_FILTER_REG(FTM3)
mbed_official 146:f64d43ff0c18 6902 #define FTM3_FLTCTRL FTM_FLTCTRL_REG(FTM3)
mbed_official 146:f64d43ff0c18 6903 #define FTM3_QDCTRL FTM_QDCTRL_REG(FTM3)
mbed_official 146:f64d43ff0c18 6904 #define FTM3_CONF FTM_CONF_REG(FTM3)
mbed_official 146:f64d43ff0c18 6905 #define FTM3_FLTPOL FTM_FLTPOL_REG(FTM3)
mbed_official 146:f64d43ff0c18 6906 #define FTM3_SYNCONF FTM_SYNCONF_REG(FTM3)
mbed_official 146:f64d43ff0c18 6907 #define FTM3_INVCTRL FTM_INVCTRL_REG(FTM3)
mbed_official 146:f64d43ff0c18 6908 #define FTM3_SWOCTRL FTM_SWOCTRL_REG(FTM3)
mbed_official 146:f64d43ff0c18 6909 #define FTM3_PWMLOAD FTM_PWMLOAD_REG(FTM3)
mbed_official 146:f64d43ff0c18 6910
mbed_official 146:f64d43ff0c18 6911 /* FTM - Register array accessors */
mbed_official 146:f64d43ff0c18 6912 #define FTM0_CnSC(index) FTM_CnSC_REG(FTM0,index)
mbed_official 146:f64d43ff0c18 6913 #define FTM1_CnSC(index) FTM_CnSC_REG(FTM1,index)
mbed_official 146:f64d43ff0c18 6914 #define FTM2_CnSC(index) FTM_CnSC_REG(FTM2,index)
mbed_official 146:f64d43ff0c18 6915 #define FTM3_CnSC(index) FTM_CnSC_REG(FTM3,index)
mbed_official 146:f64d43ff0c18 6916 #define FTM0_CnV(index) FTM_CnV_REG(FTM0,index)
mbed_official 146:f64d43ff0c18 6917 #define FTM1_CnV(index) FTM_CnV_REG(FTM1,index)
mbed_official 146:f64d43ff0c18 6918 #define FTM2_CnV(index) FTM_CnV_REG(FTM2,index)
mbed_official 146:f64d43ff0c18 6919 #define FTM3_CnV(index) FTM_CnV_REG(FTM3,index)
mbed_official 146:f64d43ff0c18 6920
mbed_official 146:f64d43ff0c18 6921 /*!
mbed_official 146:f64d43ff0c18 6922 * @}
mbed_official 146:f64d43ff0c18 6923 */ /* end of group FTM_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 6924
mbed_official 146:f64d43ff0c18 6925
mbed_official 146:f64d43ff0c18 6926 /*!
mbed_official 146:f64d43ff0c18 6927 * @}
mbed_official 146:f64d43ff0c18 6928 */ /* end of group FTM_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 6929
mbed_official 146:f64d43ff0c18 6930
mbed_official 146:f64d43ff0c18 6931 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6932 -- GPIO Peripheral Access Layer
mbed_official 146:f64d43ff0c18 6933 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 6934
mbed_official 146:f64d43ff0c18 6935 /*!
mbed_official 146:f64d43ff0c18 6936 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
mbed_official 146:f64d43ff0c18 6937 * @{
mbed_official 146:f64d43ff0c18 6938 */
mbed_official 146:f64d43ff0c18 6939
mbed_official 146:f64d43ff0c18 6940 /** GPIO - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 6941 typedef struct {
mbed_official 146:f64d43ff0c18 6942 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
mbed_official 146:f64d43ff0c18 6943 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
mbed_official 146:f64d43ff0c18 6944 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
mbed_official 146:f64d43ff0c18 6945 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
mbed_official 146:f64d43ff0c18 6946 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
mbed_official 146:f64d43ff0c18 6947 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
mbed_official 146:f64d43ff0c18 6948 } GPIO_Type, *GPIO_MemMapPtr;
mbed_official 146:f64d43ff0c18 6949
mbed_official 146:f64d43ff0c18 6950 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6951 -- GPIO - Register accessor macros
mbed_official 146:f64d43ff0c18 6952 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 6953
mbed_official 146:f64d43ff0c18 6954 /*!
mbed_official 146:f64d43ff0c18 6955 * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
mbed_official 146:f64d43ff0c18 6956 * @{
mbed_official 146:f64d43ff0c18 6957 */
mbed_official 146:f64d43ff0c18 6958
mbed_official 146:f64d43ff0c18 6959
mbed_official 146:f64d43ff0c18 6960 /* GPIO - Register accessors */
mbed_official 146:f64d43ff0c18 6961 #define GPIO_PDOR_REG(base) ((base)->PDOR)
mbed_official 146:f64d43ff0c18 6962 #define GPIO_PSOR_REG(base) ((base)->PSOR)
mbed_official 146:f64d43ff0c18 6963 #define GPIO_PCOR_REG(base) ((base)->PCOR)
mbed_official 146:f64d43ff0c18 6964 #define GPIO_PTOR_REG(base) ((base)->PTOR)
mbed_official 146:f64d43ff0c18 6965 #define GPIO_PDIR_REG(base) ((base)->PDIR)
mbed_official 146:f64d43ff0c18 6966 #define GPIO_PDDR_REG(base) ((base)->PDDR)
mbed_official 146:f64d43ff0c18 6967
mbed_official 146:f64d43ff0c18 6968 /*!
mbed_official 146:f64d43ff0c18 6969 * @}
mbed_official 146:f64d43ff0c18 6970 */ /* end of group GPIO_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 6971
mbed_official 146:f64d43ff0c18 6972
mbed_official 146:f64d43ff0c18 6973 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6974 -- GPIO Register Masks
mbed_official 146:f64d43ff0c18 6975 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 6976
mbed_official 146:f64d43ff0c18 6977 /*!
mbed_official 146:f64d43ff0c18 6978 * @addtogroup GPIO_Register_Masks GPIO Register Masks
mbed_official 146:f64d43ff0c18 6979 * @{
mbed_official 146:f64d43ff0c18 6980 */
mbed_official 146:f64d43ff0c18 6981
mbed_official 146:f64d43ff0c18 6982 /* PDOR Bit Fields */
mbed_official 146:f64d43ff0c18 6983 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 6984 #define GPIO_PDOR_PDO_SHIFT 0
mbed_official 146:f64d43ff0c18 6985 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
mbed_official 146:f64d43ff0c18 6986 /* PSOR Bit Fields */
mbed_official 146:f64d43ff0c18 6987 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 6988 #define GPIO_PSOR_PTSO_SHIFT 0
mbed_official 146:f64d43ff0c18 6989 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
mbed_official 146:f64d43ff0c18 6990 /* PCOR Bit Fields */
mbed_official 146:f64d43ff0c18 6991 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 6992 #define GPIO_PCOR_PTCO_SHIFT 0
mbed_official 146:f64d43ff0c18 6993 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
mbed_official 146:f64d43ff0c18 6994 /* PTOR Bit Fields */
mbed_official 146:f64d43ff0c18 6995 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 6996 #define GPIO_PTOR_PTTO_SHIFT 0
mbed_official 146:f64d43ff0c18 6997 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
mbed_official 146:f64d43ff0c18 6998 /* PDIR Bit Fields */
mbed_official 146:f64d43ff0c18 6999 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 7000 #define GPIO_PDIR_PDI_SHIFT 0
mbed_official 146:f64d43ff0c18 7001 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
mbed_official 146:f64d43ff0c18 7002 /* PDDR Bit Fields */
mbed_official 146:f64d43ff0c18 7003 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 7004 #define GPIO_PDDR_PDD_SHIFT 0
mbed_official 146:f64d43ff0c18 7005 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
mbed_official 146:f64d43ff0c18 7006
mbed_official 146:f64d43ff0c18 7007 /*!
mbed_official 146:f64d43ff0c18 7008 * @}
mbed_official 146:f64d43ff0c18 7009 */ /* end of group GPIO_Register_Masks */
mbed_official 146:f64d43ff0c18 7010
mbed_official 146:f64d43ff0c18 7011
mbed_official 146:f64d43ff0c18 7012 /* GPIO - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 7013 /** Peripheral PTA base address */
mbed_official 146:f64d43ff0c18 7014 #define PTA_BASE (0x400FF000u)
mbed_official 146:f64d43ff0c18 7015 /** Peripheral PTA base pointer */
mbed_official 146:f64d43ff0c18 7016 #define PTA ((GPIO_Type *)PTA_BASE)
mbed_official 146:f64d43ff0c18 7017 #define PTA_BASE_PTR (PTA)
mbed_official 146:f64d43ff0c18 7018 /** Peripheral PTB base address */
mbed_official 146:f64d43ff0c18 7019 #define PTB_BASE (0x400FF040u)
mbed_official 146:f64d43ff0c18 7020 /** Peripheral PTB base pointer */
mbed_official 146:f64d43ff0c18 7021 #define PTB ((GPIO_Type *)PTB_BASE)
mbed_official 146:f64d43ff0c18 7022 #define PTB_BASE_PTR (PTB)
mbed_official 146:f64d43ff0c18 7023 /** Peripheral PTC base address */
mbed_official 146:f64d43ff0c18 7024 #define PTC_BASE (0x400FF080u)
mbed_official 146:f64d43ff0c18 7025 /** Peripheral PTC base pointer */
mbed_official 146:f64d43ff0c18 7026 #define PTC ((GPIO_Type *)PTC_BASE)
mbed_official 146:f64d43ff0c18 7027 #define PTC_BASE_PTR (PTC)
mbed_official 146:f64d43ff0c18 7028 /** Peripheral PTD base address */
mbed_official 146:f64d43ff0c18 7029 #define PTD_BASE (0x400FF0C0u)
mbed_official 146:f64d43ff0c18 7030 /** Peripheral PTD base pointer */
mbed_official 146:f64d43ff0c18 7031 #define PTD ((GPIO_Type *)PTD_BASE)
mbed_official 146:f64d43ff0c18 7032 #define PTD_BASE_PTR (PTD)
mbed_official 146:f64d43ff0c18 7033 /** Peripheral PTE base address */
mbed_official 146:f64d43ff0c18 7034 #define PTE_BASE (0x400FF100u)
mbed_official 146:f64d43ff0c18 7035 /** Peripheral PTE base pointer */
mbed_official 146:f64d43ff0c18 7036 #define PTE ((GPIO_Type *)PTE_BASE)
mbed_official 146:f64d43ff0c18 7037 #define PTE_BASE_PTR (PTE)
mbed_official 146:f64d43ff0c18 7038 /** Array initializer of GPIO peripheral base pointers */
mbed_official 146:f64d43ff0c18 7039 #define GPIO_BASES { PTA, PTB, PTC, PTD, PTE }
mbed_official 146:f64d43ff0c18 7040
mbed_official 146:f64d43ff0c18 7041 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 7042 -- GPIO - Register accessor macros
mbed_official 146:f64d43ff0c18 7043 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 7044
mbed_official 146:f64d43ff0c18 7045 /*!
mbed_official 146:f64d43ff0c18 7046 * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
mbed_official 146:f64d43ff0c18 7047 * @{
mbed_official 146:f64d43ff0c18 7048 */
mbed_official 146:f64d43ff0c18 7049
mbed_official 146:f64d43ff0c18 7050
mbed_official 146:f64d43ff0c18 7051 /* GPIO - Register instance definitions */
mbed_official 146:f64d43ff0c18 7052 /* PTA */
mbed_official 146:f64d43ff0c18 7053 #define GPIOA_PDOR GPIO_PDOR_REG(PTA)
mbed_official 146:f64d43ff0c18 7054 #define GPIOA_PSOR GPIO_PSOR_REG(PTA)
mbed_official 146:f64d43ff0c18 7055 #define GPIOA_PCOR GPIO_PCOR_REG(PTA)
mbed_official 146:f64d43ff0c18 7056 #define GPIOA_PTOR GPIO_PTOR_REG(PTA)
mbed_official 146:f64d43ff0c18 7057 #define GPIOA_PDIR GPIO_PDIR_REG(PTA)
mbed_official 146:f64d43ff0c18 7058 #define GPIOA_PDDR GPIO_PDDR_REG(PTA)
mbed_official 146:f64d43ff0c18 7059 /* PTB */
mbed_official 146:f64d43ff0c18 7060 #define GPIOB_PDOR GPIO_PDOR_REG(PTB)
mbed_official 146:f64d43ff0c18 7061 #define GPIOB_PSOR GPIO_PSOR_REG(PTB)
mbed_official 146:f64d43ff0c18 7062 #define GPIOB_PCOR GPIO_PCOR_REG(PTB)
mbed_official 146:f64d43ff0c18 7063 #define GPIOB_PTOR GPIO_PTOR_REG(PTB)
mbed_official 146:f64d43ff0c18 7064 #define GPIOB_PDIR GPIO_PDIR_REG(PTB)
mbed_official 146:f64d43ff0c18 7065 #define GPIOB_PDDR GPIO_PDDR_REG(PTB)
mbed_official 146:f64d43ff0c18 7066 /* PTC */
mbed_official 146:f64d43ff0c18 7067 #define GPIOC_PDOR GPIO_PDOR_REG(PTC)
mbed_official 146:f64d43ff0c18 7068 #define GPIOC_PSOR GPIO_PSOR_REG(PTC)
mbed_official 146:f64d43ff0c18 7069 #define GPIOC_PCOR GPIO_PCOR_REG(PTC)
mbed_official 146:f64d43ff0c18 7070 #define GPIOC_PTOR GPIO_PTOR_REG(PTC)
mbed_official 146:f64d43ff0c18 7071 #define GPIOC_PDIR GPIO_PDIR_REG(PTC)
mbed_official 146:f64d43ff0c18 7072 #define GPIOC_PDDR GPIO_PDDR_REG(PTC)
mbed_official 146:f64d43ff0c18 7073 /* PTD */
mbed_official 146:f64d43ff0c18 7074 #define GPIOD_PDOR GPIO_PDOR_REG(PTD)
mbed_official 146:f64d43ff0c18 7075 #define GPIOD_PSOR GPIO_PSOR_REG(PTD)
mbed_official 146:f64d43ff0c18 7076 #define GPIOD_PCOR GPIO_PCOR_REG(PTD)
mbed_official 146:f64d43ff0c18 7077 #define GPIOD_PTOR GPIO_PTOR_REG(PTD)
mbed_official 146:f64d43ff0c18 7078 #define GPIOD_PDIR GPIO_PDIR_REG(PTD)
mbed_official 146:f64d43ff0c18 7079 #define GPIOD_PDDR GPIO_PDDR_REG(PTD)
mbed_official 146:f64d43ff0c18 7080 /* PTE */
mbed_official 146:f64d43ff0c18 7081 #define GPIOE_PDOR GPIO_PDOR_REG(PTE)
mbed_official 146:f64d43ff0c18 7082 #define GPIOE_PSOR GPIO_PSOR_REG(PTE)
mbed_official 146:f64d43ff0c18 7083 #define GPIOE_PCOR GPIO_PCOR_REG(PTE)
mbed_official 146:f64d43ff0c18 7084 #define GPIOE_PTOR GPIO_PTOR_REG(PTE)
mbed_official 146:f64d43ff0c18 7085 #define GPIOE_PDIR GPIO_PDIR_REG(PTE)
mbed_official 146:f64d43ff0c18 7086 #define GPIOE_PDDR GPIO_PDDR_REG(PTE)
mbed_official 146:f64d43ff0c18 7087
mbed_official 146:f64d43ff0c18 7088 /*!
mbed_official 146:f64d43ff0c18 7089 * @}
mbed_official 146:f64d43ff0c18 7090 */ /* end of group GPIO_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 7091
mbed_official 146:f64d43ff0c18 7092
mbed_official 146:f64d43ff0c18 7093 /*!
mbed_official 146:f64d43ff0c18 7094 * @}
mbed_official 146:f64d43ff0c18 7095 */ /* end of group GPIO_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 7096
mbed_official 146:f64d43ff0c18 7097
mbed_official 146:f64d43ff0c18 7098 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 7099 -- I2C Peripheral Access Layer
mbed_official 146:f64d43ff0c18 7100 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 7101
mbed_official 146:f64d43ff0c18 7102 /*!
mbed_official 146:f64d43ff0c18 7103 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
mbed_official 146:f64d43ff0c18 7104 * @{
mbed_official 146:f64d43ff0c18 7105 */
mbed_official 146:f64d43ff0c18 7106
mbed_official 146:f64d43ff0c18 7107 /** I2C - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 7108 typedef struct {
mbed_official 146:f64d43ff0c18 7109 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
mbed_official 146:f64d43ff0c18 7110 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
mbed_official 146:f64d43ff0c18 7111 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
mbed_official 146:f64d43ff0c18 7112 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
mbed_official 146:f64d43ff0c18 7113 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
mbed_official 146:f64d43ff0c18 7114 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
mbed_official 146:f64d43ff0c18 7115 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
mbed_official 146:f64d43ff0c18 7116 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
mbed_official 146:f64d43ff0c18 7117 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
mbed_official 146:f64d43ff0c18 7118 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
mbed_official 146:f64d43ff0c18 7119 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
mbed_official 146:f64d43ff0c18 7120 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
mbed_official 146:f64d43ff0c18 7121 } I2C_Type, *I2C_MemMapPtr;
mbed_official 146:f64d43ff0c18 7122
mbed_official 146:f64d43ff0c18 7123 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 7124 -- I2C - Register accessor macros
mbed_official 146:f64d43ff0c18 7125 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 7126
mbed_official 146:f64d43ff0c18 7127 /*!
mbed_official 146:f64d43ff0c18 7128 * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
mbed_official 146:f64d43ff0c18 7129 * @{
mbed_official 146:f64d43ff0c18 7130 */
mbed_official 146:f64d43ff0c18 7131
mbed_official 146:f64d43ff0c18 7132
mbed_official 146:f64d43ff0c18 7133 /* I2C - Register accessors */
mbed_official 146:f64d43ff0c18 7134 #define I2C_A1_REG(base) ((base)->A1)
mbed_official 146:f64d43ff0c18 7135 #define I2C_F_REG(base) ((base)->F)
mbed_official 146:f64d43ff0c18 7136 #define I2C_C1_REG(base) ((base)->C1)
mbed_official 146:f64d43ff0c18 7137 #define I2C_S_REG(base) ((base)->S)
mbed_official 146:f64d43ff0c18 7138 #define I2C_D_REG(base) ((base)->D)
mbed_official 146:f64d43ff0c18 7139 #define I2C_C2_REG(base) ((base)->C2)
mbed_official 146:f64d43ff0c18 7140 #define I2C_FLT_REG(base) ((base)->FLT)
mbed_official 146:f64d43ff0c18 7141 #define I2C_RA_REG(base) ((base)->RA)
mbed_official 146:f64d43ff0c18 7142 #define I2C_SMB_REG(base) ((base)->SMB)
mbed_official 146:f64d43ff0c18 7143 #define I2C_A2_REG(base) ((base)->A2)
mbed_official 146:f64d43ff0c18 7144 #define I2C_SLTH_REG(base) ((base)->SLTH)
mbed_official 146:f64d43ff0c18 7145 #define I2C_SLTL_REG(base) ((base)->SLTL)
mbed_official 146:f64d43ff0c18 7146
mbed_official 146:f64d43ff0c18 7147 /*!
mbed_official 146:f64d43ff0c18 7148 * @}
mbed_official 146:f64d43ff0c18 7149 */ /* end of group I2C_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 7150
mbed_official 146:f64d43ff0c18 7151
mbed_official 146:f64d43ff0c18 7152 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 7153 -- I2C Register Masks
mbed_official 146:f64d43ff0c18 7154 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 7155
mbed_official 146:f64d43ff0c18 7156 /*!
mbed_official 146:f64d43ff0c18 7157 * @addtogroup I2C_Register_Masks I2C Register Masks
mbed_official 146:f64d43ff0c18 7158 * @{
mbed_official 146:f64d43ff0c18 7159 */
mbed_official 146:f64d43ff0c18 7160
mbed_official 146:f64d43ff0c18 7161 /* A1 Bit Fields */
mbed_official 146:f64d43ff0c18 7162 #define I2C_A1_AD_MASK 0xFEu
mbed_official 146:f64d43ff0c18 7163 #define I2C_A1_AD_SHIFT 1
mbed_official 146:f64d43ff0c18 7164 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
mbed_official 146:f64d43ff0c18 7165 /* F Bit Fields */
mbed_official 146:f64d43ff0c18 7166 #define I2C_F_ICR_MASK 0x3Fu
mbed_official 146:f64d43ff0c18 7167 #define I2C_F_ICR_SHIFT 0
mbed_official 146:f64d43ff0c18 7168 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
mbed_official 146:f64d43ff0c18 7169 #define I2C_F_MULT_MASK 0xC0u
mbed_official 146:f64d43ff0c18 7170 #define I2C_F_MULT_SHIFT 6
mbed_official 146:f64d43ff0c18 7171 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
mbed_official 146:f64d43ff0c18 7172 /* C1 Bit Fields */
mbed_official 146:f64d43ff0c18 7173 #define I2C_C1_DMAEN_MASK 0x1u
mbed_official 146:f64d43ff0c18 7174 #define I2C_C1_DMAEN_SHIFT 0
mbed_official 146:f64d43ff0c18 7175 #define I2C_C1_WUEN_MASK 0x2u
mbed_official 146:f64d43ff0c18 7176 #define I2C_C1_WUEN_SHIFT 1
mbed_official 146:f64d43ff0c18 7177 #define I2C_C1_RSTA_MASK 0x4u
mbed_official 146:f64d43ff0c18 7178 #define I2C_C1_RSTA_SHIFT 2
mbed_official 146:f64d43ff0c18 7179 #define I2C_C1_TXAK_MASK 0x8u
mbed_official 146:f64d43ff0c18 7180 #define I2C_C1_TXAK_SHIFT 3
mbed_official 146:f64d43ff0c18 7181 #define I2C_C1_TX_MASK 0x10u
mbed_official 146:f64d43ff0c18 7182 #define I2C_C1_TX_SHIFT 4
mbed_official 146:f64d43ff0c18 7183 #define I2C_C1_MST_MASK 0x20u
mbed_official 146:f64d43ff0c18 7184 #define I2C_C1_MST_SHIFT 5
mbed_official 146:f64d43ff0c18 7185 #define I2C_C1_IICIE_MASK 0x40u
mbed_official 146:f64d43ff0c18 7186 #define I2C_C1_IICIE_SHIFT 6
mbed_official 146:f64d43ff0c18 7187 #define I2C_C1_IICEN_MASK 0x80u
mbed_official 146:f64d43ff0c18 7188 #define I2C_C1_IICEN_SHIFT 7
mbed_official 146:f64d43ff0c18 7189 /* S Bit Fields */
mbed_official 146:f64d43ff0c18 7190 #define I2C_S_RXAK_MASK 0x1u
mbed_official 146:f64d43ff0c18 7191 #define I2C_S_RXAK_SHIFT 0
mbed_official 146:f64d43ff0c18 7192 #define I2C_S_IICIF_MASK 0x2u
mbed_official 146:f64d43ff0c18 7193 #define I2C_S_IICIF_SHIFT 1
mbed_official 146:f64d43ff0c18 7194 #define I2C_S_SRW_MASK 0x4u
mbed_official 146:f64d43ff0c18 7195 #define I2C_S_SRW_SHIFT 2
mbed_official 146:f64d43ff0c18 7196 #define I2C_S_RAM_MASK 0x8u
mbed_official 146:f64d43ff0c18 7197 #define I2C_S_RAM_SHIFT 3
mbed_official 146:f64d43ff0c18 7198 #define I2C_S_ARBL_MASK 0x10u
mbed_official 146:f64d43ff0c18 7199 #define I2C_S_ARBL_SHIFT 4
mbed_official 146:f64d43ff0c18 7200 #define I2C_S_BUSY_MASK 0x20u
mbed_official 146:f64d43ff0c18 7201 #define I2C_S_BUSY_SHIFT 5
mbed_official 146:f64d43ff0c18 7202 #define I2C_S_IAAS_MASK 0x40u
mbed_official 146:f64d43ff0c18 7203 #define I2C_S_IAAS_SHIFT 6
mbed_official 146:f64d43ff0c18 7204 #define I2C_S_TCF_MASK 0x80u
mbed_official 146:f64d43ff0c18 7205 #define I2C_S_TCF_SHIFT 7
mbed_official 146:f64d43ff0c18 7206 /* D Bit Fields */
mbed_official 146:f64d43ff0c18 7207 #define I2C_D_DATA_MASK 0xFFu
mbed_official 146:f64d43ff0c18 7208 #define I2C_D_DATA_SHIFT 0
mbed_official 146:f64d43ff0c18 7209 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
mbed_official 146:f64d43ff0c18 7210 /* C2 Bit Fields */
mbed_official 146:f64d43ff0c18 7211 #define I2C_C2_AD_MASK 0x7u
mbed_official 146:f64d43ff0c18 7212 #define I2C_C2_AD_SHIFT 0
mbed_official 146:f64d43ff0c18 7213 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
mbed_official 146:f64d43ff0c18 7214 #define I2C_C2_RMEN_MASK 0x8u
mbed_official 146:f64d43ff0c18 7215 #define I2C_C2_RMEN_SHIFT 3
mbed_official 146:f64d43ff0c18 7216 #define I2C_C2_SBRC_MASK 0x10u
mbed_official 146:f64d43ff0c18 7217 #define I2C_C2_SBRC_SHIFT 4
mbed_official 146:f64d43ff0c18 7218 #define I2C_C2_HDRS_MASK 0x20u
mbed_official 146:f64d43ff0c18 7219 #define I2C_C2_HDRS_SHIFT 5
mbed_official 146:f64d43ff0c18 7220 #define I2C_C2_ADEXT_MASK 0x40u
mbed_official 146:f64d43ff0c18 7221 #define I2C_C2_ADEXT_SHIFT 6
mbed_official 146:f64d43ff0c18 7222 #define I2C_C2_GCAEN_MASK 0x80u
mbed_official 146:f64d43ff0c18 7223 #define I2C_C2_GCAEN_SHIFT 7
mbed_official 146:f64d43ff0c18 7224 /* FLT Bit Fields */
mbed_official 146:f64d43ff0c18 7225 #define I2C_FLT_FLT_MASK 0xFu
mbed_official 146:f64d43ff0c18 7226 #define I2C_FLT_FLT_SHIFT 0
mbed_official 146:f64d43ff0c18 7227 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
mbed_official 146:f64d43ff0c18 7228 #define I2C_FLT_STARTF_MASK 0x10u
mbed_official 146:f64d43ff0c18 7229 #define I2C_FLT_STARTF_SHIFT 4
mbed_official 146:f64d43ff0c18 7230 #define I2C_FLT_SSIE_MASK 0x20u
mbed_official 146:f64d43ff0c18 7231 #define I2C_FLT_SSIE_SHIFT 5
mbed_official 146:f64d43ff0c18 7232 #define I2C_FLT_STOPF_MASK 0x40u
mbed_official 146:f64d43ff0c18 7233 #define I2C_FLT_STOPF_SHIFT 6
mbed_official 146:f64d43ff0c18 7234 #define I2C_FLT_SHEN_MASK 0x80u
mbed_official 146:f64d43ff0c18 7235 #define I2C_FLT_SHEN_SHIFT 7
mbed_official 146:f64d43ff0c18 7236 /* RA Bit Fields */
mbed_official 146:f64d43ff0c18 7237 #define I2C_RA_RAD_MASK 0xFEu
mbed_official 146:f64d43ff0c18 7238 #define I2C_RA_RAD_SHIFT 1
mbed_official 146:f64d43ff0c18 7239 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
mbed_official 146:f64d43ff0c18 7240 /* SMB Bit Fields */
mbed_official 146:f64d43ff0c18 7241 #define I2C_SMB_SHTF2IE_MASK 0x1u
mbed_official 146:f64d43ff0c18 7242 #define I2C_SMB_SHTF2IE_SHIFT 0
mbed_official 146:f64d43ff0c18 7243 #define I2C_SMB_SHTF2_MASK 0x2u
mbed_official 146:f64d43ff0c18 7244 #define I2C_SMB_SHTF2_SHIFT 1
mbed_official 146:f64d43ff0c18 7245 #define I2C_SMB_SHTF1_MASK 0x4u
mbed_official 146:f64d43ff0c18 7246 #define I2C_SMB_SHTF1_SHIFT 2
mbed_official 146:f64d43ff0c18 7247 #define I2C_SMB_SLTF_MASK 0x8u
mbed_official 146:f64d43ff0c18 7248 #define I2C_SMB_SLTF_SHIFT 3
mbed_official 146:f64d43ff0c18 7249 #define I2C_SMB_TCKSEL_MASK 0x10u
mbed_official 146:f64d43ff0c18 7250 #define I2C_SMB_TCKSEL_SHIFT 4
mbed_official 146:f64d43ff0c18 7251 #define I2C_SMB_SIICAEN_MASK 0x20u
mbed_official 146:f64d43ff0c18 7252 #define I2C_SMB_SIICAEN_SHIFT 5
mbed_official 146:f64d43ff0c18 7253 #define I2C_SMB_ALERTEN_MASK 0x40u
mbed_official 146:f64d43ff0c18 7254 #define I2C_SMB_ALERTEN_SHIFT 6
mbed_official 146:f64d43ff0c18 7255 #define I2C_SMB_FACK_MASK 0x80u
mbed_official 146:f64d43ff0c18 7256 #define I2C_SMB_FACK_SHIFT 7
mbed_official 146:f64d43ff0c18 7257 /* A2 Bit Fields */
mbed_official 146:f64d43ff0c18 7258 #define I2C_A2_SAD_MASK 0xFEu
mbed_official 146:f64d43ff0c18 7259 #define I2C_A2_SAD_SHIFT 1
mbed_official 146:f64d43ff0c18 7260 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
mbed_official 146:f64d43ff0c18 7261 /* SLTH Bit Fields */
mbed_official 146:f64d43ff0c18 7262 #define I2C_SLTH_SSLT_MASK 0xFFu
mbed_official 146:f64d43ff0c18 7263 #define I2C_SLTH_SSLT_SHIFT 0
mbed_official 146:f64d43ff0c18 7264 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
mbed_official 146:f64d43ff0c18 7265 /* SLTL Bit Fields */
mbed_official 146:f64d43ff0c18 7266 #define I2C_SLTL_SSLT_MASK 0xFFu
mbed_official 146:f64d43ff0c18 7267 #define I2C_SLTL_SSLT_SHIFT 0
mbed_official 146:f64d43ff0c18 7268 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
mbed_official 146:f64d43ff0c18 7269
mbed_official 146:f64d43ff0c18 7270 /*!
mbed_official 146:f64d43ff0c18 7271 * @}
mbed_official 146:f64d43ff0c18 7272 */ /* end of group I2C_Register_Masks */
mbed_official 146:f64d43ff0c18 7273
mbed_official 146:f64d43ff0c18 7274
mbed_official 146:f64d43ff0c18 7275 /* I2C - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 7276 /** Peripheral I2C0 base address */
mbed_official 146:f64d43ff0c18 7277 #define I2C0_BASE (0x40066000u)
mbed_official 146:f64d43ff0c18 7278 /** Peripheral I2C0 base pointer */
mbed_official 146:f64d43ff0c18 7279 #define I2C0 ((I2C_Type *)I2C0_BASE)
mbed_official 146:f64d43ff0c18 7280 #define I2C0_BASE_PTR (I2C0)
mbed_official 146:f64d43ff0c18 7281 /** Peripheral I2C1 base address */
mbed_official 146:f64d43ff0c18 7282 #define I2C1_BASE (0x40067000u)
mbed_official 146:f64d43ff0c18 7283 /** Peripheral I2C1 base pointer */
mbed_official 146:f64d43ff0c18 7284 #define I2C1 ((I2C_Type *)I2C1_BASE)
mbed_official 146:f64d43ff0c18 7285 #define I2C1_BASE_PTR (I2C1)
mbed_official 146:f64d43ff0c18 7286 /** Peripheral I2C2 base address */
mbed_official 146:f64d43ff0c18 7287 #define I2C2_BASE (0x400E6000u)
mbed_official 146:f64d43ff0c18 7288 /** Peripheral I2C2 base pointer */
mbed_official 146:f64d43ff0c18 7289 #define I2C2 ((I2C_Type *)I2C2_BASE)
mbed_official 146:f64d43ff0c18 7290 #define I2C2_BASE_PTR (I2C2)
mbed_official 146:f64d43ff0c18 7291 /** Array initializer of I2C peripheral base pointers */
mbed_official 146:f64d43ff0c18 7292 #define I2C_BASES { I2C0, I2C1, I2C2 }
mbed_official 146:f64d43ff0c18 7293
mbed_official 146:f64d43ff0c18 7294 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 7295 -- I2C - Register accessor macros
mbed_official 146:f64d43ff0c18 7296 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 7297
mbed_official 146:f64d43ff0c18 7298 /*!
mbed_official 146:f64d43ff0c18 7299 * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
mbed_official 146:f64d43ff0c18 7300 * @{
mbed_official 146:f64d43ff0c18 7301 */
mbed_official 146:f64d43ff0c18 7302
mbed_official 146:f64d43ff0c18 7303
mbed_official 146:f64d43ff0c18 7304 /* I2C - Register instance definitions */
mbed_official 146:f64d43ff0c18 7305 /* I2C0 */
mbed_official 146:f64d43ff0c18 7306 #define I2C0_A1 I2C_A1_REG(I2C0)
mbed_official 146:f64d43ff0c18 7307 #define I2C0_F I2C_F_REG(I2C0)
mbed_official 146:f64d43ff0c18 7308 #define I2C0_C1 I2C_C1_REG(I2C0)
mbed_official 146:f64d43ff0c18 7309 #define I2C0_S I2C_S_REG(I2C0)
mbed_official 146:f64d43ff0c18 7310 #define I2C0_D I2C_D_REG(I2C0)
mbed_official 146:f64d43ff0c18 7311 #define I2C0_C2 I2C_C2_REG(I2C0)
mbed_official 146:f64d43ff0c18 7312 #define I2C0_FLT I2C_FLT_REG(I2C0)
mbed_official 146:f64d43ff0c18 7313 #define I2C0_RA I2C_RA_REG(I2C0)
mbed_official 146:f64d43ff0c18 7314 #define I2C0_SMB I2C_SMB_REG(I2C0)
mbed_official 146:f64d43ff0c18 7315 #define I2C0_A2 I2C_A2_REG(I2C0)
mbed_official 146:f64d43ff0c18 7316 #define I2C0_SLTH I2C_SLTH_REG(I2C0)
mbed_official 146:f64d43ff0c18 7317 #define I2C0_SLTL I2C_SLTL_REG(I2C0)
mbed_official 146:f64d43ff0c18 7318 /* I2C1 */
mbed_official 146:f64d43ff0c18 7319 #define I2C1_A1 I2C_A1_REG(I2C1)
mbed_official 146:f64d43ff0c18 7320 #define I2C1_F I2C_F_REG(I2C1)
mbed_official 146:f64d43ff0c18 7321 #define I2C1_C1 I2C_C1_REG(I2C1)
mbed_official 146:f64d43ff0c18 7322 #define I2C1_S I2C_S_REG(I2C1)
mbed_official 146:f64d43ff0c18 7323 #define I2C1_D I2C_D_REG(I2C1)
mbed_official 146:f64d43ff0c18 7324 #define I2C1_C2 I2C_C2_REG(I2C1)
mbed_official 146:f64d43ff0c18 7325 #define I2C1_FLT I2C_FLT_REG(I2C1)
mbed_official 146:f64d43ff0c18 7326 #define I2C1_RA I2C_RA_REG(I2C1)
mbed_official 146:f64d43ff0c18 7327 #define I2C1_SMB I2C_SMB_REG(I2C1)
mbed_official 146:f64d43ff0c18 7328 #define I2C1_A2 I2C_A2_REG(I2C1)
mbed_official 146:f64d43ff0c18 7329 #define I2C1_SLTH I2C_SLTH_REG(I2C1)
mbed_official 146:f64d43ff0c18 7330 #define I2C1_SLTL I2C_SLTL_REG(I2C1)
mbed_official 146:f64d43ff0c18 7331 /* I2C2 */
mbed_official 146:f64d43ff0c18 7332 #define I2C2_A1 I2C_A1_REG(I2C2)
mbed_official 146:f64d43ff0c18 7333 #define I2C2_F I2C_F_REG(I2C2)
mbed_official 146:f64d43ff0c18 7334 #define I2C2_C1 I2C_C1_REG(I2C2)
mbed_official 146:f64d43ff0c18 7335 #define I2C2_S I2C_S_REG(I2C2)
mbed_official 146:f64d43ff0c18 7336 #define I2C2_D I2C_D_REG(I2C2)
mbed_official 146:f64d43ff0c18 7337 #define I2C2_C2 I2C_C2_REG(I2C2)
mbed_official 146:f64d43ff0c18 7338 #define I2C2_FLT I2C_FLT_REG(I2C2)
mbed_official 146:f64d43ff0c18 7339 #define I2C2_RA I2C_RA_REG(I2C2)
mbed_official 146:f64d43ff0c18 7340 #define I2C2_SMB I2C_SMB_REG(I2C2)
mbed_official 146:f64d43ff0c18 7341 #define I2C2_A2 I2C_A2_REG(I2C2)
mbed_official 146:f64d43ff0c18 7342 #define I2C2_SLTH I2C_SLTH_REG(I2C2)
mbed_official 146:f64d43ff0c18 7343 #define I2C2_SLTL I2C_SLTL_REG(I2C2)
mbed_official 146:f64d43ff0c18 7344
mbed_official 146:f64d43ff0c18 7345 /*!
mbed_official 146:f64d43ff0c18 7346 * @}
mbed_official 146:f64d43ff0c18 7347 */ /* end of group I2C_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 7348
mbed_official 146:f64d43ff0c18 7349
mbed_official 146:f64d43ff0c18 7350 /*!
mbed_official 146:f64d43ff0c18 7351 * @}
mbed_official 146:f64d43ff0c18 7352 */ /* end of group I2C_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 7353
mbed_official 146:f64d43ff0c18 7354
mbed_official 146:f64d43ff0c18 7355 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 7356 -- I2S Peripheral Access Layer
mbed_official 146:f64d43ff0c18 7357 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 7358
mbed_official 146:f64d43ff0c18 7359 /*!
mbed_official 146:f64d43ff0c18 7360 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
mbed_official 146:f64d43ff0c18 7361 * @{
mbed_official 146:f64d43ff0c18 7362 */
mbed_official 146:f64d43ff0c18 7363
mbed_official 146:f64d43ff0c18 7364 /** I2S - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 7365 typedef struct {
mbed_official 146:f64d43ff0c18 7366 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
mbed_official 146:f64d43ff0c18 7367 __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
mbed_official 146:f64d43ff0c18 7368 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
mbed_official 146:f64d43ff0c18 7369 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
mbed_official 146:f64d43ff0c18 7370 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
mbed_official 146:f64d43ff0c18 7371 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
mbed_official 146:f64d43ff0c18 7372 uint8_t RESERVED_0[8];
mbed_official 146:f64d43ff0c18 7373 __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
mbed_official 146:f64d43ff0c18 7374 uint8_t RESERVED_1[24];
mbed_official 146:f64d43ff0c18 7375 __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
mbed_official 146:f64d43ff0c18 7376 uint8_t RESERVED_2[24];
mbed_official 146:f64d43ff0c18 7377 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
mbed_official 146:f64d43ff0c18 7378 uint8_t RESERVED_3[28];
mbed_official 146:f64d43ff0c18 7379 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
mbed_official 146:f64d43ff0c18 7380 __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
mbed_official 146:f64d43ff0c18 7381 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
mbed_official 146:f64d43ff0c18 7382 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
mbed_official 146:f64d43ff0c18 7383 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
mbed_official 146:f64d43ff0c18 7384 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
mbed_official 146:f64d43ff0c18 7385 uint8_t RESERVED_4[8];
mbed_official 146:f64d43ff0c18 7386 __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
mbed_official 146:f64d43ff0c18 7387 uint8_t RESERVED_5[24];
mbed_official 146:f64d43ff0c18 7388 __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
mbed_official 146:f64d43ff0c18 7389 uint8_t RESERVED_6[24];
mbed_official 146:f64d43ff0c18 7390 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
mbed_official 146:f64d43ff0c18 7391 uint8_t RESERVED_7[28];
mbed_official 146:f64d43ff0c18 7392 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
mbed_official 146:f64d43ff0c18 7393 __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
mbed_official 146:f64d43ff0c18 7394 } I2S_Type, *I2S_MemMapPtr;
mbed_official 146:f64d43ff0c18 7395
mbed_official 146:f64d43ff0c18 7396 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 7397 -- I2S - Register accessor macros
mbed_official 146:f64d43ff0c18 7398 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 7399
mbed_official 146:f64d43ff0c18 7400 /*!
mbed_official 146:f64d43ff0c18 7401 * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
mbed_official 146:f64d43ff0c18 7402 * @{
mbed_official 146:f64d43ff0c18 7403 */
mbed_official 146:f64d43ff0c18 7404
mbed_official 146:f64d43ff0c18 7405
mbed_official 146:f64d43ff0c18 7406 /* I2S - Register accessors */
mbed_official 146:f64d43ff0c18 7407 #define I2S_TCSR_REG(base) ((base)->TCSR)
mbed_official 146:f64d43ff0c18 7408 #define I2S_TCR1_REG(base) ((base)->TCR1)
mbed_official 146:f64d43ff0c18 7409 #define I2S_TCR2_REG(base) ((base)->TCR2)
mbed_official 146:f64d43ff0c18 7410 #define I2S_TCR3_REG(base) ((base)->TCR3)
mbed_official 146:f64d43ff0c18 7411 #define I2S_TCR4_REG(base) ((base)->TCR4)
mbed_official 146:f64d43ff0c18 7412 #define I2S_TCR5_REG(base) ((base)->TCR5)
mbed_official 146:f64d43ff0c18 7413 #define I2S_TDR_REG(base,index) ((base)->TDR[index])
mbed_official 146:f64d43ff0c18 7414 #define I2S_TFR_REG(base,index) ((base)->TFR[index])
mbed_official 146:f64d43ff0c18 7415 #define I2S_TMR_REG(base) ((base)->TMR)
mbed_official 146:f64d43ff0c18 7416 #define I2S_RCSR_REG(base) ((base)->RCSR)
mbed_official 146:f64d43ff0c18 7417 #define I2S_RCR1_REG(base) ((base)->RCR1)
mbed_official 146:f64d43ff0c18 7418 #define I2S_RCR2_REG(base) ((base)->RCR2)
mbed_official 146:f64d43ff0c18 7419 #define I2S_RCR3_REG(base) ((base)->RCR3)
mbed_official 146:f64d43ff0c18 7420 #define I2S_RCR4_REG(base) ((base)->RCR4)
mbed_official 146:f64d43ff0c18 7421 #define I2S_RCR5_REG(base) ((base)->RCR5)
mbed_official 146:f64d43ff0c18 7422 #define I2S_RDR_REG(base,index) ((base)->RDR[index])
mbed_official 146:f64d43ff0c18 7423 #define I2S_RFR_REG(base,index) ((base)->RFR[index])
mbed_official 146:f64d43ff0c18 7424 #define I2S_RMR_REG(base) ((base)->RMR)
mbed_official 146:f64d43ff0c18 7425 #define I2S_MCR_REG(base) ((base)->MCR)
mbed_official 146:f64d43ff0c18 7426 #define I2S_MDR_REG(base) ((base)->MDR)
mbed_official 146:f64d43ff0c18 7427
mbed_official 146:f64d43ff0c18 7428 /*!
mbed_official 146:f64d43ff0c18 7429 * @}
mbed_official 146:f64d43ff0c18 7430 */ /* end of group I2S_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 7431
mbed_official 146:f64d43ff0c18 7432
mbed_official 146:f64d43ff0c18 7433 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 7434 -- I2S Register Masks
mbed_official 146:f64d43ff0c18 7435 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 7436
mbed_official 146:f64d43ff0c18 7437 /*!
mbed_official 146:f64d43ff0c18 7438 * @addtogroup I2S_Register_Masks I2S Register Masks
mbed_official 146:f64d43ff0c18 7439 * @{
mbed_official 146:f64d43ff0c18 7440 */
mbed_official 146:f64d43ff0c18 7441
mbed_official 146:f64d43ff0c18 7442 /* TCSR Bit Fields */
mbed_official 146:f64d43ff0c18 7443 #define I2S_TCSR_FRDE_MASK 0x1u
mbed_official 146:f64d43ff0c18 7444 #define I2S_TCSR_FRDE_SHIFT 0
mbed_official 146:f64d43ff0c18 7445 #define I2S_TCSR_FWDE_MASK 0x2u
mbed_official 146:f64d43ff0c18 7446 #define I2S_TCSR_FWDE_SHIFT 1
mbed_official 146:f64d43ff0c18 7447 #define I2S_TCSR_FRIE_MASK 0x100u
mbed_official 146:f64d43ff0c18 7448 #define I2S_TCSR_FRIE_SHIFT 8
mbed_official 146:f64d43ff0c18 7449 #define I2S_TCSR_FWIE_MASK 0x200u
mbed_official 146:f64d43ff0c18 7450 #define I2S_TCSR_FWIE_SHIFT 9
mbed_official 146:f64d43ff0c18 7451 #define I2S_TCSR_FEIE_MASK 0x400u
mbed_official 146:f64d43ff0c18 7452 #define I2S_TCSR_FEIE_SHIFT 10
mbed_official 146:f64d43ff0c18 7453 #define I2S_TCSR_SEIE_MASK 0x800u
mbed_official 146:f64d43ff0c18 7454 #define I2S_TCSR_SEIE_SHIFT 11
mbed_official 146:f64d43ff0c18 7455 #define I2S_TCSR_WSIE_MASK 0x1000u
mbed_official 146:f64d43ff0c18 7456 #define I2S_TCSR_WSIE_SHIFT 12
mbed_official 146:f64d43ff0c18 7457 #define I2S_TCSR_FRF_MASK 0x10000u
mbed_official 146:f64d43ff0c18 7458 #define I2S_TCSR_FRF_SHIFT 16
mbed_official 146:f64d43ff0c18 7459 #define I2S_TCSR_FWF_MASK 0x20000u
mbed_official 146:f64d43ff0c18 7460 #define I2S_TCSR_FWF_SHIFT 17
mbed_official 146:f64d43ff0c18 7461 #define I2S_TCSR_FEF_MASK 0x40000u
mbed_official 146:f64d43ff0c18 7462 #define I2S_TCSR_FEF_SHIFT 18
mbed_official 146:f64d43ff0c18 7463 #define I2S_TCSR_SEF_MASK 0x80000u
mbed_official 146:f64d43ff0c18 7464 #define I2S_TCSR_SEF_SHIFT 19
mbed_official 146:f64d43ff0c18 7465 #define I2S_TCSR_WSF_MASK 0x100000u
mbed_official 146:f64d43ff0c18 7466 #define I2S_TCSR_WSF_SHIFT 20
mbed_official 146:f64d43ff0c18 7467 #define I2S_TCSR_SR_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 7468 #define I2S_TCSR_SR_SHIFT 24
mbed_official 146:f64d43ff0c18 7469 #define I2S_TCSR_FR_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 7470 #define I2S_TCSR_FR_SHIFT 25
mbed_official 146:f64d43ff0c18 7471 #define I2S_TCSR_BCE_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 7472 #define I2S_TCSR_BCE_SHIFT 28
mbed_official 146:f64d43ff0c18 7473 #define I2S_TCSR_DBGE_MASK 0x20000000u
mbed_official 146:f64d43ff0c18 7474 #define I2S_TCSR_DBGE_SHIFT 29
mbed_official 146:f64d43ff0c18 7475 #define I2S_TCSR_STOPE_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 7476 #define I2S_TCSR_STOPE_SHIFT 30
mbed_official 146:f64d43ff0c18 7477 #define I2S_TCSR_TE_MASK 0x80000000u
mbed_official 146:f64d43ff0c18 7478 #define I2S_TCSR_TE_SHIFT 31
mbed_official 146:f64d43ff0c18 7479 /* TCR1 Bit Fields */
mbed_official 146:f64d43ff0c18 7480 #define I2S_TCR1_TFW_MASK 0x7u
mbed_official 146:f64d43ff0c18 7481 #define I2S_TCR1_TFW_SHIFT 0
mbed_official 146:f64d43ff0c18 7482 #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
mbed_official 146:f64d43ff0c18 7483 /* TCR2 Bit Fields */
mbed_official 146:f64d43ff0c18 7484 #define I2S_TCR2_DIV_MASK 0xFFu
mbed_official 146:f64d43ff0c18 7485 #define I2S_TCR2_DIV_SHIFT 0
mbed_official 146:f64d43ff0c18 7486 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
mbed_official 146:f64d43ff0c18 7487 #define I2S_TCR2_BCD_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 7488 #define I2S_TCR2_BCD_SHIFT 24
mbed_official 146:f64d43ff0c18 7489 #define I2S_TCR2_BCP_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 7490 #define I2S_TCR2_BCP_SHIFT 25
mbed_official 146:f64d43ff0c18 7491 #define I2S_TCR2_MSEL_MASK 0xC000000u
mbed_official 146:f64d43ff0c18 7492 #define I2S_TCR2_MSEL_SHIFT 26
mbed_official 146:f64d43ff0c18 7493 #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
mbed_official 146:f64d43ff0c18 7494 #define I2S_TCR2_BCI_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 7495 #define I2S_TCR2_BCI_SHIFT 28
mbed_official 146:f64d43ff0c18 7496 #define I2S_TCR2_BCS_MASK 0x20000000u
mbed_official 146:f64d43ff0c18 7497 #define I2S_TCR2_BCS_SHIFT 29
mbed_official 146:f64d43ff0c18 7498 #define I2S_TCR2_SYNC_MASK 0xC0000000u
mbed_official 146:f64d43ff0c18 7499 #define I2S_TCR2_SYNC_SHIFT 30
mbed_official 146:f64d43ff0c18 7500 #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
mbed_official 146:f64d43ff0c18 7501 /* TCR3 Bit Fields */
mbed_official 146:f64d43ff0c18 7502 #define I2S_TCR3_WDFL_MASK 0x1Fu
mbed_official 146:f64d43ff0c18 7503 #define I2S_TCR3_WDFL_SHIFT 0
mbed_official 146:f64d43ff0c18 7504 #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
mbed_official 146:f64d43ff0c18 7505 #define I2S_TCR3_TCE_MASK 0x30000u
mbed_official 146:f64d43ff0c18 7506 #define I2S_TCR3_TCE_SHIFT 16
mbed_official 146:f64d43ff0c18 7507 #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
mbed_official 146:f64d43ff0c18 7508 /* TCR4 Bit Fields */
mbed_official 146:f64d43ff0c18 7509 #define I2S_TCR4_FSD_MASK 0x1u
mbed_official 146:f64d43ff0c18 7510 #define I2S_TCR4_FSD_SHIFT 0
mbed_official 146:f64d43ff0c18 7511 #define I2S_TCR4_FSP_MASK 0x2u
mbed_official 146:f64d43ff0c18 7512 #define I2S_TCR4_FSP_SHIFT 1
mbed_official 146:f64d43ff0c18 7513 #define I2S_TCR4_FSE_MASK 0x8u
mbed_official 146:f64d43ff0c18 7514 #define I2S_TCR4_FSE_SHIFT 3
mbed_official 146:f64d43ff0c18 7515 #define I2S_TCR4_MF_MASK 0x10u
mbed_official 146:f64d43ff0c18 7516 #define I2S_TCR4_MF_SHIFT 4
mbed_official 146:f64d43ff0c18 7517 #define I2S_TCR4_SYWD_MASK 0x1F00u
mbed_official 146:f64d43ff0c18 7518 #define I2S_TCR4_SYWD_SHIFT 8
mbed_official 146:f64d43ff0c18 7519 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
mbed_official 146:f64d43ff0c18 7520 #define I2S_TCR4_FRSZ_MASK 0x1F0000u
mbed_official 146:f64d43ff0c18 7521 #define I2S_TCR4_FRSZ_SHIFT 16
mbed_official 146:f64d43ff0c18 7522 #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
mbed_official 146:f64d43ff0c18 7523 /* TCR5 Bit Fields */
mbed_official 146:f64d43ff0c18 7524 #define I2S_TCR5_FBT_MASK 0x1F00u
mbed_official 146:f64d43ff0c18 7525 #define I2S_TCR5_FBT_SHIFT 8
mbed_official 146:f64d43ff0c18 7526 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
mbed_official 146:f64d43ff0c18 7527 #define I2S_TCR5_W0W_MASK 0x1F0000u
mbed_official 146:f64d43ff0c18 7528 #define I2S_TCR5_W0W_SHIFT 16
mbed_official 146:f64d43ff0c18 7529 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
mbed_official 146:f64d43ff0c18 7530 #define I2S_TCR5_WNW_MASK 0x1F000000u
mbed_official 146:f64d43ff0c18 7531 #define I2S_TCR5_WNW_SHIFT 24
mbed_official 146:f64d43ff0c18 7532 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
mbed_official 146:f64d43ff0c18 7533 /* TDR Bit Fields */
mbed_official 146:f64d43ff0c18 7534 #define I2S_TDR_TDR_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 7535 #define I2S_TDR_TDR_SHIFT 0
mbed_official 146:f64d43ff0c18 7536 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
mbed_official 146:f64d43ff0c18 7537 /* TFR Bit Fields */
mbed_official 146:f64d43ff0c18 7538 #define I2S_TFR_RFP_MASK 0xFu
mbed_official 146:f64d43ff0c18 7539 #define I2S_TFR_RFP_SHIFT 0
mbed_official 146:f64d43ff0c18 7540 #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
mbed_official 146:f64d43ff0c18 7541 #define I2S_TFR_WFP_MASK 0xF0000u
mbed_official 146:f64d43ff0c18 7542 #define I2S_TFR_WFP_SHIFT 16
mbed_official 146:f64d43ff0c18 7543 #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
mbed_official 146:f64d43ff0c18 7544 /* TMR Bit Fields */
mbed_official 146:f64d43ff0c18 7545 #define I2S_TMR_TWM_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 7546 #define I2S_TMR_TWM_SHIFT 0
mbed_official 146:f64d43ff0c18 7547 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
mbed_official 146:f64d43ff0c18 7548 /* RCSR Bit Fields */
mbed_official 146:f64d43ff0c18 7549 #define I2S_RCSR_FRDE_MASK 0x1u
mbed_official 146:f64d43ff0c18 7550 #define I2S_RCSR_FRDE_SHIFT 0
mbed_official 146:f64d43ff0c18 7551 #define I2S_RCSR_FWDE_MASK 0x2u
mbed_official 146:f64d43ff0c18 7552 #define I2S_RCSR_FWDE_SHIFT 1
mbed_official 146:f64d43ff0c18 7553 #define I2S_RCSR_FRIE_MASK 0x100u
mbed_official 146:f64d43ff0c18 7554 #define I2S_RCSR_FRIE_SHIFT 8
mbed_official 146:f64d43ff0c18 7555 #define I2S_RCSR_FWIE_MASK 0x200u
mbed_official 146:f64d43ff0c18 7556 #define I2S_RCSR_FWIE_SHIFT 9
mbed_official 146:f64d43ff0c18 7557 #define I2S_RCSR_FEIE_MASK 0x400u
mbed_official 146:f64d43ff0c18 7558 #define I2S_RCSR_FEIE_SHIFT 10
mbed_official 146:f64d43ff0c18 7559 #define I2S_RCSR_SEIE_MASK 0x800u
mbed_official 146:f64d43ff0c18 7560 #define I2S_RCSR_SEIE_SHIFT 11
mbed_official 146:f64d43ff0c18 7561 #define I2S_RCSR_WSIE_MASK 0x1000u
mbed_official 146:f64d43ff0c18 7562 #define I2S_RCSR_WSIE_SHIFT 12
mbed_official 146:f64d43ff0c18 7563 #define I2S_RCSR_FRF_MASK 0x10000u
mbed_official 146:f64d43ff0c18 7564 #define I2S_RCSR_FRF_SHIFT 16
mbed_official 146:f64d43ff0c18 7565 #define I2S_RCSR_FWF_MASK 0x20000u
mbed_official 146:f64d43ff0c18 7566 #define I2S_RCSR_FWF_SHIFT 17
mbed_official 146:f64d43ff0c18 7567 #define I2S_RCSR_FEF_MASK 0x40000u
mbed_official 146:f64d43ff0c18 7568 #define I2S_RCSR_FEF_SHIFT 18
mbed_official 146:f64d43ff0c18 7569 #define I2S_RCSR_SEF_MASK 0x80000u
mbed_official 146:f64d43ff0c18 7570 #define I2S_RCSR_SEF_SHIFT 19
mbed_official 146:f64d43ff0c18 7571 #define I2S_RCSR_WSF_MASK 0x100000u
mbed_official 146:f64d43ff0c18 7572 #define I2S_RCSR_WSF_SHIFT 20
mbed_official 146:f64d43ff0c18 7573 #define I2S_RCSR_SR_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 7574 #define I2S_RCSR_SR_SHIFT 24
mbed_official 146:f64d43ff0c18 7575 #define I2S_RCSR_FR_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 7576 #define I2S_RCSR_FR_SHIFT 25
mbed_official 146:f64d43ff0c18 7577 #define I2S_RCSR_BCE_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 7578 #define I2S_RCSR_BCE_SHIFT 28
mbed_official 146:f64d43ff0c18 7579 #define I2S_RCSR_DBGE_MASK 0x20000000u
mbed_official 146:f64d43ff0c18 7580 #define I2S_RCSR_DBGE_SHIFT 29
mbed_official 146:f64d43ff0c18 7581 #define I2S_RCSR_STOPE_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 7582 #define I2S_RCSR_STOPE_SHIFT 30
mbed_official 146:f64d43ff0c18 7583 #define I2S_RCSR_RE_MASK 0x80000000u
mbed_official 146:f64d43ff0c18 7584 #define I2S_RCSR_RE_SHIFT 31
mbed_official 146:f64d43ff0c18 7585 /* RCR1 Bit Fields */
mbed_official 146:f64d43ff0c18 7586 #define I2S_RCR1_RFW_MASK 0x7u
mbed_official 146:f64d43ff0c18 7587 #define I2S_RCR1_RFW_SHIFT 0
mbed_official 146:f64d43ff0c18 7588 #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
mbed_official 146:f64d43ff0c18 7589 /* RCR2 Bit Fields */
mbed_official 146:f64d43ff0c18 7590 #define I2S_RCR2_DIV_MASK 0xFFu
mbed_official 146:f64d43ff0c18 7591 #define I2S_RCR2_DIV_SHIFT 0
mbed_official 146:f64d43ff0c18 7592 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
mbed_official 146:f64d43ff0c18 7593 #define I2S_RCR2_BCD_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 7594 #define I2S_RCR2_BCD_SHIFT 24
mbed_official 146:f64d43ff0c18 7595 #define I2S_RCR2_BCP_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 7596 #define I2S_RCR2_BCP_SHIFT 25
mbed_official 146:f64d43ff0c18 7597 #define I2S_RCR2_MSEL_MASK 0xC000000u
mbed_official 146:f64d43ff0c18 7598 #define I2S_RCR2_MSEL_SHIFT 26
mbed_official 146:f64d43ff0c18 7599 #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
mbed_official 146:f64d43ff0c18 7600 #define I2S_RCR2_BCI_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 7601 #define I2S_RCR2_BCI_SHIFT 28
mbed_official 146:f64d43ff0c18 7602 #define I2S_RCR2_BCS_MASK 0x20000000u
mbed_official 146:f64d43ff0c18 7603 #define I2S_RCR2_BCS_SHIFT 29
mbed_official 146:f64d43ff0c18 7604 #define I2S_RCR2_SYNC_MASK 0xC0000000u
mbed_official 146:f64d43ff0c18 7605 #define I2S_RCR2_SYNC_SHIFT 30
mbed_official 146:f64d43ff0c18 7606 #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
mbed_official 146:f64d43ff0c18 7607 /* RCR3 Bit Fields */
mbed_official 146:f64d43ff0c18 7608 #define I2S_RCR3_WDFL_MASK 0x1Fu
mbed_official 146:f64d43ff0c18 7609 #define I2S_RCR3_WDFL_SHIFT 0
mbed_official 146:f64d43ff0c18 7610 #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
mbed_official 146:f64d43ff0c18 7611 #define I2S_RCR3_RCE_MASK 0x30000u
mbed_official 146:f64d43ff0c18 7612 #define I2S_RCR3_RCE_SHIFT 16
mbed_official 146:f64d43ff0c18 7613 #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
mbed_official 146:f64d43ff0c18 7614 /* RCR4 Bit Fields */
mbed_official 146:f64d43ff0c18 7615 #define I2S_RCR4_FSD_MASK 0x1u
mbed_official 146:f64d43ff0c18 7616 #define I2S_RCR4_FSD_SHIFT 0
mbed_official 146:f64d43ff0c18 7617 #define I2S_RCR4_FSP_MASK 0x2u
mbed_official 146:f64d43ff0c18 7618 #define I2S_RCR4_FSP_SHIFT 1
mbed_official 146:f64d43ff0c18 7619 #define I2S_RCR4_FSE_MASK 0x8u
mbed_official 146:f64d43ff0c18 7620 #define I2S_RCR4_FSE_SHIFT 3
mbed_official 146:f64d43ff0c18 7621 #define I2S_RCR4_MF_MASK 0x10u
mbed_official 146:f64d43ff0c18 7622 #define I2S_RCR4_MF_SHIFT 4
mbed_official 146:f64d43ff0c18 7623 #define I2S_RCR4_SYWD_MASK 0x1F00u
mbed_official 146:f64d43ff0c18 7624 #define I2S_RCR4_SYWD_SHIFT 8
mbed_official 146:f64d43ff0c18 7625 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
mbed_official 146:f64d43ff0c18 7626 #define I2S_RCR4_FRSZ_MASK 0x1F0000u
mbed_official 146:f64d43ff0c18 7627 #define I2S_RCR4_FRSZ_SHIFT 16
mbed_official 146:f64d43ff0c18 7628 #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
mbed_official 146:f64d43ff0c18 7629 /* RCR5 Bit Fields */
mbed_official 146:f64d43ff0c18 7630 #define I2S_RCR5_FBT_MASK 0x1F00u
mbed_official 146:f64d43ff0c18 7631 #define I2S_RCR5_FBT_SHIFT 8
mbed_official 146:f64d43ff0c18 7632 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
mbed_official 146:f64d43ff0c18 7633 #define I2S_RCR5_W0W_MASK 0x1F0000u
mbed_official 146:f64d43ff0c18 7634 #define I2S_RCR5_W0W_SHIFT 16
mbed_official 146:f64d43ff0c18 7635 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
mbed_official 146:f64d43ff0c18 7636 #define I2S_RCR5_WNW_MASK 0x1F000000u
mbed_official 146:f64d43ff0c18 7637 #define I2S_RCR5_WNW_SHIFT 24
mbed_official 146:f64d43ff0c18 7638 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
mbed_official 146:f64d43ff0c18 7639 /* RDR Bit Fields */
mbed_official 146:f64d43ff0c18 7640 #define I2S_RDR_RDR_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 7641 #define I2S_RDR_RDR_SHIFT 0
mbed_official 146:f64d43ff0c18 7642 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
mbed_official 146:f64d43ff0c18 7643 /* RFR Bit Fields */
mbed_official 146:f64d43ff0c18 7644 #define I2S_RFR_RFP_MASK 0xFu
mbed_official 146:f64d43ff0c18 7645 #define I2S_RFR_RFP_SHIFT 0
mbed_official 146:f64d43ff0c18 7646 #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
mbed_official 146:f64d43ff0c18 7647 #define I2S_RFR_WFP_MASK 0xF0000u
mbed_official 146:f64d43ff0c18 7648 #define I2S_RFR_WFP_SHIFT 16
mbed_official 146:f64d43ff0c18 7649 #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
mbed_official 146:f64d43ff0c18 7650 /* RMR Bit Fields */
mbed_official 146:f64d43ff0c18 7651 #define I2S_RMR_RWM_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 7652 #define I2S_RMR_RWM_SHIFT 0
mbed_official 146:f64d43ff0c18 7653 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
mbed_official 146:f64d43ff0c18 7654 /* MCR Bit Fields */
mbed_official 146:f64d43ff0c18 7655 #define I2S_MCR_MICS_MASK 0x3000000u
mbed_official 146:f64d43ff0c18 7656 #define I2S_MCR_MICS_SHIFT 24
mbed_official 146:f64d43ff0c18 7657 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
mbed_official 146:f64d43ff0c18 7658 #define I2S_MCR_MOE_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 7659 #define I2S_MCR_MOE_SHIFT 30
mbed_official 146:f64d43ff0c18 7660 #define I2S_MCR_DUF_MASK 0x80000000u
mbed_official 146:f64d43ff0c18 7661 #define I2S_MCR_DUF_SHIFT 31
mbed_official 146:f64d43ff0c18 7662 /* MDR Bit Fields */
mbed_official 146:f64d43ff0c18 7663 #define I2S_MDR_DIVIDE_MASK 0xFFFu
mbed_official 146:f64d43ff0c18 7664 #define I2S_MDR_DIVIDE_SHIFT 0
mbed_official 146:f64d43ff0c18 7665 #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
mbed_official 146:f64d43ff0c18 7666 #define I2S_MDR_FRACT_MASK 0xFF000u
mbed_official 146:f64d43ff0c18 7667 #define I2S_MDR_FRACT_SHIFT 12
mbed_official 146:f64d43ff0c18 7668 #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
mbed_official 146:f64d43ff0c18 7669
mbed_official 146:f64d43ff0c18 7670 /*!
mbed_official 146:f64d43ff0c18 7671 * @}
mbed_official 146:f64d43ff0c18 7672 */ /* end of group I2S_Register_Masks */
mbed_official 146:f64d43ff0c18 7673
mbed_official 146:f64d43ff0c18 7674
mbed_official 146:f64d43ff0c18 7675 /* I2S - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 7676 /** Peripheral I2S0 base address */
mbed_official 146:f64d43ff0c18 7677 #define I2S0_BASE (0x4002F000u)
mbed_official 146:f64d43ff0c18 7678 /** Peripheral I2S0 base pointer */
mbed_official 146:f64d43ff0c18 7679 #define I2S0 ((I2S_Type *)I2S0_BASE)
mbed_official 146:f64d43ff0c18 7680 #define I2S0_BASE_PTR (I2S0)
mbed_official 146:f64d43ff0c18 7681 /** Array initializer of I2S peripheral base pointers */
mbed_official 146:f64d43ff0c18 7682 #define I2S_BASES { I2S0 }
mbed_official 146:f64d43ff0c18 7683
mbed_official 146:f64d43ff0c18 7684 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 7685 -- I2S - Register accessor macros
mbed_official 146:f64d43ff0c18 7686 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 7687
mbed_official 146:f64d43ff0c18 7688 /*!
mbed_official 146:f64d43ff0c18 7689 * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
mbed_official 146:f64d43ff0c18 7690 * @{
mbed_official 146:f64d43ff0c18 7691 */
mbed_official 146:f64d43ff0c18 7692
mbed_official 146:f64d43ff0c18 7693
mbed_official 146:f64d43ff0c18 7694 /* I2S - Register instance definitions */
mbed_official 146:f64d43ff0c18 7695 /* I2S0 */
mbed_official 146:f64d43ff0c18 7696 #define I2S0_TCSR I2S_TCSR_REG(I2S0)
mbed_official 146:f64d43ff0c18 7697 #define I2S0_TCR1 I2S_TCR1_REG(I2S0)
mbed_official 146:f64d43ff0c18 7698 #define I2S0_TCR2 I2S_TCR2_REG(I2S0)
mbed_official 146:f64d43ff0c18 7699 #define I2S0_TCR3 I2S_TCR3_REG(I2S0)
mbed_official 146:f64d43ff0c18 7700 #define I2S0_TCR4 I2S_TCR4_REG(I2S0)
mbed_official 146:f64d43ff0c18 7701 #define I2S0_TCR5 I2S_TCR5_REG(I2S0)
mbed_official 146:f64d43ff0c18 7702 #define I2S0_TDR0 I2S_TDR_REG(I2S0,0)
mbed_official 146:f64d43ff0c18 7703 #define I2S0_TDR1 I2S_TDR_REG(I2S0,1)
mbed_official 146:f64d43ff0c18 7704 #define I2S0_TFR0 I2S_TFR_REG(I2S0,0)
mbed_official 146:f64d43ff0c18 7705 #define I2S0_TFR1 I2S_TFR_REG(I2S0,1)
mbed_official 146:f64d43ff0c18 7706 #define I2S0_TMR I2S_TMR_REG(I2S0)
mbed_official 146:f64d43ff0c18 7707 #define I2S0_RCSR I2S_RCSR_REG(I2S0)
mbed_official 146:f64d43ff0c18 7708 #define I2S0_RCR1 I2S_RCR1_REG(I2S0)
mbed_official 146:f64d43ff0c18 7709 #define I2S0_RCR2 I2S_RCR2_REG(I2S0)
mbed_official 146:f64d43ff0c18 7710 #define I2S0_RCR3 I2S_RCR3_REG(I2S0)
mbed_official 146:f64d43ff0c18 7711 #define I2S0_RCR4 I2S_RCR4_REG(I2S0)
mbed_official 146:f64d43ff0c18 7712 #define I2S0_RCR5 I2S_RCR5_REG(I2S0)
mbed_official 146:f64d43ff0c18 7713 #define I2S0_RDR0 I2S_RDR_REG(I2S0,0)
mbed_official 146:f64d43ff0c18 7714 #define I2S0_RDR1 I2S_RDR_REG(I2S0,1)
mbed_official 146:f64d43ff0c18 7715 #define I2S0_RFR0 I2S_RFR_REG(I2S0,0)
mbed_official 146:f64d43ff0c18 7716 #define I2S0_RFR1 I2S_RFR_REG(I2S0,1)
mbed_official 146:f64d43ff0c18 7717 #define I2S0_RMR I2S_RMR_REG(I2S0)
mbed_official 146:f64d43ff0c18 7718 #define I2S0_MCR I2S_MCR_REG(I2S0)
mbed_official 146:f64d43ff0c18 7719 #define I2S0_MDR I2S_MDR_REG(I2S0)
mbed_official 146:f64d43ff0c18 7720
mbed_official 146:f64d43ff0c18 7721 /* I2S - Register array accessors */
mbed_official 146:f64d43ff0c18 7722 #define I2S0_TDR(index) I2S_TDR_REG(I2S0,index)
mbed_official 146:f64d43ff0c18 7723 #define I2S0_TFR(index) I2S_TFR_REG(I2S0,index)
mbed_official 146:f64d43ff0c18 7724 #define I2S0_RDR(index) I2S_RDR_REG(I2S0,index)
mbed_official 146:f64d43ff0c18 7725 #define I2S0_RFR(index) I2S_RFR_REG(I2S0,index)
mbed_official 146:f64d43ff0c18 7726
mbed_official 146:f64d43ff0c18 7727 /*!
mbed_official 146:f64d43ff0c18 7728 * @}
mbed_official 146:f64d43ff0c18 7729 */ /* end of group I2S_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 7730
mbed_official 146:f64d43ff0c18 7731
mbed_official 146:f64d43ff0c18 7732 /*!
mbed_official 146:f64d43ff0c18 7733 * @}
mbed_official 146:f64d43ff0c18 7734 */ /* end of group I2S_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 7735
mbed_official 146:f64d43ff0c18 7736
mbed_official 146:f64d43ff0c18 7737 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 7738 -- LLWU Peripheral Access Layer
mbed_official 146:f64d43ff0c18 7739 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 7740
mbed_official 146:f64d43ff0c18 7741 /*!
mbed_official 146:f64d43ff0c18 7742 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
mbed_official 146:f64d43ff0c18 7743 * @{
mbed_official 146:f64d43ff0c18 7744 */
mbed_official 146:f64d43ff0c18 7745
mbed_official 146:f64d43ff0c18 7746 /** LLWU - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 7747 typedef struct {
mbed_official 146:f64d43ff0c18 7748 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
mbed_official 146:f64d43ff0c18 7749 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
mbed_official 146:f64d43ff0c18 7750 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
mbed_official 146:f64d43ff0c18 7751 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
mbed_official 146:f64d43ff0c18 7752 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
mbed_official 146:f64d43ff0c18 7753 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
mbed_official 146:f64d43ff0c18 7754 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
mbed_official 146:f64d43ff0c18 7755 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
mbed_official 146:f64d43ff0c18 7756 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
mbed_official 146:f64d43ff0c18 7757 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
mbed_official 146:f64d43ff0c18 7758 __IO uint8_t RST; /**< LLWU Reset Enable register, offset: 0xA */
mbed_official 146:f64d43ff0c18 7759 } LLWU_Type, *LLWU_MemMapPtr;
mbed_official 146:f64d43ff0c18 7760
mbed_official 146:f64d43ff0c18 7761 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 7762 -- LLWU - Register accessor macros
mbed_official 146:f64d43ff0c18 7763 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 7764
mbed_official 146:f64d43ff0c18 7765 /*!
mbed_official 146:f64d43ff0c18 7766 * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
mbed_official 146:f64d43ff0c18 7767 * @{
mbed_official 146:f64d43ff0c18 7768 */
mbed_official 146:f64d43ff0c18 7769
mbed_official 146:f64d43ff0c18 7770
mbed_official 146:f64d43ff0c18 7771 /* LLWU - Register accessors */
mbed_official 146:f64d43ff0c18 7772 #define LLWU_PE1_REG(base) ((base)->PE1)
mbed_official 146:f64d43ff0c18 7773 #define LLWU_PE2_REG(base) ((base)->PE2)
mbed_official 146:f64d43ff0c18 7774 #define LLWU_PE3_REG(base) ((base)->PE3)
mbed_official 146:f64d43ff0c18 7775 #define LLWU_PE4_REG(base) ((base)->PE4)
mbed_official 146:f64d43ff0c18 7776 #define LLWU_ME_REG(base) ((base)->ME)
mbed_official 146:f64d43ff0c18 7777 #define LLWU_F1_REG(base) ((base)->F1)
mbed_official 146:f64d43ff0c18 7778 #define LLWU_F2_REG(base) ((base)->F2)
mbed_official 146:f64d43ff0c18 7779 #define LLWU_F3_REG(base) ((base)->F3)
mbed_official 146:f64d43ff0c18 7780 #define LLWU_FILT1_REG(base) ((base)->FILT1)
mbed_official 146:f64d43ff0c18 7781 #define LLWU_FILT2_REG(base) ((base)->FILT2)
mbed_official 146:f64d43ff0c18 7782 #define LLWU_RST_REG(base) ((base)->RST)
mbed_official 146:f64d43ff0c18 7783
mbed_official 146:f64d43ff0c18 7784 /*!
mbed_official 146:f64d43ff0c18 7785 * @}
mbed_official 146:f64d43ff0c18 7786 */ /* end of group LLWU_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 7787
mbed_official 146:f64d43ff0c18 7788
mbed_official 146:f64d43ff0c18 7789 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 7790 -- LLWU Register Masks
mbed_official 146:f64d43ff0c18 7791 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 7792
mbed_official 146:f64d43ff0c18 7793 /*!
mbed_official 146:f64d43ff0c18 7794 * @addtogroup LLWU_Register_Masks LLWU Register Masks
mbed_official 146:f64d43ff0c18 7795 * @{
mbed_official 146:f64d43ff0c18 7796 */
mbed_official 146:f64d43ff0c18 7797
mbed_official 146:f64d43ff0c18 7798 /* PE1 Bit Fields */
mbed_official 146:f64d43ff0c18 7799 #define LLWU_PE1_WUPE0_MASK 0x3u
mbed_official 146:f64d43ff0c18 7800 #define LLWU_PE1_WUPE0_SHIFT 0
mbed_official 146:f64d43ff0c18 7801 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
mbed_official 146:f64d43ff0c18 7802 #define LLWU_PE1_WUPE1_MASK 0xCu
mbed_official 146:f64d43ff0c18 7803 #define LLWU_PE1_WUPE1_SHIFT 2
mbed_official 146:f64d43ff0c18 7804 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
mbed_official 146:f64d43ff0c18 7805 #define LLWU_PE1_WUPE2_MASK 0x30u
mbed_official 146:f64d43ff0c18 7806 #define LLWU_PE1_WUPE2_SHIFT 4
mbed_official 146:f64d43ff0c18 7807 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
mbed_official 146:f64d43ff0c18 7808 #define LLWU_PE1_WUPE3_MASK 0xC0u
mbed_official 146:f64d43ff0c18 7809 #define LLWU_PE1_WUPE3_SHIFT 6
mbed_official 146:f64d43ff0c18 7810 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
mbed_official 146:f64d43ff0c18 7811 /* PE2 Bit Fields */
mbed_official 146:f64d43ff0c18 7812 #define LLWU_PE2_WUPE4_MASK 0x3u
mbed_official 146:f64d43ff0c18 7813 #define LLWU_PE2_WUPE4_SHIFT 0
mbed_official 146:f64d43ff0c18 7814 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
mbed_official 146:f64d43ff0c18 7815 #define LLWU_PE2_WUPE5_MASK 0xCu
mbed_official 146:f64d43ff0c18 7816 #define LLWU_PE2_WUPE5_SHIFT 2
mbed_official 146:f64d43ff0c18 7817 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
mbed_official 146:f64d43ff0c18 7818 #define LLWU_PE2_WUPE6_MASK 0x30u
mbed_official 146:f64d43ff0c18 7819 #define LLWU_PE2_WUPE6_SHIFT 4
mbed_official 146:f64d43ff0c18 7820 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
mbed_official 146:f64d43ff0c18 7821 #define LLWU_PE2_WUPE7_MASK 0xC0u
mbed_official 146:f64d43ff0c18 7822 #define LLWU_PE2_WUPE7_SHIFT 6
mbed_official 146:f64d43ff0c18 7823 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
mbed_official 146:f64d43ff0c18 7824 /* PE3 Bit Fields */
mbed_official 146:f64d43ff0c18 7825 #define LLWU_PE3_WUPE8_MASK 0x3u
mbed_official 146:f64d43ff0c18 7826 #define LLWU_PE3_WUPE8_SHIFT 0
mbed_official 146:f64d43ff0c18 7827 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
mbed_official 146:f64d43ff0c18 7828 #define LLWU_PE3_WUPE9_MASK 0xCu
mbed_official 146:f64d43ff0c18 7829 #define LLWU_PE3_WUPE9_SHIFT 2
mbed_official 146:f64d43ff0c18 7830 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
mbed_official 146:f64d43ff0c18 7831 #define LLWU_PE3_WUPE10_MASK 0x30u
mbed_official 146:f64d43ff0c18 7832 #define LLWU_PE3_WUPE10_SHIFT 4
mbed_official 146:f64d43ff0c18 7833 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
mbed_official 146:f64d43ff0c18 7834 #define LLWU_PE3_WUPE11_MASK 0xC0u
mbed_official 146:f64d43ff0c18 7835 #define LLWU_PE3_WUPE11_SHIFT 6
mbed_official 146:f64d43ff0c18 7836 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
mbed_official 146:f64d43ff0c18 7837 /* PE4 Bit Fields */
mbed_official 146:f64d43ff0c18 7838 #define LLWU_PE4_WUPE12_MASK 0x3u
mbed_official 146:f64d43ff0c18 7839 #define LLWU_PE4_WUPE12_SHIFT 0
mbed_official 146:f64d43ff0c18 7840 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
mbed_official 146:f64d43ff0c18 7841 #define LLWU_PE4_WUPE13_MASK 0xCu
mbed_official 146:f64d43ff0c18 7842 #define LLWU_PE4_WUPE13_SHIFT 2
mbed_official 146:f64d43ff0c18 7843 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
mbed_official 146:f64d43ff0c18 7844 #define LLWU_PE4_WUPE14_MASK 0x30u
mbed_official 146:f64d43ff0c18 7845 #define LLWU_PE4_WUPE14_SHIFT 4
mbed_official 146:f64d43ff0c18 7846 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
mbed_official 146:f64d43ff0c18 7847 #define LLWU_PE4_WUPE15_MASK 0xC0u
mbed_official 146:f64d43ff0c18 7848 #define LLWU_PE4_WUPE15_SHIFT 6
mbed_official 146:f64d43ff0c18 7849 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
mbed_official 146:f64d43ff0c18 7850 /* ME Bit Fields */
mbed_official 146:f64d43ff0c18 7851 #define LLWU_ME_WUME0_MASK 0x1u
mbed_official 146:f64d43ff0c18 7852 #define LLWU_ME_WUME0_SHIFT 0
mbed_official 146:f64d43ff0c18 7853 #define LLWU_ME_WUME1_MASK 0x2u
mbed_official 146:f64d43ff0c18 7854 #define LLWU_ME_WUME1_SHIFT 1
mbed_official 146:f64d43ff0c18 7855 #define LLWU_ME_WUME2_MASK 0x4u
mbed_official 146:f64d43ff0c18 7856 #define LLWU_ME_WUME2_SHIFT 2
mbed_official 146:f64d43ff0c18 7857 #define LLWU_ME_WUME3_MASK 0x8u
mbed_official 146:f64d43ff0c18 7858 #define LLWU_ME_WUME3_SHIFT 3
mbed_official 146:f64d43ff0c18 7859 #define LLWU_ME_WUME4_MASK 0x10u
mbed_official 146:f64d43ff0c18 7860 #define LLWU_ME_WUME4_SHIFT 4
mbed_official 146:f64d43ff0c18 7861 #define LLWU_ME_WUME5_MASK 0x20u
mbed_official 146:f64d43ff0c18 7862 #define LLWU_ME_WUME5_SHIFT 5
mbed_official 146:f64d43ff0c18 7863 #define LLWU_ME_WUME6_MASK 0x40u
mbed_official 146:f64d43ff0c18 7864 #define LLWU_ME_WUME6_SHIFT 6
mbed_official 146:f64d43ff0c18 7865 #define LLWU_ME_WUME7_MASK 0x80u
mbed_official 146:f64d43ff0c18 7866 #define LLWU_ME_WUME7_SHIFT 7
mbed_official 146:f64d43ff0c18 7867 /* F1 Bit Fields */
mbed_official 146:f64d43ff0c18 7868 #define LLWU_F1_WUF0_MASK 0x1u
mbed_official 146:f64d43ff0c18 7869 #define LLWU_F1_WUF0_SHIFT 0
mbed_official 146:f64d43ff0c18 7870 #define LLWU_F1_WUF1_MASK 0x2u
mbed_official 146:f64d43ff0c18 7871 #define LLWU_F1_WUF1_SHIFT 1
mbed_official 146:f64d43ff0c18 7872 #define LLWU_F1_WUF2_MASK 0x4u
mbed_official 146:f64d43ff0c18 7873 #define LLWU_F1_WUF2_SHIFT 2
mbed_official 146:f64d43ff0c18 7874 #define LLWU_F1_WUF3_MASK 0x8u
mbed_official 146:f64d43ff0c18 7875 #define LLWU_F1_WUF3_SHIFT 3
mbed_official 146:f64d43ff0c18 7876 #define LLWU_F1_WUF4_MASK 0x10u
mbed_official 146:f64d43ff0c18 7877 #define LLWU_F1_WUF4_SHIFT 4
mbed_official 146:f64d43ff0c18 7878 #define LLWU_F1_WUF5_MASK 0x20u
mbed_official 146:f64d43ff0c18 7879 #define LLWU_F1_WUF5_SHIFT 5
mbed_official 146:f64d43ff0c18 7880 #define LLWU_F1_WUF6_MASK 0x40u
mbed_official 146:f64d43ff0c18 7881 #define LLWU_F1_WUF6_SHIFT 6
mbed_official 146:f64d43ff0c18 7882 #define LLWU_F1_WUF7_MASK 0x80u
mbed_official 146:f64d43ff0c18 7883 #define LLWU_F1_WUF7_SHIFT 7
mbed_official 146:f64d43ff0c18 7884 /* F2 Bit Fields */
mbed_official 146:f64d43ff0c18 7885 #define LLWU_F2_WUF8_MASK 0x1u
mbed_official 146:f64d43ff0c18 7886 #define LLWU_F2_WUF8_SHIFT 0
mbed_official 146:f64d43ff0c18 7887 #define LLWU_F2_WUF9_MASK 0x2u
mbed_official 146:f64d43ff0c18 7888 #define LLWU_F2_WUF9_SHIFT 1
mbed_official 146:f64d43ff0c18 7889 #define LLWU_F2_WUF10_MASK 0x4u
mbed_official 146:f64d43ff0c18 7890 #define LLWU_F2_WUF10_SHIFT 2
mbed_official 146:f64d43ff0c18 7891 #define LLWU_F2_WUF11_MASK 0x8u
mbed_official 146:f64d43ff0c18 7892 #define LLWU_F2_WUF11_SHIFT 3
mbed_official 146:f64d43ff0c18 7893 #define LLWU_F2_WUF12_MASK 0x10u
mbed_official 146:f64d43ff0c18 7894 #define LLWU_F2_WUF12_SHIFT 4
mbed_official 146:f64d43ff0c18 7895 #define LLWU_F2_WUF13_MASK 0x20u
mbed_official 146:f64d43ff0c18 7896 #define LLWU_F2_WUF13_SHIFT 5
mbed_official 146:f64d43ff0c18 7897 #define LLWU_F2_WUF14_MASK 0x40u
mbed_official 146:f64d43ff0c18 7898 #define LLWU_F2_WUF14_SHIFT 6
mbed_official 146:f64d43ff0c18 7899 #define LLWU_F2_WUF15_MASK 0x80u
mbed_official 146:f64d43ff0c18 7900 #define LLWU_F2_WUF15_SHIFT 7
mbed_official 146:f64d43ff0c18 7901 /* F3 Bit Fields */
mbed_official 146:f64d43ff0c18 7902 #define LLWU_F3_MWUF0_MASK 0x1u
mbed_official 146:f64d43ff0c18 7903 #define LLWU_F3_MWUF0_SHIFT 0
mbed_official 146:f64d43ff0c18 7904 #define LLWU_F3_MWUF1_MASK 0x2u
mbed_official 146:f64d43ff0c18 7905 #define LLWU_F3_MWUF1_SHIFT 1
mbed_official 146:f64d43ff0c18 7906 #define LLWU_F3_MWUF2_MASK 0x4u
mbed_official 146:f64d43ff0c18 7907 #define LLWU_F3_MWUF2_SHIFT 2
mbed_official 146:f64d43ff0c18 7908 #define LLWU_F3_MWUF3_MASK 0x8u
mbed_official 146:f64d43ff0c18 7909 #define LLWU_F3_MWUF3_SHIFT 3
mbed_official 146:f64d43ff0c18 7910 #define LLWU_F3_MWUF4_MASK 0x10u
mbed_official 146:f64d43ff0c18 7911 #define LLWU_F3_MWUF4_SHIFT 4
mbed_official 146:f64d43ff0c18 7912 #define LLWU_F3_MWUF5_MASK 0x20u
mbed_official 146:f64d43ff0c18 7913 #define LLWU_F3_MWUF5_SHIFT 5
mbed_official 146:f64d43ff0c18 7914 #define LLWU_F3_MWUF6_MASK 0x40u
mbed_official 146:f64d43ff0c18 7915 #define LLWU_F3_MWUF6_SHIFT 6
mbed_official 146:f64d43ff0c18 7916 #define LLWU_F3_MWUF7_MASK 0x80u
mbed_official 146:f64d43ff0c18 7917 #define LLWU_F3_MWUF7_SHIFT 7
mbed_official 146:f64d43ff0c18 7918 /* FILT1 Bit Fields */
mbed_official 146:f64d43ff0c18 7919 #define LLWU_FILT1_FILTSEL_MASK 0xFu
mbed_official 146:f64d43ff0c18 7920 #define LLWU_FILT1_FILTSEL_SHIFT 0
mbed_official 146:f64d43ff0c18 7921 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
mbed_official 146:f64d43ff0c18 7922 #define LLWU_FILT1_FILTE_MASK 0x60u
mbed_official 146:f64d43ff0c18 7923 #define LLWU_FILT1_FILTE_SHIFT 5
mbed_official 146:f64d43ff0c18 7924 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
mbed_official 146:f64d43ff0c18 7925 #define LLWU_FILT1_FILTF_MASK 0x80u
mbed_official 146:f64d43ff0c18 7926 #define LLWU_FILT1_FILTF_SHIFT 7
mbed_official 146:f64d43ff0c18 7927 /* FILT2 Bit Fields */
mbed_official 146:f64d43ff0c18 7928 #define LLWU_FILT2_FILTSEL_MASK 0xFu
mbed_official 146:f64d43ff0c18 7929 #define LLWU_FILT2_FILTSEL_SHIFT 0
mbed_official 146:f64d43ff0c18 7930 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
mbed_official 146:f64d43ff0c18 7931 #define LLWU_FILT2_FILTE_MASK 0x60u
mbed_official 146:f64d43ff0c18 7932 #define LLWU_FILT2_FILTE_SHIFT 5
mbed_official 146:f64d43ff0c18 7933 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
mbed_official 146:f64d43ff0c18 7934 #define LLWU_FILT2_FILTF_MASK 0x80u
mbed_official 146:f64d43ff0c18 7935 #define LLWU_FILT2_FILTF_SHIFT 7
mbed_official 146:f64d43ff0c18 7936 /* RST Bit Fields */
mbed_official 146:f64d43ff0c18 7937 #define LLWU_RST_RSTFILT_MASK 0x1u
mbed_official 146:f64d43ff0c18 7938 #define LLWU_RST_RSTFILT_SHIFT 0
mbed_official 146:f64d43ff0c18 7939 #define LLWU_RST_LLRSTE_MASK 0x2u
mbed_official 146:f64d43ff0c18 7940 #define LLWU_RST_LLRSTE_SHIFT 1
mbed_official 146:f64d43ff0c18 7941
mbed_official 146:f64d43ff0c18 7942 /*!
mbed_official 146:f64d43ff0c18 7943 * @}
mbed_official 146:f64d43ff0c18 7944 */ /* end of group LLWU_Register_Masks */
mbed_official 146:f64d43ff0c18 7945
mbed_official 146:f64d43ff0c18 7946
mbed_official 146:f64d43ff0c18 7947 /* LLWU - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 7948 /** Peripheral LLWU base address */
mbed_official 146:f64d43ff0c18 7949 #define LLWU_BASE (0x4007C000u)
mbed_official 146:f64d43ff0c18 7950 /** Peripheral LLWU base pointer */
mbed_official 146:f64d43ff0c18 7951 #define LLWU ((LLWU_Type *)LLWU_BASE)
mbed_official 146:f64d43ff0c18 7952 #define LLWU_BASE_PTR (LLWU)
mbed_official 146:f64d43ff0c18 7953 /** Array initializer of LLWU peripheral base pointers */
mbed_official 146:f64d43ff0c18 7954 #define LLWU_BASES { LLWU }
mbed_official 146:f64d43ff0c18 7955
mbed_official 146:f64d43ff0c18 7956 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 7957 -- LLWU - Register accessor macros
mbed_official 146:f64d43ff0c18 7958 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 7959
mbed_official 146:f64d43ff0c18 7960 /*!
mbed_official 146:f64d43ff0c18 7961 * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
mbed_official 146:f64d43ff0c18 7962 * @{
mbed_official 146:f64d43ff0c18 7963 */
mbed_official 146:f64d43ff0c18 7964
mbed_official 146:f64d43ff0c18 7965
mbed_official 146:f64d43ff0c18 7966 /* LLWU - Register instance definitions */
mbed_official 146:f64d43ff0c18 7967 /* LLWU */
mbed_official 146:f64d43ff0c18 7968 #define LLWU_PE1 LLWU_PE1_REG(LLWU)
mbed_official 146:f64d43ff0c18 7969 #define LLWU_PE2 LLWU_PE2_REG(LLWU)
mbed_official 146:f64d43ff0c18 7970 #define LLWU_PE3 LLWU_PE3_REG(LLWU)
mbed_official 146:f64d43ff0c18 7971 #define LLWU_PE4 LLWU_PE4_REG(LLWU)
mbed_official 146:f64d43ff0c18 7972 #define LLWU_ME LLWU_ME_REG(LLWU)
mbed_official 146:f64d43ff0c18 7973 #define LLWU_F1 LLWU_F1_REG(LLWU)
mbed_official 146:f64d43ff0c18 7974 #define LLWU_F2 LLWU_F2_REG(LLWU)
mbed_official 146:f64d43ff0c18 7975 #define LLWU_F3 LLWU_F3_REG(LLWU)
mbed_official 146:f64d43ff0c18 7976 #define LLWU_FILT1 LLWU_FILT1_REG(LLWU)
mbed_official 146:f64d43ff0c18 7977 #define LLWU_FILT2 LLWU_FILT2_REG(LLWU)
mbed_official 146:f64d43ff0c18 7978 #define LLWU_RST LLWU_RST_REG(LLWU)
mbed_official 146:f64d43ff0c18 7979
mbed_official 146:f64d43ff0c18 7980 /*!
mbed_official 146:f64d43ff0c18 7981 * @}
mbed_official 146:f64d43ff0c18 7982 */ /* end of group LLWU_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 7983
mbed_official 146:f64d43ff0c18 7984
mbed_official 146:f64d43ff0c18 7985 /*!
mbed_official 146:f64d43ff0c18 7986 * @}
mbed_official 146:f64d43ff0c18 7987 */ /* end of group LLWU_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 7988
mbed_official 146:f64d43ff0c18 7989
mbed_official 146:f64d43ff0c18 7990 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 7991 -- LPTMR Peripheral Access Layer
mbed_official 146:f64d43ff0c18 7992 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 7993
mbed_official 146:f64d43ff0c18 7994 /*!
mbed_official 146:f64d43ff0c18 7995 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
mbed_official 146:f64d43ff0c18 7996 * @{
mbed_official 146:f64d43ff0c18 7997 */
mbed_official 146:f64d43ff0c18 7998
mbed_official 146:f64d43ff0c18 7999 /** LPTMR - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 8000 typedef struct {
mbed_official 146:f64d43ff0c18 8001 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
mbed_official 146:f64d43ff0c18 8002 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
mbed_official 146:f64d43ff0c18 8003 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
mbed_official 146:f64d43ff0c18 8004 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
mbed_official 146:f64d43ff0c18 8005 } LPTMR_Type, *LPTMR_MemMapPtr;
mbed_official 146:f64d43ff0c18 8006
mbed_official 146:f64d43ff0c18 8007 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 8008 -- LPTMR - Register accessor macros
mbed_official 146:f64d43ff0c18 8009 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 8010
mbed_official 146:f64d43ff0c18 8011 /*!
mbed_official 146:f64d43ff0c18 8012 * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
mbed_official 146:f64d43ff0c18 8013 * @{
mbed_official 146:f64d43ff0c18 8014 */
mbed_official 146:f64d43ff0c18 8015
mbed_official 146:f64d43ff0c18 8016
mbed_official 146:f64d43ff0c18 8017 /* LPTMR - Register accessors */
mbed_official 146:f64d43ff0c18 8018 #define LPTMR_CSR_REG(base) ((base)->CSR)
mbed_official 146:f64d43ff0c18 8019 #define LPTMR_PSR_REG(base) ((base)->PSR)
mbed_official 146:f64d43ff0c18 8020 #define LPTMR_CMR_REG(base) ((base)->CMR)
mbed_official 146:f64d43ff0c18 8021 #define LPTMR_CNR_REG(base) ((base)->CNR)
mbed_official 146:f64d43ff0c18 8022
mbed_official 146:f64d43ff0c18 8023 /*!
mbed_official 146:f64d43ff0c18 8024 * @}
mbed_official 146:f64d43ff0c18 8025 */ /* end of group LPTMR_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 8026
mbed_official 146:f64d43ff0c18 8027
mbed_official 146:f64d43ff0c18 8028 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 8029 -- LPTMR Register Masks
mbed_official 146:f64d43ff0c18 8030 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 8031
mbed_official 146:f64d43ff0c18 8032 /*!
mbed_official 146:f64d43ff0c18 8033 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
mbed_official 146:f64d43ff0c18 8034 * @{
mbed_official 146:f64d43ff0c18 8035 */
mbed_official 146:f64d43ff0c18 8036
mbed_official 146:f64d43ff0c18 8037 /* CSR Bit Fields */
mbed_official 146:f64d43ff0c18 8038 #define LPTMR_CSR_TEN_MASK 0x1u
mbed_official 146:f64d43ff0c18 8039 #define LPTMR_CSR_TEN_SHIFT 0
mbed_official 146:f64d43ff0c18 8040 #define LPTMR_CSR_TMS_MASK 0x2u
mbed_official 146:f64d43ff0c18 8041 #define LPTMR_CSR_TMS_SHIFT 1
mbed_official 146:f64d43ff0c18 8042 #define LPTMR_CSR_TFC_MASK 0x4u
mbed_official 146:f64d43ff0c18 8043 #define LPTMR_CSR_TFC_SHIFT 2
mbed_official 146:f64d43ff0c18 8044 #define LPTMR_CSR_TPP_MASK 0x8u
mbed_official 146:f64d43ff0c18 8045 #define LPTMR_CSR_TPP_SHIFT 3
mbed_official 146:f64d43ff0c18 8046 #define LPTMR_CSR_TPS_MASK 0x30u
mbed_official 146:f64d43ff0c18 8047 #define LPTMR_CSR_TPS_SHIFT 4
mbed_official 146:f64d43ff0c18 8048 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
mbed_official 146:f64d43ff0c18 8049 #define LPTMR_CSR_TIE_MASK 0x40u
mbed_official 146:f64d43ff0c18 8050 #define LPTMR_CSR_TIE_SHIFT 6
mbed_official 146:f64d43ff0c18 8051 #define LPTMR_CSR_TCF_MASK 0x80u
mbed_official 146:f64d43ff0c18 8052 #define LPTMR_CSR_TCF_SHIFT 7
mbed_official 146:f64d43ff0c18 8053 /* PSR Bit Fields */
mbed_official 146:f64d43ff0c18 8054 #define LPTMR_PSR_PCS_MASK 0x3u
mbed_official 146:f64d43ff0c18 8055 #define LPTMR_PSR_PCS_SHIFT 0
mbed_official 146:f64d43ff0c18 8056 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
mbed_official 146:f64d43ff0c18 8057 #define LPTMR_PSR_PBYP_MASK 0x4u
mbed_official 146:f64d43ff0c18 8058 #define LPTMR_PSR_PBYP_SHIFT 2
mbed_official 146:f64d43ff0c18 8059 #define LPTMR_PSR_PRESCALE_MASK 0x78u
mbed_official 146:f64d43ff0c18 8060 #define LPTMR_PSR_PRESCALE_SHIFT 3
mbed_official 146:f64d43ff0c18 8061 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
mbed_official 146:f64d43ff0c18 8062 /* CMR Bit Fields */
mbed_official 146:f64d43ff0c18 8063 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 8064 #define LPTMR_CMR_COMPARE_SHIFT 0
mbed_official 146:f64d43ff0c18 8065 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
mbed_official 146:f64d43ff0c18 8066 /* CNR Bit Fields */
mbed_official 146:f64d43ff0c18 8067 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 8068 #define LPTMR_CNR_COUNTER_SHIFT 0
mbed_official 146:f64d43ff0c18 8069 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
mbed_official 146:f64d43ff0c18 8070
mbed_official 146:f64d43ff0c18 8071 /*!
mbed_official 146:f64d43ff0c18 8072 * @}
mbed_official 146:f64d43ff0c18 8073 */ /* end of group LPTMR_Register_Masks */
mbed_official 146:f64d43ff0c18 8074
mbed_official 146:f64d43ff0c18 8075
mbed_official 146:f64d43ff0c18 8076 /* LPTMR - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 8077 /** Peripheral LPTMR0 base address */
mbed_official 146:f64d43ff0c18 8078 #define LPTMR0_BASE (0x40040000u)
mbed_official 146:f64d43ff0c18 8079 /** Peripheral LPTMR0 base pointer */
mbed_official 146:f64d43ff0c18 8080 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
mbed_official 146:f64d43ff0c18 8081 #define LPTMR0_BASE_PTR (LPTMR0)
mbed_official 146:f64d43ff0c18 8082 /** Array initializer of LPTMR peripheral base pointers */
mbed_official 146:f64d43ff0c18 8083 #define LPTMR_BASES { LPTMR0 }
mbed_official 146:f64d43ff0c18 8084
mbed_official 146:f64d43ff0c18 8085 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 8086 -- LPTMR - Register accessor macros
mbed_official 146:f64d43ff0c18 8087 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 8088
mbed_official 146:f64d43ff0c18 8089 /*!
mbed_official 146:f64d43ff0c18 8090 * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
mbed_official 146:f64d43ff0c18 8091 * @{
mbed_official 146:f64d43ff0c18 8092 */
mbed_official 146:f64d43ff0c18 8093
mbed_official 146:f64d43ff0c18 8094
mbed_official 146:f64d43ff0c18 8095 /* LPTMR - Register instance definitions */
mbed_official 146:f64d43ff0c18 8096 /* LPTMR0 */
mbed_official 146:f64d43ff0c18 8097 #define LPTMR0_CSR LPTMR_CSR_REG(LPTMR0)
mbed_official 146:f64d43ff0c18 8098 #define LPTMR0_PSR LPTMR_PSR_REG(LPTMR0)
mbed_official 146:f64d43ff0c18 8099 #define LPTMR0_CMR LPTMR_CMR_REG(LPTMR0)
mbed_official 146:f64d43ff0c18 8100 #define LPTMR0_CNR LPTMR_CNR_REG(LPTMR0)
mbed_official 146:f64d43ff0c18 8101
mbed_official 146:f64d43ff0c18 8102 /*!
mbed_official 146:f64d43ff0c18 8103 * @}
mbed_official 146:f64d43ff0c18 8104 */ /* end of group LPTMR_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 8105
mbed_official 146:f64d43ff0c18 8106
mbed_official 146:f64d43ff0c18 8107 /*!
mbed_official 146:f64d43ff0c18 8108 * @}
mbed_official 146:f64d43ff0c18 8109 */ /* end of group LPTMR_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 8110
mbed_official 146:f64d43ff0c18 8111
mbed_official 146:f64d43ff0c18 8112 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 8113 -- MCG Peripheral Access Layer
mbed_official 146:f64d43ff0c18 8114 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 8115
mbed_official 146:f64d43ff0c18 8116 /*!
mbed_official 146:f64d43ff0c18 8117 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
mbed_official 146:f64d43ff0c18 8118 * @{
mbed_official 146:f64d43ff0c18 8119 */
mbed_official 146:f64d43ff0c18 8120
mbed_official 146:f64d43ff0c18 8121 /** MCG - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 8122 typedef struct {
mbed_official 146:f64d43ff0c18 8123 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
mbed_official 146:f64d43ff0c18 8124 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
mbed_official 146:f64d43ff0c18 8125 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
mbed_official 146:f64d43ff0c18 8126 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
mbed_official 146:f64d43ff0c18 8127 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
mbed_official 146:f64d43ff0c18 8128 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
mbed_official 146:f64d43ff0c18 8129 __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */
mbed_official 146:f64d43ff0c18 8130 uint8_t RESERVED_0[1];
mbed_official 146:f64d43ff0c18 8131 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
mbed_official 146:f64d43ff0c18 8132 uint8_t RESERVED_1[1];
mbed_official 146:f64d43ff0c18 8133 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
mbed_official 146:f64d43ff0c18 8134 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
mbed_official 146:f64d43ff0c18 8135 __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
mbed_official 146:f64d43ff0c18 8136 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
mbed_official 146:f64d43ff0c18 8137 } MCG_Type, *MCG_MemMapPtr;
mbed_official 146:f64d43ff0c18 8138
mbed_official 146:f64d43ff0c18 8139 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 8140 -- MCG - Register accessor macros
mbed_official 146:f64d43ff0c18 8141 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 8142
mbed_official 146:f64d43ff0c18 8143 /*!
mbed_official 146:f64d43ff0c18 8144 * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
mbed_official 146:f64d43ff0c18 8145 * @{
mbed_official 146:f64d43ff0c18 8146 */
mbed_official 146:f64d43ff0c18 8147
mbed_official 146:f64d43ff0c18 8148
mbed_official 146:f64d43ff0c18 8149 /* MCG - Register accessors */
mbed_official 146:f64d43ff0c18 8150 #define MCG_C1_REG(base) ((base)->C1)
mbed_official 146:f64d43ff0c18 8151 #define MCG_C2_REG(base) ((base)->C2)
mbed_official 146:f64d43ff0c18 8152 #define MCG_C3_REG(base) ((base)->C3)
mbed_official 146:f64d43ff0c18 8153 #define MCG_C4_REG(base) ((base)->C4)
mbed_official 146:f64d43ff0c18 8154 #define MCG_C5_REG(base) ((base)->C5)
mbed_official 146:f64d43ff0c18 8155 #define MCG_C6_REG(base) ((base)->C6)
mbed_official 146:f64d43ff0c18 8156 #define MCG_S_REG(base) ((base)->S)
mbed_official 146:f64d43ff0c18 8157 #define MCG_SC_REG(base) ((base)->SC)
mbed_official 146:f64d43ff0c18 8158 #define MCG_ATCVH_REG(base) ((base)->ATCVH)
mbed_official 146:f64d43ff0c18 8159 #define MCG_ATCVL_REG(base) ((base)->ATCVL)
mbed_official 146:f64d43ff0c18 8160 #define MCG_C7_REG(base) ((base)->C7)
mbed_official 146:f64d43ff0c18 8161 #define MCG_C8_REG(base) ((base)->C8)
mbed_official 146:f64d43ff0c18 8162
mbed_official 146:f64d43ff0c18 8163 /*!
mbed_official 146:f64d43ff0c18 8164 * @}
mbed_official 146:f64d43ff0c18 8165 */ /* end of group MCG_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 8166
mbed_official 146:f64d43ff0c18 8167
mbed_official 146:f64d43ff0c18 8168 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 8169 -- MCG Register Masks
mbed_official 146:f64d43ff0c18 8170 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 8171
mbed_official 146:f64d43ff0c18 8172 /*!
mbed_official 146:f64d43ff0c18 8173 * @addtogroup MCG_Register_Masks MCG Register Masks
mbed_official 146:f64d43ff0c18 8174 * @{
mbed_official 146:f64d43ff0c18 8175 */
mbed_official 146:f64d43ff0c18 8176
mbed_official 146:f64d43ff0c18 8177 /* C1 Bit Fields */
mbed_official 146:f64d43ff0c18 8178 #define MCG_C1_IREFSTEN_MASK 0x1u
mbed_official 146:f64d43ff0c18 8179 #define MCG_C1_IREFSTEN_SHIFT 0
mbed_official 146:f64d43ff0c18 8180 #define MCG_C1_IRCLKEN_MASK 0x2u
mbed_official 146:f64d43ff0c18 8181 #define MCG_C1_IRCLKEN_SHIFT 1
mbed_official 146:f64d43ff0c18 8182 #define MCG_C1_IREFS_MASK 0x4u
mbed_official 146:f64d43ff0c18 8183 #define MCG_C1_IREFS_SHIFT 2
mbed_official 146:f64d43ff0c18 8184 #define MCG_C1_FRDIV_MASK 0x38u
mbed_official 146:f64d43ff0c18 8185 #define MCG_C1_FRDIV_SHIFT 3
mbed_official 146:f64d43ff0c18 8186 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
mbed_official 146:f64d43ff0c18 8187 #define MCG_C1_CLKS_MASK 0xC0u
mbed_official 146:f64d43ff0c18 8188 #define MCG_C1_CLKS_SHIFT 6
mbed_official 146:f64d43ff0c18 8189 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
mbed_official 146:f64d43ff0c18 8190 /* C2 Bit Fields */
mbed_official 146:f64d43ff0c18 8191 #define MCG_C2_IRCS_MASK 0x1u
mbed_official 146:f64d43ff0c18 8192 #define MCG_C2_IRCS_SHIFT 0
mbed_official 146:f64d43ff0c18 8193 #define MCG_C2_LP_MASK 0x2u
mbed_official 146:f64d43ff0c18 8194 #define MCG_C2_LP_SHIFT 1
mbed_official 146:f64d43ff0c18 8195 #define MCG_C2_EREFS_MASK 0x4u
mbed_official 146:f64d43ff0c18 8196 #define MCG_C2_EREFS_SHIFT 2
mbed_official 146:f64d43ff0c18 8197 #define MCG_C2_HGO_MASK 0x8u
mbed_official 146:f64d43ff0c18 8198 #define MCG_C2_HGO_SHIFT 3
mbed_official 146:f64d43ff0c18 8199 #define MCG_C2_RANGE_MASK 0x30u
mbed_official 146:f64d43ff0c18 8200 #define MCG_C2_RANGE_SHIFT 4
mbed_official 146:f64d43ff0c18 8201 #define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE_SHIFT))&MCG_C2_RANGE_MASK)
mbed_official 146:f64d43ff0c18 8202 #define MCG_C2_FCFTRIM_MASK 0x40u
mbed_official 146:f64d43ff0c18 8203 #define MCG_C2_FCFTRIM_SHIFT 6
mbed_official 146:f64d43ff0c18 8204 #define MCG_C2_LOCRE0_MASK 0x80u
mbed_official 146:f64d43ff0c18 8205 #define MCG_C2_LOCRE0_SHIFT 7
mbed_official 146:f64d43ff0c18 8206 /* C3 Bit Fields */
mbed_official 146:f64d43ff0c18 8207 #define MCG_C3_SCTRIM_MASK 0xFFu
mbed_official 146:f64d43ff0c18 8208 #define MCG_C3_SCTRIM_SHIFT 0
mbed_official 146:f64d43ff0c18 8209 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
mbed_official 146:f64d43ff0c18 8210 /* C4 Bit Fields */
mbed_official 146:f64d43ff0c18 8211 #define MCG_C4_SCFTRIM_MASK 0x1u
mbed_official 146:f64d43ff0c18 8212 #define MCG_C4_SCFTRIM_SHIFT 0
mbed_official 146:f64d43ff0c18 8213 #define MCG_C4_FCTRIM_MASK 0x1Eu
mbed_official 146:f64d43ff0c18 8214 #define MCG_C4_FCTRIM_SHIFT 1
mbed_official 146:f64d43ff0c18 8215 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
mbed_official 146:f64d43ff0c18 8216 #define MCG_C4_DRST_DRS_MASK 0x60u
mbed_official 146:f64d43ff0c18 8217 #define MCG_C4_DRST_DRS_SHIFT 5
mbed_official 146:f64d43ff0c18 8218 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
mbed_official 146:f64d43ff0c18 8219 #define MCG_C4_DMX32_MASK 0x80u
mbed_official 146:f64d43ff0c18 8220 #define MCG_C4_DMX32_SHIFT 7
mbed_official 146:f64d43ff0c18 8221 /* C5 Bit Fields */
mbed_official 146:f64d43ff0c18 8222 #define MCG_C5_PRDIV0_MASK 0x1Fu
mbed_official 146:f64d43ff0c18 8223 #define MCG_C5_PRDIV0_SHIFT 0
mbed_official 146:f64d43ff0c18 8224 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
mbed_official 146:f64d43ff0c18 8225 #define MCG_C5_PLLSTEN0_MASK 0x20u
mbed_official 146:f64d43ff0c18 8226 #define MCG_C5_PLLSTEN0_SHIFT 5
mbed_official 146:f64d43ff0c18 8227 #define MCG_C5_PLLCLKEN0_MASK 0x40u
mbed_official 146:f64d43ff0c18 8228 #define MCG_C5_PLLCLKEN0_SHIFT 6
mbed_official 146:f64d43ff0c18 8229 /* C6 Bit Fields */
mbed_official 146:f64d43ff0c18 8230 #define MCG_C6_VDIV0_MASK 0x1Fu
mbed_official 146:f64d43ff0c18 8231 #define MCG_C6_VDIV0_SHIFT 0
mbed_official 146:f64d43ff0c18 8232 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
mbed_official 146:f64d43ff0c18 8233 #define MCG_C6_CME0_MASK 0x20u
mbed_official 146:f64d43ff0c18 8234 #define MCG_C6_CME0_SHIFT 5
mbed_official 146:f64d43ff0c18 8235 #define MCG_C6_PLLS_MASK 0x40u
mbed_official 146:f64d43ff0c18 8236 #define MCG_C6_PLLS_SHIFT 6
mbed_official 146:f64d43ff0c18 8237 #define MCG_C6_LOLIE0_MASK 0x80u
mbed_official 146:f64d43ff0c18 8238 #define MCG_C6_LOLIE0_SHIFT 7
mbed_official 146:f64d43ff0c18 8239 /* S Bit Fields */
mbed_official 146:f64d43ff0c18 8240 #define MCG_S_IRCST_MASK 0x1u
mbed_official 146:f64d43ff0c18 8241 #define MCG_S_IRCST_SHIFT 0
mbed_official 146:f64d43ff0c18 8242 #define MCG_S_OSCINIT0_MASK 0x2u
mbed_official 146:f64d43ff0c18 8243 #define MCG_S_OSCINIT0_SHIFT 1
mbed_official 146:f64d43ff0c18 8244 #define MCG_S_CLKST_MASK 0xCu
mbed_official 146:f64d43ff0c18 8245 #define MCG_S_CLKST_SHIFT 2
mbed_official 146:f64d43ff0c18 8246 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
mbed_official 146:f64d43ff0c18 8247 #define MCG_S_IREFST_MASK 0x10u
mbed_official 146:f64d43ff0c18 8248 #define MCG_S_IREFST_SHIFT 4
mbed_official 146:f64d43ff0c18 8249 #define MCG_S_PLLST_MASK 0x20u
mbed_official 146:f64d43ff0c18 8250 #define MCG_S_PLLST_SHIFT 5
mbed_official 146:f64d43ff0c18 8251 #define MCG_S_LOCK0_MASK 0x40u
mbed_official 146:f64d43ff0c18 8252 #define MCG_S_LOCK0_SHIFT 6
mbed_official 146:f64d43ff0c18 8253 #define MCG_S_LOLS0_MASK 0x80u
mbed_official 146:f64d43ff0c18 8254 #define MCG_S_LOLS0_SHIFT 7
mbed_official 146:f64d43ff0c18 8255 /* SC Bit Fields */
mbed_official 146:f64d43ff0c18 8256 #define MCG_SC_LOCS0_MASK 0x1u
mbed_official 146:f64d43ff0c18 8257 #define MCG_SC_LOCS0_SHIFT 0
mbed_official 146:f64d43ff0c18 8258 #define MCG_SC_FCRDIV_MASK 0xEu
mbed_official 146:f64d43ff0c18 8259 #define MCG_SC_FCRDIV_SHIFT 1
mbed_official 146:f64d43ff0c18 8260 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
mbed_official 146:f64d43ff0c18 8261 #define MCG_SC_FLTPRSRV_MASK 0x10u
mbed_official 146:f64d43ff0c18 8262 #define MCG_SC_FLTPRSRV_SHIFT 4
mbed_official 146:f64d43ff0c18 8263 #define MCG_SC_ATMF_MASK 0x20u
mbed_official 146:f64d43ff0c18 8264 #define MCG_SC_ATMF_SHIFT 5
mbed_official 146:f64d43ff0c18 8265 #define MCG_SC_ATMS_MASK 0x40u
mbed_official 146:f64d43ff0c18 8266 #define MCG_SC_ATMS_SHIFT 6
mbed_official 146:f64d43ff0c18 8267 #define MCG_SC_ATME_MASK 0x80u
mbed_official 146:f64d43ff0c18 8268 #define MCG_SC_ATME_SHIFT 7
mbed_official 146:f64d43ff0c18 8269 /* ATCVH Bit Fields */
mbed_official 146:f64d43ff0c18 8270 #define MCG_ATCVH_ATCVH_MASK 0xFFu
mbed_official 146:f64d43ff0c18 8271 #define MCG_ATCVH_ATCVH_SHIFT 0
mbed_official 146:f64d43ff0c18 8272 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
mbed_official 146:f64d43ff0c18 8273 /* ATCVL Bit Fields */
mbed_official 146:f64d43ff0c18 8274 #define MCG_ATCVL_ATCVL_MASK 0xFFu
mbed_official 146:f64d43ff0c18 8275 #define MCG_ATCVL_ATCVL_SHIFT 0
mbed_official 146:f64d43ff0c18 8276 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
mbed_official 146:f64d43ff0c18 8277 /* C7 Bit Fields */
mbed_official 146:f64d43ff0c18 8278 #define MCG_C7_OSCSEL_MASK 0x3u
mbed_official 146:f64d43ff0c18 8279 #define MCG_C7_OSCSEL_SHIFT 0
mbed_official 146:f64d43ff0c18 8280 #define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x))<<MCG_C7_OSCSEL_SHIFT))&MCG_C7_OSCSEL_MASK)
mbed_official 146:f64d43ff0c18 8281 /* C8 Bit Fields */
mbed_official 146:f64d43ff0c18 8282 #define MCG_C8_LOCS1_MASK 0x1u
mbed_official 146:f64d43ff0c18 8283 #define MCG_C8_LOCS1_SHIFT 0
mbed_official 146:f64d43ff0c18 8284 #define MCG_C8_CME1_MASK 0x20u
mbed_official 146:f64d43ff0c18 8285 #define MCG_C8_CME1_SHIFT 5
mbed_official 146:f64d43ff0c18 8286 #define MCG_C8_LOLRE_MASK 0x40u
mbed_official 146:f64d43ff0c18 8287 #define MCG_C8_LOLRE_SHIFT 6
mbed_official 146:f64d43ff0c18 8288 #define MCG_C8_LOCRE1_MASK 0x80u
mbed_official 146:f64d43ff0c18 8289 #define MCG_C8_LOCRE1_SHIFT 7
mbed_official 146:f64d43ff0c18 8290
mbed_official 146:f64d43ff0c18 8291 /*!
mbed_official 146:f64d43ff0c18 8292 * @}
mbed_official 146:f64d43ff0c18 8293 */ /* end of group MCG_Register_Masks */
mbed_official 146:f64d43ff0c18 8294
mbed_official 146:f64d43ff0c18 8295
mbed_official 146:f64d43ff0c18 8296 /* MCG - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 8297 /** Peripheral MCG base address */
mbed_official 146:f64d43ff0c18 8298 #define MCG_BASE (0x40064000u)
mbed_official 146:f64d43ff0c18 8299 /** Peripheral MCG base pointer */
mbed_official 146:f64d43ff0c18 8300 #define MCG ((MCG_Type *)MCG_BASE)
mbed_official 146:f64d43ff0c18 8301 #define MCG_BASE_PTR (MCG)
mbed_official 146:f64d43ff0c18 8302 /** Array initializer of MCG peripheral base pointers */
mbed_official 146:f64d43ff0c18 8303 #define MCG_BASES { MCG }
mbed_official 146:f64d43ff0c18 8304
mbed_official 146:f64d43ff0c18 8305 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 8306 -- MCG - Register accessor macros
mbed_official 146:f64d43ff0c18 8307 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 8308
mbed_official 146:f64d43ff0c18 8309 /*!
mbed_official 146:f64d43ff0c18 8310 * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
mbed_official 146:f64d43ff0c18 8311 * @{
mbed_official 146:f64d43ff0c18 8312 */
mbed_official 146:f64d43ff0c18 8313
mbed_official 146:f64d43ff0c18 8314
mbed_official 146:f64d43ff0c18 8315 /* MCG - Register instance definitions */
mbed_official 146:f64d43ff0c18 8316 /* MCG */
mbed_official 146:f64d43ff0c18 8317 #define MCG_C1 MCG_C1_REG(MCG)
mbed_official 146:f64d43ff0c18 8318 #define MCG_C2 MCG_C2_REG(MCG)
mbed_official 146:f64d43ff0c18 8319 #define MCG_C3 MCG_C3_REG(MCG)
mbed_official 146:f64d43ff0c18 8320 #define MCG_C4 MCG_C4_REG(MCG)
mbed_official 146:f64d43ff0c18 8321 #define MCG_C5 MCG_C5_REG(MCG)
mbed_official 146:f64d43ff0c18 8322 #define MCG_C6 MCG_C6_REG(MCG)
mbed_official 146:f64d43ff0c18 8323 #define MCG_S MCG_S_REG(MCG)
mbed_official 146:f64d43ff0c18 8324 #define MCG_SC MCG_SC_REG(MCG)
mbed_official 146:f64d43ff0c18 8325 #define MCG_ATCVH MCG_ATCVH_REG(MCG)
mbed_official 146:f64d43ff0c18 8326 #define MCG_ATCVL MCG_ATCVL_REG(MCG)
mbed_official 146:f64d43ff0c18 8327 #define MCG_C7 MCG_C7_REG(MCG)
mbed_official 146:f64d43ff0c18 8328 #define MCG_C8 MCG_C8_REG(MCG)
mbed_official 146:f64d43ff0c18 8329
mbed_official 146:f64d43ff0c18 8330 /*!
mbed_official 146:f64d43ff0c18 8331 * @}
mbed_official 146:f64d43ff0c18 8332 */ /* end of group MCG_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 8333
mbed_official 146:f64d43ff0c18 8334
mbed_official 146:f64d43ff0c18 8335 /*!
mbed_official 146:f64d43ff0c18 8336 * @}
mbed_official 146:f64d43ff0c18 8337 */ /* end of group MCG_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 8338
mbed_official 146:f64d43ff0c18 8339
mbed_official 146:f64d43ff0c18 8340 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 8341 -- MCM Peripheral Access Layer
mbed_official 146:f64d43ff0c18 8342 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 8343
mbed_official 146:f64d43ff0c18 8344 /*!
mbed_official 146:f64d43ff0c18 8345 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
mbed_official 146:f64d43ff0c18 8346 * @{
mbed_official 146:f64d43ff0c18 8347 */
mbed_official 146:f64d43ff0c18 8348
mbed_official 146:f64d43ff0c18 8349 /** MCM - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 8350 typedef struct {
mbed_official 146:f64d43ff0c18 8351 uint8_t RESERVED_0[8];
mbed_official 146:f64d43ff0c18 8352 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
mbed_official 146:f64d43ff0c18 8353 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
mbed_official 146:f64d43ff0c18 8354 __IO uint32_t CR; /**< Control Register, offset: 0xC */
mbed_official 146:f64d43ff0c18 8355 __IO uint32_t ISR; /**< Interrupt Status Register, offset: 0x10 */
mbed_official 146:f64d43ff0c18 8356 __IO uint32_t ETBCC; /**< ETB Counter Control register, offset: 0x14 */
mbed_official 146:f64d43ff0c18 8357 __IO uint32_t ETBRL; /**< ETB Reload register, offset: 0x18 */
mbed_official 146:f64d43ff0c18 8358 __I uint32_t ETBCNT; /**< ETB Counter Value register, offset: 0x1C */
mbed_official 146:f64d43ff0c18 8359 uint8_t RESERVED_1[16];
mbed_official 146:f64d43ff0c18 8360 __IO uint32_t PID; /**< Process ID register, offset: 0x30 */
mbed_official 146:f64d43ff0c18 8361 } MCM_Type, *MCM_MemMapPtr;
mbed_official 146:f64d43ff0c18 8362
mbed_official 146:f64d43ff0c18 8363 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 8364 -- MCM - Register accessor macros
mbed_official 146:f64d43ff0c18 8365 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 8366
mbed_official 146:f64d43ff0c18 8367 /*!
mbed_official 146:f64d43ff0c18 8368 * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
mbed_official 146:f64d43ff0c18 8369 * @{
mbed_official 146:f64d43ff0c18 8370 */
mbed_official 146:f64d43ff0c18 8371
mbed_official 146:f64d43ff0c18 8372
mbed_official 146:f64d43ff0c18 8373 /* MCM - Register accessors */
mbed_official 146:f64d43ff0c18 8374 #define MCM_PLASC_REG(base) ((base)->PLASC)
mbed_official 146:f64d43ff0c18 8375 #define MCM_PLAMC_REG(base) ((base)->PLAMC)
mbed_official 146:f64d43ff0c18 8376 #define MCM_CR_REG(base) ((base)->CR)
mbed_official 146:f64d43ff0c18 8377 #define MCM_ISR_REG(base) ((base)->ISR)
mbed_official 146:f64d43ff0c18 8378 #define MCM_ETBCC_REG(base) ((base)->ETBCC)
mbed_official 146:f64d43ff0c18 8379 #define MCM_ETBRL_REG(base) ((base)->ETBRL)
mbed_official 146:f64d43ff0c18 8380 #define MCM_ETBCNT_REG(base) ((base)->ETBCNT)
mbed_official 146:f64d43ff0c18 8381 #define MCM_PID_REG(base) ((base)->PID)
mbed_official 146:f64d43ff0c18 8382
mbed_official 146:f64d43ff0c18 8383 /*!
mbed_official 146:f64d43ff0c18 8384 * @}
mbed_official 146:f64d43ff0c18 8385 */ /* end of group MCM_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 8386
mbed_official 146:f64d43ff0c18 8387
mbed_official 146:f64d43ff0c18 8388 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 8389 -- MCM Register Masks
mbed_official 146:f64d43ff0c18 8390 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 8391
mbed_official 146:f64d43ff0c18 8392 /*!
mbed_official 146:f64d43ff0c18 8393 * @addtogroup MCM_Register_Masks MCM Register Masks
mbed_official 146:f64d43ff0c18 8394 * @{
mbed_official 146:f64d43ff0c18 8395 */
mbed_official 146:f64d43ff0c18 8396
mbed_official 146:f64d43ff0c18 8397 /* PLASC Bit Fields */
mbed_official 146:f64d43ff0c18 8398 #define MCM_PLASC_ASC_MASK 0xFFu
mbed_official 146:f64d43ff0c18 8399 #define MCM_PLASC_ASC_SHIFT 0
mbed_official 146:f64d43ff0c18 8400 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
mbed_official 146:f64d43ff0c18 8401 /* PLAMC Bit Fields */
mbed_official 146:f64d43ff0c18 8402 #define MCM_PLAMC_AMC_MASK 0xFFu
mbed_official 146:f64d43ff0c18 8403 #define MCM_PLAMC_AMC_SHIFT 0
mbed_official 146:f64d43ff0c18 8404 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
mbed_official 146:f64d43ff0c18 8405 /* CR Bit Fields */
mbed_official 146:f64d43ff0c18 8406 #define MCM_CR_SRAMUAP_MASK 0x3000000u
mbed_official 146:f64d43ff0c18 8407 #define MCM_CR_SRAMUAP_SHIFT 24
mbed_official 146:f64d43ff0c18 8408 #define MCM_CR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMUAP_SHIFT))&MCM_CR_SRAMUAP_MASK)
mbed_official 146:f64d43ff0c18 8409 #define MCM_CR_SRAMUWP_MASK 0x4000000u
mbed_official 146:f64d43ff0c18 8410 #define MCM_CR_SRAMUWP_SHIFT 26
mbed_official 146:f64d43ff0c18 8411 #define MCM_CR_SRAMLAP_MASK 0x30000000u
mbed_official 146:f64d43ff0c18 8412 #define MCM_CR_SRAMLAP_SHIFT 28
mbed_official 146:f64d43ff0c18 8413 #define MCM_CR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMLAP_SHIFT))&MCM_CR_SRAMLAP_MASK)
mbed_official 146:f64d43ff0c18 8414 #define MCM_CR_SRAMLWP_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 8415 #define MCM_CR_SRAMLWP_SHIFT 30
mbed_official 146:f64d43ff0c18 8416 /* ISR Bit Fields */
mbed_official 146:f64d43ff0c18 8417 #define MCM_ISR_IRQ_MASK 0x2u
mbed_official 146:f64d43ff0c18 8418 #define MCM_ISR_IRQ_SHIFT 1
mbed_official 146:f64d43ff0c18 8419 #define MCM_ISR_NMI_MASK 0x4u
mbed_official 146:f64d43ff0c18 8420 #define MCM_ISR_NMI_SHIFT 2
mbed_official 146:f64d43ff0c18 8421 #define MCM_ISR_DHREQ_MASK 0x8u
mbed_official 146:f64d43ff0c18 8422 #define MCM_ISR_DHREQ_SHIFT 3
mbed_official 146:f64d43ff0c18 8423 #define MCM_ISR_FIOC_MASK 0x100u
mbed_official 146:f64d43ff0c18 8424 #define MCM_ISR_FIOC_SHIFT 8
mbed_official 146:f64d43ff0c18 8425 #define MCM_ISR_FDZC_MASK 0x200u
mbed_official 146:f64d43ff0c18 8426 #define MCM_ISR_FDZC_SHIFT 9
mbed_official 146:f64d43ff0c18 8427 #define MCM_ISR_FOFC_MASK 0x400u
mbed_official 146:f64d43ff0c18 8428 #define MCM_ISR_FOFC_SHIFT 10
mbed_official 146:f64d43ff0c18 8429 #define MCM_ISR_FUFC_MASK 0x800u
mbed_official 146:f64d43ff0c18 8430 #define MCM_ISR_FUFC_SHIFT 11
mbed_official 146:f64d43ff0c18 8431 #define MCM_ISR_FIXC_MASK 0x1000u
mbed_official 146:f64d43ff0c18 8432 #define MCM_ISR_FIXC_SHIFT 12
mbed_official 146:f64d43ff0c18 8433 #define MCM_ISR_FIDC_MASK 0x8000u
mbed_official 146:f64d43ff0c18 8434 #define MCM_ISR_FIDC_SHIFT 15
mbed_official 146:f64d43ff0c18 8435 #define MCM_ISR_FIOCE_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 8436 #define MCM_ISR_FIOCE_SHIFT 24
mbed_official 146:f64d43ff0c18 8437 #define MCM_ISR_FDZCE_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 8438 #define MCM_ISR_FDZCE_SHIFT 25
mbed_official 146:f64d43ff0c18 8439 #define MCM_ISR_FOFCE_MASK 0x4000000u
mbed_official 146:f64d43ff0c18 8440 #define MCM_ISR_FOFCE_SHIFT 26
mbed_official 146:f64d43ff0c18 8441 #define MCM_ISR_FUFCE_MASK 0x8000000u
mbed_official 146:f64d43ff0c18 8442 #define MCM_ISR_FUFCE_SHIFT 27
mbed_official 146:f64d43ff0c18 8443 #define MCM_ISR_FIXCE_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 8444 #define MCM_ISR_FIXCE_SHIFT 28
mbed_official 146:f64d43ff0c18 8445 #define MCM_ISR_FIDCE_MASK 0x80000000u
mbed_official 146:f64d43ff0c18 8446 #define MCM_ISR_FIDCE_SHIFT 31
mbed_official 146:f64d43ff0c18 8447 /* ETBCC Bit Fields */
mbed_official 146:f64d43ff0c18 8448 #define MCM_ETBCC_CNTEN_MASK 0x1u
mbed_official 146:f64d43ff0c18 8449 #define MCM_ETBCC_CNTEN_SHIFT 0
mbed_official 146:f64d43ff0c18 8450 #define MCM_ETBCC_RSPT_MASK 0x6u
mbed_official 146:f64d43ff0c18 8451 #define MCM_ETBCC_RSPT_SHIFT 1
mbed_official 146:f64d43ff0c18 8452 #define MCM_ETBCC_RSPT(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_RSPT_SHIFT))&MCM_ETBCC_RSPT_MASK)
mbed_official 146:f64d43ff0c18 8453 #define MCM_ETBCC_RLRQ_MASK 0x8u
mbed_official 146:f64d43ff0c18 8454 #define MCM_ETBCC_RLRQ_SHIFT 3
mbed_official 146:f64d43ff0c18 8455 #define MCM_ETBCC_ETDIS_MASK 0x10u
mbed_official 146:f64d43ff0c18 8456 #define MCM_ETBCC_ETDIS_SHIFT 4
mbed_official 146:f64d43ff0c18 8457 #define MCM_ETBCC_ITDIS_MASK 0x20u
mbed_official 146:f64d43ff0c18 8458 #define MCM_ETBCC_ITDIS_SHIFT 5
mbed_official 146:f64d43ff0c18 8459 /* ETBRL Bit Fields */
mbed_official 146:f64d43ff0c18 8460 #define MCM_ETBRL_RELOAD_MASK 0x7FFu
mbed_official 146:f64d43ff0c18 8461 #define MCM_ETBRL_RELOAD_SHIFT 0
mbed_official 146:f64d43ff0c18 8462 #define MCM_ETBRL_RELOAD(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBRL_RELOAD_SHIFT))&MCM_ETBRL_RELOAD_MASK)
mbed_official 146:f64d43ff0c18 8463 /* ETBCNT Bit Fields */
mbed_official 146:f64d43ff0c18 8464 #define MCM_ETBCNT_COUNTER_MASK 0x7FFu
mbed_official 146:f64d43ff0c18 8465 #define MCM_ETBCNT_COUNTER_SHIFT 0
mbed_official 146:f64d43ff0c18 8466 #define MCM_ETBCNT_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBCNT_COUNTER_SHIFT))&MCM_ETBCNT_COUNTER_MASK)
mbed_official 146:f64d43ff0c18 8467 /* PID Bit Fields */
mbed_official 146:f64d43ff0c18 8468 #define MCM_PID_PID_MASK 0xFFu
mbed_official 146:f64d43ff0c18 8469 #define MCM_PID_PID_SHIFT 0
mbed_official 146:f64d43ff0c18 8470 #define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x))<<MCM_PID_PID_SHIFT))&MCM_PID_PID_MASK)
mbed_official 146:f64d43ff0c18 8471
mbed_official 146:f64d43ff0c18 8472 /*!
mbed_official 146:f64d43ff0c18 8473 * @}
mbed_official 146:f64d43ff0c18 8474 */ /* end of group MCM_Register_Masks */
mbed_official 146:f64d43ff0c18 8475
mbed_official 146:f64d43ff0c18 8476
mbed_official 146:f64d43ff0c18 8477 /* MCM - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 8478 /** Peripheral MCM base address */
mbed_official 146:f64d43ff0c18 8479 #define MCM_BASE (0xE0080000u)
mbed_official 146:f64d43ff0c18 8480 /** Peripheral MCM base pointer */
mbed_official 146:f64d43ff0c18 8481 #define MCM ((MCM_Type *)MCM_BASE)
mbed_official 146:f64d43ff0c18 8482 #define MCM_BASE_PTR (MCM)
mbed_official 146:f64d43ff0c18 8483 /** Array initializer of MCM peripheral base pointers */
mbed_official 146:f64d43ff0c18 8484 #define MCM_BASES { MCM }
mbed_official 146:f64d43ff0c18 8485
mbed_official 146:f64d43ff0c18 8486 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 8487 -- MCM - Register accessor macros
mbed_official 146:f64d43ff0c18 8488 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 8489
mbed_official 146:f64d43ff0c18 8490 /*!
mbed_official 146:f64d43ff0c18 8491 * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
mbed_official 146:f64d43ff0c18 8492 * @{
mbed_official 146:f64d43ff0c18 8493 */
mbed_official 146:f64d43ff0c18 8494
mbed_official 146:f64d43ff0c18 8495
mbed_official 146:f64d43ff0c18 8496 /* MCM - Register instance definitions */
mbed_official 146:f64d43ff0c18 8497 /* MCM */
mbed_official 146:f64d43ff0c18 8498 #define MCM_PLASC MCM_PLASC_REG(MCM)
mbed_official 146:f64d43ff0c18 8499 #define MCM_PLAMC MCM_PLAMC_REG(MCM)
mbed_official 146:f64d43ff0c18 8500 #define MCM_CR MCM_CR_REG(MCM)
mbed_official 146:f64d43ff0c18 8501 #define MCM_ISCR MCM_ISR_REG(MCM)
mbed_official 146:f64d43ff0c18 8502 #define MCM_ETBCC MCM_ETBCC_REG(MCM)
mbed_official 146:f64d43ff0c18 8503 #define MCM_ETBRL MCM_ETBRL_REG(MCM)
mbed_official 146:f64d43ff0c18 8504 #define MCM_ETBCNT MCM_ETBCNT_REG(MCM)
mbed_official 146:f64d43ff0c18 8505 #define MCM_PID MCM_PID_REG(MCM)
mbed_official 146:f64d43ff0c18 8506
mbed_official 146:f64d43ff0c18 8507 /*!
mbed_official 146:f64d43ff0c18 8508 * @}
mbed_official 146:f64d43ff0c18 8509 */ /* end of group MCM_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 8510
mbed_official 146:f64d43ff0c18 8511
mbed_official 146:f64d43ff0c18 8512 /*!
mbed_official 146:f64d43ff0c18 8513 * @}
mbed_official 146:f64d43ff0c18 8514 */ /* end of group MCM_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 8515
mbed_official 146:f64d43ff0c18 8516
mbed_official 146:f64d43ff0c18 8517 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 8518 -- MPU Peripheral Access Layer
mbed_official 146:f64d43ff0c18 8519 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 8520
mbed_official 146:f64d43ff0c18 8521 /*!
mbed_official 146:f64d43ff0c18 8522 * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer
mbed_official 146:f64d43ff0c18 8523 * @{
mbed_official 146:f64d43ff0c18 8524 */
mbed_official 146:f64d43ff0c18 8525
mbed_official 146:f64d43ff0c18 8526 /** MPU - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 8527 typedef struct {
mbed_official 146:f64d43ff0c18 8528 __IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */
mbed_official 146:f64d43ff0c18 8529 uint8_t RESERVED_0[12];
mbed_official 146:f64d43ff0c18 8530 struct { /* offset: 0x10, array step: 0x8 */
mbed_official 146:f64d43ff0c18 8531 __I uint32_t EAR; /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
mbed_official 146:f64d43ff0c18 8532 __I uint32_t EDR; /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
mbed_official 146:f64d43ff0c18 8533 } SP[5];
mbed_official 146:f64d43ff0c18 8534 uint8_t RESERVED_1[968];
mbed_official 146:f64d43ff0c18 8535 __IO uint32_t WORD[12][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
mbed_official 146:f64d43ff0c18 8536 uint8_t RESERVED_2[832];
mbed_official 146:f64d43ff0c18 8537 __IO uint32_t RGDAAC[12]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
mbed_official 146:f64d43ff0c18 8538 } MPU_Type, *MPU_MemMapPtr;
mbed_official 146:f64d43ff0c18 8539
mbed_official 146:f64d43ff0c18 8540 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 8541 -- MPU - Register accessor macros
mbed_official 146:f64d43ff0c18 8542 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 8543
mbed_official 146:f64d43ff0c18 8544 /*!
mbed_official 146:f64d43ff0c18 8545 * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
mbed_official 146:f64d43ff0c18 8546 * @{
mbed_official 146:f64d43ff0c18 8547 */
mbed_official 146:f64d43ff0c18 8548
mbed_official 146:f64d43ff0c18 8549
mbed_official 146:f64d43ff0c18 8550 /* MPU - Register accessors */
mbed_official 146:f64d43ff0c18 8551 #define MPU_CESR_REG(base) ((base)->CESR)
mbed_official 146:f64d43ff0c18 8552 #define MPU_EAR_REG(base,index) ((base)->SP[index].EAR)
mbed_official 146:f64d43ff0c18 8553 #define MPU_EDR_REG(base,index) ((base)->SP[index].EDR)
mbed_official 146:f64d43ff0c18 8554 #define MPU_WORD_REG(base,index,index2) ((base)->WORD[index][index2])
mbed_official 146:f64d43ff0c18 8555 #define MPU_RGDAAC_REG(base,index) ((base)->RGDAAC[index])
mbed_official 146:f64d43ff0c18 8556
mbed_official 146:f64d43ff0c18 8557 /*!
mbed_official 146:f64d43ff0c18 8558 * @}
mbed_official 146:f64d43ff0c18 8559 */ /* end of group MPU_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 8560
mbed_official 146:f64d43ff0c18 8561
mbed_official 146:f64d43ff0c18 8562 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 8563 -- MPU Register Masks
mbed_official 146:f64d43ff0c18 8564 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 8565
mbed_official 146:f64d43ff0c18 8566 /*!
mbed_official 146:f64d43ff0c18 8567 * @addtogroup MPU_Register_Masks MPU Register Masks
mbed_official 146:f64d43ff0c18 8568 * @{
mbed_official 146:f64d43ff0c18 8569 */
mbed_official 146:f64d43ff0c18 8570
mbed_official 146:f64d43ff0c18 8571 /* CESR Bit Fields */
mbed_official 146:f64d43ff0c18 8572 #define MPU_CESR_VLD_MASK 0x1u
mbed_official 146:f64d43ff0c18 8573 #define MPU_CESR_VLD_SHIFT 0
mbed_official 146:f64d43ff0c18 8574 #define MPU_CESR_NRGD_MASK 0xF00u
mbed_official 146:f64d43ff0c18 8575 #define MPU_CESR_NRGD_SHIFT 8
mbed_official 146:f64d43ff0c18 8576 #define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NRGD_SHIFT))&MPU_CESR_NRGD_MASK)
mbed_official 146:f64d43ff0c18 8577 #define MPU_CESR_NSP_MASK 0xF000u
mbed_official 146:f64d43ff0c18 8578 #define MPU_CESR_NSP_SHIFT 12
mbed_official 146:f64d43ff0c18 8579 #define MPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NSP_SHIFT))&MPU_CESR_NSP_MASK)
mbed_official 146:f64d43ff0c18 8580 #define MPU_CESR_HRL_MASK 0xF0000u
mbed_official 146:f64d43ff0c18 8581 #define MPU_CESR_HRL_SHIFT 16
mbed_official 146:f64d43ff0c18 8582 #define MPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_HRL_SHIFT))&MPU_CESR_HRL_MASK)
mbed_official 146:f64d43ff0c18 8583 #define MPU_CESR_SPERR_MASK 0xF8000000u
mbed_official 146:f64d43ff0c18 8584 #define MPU_CESR_SPERR_SHIFT 27
mbed_official 146:f64d43ff0c18 8585 #define MPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR_SHIFT))&MPU_CESR_SPERR_MASK)
mbed_official 146:f64d43ff0c18 8586 /* EAR Bit Fields */
mbed_official 146:f64d43ff0c18 8587 #define MPU_EAR_EADDR_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 8588 #define MPU_EAR_EADDR_SHIFT 0
mbed_official 146:f64d43ff0c18 8589 #define MPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EAR_EADDR_SHIFT))&MPU_EAR_EADDR_MASK)
mbed_official 146:f64d43ff0c18 8590 /* EDR Bit Fields */
mbed_official 146:f64d43ff0c18 8591 #define MPU_EDR_ERW_MASK 0x1u
mbed_official 146:f64d43ff0c18 8592 #define MPU_EDR_ERW_SHIFT 0
mbed_official 146:f64d43ff0c18 8593 #define MPU_EDR_EATTR_MASK 0xEu
mbed_official 146:f64d43ff0c18 8594 #define MPU_EDR_EATTR_SHIFT 1
mbed_official 146:f64d43ff0c18 8595 #define MPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EATTR_SHIFT))&MPU_EDR_EATTR_MASK)
mbed_official 146:f64d43ff0c18 8596 #define MPU_EDR_EMN_MASK 0xF0u
mbed_official 146:f64d43ff0c18 8597 #define MPU_EDR_EMN_SHIFT 4
mbed_official 146:f64d43ff0c18 8598 #define MPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EMN_SHIFT))&MPU_EDR_EMN_MASK)
mbed_official 146:f64d43ff0c18 8599 #define MPU_EDR_EPID_MASK 0xFF00u
mbed_official 146:f64d43ff0c18 8600 #define MPU_EDR_EPID_SHIFT 8
mbed_official 146:f64d43ff0c18 8601 #define MPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EPID_SHIFT))&MPU_EDR_EPID_MASK)
mbed_official 146:f64d43ff0c18 8602 #define MPU_EDR_EACD_MASK 0xFFFF0000u
mbed_official 146:f64d43ff0c18 8603 #define MPU_EDR_EACD_SHIFT 16
mbed_official 146:f64d43ff0c18 8604 #define MPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EACD_SHIFT))&MPU_EDR_EACD_MASK)
mbed_official 146:f64d43ff0c18 8605 /* WORD Bit Fields */
mbed_official 146:f64d43ff0c18 8606 #define MPU_WORD_VLD_MASK 0x1u
mbed_official 146:f64d43ff0c18 8607 #define MPU_WORD_VLD_SHIFT 0
mbed_official 146:f64d43ff0c18 8608 #define MPU_WORD_M0UM_MASK 0x7u
mbed_official 146:f64d43ff0c18 8609 #define MPU_WORD_M0UM_SHIFT 0
mbed_official 146:f64d43ff0c18 8610 #define MPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0UM_SHIFT))&MPU_WORD_M0UM_MASK)
mbed_official 146:f64d43ff0c18 8611 #define MPU_WORD_M0SM_MASK 0x18u
mbed_official 146:f64d43ff0c18 8612 #define MPU_WORD_M0SM_SHIFT 3
mbed_official 146:f64d43ff0c18 8613 #define MPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0SM_SHIFT))&MPU_WORD_M0SM_MASK)
mbed_official 146:f64d43ff0c18 8614 #define MPU_WORD_M0PE_MASK 0x20u
mbed_official 146:f64d43ff0c18 8615 #define MPU_WORD_M0PE_SHIFT 5
mbed_official 146:f64d43ff0c18 8616 #define MPU_WORD_ENDADDR_MASK 0xFFFFFFE0u
mbed_official 146:f64d43ff0c18 8617 #define MPU_WORD_ENDADDR_SHIFT 5
mbed_official 146:f64d43ff0c18 8618 #define MPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_ENDADDR_SHIFT))&MPU_WORD_ENDADDR_MASK)
mbed_official 146:f64d43ff0c18 8619 #define MPU_WORD_SRTADDR_MASK 0xFFFFFFE0u
mbed_official 146:f64d43ff0c18 8620 #define MPU_WORD_SRTADDR_SHIFT 5
mbed_official 146:f64d43ff0c18 8621 #define MPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_SRTADDR_SHIFT))&MPU_WORD_SRTADDR_MASK)
mbed_official 146:f64d43ff0c18 8622 #define MPU_WORD_M1UM_MASK 0x1C0u
mbed_official 146:f64d43ff0c18 8623 #define MPU_WORD_M1UM_SHIFT 6
mbed_official 146:f64d43ff0c18 8624 #define MPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1UM_SHIFT))&MPU_WORD_M1UM_MASK)
mbed_official 146:f64d43ff0c18 8625 #define MPU_WORD_M1SM_MASK 0x600u
mbed_official 146:f64d43ff0c18 8626 #define MPU_WORD_M1SM_SHIFT 9
mbed_official 146:f64d43ff0c18 8627 #define MPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1SM_SHIFT))&MPU_WORD_M1SM_MASK)
mbed_official 146:f64d43ff0c18 8628 #define MPU_WORD_M1PE_MASK 0x800u
mbed_official 146:f64d43ff0c18 8629 #define MPU_WORD_M1PE_SHIFT 11
mbed_official 146:f64d43ff0c18 8630 #define MPU_WORD_M2UM_MASK 0x7000u
mbed_official 146:f64d43ff0c18 8631 #define MPU_WORD_M2UM_SHIFT 12
mbed_official 146:f64d43ff0c18 8632 #define MPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2UM_SHIFT))&MPU_WORD_M2UM_MASK)
mbed_official 146:f64d43ff0c18 8633 #define MPU_WORD_M2SM_MASK 0x18000u
mbed_official 146:f64d43ff0c18 8634 #define MPU_WORD_M2SM_SHIFT 15
mbed_official 146:f64d43ff0c18 8635 #define MPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2SM_SHIFT))&MPU_WORD_M2SM_MASK)
mbed_official 146:f64d43ff0c18 8636 #define MPU_WORD_PIDMASK_MASK 0xFF0000u
mbed_official 146:f64d43ff0c18 8637 #define MPU_WORD_PIDMASK_SHIFT 16
mbed_official 146:f64d43ff0c18 8638 #define MPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PIDMASK_SHIFT))&MPU_WORD_PIDMASK_MASK)
mbed_official 146:f64d43ff0c18 8639 #define MPU_WORD_M2PE_MASK 0x20000u
mbed_official 146:f64d43ff0c18 8640 #define MPU_WORD_M2PE_SHIFT 17
mbed_official 146:f64d43ff0c18 8641 #define MPU_WORD_M3UM_MASK 0x1C0000u
mbed_official 146:f64d43ff0c18 8642 #define MPU_WORD_M3UM_SHIFT 18
mbed_official 146:f64d43ff0c18 8643 #define MPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3UM_SHIFT))&MPU_WORD_M3UM_MASK)
mbed_official 146:f64d43ff0c18 8644 #define MPU_WORD_M3SM_MASK 0x600000u
mbed_official 146:f64d43ff0c18 8645 #define MPU_WORD_M3SM_SHIFT 21
mbed_official 146:f64d43ff0c18 8646 #define MPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3SM_SHIFT))&MPU_WORD_M3SM_MASK)
mbed_official 146:f64d43ff0c18 8647 #define MPU_WORD_M3PE_MASK 0x800000u
mbed_official 146:f64d43ff0c18 8648 #define MPU_WORD_M3PE_SHIFT 23
mbed_official 146:f64d43ff0c18 8649 #define MPU_WORD_PID_MASK 0xFF000000u
mbed_official 146:f64d43ff0c18 8650 #define MPU_WORD_PID_SHIFT 24
mbed_official 146:f64d43ff0c18 8651 #define MPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PID_SHIFT))&MPU_WORD_PID_MASK)
mbed_official 146:f64d43ff0c18 8652 #define MPU_WORD_M4WE_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 8653 #define MPU_WORD_M4WE_SHIFT 24
mbed_official 146:f64d43ff0c18 8654 #define MPU_WORD_M4RE_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 8655 #define MPU_WORD_M4RE_SHIFT 25
mbed_official 146:f64d43ff0c18 8656 #define MPU_WORD_M5WE_MASK 0x4000000u
mbed_official 146:f64d43ff0c18 8657 #define MPU_WORD_M5WE_SHIFT 26
mbed_official 146:f64d43ff0c18 8658 #define MPU_WORD_M5RE_MASK 0x8000000u
mbed_official 146:f64d43ff0c18 8659 #define MPU_WORD_M5RE_SHIFT 27
mbed_official 146:f64d43ff0c18 8660 #define MPU_WORD_M6WE_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 8661 #define MPU_WORD_M6WE_SHIFT 28
mbed_official 146:f64d43ff0c18 8662 #define MPU_WORD_M6RE_MASK 0x20000000u
mbed_official 146:f64d43ff0c18 8663 #define MPU_WORD_M6RE_SHIFT 29
mbed_official 146:f64d43ff0c18 8664 #define MPU_WORD_M7WE_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 8665 #define MPU_WORD_M7WE_SHIFT 30
mbed_official 146:f64d43ff0c18 8666 #define MPU_WORD_M7RE_MASK 0x80000000u
mbed_official 146:f64d43ff0c18 8667 #define MPU_WORD_M7RE_SHIFT 31
mbed_official 146:f64d43ff0c18 8668 /* RGDAAC Bit Fields */
mbed_official 146:f64d43ff0c18 8669 #define MPU_RGDAAC_M0UM_MASK 0x7u
mbed_official 146:f64d43ff0c18 8670 #define MPU_RGDAAC_M0UM_SHIFT 0
mbed_official 146:f64d43ff0c18 8671 #define MPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0UM_SHIFT))&MPU_RGDAAC_M0UM_MASK)
mbed_official 146:f64d43ff0c18 8672 #define MPU_RGDAAC_M0SM_MASK 0x18u
mbed_official 146:f64d43ff0c18 8673 #define MPU_RGDAAC_M0SM_SHIFT 3
mbed_official 146:f64d43ff0c18 8674 #define MPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0SM_SHIFT))&MPU_RGDAAC_M0SM_MASK)
mbed_official 146:f64d43ff0c18 8675 #define MPU_RGDAAC_M0PE_MASK 0x20u
mbed_official 146:f64d43ff0c18 8676 #define MPU_RGDAAC_M0PE_SHIFT 5
mbed_official 146:f64d43ff0c18 8677 #define MPU_RGDAAC_M1UM_MASK 0x1C0u
mbed_official 146:f64d43ff0c18 8678 #define MPU_RGDAAC_M1UM_SHIFT 6
mbed_official 146:f64d43ff0c18 8679 #define MPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1UM_SHIFT))&MPU_RGDAAC_M1UM_MASK)
mbed_official 146:f64d43ff0c18 8680 #define MPU_RGDAAC_M1SM_MASK 0x600u
mbed_official 146:f64d43ff0c18 8681 #define MPU_RGDAAC_M1SM_SHIFT 9
mbed_official 146:f64d43ff0c18 8682 #define MPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1SM_SHIFT))&MPU_RGDAAC_M1SM_MASK)
mbed_official 146:f64d43ff0c18 8683 #define MPU_RGDAAC_M1PE_MASK 0x800u
mbed_official 146:f64d43ff0c18 8684 #define MPU_RGDAAC_M1PE_SHIFT 11
mbed_official 146:f64d43ff0c18 8685 #define MPU_RGDAAC_M2UM_MASK 0x7000u
mbed_official 146:f64d43ff0c18 8686 #define MPU_RGDAAC_M2UM_SHIFT 12
mbed_official 146:f64d43ff0c18 8687 #define MPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2UM_SHIFT))&MPU_RGDAAC_M2UM_MASK)
mbed_official 146:f64d43ff0c18 8688 #define MPU_RGDAAC_M2SM_MASK 0x18000u
mbed_official 146:f64d43ff0c18 8689 #define MPU_RGDAAC_M2SM_SHIFT 15
mbed_official 146:f64d43ff0c18 8690 #define MPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2SM_SHIFT))&MPU_RGDAAC_M2SM_MASK)
mbed_official 146:f64d43ff0c18 8691 #define MPU_RGDAAC_M2PE_MASK 0x20000u
mbed_official 146:f64d43ff0c18 8692 #define MPU_RGDAAC_M2PE_SHIFT 17
mbed_official 146:f64d43ff0c18 8693 #define MPU_RGDAAC_M3UM_MASK 0x1C0000u
mbed_official 146:f64d43ff0c18 8694 #define MPU_RGDAAC_M3UM_SHIFT 18
mbed_official 146:f64d43ff0c18 8695 #define MPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3UM_SHIFT))&MPU_RGDAAC_M3UM_MASK)
mbed_official 146:f64d43ff0c18 8696 #define MPU_RGDAAC_M3SM_MASK 0x600000u
mbed_official 146:f64d43ff0c18 8697 #define MPU_RGDAAC_M3SM_SHIFT 21
mbed_official 146:f64d43ff0c18 8698 #define MPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3SM_SHIFT))&MPU_RGDAAC_M3SM_MASK)
mbed_official 146:f64d43ff0c18 8699 #define MPU_RGDAAC_M3PE_MASK 0x800000u
mbed_official 146:f64d43ff0c18 8700 #define MPU_RGDAAC_M3PE_SHIFT 23
mbed_official 146:f64d43ff0c18 8701 #define MPU_RGDAAC_M4WE_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 8702 #define MPU_RGDAAC_M4WE_SHIFT 24
mbed_official 146:f64d43ff0c18 8703 #define MPU_RGDAAC_M4RE_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 8704 #define MPU_RGDAAC_M4RE_SHIFT 25
mbed_official 146:f64d43ff0c18 8705 #define MPU_RGDAAC_M5WE_MASK 0x4000000u
mbed_official 146:f64d43ff0c18 8706 #define MPU_RGDAAC_M5WE_SHIFT 26
mbed_official 146:f64d43ff0c18 8707 #define MPU_RGDAAC_M5RE_MASK 0x8000000u
mbed_official 146:f64d43ff0c18 8708 #define MPU_RGDAAC_M5RE_SHIFT 27
mbed_official 146:f64d43ff0c18 8709 #define MPU_RGDAAC_M6WE_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 8710 #define MPU_RGDAAC_M6WE_SHIFT 28
mbed_official 146:f64d43ff0c18 8711 #define MPU_RGDAAC_M6RE_MASK 0x20000000u
mbed_official 146:f64d43ff0c18 8712 #define MPU_RGDAAC_M6RE_SHIFT 29
mbed_official 146:f64d43ff0c18 8713 #define MPU_RGDAAC_M7WE_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 8714 #define MPU_RGDAAC_M7WE_SHIFT 30
mbed_official 146:f64d43ff0c18 8715 #define MPU_RGDAAC_M7RE_MASK 0x80000000u
mbed_official 146:f64d43ff0c18 8716 #define MPU_RGDAAC_M7RE_SHIFT 31
mbed_official 146:f64d43ff0c18 8717
mbed_official 146:f64d43ff0c18 8718 /*!
mbed_official 146:f64d43ff0c18 8719 * @}
mbed_official 146:f64d43ff0c18 8720 */ /* end of group MPU_Register_Masks */
mbed_official 146:f64d43ff0c18 8721
mbed_official 146:f64d43ff0c18 8722
mbed_official 146:f64d43ff0c18 8723 /* MPU - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 8724 /** Peripheral MPU base address */
mbed_official 146:f64d43ff0c18 8725 #define MPU_BASE (0x4000D000u)
mbed_official 146:f64d43ff0c18 8726 /** Peripheral MPU base pointer */
mbed_official 146:f64d43ff0c18 8727 #define MPU ((MPU_Type *)MPU_BASE)
mbed_official 146:f64d43ff0c18 8728 #define MPU_BASE_PTR (MPU)
mbed_official 146:f64d43ff0c18 8729 /** Array initializer of MPU peripheral base pointers */
mbed_official 146:f64d43ff0c18 8730 #define MPU_BASES { MPU }
mbed_official 146:f64d43ff0c18 8731
mbed_official 146:f64d43ff0c18 8732 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 8733 -- MPU - Register accessor macros
mbed_official 146:f64d43ff0c18 8734 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 8735
mbed_official 146:f64d43ff0c18 8736 /*!
mbed_official 146:f64d43ff0c18 8737 * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
mbed_official 146:f64d43ff0c18 8738 * @{
mbed_official 146:f64d43ff0c18 8739 */
mbed_official 146:f64d43ff0c18 8740
mbed_official 146:f64d43ff0c18 8741
mbed_official 146:f64d43ff0c18 8742 /* MPU - Register instance definitions */
mbed_official 146:f64d43ff0c18 8743 /* MPU */
mbed_official 146:f64d43ff0c18 8744 #define MPU_CESR MPU_CESR_REG(MPU)
mbed_official 146:f64d43ff0c18 8745 #define MPU_EAR0 MPU_EAR_REG(MPU,0)
mbed_official 146:f64d43ff0c18 8746 #define MPU_EDR0 MPU_EDR_REG(MPU,0)
mbed_official 146:f64d43ff0c18 8747 #define MPU_EAR1 MPU_EAR_REG(MPU,1)
mbed_official 146:f64d43ff0c18 8748 #define MPU_EDR1 MPU_EDR_REG(MPU,1)
mbed_official 146:f64d43ff0c18 8749 #define MPU_EAR2 MPU_EAR_REG(MPU,2)
mbed_official 146:f64d43ff0c18 8750 #define MPU_EDR2 MPU_EDR_REG(MPU,2)
mbed_official 146:f64d43ff0c18 8751 #define MPU_EAR3 MPU_EAR_REG(MPU,3)
mbed_official 146:f64d43ff0c18 8752 #define MPU_EDR3 MPU_EDR_REG(MPU,3)
mbed_official 146:f64d43ff0c18 8753 #define MPU_EAR4 MPU_EAR_REG(MPU,4)
mbed_official 146:f64d43ff0c18 8754 #define MPU_EDR4 MPU_EDR_REG(MPU,4)
mbed_official 146:f64d43ff0c18 8755 #define MPU_RGD0_WORD0 MPU_WORD_REG(MPU,0,0)
mbed_official 146:f64d43ff0c18 8756 #define MPU_RGD0_WORD1 MPU_WORD_REG(MPU,0,1)
mbed_official 146:f64d43ff0c18 8757 #define MPU_RGD0_WORD2 MPU_WORD_REG(MPU,0,2)
mbed_official 146:f64d43ff0c18 8758 #define MPU_RGD0_WORD3 MPU_WORD_REG(MPU,0,3)
mbed_official 146:f64d43ff0c18 8759 #define MPU_RGD1_WORD0 MPU_WORD_REG(MPU,1,0)
mbed_official 146:f64d43ff0c18 8760 #define MPU_RGD1_WORD1 MPU_WORD_REG(MPU,1,1)
mbed_official 146:f64d43ff0c18 8761 #define MPU_RGD1_WORD2 MPU_WORD_REG(MPU,1,2)
mbed_official 146:f64d43ff0c18 8762 #define MPU_RGD1_WORD3 MPU_WORD_REG(MPU,1,3)
mbed_official 146:f64d43ff0c18 8763 #define MPU_RGD2_WORD0 MPU_WORD_REG(MPU,2,0)
mbed_official 146:f64d43ff0c18 8764 #define MPU_RGD2_WORD1 MPU_WORD_REG(MPU,2,1)
mbed_official 146:f64d43ff0c18 8765 #define MPU_RGD2_WORD2 MPU_WORD_REG(MPU,2,2)
mbed_official 146:f64d43ff0c18 8766 #define MPU_RGD2_WORD3 MPU_WORD_REG(MPU,2,3)
mbed_official 146:f64d43ff0c18 8767 #define MPU_RGD3_WORD0 MPU_WORD_REG(MPU,3,0)
mbed_official 146:f64d43ff0c18 8768 #define MPU_RGD3_WORD1 MPU_WORD_REG(MPU,3,1)
mbed_official 146:f64d43ff0c18 8769 #define MPU_RGD3_WORD2 MPU_WORD_REG(MPU,3,2)
mbed_official 146:f64d43ff0c18 8770 #define MPU_RGD3_WORD3 MPU_WORD_REG(MPU,3,3)
mbed_official 146:f64d43ff0c18 8771 #define MPU_RGD4_WORD0 MPU_WORD_REG(MPU,4,0)
mbed_official 146:f64d43ff0c18 8772 #define MPU_RGD4_WORD1 MPU_WORD_REG(MPU,4,1)
mbed_official 146:f64d43ff0c18 8773 #define MPU_RGD4_WORD2 MPU_WORD_REG(MPU,4,2)
mbed_official 146:f64d43ff0c18 8774 #define MPU_RGD4_WORD3 MPU_WORD_REG(MPU,4,3)
mbed_official 146:f64d43ff0c18 8775 #define MPU_RGD5_WORD0 MPU_WORD_REG(MPU,5,0)
mbed_official 146:f64d43ff0c18 8776 #define MPU_RGD5_WORD1 MPU_WORD_REG(MPU,5,1)
mbed_official 146:f64d43ff0c18 8777 #define MPU_RGD5_WORD2 MPU_WORD_REG(MPU,5,2)
mbed_official 146:f64d43ff0c18 8778 #define MPU_RGD5_WORD3 MPU_WORD_REG(MPU,5,3)
mbed_official 146:f64d43ff0c18 8779 #define MPU_RGD6_WORD0 MPU_WORD_REG(MPU,6,0)
mbed_official 146:f64d43ff0c18 8780 #define MPU_RGD6_WORD1 MPU_WORD_REG(MPU,6,1)
mbed_official 146:f64d43ff0c18 8781 #define MPU_RGD6_WORD2 MPU_WORD_REG(MPU,6,2)
mbed_official 146:f64d43ff0c18 8782 #define MPU_RGD6_WORD3 MPU_WORD_REG(MPU,6,3)
mbed_official 146:f64d43ff0c18 8783 #define MPU_RGD7_WORD0 MPU_WORD_REG(MPU,7,0)
mbed_official 146:f64d43ff0c18 8784 #define MPU_RGD7_WORD1 MPU_WORD_REG(MPU,7,1)
mbed_official 146:f64d43ff0c18 8785 #define MPU_RGD7_WORD2 MPU_WORD_REG(MPU,7,2)
mbed_official 146:f64d43ff0c18 8786 #define MPU_RGD7_WORD3 MPU_WORD_REG(MPU,7,3)
mbed_official 146:f64d43ff0c18 8787 #define MPU_RGD8_WORD0 MPU_WORD_REG(MPU,8,0)
mbed_official 146:f64d43ff0c18 8788 #define MPU_RGD8_WORD1 MPU_WORD_REG(MPU,8,1)
mbed_official 146:f64d43ff0c18 8789 #define MPU_RGD8_WORD2 MPU_WORD_REG(MPU,8,2)
mbed_official 146:f64d43ff0c18 8790 #define MPU_RGD8_WORD3 MPU_WORD_REG(MPU,8,3)
mbed_official 146:f64d43ff0c18 8791 #define MPU_RGD9_WORD0 MPU_WORD_REG(MPU,9,0)
mbed_official 146:f64d43ff0c18 8792 #define MPU_RGD9_WORD1 MPU_WORD_REG(MPU,9,1)
mbed_official 146:f64d43ff0c18 8793 #define MPU_RGD9_WORD2 MPU_WORD_REG(MPU,9,2)
mbed_official 146:f64d43ff0c18 8794 #define MPU_RGD9_WORD3 MPU_WORD_REG(MPU,9,3)
mbed_official 146:f64d43ff0c18 8795 #define MPU_RGD10_WORD0 MPU_WORD_REG(MPU,10,0)
mbed_official 146:f64d43ff0c18 8796 #define MPU_RGD10_WORD1 MPU_WORD_REG(MPU,10,1)
mbed_official 146:f64d43ff0c18 8797 #define MPU_RGD10_WORD2 MPU_WORD_REG(MPU,10,2)
mbed_official 146:f64d43ff0c18 8798 #define MPU_RGD10_WORD3 MPU_WORD_REG(MPU,10,3)
mbed_official 146:f64d43ff0c18 8799 #define MPU_RGD11_WORD0 MPU_WORD_REG(MPU,11,0)
mbed_official 146:f64d43ff0c18 8800 #define MPU_RGD11_WORD1 MPU_WORD_REG(MPU,11,1)
mbed_official 146:f64d43ff0c18 8801 #define MPU_RGD11_WORD2 MPU_WORD_REG(MPU,11,2)
mbed_official 146:f64d43ff0c18 8802 #define MPU_RGD11_WORD3 MPU_WORD_REG(MPU,11,3)
mbed_official 146:f64d43ff0c18 8803 #define MPU_RGDAAC0 MPU_RGDAAC_REG(MPU,0)
mbed_official 146:f64d43ff0c18 8804 #define MPU_RGDAAC1 MPU_RGDAAC_REG(MPU,1)
mbed_official 146:f64d43ff0c18 8805 #define MPU_RGDAAC2 MPU_RGDAAC_REG(MPU,2)
mbed_official 146:f64d43ff0c18 8806 #define MPU_RGDAAC3 MPU_RGDAAC_REG(MPU,3)
mbed_official 146:f64d43ff0c18 8807 #define MPU_RGDAAC4 MPU_RGDAAC_REG(MPU,4)
mbed_official 146:f64d43ff0c18 8808 #define MPU_RGDAAC5 MPU_RGDAAC_REG(MPU,5)
mbed_official 146:f64d43ff0c18 8809 #define MPU_RGDAAC6 MPU_RGDAAC_REG(MPU,6)
mbed_official 146:f64d43ff0c18 8810 #define MPU_RGDAAC7 MPU_RGDAAC_REG(MPU,7)
mbed_official 146:f64d43ff0c18 8811 #define MPU_RGDAAC8 MPU_RGDAAC_REG(MPU,8)
mbed_official 146:f64d43ff0c18 8812 #define MPU_RGDAAC9 MPU_RGDAAC_REG(MPU,9)
mbed_official 146:f64d43ff0c18 8813 #define MPU_RGDAAC10 MPU_RGDAAC_REG(MPU,10)
mbed_official 146:f64d43ff0c18 8814 #define MPU_RGDAAC11 MPU_RGDAAC_REG(MPU,11)
mbed_official 146:f64d43ff0c18 8815
mbed_official 146:f64d43ff0c18 8816 /* MPU - Register array accessors */
mbed_official 146:f64d43ff0c18 8817 #define MPU_EAR(index) MPU_EAR_REG(MPU,index)
mbed_official 146:f64d43ff0c18 8818 #define MPU_EDR(index) MPU_EDR_REG(MPU,index)
mbed_official 146:f64d43ff0c18 8819 #define MPU_WORD(index,index2) MPU_WORD_REG(MPU,index,index2)
mbed_official 146:f64d43ff0c18 8820 #define MPU_RGDAAC(index) MPU_RGDAAC_REG(MPU,index)
mbed_official 146:f64d43ff0c18 8821
mbed_official 146:f64d43ff0c18 8822 /*!
mbed_official 146:f64d43ff0c18 8823 * @}
mbed_official 146:f64d43ff0c18 8824 */ /* end of group MPU_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 8825
mbed_official 146:f64d43ff0c18 8826
mbed_official 146:f64d43ff0c18 8827 /*!
mbed_official 146:f64d43ff0c18 8828 * @}
mbed_official 146:f64d43ff0c18 8829 */ /* end of group MPU_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 8830
mbed_official 146:f64d43ff0c18 8831
mbed_official 146:f64d43ff0c18 8832 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 8833 -- NV Peripheral Access Layer
mbed_official 146:f64d43ff0c18 8834 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 8835
mbed_official 146:f64d43ff0c18 8836 /*!
mbed_official 146:f64d43ff0c18 8837 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
mbed_official 146:f64d43ff0c18 8838 * @{
mbed_official 146:f64d43ff0c18 8839 */
mbed_official 146:f64d43ff0c18 8840
mbed_official 146:f64d43ff0c18 8841 /** NV - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 8842 typedef struct {
mbed_official 146:f64d43ff0c18 8843 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
mbed_official 146:f64d43ff0c18 8844 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
mbed_official 146:f64d43ff0c18 8845 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
mbed_official 146:f64d43ff0c18 8846 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
mbed_official 146:f64d43ff0c18 8847 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
mbed_official 146:f64d43ff0c18 8848 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
mbed_official 146:f64d43ff0c18 8849 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
mbed_official 146:f64d43ff0c18 8850 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
mbed_official 146:f64d43ff0c18 8851 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
mbed_official 146:f64d43ff0c18 8852 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
mbed_official 146:f64d43ff0c18 8853 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
mbed_official 146:f64d43ff0c18 8854 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
mbed_official 146:f64d43ff0c18 8855 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
mbed_official 146:f64d43ff0c18 8856 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
mbed_official 146:f64d43ff0c18 8857 __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */
mbed_official 146:f64d43ff0c18 8858 __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */
mbed_official 146:f64d43ff0c18 8859 } NV_Type, *NV_MemMapPtr;
mbed_official 146:f64d43ff0c18 8860
mbed_official 146:f64d43ff0c18 8861 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 8862 -- NV - Register accessor macros
mbed_official 146:f64d43ff0c18 8863 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 8864
mbed_official 146:f64d43ff0c18 8865 /*!
mbed_official 146:f64d43ff0c18 8866 * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
mbed_official 146:f64d43ff0c18 8867 * @{
mbed_official 146:f64d43ff0c18 8868 */
mbed_official 146:f64d43ff0c18 8869
mbed_official 146:f64d43ff0c18 8870
mbed_official 146:f64d43ff0c18 8871 /* NV - Register accessors */
mbed_official 146:f64d43ff0c18 8872 #define NV_BACKKEY3_REG(base) ((base)->BACKKEY3)
mbed_official 146:f64d43ff0c18 8873 #define NV_BACKKEY2_REG(base) ((base)->BACKKEY2)
mbed_official 146:f64d43ff0c18 8874 #define NV_BACKKEY1_REG(base) ((base)->BACKKEY1)
mbed_official 146:f64d43ff0c18 8875 #define NV_BACKKEY0_REG(base) ((base)->BACKKEY0)
mbed_official 146:f64d43ff0c18 8876 #define NV_BACKKEY7_REG(base) ((base)->BACKKEY7)
mbed_official 146:f64d43ff0c18 8877 #define NV_BACKKEY6_REG(base) ((base)->BACKKEY6)
mbed_official 146:f64d43ff0c18 8878 #define NV_BACKKEY5_REG(base) ((base)->BACKKEY5)
mbed_official 146:f64d43ff0c18 8879 #define NV_BACKKEY4_REG(base) ((base)->BACKKEY4)
mbed_official 146:f64d43ff0c18 8880 #define NV_FPROT3_REG(base) ((base)->FPROT3)
mbed_official 146:f64d43ff0c18 8881 #define NV_FPROT2_REG(base) ((base)->FPROT2)
mbed_official 146:f64d43ff0c18 8882 #define NV_FPROT1_REG(base) ((base)->FPROT1)
mbed_official 146:f64d43ff0c18 8883 #define NV_FPROT0_REG(base) ((base)->FPROT0)
mbed_official 146:f64d43ff0c18 8884 #define NV_FSEC_REG(base) ((base)->FSEC)
mbed_official 146:f64d43ff0c18 8885 #define NV_FOPT_REG(base) ((base)->FOPT)
mbed_official 146:f64d43ff0c18 8886 #define NV_FEPROT_REG(base) ((base)->FEPROT)
mbed_official 146:f64d43ff0c18 8887 #define NV_FDPROT_REG(base) ((base)->FDPROT)
mbed_official 146:f64d43ff0c18 8888
mbed_official 146:f64d43ff0c18 8889 /*!
mbed_official 146:f64d43ff0c18 8890 * @}
mbed_official 146:f64d43ff0c18 8891 */ /* end of group NV_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 8892
mbed_official 146:f64d43ff0c18 8893
mbed_official 146:f64d43ff0c18 8894 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 8895 -- NV Register Masks
mbed_official 146:f64d43ff0c18 8896 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 8897
mbed_official 146:f64d43ff0c18 8898 /*!
mbed_official 146:f64d43ff0c18 8899 * @addtogroup NV_Register_Masks NV Register Masks
mbed_official 146:f64d43ff0c18 8900 * @{
mbed_official 146:f64d43ff0c18 8901 */
mbed_official 146:f64d43ff0c18 8902
mbed_official 146:f64d43ff0c18 8903 /* BACKKEY3 Bit Fields */
mbed_official 146:f64d43ff0c18 8904 #define NV_BACKKEY3_KEY_MASK 0xFFu
mbed_official 146:f64d43ff0c18 8905 #define NV_BACKKEY3_KEY_SHIFT 0
mbed_official 146:f64d43ff0c18 8906 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
mbed_official 146:f64d43ff0c18 8907 /* BACKKEY2 Bit Fields */
mbed_official 146:f64d43ff0c18 8908 #define NV_BACKKEY2_KEY_MASK 0xFFu
mbed_official 146:f64d43ff0c18 8909 #define NV_BACKKEY2_KEY_SHIFT 0
mbed_official 146:f64d43ff0c18 8910 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
mbed_official 146:f64d43ff0c18 8911 /* BACKKEY1 Bit Fields */
mbed_official 146:f64d43ff0c18 8912 #define NV_BACKKEY1_KEY_MASK 0xFFu
mbed_official 146:f64d43ff0c18 8913 #define NV_BACKKEY1_KEY_SHIFT 0
mbed_official 146:f64d43ff0c18 8914 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
mbed_official 146:f64d43ff0c18 8915 /* BACKKEY0 Bit Fields */
mbed_official 146:f64d43ff0c18 8916 #define NV_BACKKEY0_KEY_MASK 0xFFu
mbed_official 146:f64d43ff0c18 8917 #define NV_BACKKEY0_KEY_SHIFT 0
mbed_official 146:f64d43ff0c18 8918 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
mbed_official 146:f64d43ff0c18 8919 /* BACKKEY7 Bit Fields */
mbed_official 146:f64d43ff0c18 8920 #define NV_BACKKEY7_KEY_MASK 0xFFu
mbed_official 146:f64d43ff0c18 8921 #define NV_BACKKEY7_KEY_SHIFT 0
mbed_official 146:f64d43ff0c18 8922 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
mbed_official 146:f64d43ff0c18 8923 /* BACKKEY6 Bit Fields */
mbed_official 146:f64d43ff0c18 8924 #define NV_BACKKEY6_KEY_MASK 0xFFu
mbed_official 146:f64d43ff0c18 8925 #define NV_BACKKEY6_KEY_SHIFT 0
mbed_official 146:f64d43ff0c18 8926 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
mbed_official 146:f64d43ff0c18 8927 /* BACKKEY5 Bit Fields */
mbed_official 146:f64d43ff0c18 8928 #define NV_BACKKEY5_KEY_MASK 0xFFu
mbed_official 146:f64d43ff0c18 8929 #define NV_BACKKEY5_KEY_SHIFT 0
mbed_official 146:f64d43ff0c18 8930 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
mbed_official 146:f64d43ff0c18 8931 /* BACKKEY4 Bit Fields */
mbed_official 146:f64d43ff0c18 8932 #define NV_BACKKEY4_KEY_MASK 0xFFu
mbed_official 146:f64d43ff0c18 8933 #define NV_BACKKEY4_KEY_SHIFT 0
mbed_official 146:f64d43ff0c18 8934 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
mbed_official 146:f64d43ff0c18 8935 /* FPROT3 Bit Fields */
mbed_official 146:f64d43ff0c18 8936 #define NV_FPROT3_PROT_MASK 0xFFu
mbed_official 146:f64d43ff0c18 8937 #define NV_FPROT3_PROT_SHIFT 0
mbed_official 146:f64d43ff0c18 8938 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
mbed_official 146:f64d43ff0c18 8939 /* FPROT2 Bit Fields */
mbed_official 146:f64d43ff0c18 8940 #define NV_FPROT2_PROT_MASK 0xFFu
mbed_official 146:f64d43ff0c18 8941 #define NV_FPROT2_PROT_SHIFT 0
mbed_official 146:f64d43ff0c18 8942 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
mbed_official 146:f64d43ff0c18 8943 /* FPROT1 Bit Fields */
mbed_official 146:f64d43ff0c18 8944 #define NV_FPROT1_PROT_MASK 0xFFu
mbed_official 146:f64d43ff0c18 8945 #define NV_FPROT1_PROT_SHIFT 0
mbed_official 146:f64d43ff0c18 8946 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
mbed_official 146:f64d43ff0c18 8947 /* FPROT0 Bit Fields */
mbed_official 146:f64d43ff0c18 8948 #define NV_FPROT0_PROT_MASK 0xFFu
mbed_official 146:f64d43ff0c18 8949 #define NV_FPROT0_PROT_SHIFT 0
mbed_official 146:f64d43ff0c18 8950 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
mbed_official 146:f64d43ff0c18 8951 /* FSEC Bit Fields */
mbed_official 146:f64d43ff0c18 8952 #define NV_FSEC_SEC_MASK 0x3u
mbed_official 146:f64d43ff0c18 8953 #define NV_FSEC_SEC_SHIFT 0
mbed_official 146:f64d43ff0c18 8954 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
mbed_official 146:f64d43ff0c18 8955 #define NV_FSEC_FSLACC_MASK 0xCu
mbed_official 146:f64d43ff0c18 8956 #define NV_FSEC_FSLACC_SHIFT 2
mbed_official 146:f64d43ff0c18 8957 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
mbed_official 146:f64d43ff0c18 8958 #define NV_FSEC_MEEN_MASK 0x30u
mbed_official 146:f64d43ff0c18 8959 #define NV_FSEC_MEEN_SHIFT 4
mbed_official 146:f64d43ff0c18 8960 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
mbed_official 146:f64d43ff0c18 8961 #define NV_FSEC_KEYEN_MASK 0xC0u
mbed_official 146:f64d43ff0c18 8962 #define NV_FSEC_KEYEN_SHIFT 6
mbed_official 146:f64d43ff0c18 8963 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
mbed_official 146:f64d43ff0c18 8964 /* FOPT Bit Fields */
mbed_official 146:f64d43ff0c18 8965 #define NV_FOPT_LPBOOT_MASK 0x1u
mbed_official 146:f64d43ff0c18 8966 #define NV_FOPT_LPBOOT_SHIFT 0
mbed_official 146:f64d43ff0c18 8967 #define NV_FOPT_EZPORT_DIS_MASK 0x2u
mbed_official 146:f64d43ff0c18 8968 #define NV_FOPT_EZPORT_DIS_SHIFT 1
mbed_official 146:f64d43ff0c18 8969 /* FEPROT Bit Fields */
mbed_official 146:f64d43ff0c18 8970 #define NV_FEPROT_EPROT_MASK 0xFFu
mbed_official 146:f64d43ff0c18 8971 #define NV_FEPROT_EPROT_SHIFT 0
mbed_official 146:f64d43ff0c18 8972 #define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)
mbed_official 146:f64d43ff0c18 8973 /* FDPROT Bit Fields */
mbed_official 146:f64d43ff0c18 8974 #define NV_FDPROT_DPROT_MASK 0xFFu
mbed_official 146:f64d43ff0c18 8975 #define NV_FDPROT_DPROT_SHIFT 0
mbed_official 146:f64d43ff0c18 8976 #define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)
mbed_official 146:f64d43ff0c18 8977
mbed_official 146:f64d43ff0c18 8978 /*!
mbed_official 146:f64d43ff0c18 8979 * @}
mbed_official 146:f64d43ff0c18 8980 */ /* end of group NV_Register_Masks */
mbed_official 146:f64d43ff0c18 8981
mbed_official 146:f64d43ff0c18 8982
mbed_official 146:f64d43ff0c18 8983 /* NV - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 8984 /** Peripheral FTFE_FlashConfig base address */
mbed_official 146:f64d43ff0c18 8985 #define FTFE_FlashConfig_BASE (0x400u)
mbed_official 146:f64d43ff0c18 8986 /** Peripheral FTFE_FlashConfig base pointer */
mbed_official 146:f64d43ff0c18 8987 #define FTFE_FlashConfig ((NV_Type *)FTFE_FlashConfig_BASE)
mbed_official 146:f64d43ff0c18 8988 #define FTFE_FlashConfig_BASE_PTR (FTFE_FlashConfig)
mbed_official 146:f64d43ff0c18 8989 /** Array initializer of NV peripheral base pointers */
mbed_official 146:f64d43ff0c18 8990 #define NV_BASES { FTFE_FlashConfig }
mbed_official 146:f64d43ff0c18 8991
mbed_official 146:f64d43ff0c18 8992 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 8993 -- NV - Register accessor macros
mbed_official 146:f64d43ff0c18 8994 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 8995
mbed_official 146:f64d43ff0c18 8996 /*!
mbed_official 146:f64d43ff0c18 8997 * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
mbed_official 146:f64d43ff0c18 8998 * @{
mbed_official 146:f64d43ff0c18 8999 */
mbed_official 146:f64d43ff0c18 9000
mbed_official 146:f64d43ff0c18 9001
mbed_official 146:f64d43ff0c18 9002 /* NV - Register instance definitions */
mbed_official 146:f64d43ff0c18 9003 /* FTFE_FlashConfig */
mbed_official 146:f64d43ff0c18 9004 #define NV_BACKKEY3 NV_BACKKEY3_REG(FTFE_FlashConfig)
mbed_official 146:f64d43ff0c18 9005 #define NV_BACKKEY2 NV_BACKKEY2_REG(FTFE_FlashConfig)
mbed_official 146:f64d43ff0c18 9006 #define NV_BACKKEY1 NV_BACKKEY1_REG(FTFE_FlashConfig)
mbed_official 146:f64d43ff0c18 9007 #define NV_BACKKEY0 NV_BACKKEY0_REG(FTFE_FlashConfig)
mbed_official 146:f64d43ff0c18 9008 #define NV_BACKKEY7 NV_BACKKEY7_REG(FTFE_FlashConfig)
mbed_official 146:f64d43ff0c18 9009 #define NV_BACKKEY6 NV_BACKKEY6_REG(FTFE_FlashConfig)
mbed_official 146:f64d43ff0c18 9010 #define NV_BACKKEY5 NV_BACKKEY5_REG(FTFE_FlashConfig)
mbed_official 146:f64d43ff0c18 9011 #define NV_BACKKEY4 NV_BACKKEY4_REG(FTFE_FlashConfig)
mbed_official 146:f64d43ff0c18 9012 #define NV_FPROT3 NV_FPROT3_REG(FTFE_FlashConfig)
mbed_official 146:f64d43ff0c18 9013 #define NV_FPROT2 NV_FPROT2_REG(FTFE_FlashConfig)
mbed_official 146:f64d43ff0c18 9014 #define NV_FPROT1 NV_FPROT1_REG(FTFE_FlashConfig)
mbed_official 146:f64d43ff0c18 9015 #define NV_FPROT0 NV_FPROT0_REG(FTFE_FlashConfig)
mbed_official 146:f64d43ff0c18 9016 #define NV_FSEC NV_FSEC_REG(FTFE_FlashConfig)
mbed_official 146:f64d43ff0c18 9017 #define NV_FOPT NV_FOPT_REG(FTFE_FlashConfig)
mbed_official 146:f64d43ff0c18 9018 #define NV_FEPROT NV_FEPROT_REG(FTFE_FlashConfig)
mbed_official 146:f64d43ff0c18 9019 #define NV_FDPROT NV_FDPROT_REG(FTFE_FlashConfig)
mbed_official 146:f64d43ff0c18 9020
mbed_official 146:f64d43ff0c18 9021 /*!
mbed_official 146:f64d43ff0c18 9022 * @}
mbed_official 146:f64d43ff0c18 9023 */ /* end of group NV_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 9024
mbed_official 146:f64d43ff0c18 9025
mbed_official 146:f64d43ff0c18 9026 /*!
mbed_official 146:f64d43ff0c18 9027 * @}
mbed_official 146:f64d43ff0c18 9028 */ /* end of group NV_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 9029
mbed_official 146:f64d43ff0c18 9030
mbed_official 146:f64d43ff0c18 9031 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 9032 -- OSC Peripheral Access Layer
mbed_official 146:f64d43ff0c18 9033 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 9034
mbed_official 146:f64d43ff0c18 9035 /*!
mbed_official 146:f64d43ff0c18 9036 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
mbed_official 146:f64d43ff0c18 9037 * @{
mbed_official 146:f64d43ff0c18 9038 */
mbed_official 146:f64d43ff0c18 9039
mbed_official 146:f64d43ff0c18 9040 /** OSC - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 9041 typedef struct {
mbed_official 146:f64d43ff0c18 9042 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
mbed_official 146:f64d43ff0c18 9043 } OSC_Type, *OSC_MemMapPtr;
mbed_official 146:f64d43ff0c18 9044
mbed_official 146:f64d43ff0c18 9045 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 9046 -- OSC - Register accessor macros
mbed_official 146:f64d43ff0c18 9047 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 9048
mbed_official 146:f64d43ff0c18 9049 /*!
mbed_official 146:f64d43ff0c18 9050 * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
mbed_official 146:f64d43ff0c18 9051 * @{
mbed_official 146:f64d43ff0c18 9052 */
mbed_official 146:f64d43ff0c18 9053
mbed_official 146:f64d43ff0c18 9054
mbed_official 146:f64d43ff0c18 9055 /* OSC - Register accessors */
mbed_official 146:f64d43ff0c18 9056 #define OSC_CR_REG(base) ((base)->CR)
mbed_official 146:f64d43ff0c18 9057
mbed_official 146:f64d43ff0c18 9058 /*!
mbed_official 146:f64d43ff0c18 9059 * @}
mbed_official 146:f64d43ff0c18 9060 */ /* end of group OSC_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 9061
mbed_official 146:f64d43ff0c18 9062
mbed_official 146:f64d43ff0c18 9063 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 9064 -- OSC Register Masks
mbed_official 146:f64d43ff0c18 9065 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 9066
mbed_official 146:f64d43ff0c18 9067 /*!
mbed_official 146:f64d43ff0c18 9068 * @addtogroup OSC_Register_Masks OSC Register Masks
mbed_official 146:f64d43ff0c18 9069 * @{
mbed_official 146:f64d43ff0c18 9070 */
mbed_official 146:f64d43ff0c18 9071
mbed_official 146:f64d43ff0c18 9072 /* CR Bit Fields */
mbed_official 146:f64d43ff0c18 9073 #define OSC_CR_SC16P_MASK 0x1u
mbed_official 146:f64d43ff0c18 9074 #define OSC_CR_SC16P_SHIFT 0
mbed_official 146:f64d43ff0c18 9075 #define OSC_CR_SC8P_MASK 0x2u
mbed_official 146:f64d43ff0c18 9076 #define OSC_CR_SC8P_SHIFT 1
mbed_official 146:f64d43ff0c18 9077 #define OSC_CR_SC4P_MASK 0x4u
mbed_official 146:f64d43ff0c18 9078 #define OSC_CR_SC4P_SHIFT 2
mbed_official 146:f64d43ff0c18 9079 #define OSC_CR_SC2P_MASK 0x8u
mbed_official 146:f64d43ff0c18 9080 #define OSC_CR_SC2P_SHIFT 3
mbed_official 146:f64d43ff0c18 9081 #define OSC_CR_EREFSTEN_MASK 0x20u
mbed_official 146:f64d43ff0c18 9082 #define OSC_CR_EREFSTEN_SHIFT 5
mbed_official 146:f64d43ff0c18 9083 #define OSC_CR_ERCLKEN_MASK 0x80u
mbed_official 146:f64d43ff0c18 9084 #define OSC_CR_ERCLKEN_SHIFT 7
mbed_official 146:f64d43ff0c18 9085
mbed_official 146:f64d43ff0c18 9086 /*!
mbed_official 146:f64d43ff0c18 9087 * @}
mbed_official 146:f64d43ff0c18 9088 */ /* end of group OSC_Register_Masks */
mbed_official 146:f64d43ff0c18 9089
mbed_official 146:f64d43ff0c18 9090
mbed_official 146:f64d43ff0c18 9091 /* OSC - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 9092 /** Peripheral OSC base address */
mbed_official 146:f64d43ff0c18 9093 #define OSC_BASE (0x40065000u)
mbed_official 146:f64d43ff0c18 9094 /** Peripheral OSC base pointer */
mbed_official 146:f64d43ff0c18 9095 #define OSC ((OSC_Type *)OSC_BASE)
mbed_official 146:f64d43ff0c18 9096 #define OSC_BASE_PTR (OSC)
mbed_official 146:f64d43ff0c18 9097 /** Array initializer of OSC peripheral base pointers */
mbed_official 146:f64d43ff0c18 9098 #define OSC_BASES { OSC }
mbed_official 146:f64d43ff0c18 9099
mbed_official 146:f64d43ff0c18 9100 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 9101 -- OSC - Register accessor macros
mbed_official 146:f64d43ff0c18 9102 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 9103
mbed_official 146:f64d43ff0c18 9104 /*!
mbed_official 146:f64d43ff0c18 9105 * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
mbed_official 146:f64d43ff0c18 9106 * @{
mbed_official 146:f64d43ff0c18 9107 */
mbed_official 146:f64d43ff0c18 9108
mbed_official 146:f64d43ff0c18 9109
mbed_official 146:f64d43ff0c18 9110 /* OSC - Register instance definitions */
mbed_official 146:f64d43ff0c18 9111 /* OSC */
mbed_official 146:f64d43ff0c18 9112 #define OSC_CR OSC_CR_REG(OSC)
mbed_official 146:f64d43ff0c18 9113
mbed_official 146:f64d43ff0c18 9114 /*!
mbed_official 146:f64d43ff0c18 9115 * @}
mbed_official 146:f64d43ff0c18 9116 */ /* end of group OSC_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 9117
mbed_official 146:f64d43ff0c18 9118
mbed_official 146:f64d43ff0c18 9119 /*!
mbed_official 146:f64d43ff0c18 9120 * @}
mbed_official 146:f64d43ff0c18 9121 */ /* end of group OSC_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 9122
mbed_official 146:f64d43ff0c18 9123
mbed_official 146:f64d43ff0c18 9124 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 9125 -- PDB Peripheral Access Layer
mbed_official 146:f64d43ff0c18 9126 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 9127
mbed_official 146:f64d43ff0c18 9128 /*!
mbed_official 146:f64d43ff0c18 9129 * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
mbed_official 146:f64d43ff0c18 9130 * @{
mbed_official 146:f64d43ff0c18 9131 */
mbed_official 146:f64d43ff0c18 9132
mbed_official 146:f64d43ff0c18 9133 /** PDB - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 9134 typedef struct {
mbed_official 146:f64d43ff0c18 9135 __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */
mbed_official 146:f64d43ff0c18 9136 __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */
mbed_official 146:f64d43ff0c18 9137 __I uint32_t CNT; /**< Counter register, offset: 0x8 */
mbed_official 146:f64d43ff0c18 9138 __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */
mbed_official 146:f64d43ff0c18 9139 struct { /* offset: 0x10, array step: 0x28 */
mbed_official 146:f64d43ff0c18 9140 __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
mbed_official 146:f64d43ff0c18 9141 __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
mbed_official 146:f64d43ff0c18 9142 __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
mbed_official 146:f64d43ff0c18 9143 uint8_t RESERVED_0[24];
mbed_official 146:f64d43ff0c18 9144 } CH[2];
mbed_official 146:f64d43ff0c18 9145 uint8_t RESERVED_0[240];
mbed_official 146:f64d43ff0c18 9146 struct { /* offset: 0x150, array step: 0x8 */
mbed_official 146:f64d43ff0c18 9147 __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
mbed_official 146:f64d43ff0c18 9148 __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
mbed_official 146:f64d43ff0c18 9149 } DAC[2];
mbed_official 146:f64d43ff0c18 9150 uint8_t RESERVED_1[48];
mbed_official 146:f64d43ff0c18 9151 __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */
mbed_official 146:f64d43ff0c18 9152 __IO uint32_t PODLY[3]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
mbed_official 146:f64d43ff0c18 9153 } PDB_Type, *PDB_MemMapPtr;
mbed_official 146:f64d43ff0c18 9154
mbed_official 146:f64d43ff0c18 9155 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 9156 -- PDB - Register accessor macros
mbed_official 146:f64d43ff0c18 9157 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 9158
mbed_official 146:f64d43ff0c18 9159 /*!
mbed_official 146:f64d43ff0c18 9160 * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
mbed_official 146:f64d43ff0c18 9161 * @{
mbed_official 146:f64d43ff0c18 9162 */
mbed_official 146:f64d43ff0c18 9163
mbed_official 146:f64d43ff0c18 9164
mbed_official 146:f64d43ff0c18 9165 /* PDB - Register accessors */
mbed_official 146:f64d43ff0c18 9166 #define PDB_SC_REG(base) ((base)->SC)
mbed_official 146:f64d43ff0c18 9167 #define PDB_MOD_REG(base) ((base)->MOD)
mbed_official 146:f64d43ff0c18 9168 #define PDB_CNT_REG(base) ((base)->CNT)
mbed_official 146:f64d43ff0c18 9169 #define PDB_IDLY_REG(base) ((base)->IDLY)
mbed_official 146:f64d43ff0c18 9170 #define PDB_C1_REG(base,index) ((base)->CH[index].C1)
mbed_official 146:f64d43ff0c18 9171 #define PDB_S_REG(base,index) ((base)->CH[index].S)
mbed_official 146:f64d43ff0c18 9172 #define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2])
mbed_official 146:f64d43ff0c18 9173 #define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC)
mbed_official 146:f64d43ff0c18 9174 #define PDB_INT_REG(base,index) ((base)->DAC[index].INT)
mbed_official 146:f64d43ff0c18 9175 #define PDB_POEN_REG(base) ((base)->POEN)
mbed_official 146:f64d43ff0c18 9176 #define PDB_PODLY_REG(base,index) ((base)->PODLY[index])
mbed_official 146:f64d43ff0c18 9177
mbed_official 146:f64d43ff0c18 9178 /*!
mbed_official 146:f64d43ff0c18 9179 * @}
mbed_official 146:f64d43ff0c18 9180 */ /* end of group PDB_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 9181
mbed_official 146:f64d43ff0c18 9182
mbed_official 146:f64d43ff0c18 9183 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 9184 -- PDB Register Masks
mbed_official 146:f64d43ff0c18 9185 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 9186
mbed_official 146:f64d43ff0c18 9187 /*!
mbed_official 146:f64d43ff0c18 9188 * @addtogroup PDB_Register_Masks PDB Register Masks
mbed_official 146:f64d43ff0c18 9189 * @{
mbed_official 146:f64d43ff0c18 9190 */
mbed_official 146:f64d43ff0c18 9191
mbed_official 146:f64d43ff0c18 9192 /* SC Bit Fields */
mbed_official 146:f64d43ff0c18 9193 #define PDB_SC_LDOK_MASK 0x1u
mbed_official 146:f64d43ff0c18 9194 #define PDB_SC_LDOK_SHIFT 0
mbed_official 146:f64d43ff0c18 9195 #define PDB_SC_CONT_MASK 0x2u
mbed_official 146:f64d43ff0c18 9196 #define PDB_SC_CONT_SHIFT 1
mbed_official 146:f64d43ff0c18 9197 #define PDB_SC_MULT_MASK 0xCu
mbed_official 146:f64d43ff0c18 9198 #define PDB_SC_MULT_SHIFT 2
mbed_official 146:f64d43ff0c18 9199 #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
mbed_official 146:f64d43ff0c18 9200 #define PDB_SC_PDBIE_MASK 0x20u
mbed_official 146:f64d43ff0c18 9201 #define PDB_SC_PDBIE_SHIFT 5
mbed_official 146:f64d43ff0c18 9202 #define PDB_SC_PDBIF_MASK 0x40u
mbed_official 146:f64d43ff0c18 9203 #define PDB_SC_PDBIF_SHIFT 6
mbed_official 146:f64d43ff0c18 9204 #define PDB_SC_PDBEN_MASK 0x80u
mbed_official 146:f64d43ff0c18 9205 #define PDB_SC_PDBEN_SHIFT 7
mbed_official 146:f64d43ff0c18 9206 #define PDB_SC_TRGSEL_MASK 0xF00u
mbed_official 146:f64d43ff0c18 9207 #define PDB_SC_TRGSEL_SHIFT 8
mbed_official 146:f64d43ff0c18 9208 #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
mbed_official 146:f64d43ff0c18 9209 #define PDB_SC_PRESCALER_MASK 0x7000u
mbed_official 146:f64d43ff0c18 9210 #define PDB_SC_PRESCALER_SHIFT 12
mbed_official 146:f64d43ff0c18 9211 #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
mbed_official 146:f64d43ff0c18 9212 #define PDB_SC_DMAEN_MASK 0x8000u
mbed_official 146:f64d43ff0c18 9213 #define PDB_SC_DMAEN_SHIFT 15
mbed_official 146:f64d43ff0c18 9214 #define PDB_SC_SWTRIG_MASK 0x10000u
mbed_official 146:f64d43ff0c18 9215 #define PDB_SC_SWTRIG_SHIFT 16
mbed_official 146:f64d43ff0c18 9216 #define PDB_SC_PDBEIE_MASK 0x20000u
mbed_official 146:f64d43ff0c18 9217 #define PDB_SC_PDBEIE_SHIFT 17
mbed_official 146:f64d43ff0c18 9218 #define PDB_SC_LDMOD_MASK 0xC0000u
mbed_official 146:f64d43ff0c18 9219 #define PDB_SC_LDMOD_SHIFT 18
mbed_official 146:f64d43ff0c18 9220 #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
mbed_official 146:f64d43ff0c18 9221 /* MOD Bit Fields */
mbed_official 146:f64d43ff0c18 9222 #define PDB_MOD_MOD_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 9223 #define PDB_MOD_MOD_SHIFT 0
mbed_official 146:f64d43ff0c18 9224 #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
mbed_official 146:f64d43ff0c18 9225 /* CNT Bit Fields */
mbed_official 146:f64d43ff0c18 9226 #define PDB_CNT_CNT_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 9227 #define PDB_CNT_CNT_SHIFT 0
mbed_official 146:f64d43ff0c18 9228 #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
mbed_official 146:f64d43ff0c18 9229 /* IDLY Bit Fields */
mbed_official 146:f64d43ff0c18 9230 #define PDB_IDLY_IDLY_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 9231 #define PDB_IDLY_IDLY_SHIFT 0
mbed_official 146:f64d43ff0c18 9232 #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
mbed_official 146:f64d43ff0c18 9233 /* C1 Bit Fields */
mbed_official 146:f64d43ff0c18 9234 #define PDB_C1_EN_MASK 0xFFu
mbed_official 146:f64d43ff0c18 9235 #define PDB_C1_EN_SHIFT 0
mbed_official 146:f64d43ff0c18 9236 #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
mbed_official 146:f64d43ff0c18 9237 #define PDB_C1_TOS_MASK 0xFF00u
mbed_official 146:f64d43ff0c18 9238 #define PDB_C1_TOS_SHIFT 8
mbed_official 146:f64d43ff0c18 9239 #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
mbed_official 146:f64d43ff0c18 9240 #define PDB_C1_BB_MASK 0xFF0000u
mbed_official 146:f64d43ff0c18 9241 #define PDB_C1_BB_SHIFT 16
mbed_official 146:f64d43ff0c18 9242 #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
mbed_official 146:f64d43ff0c18 9243 /* S Bit Fields */
mbed_official 146:f64d43ff0c18 9244 #define PDB_S_ERR_MASK 0xFFu
mbed_official 146:f64d43ff0c18 9245 #define PDB_S_ERR_SHIFT 0
mbed_official 146:f64d43ff0c18 9246 #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
mbed_official 146:f64d43ff0c18 9247 #define PDB_S_CF_MASK 0xFF0000u
mbed_official 146:f64d43ff0c18 9248 #define PDB_S_CF_SHIFT 16
mbed_official 146:f64d43ff0c18 9249 #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
mbed_official 146:f64d43ff0c18 9250 /* DLY Bit Fields */
mbed_official 146:f64d43ff0c18 9251 #define PDB_DLY_DLY_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 9252 #define PDB_DLY_DLY_SHIFT 0
mbed_official 146:f64d43ff0c18 9253 #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
mbed_official 146:f64d43ff0c18 9254 /* INTC Bit Fields */
mbed_official 146:f64d43ff0c18 9255 #define PDB_INTC_TOE_MASK 0x1u
mbed_official 146:f64d43ff0c18 9256 #define PDB_INTC_TOE_SHIFT 0
mbed_official 146:f64d43ff0c18 9257 #define PDB_INTC_EXT_MASK 0x2u
mbed_official 146:f64d43ff0c18 9258 #define PDB_INTC_EXT_SHIFT 1
mbed_official 146:f64d43ff0c18 9259 /* INT Bit Fields */
mbed_official 146:f64d43ff0c18 9260 #define PDB_INT_INT_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 9261 #define PDB_INT_INT_SHIFT 0
mbed_official 146:f64d43ff0c18 9262 #define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x))<<PDB_INT_INT_SHIFT))&PDB_INT_INT_MASK)
mbed_official 146:f64d43ff0c18 9263 /* POEN Bit Fields */
mbed_official 146:f64d43ff0c18 9264 #define PDB_POEN_POEN_MASK 0xFFu
mbed_official 146:f64d43ff0c18 9265 #define PDB_POEN_POEN_SHIFT 0
mbed_official 146:f64d43ff0c18 9266 #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
mbed_official 146:f64d43ff0c18 9267 /* PODLY Bit Fields */
mbed_official 146:f64d43ff0c18 9268 #define PDB_PODLY_DLY2_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 9269 #define PDB_PODLY_DLY2_SHIFT 0
mbed_official 146:f64d43ff0c18 9270 #define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
mbed_official 146:f64d43ff0c18 9271 #define PDB_PODLY_DLY1_MASK 0xFFFF0000u
mbed_official 146:f64d43ff0c18 9272 #define PDB_PODLY_DLY1_SHIFT 16
mbed_official 146:f64d43ff0c18 9273 #define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
mbed_official 146:f64d43ff0c18 9274
mbed_official 146:f64d43ff0c18 9275 /*!
mbed_official 146:f64d43ff0c18 9276 * @}
mbed_official 146:f64d43ff0c18 9277 */ /* end of group PDB_Register_Masks */
mbed_official 146:f64d43ff0c18 9278
mbed_official 146:f64d43ff0c18 9279
mbed_official 146:f64d43ff0c18 9280 /* PDB - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 9281 /** Peripheral PDB0 base address */
mbed_official 146:f64d43ff0c18 9282 #define PDB0_BASE (0x40036000u)
mbed_official 146:f64d43ff0c18 9283 /** Peripheral PDB0 base pointer */
mbed_official 146:f64d43ff0c18 9284 #define PDB0 ((PDB_Type *)PDB0_BASE)
mbed_official 146:f64d43ff0c18 9285 #define PDB0_BASE_PTR (PDB0)
mbed_official 146:f64d43ff0c18 9286 /** Array initializer of PDB peripheral base pointers */
mbed_official 146:f64d43ff0c18 9287 #define PDB_BASES { PDB0 }
mbed_official 146:f64d43ff0c18 9288
mbed_official 146:f64d43ff0c18 9289 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 9290 -- PDB - Register accessor macros
mbed_official 146:f64d43ff0c18 9291 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 9292
mbed_official 146:f64d43ff0c18 9293 /*!
mbed_official 146:f64d43ff0c18 9294 * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
mbed_official 146:f64d43ff0c18 9295 * @{
mbed_official 146:f64d43ff0c18 9296 */
mbed_official 146:f64d43ff0c18 9297
mbed_official 146:f64d43ff0c18 9298
mbed_official 146:f64d43ff0c18 9299 /* PDB - Register instance definitions */
mbed_official 146:f64d43ff0c18 9300 /* PDB0 */
mbed_official 146:f64d43ff0c18 9301 #define PDB0_SC PDB_SC_REG(PDB0)
mbed_official 146:f64d43ff0c18 9302 #define PDB0_MOD PDB_MOD_REG(PDB0)
mbed_official 146:f64d43ff0c18 9303 #define PDB0_CNT PDB_CNT_REG(PDB0)
mbed_official 146:f64d43ff0c18 9304 #define PDB0_IDLY PDB_IDLY_REG(PDB0)
mbed_official 146:f64d43ff0c18 9305 #define PDB0_CH0C1 PDB_C1_REG(PDB0,0)
mbed_official 146:f64d43ff0c18 9306 #define PDB0_CH0S PDB_S_REG(PDB0,0)
mbed_official 146:f64d43ff0c18 9307 #define PDB0_CH0DLY0 PDB_DLY_REG(PDB0,0,0)
mbed_official 146:f64d43ff0c18 9308 #define PDB0_CH0DLY1 PDB_DLY_REG(PDB0,0,1)
mbed_official 146:f64d43ff0c18 9309 #define PDB0_CH1C1 PDB_C1_REG(PDB0,1)
mbed_official 146:f64d43ff0c18 9310 #define PDB0_CH1S PDB_S_REG(PDB0,1)
mbed_official 146:f64d43ff0c18 9311 #define PDB0_CH1DLY0 PDB_DLY_REG(PDB0,1,0)
mbed_official 146:f64d43ff0c18 9312 #define PDB0_CH1DLY1 PDB_DLY_REG(PDB0,1,1)
mbed_official 146:f64d43ff0c18 9313 #define PDB0_DACINTC0 PDB_INTC_REG(PDB0,0)
mbed_official 146:f64d43ff0c18 9314 #define PDB0_DACINT0 PDB_INT_REG(PDB0,0)
mbed_official 146:f64d43ff0c18 9315 #define PDB0_DACINTC1 PDB_INTC_REG(PDB0,1)
mbed_official 146:f64d43ff0c18 9316 #define PDB0_DACINT1 PDB_INT_REG(PDB0,1)
mbed_official 146:f64d43ff0c18 9317 #define PDB0_POEN PDB_POEN_REG(PDB0)
mbed_official 146:f64d43ff0c18 9318 #define PDB0_PO0DLY PDB_PODLY_REG(PDB0,0)
mbed_official 146:f64d43ff0c18 9319 #define PDB0_PO1DLY PDB_PODLY_REG(PDB0,1)
mbed_official 146:f64d43ff0c18 9320 #define PDB0_PO2DLY PDB_PODLY_REG(PDB0,2)
mbed_official 146:f64d43ff0c18 9321
mbed_official 146:f64d43ff0c18 9322 /* PDB - Register array accessors */
mbed_official 146:f64d43ff0c18 9323 #define PDB0_C1(index) PDB_C1_REG(PDB0,index)
mbed_official 146:f64d43ff0c18 9324 #define PDB0_S(index) PDB_S_REG(PDB0,index)
mbed_official 146:f64d43ff0c18 9325 #define PDB0_DLY(index,index2) PDB_DLY_REG(PDB0,index,index2)
mbed_official 146:f64d43ff0c18 9326 #define PDB0_INTC(index) PDB_INTC_REG(PDB0,index)
mbed_official 146:f64d43ff0c18 9327 #define PDB0_INT(index) PDB_INT_REG(PDB0,index)
mbed_official 146:f64d43ff0c18 9328 #define PDB0_PODLY(index) PDB_PODLY_REG(PDB0,index)
mbed_official 146:f64d43ff0c18 9329
mbed_official 146:f64d43ff0c18 9330 /*!
mbed_official 146:f64d43ff0c18 9331 * @}
mbed_official 146:f64d43ff0c18 9332 */ /* end of group PDB_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 9333
mbed_official 146:f64d43ff0c18 9334
mbed_official 146:f64d43ff0c18 9335 /*!
mbed_official 146:f64d43ff0c18 9336 * @}
mbed_official 146:f64d43ff0c18 9337 */ /* end of group PDB_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 9338
mbed_official 146:f64d43ff0c18 9339
mbed_official 146:f64d43ff0c18 9340 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 9341 -- PIT Peripheral Access Layer
mbed_official 146:f64d43ff0c18 9342 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 9343
mbed_official 146:f64d43ff0c18 9344 /*!
mbed_official 146:f64d43ff0c18 9345 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
mbed_official 146:f64d43ff0c18 9346 * @{
mbed_official 146:f64d43ff0c18 9347 */
mbed_official 146:f64d43ff0c18 9348
mbed_official 146:f64d43ff0c18 9349 /** PIT - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 9350 typedef struct {
mbed_official 146:f64d43ff0c18 9351 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
mbed_official 146:f64d43ff0c18 9352 uint8_t RESERVED_0[252];
mbed_official 146:f64d43ff0c18 9353 struct { /* offset: 0x100, array step: 0x10 */
mbed_official 146:f64d43ff0c18 9354 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
mbed_official 146:f64d43ff0c18 9355 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
mbed_official 146:f64d43ff0c18 9356 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
mbed_official 146:f64d43ff0c18 9357 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
mbed_official 146:f64d43ff0c18 9358 } CHANNEL[4];
mbed_official 146:f64d43ff0c18 9359 } PIT_Type, *PIT_MemMapPtr;
mbed_official 146:f64d43ff0c18 9360
mbed_official 146:f64d43ff0c18 9361 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 9362 -- PIT - Register accessor macros
mbed_official 146:f64d43ff0c18 9363 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 9364
mbed_official 146:f64d43ff0c18 9365 /*!
mbed_official 146:f64d43ff0c18 9366 * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
mbed_official 146:f64d43ff0c18 9367 * @{
mbed_official 146:f64d43ff0c18 9368 */
mbed_official 146:f64d43ff0c18 9369
mbed_official 146:f64d43ff0c18 9370
mbed_official 146:f64d43ff0c18 9371 /* PIT - Register accessors */
mbed_official 146:f64d43ff0c18 9372 #define PIT_MCR_REG(base) ((base)->MCR)
mbed_official 146:f64d43ff0c18 9373 #define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL)
mbed_official 146:f64d43ff0c18 9374 #define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL)
mbed_official 146:f64d43ff0c18 9375 #define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL)
mbed_official 146:f64d43ff0c18 9376 #define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG)
mbed_official 146:f64d43ff0c18 9377
mbed_official 146:f64d43ff0c18 9378 /*!
mbed_official 146:f64d43ff0c18 9379 * @}
mbed_official 146:f64d43ff0c18 9380 */ /* end of group PIT_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 9381
mbed_official 146:f64d43ff0c18 9382
mbed_official 146:f64d43ff0c18 9383 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 9384 -- PIT Register Masks
mbed_official 146:f64d43ff0c18 9385 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 9386
mbed_official 146:f64d43ff0c18 9387 /*!
mbed_official 146:f64d43ff0c18 9388 * @addtogroup PIT_Register_Masks PIT Register Masks
mbed_official 146:f64d43ff0c18 9389 * @{
mbed_official 146:f64d43ff0c18 9390 */
mbed_official 146:f64d43ff0c18 9391
mbed_official 146:f64d43ff0c18 9392 /* MCR Bit Fields */
mbed_official 146:f64d43ff0c18 9393 #define PIT_MCR_FRZ_MASK 0x1u
mbed_official 146:f64d43ff0c18 9394 #define PIT_MCR_FRZ_SHIFT 0
mbed_official 146:f64d43ff0c18 9395 #define PIT_MCR_MDIS_MASK 0x2u
mbed_official 146:f64d43ff0c18 9396 #define PIT_MCR_MDIS_SHIFT 1
mbed_official 146:f64d43ff0c18 9397 /* LDVAL Bit Fields */
mbed_official 146:f64d43ff0c18 9398 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 9399 #define PIT_LDVAL_TSV_SHIFT 0
mbed_official 146:f64d43ff0c18 9400 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
mbed_official 146:f64d43ff0c18 9401 /* CVAL Bit Fields */
mbed_official 146:f64d43ff0c18 9402 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 9403 #define PIT_CVAL_TVL_SHIFT 0
mbed_official 146:f64d43ff0c18 9404 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
mbed_official 146:f64d43ff0c18 9405 /* TCTRL Bit Fields */
mbed_official 146:f64d43ff0c18 9406 #define PIT_TCTRL_TEN_MASK 0x1u
mbed_official 146:f64d43ff0c18 9407 #define PIT_TCTRL_TEN_SHIFT 0
mbed_official 146:f64d43ff0c18 9408 #define PIT_TCTRL_TIE_MASK 0x2u
mbed_official 146:f64d43ff0c18 9409 #define PIT_TCTRL_TIE_SHIFT 1
mbed_official 146:f64d43ff0c18 9410 #define PIT_TCTRL_CHN_MASK 0x4u
mbed_official 146:f64d43ff0c18 9411 #define PIT_TCTRL_CHN_SHIFT 2
mbed_official 146:f64d43ff0c18 9412 /* TFLG Bit Fields */
mbed_official 146:f64d43ff0c18 9413 #define PIT_TFLG_TIF_MASK 0x1u
mbed_official 146:f64d43ff0c18 9414 #define PIT_TFLG_TIF_SHIFT 0
mbed_official 146:f64d43ff0c18 9415
mbed_official 146:f64d43ff0c18 9416 /*!
mbed_official 146:f64d43ff0c18 9417 * @}
mbed_official 146:f64d43ff0c18 9418 */ /* end of group PIT_Register_Masks */
mbed_official 146:f64d43ff0c18 9419
mbed_official 146:f64d43ff0c18 9420
mbed_official 146:f64d43ff0c18 9421 /* PIT - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 9422 /** Peripheral PIT base address */
mbed_official 146:f64d43ff0c18 9423 #define PIT_BASE (0x40037000u)
mbed_official 146:f64d43ff0c18 9424 /** Peripheral PIT base pointer */
mbed_official 146:f64d43ff0c18 9425 #define PIT ((PIT_Type *)PIT_BASE)
mbed_official 146:f64d43ff0c18 9426 #define PIT_BASE_PTR (PIT)
mbed_official 146:f64d43ff0c18 9427 /** Array initializer of PIT peripheral base pointers */
mbed_official 146:f64d43ff0c18 9428 #define PIT_BASES { PIT }
mbed_official 146:f64d43ff0c18 9429
mbed_official 146:f64d43ff0c18 9430 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 9431 -- PIT - Register accessor macros
mbed_official 146:f64d43ff0c18 9432 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 9433
mbed_official 146:f64d43ff0c18 9434 /*!
mbed_official 146:f64d43ff0c18 9435 * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
mbed_official 146:f64d43ff0c18 9436 * @{
mbed_official 146:f64d43ff0c18 9437 */
mbed_official 146:f64d43ff0c18 9438
mbed_official 146:f64d43ff0c18 9439
mbed_official 146:f64d43ff0c18 9440 /* PIT - Register instance definitions */
mbed_official 146:f64d43ff0c18 9441 /* PIT */
mbed_official 146:f64d43ff0c18 9442 #define PIT_MCR PIT_MCR_REG(PIT)
mbed_official 146:f64d43ff0c18 9443 #define PIT_LDVAL0 PIT_LDVAL_REG(PIT,0)
mbed_official 146:f64d43ff0c18 9444 #define PIT_CVAL0 PIT_CVAL_REG(PIT,0)
mbed_official 146:f64d43ff0c18 9445 #define PIT_TCTRL0 PIT_TCTRL_REG(PIT,0)
mbed_official 146:f64d43ff0c18 9446 #define PIT_TFLG0 PIT_TFLG_REG(PIT,0)
mbed_official 146:f64d43ff0c18 9447 #define PIT_LDVAL1 PIT_LDVAL_REG(PIT,1)
mbed_official 146:f64d43ff0c18 9448 #define PIT_CVAL1 PIT_CVAL_REG(PIT,1)
mbed_official 146:f64d43ff0c18 9449 #define PIT_TCTRL1 PIT_TCTRL_REG(PIT,1)
mbed_official 146:f64d43ff0c18 9450 #define PIT_TFLG1 PIT_TFLG_REG(PIT,1)
mbed_official 146:f64d43ff0c18 9451 #define PIT_LDVAL2 PIT_LDVAL_REG(PIT,2)
mbed_official 146:f64d43ff0c18 9452 #define PIT_CVAL2 PIT_CVAL_REG(PIT,2)
mbed_official 146:f64d43ff0c18 9453 #define PIT_TCTRL2 PIT_TCTRL_REG(PIT,2)
mbed_official 146:f64d43ff0c18 9454 #define PIT_TFLG2 PIT_TFLG_REG(PIT,2)
mbed_official 146:f64d43ff0c18 9455 #define PIT_LDVAL3 PIT_LDVAL_REG(PIT,3)
mbed_official 146:f64d43ff0c18 9456 #define PIT_CVAL3 PIT_CVAL_REG(PIT,3)
mbed_official 146:f64d43ff0c18 9457 #define PIT_TCTRL3 PIT_TCTRL_REG(PIT,3)
mbed_official 146:f64d43ff0c18 9458 #define PIT_TFLG3 PIT_TFLG_REG(PIT,3)
mbed_official 146:f64d43ff0c18 9459
mbed_official 146:f64d43ff0c18 9460 /* PIT - Register array accessors */
mbed_official 146:f64d43ff0c18 9461 #define PIT_LDVAL(index) PIT_LDVAL_REG(PIT,index)
mbed_official 146:f64d43ff0c18 9462 #define PIT_CVAL(index) PIT_CVAL_REG(PIT,index)
mbed_official 146:f64d43ff0c18 9463 #define PIT_TCTRL(index) PIT_TCTRL_REG(PIT,index)
mbed_official 146:f64d43ff0c18 9464 #define PIT_TFLG(index) PIT_TFLG_REG(PIT,index)
mbed_official 146:f64d43ff0c18 9465
mbed_official 146:f64d43ff0c18 9466 /*!
mbed_official 146:f64d43ff0c18 9467 * @}
mbed_official 146:f64d43ff0c18 9468 */ /* end of group PIT_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 9469
mbed_official 146:f64d43ff0c18 9470
mbed_official 146:f64d43ff0c18 9471 /*!
mbed_official 146:f64d43ff0c18 9472 * @}
mbed_official 146:f64d43ff0c18 9473 */ /* end of group PIT_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 9474
mbed_official 146:f64d43ff0c18 9475
mbed_official 146:f64d43ff0c18 9476 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 9477 -- PMC Peripheral Access Layer
mbed_official 146:f64d43ff0c18 9478 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 9479
mbed_official 146:f64d43ff0c18 9480 /*!
mbed_official 146:f64d43ff0c18 9481 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
mbed_official 146:f64d43ff0c18 9482 * @{
mbed_official 146:f64d43ff0c18 9483 */
mbed_official 146:f64d43ff0c18 9484
mbed_official 146:f64d43ff0c18 9485 /** PMC - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 9486 typedef struct {
mbed_official 146:f64d43ff0c18 9487 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
mbed_official 146:f64d43ff0c18 9488 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
mbed_official 146:f64d43ff0c18 9489 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
mbed_official 146:f64d43ff0c18 9490 } PMC_Type, *PMC_MemMapPtr;
mbed_official 146:f64d43ff0c18 9491
mbed_official 146:f64d43ff0c18 9492 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 9493 -- PMC - Register accessor macros
mbed_official 146:f64d43ff0c18 9494 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 9495
mbed_official 146:f64d43ff0c18 9496 /*!
mbed_official 146:f64d43ff0c18 9497 * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
mbed_official 146:f64d43ff0c18 9498 * @{
mbed_official 146:f64d43ff0c18 9499 */
mbed_official 146:f64d43ff0c18 9500
mbed_official 146:f64d43ff0c18 9501
mbed_official 146:f64d43ff0c18 9502 /* PMC - Register accessors */
mbed_official 146:f64d43ff0c18 9503 #define PMC_LVDSC1_REG(base) ((base)->LVDSC1)
mbed_official 146:f64d43ff0c18 9504 #define PMC_LVDSC2_REG(base) ((base)->LVDSC2)
mbed_official 146:f64d43ff0c18 9505 #define PMC_REGSC_REG(base) ((base)->REGSC)
mbed_official 146:f64d43ff0c18 9506
mbed_official 146:f64d43ff0c18 9507 /*!
mbed_official 146:f64d43ff0c18 9508 * @}
mbed_official 146:f64d43ff0c18 9509 */ /* end of group PMC_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 9510
mbed_official 146:f64d43ff0c18 9511
mbed_official 146:f64d43ff0c18 9512 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 9513 -- PMC Register Masks
mbed_official 146:f64d43ff0c18 9514 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 9515
mbed_official 146:f64d43ff0c18 9516 /*!
mbed_official 146:f64d43ff0c18 9517 * @addtogroup PMC_Register_Masks PMC Register Masks
mbed_official 146:f64d43ff0c18 9518 * @{
mbed_official 146:f64d43ff0c18 9519 */
mbed_official 146:f64d43ff0c18 9520
mbed_official 146:f64d43ff0c18 9521 /* LVDSC1 Bit Fields */
mbed_official 146:f64d43ff0c18 9522 #define PMC_LVDSC1_LVDV_MASK 0x3u
mbed_official 146:f64d43ff0c18 9523 #define PMC_LVDSC1_LVDV_SHIFT 0
mbed_official 146:f64d43ff0c18 9524 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
mbed_official 146:f64d43ff0c18 9525 #define PMC_LVDSC1_LVDRE_MASK 0x10u
mbed_official 146:f64d43ff0c18 9526 #define PMC_LVDSC1_LVDRE_SHIFT 4
mbed_official 146:f64d43ff0c18 9527 #define PMC_LVDSC1_LVDIE_MASK 0x20u
mbed_official 146:f64d43ff0c18 9528 #define PMC_LVDSC1_LVDIE_SHIFT 5
mbed_official 146:f64d43ff0c18 9529 #define PMC_LVDSC1_LVDACK_MASK 0x40u
mbed_official 146:f64d43ff0c18 9530 #define PMC_LVDSC1_LVDACK_SHIFT 6
mbed_official 146:f64d43ff0c18 9531 #define PMC_LVDSC1_LVDF_MASK 0x80u
mbed_official 146:f64d43ff0c18 9532 #define PMC_LVDSC1_LVDF_SHIFT 7
mbed_official 146:f64d43ff0c18 9533 /* LVDSC2 Bit Fields */
mbed_official 146:f64d43ff0c18 9534 #define PMC_LVDSC2_LVWV_MASK 0x3u
mbed_official 146:f64d43ff0c18 9535 #define PMC_LVDSC2_LVWV_SHIFT 0
mbed_official 146:f64d43ff0c18 9536 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
mbed_official 146:f64d43ff0c18 9537 #define PMC_LVDSC2_LVWIE_MASK 0x20u
mbed_official 146:f64d43ff0c18 9538 #define PMC_LVDSC2_LVWIE_SHIFT 5
mbed_official 146:f64d43ff0c18 9539 #define PMC_LVDSC2_LVWACK_MASK 0x40u
mbed_official 146:f64d43ff0c18 9540 #define PMC_LVDSC2_LVWACK_SHIFT 6
mbed_official 146:f64d43ff0c18 9541 #define PMC_LVDSC2_LVWF_MASK 0x80u
mbed_official 146:f64d43ff0c18 9542 #define PMC_LVDSC2_LVWF_SHIFT 7
mbed_official 146:f64d43ff0c18 9543 /* REGSC Bit Fields */
mbed_official 146:f64d43ff0c18 9544 #define PMC_REGSC_BGBE_MASK 0x1u
mbed_official 146:f64d43ff0c18 9545 #define PMC_REGSC_BGBE_SHIFT 0
mbed_official 146:f64d43ff0c18 9546 #define PMC_REGSC_REGONS_MASK 0x4u
mbed_official 146:f64d43ff0c18 9547 #define PMC_REGSC_REGONS_SHIFT 2
mbed_official 146:f64d43ff0c18 9548 #define PMC_REGSC_ACKISO_MASK 0x8u
mbed_official 146:f64d43ff0c18 9549 #define PMC_REGSC_ACKISO_SHIFT 3
mbed_official 146:f64d43ff0c18 9550 #define PMC_REGSC_BGEN_MASK 0x10u
mbed_official 146:f64d43ff0c18 9551 #define PMC_REGSC_BGEN_SHIFT 4
mbed_official 146:f64d43ff0c18 9552
mbed_official 146:f64d43ff0c18 9553 /*!
mbed_official 146:f64d43ff0c18 9554 * @}
mbed_official 146:f64d43ff0c18 9555 */ /* end of group PMC_Register_Masks */
mbed_official 146:f64d43ff0c18 9556
mbed_official 146:f64d43ff0c18 9557
mbed_official 146:f64d43ff0c18 9558 /* PMC - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 9559 /** Peripheral PMC base address */
mbed_official 146:f64d43ff0c18 9560 #define PMC_BASE (0x4007D000u)
mbed_official 146:f64d43ff0c18 9561 /** Peripheral PMC base pointer */
mbed_official 146:f64d43ff0c18 9562 #define PMC ((PMC_Type *)PMC_BASE)
mbed_official 146:f64d43ff0c18 9563 #define PMC_BASE_PTR (PMC)
mbed_official 146:f64d43ff0c18 9564 /** Array initializer of PMC peripheral base pointers */
mbed_official 146:f64d43ff0c18 9565 #define PMC_BASES { PMC }
mbed_official 146:f64d43ff0c18 9566
mbed_official 146:f64d43ff0c18 9567 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 9568 -- PMC - Register accessor macros
mbed_official 146:f64d43ff0c18 9569 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 9570
mbed_official 146:f64d43ff0c18 9571 /*!
mbed_official 146:f64d43ff0c18 9572 * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
mbed_official 146:f64d43ff0c18 9573 * @{
mbed_official 146:f64d43ff0c18 9574 */
mbed_official 146:f64d43ff0c18 9575
mbed_official 146:f64d43ff0c18 9576
mbed_official 146:f64d43ff0c18 9577 /* PMC - Register instance definitions */
mbed_official 146:f64d43ff0c18 9578 /* PMC */
mbed_official 146:f64d43ff0c18 9579 #define PMC_LVDSC1 PMC_LVDSC1_REG(PMC)
mbed_official 146:f64d43ff0c18 9580 #define PMC_LVDSC2 PMC_LVDSC2_REG(PMC)
mbed_official 146:f64d43ff0c18 9581 #define PMC_REGSC PMC_REGSC_REG(PMC)
mbed_official 146:f64d43ff0c18 9582
mbed_official 146:f64d43ff0c18 9583 /*!
mbed_official 146:f64d43ff0c18 9584 * @}
mbed_official 146:f64d43ff0c18 9585 */ /* end of group PMC_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 9586
mbed_official 146:f64d43ff0c18 9587
mbed_official 146:f64d43ff0c18 9588 /*!
mbed_official 146:f64d43ff0c18 9589 * @}
mbed_official 146:f64d43ff0c18 9590 */ /* end of group PMC_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 9591
mbed_official 146:f64d43ff0c18 9592
mbed_official 146:f64d43ff0c18 9593 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 9594 -- PORT Peripheral Access Layer
mbed_official 146:f64d43ff0c18 9595 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 9596
mbed_official 146:f64d43ff0c18 9597 /*!
mbed_official 146:f64d43ff0c18 9598 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
mbed_official 146:f64d43ff0c18 9599 * @{
mbed_official 146:f64d43ff0c18 9600 */
mbed_official 146:f64d43ff0c18 9601
mbed_official 146:f64d43ff0c18 9602 /** PORT - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 9603 typedef struct {
mbed_official 146:f64d43ff0c18 9604 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
mbed_official 146:f64d43ff0c18 9605 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
mbed_official 146:f64d43ff0c18 9606 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
mbed_official 146:f64d43ff0c18 9607 uint8_t RESERVED_0[24];
mbed_official 146:f64d43ff0c18 9608 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
mbed_official 146:f64d43ff0c18 9609 uint8_t RESERVED_1[28];
mbed_official 146:f64d43ff0c18 9610 __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
mbed_official 146:f64d43ff0c18 9611 __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
mbed_official 146:f64d43ff0c18 9612 __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
mbed_official 146:f64d43ff0c18 9613 } PORT_Type, *PORT_MemMapPtr;
mbed_official 146:f64d43ff0c18 9614
mbed_official 146:f64d43ff0c18 9615 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 9616 -- PORT - Register accessor macros
mbed_official 146:f64d43ff0c18 9617 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 9618
mbed_official 146:f64d43ff0c18 9619 /*!
mbed_official 146:f64d43ff0c18 9620 * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
mbed_official 146:f64d43ff0c18 9621 * @{
mbed_official 146:f64d43ff0c18 9622 */
mbed_official 146:f64d43ff0c18 9623
mbed_official 146:f64d43ff0c18 9624
mbed_official 146:f64d43ff0c18 9625 /* PORT - Register accessors */
mbed_official 146:f64d43ff0c18 9626 #define PORT_PCR_REG(base,index) ((base)->PCR[index])
mbed_official 146:f64d43ff0c18 9627 #define PORT_GPCLR_REG(base) ((base)->GPCLR)
mbed_official 146:f64d43ff0c18 9628 #define PORT_GPCHR_REG(base) ((base)->GPCHR)
mbed_official 146:f64d43ff0c18 9629 #define PORT_ISFR_REG(base) ((base)->ISFR)
mbed_official 146:f64d43ff0c18 9630 #define PORT_DFER_REG(base) ((base)->DFER)
mbed_official 146:f64d43ff0c18 9631 #define PORT_DFCR_REG(base) ((base)->DFCR)
mbed_official 146:f64d43ff0c18 9632 #define PORT_DFWR_REG(base) ((base)->DFWR)
mbed_official 146:f64d43ff0c18 9633
mbed_official 146:f64d43ff0c18 9634 /*!
mbed_official 146:f64d43ff0c18 9635 * @}
mbed_official 146:f64d43ff0c18 9636 */ /* end of group PORT_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 9637
mbed_official 146:f64d43ff0c18 9638
mbed_official 146:f64d43ff0c18 9639 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 9640 -- PORT Register Masks
mbed_official 146:f64d43ff0c18 9641 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 9642
mbed_official 146:f64d43ff0c18 9643 /*!
mbed_official 146:f64d43ff0c18 9644 * @addtogroup PORT_Register_Masks PORT Register Masks
mbed_official 146:f64d43ff0c18 9645 * @{
mbed_official 146:f64d43ff0c18 9646 */
mbed_official 146:f64d43ff0c18 9647
mbed_official 146:f64d43ff0c18 9648 /* PCR Bit Fields */
mbed_official 146:f64d43ff0c18 9649 #define PORT_PCR_PS_MASK 0x1u
mbed_official 146:f64d43ff0c18 9650 #define PORT_PCR_PS_SHIFT 0
mbed_official 146:f64d43ff0c18 9651 #define PORT_PCR_PE_MASK 0x2u
mbed_official 146:f64d43ff0c18 9652 #define PORT_PCR_PE_SHIFT 1
mbed_official 146:f64d43ff0c18 9653 #define PORT_PCR_SRE_MASK 0x4u
mbed_official 146:f64d43ff0c18 9654 #define PORT_PCR_SRE_SHIFT 2
mbed_official 146:f64d43ff0c18 9655 #define PORT_PCR_PFE_MASK 0x10u
mbed_official 146:f64d43ff0c18 9656 #define PORT_PCR_PFE_SHIFT 4
mbed_official 146:f64d43ff0c18 9657 #define PORT_PCR_ODE_MASK 0x20u
mbed_official 146:f64d43ff0c18 9658 #define PORT_PCR_ODE_SHIFT 5
mbed_official 146:f64d43ff0c18 9659 #define PORT_PCR_DSE_MASK 0x40u
mbed_official 146:f64d43ff0c18 9660 #define PORT_PCR_DSE_SHIFT 6
mbed_official 146:f64d43ff0c18 9661 #define PORT_PCR_MUX_MASK 0x700u
mbed_official 146:f64d43ff0c18 9662 #define PORT_PCR_MUX_SHIFT 8
mbed_official 146:f64d43ff0c18 9663 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
mbed_official 146:f64d43ff0c18 9664 #define PORT_PCR_LK_MASK 0x8000u
mbed_official 146:f64d43ff0c18 9665 #define PORT_PCR_LK_SHIFT 15
mbed_official 146:f64d43ff0c18 9666 #define PORT_PCR_IRQC_MASK 0xF0000u
mbed_official 146:f64d43ff0c18 9667 #define PORT_PCR_IRQC_SHIFT 16
mbed_official 146:f64d43ff0c18 9668 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
mbed_official 146:f64d43ff0c18 9669 #define PORT_PCR_ISF_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 9670 #define PORT_PCR_ISF_SHIFT 24
mbed_official 146:f64d43ff0c18 9671 /* GPCLR Bit Fields */
mbed_official 146:f64d43ff0c18 9672 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 9673 #define PORT_GPCLR_GPWD_SHIFT 0
mbed_official 146:f64d43ff0c18 9674 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
mbed_official 146:f64d43ff0c18 9675 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
mbed_official 146:f64d43ff0c18 9676 #define PORT_GPCLR_GPWE_SHIFT 16
mbed_official 146:f64d43ff0c18 9677 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
mbed_official 146:f64d43ff0c18 9678 /* GPCHR Bit Fields */
mbed_official 146:f64d43ff0c18 9679 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 9680 #define PORT_GPCHR_GPWD_SHIFT 0
mbed_official 146:f64d43ff0c18 9681 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
mbed_official 146:f64d43ff0c18 9682 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
mbed_official 146:f64d43ff0c18 9683 #define PORT_GPCHR_GPWE_SHIFT 16
mbed_official 146:f64d43ff0c18 9684 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
mbed_official 146:f64d43ff0c18 9685 /* ISFR Bit Fields */
mbed_official 146:f64d43ff0c18 9686 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 9687 #define PORT_ISFR_ISF_SHIFT 0
mbed_official 146:f64d43ff0c18 9688 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
mbed_official 146:f64d43ff0c18 9689 /* DFER Bit Fields */
mbed_official 146:f64d43ff0c18 9690 #define PORT_DFER_DFE_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 9691 #define PORT_DFER_DFE_SHIFT 0
mbed_official 146:f64d43ff0c18 9692 #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
mbed_official 146:f64d43ff0c18 9693 /* DFCR Bit Fields */
mbed_official 146:f64d43ff0c18 9694 #define PORT_DFCR_CS_MASK 0x1u
mbed_official 146:f64d43ff0c18 9695 #define PORT_DFCR_CS_SHIFT 0
mbed_official 146:f64d43ff0c18 9696 /* DFWR Bit Fields */
mbed_official 146:f64d43ff0c18 9697 #define PORT_DFWR_FILT_MASK 0x1Fu
mbed_official 146:f64d43ff0c18 9698 #define PORT_DFWR_FILT_SHIFT 0
mbed_official 146:f64d43ff0c18 9699 #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
mbed_official 146:f64d43ff0c18 9700
mbed_official 146:f64d43ff0c18 9701 /*!
mbed_official 146:f64d43ff0c18 9702 * @}
mbed_official 146:f64d43ff0c18 9703 */ /* end of group PORT_Register_Masks */
mbed_official 146:f64d43ff0c18 9704
mbed_official 146:f64d43ff0c18 9705
mbed_official 146:f64d43ff0c18 9706 /* PORT - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 9707 /** Peripheral PORTA base address */
mbed_official 146:f64d43ff0c18 9708 #define PORTA_BASE (0x40049000u)
mbed_official 146:f64d43ff0c18 9709 /** Peripheral PORTA base pointer */
mbed_official 146:f64d43ff0c18 9710 #define PORTA ((PORT_Type *)PORTA_BASE)
mbed_official 146:f64d43ff0c18 9711 #define PORTA_BASE_PTR (PORTA)
mbed_official 146:f64d43ff0c18 9712 /** Peripheral PORTB base address */
mbed_official 146:f64d43ff0c18 9713 #define PORTB_BASE (0x4004A000u)
mbed_official 146:f64d43ff0c18 9714 /** Peripheral PORTB base pointer */
mbed_official 146:f64d43ff0c18 9715 #define PORTB ((PORT_Type *)PORTB_BASE)
mbed_official 146:f64d43ff0c18 9716 #define PORTB_BASE_PTR (PORTB)
mbed_official 146:f64d43ff0c18 9717 /** Peripheral PORTC base address */
mbed_official 146:f64d43ff0c18 9718 #define PORTC_BASE (0x4004B000u)
mbed_official 146:f64d43ff0c18 9719 /** Peripheral PORTC base pointer */
mbed_official 146:f64d43ff0c18 9720 #define PORTC ((PORT_Type *)PORTC_BASE)
mbed_official 146:f64d43ff0c18 9721 #define PORTC_BASE_PTR (PORTC)
mbed_official 146:f64d43ff0c18 9722 /** Peripheral PORTD base address */
mbed_official 146:f64d43ff0c18 9723 #define PORTD_BASE (0x4004C000u)
mbed_official 146:f64d43ff0c18 9724 /** Peripheral PORTD base pointer */
mbed_official 146:f64d43ff0c18 9725 #define PORTD ((PORT_Type *)PORTD_BASE)
mbed_official 146:f64d43ff0c18 9726 #define PORTD_BASE_PTR (PORTD)
mbed_official 146:f64d43ff0c18 9727 /** Peripheral PORTE base address */
mbed_official 146:f64d43ff0c18 9728 #define PORTE_BASE (0x4004D000u)
mbed_official 146:f64d43ff0c18 9729 /** Peripheral PORTE base pointer */
mbed_official 146:f64d43ff0c18 9730 #define PORTE ((PORT_Type *)PORTE_BASE)
mbed_official 146:f64d43ff0c18 9731 #define PORTE_BASE_PTR (PORTE)
mbed_official 146:f64d43ff0c18 9732 /** Array initializer of PORT peripheral base pointers */
mbed_official 146:f64d43ff0c18 9733 #define PORT_BASES { PORTA, PORTB, PORTC, PORTD, PORTE }
mbed_official 146:f64d43ff0c18 9734
mbed_official 146:f64d43ff0c18 9735 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 9736 -- PORT - Register accessor macros
mbed_official 146:f64d43ff0c18 9737 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 9738
mbed_official 146:f64d43ff0c18 9739 /*!
mbed_official 146:f64d43ff0c18 9740 * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
mbed_official 146:f64d43ff0c18 9741 * @{
mbed_official 146:f64d43ff0c18 9742 */
mbed_official 146:f64d43ff0c18 9743
mbed_official 146:f64d43ff0c18 9744
mbed_official 146:f64d43ff0c18 9745 /* PORT - Register instance definitions */
mbed_official 146:f64d43ff0c18 9746 /* PORTA */
mbed_official 146:f64d43ff0c18 9747 #define PORTA_PCR0 PORT_PCR_REG(PORTA,0)
mbed_official 146:f64d43ff0c18 9748 #define PORTA_PCR1 PORT_PCR_REG(PORTA,1)
mbed_official 146:f64d43ff0c18 9749 #define PORTA_PCR2 PORT_PCR_REG(PORTA,2)
mbed_official 146:f64d43ff0c18 9750 #define PORTA_PCR3 PORT_PCR_REG(PORTA,3)
mbed_official 146:f64d43ff0c18 9751 #define PORTA_PCR4 PORT_PCR_REG(PORTA,4)
mbed_official 146:f64d43ff0c18 9752 #define PORTA_PCR5 PORT_PCR_REG(PORTA,5)
mbed_official 146:f64d43ff0c18 9753 #define PORTA_PCR6 PORT_PCR_REG(PORTA,6)
mbed_official 146:f64d43ff0c18 9754 #define PORTA_PCR7 PORT_PCR_REG(PORTA,7)
mbed_official 146:f64d43ff0c18 9755 #define PORTA_PCR8 PORT_PCR_REG(PORTA,8)
mbed_official 146:f64d43ff0c18 9756 #define PORTA_PCR9 PORT_PCR_REG(PORTA,9)
mbed_official 146:f64d43ff0c18 9757 #define PORTA_PCR10 PORT_PCR_REG(PORTA,10)
mbed_official 146:f64d43ff0c18 9758 #define PORTA_PCR11 PORT_PCR_REG(PORTA,11)
mbed_official 146:f64d43ff0c18 9759 #define PORTA_PCR12 PORT_PCR_REG(PORTA,12)
mbed_official 146:f64d43ff0c18 9760 #define PORTA_PCR13 PORT_PCR_REG(PORTA,13)
mbed_official 146:f64d43ff0c18 9761 #define PORTA_PCR14 PORT_PCR_REG(PORTA,14)
mbed_official 146:f64d43ff0c18 9762 #define PORTA_PCR15 PORT_PCR_REG(PORTA,15)
mbed_official 146:f64d43ff0c18 9763 #define PORTA_PCR16 PORT_PCR_REG(PORTA,16)
mbed_official 146:f64d43ff0c18 9764 #define PORTA_PCR17 PORT_PCR_REG(PORTA,17)
mbed_official 146:f64d43ff0c18 9765 #define PORTA_PCR18 PORT_PCR_REG(PORTA,18)
mbed_official 146:f64d43ff0c18 9766 #define PORTA_PCR19 PORT_PCR_REG(PORTA,19)
mbed_official 146:f64d43ff0c18 9767 #define PORTA_PCR20 PORT_PCR_REG(PORTA,20)
mbed_official 146:f64d43ff0c18 9768 #define PORTA_PCR21 PORT_PCR_REG(PORTA,21)
mbed_official 146:f64d43ff0c18 9769 #define PORTA_PCR22 PORT_PCR_REG(PORTA,22)
mbed_official 146:f64d43ff0c18 9770 #define PORTA_PCR23 PORT_PCR_REG(PORTA,23)
mbed_official 146:f64d43ff0c18 9771 #define PORTA_PCR24 PORT_PCR_REG(PORTA,24)
mbed_official 146:f64d43ff0c18 9772 #define PORTA_PCR25 PORT_PCR_REG(PORTA,25)
mbed_official 146:f64d43ff0c18 9773 #define PORTA_PCR26 PORT_PCR_REG(PORTA,26)
mbed_official 146:f64d43ff0c18 9774 #define PORTA_PCR27 PORT_PCR_REG(PORTA,27)
mbed_official 146:f64d43ff0c18 9775 #define PORTA_PCR28 PORT_PCR_REG(PORTA,28)
mbed_official 146:f64d43ff0c18 9776 #define PORTA_PCR29 PORT_PCR_REG(PORTA,29)
mbed_official 146:f64d43ff0c18 9777 #define PORTA_PCR30 PORT_PCR_REG(PORTA,30)
mbed_official 146:f64d43ff0c18 9778 #define PORTA_PCR31 PORT_PCR_REG(PORTA,31)
mbed_official 146:f64d43ff0c18 9779 #define PORTA_GPCLR PORT_GPCLR_REG(PORTA)
mbed_official 146:f64d43ff0c18 9780 #define PORTA_GPCHR PORT_GPCHR_REG(PORTA)
mbed_official 146:f64d43ff0c18 9781 #define PORTA_ISFR PORT_ISFR_REG(PORTA)
mbed_official 146:f64d43ff0c18 9782 /* PORTB */
mbed_official 146:f64d43ff0c18 9783 #define PORTB_PCR0 PORT_PCR_REG(PORTB,0)
mbed_official 146:f64d43ff0c18 9784 #define PORTB_PCR1 PORT_PCR_REG(PORTB,1)
mbed_official 146:f64d43ff0c18 9785 #define PORTB_PCR2 PORT_PCR_REG(PORTB,2)
mbed_official 146:f64d43ff0c18 9786 #define PORTB_PCR3 PORT_PCR_REG(PORTB,3)
mbed_official 146:f64d43ff0c18 9787 #define PORTB_PCR4 PORT_PCR_REG(PORTB,4)
mbed_official 146:f64d43ff0c18 9788 #define PORTB_PCR5 PORT_PCR_REG(PORTB,5)
mbed_official 146:f64d43ff0c18 9789 #define PORTB_PCR6 PORT_PCR_REG(PORTB,6)
mbed_official 146:f64d43ff0c18 9790 #define PORTB_PCR7 PORT_PCR_REG(PORTB,7)
mbed_official 146:f64d43ff0c18 9791 #define PORTB_PCR8 PORT_PCR_REG(PORTB,8)
mbed_official 146:f64d43ff0c18 9792 #define PORTB_PCR9 PORT_PCR_REG(PORTB,9)
mbed_official 146:f64d43ff0c18 9793 #define PORTB_PCR10 PORT_PCR_REG(PORTB,10)
mbed_official 146:f64d43ff0c18 9794 #define PORTB_PCR11 PORT_PCR_REG(PORTB,11)
mbed_official 146:f64d43ff0c18 9795 #define PORTB_PCR12 PORT_PCR_REG(PORTB,12)
mbed_official 146:f64d43ff0c18 9796 #define PORTB_PCR13 PORT_PCR_REG(PORTB,13)
mbed_official 146:f64d43ff0c18 9797 #define PORTB_PCR14 PORT_PCR_REG(PORTB,14)
mbed_official 146:f64d43ff0c18 9798 #define PORTB_PCR15 PORT_PCR_REG(PORTB,15)
mbed_official 146:f64d43ff0c18 9799 #define PORTB_PCR16 PORT_PCR_REG(PORTB,16)
mbed_official 146:f64d43ff0c18 9800 #define PORTB_PCR17 PORT_PCR_REG(PORTB,17)
mbed_official 146:f64d43ff0c18 9801 #define PORTB_PCR18 PORT_PCR_REG(PORTB,18)
mbed_official 146:f64d43ff0c18 9802 #define PORTB_PCR19 PORT_PCR_REG(PORTB,19)
mbed_official 146:f64d43ff0c18 9803 #define PORTB_PCR20 PORT_PCR_REG(PORTB,20)
mbed_official 146:f64d43ff0c18 9804 #define PORTB_PCR21 PORT_PCR_REG(PORTB,21)
mbed_official 146:f64d43ff0c18 9805 #define PORTB_PCR22 PORT_PCR_REG(PORTB,22)
mbed_official 146:f64d43ff0c18 9806 #define PORTB_PCR23 PORT_PCR_REG(PORTB,23)
mbed_official 146:f64d43ff0c18 9807 #define PORTB_PCR24 PORT_PCR_REG(PORTB,24)
mbed_official 146:f64d43ff0c18 9808 #define PORTB_PCR25 PORT_PCR_REG(PORTB,25)
mbed_official 146:f64d43ff0c18 9809 #define PORTB_PCR26 PORT_PCR_REG(PORTB,26)
mbed_official 146:f64d43ff0c18 9810 #define PORTB_PCR27 PORT_PCR_REG(PORTB,27)
mbed_official 146:f64d43ff0c18 9811 #define PORTB_PCR28 PORT_PCR_REG(PORTB,28)
mbed_official 146:f64d43ff0c18 9812 #define PORTB_PCR29 PORT_PCR_REG(PORTB,29)
mbed_official 146:f64d43ff0c18 9813 #define PORTB_PCR30 PORT_PCR_REG(PORTB,30)
mbed_official 146:f64d43ff0c18 9814 #define PORTB_PCR31 PORT_PCR_REG(PORTB,31)
mbed_official 146:f64d43ff0c18 9815 #define PORTB_GPCLR PORT_GPCLR_REG(PORTB)
mbed_official 146:f64d43ff0c18 9816 #define PORTB_GPCHR PORT_GPCHR_REG(PORTB)
mbed_official 146:f64d43ff0c18 9817 #define PORTB_ISFR PORT_ISFR_REG(PORTB)
mbed_official 146:f64d43ff0c18 9818 /* PORTC */
mbed_official 146:f64d43ff0c18 9819 #define PORTC_PCR0 PORT_PCR_REG(PORTC,0)
mbed_official 146:f64d43ff0c18 9820 #define PORTC_PCR1 PORT_PCR_REG(PORTC,1)
mbed_official 146:f64d43ff0c18 9821 #define PORTC_PCR2 PORT_PCR_REG(PORTC,2)
mbed_official 146:f64d43ff0c18 9822 #define PORTC_PCR3 PORT_PCR_REG(PORTC,3)
mbed_official 146:f64d43ff0c18 9823 #define PORTC_PCR4 PORT_PCR_REG(PORTC,4)
mbed_official 146:f64d43ff0c18 9824 #define PORTC_PCR5 PORT_PCR_REG(PORTC,5)
mbed_official 146:f64d43ff0c18 9825 #define PORTC_PCR6 PORT_PCR_REG(PORTC,6)
mbed_official 146:f64d43ff0c18 9826 #define PORTC_PCR7 PORT_PCR_REG(PORTC,7)
mbed_official 146:f64d43ff0c18 9827 #define PORTC_PCR8 PORT_PCR_REG(PORTC,8)
mbed_official 146:f64d43ff0c18 9828 #define PORTC_PCR9 PORT_PCR_REG(PORTC,9)
mbed_official 146:f64d43ff0c18 9829 #define PORTC_PCR10 PORT_PCR_REG(PORTC,10)
mbed_official 146:f64d43ff0c18 9830 #define PORTC_PCR11 PORT_PCR_REG(PORTC,11)
mbed_official 146:f64d43ff0c18 9831 #define PORTC_PCR12 PORT_PCR_REG(PORTC,12)
mbed_official 146:f64d43ff0c18 9832 #define PORTC_PCR13 PORT_PCR_REG(PORTC,13)
mbed_official 146:f64d43ff0c18 9833 #define PORTC_PCR14 PORT_PCR_REG(PORTC,14)
mbed_official 146:f64d43ff0c18 9834 #define PORTC_PCR15 PORT_PCR_REG(PORTC,15)
mbed_official 146:f64d43ff0c18 9835 #define PORTC_PCR16 PORT_PCR_REG(PORTC,16)
mbed_official 146:f64d43ff0c18 9836 #define PORTC_PCR17 PORT_PCR_REG(PORTC,17)
mbed_official 146:f64d43ff0c18 9837 #define PORTC_PCR18 PORT_PCR_REG(PORTC,18)
mbed_official 146:f64d43ff0c18 9838 #define PORTC_PCR19 PORT_PCR_REG(PORTC,19)
mbed_official 146:f64d43ff0c18 9839 #define PORTC_PCR20 PORT_PCR_REG(PORTC,20)
mbed_official 146:f64d43ff0c18 9840 #define PORTC_PCR21 PORT_PCR_REG(PORTC,21)
mbed_official 146:f64d43ff0c18 9841 #define PORTC_PCR22 PORT_PCR_REG(PORTC,22)
mbed_official 146:f64d43ff0c18 9842 #define PORTC_PCR23 PORT_PCR_REG(PORTC,23)
mbed_official 146:f64d43ff0c18 9843 #define PORTC_PCR24 PORT_PCR_REG(PORTC,24)
mbed_official 146:f64d43ff0c18 9844 #define PORTC_PCR25 PORT_PCR_REG(PORTC,25)
mbed_official 146:f64d43ff0c18 9845 #define PORTC_PCR26 PORT_PCR_REG(PORTC,26)
mbed_official 146:f64d43ff0c18 9846 #define PORTC_PCR27 PORT_PCR_REG(PORTC,27)
mbed_official 146:f64d43ff0c18 9847 #define PORTC_PCR28 PORT_PCR_REG(PORTC,28)
mbed_official 146:f64d43ff0c18 9848 #define PORTC_PCR29 PORT_PCR_REG(PORTC,29)
mbed_official 146:f64d43ff0c18 9849 #define PORTC_PCR30 PORT_PCR_REG(PORTC,30)
mbed_official 146:f64d43ff0c18 9850 #define PORTC_PCR31 PORT_PCR_REG(PORTC,31)
mbed_official 146:f64d43ff0c18 9851 #define PORTC_GPCLR PORT_GPCLR_REG(PORTC)
mbed_official 146:f64d43ff0c18 9852 #define PORTC_GPCHR PORT_GPCHR_REG(PORTC)
mbed_official 146:f64d43ff0c18 9853 #define PORTC_ISFR PORT_ISFR_REG(PORTC)
mbed_official 146:f64d43ff0c18 9854 /* PORTD */
mbed_official 146:f64d43ff0c18 9855 #define PORTD_PCR0 PORT_PCR_REG(PORTD,0)
mbed_official 146:f64d43ff0c18 9856 #define PORTD_PCR1 PORT_PCR_REG(PORTD,1)
mbed_official 146:f64d43ff0c18 9857 #define PORTD_PCR2 PORT_PCR_REG(PORTD,2)
mbed_official 146:f64d43ff0c18 9858 #define PORTD_PCR3 PORT_PCR_REG(PORTD,3)
mbed_official 146:f64d43ff0c18 9859 #define PORTD_PCR4 PORT_PCR_REG(PORTD,4)
mbed_official 146:f64d43ff0c18 9860 #define PORTD_PCR5 PORT_PCR_REG(PORTD,5)
mbed_official 146:f64d43ff0c18 9861 #define PORTD_PCR6 PORT_PCR_REG(PORTD,6)
mbed_official 146:f64d43ff0c18 9862 #define PORTD_PCR7 PORT_PCR_REG(PORTD,7)
mbed_official 146:f64d43ff0c18 9863 #define PORTD_PCR8 PORT_PCR_REG(PORTD,8)
mbed_official 146:f64d43ff0c18 9864 #define PORTD_PCR9 PORT_PCR_REG(PORTD,9)
mbed_official 146:f64d43ff0c18 9865 #define PORTD_PCR10 PORT_PCR_REG(PORTD,10)
mbed_official 146:f64d43ff0c18 9866 #define PORTD_PCR11 PORT_PCR_REG(PORTD,11)
mbed_official 146:f64d43ff0c18 9867 #define PORTD_PCR12 PORT_PCR_REG(PORTD,12)
mbed_official 146:f64d43ff0c18 9868 #define PORTD_PCR13 PORT_PCR_REG(PORTD,13)
mbed_official 146:f64d43ff0c18 9869 #define PORTD_PCR14 PORT_PCR_REG(PORTD,14)
mbed_official 146:f64d43ff0c18 9870 #define PORTD_PCR15 PORT_PCR_REG(PORTD,15)
mbed_official 146:f64d43ff0c18 9871 #define PORTD_PCR16 PORT_PCR_REG(PORTD,16)
mbed_official 146:f64d43ff0c18 9872 #define PORTD_PCR17 PORT_PCR_REG(PORTD,17)
mbed_official 146:f64d43ff0c18 9873 #define PORTD_PCR18 PORT_PCR_REG(PORTD,18)
mbed_official 146:f64d43ff0c18 9874 #define PORTD_PCR19 PORT_PCR_REG(PORTD,19)
mbed_official 146:f64d43ff0c18 9875 #define PORTD_PCR20 PORT_PCR_REG(PORTD,20)
mbed_official 146:f64d43ff0c18 9876 #define PORTD_PCR21 PORT_PCR_REG(PORTD,21)
mbed_official 146:f64d43ff0c18 9877 #define PORTD_PCR22 PORT_PCR_REG(PORTD,22)
mbed_official 146:f64d43ff0c18 9878 #define PORTD_PCR23 PORT_PCR_REG(PORTD,23)
mbed_official 146:f64d43ff0c18 9879 #define PORTD_PCR24 PORT_PCR_REG(PORTD,24)
mbed_official 146:f64d43ff0c18 9880 #define PORTD_PCR25 PORT_PCR_REG(PORTD,25)
mbed_official 146:f64d43ff0c18 9881 #define PORTD_PCR26 PORT_PCR_REG(PORTD,26)
mbed_official 146:f64d43ff0c18 9882 #define PORTD_PCR27 PORT_PCR_REG(PORTD,27)
mbed_official 146:f64d43ff0c18 9883 #define PORTD_PCR28 PORT_PCR_REG(PORTD,28)
mbed_official 146:f64d43ff0c18 9884 #define PORTD_PCR29 PORT_PCR_REG(PORTD,29)
mbed_official 146:f64d43ff0c18 9885 #define PORTD_PCR30 PORT_PCR_REG(PORTD,30)
mbed_official 146:f64d43ff0c18 9886 #define PORTD_PCR31 PORT_PCR_REG(PORTD,31)
mbed_official 146:f64d43ff0c18 9887 #define PORTD_GPCLR PORT_GPCLR_REG(PORTD)
mbed_official 146:f64d43ff0c18 9888 #define PORTD_GPCHR PORT_GPCHR_REG(PORTD)
mbed_official 146:f64d43ff0c18 9889 #define PORTD_ISFR PORT_ISFR_REG(PORTD)
mbed_official 146:f64d43ff0c18 9890 #define PORTD_DFER PORT_DFER_REG(PORTD)
mbed_official 146:f64d43ff0c18 9891 #define PORTD_DFCR PORT_DFCR_REG(PORTD)
mbed_official 146:f64d43ff0c18 9892 #define PORTD_DFWR PORT_DFWR_REG(PORTD)
mbed_official 146:f64d43ff0c18 9893 /* PORTE */
mbed_official 146:f64d43ff0c18 9894 #define PORTE_PCR0 PORT_PCR_REG(PORTE,0)
mbed_official 146:f64d43ff0c18 9895 #define PORTE_PCR1 PORT_PCR_REG(PORTE,1)
mbed_official 146:f64d43ff0c18 9896 #define PORTE_PCR2 PORT_PCR_REG(PORTE,2)
mbed_official 146:f64d43ff0c18 9897 #define PORTE_PCR3 PORT_PCR_REG(PORTE,3)
mbed_official 146:f64d43ff0c18 9898 #define PORTE_PCR4 PORT_PCR_REG(PORTE,4)
mbed_official 146:f64d43ff0c18 9899 #define PORTE_PCR5 PORT_PCR_REG(PORTE,5)
mbed_official 146:f64d43ff0c18 9900 #define PORTE_PCR6 PORT_PCR_REG(PORTE,6)
mbed_official 146:f64d43ff0c18 9901 #define PORTE_PCR7 PORT_PCR_REG(PORTE,7)
mbed_official 146:f64d43ff0c18 9902 #define PORTE_PCR8 PORT_PCR_REG(PORTE,8)
mbed_official 146:f64d43ff0c18 9903 #define PORTE_PCR9 PORT_PCR_REG(PORTE,9)
mbed_official 146:f64d43ff0c18 9904 #define PORTE_PCR10 PORT_PCR_REG(PORTE,10)
mbed_official 146:f64d43ff0c18 9905 #define PORTE_PCR11 PORT_PCR_REG(PORTE,11)
mbed_official 146:f64d43ff0c18 9906 #define PORTE_PCR12 PORT_PCR_REG(PORTE,12)
mbed_official 146:f64d43ff0c18 9907 #define PORTE_PCR13 PORT_PCR_REG(PORTE,13)
mbed_official 146:f64d43ff0c18 9908 #define PORTE_PCR14 PORT_PCR_REG(PORTE,14)
mbed_official 146:f64d43ff0c18 9909 #define PORTE_PCR15 PORT_PCR_REG(PORTE,15)
mbed_official 146:f64d43ff0c18 9910 #define PORTE_PCR16 PORT_PCR_REG(PORTE,16)
mbed_official 146:f64d43ff0c18 9911 #define PORTE_PCR17 PORT_PCR_REG(PORTE,17)
mbed_official 146:f64d43ff0c18 9912 #define PORTE_PCR18 PORT_PCR_REG(PORTE,18)
mbed_official 146:f64d43ff0c18 9913 #define PORTE_PCR19 PORT_PCR_REG(PORTE,19)
mbed_official 146:f64d43ff0c18 9914 #define PORTE_PCR20 PORT_PCR_REG(PORTE,20)
mbed_official 146:f64d43ff0c18 9915 #define PORTE_PCR21 PORT_PCR_REG(PORTE,21)
mbed_official 146:f64d43ff0c18 9916 #define PORTE_PCR22 PORT_PCR_REG(PORTE,22)
mbed_official 146:f64d43ff0c18 9917 #define PORTE_PCR23 PORT_PCR_REG(PORTE,23)
mbed_official 146:f64d43ff0c18 9918 #define PORTE_PCR24 PORT_PCR_REG(PORTE,24)
mbed_official 146:f64d43ff0c18 9919 #define PORTE_PCR25 PORT_PCR_REG(PORTE,25)
mbed_official 146:f64d43ff0c18 9920 #define PORTE_PCR26 PORT_PCR_REG(PORTE,26)
mbed_official 146:f64d43ff0c18 9921 #define PORTE_PCR27 PORT_PCR_REG(PORTE,27)
mbed_official 146:f64d43ff0c18 9922 #define PORTE_PCR28 PORT_PCR_REG(PORTE,28)
mbed_official 146:f64d43ff0c18 9923 #define PORTE_PCR29 PORT_PCR_REG(PORTE,29)
mbed_official 146:f64d43ff0c18 9924 #define PORTE_PCR30 PORT_PCR_REG(PORTE,30)
mbed_official 146:f64d43ff0c18 9925 #define PORTE_PCR31 PORT_PCR_REG(PORTE,31)
mbed_official 146:f64d43ff0c18 9926 #define PORTE_GPCLR PORT_GPCLR_REG(PORTE)
mbed_official 146:f64d43ff0c18 9927 #define PORTE_GPCHR PORT_GPCHR_REG(PORTE)
mbed_official 146:f64d43ff0c18 9928 #define PORTE_ISFR PORT_ISFR_REG(PORTE)
mbed_official 146:f64d43ff0c18 9929
mbed_official 146:f64d43ff0c18 9930 /* PORT - Register array accessors */
mbed_official 146:f64d43ff0c18 9931 #define PORTA_PCR(index) PORT_PCR_REG(PORTA,index)
mbed_official 146:f64d43ff0c18 9932 #define PORTB_PCR(index) PORT_PCR_REG(PORTB,index)
mbed_official 146:f64d43ff0c18 9933 #define PORTC_PCR(index) PORT_PCR_REG(PORTC,index)
mbed_official 146:f64d43ff0c18 9934 #define PORTD_PCR(index) PORT_PCR_REG(PORTD,index)
mbed_official 146:f64d43ff0c18 9935 #define PORTE_PCR(index) PORT_PCR_REG(PORTE,index)
mbed_official 146:f64d43ff0c18 9936
mbed_official 146:f64d43ff0c18 9937 /*!
mbed_official 146:f64d43ff0c18 9938 * @}
mbed_official 146:f64d43ff0c18 9939 */ /* end of group PORT_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 9940
mbed_official 146:f64d43ff0c18 9941
mbed_official 146:f64d43ff0c18 9942 /*!
mbed_official 146:f64d43ff0c18 9943 * @}
mbed_official 146:f64d43ff0c18 9944 */ /* end of group PORT_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 9945
mbed_official 146:f64d43ff0c18 9946
mbed_official 146:f64d43ff0c18 9947 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 9948 -- RCM Peripheral Access Layer
mbed_official 146:f64d43ff0c18 9949 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 9950
mbed_official 146:f64d43ff0c18 9951 /*!
mbed_official 146:f64d43ff0c18 9952 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
mbed_official 146:f64d43ff0c18 9953 * @{
mbed_official 146:f64d43ff0c18 9954 */
mbed_official 146:f64d43ff0c18 9955
mbed_official 146:f64d43ff0c18 9956 /** RCM - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 9957 typedef struct {
mbed_official 146:f64d43ff0c18 9958 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
mbed_official 146:f64d43ff0c18 9959 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
mbed_official 146:f64d43ff0c18 9960 uint8_t RESERVED_0[2];
mbed_official 146:f64d43ff0c18 9961 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
mbed_official 146:f64d43ff0c18 9962 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
mbed_official 146:f64d43ff0c18 9963 uint8_t RESERVED_1[1];
mbed_official 146:f64d43ff0c18 9964 __I uint8_t MR; /**< Mode Register, offset: 0x7 */
mbed_official 146:f64d43ff0c18 9965 } RCM_Type, *RCM_MemMapPtr;
mbed_official 146:f64d43ff0c18 9966
mbed_official 146:f64d43ff0c18 9967 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 9968 -- RCM - Register accessor macros
mbed_official 146:f64d43ff0c18 9969 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 9970
mbed_official 146:f64d43ff0c18 9971 /*!
mbed_official 146:f64d43ff0c18 9972 * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
mbed_official 146:f64d43ff0c18 9973 * @{
mbed_official 146:f64d43ff0c18 9974 */
mbed_official 146:f64d43ff0c18 9975
mbed_official 146:f64d43ff0c18 9976
mbed_official 146:f64d43ff0c18 9977 /* RCM - Register accessors */
mbed_official 146:f64d43ff0c18 9978 #define RCM_SRS0_REG(base) ((base)->SRS0)
mbed_official 146:f64d43ff0c18 9979 #define RCM_SRS1_REG(base) ((base)->SRS1)
mbed_official 146:f64d43ff0c18 9980 #define RCM_RPFC_REG(base) ((base)->RPFC)
mbed_official 146:f64d43ff0c18 9981 #define RCM_RPFW_REG(base) ((base)->RPFW)
mbed_official 146:f64d43ff0c18 9982 #define RCM_MR_REG(base) ((base)->MR)
mbed_official 146:f64d43ff0c18 9983
mbed_official 146:f64d43ff0c18 9984 /*!
mbed_official 146:f64d43ff0c18 9985 * @}
mbed_official 146:f64d43ff0c18 9986 */ /* end of group RCM_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 9987
mbed_official 146:f64d43ff0c18 9988
mbed_official 146:f64d43ff0c18 9989 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 9990 -- RCM Register Masks
mbed_official 146:f64d43ff0c18 9991 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 9992
mbed_official 146:f64d43ff0c18 9993 /*!
mbed_official 146:f64d43ff0c18 9994 * @addtogroup RCM_Register_Masks RCM Register Masks
mbed_official 146:f64d43ff0c18 9995 * @{
mbed_official 146:f64d43ff0c18 9996 */
mbed_official 146:f64d43ff0c18 9997
mbed_official 146:f64d43ff0c18 9998 /* SRS0 Bit Fields */
mbed_official 146:f64d43ff0c18 9999 #define RCM_SRS0_WAKEUP_MASK 0x1u
mbed_official 146:f64d43ff0c18 10000 #define RCM_SRS0_WAKEUP_SHIFT 0
mbed_official 146:f64d43ff0c18 10001 #define RCM_SRS0_LVD_MASK 0x2u
mbed_official 146:f64d43ff0c18 10002 #define RCM_SRS0_LVD_SHIFT 1
mbed_official 146:f64d43ff0c18 10003 #define RCM_SRS0_LOC_MASK 0x4u
mbed_official 146:f64d43ff0c18 10004 #define RCM_SRS0_LOC_SHIFT 2
mbed_official 146:f64d43ff0c18 10005 #define RCM_SRS0_LOL_MASK 0x8u
mbed_official 146:f64d43ff0c18 10006 #define RCM_SRS0_LOL_SHIFT 3
mbed_official 146:f64d43ff0c18 10007 #define RCM_SRS0_WDOG_MASK 0x20u
mbed_official 146:f64d43ff0c18 10008 #define RCM_SRS0_WDOG_SHIFT 5
mbed_official 146:f64d43ff0c18 10009 #define RCM_SRS0_PIN_MASK 0x40u
mbed_official 146:f64d43ff0c18 10010 #define RCM_SRS0_PIN_SHIFT 6
mbed_official 146:f64d43ff0c18 10011 #define RCM_SRS0_POR_MASK 0x80u
mbed_official 146:f64d43ff0c18 10012 #define RCM_SRS0_POR_SHIFT 7
mbed_official 146:f64d43ff0c18 10013 /* SRS1 Bit Fields */
mbed_official 146:f64d43ff0c18 10014 #define RCM_SRS1_JTAG_MASK 0x1u
mbed_official 146:f64d43ff0c18 10015 #define RCM_SRS1_JTAG_SHIFT 0
mbed_official 146:f64d43ff0c18 10016 #define RCM_SRS1_LOCKUP_MASK 0x2u
mbed_official 146:f64d43ff0c18 10017 #define RCM_SRS1_LOCKUP_SHIFT 1
mbed_official 146:f64d43ff0c18 10018 #define RCM_SRS1_SW_MASK 0x4u
mbed_official 146:f64d43ff0c18 10019 #define RCM_SRS1_SW_SHIFT 2
mbed_official 146:f64d43ff0c18 10020 #define RCM_SRS1_MDM_AP_MASK 0x8u
mbed_official 146:f64d43ff0c18 10021 #define RCM_SRS1_MDM_AP_SHIFT 3
mbed_official 146:f64d43ff0c18 10022 #define RCM_SRS1_EZPT_MASK 0x10u
mbed_official 146:f64d43ff0c18 10023 #define RCM_SRS1_EZPT_SHIFT 4
mbed_official 146:f64d43ff0c18 10024 #define RCM_SRS1_SACKERR_MASK 0x20u
mbed_official 146:f64d43ff0c18 10025 #define RCM_SRS1_SACKERR_SHIFT 5
mbed_official 146:f64d43ff0c18 10026 /* RPFC Bit Fields */
mbed_official 146:f64d43ff0c18 10027 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u
mbed_official 146:f64d43ff0c18 10028 #define RCM_RPFC_RSTFLTSRW_SHIFT 0
mbed_official 146:f64d43ff0c18 10029 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
mbed_official 146:f64d43ff0c18 10030 #define RCM_RPFC_RSTFLTSS_MASK 0x4u
mbed_official 146:f64d43ff0c18 10031 #define RCM_RPFC_RSTFLTSS_SHIFT 2
mbed_official 146:f64d43ff0c18 10032 /* RPFW Bit Fields */
mbed_official 146:f64d43ff0c18 10033 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
mbed_official 146:f64d43ff0c18 10034 #define RCM_RPFW_RSTFLTSEL_SHIFT 0
mbed_official 146:f64d43ff0c18 10035 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
mbed_official 146:f64d43ff0c18 10036 /* MR Bit Fields */
mbed_official 146:f64d43ff0c18 10037 #define RCM_MR_EZP_MS_MASK 0x2u
mbed_official 146:f64d43ff0c18 10038 #define RCM_MR_EZP_MS_SHIFT 1
mbed_official 146:f64d43ff0c18 10039
mbed_official 146:f64d43ff0c18 10040 /*!
mbed_official 146:f64d43ff0c18 10041 * @}
mbed_official 146:f64d43ff0c18 10042 */ /* end of group RCM_Register_Masks */
mbed_official 146:f64d43ff0c18 10043
mbed_official 146:f64d43ff0c18 10044
mbed_official 146:f64d43ff0c18 10045 /* RCM - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 10046 /** Peripheral RCM base address */
mbed_official 146:f64d43ff0c18 10047 #define RCM_BASE (0x4007F000u)
mbed_official 146:f64d43ff0c18 10048 /** Peripheral RCM base pointer */
mbed_official 146:f64d43ff0c18 10049 #define RCM ((RCM_Type *)RCM_BASE)
mbed_official 146:f64d43ff0c18 10050 #define RCM_BASE_PTR (RCM)
mbed_official 146:f64d43ff0c18 10051 /** Array initializer of RCM peripheral base pointers */
mbed_official 146:f64d43ff0c18 10052 #define RCM_BASES { RCM }
mbed_official 146:f64d43ff0c18 10053
mbed_official 146:f64d43ff0c18 10054 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 10055 -- RCM - Register accessor macros
mbed_official 146:f64d43ff0c18 10056 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 10057
mbed_official 146:f64d43ff0c18 10058 /*!
mbed_official 146:f64d43ff0c18 10059 * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
mbed_official 146:f64d43ff0c18 10060 * @{
mbed_official 146:f64d43ff0c18 10061 */
mbed_official 146:f64d43ff0c18 10062
mbed_official 146:f64d43ff0c18 10063
mbed_official 146:f64d43ff0c18 10064 /* RCM - Register instance definitions */
mbed_official 146:f64d43ff0c18 10065 /* RCM */
mbed_official 146:f64d43ff0c18 10066 #define RCM_SRS0 RCM_SRS0_REG(RCM)
mbed_official 146:f64d43ff0c18 10067 #define RCM_SRS1 RCM_SRS1_REG(RCM)
mbed_official 146:f64d43ff0c18 10068 #define RCM_RPFC RCM_RPFC_REG(RCM)
mbed_official 146:f64d43ff0c18 10069 #define RCM_RPFW RCM_RPFW_REG(RCM)
mbed_official 146:f64d43ff0c18 10070 #define RCM_MR RCM_MR_REG(RCM)
mbed_official 146:f64d43ff0c18 10071
mbed_official 146:f64d43ff0c18 10072 /*!
mbed_official 146:f64d43ff0c18 10073 * @}
mbed_official 146:f64d43ff0c18 10074 */ /* end of group RCM_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 10075
mbed_official 146:f64d43ff0c18 10076
mbed_official 146:f64d43ff0c18 10077 /*!
mbed_official 146:f64d43ff0c18 10078 * @}
mbed_official 146:f64d43ff0c18 10079 */ /* end of group RCM_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 10080
mbed_official 146:f64d43ff0c18 10081
mbed_official 146:f64d43ff0c18 10082 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 10083 -- RFSYS Peripheral Access Layer
mbed_official 146:f64d43ff0c18 10084 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 10085
mbed_official 146:f64d43ff0c18 10086 /*!
mbed_official 146:f64d43ff0c18 10087 * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
mbed_official 146:f64d43ff0c18 10088 * @{
mbed_official 146:f64d43ff0c18 10089 */
mbed_official 146:f64d43ff0c18 10090
mbed_official 146:f64d43ff0c18 10091 /** RFSYS - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 10092 typedef struct {
mbed_official 146:f64d43ff0c18 10093 __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
mbed_official 146:f64d43ff0c18 10094 } RFSYS_Type, *RFSYS_MemMapPtr;
mbed_official 146:f64d43ff0c18 10095
mbed_official 146:f64d43ff0c18 10096 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 10097 -- RFSYS - Register accessor macros
mbed_official 146:f64d43ff0c18 10098 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 10099
mbed_official 146:f64d43ff0c18 10100 /*!
mbed_official 146:f64d43ff0c18 10101 * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
mbed_official 146:f64d43ff0c18 10102 * @{
mbed_official 146:f64d43ff0c18 10103 */
mbed_official 146:f64d43ff0c18 10104
mbed_official 146:f64d43ff0c18 10105
mbed_official 146:f64d43ff0c18 10106 /* RFSYS - Register accessors */
mbed_official 146:f64d43ff0c18 10107 #define RFSYS_REG_REG(base,index) ((base)->REG[index])
mbed_official 146:f64d43ff0c18 10108
mbed_official 146:f64d43ff0c18 10109 /*!
mbed_official 146:f64d43ff0c18 10110 * @}
mbed_official 146:f64d43ff0c18 10111 */ /* end of group RFSYS_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 10112
mbed_official 146:f64d43ff0c18 10113
mbed_official 146:f64d43ff0c18 10114 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 10115 -- RFSYS Register Masks
mbed_official 146:f64d43ff0c18 10116 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 10117
mbed_official 146:f64d43ff0c18 10118 /*!
mbed_official 146:f64d43ff0c18 10119 * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
mbed_official 146:f64d43ff0c18 10120 * @{
mbed_official 146:f64d43ff0c18 10121 */
mbed_official 146:f64d43ff0c18 10122
mbed_official 146:f64d43ff0c18 10123 /* REG Bit Fields */
mbed_official 146:f64d43ff0c18 10124 #define RFSYS_REG_LL_MASK 0xFFu
mbed_official 146:f64d43ff0c18 10125 #define RFSYS_REG_LL_SHIFT 0
mbed_official 146:f64d43ff0c18 10126 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
mbed_official 146:f64d43ff0c18 10127 #define RFSYS_REG_LH_MASK 0xFF00u
mbed_official 146:f64d43ff0c18 10128 #define RFSYS_REG_LH_SHIFT 8
mbed_official 146:f64d43ff0c18 10129 #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
mbed_official 146:f64d43ff0c18 10130 #define RFSYS_REG_HL_MASK 0xFF0000u
mbed_official 146:f64d43ff0c18 10131 #define RFSYS_REG_HL_SHIFT 16
mbed_official 146:f64d43ff0c18 10132 #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
mbed_official 146:f64d43ff0c18 10133 #define RFSYS_REG_HH_MASK 0xFF000000u
mbed_official 146:f64d43ff0c18 10134 #define RFSYS_REG_HH_SHIFT 24
mbed_official 146:f64d43ff0c18 10135 #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
mbed_official 146:f64d43ff0c18 10136
mbed_official 146:f64d43ff0c18 10137 /*!
mbed_official 146:f64d43ff0c18 10138 * @}
mbed_official 146:f64d43ff0c18 10139 */ /* end of group RFSYS_Register_Masks */
mbed_official 146:f64d43ff0c18 10140
mbed_official 146:f64d43ff0c18 10141
mbed_official 146:f64d43ff0c18 10142 /* RFSYS - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 10143 /** Peripheral RFSYS base address */
mbed_official 146:f64d43ff0c18 10144 #define RFSYS_BASE (0x40041000u)
mbed_official 146:f64d43ff0c18 10145 /** Peripheral RFSYS base pointer */
mbed_official 146:f64d43ff0c18 10146 #define RFSYS ((RFSYS_Type *)RFSYS_BASE)
mbed_official 146:f64d43ff0c18 10147 #define RFSYS_BASE_PTR (RFSYS)
mbed_official 146:f64d43ff0c18 10148 /** Array initializer of RFSYS peripheral base pointers */
mbed_official 146:f64d43ff0c18 10149 #define RFSYS_BASES { RFSYS }
mbed_official 146:f64d43ff0c18 10150
mbed_official 146:f64d43ff0c18 10151 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 10152 -- RFSYS - Register accessor macros
mbed_official 146:f64d43ff0c18 10153 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 10154
mbed_official 146:f64d43ff0c18 10155 /*!
mbed_official 146:f64d43ff0c18 10156 * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
mbed_official 146:f64d43ff0c18 10157 * @{
mbed_official 146:f64d43ff0c18 10158 */
mbed_official 146:f64d43ff0c18 10159
mbed_official 146:f64d43ff0c18 10160
mbed_official 146:f64d43ff0c18 10161 /* RFSYS - Register instance definitions */
mbed_official 146:f64d43ff0c18 10162 /* RFSYS */
mbed_official 146:f64d43ff0c18 10163 #define RFSYS_REG0 RFSYS_REG_REG(RFSYS,0)
mbed_official 146:f64d43ff0c18 10164 #define RFSYS_REG1 RFSYS_REG_REG(RFSYS,1)
mbed_official 146:f64d43ff0c18 10165 #define RFSYS_REG2 RFSYS_REG_REG(RFSYS,2)
mbed_official 146:f64d43ff0c18 10166 #define RFSYS_REG3 RFSYS_REG_REG(RFSYS,3)
mbed_official 146:f64d43ff0c18 10167 #define RFSYS_REG4 RFSYS_REG_REG(RFSYS,4)
mbed_official 146:f64d43ff0c18 10168 #define RFSYS_REG5 RFSYS_REG_REG(RFSYS,5)
mbed_official 146:f64d43ff0c18 10169 #define RFSYS_REG6 RFSYS_REG_REG(RFSYS,6)
mbed_official 146:f64d43ff0c18 10170 #define RFSYS_REG7 RFSYS_REG_REG(RFSYS,7)
mbed_official 146:f64d43ff0c18 10171
mbed_official 146:f64d43ff0c18 10172 /* RFSYS - Register array accessors */
mbed_official 146:f64d43ff0c18 10173 #define RFSYS_REG(index) RFSYS_REG_REG(RFSYS,index)
mbed_official 146:f64d43ff0c18 10174
mbed_official 146:f64d43ff0c18 10175 /*!
mbed_official 146:f64d43ff0c18 10176 * @}
mbed_official 146:f64d43ff0c18 10177 */ /* end of group RFSYS_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 10178
mbed_official 146:f64d43ff0c18 10179
mbed_official 146:f64d43ff0c18 10180 /*!
mbed_official 146:f64d43ff0c18 10181 * @}
mbed_official 146:f64d43ff0c18 10182 */ /* end of group RFSYS_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 10183
mbed_official 146:f64d43ff0c18 10184
mbed_official 146:f64d43ff0c18 10185 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 10186 -- RFVBAT Peripheral Access Layer
mbed_official 146:f64d43ff0c18 10187 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 10188
mbed_official 146:f64d43ff0c18 10189 /*!
mbed_official 146:f64d43ff0c18 10190 * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
mbed_official 146:f64d43ff0c18 10191 * @{
mbed_official 146:f64d43ff0c18 10192 */
mbed_official 146:f64d43ff0c18 10193
mbed_official 146:f64d43ff0c18 10194 /** RFVBAT - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 10195 typedef struct {
mbed_official 146:f64d43ff0c18 10196 __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
mbed_official 146:f64d43ff0c18 10197 } RFVBAT_Type, *RFVBAT_MemMapPtr;
mbed_official 146:f64d43ff0c18 10198
mbed_official 146:f64d43ff0c18 10199 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 10200 -- RFVBAT - Register accessor macros
mbed_official 146:f64d43ff0c18 10201 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 10202
mbed_official 146:f64d43ff0c18 10203 /*!
mbed_official 146:f64d43ff0c18 10204 * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
mbed_official 146:f64d43ff0c18 10205 * @{
mbed_official 146:f64d43ff0c18 10206 */
mbed_official 146:f64d43ff0c18 10207
mbed_official 146:f64d43ff0c18 10208
mbed_official 146:f64d43ff0c18 10209 /* RFVBAT - Register accessors */
mbed_official 146:f64d43ff0c18 10210 #define RFVBAT_REG_REG(base,index) ((base)->REG[index])
mbed_official 146:f64d43ff0c18 10211
mbed_official 146:f64d43ff0c18 10212 /*!
mbed_official 146:f64d43ff0c18 10213 * @}
mbed_official 146:f64d43ff0c18 10214 */ /* end of group RFVBAT_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 10215
mbed_official 146:f64d43ff0c18 10216
mbed_official 146:f64d43ff0c18 10217 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 10218 -- RFVBAT Register Masks
mbed_official 146:f64d43ff0c18 10219 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 10220
mbed_official 146:f64d43ff0c18 10221 /*!
mbed_official 146:f64d43ff0c18 10222 * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
mbed_official 146:f64d43ff0c18 10223 * @{
mbed_official 146:f64d43ff0c18 10224 */
mbed_official 146:f64d43ff0c18 10225
mbed_official 146:f64d43ff0c18 10226 /* REG Bit Fields */
mbed_official 146:f64d43ff0c18 10227 #define RFVBAT_REG_LL_MASK 0xFFu
mbed_official 146:f64d43ff0c18 10228 #define RFVBAT_REG_LL_SHIFT 0
mbed_official 146:f64d43ff0c18 10229 #define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
mbed_official 146:f64d43ff0c18 10230 #define RFVBAT_REG_LH_MASK 0xFF00u
mbed_official 146:f64d43ff0c18 10231 #define RFVBAT_REG_LH_SHIFT 8
mbed_official 146:f64d43ff0c18 10232 #define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
mbed_official 146:f64d43ff0c18 10233 #define RFVBAT_REG_HL_MASK 0xFF0000u
mbed_official 146:f64d43ff0c18 10234 #define RFVBAT_REG_HL_SHIFT 16
mbed_official 146:f64d43ff0c18 10235 #define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
mbed_official 146:f64d43ff0c18 10236 #define RFVBAT_REG_HH_MASK 0xFF000000u
mbed_official 146:f64d43ff0c18 10237 #define RFVBAT_REG_HH_SHIFT 24
mbed_official 146:f64d43ff0c18 10238 #define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
mbed_official 146:f64d43ff0c18 10239
mbed_official 146:f64d43ff0c18 10240 /*!
mbed_official 146:f64d43ff0c18 10241 * @}
mbed_official 146:f64d43ff0c18 10242 */ /* end of group RFVBAT_Register_Masks */
mbed_official 146:f64d43ff0c18 10243
mbed_official 146:f64d43ff0c18 10244
mbed_official 146:f64d43ff0c18 10245 /* RFVBAT - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 10246 /** Peripheral RFVBAT base address */
mbed_official 146:f64d43ff0c18 10247 #define RFVBAT_BASE (0x4003E000u)
mbed_official 146:f64d43ff0c18 10248 /** Peripheral RFVBAT base pointer */
mbed_official 146:f64d43ff0c18 10249 #define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
mbed_official 146:f64d43ff0c18 10250 #define RFVBAT_BASE_PTR (RFVBAT)
mbed_official 146:f64d43ff0c18 10251 /** Array initializer of RFVBAT peripheral base pointers */
mbed_official 146:f64d43ff0c18 10252 #define RFVBAT_BASES { RFVBAT }
mbed_official 146:f64d43ff0c18 10253
mbed_official 146:f64d43ff0c18 10254 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 10255 -- RFVBAT - Register accessor macros
mbed_official 146:f64d43ff0c18 10256 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 10257
mbed_official 146:f64d43ff0c18 10258 /*!
mbed_official 146:f64d43ff0c18 10259 * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
mbed_official 146:f64d43ff0c18 10260 * @{
mbed_official 146:f64d43ff0c18 10261 */
mbed_official 146:f64d43ff0c18 10262
mbed_official 146:f64d43ff0c18 10263
mbed_official 146:f64d43ff0c18 10264 /* RFVBAT - Register instance definitions */
mbed_official 146:f64d43ff0c18 10265 /* RFVBAT */
mbed_official 146:f64d43ff0c18 10266 #define RFVBAT_REG0 RFVBAT_REG_REG(RFVBAT,0)
mbed_official 146:f64d43ff0c18 10267 #define RFVBAT_REG1 RFVBAT_REG_REG(RFVBAT,1)
mbed_official 146:f64d43ff0c18 10268 #define RFVBAT_REG2 RFVBAT_REG_REG(RFVBAT,2)
mbed_official 146:f64d43ff0c18 10269 #define RFVBAT_REG3 RFVBAT_REG_REG(RFVBAT,3)
mbed_official 146:f64d43ff0c18 10270 #define RFVBAT_REG4 RFVBAT_REG_REG(RFVBAT,4)
mbed_official 146:f64d43ff0c18 10271 #define RFVBAT_REG5 RFVBAT_REG_REG(RFVBAT,5)
mbed_official 146:f64d43ff0c18 10272 #define RFVBAT_REG6 RFVBAT_REG_REG(RFVBAT,6)
mbed_official 146:f64d43ff0c18 10273 #define RFVBAT_REG7 RFVBAT_REG_REG(RFVBAT,7)
mbed_official 146:f64d43ff0c18 10274
mbed_official 146:f64d43ff0c18 10275 /* RFVBAT - Register array accessors */
mbed_official 146:f64d43ff0c18 10276 #define RFVBAT_REG(index) RFVBAT_REG_REG(RFVBAT,index)
mbed_official 146:f64d43ff0c18 10277
mbed_official 146:f64d43ff0c18 10278 /*!
mbed_official 146:f64d43ff0c18 10279 * @}
mbed_official 146:f64d43ff0c18 10280 */ /* end of group RFVBAT_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 10281
mbed_official 146:f64d43ff0c18 10282
mbed_official 146:f64d43ff0c18 10283 /*!
mbed_official 146:f64d43ff0c18 10284 * @}
mbed_official 146:f64d43ff0c18 10285 */ /* end of group RFVBAT_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 10286
mbed_official 146:f64d43ff0c18 10287
mbed_official 146:f64d43ff0c18 10288 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 10289 -- RNG Peripheral Access Layer
mbed_official 146:f64d43ff0c18 10290 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 10291
mbed_official 146:f64d43ff0c18 10292 /*!
mbed_official 146:f64d43ff0c18 10293 * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
mbed_official 146:f64d43ff0c18 10294 * @{
mbed_official 146:f64d43ff0c18 10295 */
mbed_official 146:f64d43ff0c18 10296
mbed_official 146:f64d43ff0c18 10297 /** RNG - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 10298 typedef struct {
mbed_official 146:f64d43ff0c18 10299 __IO uint32_t CR; /**< RNGA Control Register, offset: 0x0 */
mbed_official 146:f64d43ff0c18 10300 __I uint32_t SR; /**< RNGA Status Register, offset: 0x4 */
mbed_official 146:f64d43ff0c18 10301 __O uint32_t ER; /**< RNGA Entropy Register, offset: 0x8 */
mbed_official 146:f64d43ff0c18 10302 __I uint32_t OR; /**< RNGA Output Register, offset: 0xC */
mbed_official 146:f64d43ff0c18 10303 } RNG_Type, *RNG_MemMapPtr;
mbed_official 146:f64d43ff0c18 10304
mbed_official 146:f64d43ff0c18 10305 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 10306 -- RNG - Register accessor macros
mbed_official 146:f64d43ff0c18 10307 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 10308
mbed_official 146:f64d43ff0c18 10309 /*!
mbed_official 146:f64d43ff0c18 10310 * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
mbed_official 146:f64d43ff0c18 10311 * @{
mbed_official 146:f64d43ff0c18 10312 */
mbed_official 146:f64d43ff0c18 10313
mbed_official 146:f64d43ff0c18 10314
mbed_official 146:f64d43ff0c18 10315 /* RNG - Register accessors */
mbed_official 146:f64d43ff0c18 10316 #define RNG_CR_REG(base) ((base)->CR)
mbed_official 146:f64d43ff0c18 10317 #define RNG_SR_REG(base) ((base)->SR)
mbed_official 146:f64d43ff0c18 10318 #define RNG_ER_REG(base) ((base)->ER)
mbed_official 146:f64d43ff0c18 10319 #define RNG_OR_REG(base) ((base)->OR)
mbed_official 146:f64d43ff0c18 10320
mbed_official 146:f64d43ff0c18 10321 /*!
mbed_official 146:f64d43ff0c18 10322 * @}
mbed_official 146:f64d43ff0c18 10323 */ /* end of group RNG_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 10324
mbed_official 146:f64d43ff0c18 10325
mbed_official 146:f64d43ff0c18 10326 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 10327 -- RNG Register Masks
mbed_official 146:f64d43ff0c18 10328 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 10329
mbed_official 146:f64d43ff0c18 10330 /*!
mbed_official 146:f64d43ff0c18 10331 * @addtogroup RNG_Register_Masks RNG Register Masks
mbed_official 146:f64d43ff0c18 10332 * @{
mbed_official 146:f64d43ff0c18 10333 */
mbed_official 146:f64d43ff0c18 10334
mbed_official 146:f64d43ff0c18 10335 /* CR Bit Fields */
mbed_official 146:f64d43ff0c18 10336 #define RNG_CR_GO_MASK 0x1u
mbed_official 146:f64d43ff0c18 10337 #define RNG_CR_GO_SHIFT 0
mbed_official 146:f64d43ff0c18 10338 #define RNG_CR_HA_MASK 0x2u
mbed_official 146:f64d43ff0c18 10339 #define RNG_CR_HA_SHIFT 1
mbed_official 146:f64d43ff0c18 10340 #define RNG_CR_INTM_MASK 0x4u
mbed_official 146:f64d43ff0c18 10341 #define RNG_CR_INTM_SHIFT 2
mbed_official 146:f64d43ff0c18 10342 #define RNG_CR_CLRI_MASK 0x8u
mbed_official 146:f64d43ff0c18 10343 #define RNG_CR_CLRI_SHIFT 3
mbed_official 146:f64d43ff0c18 10344 #define RNG_CR_SLP_MASK 0x10u
mbed_official 146:f64d43ff0c18 10345 #define RNG_CR_SLP_SHIFT 4
mbed_official 146:f64d43ff0c18 10346 /* SR Bit Fields */
mbed_official 146:f64d43ff0c18 10347 #define RNG_SR_SECV_MASK 0x1u
mbed_official 146:f64d43ff0c18 10348 #define RNG_SR_SECV_SHIFT 0
mbed_official 146:f64d43ff0c18 10349 #define RNG_SR_LRS_MASK 0x2u
mbed_official 146:f64d43ff0c18 10350 #define RNG_SR_LRS_SHIFT 1
mbed_official 146:f64d43ff0c18 10351 #define RNG_SR_ORU_MASK 0x4u
mbed_official 146:f64d43ff0c18 10352 #define RNG_SR_ORU_SHIFT 2
mbed_official 146:f64d43ff0c18 10353 #define RNG_SR_ERRI_MASK 0x8u
mbed_official 146:f64d43ff0c18 10354 #define RNG_SR_ERRI_SHIFT 3
mbed_official 146:f64d43ff0c18 10355 #define RNG_SR_SLP_MASK 0x10u
mbed_official 146:f64d43ff0c18 10356 #define RNG_SR_SLP_SHIFT 4
mbed_official 146:f64d43ff0c18 10357 #define RNG_SR_OREG_LVL_MASK 0xFF00u
mbed_official 146:f64d43ff0c18 10358 #define RNG_SR_OREG_LVL_SHIFT 8
mbed_official 146:f64d43ff0c18 10359 #define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_LVL_SHIFT))&RNG_SR_OREG_LVL_MASK)
mbed_official 146:f64d43ff0c18 10360 #define RNG_SR_OREG_SIZE_MASK 0xFF0000u
mbed_official 146:f64d43ff0c18 10361 #define RNG_SR_OREG_SIZE_SHIFT 16
mbed_official 146:f64d43ff0c18 10362 #define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_SIZE_SHIFT))&RNG_SR_OREG_SIZE_MASK)
mbed_official 146:f64d43ff0c18 10363 /* ER Bit Fields */
mbed_official 146:f64d43ff0c18 10364 #define RNG_ER_EXT_ENT_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 10365 #define RNG_ER_EXT_ENT_SHIFT 0
mbed_official 146:f64d43ff0c18 10366 #define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x))<<RNG_ER_EXT_ENT_SHIFT))&RNG_ER_EXT_ENT_MASK)
mbed_official 146:f64d43ff0c18 10367 /* OR Bit Fields */
mbed_official 146:f64d43ff0c18 10368 #define RNG_OR_RANDOUT_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 10369 #define RNG_OR_RANDOUT_SHIFT 0
mbed_official 146:f64d43ff0c18 10370 #define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x))<<RNG_OR_RANDOUT_SHIFT))&RNG_OR_RANDOUT_MASK)
mbed_official 146:f64d43ff0c18 10371
mbed_official 146:f64d43ff0c18 10372 /*!
mbed_official 146:f64d43ff0c18 10373 * @}
mbed_official 146:f64d43ff0c18 10374 */ /* end of group RNG_Register_Masks */
mbed_official 146:f64d43ff0c18 10375
mbed_official 146:f64d43ff0c18 10376
mbed_official 146:f64d43ff0c18 10377 /* RNG - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 10378 /** Peripheral RNG base address */
mbed_official 146:f64d43ff0c18 10379 #define RNG_BASE (0x40029000u)
mbed_official 146:f64d43ff0c18 10380 /** Peripheral RNG base pointer */
mbed_official 146:f64d43ff0c18 10381 #define RNG ((RNG_Type *)RNG_BASE)
mbed_official 146:f64d43ff0c18 10382 #define RNG_BASE_PTR (RNG)
mbed_official 146:f64d43ff0c18 10383 /** Array initializer of RNG peripheral base pointers */
mbed_official 146:f64d43ff0c18 10384 #define RNG_BASES { RNG }
mbed_official 146:f64d43ff0c18 10385
mbed_official 146:f64d43ff0c18 10386 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 10387 -- RNG - Register accessor macros
mbed_official 146:f64d43ff0c18 10388 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 10389
mbed_official 146:f64d43ff0c18 10390 /*!
mbed_official 146:f64d43ff0c18 10391 * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
mbed_official 146:f64d43ff0c18 10392 * @{
mbed_official 146:f64d43ff0c18 10393 */
mbed_official 146:f64d43ff0c18 10394
mbed_official 146:f64d43ff0c18 10395
mbed_official 146:f64d43ff0c18 10396 /* RNG - Register instance definitions */
mbed_official 146:f64d43ff0c18 10397 /* RNG */
mbed_official 146:f64d43ff0c18 10398 #define RNG_CR RNG_CR_REG(RNG)
mbed_official 146:f64d43ff0c18 10399 #define RNG_SR RNG_SR_REG(RNG)
mbed_official 146:f64d43ff0c18 10400 #define RNG_ER RNG_ER_REG(RNG)
mbed_official 146:f64d43ff0c18 10401 #define RNG_OR RNG_OR_REG(RNG)
mbed_official 146:f64d43ff0c18 10402
mbed_official 146:f64d43ff0c18 10403 /*!
mbed_official 146:f64d43ff0c18 10404 * @}
mbed_official 146:f64d43ff0c18 10405 */ /* end of group RNG_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 10406
mbed_official 146:f64d43ff0c18 10407
mbed_official 146:f64d43ff0c18 10408 /*!
mbed_official 146:f64d43ff0c18 10409 * @}
mbed_official 146:f64d43ff0c18 10410 */ /* end of group RNG_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 10411
mbed_official 146:f64d43ff0c18 10412
mbed_official 146:f64d43ff0c18 10413 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 10414 -- RTC Peripheral Access Layer
mbed_official 146:f64d43ff0c18 10415 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 10416
mbed_official 146:f64d43ff0c18 10417 /*!
mbed_official 146:f64d43ff0c18 10418 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
mbed_official 146:f64d43ff0c18 10419 * @{
mbed_official 146:f64d43ff0c18 10420 */
mbed_official 146:f64d43ff0c18 10421
mbed_official 146:f64d43ff0c18 10422 /** RTC - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 10423 typedef struct {
mbed_official 146:f64d43ff0c18 10424 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
mbed_official 146:f64d43ff0c18 10425 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
mbed_official 146:f64d43ff0c18 10426 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
mbed_official 146:f64d43ff0c18 10427 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
mbed_official 146:f64d43ff0c18 10428 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
mbed_official 146:f64d43ff0c18 10429 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
mbed_official 146:f64d43ff0c18 10430 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
mbed_official 146:f64d43ff0c18 10431 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
mbed_official 146:f64d43ff0c18 10432 uint8_t RESERVED_0[2016];
mbed_official 146:f64d43ff0c18 10433 __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
mbed_official 146:f64d43ff0c18 10434 __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
mbed_official 146:f64d43ff0c18 10435 } RTC_Type, *RTC_MemMapPtr;
mbed_official 146:f64d43ff0c18 10436
mbed_official 146:f64d43ff0c18 10437 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 10438 -- RTC - Register accessor macros
mbed_official 146:f64d43ff0c18 10439 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 10440
mbed_official 146:f64d43ff0c18 10441 /*!
mbed_official 146:f64d43ff0c18 10442 * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
mbed_official 146:f64d43ff0c18 10443 * @{
mbed_official 146:f64d43ff0c18 10444 */
mbed_official 146:f64d43ff0c18 10445
mbed_official 146:f64d43ff0c18 10446
mbed_official 146:f64d43ff0c18 10447 /* RTC - Register accessors */
mbed_official 146:f64d43ff0c18 10448 #define RTC_TSR_REG(base) ((base)->TSR)
mbed_official 146:f64d43ff0c18 10449 #define RTC_TPR_REG(base) ((base)->TPR)
mbed_official 146:f64d43ff0c18 10450 #define RTC_TAR_REG(base) ((base)->TAR)
mbed_official 146:f64d43ff0c18 10451 #define RTC_TCR_REG(base) ((base)->TCR)
mbed_official 146:f64d43ff0c18 10452 #define RTC_CR_REG(base) ((base)->CR)
mbed_official 146:f64d43ff0c18 10453 #define RTC_SR_REG(base) ((base)->SR)
mbed_official 146:f64d43ff0c18 10454 #define RTC_LR_REG(base) ((base)->LR)
mbed_official 146:f64d43ff0c18 10455 #define RTC_IER_REG(base) ((base)->IER)
mbed_official 146:f64d43ff0c18 10456 #define RTC_WAR_REG(base) ((base)->WAR)
mbed_official 146:f64d43ff0c18 10457 #define RTC_RAR_REG(base) ((base)->RAR)
mbed_official 146:f64d43ff0c18 10458
mbed_official 146:f64d43ff0c18 10459 /*!
mbed_official 146:f64d43ff0c18 10460 * @}
mbed_official 146:f64d43ff0c18 10461 */ /* end of group RTC_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 10462
mbed_official 146:f64d43ff0c18 10463
mbed_official 146:f64d43ff0c18 10464 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 10465 -- RTC Register Masks
mbed_official 146:f64d43ff0c18 10466 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 10467
mbed_official 146:f64d43ff0c18 10468 /*!
mbed_official 146:f64d43ff0c18 10469 * @addtogroup RTC_Register_Masks RTC Register Masks
mbed_official 146:f64d43ff0c18 10470 * @{
mbed_official 146:f64d43ff0c18 10471 */
mbed_official 146:f64d43ff0c18 10472
mbed_official 146:f64d43ff0c18 10473 /* TSR Bit Fields */
mbed_official 146:f64d43ff0c18 10474 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 10475 #define RTC_TSR_TSR_SHIFT 0
mbed_official 146:f64d43ff0c18 10476 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
mbed_official 146:f64d43ff0c18 10477 /* TPR Bit Fields */
mbed_official 146:f64d43ff0c18 10478 #define RTC_TPR_TPR_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 10479 #define RTC_TPR_TPR_SHIFT 0
mbed_official 146:f64d43ff0c18 10480 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
mbed_official 146:f64d43ff0c18 10481 /* TAR Bit Fields */
mbed_official 146:f64d43ff0c18 10482 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 10483 #define RTC_TAR_TAR_SHIFT 0
mbed_official 146:f64d43ff0c18 10484 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
mbed_official 146:f64d43ff0c18 10485 /* TCR Bit Fields */
mbed_official 146:f64d43ff0c18 10486 #define RTC_TCR_TCR_MASK 0xFFu
mbed_official 146:f64d43ff0c18 10487 #define RTC_TCR_TCR_SHIFT 0
mbed_official 146:f64d43ff0c18 10488 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
mbed_official 146:f64d43ff0c18 10489 #define RTC_TCR_CIR_MASK 0xFF00u
mbed_official 146:f64d43ff0c18 10490 #define RTC_TCR_CIR_SHIFT 8
mbed_official 146:f64d43ff0c18 10491 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
mbed_official 146:f64d43ff0c18 10492 #define RTC_TCR_TCV_MASK 0xFF0000u
mbed_official 146:f64d43ff0c18 10493 #define RTC_TCR_TCV_SHIFT 16
mbed_official 146:f64d43ff0c18 10494 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
mbed_official 146:f64d43ff0c18 10495 #define RTC_TCR_CIC_MASK 0xFF000000u
mbed_official 146:f64d43ff0c18 10496 #define RTC_TCR_CIC_SHIFT 24
mbed_official 146:f64d43ff0c18 10497 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
mbed_official 146:f64d43ff0c18 10498 /* CR Bit Fields */
mbed_official 146:f64d43ff0c18 10499 #define RTC_CR_SWR_MASK 0x1u
mbed_official 146:f64d43ff0c18 10500 #define RTC_CR_SWR_SHIFT 0
mbed_official 146:f64d43ff0c18 10501 #define RTC_CR_WPE_MASK 0x2u
mbed_official 146:f64d43ff0c18 10502 #define RTC_CR_WPE_SHIFT 1
mbed_official 146:f64d43ff0c18 10503 #define RTC_CR_SUP_MASK 0x4u
mbed_official 146:f64d43ff0c18 10504 #define RTC_CR_SUP_SHIFT 2
mbed_official 146:f64d43ff0c18 10505 #define RTC_CR_UM_MASK 0x8u
mbed_official 146:f64d43ff0c18 10506 #define RTC_CR_UM_SHIFT 3
mbed_official 146:f64d43ff0c18 10507 #define RTC_CR_WPS_MASK 0x10u
mbed_official 146:f64d43ff0c18 10508 #define RTC_CR_WPS_SHIFT 4
mbed_official 146:f64d43ff0c18 10509 #define RTC_CR_OSCE_MASK 0x100u
mbed_official 146:f64d43ff0c18 10510 #define RTC_CR_OSCE_SHIFT 8
mbed_official 146:f64d43ff0c18 10511 #define RTC_CR_CLKO_MASK 0x200u
mbed_official 146:f64d43ff0c18 10512 #define RTC_CR_CLKO_SHIFT 9
mbed_official 146:f64d43ff0c18 10513 #define RTC_CR_SC16P_MASK 0x400u
mbed_official 146:f64d43ff0c18 10514 #define RTC_CR_SC16P_SHIFT 10
mbed_official 146:f64d43ff0c18 10515 #define RTC_CR_SC8P_MASK 0x800u
mbed_official 146:f64d43ff0c18 10516 #define RTC_CR_SC8P_SHIFT 11
mbed_official 146:f64d43ff0c18 10517 #define RTC_CR_SC4P_MASK 0x1000u
mbed_official 146:f64d43ff0c18 10518 #define RTC_CR_SC4P_SHIFT 12
mbed_official 146:f64d43ff0c18 10519 #define RTC_CR_SC2P_MASK 0x2000u
mbed_official 146:f64d43ff0c18 10520 #define RTC_CR_SC2P_SHIFT 13
mbed_official 146:f64d43ff0c18 10521 /* SR Bit Fields */
mbed_official 146:f64d43ff0c18 10522 #define RTC_SR_TIF_MASK 0x1u
mbed_official 146:f64d43ff0c18 10523 #define RTC_SR_TIF_SHIFT 0
mbed_official 146:f64d43ff0c18 10524 #define RTC_SR_TOF_MASK 0x2u
mbed_official 146:f64d43ff0c18 10525 #define RTC_SR_TOF_SHIFT 1
mbed_official 146:f64d43ff0c18 10526 #define RTC_SR_TAF_MASK 0x4u
mbed_official 146:f64d43ff0c18 10527 #define RTC_SR_TAF_SHIFT 2
mbed_official 146:f64d43ff0c18 10528 #define RTC_SR_TCE_MASK 0x10u
mbed_official 146:f64d43ff0c18 10529 #define RTC_SR_TCE_SHIFT 4
mbed_official 146:f64d43ff0c18 10530 /* LR Bit Fields */
mbed_official 146:f64d43ff0c18 10531 #define RTC_LR_TCL_MASK 0x8u
mbed_official 146:f64d43ff0c18 10532 #define RTC_LR_TCL_SHIFT 3
mbed_official 146:f64d43ff0c18 10533 #define RTC_LR_CRL_MASK 0x10u
mbed_official 146:f64d43ff0c18 10534 #define RTC_LR_CRL_SHIFT 4
mbed_official 146:f64d43ff0c18 10535 #define RTC_LR_SRL_MASK 0x20u
mbed_official 146:f64d43ff0c18 10536 #define RTC_LR_SRL_SHIFT 5
mbed_official 146:f64d43ff0c18 10537 #define RTC_LR_LRL_MASK 0x40u
mbed_official 146:f64d43ff0c18 10538 #define RTC_LR_LRL_SHIFT 6
mbed_official 146:f64d43ff0c18 10539 /* IER Bit Fields */
mbed_official 146:f64d43ff0c18 10540 #define RTC_IER_TIIE_MASK 0x1u
mbed_official 146:f64d43ff0c18 10541 #define RTC_IER_TIIE_SHIFT 0
mbed_official 146:f64d43ff0c18 10542 #define RTC_IER_TOIE_MASK 0x2u
mbed_official 146:f64d43ff0c18 10543 #define RTC_IER_TOIE_SHIFT 1
mbed_official 146:f64d43ff0c18 10544 #define RTC_IER_TAIE_MASK 0x4u
mbed_official 146:f64d43ff0c18 10545 #define RTC_IER_TAIE_SHIFT 2
mbed_official 146:f64d43ff0c18 10546 #define RTC_IER_TSIE_MASK 0x10u
mbed_official 146:f64d43ff0c18 10547 #define RTC_IER_TSIE_SHIFT 4
mbed_official 146:f64d43ff0c18 10548 #define RTC_IER_WPON_MASK 0x80u
mbed_official 146:f64d43ff0c18 10549 #define RTC_IER_WPON_SHIFT 7
mbed_official 146:f64d43ff0c18 10550 /* WAR Bit Fields */
mbed_official 146:f64d43ff0c18 10551 #define RTC_WAR_TSRW_MASK 0x1u
mbed_official 146:f64d43ff0c18 10552 #define RTC_WAR_TSRW_SHIFT 0
mbed_official 146:f64d43ff0c18 10553 #define RTC_WAR_TPRW_MASK 0x2u
mbed_official 146:f64d43ff0c18 10554 #define RTC_WAR_TPRW_SHIFT 1
mbed_official 146:f64d43ff0c18 10555 #define RTC_WAR_TARW_MASK 0x4u
mbed_official 146:f64d43ff0c18 10556 #define RTC_WAR_TARW_SHIFT 2
mbed_official 146:f64d43ff0c18 10557 #define RTC_WAR_TCRW_MASK 0x8u
mbed_official 146:f64d43ff0c18 10558 #define RTC_WAR_TCRW_SHIFT 3
mbed_official 146:f64d43ff0c18 10559 #define RTC_WAR_CRW_MASK 0x10u
mbed_official 146:f64d43ff0c18 10560 #define RTC_WAR_CRW_SHIFT 4
mbed_official 146:f64d43ff0c18 10561 #define RTC_WAR_SRW_MASK 0x20u
mbed_official 146:f64d43ff0c18 10562 #define RTC_WAR_SRW_SHIFT 5
mbed_official 146:f64d43ff0c18 10563 #define RTC_WAR_LRW_MASK 0x40u
mbed_official 146:f64d43ff0c18 10564 #define RTC_WAR_LRW_SHIFT 6
mbed_official 146:f64d43ff0c18 10565 #define RTC_WAR_IERW_MASK 0x80u
mbed_official 146:f64d43ff0c18 10566 #define RTC_WAR_IERW_SHIFT 7
mbed_official 146:f64d43ff0c18 10567 /* RAR Bit Fields */
mbed_official 146:f64d43ff0c18 10568 #define RTC_RAR_TSRR_MASK 0x1u
mbed_official 146:f64d43ff0c18 10569 #define RTC_RAR_TSRR_SHIFT 0
mbed_official 146:f64d43ff0c18 10570 #define RTC_RAR_TPRR_MASK 0x2u
mbed_official 146:f64d43ff0c18 10571 #define RTC_RAR_TPRR_SHIFT 1
mbed_official 146:f64d43ff0c18 10572 #define RTC_RAR_TARR_MASK 0x4u
mbed_official 146:f64d43ff0c18 10573 #define RTC_RAR_TARR_SHIFT 2
mbed_official 146:f64d43ff0c18 10574 #define RTC_RAR_TCRR_MASK 0x8u
mbed_official 146:f64d43ff0c18 10575 #define RTC_RAR_TCRR_SHIFT 3
mbed_official 146:f64d43ff0c18 10576 #define RTC_RAR_CRR_MASK 0x10u
mbed_official 146:f64d43ff0c18 10577 #define RTC_RAR_CRR_SHIFT 4
mbed_official 146:f64d43ff0c18 10578 #define RTC_RAR_SRR_MASK 0x20u
mbed_official 146:f64d43ff0c18 10579 #define RTC_RAR_SRR_SHIFT 5
mbed_official 146:f64d43ff0c18 10580 #define RTC_RAR_LRR_MASK 0x40u
mbed_official 146:f64d43ff0c18 10581 #define RTC_RAR_LRR_SHIFT 6
mbed_official 146:f64d43ff0c18 10582 #define RTC_RAR_IERR_MASK 0x80u
mbed_official 146:f64d43ff0c18 10583 #define RTC_RAR_IERR_SHIFT 7
mbed_official 146:f64d43ff0c18 10584
mbed_official 146:f64d43ff0c18 10585 /*!
mbed_official 146:f64d43ff0c18 10586 * @}
mbed_official 146:f64d43ff0c18 10587 */ /* end of group RTC_Register_Masks */
mbed_official 146:f64d43ff0c18 10588
mbed_official 146:f64d43ff0c18 10589
mbed_official 146:f64d43ff0c18 10590 /* RTC - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 10591 /** Peripheral RTC base address */
mbed_official 146:f64d43ff0c18 10592 #define RTC_BASE (0x4003D000u)
mbed_official 146:f64d43ff0c18 10593 /** Peripheral RTC base pointer */
mbed_official 146:f64d43ff0c18 10594 #define RTC ((RTC_Type *)RTC_BASE)
mbed_official 146:f64d43ff0c18 10595 #define RTC_BASE_PTR (RTC)
mbed_official 146:f64d43ff0c18 10596 /** Array initializer of RTC peripheral base pointers */
mbed_official 146:f64d43ff0c18 10597 #define RTC_BASES { RTC }
mbed_official 146:f64d43ff0c18 10598
mbed_official 146:f64d43ff0c18 10599 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 10600 -- RTC - Register accessor macros
mbed_official 146:f64d43ff0c18 10601 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 10602
mbed_official 146:f64d43ff0c18 10603 /*!
mbed_official 146:f64d43ff0c18 10604 * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
mbed_official 146:f64d43ff0c18 10605 * @{
mbed_official 146:f64d43ff0c18 10606 */
mbed_official 146:f64d43ff0c18 10607
mbed_official 146:f64d43ff0c18 10608
mbed_official 146:f64d43ff0c18 10609 /* RTC - Register instance definitions */
mbed_official 146:f64d43ff0c18 10610 /* RTC */
mbed_official 146:f64d43ff0c18 10611 #define RTC_TSR RTC_TSR_REG(RTC)
mbed_official 146:f64d43ff0c18 10612 #define RTC_TPR RTC_TPR_REG(RTC)
mbed_official 146:f64d43ff0c18 10613 #define RTC_TAR RTC_TAR_REG(RTC)
mbed_official 146:f64d43ff0c18 10614 #define RTC_TCR RTC_TCR_REG(RTC)
mbed_official 146:f64d43ff0c18 10615 #define RTC_CR RTC_CR_REG(RTC)
mbed_official 146:f64d43ff0c18 10616 #define RTC_SR RTC_SR_REG(RTC)
mbed_official 146:f64d43ff0c18 10617 #define RTC_LR RTC_LR_REG(RTC)
mbed_official 146:f64d43ff0c18 10618 #define RTC_IER RTC_IER_REG(RTC)
mbed_official 146:f64d43ff0c18 10619 #define RTC_WAR RTC_WAR_REG(RTC)
mbed_official 146:f64d43ff0c18 10620 #define RTC_RAR RTC_RAR_REG(RTC)
mbed_official 146:f64d43ff0c18 10621
mbed_official 146:f64d43ff0c18 10622 /*!
mbed_official 146:f64d43ff0c18 10623 * @}
mbed_official 146:f64d43ff0c18 10624 */ /* end of group RTC_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 10625
mbed_official 146:f64d43ff0c18 10626
mbed_official 146:f64d43ff0c18 10627 /*!
mbed_official 146:f64d43ff0c18 10628 * @}
mbed_official 146:f64d43ff0c18 10629 */ /* end of group RTC_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 10630
mbed_official 146:f64d43ff0c18 10631
mbed_official 146:f64d43ff0c18 10632 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 10633 -- SDHC Peripheral Access Layer
mbed_official 146:f64d43ff0c18 10634 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 10635
mbed_official 146:f64d43ff0c18 10636 /*!
mbed_official 146:f64d43ff0c18 10637 * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer
mbed_official 146:f64d43ff0c18 10638 * @{
mbed_official 146:f64d43ff0c18 10639 */
mbed_official 146:f64d43ff0c18 10640
mbed_official 146:f64d43ff0c18 10641 /** SDHC - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 10642 typedef struct {
mbed_official 146:f64d43ff0c18 10643 __IO uint32_t DSADDR; /**< DMA System Address register, offset: 0x0 */
mbed_official 146:f64d43ff0c18 10644 __IO uint32_t BLKATTR; /**< Block Attributes register, offset: 0x4 */
mbed_official 146:f64d43ff0c18 10645 __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x8 */
mbed_official 146:f64d43ff0c18 10646 __IO uint32_t XFERTYP; /**< Transfer Type register, offset: 0xC */
mbed_official 146:f64d43ff0c18 10647 __I uint32_t CMDRSP[4]; /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */
mbed_official 146:f64d43ff0c18 10648 __IO uint32_t DATPORT; /**< Buffer Data Port register, offset: 0x20 */
mbed_official 146:f64d43ff0c18 10649 __I uint32_t PRSSTAT; /**< Present State register, offset: 0x24 */
mbed_official 146:f64d43ff0c18 10650 __IO uint32_t PROCTL; /**< Protocol Control register, offset: 0x28 */
mbed_official 146:f64d43ff0c18 10651 __IO uint32_t SYSCTL; /**< System Control register, offset: 0x2C */
mbed_official 146:f64d43ff0c18 10652 __IO uint32_t IRQSTAT; /**< Interrupt Status register, offset: 0x30 */
mbed_official 146:f64d43ff0c18 10653 __IO uint32_t IRQSTATEN; /**< Interrupt Status Enable register, offset: 0x34 */
mbed_official 146:f64d43ff0c18 10654 __IO uint32_t IRQSIGEN; /**< Interrupt Signal Enable register, offset: 0x38 */
mbed_official 146:f64d43ff0c18 10655 __I uint32_t AC12ERR; /**< Auto CMD12 Error Status Register, offset: 0x3C */
mbed_official 146:f64d43ff0c18 10656 __I uint32_t HTCAPBLT; /**< Host Controller Capabilities, offset: 0x40 */
mbed_official 146:f64d43ff0c18 10657 __IO uint32_t WML; /**< Watermark Level Register, offset: 0x44 */
mbed_official 146:f64d43ff0c18 10658 uint8_t RESERVED_0[8];
mbed_official 146:f64d43ff0c18 10659 __O uint32_t FEVT; /**< Force Event register, offset: 0x50 */
mbed_official 146:f64d43ff0c18 10660 __I uint32_t ADMAES; /**< ADMA Error Status register, offset: 0x54 */
mbed_official 146:f64d43ff0c18 10661 __IO uint32_t ADSADDR; /**< ADMA System Addressregister, offset: 0x58 */
mbed_official 146:f64d43ff0c18 10662 uint8_t RESERVED_1[100];
mbed_official 146:f64d43ff0c18 10663 __IO uint32_t VENDOR; /**< Vendor Specific register, offset: 0xC0 */
mbed_official 146:f64d43ff0c18 10664 __IO uint32_t MMCBOOT; /**< MMC Boot register, offset: 0xC4 */
mbed_official 146:f64d43ff0c18 10665 uint8_t RESERVED_2[52];
mbed_official 146:f64d43ff0c18 10666 __I uint32_t HOSTVER; /**< Host Controller Version, offset: 0xFC */
mbed_official 146:f64d43ff0c18 10667 } SDHC_Type, *SDHC_MemMapPtr;
mbed_official 146:f64d43ff0c18 10668
mbed_official 146:f64d43ff0c18 10669 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 10670 -- SDHC - Register accessor macros
mbed_official 146:f64d43ff0c18 10671 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 10672
mbed_official 146:f64d43ff0c18 10673 /*!
mbed_official 146:f64d43ff0c18 10674 * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
mbed_official 146:f64d43ff0c18 10675 * @{
mbed_official 146:f64d43ff0c18 10676 */
mbed_official 146:f64d43ff0c18 10677
mbed_official 146:f64d43ff0c18 10678
mbed_official 146:f64d43ff0c18 10679 /* SDHC - Register accessors */
mbed_official 146:f64d43ff0c18 10680 #define SDHC_DSADDR_REG(base) ((base)->DSADDR)
mbed_official 146:f64d43ff0c18 10681 #define SDHC_BLKATTR_REG(base) ((base)->BLKATTR)
mbed_official 146:f64d43ff0c18 10682 #define SDHC_CMDARG_REG(base) ((base)->CMDARG)
mbed_official 146:f64d43ff0c18 10683 #define SDHC_XFERTYP_REG(base) ((base)->XFERTYP)
mbed_official 146:f64d43ff0c18 10684 #define SDHC_CMDRSP_REG(base,index) ((base)->CMDRSP[index])
mbed_official 146:f64d43ff0c18 10685 #define SDHC_DATPORT_REG(base) ((base)->DATPORT)
mbed_official 146:f64d43ff0c18 10686 #define SDHC_PRSSTAT_REG(base) ((base)->PRSSTAT)
mbed_official 146:f64d43ff0c18 10687 #define SDHC_PROCTL_REG(base) ((base)->PROCTL)
mbed_official 146:f64d43ff0c18 10688 #define SDHC_SYSCTL_REG(base) ((base)->SYSCTL)
mbed_official 146:f64d43ff0c18 10689 #define SDHC_IRQSTAT_REG(base) ((base)->IRQSTAT)
mbed_official 146:f64d43ff0c18 10690 #define SDHC_IRQSTATEN_REG(base) ((base)->IRQSTATEN)
mbed_official 146:f64d43ff0c18 10691 #define SDHC_IRQSIGEN_REG(base) ((base)->IRQSIGEN)
mbed_official 146:f64d43ff0c18 10692 #define SDHC_AC12ERR_REG(base) ((base)->AC12ERR)
mbed_official 146:f64d43ff0c18 10693 #define SDHC_HTCAPBLT_REG(base) ((base)->HTCAPBLT)
mbed_official 146:f64d43ff0c18 10694 #define SDHC_WML_REG(base) ((base)->WML)
mbed_official 146:f64d43ff0c18 10695 #define SDHC_FEVT_REG(base) ((base)->FEVT)
mbed_official 146:f64d43ff0c18 10696 #define SDHC_ADMAES_REG(base) ((base)->ADMAES)
mbed_official 146:f64d43ff0c18 10697 #define SDHC_ADSADDR_REG(base) ((base)->ADSADDR)
mbed_official 146:f64d43ff0c18 10698 #define SDHC_VENDOR_REG(base) ((base)->VENDOR)
mbed_official 146:f64d43ff0c18 10699 #define SDHC_MMCBOOT_REG(base) ((base)->MMCBOOT)
mbed_official 146:f64d43ff0c18 10700 #define SDHC_HOSTVER_REG(base) ((base)->HOSTVER)
mbed_official 146:f64d43ff0c18 10701
mbed_official 146:f64d43ff0c18 10702 /*!
mbed_official 146:f64d43ff0c18 10703 * @}
mbed_official 146:f64d43ff0c18 10704 */ /* end of group SDHC_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 10705
mbed_official 146:f64d43ff0c18 10706
mbed_official 146:f64d43ff0c18 10707 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 10708 -- SDHC Register Masks
mbed_official 146:f64d43ff0c18 10709 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 10710
mbed_official 146:f64d43ff0c18 10711 /*!
mbed_official 146:f64d43ff0c18 10712 * @addtogroup SDHC_Register_Masks SDHC Register Masks
mbed_official 146:f64d43ff0c18 10713 * @{
mbed_official 146:f64d43ff0c18 10714 */
mbed_official 146:f64d43ff0c18 10715
mbed_official 146:f64d43ff0c18 10716 /* DSADDR Bit Fields */
mbed_official 146:f64d43ff0c18 10717 #define SDHC_DSADDR_DSADDR_MASK 0xFFFFFFFCu
mbed_official 146:f64d43ff0c18 10718 #define SDHC_DSADDR_DSADDR_SHIFT 2
mbed_official 146:f64d43ff0c18 10719 #define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x))<<SDHC_DSADDR_DSADDR_SHIFT))&SDHC_DSADDR_DSADDR_MASK)
mbed_official 146:f64d43ff0c18 10720 /* BLKATTR Bit Fields */
mbed_official 146:f64d43ff0c18 10721 #define SDHC_BLKATTR_BLKSIZE_MASK 0x1FFFu
mbed_official 146:f64d43ff0c18 10722 #define SDHC_BLKATTR_BLKSIZE_SHIFT 0
mbed_official 146:f64d43ff0c18 10723 #define SDHC_BLKATTR_BLKSIZE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKSIZE_SHIFT))&SDHC_BLKATTR_BLKSIZE_MASK)
mbed_official 146:f64d43ff0c18 10724 #define SDHC_BLKATTR_BLKCNT_MASK 0xFFFF0000u
mbed_official 146:f64d43ff0c18 10725 #define SDHC_BLKATTR_BLKCNT_SHIFT 16
mbed_official 146:f64d43ff0c18 10726 #define SDHC_BLKATTR_BLKCNT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKCNT_SHIFT))&SDHC_BLKATTR_BLKCNT_MASK)
mbed_official 146:f64d43ff0c18 10727 /* CMDARG Bit Fields */
mbed_official 146:f64d43ff0c18 10728 #define SDHC_CMDARG_CMDARG_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 10729 #define SDHC_CMDARG_CMDARG_SHIFT 0
mbed_official 146:f64d43ff0c18 10730 #define SDHC_CMDARG_CMDARG(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDARG_CMDARG_SHIFT))&SDHC_CMDARG_CMDARG_MASK)
mbed_official 146:f64d43ff0c18 10731 /* XFERTYP Bit Fields */
mbed_official 146:f64d43ff0c18 10732 #define SDHC_XFERTYP_DMAEN_MASK 0x1u
mbed_official 146:f64d43ff0c18 10733 #define SDHC_XFERTYP_DMAEN_SHIFT 0
mbed_official 146:f64d43ff0c18 10734 #define SDHC_XFERTYP_BCEN_MASK 0x2u
mbed_official 146:f64d43ff0c18 10735 #define SDHC_XFERTYP_BCEN_SHIFT 1
mbed_official 146:f64d43ff0c18 10736 #define SDHC_XFERTYP_AC12EN_MASK 0x4u
mbed_official 146:f64d43ff0c18 10737 #define SDHC_XFERTYP_AC12EN_SHIFT 2
mbed_official 146:f64d43ff0c18 10738 #define SDHC_XFERTYP_DTDSEL_MASK 0x10u
mbed_official 146:f64d43ff0c18 10739 #define SDHC_XFERTYP_DTDSEL_SHIFT 4
mbed_official 146:f64d43ff0c18 10740 #define SDHC_XFERTYP_MSBSEL_MASK 0x20u
mbed_official 146:f64d43ff0c18 10741 #define SDHC_XFERTYP_MSBSEL_SHIFT 5
mbed_official 146:f64d43ff0c18 10742 #define SDHC_XFERTYP_RSPTYP_MASK 0x30000u
mbed_official 146:f64d43ff0c18 10743 #define SDHC_XFERTYP_RSPTYP_SHIFT 16
mbed_official 146:f64d43ff0c18 10744 #define SDHC_XFERTYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_RSPTYP_SHIFT))&SDHC_XFERTYP_RSPTYP_MASK)
mbed_official 146:f64d43ff0c18 10745 #define SDHC_XFERTYP_CCCEN_MASK 0x80000u
mbed_official 146:f64d43ff0c18 10746 #define SDHC_XFERTYP_CCCEN_SHIFT 19
mbed_official 146:f64d43ff0c18 10747 #define SDHC_XFERTYP_CICEN_MASK 0x100000u
mbed_official 146:f64d43ff0c18 10748 #define SDHC_XFERTYP_CICEN_SHIFT 20
mbed_official 146:f64d43ff0c18 10749 #define SDHC_XFERTYP_DPSEL_MASK 0x200000u
mbed_official 146:f64d43ff0c18 10750 #define SDHC_XFERTYP_DPSEL_SHIFT 21
mbed_official 146:f64d43ff0c18 10751 #define SDHC_XFERTYP_CMDTYP_MASK 0xC00000u
mbed_official 146:f64d43ff0c18 10752 #define SDHC_XFERTYP_CMDTYP_SHIFT 22
mbed_official 146:f64d43ff0c18 10753 #define SDHC_XFERTYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDTYP_SHIFT))&SDHC_XFERTYP_CMDTYP_MASK)
mbed_official 146:f64d43ff0c18 10754 #define SDHC_XFERTYP_CMDINX_MASK 0x3F000000u
mbed_official 146:f64d43ff0c18 10755 #define SDHC_XFERTYP_CMDINX_SHIFT 24
mbed_official 146:f64d43ff0c18 10756 #define SDHC_XFERTYP_CMDINX(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDINX_SHIFT))&SDHC_XFERTYP_CMDINX_MASK)
mbed_official 146:f64d43ff0c18 10757 /* CMDRSP Bit Fields */
mbed_official 146:f64d43ff0c18 10758 #define SDHC_CMDRSP_CMDRSP0_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 10759 #define SDHC_CMDRSP_CMDRSP0_SHIFT 0
mbed_official 146:f64d43ff0c18 10760 #define SDHC_CMDRSP_CMDRSP0(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP0_SHIFT))&SDHC_CMDRSP_CMDRSP0_MASK)
mbed_official 146:f64d43ff0c18 10761 #define SDHC_CMDRSP_CMDRSP1_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 10762 #define SDHC_CMDRSP_CMDRSP1_SHIFT 0
mbed_official 146:f64d43ff0c18 10763 #define SDHC_CMDRSP_CMDRSP1(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP1_SHIFT))&SDHC_CMDRSP_CMDRSP1_MASK)
mbed_official 146:f64d43ff0c18 10764 #define SDHC_CMDRSP_CMDRSP2_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 10765 #define SDHC_CMDRSP_CMDRSP2_SHIFT 0
mbed_official 146:f64d43ff0c18 10766 #define SDHC_CMDRSP_CMDRSP2(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP2_SHIFT))&SDHC_CMDRSP_CMDRSP2_MASK)
mbed_official 146:f64d43ff0c18 10767 #define SDHC_CMDRSP_CMDRSP3_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 10768 #define SDHC_CMDRSP_CMDRSP3_SHIFT 0
mbed_official 146:f64d43ff0c18 10769 #define SDHC_CMDRSP_CMDRSP3(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP3_SHIFT))&SDHC_CMDRSP_CMDRSP3_MASK)
mbed_official 146:f64d43ff0c18 10770 /* DATPORT Bit Fields */
mbed_official 146:f64d43ff0c18 10771 #define SDHC_DATPORT_DATCONT_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 10772 #define SDHC_DATPORT_DATCONT_SHIFT 0
mbed_official 146:f64d43ff0c18 10773 #define SDHC_DATPORT_DATCONT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_DATPORT_DATCONT_SHIFT))&SDHC_DATPORT_DATCONT_MASK)
mbed_official 146:f64d43ff0c18 10774 /* PRSSTAT Bit Fields */
mbed_official 146:f64d43ff0c18 10775 #define SDHC_PRSSTAT_CIHB_MASK 0x1u
mbed_official 146:f64d43ff0c18 10776 #define SDHC_PRSSTAT_CIHB_SHIFT 0
mbed_official 146:f64d43ff0c18 10777 #define SDHC_PRSSTAT_CDIHB_MASK 0x2u
mbed_official 146:f64d43ff0c18 10778 #define SDHC_PRSSTAT_CDIHB_SHIFT 1
mbed_official 146:f64d43ff0c18 10779 #define SDHC_PRSSTAT_DLA_MASK 0x4u
mbed_official 146:f64d43ff0c18 10780 #define SDHC_PRSSTAT_DLA_SHIFT 2
mbed_official 146:f64d43ff0c18 10781 #define SDHC_PRSSTAT_SDSTB_MASK 0x8u
mbed_official 146:f64d43ff0c18 10782 #define SDHC_PRSSTAT_SDSTB_SHIFT 3
mbed_official 146:f64d43ff0c18 10783 #define SDHC_PRSSTAT_IPGOFF_MASK 0x10u
mbed_official 146:f64d43ff0c18 10784 #define SDHC_PRSSTAT_IPGOFF_SHIFT 4
mbed_official 146:f64d43ff0c18 10785 #define SDHC_PRSSTAT_HCKOFF_MASK 0x20u
mbed_official 146:f64d43ff0c18 10786 #define SDHC_PRSSTAT_HCKOFF_SHIFT 5
mbed_official 146:f64d43ff0c18 10787 #define SDHC_PRSSTAT_PEROFF_MASK 0x40u
mbed_official 146:f64d43ff0c18 10788 #define SDHC_PRSSTAT_PEROFF_SHIFT 6
mbed_official 146:f64d43ff0c18 10789 #define SDHC_PRSSTAT_SDOFF_MASK 0x80u
mbed_official 146:f64d43ff0c18 10790 #define SDHC_PRSSTAT_SDOFF_SHIFT 7
mbed_official 146:f64d43ff0c18 10791 #define SDHC_PRSSTAT_WTA_MASK 0x100u
mbed_official 146:f64d43ff0c18 10792 #define SDHC_PRSSTAT_WTA_SHIFT 8
mbed_official 146:f64d43ff0c18 10793 #define SDHC_PRSSTAT_RTA_MASK 0x200u
mbed_official 146:f64d43ff0c18 10794 #define SDHC_PRSSTAT_RTA_SHIFT 9
mbed_official 146:f64d43ff0c18 10795 #define SDHC_PRSSTAT_BWEN_MASK 0x400u
mbed_official 146:f64d43ff0c18 10796 #define SDHC_PRSSTAT_BWEN_SHIFT 10
mbed_official 146:f64d43ff0c18 10797 #define SDHC_PRSSTAT_BREN_MASK 0x800u
mbed_official 146:f64d43ff0c18 10798 #define SDHC_PRSSTAT_BREN_SHIFT 11
mbed_official 146:f64d43ff0c18 10799 #define SDHC_PRSSTAT_CINS_MASK 0x10000u
mbed_official 146:f64d43ff0c18 10800 #define SDHC_PRSSTAT_CINS_SHIFT 16
mbed_official 146:f64d43ff0c18 10801 #define SDHC_PRSSTAT_CLSL_MASK 0x800000u
mbed_official 146:f64d43ff0c18 10802 #define SDHC_PRSSTAT_CLSL_SHIFT 23
mbed_official 146:f64d43ff0c18 10803 #define SDHC_PRSSTAT_DLSL_MASK 0xFF000000u
mbed_official 146:f64d43ff0c18 10804 #define SDHC_PRSSTAT_DLSL_SHIFT 24
mbed_official 146:f64d43ff0c18 10805 #define SDHC_PRSSTAT_DLSL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_DLSL_SHIFT))&SDHC_PRSSTAT_DLSL_MASK)
mbed_official 146:f64d43ff0c18 10806 /* PROCTL Bit Fields */
mbed_official 146:f64d43ff0c18 10807 #define SDHC_PROCTL_LCTL_MASK 0x1u
mbed_official 146:f64d43ff0c18 10808 #define SDHC_PROCTL_LCTL_SHIFT 0
mbed_official 146:f64d43ff0c18 10809 #define SDHC_PROCTL_DTW_MASK 0x6u
mbed_official 146:f64d43ff0c18 10810 #define SDHC_PROCTL_DTW_SHIFT 1
mbed_official 146:f64d43ff0c18 10811 #define SDHC_PROCTL_DTW(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DTW_SHIFT))&SDHC_PROCTL_DTW_MASK)
mbed_official 146:f64d43ff0c18 10812 #define SDHC_PROCTL_D3CD_MASK 0x8u
mbed_official 146:f64d43ff0c18 10813 #define SDHC_PROCTL_D3CD_SHIFT 3
mbed_official 146:f64d43ff0c18 10814 #define SDHC_PROCTL_EMODE_MASK 0x30u
mbed_official 146:f64d43ff0c18 10815 #define SDHC_PROCTL_EMODE_SHIFT 4
mbed_official 146:f64d43ff0c18 10816 #define SDHC_PROCTL_EMODE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_EMODE_SHIFT))&SDHC_PROCTL_EMODE_MASK)
mbed_official 146:f64d43ff0c18 10817 #define SDHC_PROCTL_CDTL_MASK 0x40u
mbed_official 146:f64d43ff0c18 10818 #define SDHC_PROCTL_CDTL_SHIFT 6
mbed_official 146:f64d43ff0c18 10819 #define SDHC_PROCTL_CDSS_MASK 0x80u
mbed_official 146:f64d43ff0c18 10820 #define SDHC_PROCTL_CDSS_SHIFT 7
mbed_official 146:f64d43ff0c18 10821 #define SDHC_PROCTL_DMAS_MASK 0x300u
mbed_official 146:f64d43ff0c18 10822 #define SDHC_PROCTL_DMAS_SHIFT 8
mbed_official 146:f64d43ff0c18 10823 #define SDHC_PROCTL_DMAS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DMAS_SHIFT))&SDHC_PROCTL_DMAS_MASK)
mbed_official 146:f64d43ff0c18 10824 #define SDHC_PROCTL_SABGREQ_MASK 0x10000u
mbed_official 146:f64d43ff0c18 10825 #define SDHC_PROCTL_SABGREQ_SHIFT 16
mbed_official 146:f64d43ff0c18 10826 #define SDHC_PROCTL_CREQ_MASK 0x20000u
mbed_official 146:f64d43ff0c18 10827 #define SDHC_PROCTL_CREQ_SHIFT 17
mbed_official 146:f64d43ff0c18 10828 #define SDHC_PROCTL_RWCTL_MASK 0x40000u
mbed_official 146:f64d43ff0c18 10829 #define SDHC_PROCTL_RWCTL_SHIFT 18
mbed_official 146:f64d43ff0c18 10830 #define SDHC_PROCTL_IABG_MASK 0x80000u
mbed_official 146:f64d43ff0c18 10831 #define SDHC_PROCTL_IABG_SHIFT 19
mbed_official 146:f64d43ff0c18 10832 #define SDHC_PROCTL_WECINT_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 10833 #define SDHC_PROCTL_WECINT_SHIFT 24
mbed_official 146:f64d43ff0c18 10834 #define SDHC_PROCTL_WECINS_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 10835 #define SDHC_PROCTL_WECINS_SHIFT 25
mbed_official 146:f64d43ff0c18 10836 #define SDHC_PROCTL_WECRM_MASK 0x4000000u
mbed_official 146:f64d43ff0c18 10837 #define SDHC_PROCTL_WECRM_SHIFT 26
mbed_official 146:f64d43ff0c18 10838 /* SYSCTL Bit Fields */
mbed_official 146:f64d43ff0c18 10839 #define SDHC_SYSCTL_IPGEN_MASK 0x1u
mbed_official 146:f64d43ff0c18 10840 #define SDHC_SYSCTL_IPGEN_SHIFT 0
mbed_official 146:f64d43ff0c18 10841 #define SDHC_SYSCTL_HCKEN_MASK 0x2u
mbed_official 146:f64d43ff0c18 10842 #define SDHC_SYSCTL_HCKEN_SHIFT 1
mbed_official 146:f64d43ff0c18 10843 #define SDHC_SYSCTL_PEREN_MASK 0x4u
mbed_official 146:f64d43ff0c18 10844 #define SDHC_SYSCTL_PEREN_SHIFT 2
mbed_official 146:f64d43ff0c18 10845 #define SDHC_SYSCTL_SDCLKEN_MASK 0x8u
mbed_official 146:f64d43ff0c18 10846 #define SDHC_SYSCTL_SDCLKEN_SHIFT 3
mbed_official 146:f64d43ff0c18 10847 #define SDHC_SYSCTL_DVS_MASK 0xF0u
mbed_official 146:f64d43ff0c18 10848 #define SDHC_SYSCTL_DVS_SHIFT 4
mbed_official 146:f64d43ff0c18 10849 #define SDHC_SYSCTL_DVS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DVS_SHIFT))&SDHC_SYSCTL_DVS_MASK)
mbed_official 146:f64d43ff0c18 10850 #define SDHC_SYSCTL_SDCLKFS_MASK 0xFF00u
mbed_official 146:f64d43ff0c18 10851 #define SDHC_SYSCTL_SDCLKFS_SHIFT 8
mbed_official 146:f64d43ff0c18 10852 #define SDHC_SYSCTL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_SDCLKFS_SHIFT))&SDHC_SYSCTL_SDCLKFS_MASK)
mbed_official 146:f64d43ff0c18 10853 #define SDHC_SYSCTL_DTOCV_MASK 0xF0000u
mbed_official 146:f64d43ff0c18 10854 #define SDHC_SYSCTL_DTOCV_SHIFT 16
mbed_official 146:f64d43ff0c18 10855 #define SDHC_SYSCTL_DTOCV(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DTOCV_SHIFT))&SDHC_SYSCTL_DTOCV_MASK)
mbed_official 146:f64d43ff0c18 10856 #define SDHC_SYSCTL_RSTA_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 10857 #define SDHC_SYSCTL_RSTA_SHIFT 24
mbed_official 146:f64d43ff0c18 10858 #define SDHC_SYSCTL_RSTC_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 10859 #define SDHC_SYSCTL_RSTC_SHIFT 25
mbed_official 146:f64d43ff0c18 10860 #define SDHC_SYSCTL_RSTD_MASK 0x4000000u
mbed_official 146:f64d43ff0c18 10861 #define SDHC_SYSCTL_RSTD_SHIFT 26
mbed_official 146:f64d43ff0c18 10862 #define SDHC_SYSCTL_INITA_MASK 0x8000000u
mbed_official 146:f64d43ff0c18 10863 #define SDHC_SYSCTL_INITA_SHIFT 27
mbed_official 146:f64d43ff0c18 10864 /* IRQSTAT Bit Fields */
mbed_official 146:f64d43ff0c18 10865 #define SDHC_IRQSTAT_CC_MASK 0x1u
mbed_official 146:f64d43ff0c18 10866 #define SDHC_IRQSTAT_CC_SHIFT 0
mbed_official 146:f64d43ff0c18 10867 #define SDHC_IRQSTAT_TC_MASK 0x2u
mbed_official 146:f64d43ff0c18 10868 #define SDHC_IRQSTAT_TC_SHIFT 1
mbed_official 146:f64d43ff0c18 10869 #define SDHC_IRQSTAT_BGE_MASK 0x4u
mbed_official 146:f64d43ff0c18 10870 #define SDHC_IRQSTAT_BGE_SHIFT 2
mbed_official 146:f64d43ff0c18 10871 #define SDHC_IRQSTAT_DINT_MASK 0x8u
mbed_official 146:f64d43ff0c18 10872 #define SDHC_IRQSTAT_DINT_SHIFT 3
mbed_official 146:f64d43ff0c18 10873 #define SDHC_IRQSTAT_BWR_MASK 0x10u
mbed_official 146:f64d43ff0c18 10874 #define SDHC_IRQSTAT_BWR_SHIFT 4
mbed_official 146:f64d43ff0c18 10875 #define SDHC_IRQSTAT_BRR_MASK 0x20u
mbed_official 146:f64d43ff0c18 10876 #define SDHC_IRQSTAT_BRR_SHIFT 5
mbed_official 146:f64d43ff0c18 10877 #define SDHC_IRQSTAT_CINS_MASK 0x40u
mbed_official 146:f64d43ff0c18 10878 #define SDHC_IRQSTAT_CINS_SHIFT 6
mbed_official 146:f64d43ff0c18 10879 #define SDHC_IRQSTAT_CRM_MASK 0x80u
mbed_official 146:f64d43ff0c18 10880 #define SDHC_IRQSTAT_CRM_SHIFT 7
mbed_official 146:f64d43ff0c18 10881 #define SDHC_IRQSTAT_CINT_MASK 0x100u
mbed_official 146:f64d43ff0c18 10882 #define SDHC_IRQSTAT_CINT_SHIFT 8
mbed_official 146:f64d43ff0c18 10883 #define SDHC_IRQSTAT_CTOE_MASK 0x10000u
mbed_official 146:f64d43ff0c18 10884 #define SDHC_IRQSTAT_CTOE_SHIFT 16
mbed_official 146:f64d43ff0c18 10885 #define SDHC_IRQSTAT_CCE_MASK 0x20000u
mbed_official 146:f64d43ff0c18 10886 #define SDHC_IRQSTAT_CCE_SHIFT 17
mbed_official 146:f64d43ff0c18 10887 #define SDHC_IRQSTAT_CEBE_MASK 0x40000u
mbed_official 146:f64d43ff0c18 10888 #define SDHC_IRQSTAT_CEBE_SHIFT 18
mbed_official 146:f64d43ff0c18 10889 #define SDHC_IRQSTAT_CIE_MASK 0x80000u
mbed_official 146:f64d43ff0c18 10890 #define SDHC_IRQSTAT_CIE_SHIFT 19
mbed_official 146:f64d43ff0c18 10891 #define SDHC_IRQSTAT_DTOE_MASK 0x100000u
mbed_official 146:f64d43ff0c18 10892 #define SDHC_IRQSTAT_DTOE_SHIFT 20
mbed_official 146:f64d43ff0c18 10893 #define SDHC_IRQSTAT_DCE_MASK 0x200000u
mbed_official 146:f64d43ff0c18 10894 #define SDHC_IRQSTAT_DCE_SHIFT 21
mbed_official 146:f64d43ff0c18 10895 #define SDHC_IRQSTAT_DEBE_MASK 0x400000u
mbed_official 146:f64d43ff0c18 10896 #define SDHC_IRQSTAT_DEBE_SHIFT 22
mbed_official 146:f64d43ff0c18 10897 #define SDHC_IRQSTAT_AC12E_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 10898 #define SDHC_IRQSTAT_AC12E_SHIFT 24
mbed_official 146:f64d43ff0c18 10899 #define SDHC_IRQSTAT_DMAE_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 10900 #define SDHC_IRQSTAT_DMAE_SHIFT 28
mbed_official 146:f64d43ff0c18 10901 /* IRQSTATEN Bit Fields */
mbed_official 146:f64d43ff0c18 10902 #define SDHC_IRQSTATEN_CCSEN_MASK 0x1u
mbed_official 146:f64d43ff0c18 10903 #define SDHC_IRQSTATEN_CCSEN_SHIFT 0
mbed_official 146:f64d43ff0c18 10904 #define SDHC_IRQSTATEN_TCSEN_MASK 0x2u
mbed_official 146:f64d43ff0c18 10905 #define SDHC_IRQSTATEN_TCSEN_SHIFT 1
mbed_official 146:f64d43ff0c18 10906 #define SDHC_IRQSTATEN_BGESEN_MASK 0x4u
mbed_official 146:f64d43ff0c18 10907 #define SDHC_IRQSTATEN_BGESEN_SHIFT 2
mbed_official 146:f64d43ff0c18 10908 #define SDHC_IRQSTATEN_DINTSEN_MASK 0x8u
mbed_official 146:f64d43ff0c18 10909 #define SDHC_IRQSTATEN_DINTSEN_SHIFT 3
mbed_official 146:f64d43ff0c18 10910 #define SDHC_IRQSTATEN_BWRSEN_MASK 0x10u
mbed_official 146:f64d43ff0c18 10911 #define SDHC_IRQSTATEN_BWRSEN_SHIFT 4
mbed_official 146:f64d43ff0c18 10912 #define SDHC_IRQSTATEN_BRRSEN_MASK 0x20u
mbed_official 146:f64d43ff0c18 10913 #define SDHC_IRQSTATEN_BRRSEN_SHIFT 5
mbed_official 146:f64d43ff0c18 10914 #define SDHC_IRQSTATEN_CINSEN_MASK 0x40u
mbed_official 146:f64d43ff0c18 10915 #define SDHC_IRQSTATEN_CINSEN_SHIFT 6
mbed_official 146:f64d43ff0c18 10916 #define SDHC_IRQSTATEN_CRMSEN_MASK 0x80u
mbed_official 146:f64d43ff0c18 10917 #define SDHC_IRQSTATEN_CRMSEN_SHIFT 7
mbed_official 146:f64d43ff0c18 10918 #define SDHC_IRQSTATEN_CINTSEN_MASK 0x100u
mbed_official 146:f64d43ff0c18 10919 #define SDHC_IRQSTATEN_CINTSEN_SHIFT 8
mbed_official 146:f64d43ff0c18 10920 #define SDHC_IRQSTATEN_CTOESEN_MASK 0x10000u
mbed_official 146:f64d43ff0c18 10921 #define SDHC_IRQSTATEN_CTOESEN_SHIFT 16
mbed_official 146:f64d43ff0c18 10922 #define SDHC_IRQSTATEN_CCESEN_MASK 0x20000u
mbed_official 146:f64d43ff0c18 10923 #define SDHC_IRQSTATEN_CCESEN_SHIFT 17
mbed_official 146:f64d43ff0c18 10924 #define SDHC_IRQSTATEN_CEBESEN_MASK 0x40000u
mbed_official 146:f64d43ff0c18 10925 #define SDHC_IRQSTATEN_CEBESEN_SHIFT 18
mbed_official 146:f64d43ff0c18 10926 #define SDHC_IRQSTATEN_CIESEN_MASK 0x80000u
mbed_official 146:f64d43ff0c18 10927 #define SDHC_IRQSTATEN_CIESEN_SHIFT 19
mbed_official 146:f64d43ff0c18 10928 #define SDHC_IRQSTATEN_DTOESEN_MASK 0x100000u
mbed_official 146:f64d43ff0c18 10929 #define SDHC_IRQSTATEN_DTOESEN_SHIFT 20
mbed_official 146:f64d43ff0c18 10930 #define SDHC_IRQSTATEN_DCESEN_MASK 0x200000u
mbed_official 146:f64d43ff0c18 10931 #define SDHC_IRQSTATEN_DCESEN_SHIFT 21
mbed_official 146:f64d43ff0c18 10932 #define SDHC_IRQSTATEN_DEBESEN_MASK 0x400000u
mbed_official 146:f64d43ff0c18 10933 #define SDHC_IRQSTATEN_DEBESEN_SHIFT 22
mbed_official 146:f64d43ff0c18 10934 #define SDHC_IRQSTATEN_AC12ESEN_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 10935 #define SDHC_IRQSTATEN_AC12ESEN_SHIFT 24
mbed_official 146:f64d43ff0c18 10936 #define SDHC_IRQSTATEN_DMAESEN_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 10937 #define SDHC_IRQSTATEN_DMAESEN_SHIFT 28
mbed_official 146:f64d43ff0c18 10938 /* IRQSIGEN Bit Fields */
mbed_official 146:f64d43ff0c18 10939 #define SDHC_IRQSIGEN_CCIEN_MASK 0x1u
mbed_official 146:f64d43ff0c18 10940 #define SDHC_IRQSIGEN_CCIEN_SHIFT 0
mbed_official 146:f64d43ff0c18 10941 #define SDHC_IRQSIGEN_TCIEN_MASK 0x2u
mbed_official 146:f64d43ff0c18 10942 #define SDHC_IRQSIGEN_TCIEN_SHIFT 1
mbed_official 146:f64d43ff0c18 10943 #define SDHC_IRQSIGEN_BGEIEN_MASK 0x4u
mbed_official 146:f64d43ff0c18 10944 #define SDHC_IRQSIGEN_BGEIEN_SHIFT 2
mbed_official 146:f64d43ff0c18 10945 #define SDHC_IRQSIGEN_DINTIEN_MASK 0x8u
mbed_official 146:f64d43ff0c18 10946 #define SDHC_IRQSIGEN_DINTIEN_SHIFT 3
mbed_official 146:f64d43ff0c18 10947 #define SDHC_IRQSIGEN_BWRIEN_MASK 0x10u
mbed_official 146:f64d43ff0c18 10948 #define SDHC_IRQSIGEN_BWRIEN_SHIFT 4
mbed_official 146:f64d43ff0c18 10949 #define SDHC_IRQSIGEN_BRRIEN_MASK 0x20u
mbed_official 146:f64d43ff0c18 10950 #define SDHC_IRQSIGEN_BRRIEN_SHIFT 5
mbed_official 146:f64d43ff0c18 10951 #define SDHC_IRQSIGEN_CINSIEN_MASK 0x40u
mbed_official 146:f64d43ff0c18 10952 #define SDHC_IRQSIGEN_CINSIEN_SHIFT 6
mbed_official 146:f64d43ff0c18 10953 #define SDHC_IRQSIGEN_CRMIEN_MASK 0x80u
mbed_official 146:f64d43ff0c18 10954 #define SDHC_IRQSIGEN_CRMIEN_SHIFT 7
mbed_official 146:f64d43ff0c18 10955 #define SDHC_IRQSIGEN_CINTIEN_MASK 0x100u
mbed_official 146:f64d43ff0c18 10956 #define SDHC_IRQSIGEN_CINTIEN_SHIFT 8
mbed_official 146:f64d43ff0c18 10957 #define SDHC_IRQSIGEN_CTOEIEN_MASK 0x10000u
mbed_official 146:f64d43ff0c18 10958 #define SDHC_IRQSIGEN_CTOEIEN_SHIFT 16
mbed_official 146:f64d43ff0c18 10959 #define SDHC_IRQSIGEN_CCEIEN_MASK 0x20000u
mbed_official 146:f64d43ff0c18 10960 #define SDHC_IRQSIGEN_CCEIEN_SHIFT 17
mbed_official 146:f64d43ff0c18 10961 #define SDHC_IRQSIGEN_CEBEIEN_MASK 0x40000u
mbed_official 146:f64d43ff0c18 10962 #define SDHC_IRQSIGEN_CEBEIEN_SHIFT 18
mbed_official 146:f64d43ff0c18 10963 #define SDHC_IRQSIGEN_CIEIEN_MASK 0x80000u
mbed_official 146:f64d43ff0c18 10964 #define SDHC_IRQSIGEN_CIEIEN_SHIFT 19
mbed_official 146:f64d43ff0c18 10965 #define SDHC_IRQSIGEN_DTOEIEN_MASK 0x100000u
mbed_official 146:f64d43ff0c18 10966 #define SDHC_IRQSIGEN_DTOEIEN_SHIFT 20
mbed_official 146:f64d43ff0c18 10967 #define SDHC_IRQSIGEN_DCEIEN_MASK 0x200000u
mbed_official 146:f64d43ff0c18 10968 #define SDHC_IRQSIGEN_DCEIEN_SHIFT 21
mbed_official 146:f64d43ff0c18 10969 #define SDHC_IRQSIGEN_DEBEIEN_MASK 0x400000u
mbed_official 146:f64d43ff0c18 10970 #define SDHC_IRQSIGEN_DEBEIEN_SHIFT 22
mbed_official 146:f64d43ff0c18 10971 #define SDHC_IRQSIGEN_AC12EIEN_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 10972 #define SDHC_IRQSIGEN_AC12EIEN_SHIFT 24
mbed_official 146:f64d43ff0c18 10973 #define SDHC_IRQSIGEN_DMAEIEN_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 10974 #define SDHC_IRQSIGEN_DMAEIEN_SHIFT 28
mbed_official 146:f64d43ff0c18 10975 /* AC12ERR Bit Fields */
mbed_official 146:f64d43ff0c18 10976 #define SDHC_AC12ERR_AC12NE_MASK 0x1u
mbed_official 146:f64d43ff0c18 10977 #define SDHC_AC12ERR_AC12NE_SHIFT 0
mbed_official 146:f64d43ff0c18 10978 #define SDHC_AC12ERR_AC12TOE_MASK 0x2u
mbed_official 146:f64d43ff0c18 10979 #define SDHC_AC12ERR_AC12TOE_SHIFT 1
mbed_official 146:f64d43ff0c18 10980 #define SDHC_AC12ERR_AC12EBE_MASK 0x4u
mbed_official 146:f64d43ff0c18 10981 #define SDHC_AC12ERR_AC12EBE_SHIFT 2
mbed_official 146:f64d43ff0c18 10982 #define SDHC_AC12ERR_AC12CE_MASK 0x8u
mbed_official 146:f64d43ff0c18 10983 #define SDHC_AC12ERR_AC12CE_SHIFT 3
mbed_official 146:f64d43ff0c18 10984 #define SDHC_AC12ERR_AC12IE_MASK 0x10u
mbed_official 146:f64d43ff0c18 10985 #define SDHC_AC12ERR_AC12IE_SHIFT 4
mbed_official 146:f64d43ff0c18 10986 #define SDHC_AC12ERR_CNIBAC12E_MASK 0x80u
mbed_official 146:f64d43ff0c18 10987 #define SDHC_AC12ERR_CNIBAC12E_SHIFT 7
mbed_official 146:f64d43ff0c18 10988 /* HTCAPBLT Bit Fields */
mbed_official 146:f64d43ff0c18 10989 #define SDHC_HTCAPBLT_MBL_MASK 0x70000u
mbed_official 146:f64d43ff0c18 10990 #define SDHC_HTCAPBLT_MBL_SHIFT 16
mbed_official 146:f64d43ff0c18 10991 #define SDHC_HTCAPBLT_MBL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_MBL_SHIFT))&SDHC_HTCAPBLT_MBL_MASK)
mbed_official 146:f64d43ff0c18 10992 #define SDHC_HTCAPBLT_ADMAS_MASK 0x100000u
mbed_official 146:f64d43ff0c18 10993 #define SDHC_HTCAPBLT_ADMAS_SHIFT 20
mbed_official 146:f64d43ff0c18 10994 #define SDHC_HTCAPBLT_HSS_MASK 0x200000u
mbed_official 146:f64d43ff0c18 10995 #define SDHC_HTCAPBLT_HSS_SHIFT 21
mbed_official 146:f64d43ff0c18 10996 #define SDHC_HTCAPBLT_DMAS_MASK 0x400000u
mbed_official 146:f64d43ff0c18 10997 #define SDHC_HTCAPBLT_DMAS_SHIFT 22
mbed_official 146:f64d43ff0c18 10998 #define SDHC_HTCAPBLT_SRS_MASK 0x800000u
mbed_official 146:f64d43ff0c18 10999 #define SDHC_HTCAPBLT_SRS_SHIFT 23
mbed_official 146:f64d43ff0c18 11000 #define SDHC_HTCAPBLT_VS33_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 11001 #define SDHC_HTCAPBLT_VS33_SHIFT 24
mbed_official 146:f64d43ff0c18 11002 /* WML Bit Fields */
mbed_official 146:f64d43ff0c18 11003 #define SDHC_WML_RDWML_MASK 0xFFu
mbed_official 146:f64d43ff0c18 11004 #define SDHC_WML_RDWML_SHIFT 0
mbed_official 146:f64d43ff0c18 11005 #define SDHC_WML_RDWML(x) (((uint32_t)(((uint32_t)(x))<<SDHC_WML_RDWML_SHIFT))&SDHC_WML_RDWML_MASK)
mbed_official 146:f64d43ff0c18 11006 #define SDHC_WML_WRWML_MASK 0xFF0000u
mbed_official 146:f64d43ff0c18 11007 #define SDHC_WML_WRWML_SHIFT 16
mbed_official 146:f64d43ff0c18 11008 #define SDHC_WML_WRWML(x) (((uint32_t)(((uint32_t)(x))<<SDHC_WML_WRWML_SHIFT))&SDHC_WML_WRWML_MASK)
mbed_official 146:f64d43ff0c18 11009 /* FEVT Bit Fields */
mbed_official 146:f64d43ff0c18 11010 #define SDHC_FEVT_AC12NE_MASK 0x1u
mbed_official 146:f64d43ff0c18 11011 #define SDHC_FEVT_AC12NE_SHIFT 0
mbed_official 146:f64d43ff0c18 11012 #define SDHC_FEVT_AC12TOE_MASK 0x2u
mbed_official 146:f64d43ff0c18 11013 #define SDHC_FEVT_AC12TOE_SHIFT 1
mbed_official 146:f64d43ff0c18 11014 #define SDHC_FEVT_AC12CE_MASK 0x4u
mbed_official 146:f64d43ff0c18 11015 #define SDHC_FEVT_AC12CE_SHIFT 2
mbed_official 146:f64d43ff0c18 11016 #define SDHC_FEVT_AC12EBE_MASK 0x8u
mbed_official 146:f64d43ff0c18 11017 #define SDHC_FEVT_AC12EBE_SHIFT 3
mbed_official 146:f64d43ff0c18 11018 #define SDHC_FEVT_AC12IE_MASK 0x10u
mbed_official 146:f64d43ff0c18 11019 #define SDHC_FEVT_AC12IE_SHIFT 4
mbed_official 146:f64d43ff0c18 11020 #define SDHC_FEVT_CNIBAC12E_MASK 0x80u
mbed_official 146:f64d43ff0c18 11021 #define SDHC_FEVT_CNIBAC12E_SHIFT 7
mbed_official 146:f64d43ff0c18 11022 #define SDHC_FEVT_CTOE_MASK 0x10000u
mbed_official 146:f64d43ff0c18 11023 #define SDHC_FEVT_CTOE_SHIFT 16
mbed_official 146:f64d43ff0c18 11024 #define SDHC_FEVT_CCE_MASK 0x20000u
mbed_official 146:f64d43ff0c18 11025 #define SDHC_FEVT_CCE_SHIFT 17
mbed_official 146:f64d43ff0c18 11026 #define SDHC_FEVT_CEBE_MASK 0x40000u
mbed_official 146:f64d43ff0c18 11027 #define SDHC_FEVT_CEBE_SHIFT 18
mbed_official 146:f64d43ff0c18 11028 #define SDHC_FEVT_CIE_MASK 0x80000u
mbed_official 146:f64d43ff0c18 11029 #define SDHC_FEVT_CIE_SHIFT 19
mbed_official 146:f64d43ff0c18 11030 #define SDHC_FEVT_DTOE_MASK 0x100000u
mbed_official 146:f64d43ff0c18 11031 #define SDHC_FEVT_DTOE_SHIFT 20
mbed_official 146:f64d43ff0c18 11032 #define SDHC_FEVT_DCE_MASK 0x200000u
mbed_official 146:f64d43ff0c18 11033 #define SDHC_FEVT_DCE_SHIFT 21
mbed_official 146:f64d43ff0c18 11034 #define SDHC_FEVT_DEBE_MASK 0x400000u
mbed_official 146:f64d43ff0c18 11035 #define SDHC_FEVT_DEBE_SHIFT 22
mbed_official 146:f64d43ff0c18 11036 #define SDHC_FEVT_AC12E_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 11037 #define SDHC_FEVT_AC12E_SHIFT 24
mbed_official 146:f64d43ff0c18 11038 #define SDHC_FEVT_DMAE_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 11039 #define SDHC_FEVT_DMAE_SHIFT 28
mbed_official 146:f64d43ff0c18 11040 #define SDHC_FEVT_CINT_MASK 0x80000000u
mbed_official 146:f64d43ff0c18 11041 #define SDHC_FEVT_CINT_SHIFT 31
mbed_official 146:f64d43ff0c18 11042 /* ADMAES Bit Fields */
mbed_official 146:f64d43ff0c18 11043 #define SDHC_ADMAES_ADMAES_MASK 0x3u
mbed_official 146:f64d43ff0c18 11044 #define SDHC_ADMAES_ADMAES_SHIFT 0
mbed_official 146:f64d43ff0c18 11045 #define SDHC_ADMAES_ADMAES(x) (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMAES_SHIFT))&SDHC_ADMAES_ADMAES_MASK)
mbed_official 146:f64d43ff0c18 11046 #define SDHC_ADMAES_ADMALME_MASK 0x4u
mbed_official 146:f64d43ff0c18 11047 #define SDHC_ADMAES_ADMALME_SHIFT 2
mbed_official 146:f64d43ff0c18 11048 #define SDHC_ADMAES_ADMADCE_MASK 0x8u
mbed_official 146:f64d43ff0c18 11049 #define SDHC_ADMAES_ADMADCE_SHIFT 3
mbed_official 146:f64d43ff0c18 11050 /* ADSADDR Bit Fields */
mbed_official 146:f64d43ff0c18 11051 #define SDHC_ADSADDR_ADSADDR_MASK 0xFFFFFFFCu
mbed_official 146:f64d43ff0c18 11052 #define SDHC_ADSADDR_ADSADDR_SHIFT 2
mbed_official 146:f64d43ff0c18 11053 #define SDHC_ADSADDR_ADSADDR(x) (((uint32_t)(((uint32_t)(x))<<SDHC_ADSADDR_ADSADDR_SHIFT))&SDHC_ADSADDR_ADSADDR_MASK)
mbed_official 146:f64d43ff0c18 11054 /* VENDOR Bit Fields */
mbed_official 146:f64d43ff0c18 11055 #define SDHC_VENDOR_EXTDMAEN_MASK 0x1u
mbed_official 146:f64d43ff0c18 11056 #define SDHC_VENDOR_EXTDMAEN_SHIFT 0
mbed_official 146:f64d43ff0c18 11057 #define SDHC_VENDOR_EXBLKNU_MASK 0x2u
mbed_official 146:f64d43ff0c18 11058 #define SDHC_VENDOR_EXBLKNU_SHIFT 1
mbed_official 146:f64d43ff0c18 11059 #define SDHC_VENDOR_INTSTVAL_MASK 0xFF0000u
mbed_official 146:f64d43ff0c18 11060 #define SDHC_VENDOR_INTSTVAL_SHIFT 16
mbed_official 146:f64d43ff0c18 11061 #define SDHC_VENDOR_INTSTVAL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_INTSTVAL_SHIFT))&SDHC_VENDOR_INTSTVAL_MASK)
mbed_official 146:f64d43ff0c18 11062 /* MMCBOOT Bit Fields */
mbed_official 146:f64d43ff0c18 11063 #define SDHC_MMCBOOT_DTOCVACK_MASK 0xFu
mbed_official 146:f64d43ff0c18 11064 #define SDHC_MMCBOOT_DTOCVACK_SHIFT 0
mbed_official 146:f64d43ff0c18 11065 #define SDHC_MMCBOOT_DTOCVACK(x) (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_DTOCVACK_SHIFT))&SDHC_MMCBOOT_DTOCVACK_MASK)
mbed_official 146:f64d43ff0c18 11066 #define SDHC_MMCBOOT_BOOTACK_MASK 0x10u
mbed_official 146:f64d43ff0c18 11067 #define SDHC_MMCBOOT_BOOTACK_SHIFT 4
mbed_official 146:f64d43ff0c18 11068 #define SDHC_MMCBOOT_BOOTMODE_MASK 0x20u
mbed_official 146:f64d43ff0c18 11069 #define SDHC_MMCBOOT_BOOTMODE_SHIFT 5
mbed_official 146:f64d43ff0c18 11070 #define SDHC_MMCBOOT_BOOTEN_MASK 0x40u
mbed_official 146:f64d43ff0c18 11071 #define SDHC_MMCBOOT_BOOTEN_SHIFT 6
mbed_official 146:f64d43ff0c18 11072 #define SDHC_MMCBOOT_AUTOSABGEN_MASK 0x80u
mbed_official 146:f64d43ff0c18 11073 #define SDHC_MMCBOOT_AUTOSABGEN_SHIFT 7
mbed_official 146:f64d43ff0c18 11074 #define SDHC_MMCBOOT_BOOTBLKCNT_MASK 0xFFFF0000u
mbed_official 146:f64d43ff0c18 11075 #define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT 16
mbed_official 146:f64d43ff0c18 11076 #define SDHC_MMCBOOT_BOOTBLKCNT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTBLKCNT_SHIFT))&SDHC_MMCBOOT_BOOTBLKCNT_MASK)
mbed_official 146:f64d43ff0c18 11077 /* HOSTVER Bit Fields */
mbed_official 146:f64d43ff0c18 11078 #define SDHC_HOSTVER_SVN_MASK 0xFFu
mbed_official 146:f64d43ff0c18 11079 #define SDHC_HOSTVER_SVN_SHIFT 0
mbed_official 146:f64d43ff0c18 11080 #define SDHC_HOSTVER_SVN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_SVN_SHIFT))&SDHC_HOSTVER_SVN_MASK)
mbed_official 146:f64d43ff0c18 11081 #define SDHC_HOSTVER_VVN_MASK 0xFF00u
mbed_official 146:f64d43ff0c18 11082 #define SDHC_HOSTVER_VVN_SHIFT 8
mbed_official 146:f64d43ff0c18 11083 #define SDHC_HOSTVER_VVN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_VVN_SHIFT))&SDHC_HOSTVER_VVN_MASK)
mbed_official 146:f64d43ff0c18 11084
mbed_official 146:f64d43ff0c18 11085 /*!
mbed_official 146:f64d43ff0c18 11086 * @}
mbed_official 146:f64d43ff0c18 11087 */ /* end of group SDHC_Register_Masks */
mbed_official 146:f64d43ff0c18 11088
mbed_official 146:f64d43ff0c18 11089
mbed_official 146:f64d43ff0c18 11090 /* SDHC - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 11091 /** Peripheral SDHC base address */
mbed_official 146:f64d43ff0c18 11092 #define SDHC_BASE (0x400B1000u)
mbed_official 146:f64d43ff0c18 11093 /** Peripheral SDHC base pointer */
mbed_official 146:f64d43ff0c18 11094 #define SDHC ((SDHC_Type *)SDHC_BASE)
mbed_official 146:f64d43ff0c18 11095 #define SDHC_BASE_PTR (SDHC)
mbed_official 146:f64d43ff0c18 11096 /** Array initializer of SDHC peripheral base pointers */
mbed_official 146:f64d43ff0c18 11097 #define SDHC_BASES { SDHC }
mbed_official 146:f64d43ff0c18 11098
mbed_official 146:f64d43ff0c18 11099 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 11100 -- SDHC - Register accessor macros
mbed_official 146:f64d43ff0c18 11101 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 11102
mbed_official 146:f64d43ff0c18 11103 /*!
mbed_official 146:f64d43ff0c18 11104 * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
mbed_official 146:f64d43ff0c18 11105 * @{
mbed_official 146:f64d43ff0c18 11106 */
mbed_official 146:f64d43ff0c18 11107
mbed_official 146:f64d43ff0c18 11108
mbed_official 146:f64d43ff0c18 11109 /* SDHC - Register instance definitions */
mbed_official 146:f64d43ff0c18 11110 /* SDHC */
mbed_official 146:f64d43ff0c18 11111 #define SDHC_DSADDR SDHC_DSADDR_REG(SDHC)
mbed_official 146:f64d43ff0c18 11112 #define SDHC_BLKATTR SDHC_BLKATTR_REG(SDHC)
mbed_official 146:f64d43ff0c18 11113 #define SDHC_CMDARG SDHC_CMDARG_REG(SDHC)
mbed_official 146:f64d43ff0c18 11114 #define SDHC_XFERTYP SDHC_XFERTYP_REG(SDHC)
mbed_official 146:f64d43ff0c18 11115 #define SDHC_CMDRSP0 SDHC_CMDRSP_REG(SDHC,0)
mbed_official 146:f64d43ff0c18 11116 #define SDHC_CMDRSP1 SDHC_CMDRSP_REG(SDHC,1)
mbed_official 146:f64d43ff0c18 11117 #define SDHC_CMDRSP2 SDHC_CMDRSP_REG(SDHC,2)
mbed_official 146:f64d43ff0c18 11118 #define SDHC_CMDRSP3 SDHC_CMDRSP_REG(SDHC,3)
mbed_official 146:f64d43ff0c18 11119 #define SDHC_DATPORT SDHC_DATPORT_REG(SDHC)
mbed_official 146:f64d43ff0c18 11120 #define SDHC_PRSSTAT SDHC_PRSSTAT_REG(SDHC)
mbed_official 146:f64d43ff0c18 11121 #define SDHC_PROCTL SDHC_PROCTL_REG(SDHC)
mbed_official 146:f64d43ff0c18 11122 #define SDHC_SYSCTL SDHC_SYSCTL_REG(SDHC)
mbed_official 146:f64d43ff0c18 11123 #define SDHC_IRQSTAT SDHC_IRQSTAT_REG(SDHC)
mbed_official 146:f64d43ff0c18 11124 #define SDHC_IRQSTATEN SDHC_IRQSTATEN_REG(SDHC)
mbed_official 146:f64d43ff0c18 11125 #define SDHC_IRQSIGEN SDHC_IRQSIGEN_REG(SDHC)
mbed_official 146:f64d43ff0c18 11126 #define SDHC_AC12ERR SDHC_AC12ERR_REG(SDHC)
mbed_official 146:f64d43ff0c18 11127 #define SDHC_HTCAPBLT SDHC_HTCAPBLT_REG(SDHC)
mbed_official 146:f64d43ff0c18 11128 #define SDHC_WML SDHC_WML_REG(SDHC)
mbed_official 146:f64d43ff0c18 11129 #define SDHC_FEVT SDHC_FEVT_REG(SDHC)
mbed_official 146:f64d43ff0c18 11130 #define SDHC_ADMAES SDHC_ADMAES_REG(SDHC)
mbed_official 146:f64d43ff0c18 11131 #define SDHC_ADSADDR SDHC_ADSADDR_REG(SDHC)
mbed_official 146:f64d43ff0c18 11132 #define SDHC_VENDOR SDHC_VENDOR_REG(SDHC)
mbed_official 146:f64d43ff0c18 11133 #define SDHC_MMCBOOT SDHC_MMCBOOT_REG(SDHC)
mbed_official 146:f64d43ff0c18 11134 #define SDHC_HOSTVER SDHC_HOSTVER_REG(SDHC)
mbed_official 146:f64d43ff0c18 11135
mbed_official 146:f64d43ff0c18 11136 /* SDHC - Register array accessors */
mbed_official 146:f64d43ff0c18 11137 #define SDHC_CMDRSP(index) SDHC_CMDRSP_REG(SDHC,index)
mbed_official 146:f64d43ff0c18 11138
mbed_official 146:f64d43ff0c18 11139 /*!
mbed_official 146:f64d43ff0c18 11140 * @}
mbed_official 146:f64d43ff0c18 11141 */ /* end of group SDHC_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 11142
mbed_official 146:f64d43ff0c18 11143
mbed_official 146:f64d43ff0c18 11144 /*!
mbed_official 146:f64d43ff0c18 11145 * @}
mbed_official 146:f64d43ff0c18 11146 */ /* end of group SDHC_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 11147
mbed_official 146:f64d43ff0c18 11148
mbed_official 146:f64d43ff0c18 11149 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 11150 -- SIM Peripheral Access Layer
mbed_official 146:f64d43ff0c18 11151 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 11152
mbed_official 146:f64d43ff0c18 11153 /*!
mbed_official 146:f64d43ff0c18 11154 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
mbed_official 146:f64d43ff0c18 11155 * @{
mbed_official 146:f64d43ff0c18 11156 */
mbed_official 146:f64d43ff0c18 11157
mbed_official 146:f64d43ff0c18 11158 /** SIM - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 11159 typedef struct {
mbed_official 146:f64d43ff0c18 11160 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
mbed_official 146:f64d43ff0c18 11161 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
mbed_official 146:f64d43ff0c18 11162 uint8_t RESERVED_0[4092];
mbed_official 146:f64d43ff0c18 11163 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
mbed_official 146:f64d43ff0c18 11164 uint8_t RESERVED_1[4];
mbed_official 146:f64d43ff0c18 11165 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
mbed_official 146:f64d43ff0c18 11166 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
mbed_official 146:f64d43ff0c18 11167 uint8_t RESERVED_2[4];
mbed_official 146:f64d43ff0c18 11168 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
mbed_official 146:f64d43ff0c18 11169 uint8_t RESERVED_3[8];
mbed_official 146:f64d43ff0c18 11170 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
mbed_official 146:f64d43ff0c18 11171 __IO uint32_t SCGC1; /**< System Clock Gating Control Register 1, offset: 0x1028 */
mbed_official 146:f64d43ff0c18 11172 __IO uint32_t SCGC2; /**< System Clock Gating Control Register 2, offset: 0x102C */
mbed_official 146:f64d43ff0c18 11173 __IO uint32_t SCGC3; /**< System Clock Gating Control Register 3, offset: 0x1030 */
mbed_official 146:f64d43ff0c18 11174 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
mbed_official 146:f64d43ff0c18 11175 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
mbed_official 146:f64d43ff0c18 11176 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
mbed_official 146:f64d43ff0c18 11177 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
mbed_official 146:f64d43ff0c18 11178 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
mbed_official 146:f64d43ff0c18 11179 __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
mbed_official 146:f64d43ff0c18 11180 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
mbed_official 146:f64d43ff0c18 11181 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
mbed_official 146:f64d43ff0c18 11182 __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
mbed_official 146:f64d43ff0c18 11183 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
mbed_official 146:f64d43ff0c18 11184 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
mbed_official 146:f64d43ff0c18 11185 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
mbed_official 146:f64d43ff0c18 11186 } SIM_Type, *SIM_MemMapPtr;
mbed_official 146:f64d43ff0c18 11187
mbed_official 146:f64d43ff0c18 11188 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 11189 -- SIM - Register accessor macros
mbed_official 146:f64d43ff0c18 11190 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 11191
mbed_official 146:f64d43ff0c18 11192 /*!
mbed_official 146:f64d43ff0c18 11193 * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
mbed_official 146:f64d43ff0c18 11194 * @{
mbed_official 146:f64d43ff0c18 11195 */
mbed_official 146:f64d43ff0c18 11196
mbed_official 146:f64d43ff0c18 11197
mbed_official 146:f64d43ff0c18 11198 /* SIM - Register accessors */
mbed_official 146:f64d43ff0c18 11199 #define SIM_SOPT1_REG(base) ((base)->SOPT1)
mbed_official 146:f64d43ff0c18 11200 #define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG)
mbed_official 146:f64d43ff0c18 11201 #define SIM_SOPT2_REG(base) ((base)->SOPT2)
mbed_official 146:f64d43ff0c18 11202 #define SIM_SOPT4_REG(base) ((base)->SOPT4)
mbed_official 146:f64d43ff0c18 11203 #define SIM_SOPT5_REG(base) ((base)->SOPT5)
mbed_official 146:f64d43ff0c18 11204 #define SIM_SOPT7_REG(base) ((base)->SOPT7)
mbed_official 146:f64d43ff0c18 11205 #define SIM_SDID_REG(base) ((base)->SDID)
mbed_official 146:f64d43ff0c18 11206 #define SIM_SCGC1_REG(base) ((base)->SCGC1)
mbed_official 146:f64d43ff0c18 11207 #define SIM_SCGC2_REG(base) ((base)->SCGC2)
mbed_official 146:f64d43ff0c18 11208 #define SIM_SCGC3_REG(base) ((base)->SCGC3)
mbed_official 146:f64d43ff0c18 11209 #define SIM_SCGC4_REG(base) ((base)->SCGC4)
mbed_official 146:f64d43ff0c18 11210 #define SIM_SCGC5_REG(base) ((base)->SCGC5)
mbed_official 146:f64d43ff0c18 11211 #define SIM_SCGC6_REG(base) ((base)->SCGC6)
mbed_official 146:f64d43ff0c18 11212 #define SIM_SCGC7_REG(base) ((base)->SCGC7)
mbed_official 146:f64d43ff0c18 11213 #define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1)
mbed_official 146:f64d43ff0c18 11214 #define SIM_CLKDIV2_REG(base) ((base)->CLKDIV2)
mbed_official 146:f64d43ff0c18 11215 #define SIM_FCFG1_REG(base) ((base)->FCFG1)
mbed_official 146:f64d43ff0c18 11216 #define SIM_FCFG2_REG(base) ((base)->FCFG2)
mbed_official 146:f64d43ff0c18 11217 #define SIM_UIDH_REG(base) ((base)->UIDH)
mbed_official 146:f64d43ff0c18 11218 #define SIM_UIDMH_REG(base) ((base)->UIDMH)
mbed_official 146:f64d43ff0c18 11219 #define SIM_UIDML_REG(base) ((base)->UIDML)
mbed_official 146:f64d43ff0c18 11220 #define SIM_UIDL_REG(base) ((base)->UIDL)
mbed_official 146:f64d43ff0c18 11221
mbed_official 146:f64d43ff0c18 11222 /*!
mbed_official 146:f64d43ff0c18 11223 * @}
mbed_official 146:f64d43ff0c18 11224 */ /* end of group SIM_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 11225
mbed_official 146:f64d43ff0c18 11226
mbed_official 146:f64d43ff0c18 11227 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 11228 -- SIM Register Masks
mbed_official 146:f64d43ff0c18 11229 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 11230
mbed_official 146:f64d43ff0c18 11231 /*!
mbed_official 146:f64d43ff0c18 11232 * @addtogroup SIM_Register_Masks SIM Register Masks
mbed_official 146:f64d43ff0c18 11233 * @{
mbed_official 146:f64d43ff0c18 11234 */
mbed_official 146:f64d43ff0c18 11235
mbed_official 146:f64d43ff0c18 11236 /* SOPT1 Bit Fields */
mbed_official 146:f64d43ff0c18 11237 #define SIM_SOPT1_RAMSIZE_MASK 0xF000u
mbed_official 146:f64d43ff0c18 11238 #define SIM_SOPT1_RAMSIZE_SHIFT 12
mbed_official 146:f64d43ff0c18 11239 #define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
mbed_official 146:f64d43ff0c18 11240 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
mbed_official 146:f64d43ff0c18 11241 #define SIM_SOPT1_OSC32KSEL_SHIFT 18
mbed_official 146:f64d43ff0c18 11242 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
mbed_official 146:f64d43ff0c18 11243 #define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
mbed_official 146:f64d43ff0c18 11244 #define SIM_SOPT1_USBVSTBY_SHIFT 29
mbed_official 146:f64d43ff0c18 11245 #define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 11246 #define SIM_SOPT1_USBSSTBY_SHIFT 30
mbed_official 146:f64d43ff0c18 11247 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u
mbed_official 146:f64d43ff0c18 11248 #define SIM_SOPT1_USBREGEN_SHIFT 31
mbed_official 146:f64d43ff0c18 11249 /* SOPT1CFG Bit Fields */
mbed_official 146:f64d43ff0c18 11250 #define SIM_SOPT1CFG_URWE_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 11251 #define SIM_SOPT1CFG_URWE_SHIFT 24
mbed_official 146:f64d43ff0c18 11252 #define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 11253 #define SIM_SOPT1CFG_UVSWE_SHIFT 25
mbed_official 146:f64d43ff0c18 11254 #define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
mbed_official 146:f64d43ff0c18 11255 #define SIM_SOPT1CFG_USSWE_SHIFT 26
mbed_official 146:f64d43ff0c18 11256 /* SOPT2 Bit Fields */
mbed_official 146:f64d43ff0c18 11257 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
mbed_official 146:f64d43ff0c18 11258 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
mbed_official 146:f64d43ff0c18 11259 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
mbed_official 146:f64d43ff0c18 11260 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5
mbed_official 146:f64d43ff0c18 11261 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
mbed_official 146:f64d43ff0c18 11262 #define SIM_SOPT2_FBSL_MASK 0x300u
mbed_official 146:f64d43ff0c18 11263 #define SIM_SOPT2_FBSL_SHIFT 8
mbed_official 146:f64d43ff0c18 11264 #define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FBSL_SHIFT))&SIM_SOPT2_FBSL_MASK)
mbed_official 146:f64d43ff0c18 11265 #define SIM_SOPT2_PTD7PAD_MASK 0x800u
mbed_official 146:f64d43ff0c18 11266 #define SIM_SOPT2_PTD7PAD_SHIFT 11
mbed_official 146:f64d43ff0c18 11267 #define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u
mbed_official 146:f64d43ff0c18 11268 #define SIM_SOPT2_TRACECLKSEL_SHIFT 12
mbed_official 146:f64d43ff0c18 11269 #define SIM_SOPT2_PLLFLLSEL_MASK 0x30000u
mbed_official 146:f64d43ff0c18 11270 #define SIM_SOPT2_PLLFLLSEL_SHIFT 16
mbed_official 146:f64d43ff0c18 11271 #define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_PLLFLLSEL_SHIFT))&SIM_SOPT2_PLLFLLSEL_MASK)
mbed_official 146:f64d43ff0c18 11272 #define SIM_SOPT2_USBSRC_MASK 0x40000u
mbed_official 146:f64d43ff0c18 11273 #define SIM_SOPT2_USBSRC_SHIFT 18
mbed_official 146:f64d43ff0c18 11274 #define SIM_SOPT2_RMIISRC_MASK 0x80000u
mbed_official 146:f64d43ff0c18 11275 #define SIM_SOPT2_RMIISRC_SHIFT 19
mbed_official 146:f64d43ff0c18 11276 #define SIM_SOPT2_TIMESRC_MASK 0x300000u
mbed_official 146:f64d43ff0c18 11277 #define SIM_SOPT2_TIMESRC_SHIFT 20
mbed_official 146:f64d43ff0c18 11278 #define SIM_SOPT2_TIMESRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TIMESRC_SHIFT))&SIM_SOPT2_TIMESRC_MASK)
mbed_official 146:f64d43ff0c18 11279 #define SIM_SOPT2_SDHCSRC_MASK 0x30000000u
mbed_official 146:f64d43ff0c18 11280 #define SIM_SOPT2_SDHCSRC_SHIFT 28
mbed_official 146:f64d43ff0c18 11281 #define SIM_SOPT2_SDHCSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_SDHCSRC_SHIFT))&SIM_SOPT2_SDHCSRC_MASK)
mbed_official 146:f64d43ff0c18 11282 /* SOPT4 Bit Fields */
mbed_official 146:f64d43ff0c18 11283 #define SIM_SOPT4_FTM0FLT0_MASK 0x1u
mbed_official 146:f64d43ff0c18 11284 #define SIM_SOPT4_FTM0FLT0_SHIFT 0
mbed_official 146:f64d43ff0c18 11285 #define SIM_SOPT4_FTM0FLT1_MASK 0x2u
mbed_official 146:f64d43ff0c18 11286 #define SIM_SOPT4_FTM0FLT1_SHIFT 1
mbed_official 146:f64d43ff0c18 11287 #define SIM_SOPT4_FTM0FLT2_MASK 0x4u
mbed_official 146:f64d43ff0c18 11288 #define SIM_SOPT4_FTM0FLT2_SHIFT 2
mbed_official 146:f64d43ff0c18 11289 #define SIM_SOPT4_FTM1FLT0_MASK 0x10u
mbed_official 146:f64d43ff0c18 11290 #define SIM_SOPT4_FTM1FLT0_SHIFT 4
mbed_official 146:f64d43ff0c18 11291 #define SIM_SOPT4_FTM2FLT0_MASK 0x100u
mbed_official 146:f64d43ff0c18 11292 #define SIM_SOPT4_FTM2FLT0_SHIFT 8
mbed_official 146:f64d43ff0c18 11293 #define SIM_SOPT4_FTM3FLT0_MASK 0x1000u
mbed_official 146:f64d43ff0c18 11294 #define SIM_SOPT4_FTM3FLT0_SHIFT 12
mbed_official 146:f64d43ff0c18 11295 #define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u
mbed_official 146:f64d43ff0c18 11296 #define SIM_SOPT4_FTM1CH0SRC_SHIFT 18
mbed_official 146:f64d43ff0c18 11297 #define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
mbed_official 146:f64d43ff0c18 11298 #define SIM_SOPT4_FTM2CH0SRC_MASK 0x300000u
mbed_official 146:f64d43ff0c18 11299 #define SIM_SOPT4_FTM2CH0SRC_SHIFT 20
mbed_official 146:f64d43ff0c18 11300 #define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
mbed_official 146:f64d43ff0c18 11301 #define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 11302 #define SIM_SOPT4_FTM0CLKSEL_SHIFT 24
mbed_official 146:f64d43ff0c18 11303 #define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 11304 #define SIM_SOPT4_FTM1CLKSEL_SHIFT 25
mbed_official 146:f64d43ff0c18 11305 #define SIM_SOPT4_FTM2CLKSEL_MASK 0x4000000u
mbed_official 146:f64d43ff0c18 11306 #define SIM_SOPT4_FTM2CLKSEL_SHIFT 26
mbed_official 146:f64d43ff0c18 11307 #define SIM_SOPT4_FTM3CLKSEL_MASK 0x8000000u
mbed_official 146:f64d43ff0c18 11308 #define SIM_SOPT4_FTM3CLKSEL_SHIFT 27
mbed_official 146:f64d43ff0c18 11309 #define SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 11310 #define SIM_SOPT4_FTM0TRG0SRC_SHIFT 28
mbed_official 146:f64d43ff0c18 11311 #define SIM_SOPT4_FTM0TRG1SRC_MASK 0x20000000u
mbed_official 146:f64d43ff0c18 11312 #define SIM_SOPT4_FTM0TRG1SRC_SHIFT 29
mbed_official 146:f64d43ff0c18 11313 #define SIM_SOPT4_FTM3TRG0SRC_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 11314 #define SIM_SOPT4_FTM3TRG0SRC_SHIFT 30
mbed_official 146:f64d43ff0c18 11315 #define SIM_SOPT4_FTM3TRG1SRC_MASK 0x80000000u
mbed_official 146:f64d43ff0c18 11316 #define SIM_SOPT4_FTM3TRG1SRC_SHIFT 31
mbed_official 146:f64d43ff0c18 11317 /* SOPT5 Bit Fields */
mbed_official 146:f64d43ff0c18 11318 #define SIM_SOPT5_UART0TXSRC_MASK 0x3u
mbed_official 146:f64d43ff0c18 11319 #define SIM_SOPT5_UART0TXSRC_SHIFT 0
mbed_official 146:f64d43ff0c18 11320 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
mbed_official 146:f64d43ff0c18 11321 #define SIM_SOPT5_UART0RXSRC_MASK 0xCu
mbed_official 146:f64d43ff0c18 11322 #define SIM_SOPT5_UART0RXSRC_SHIFT 2
mbed_official 146:f64d43ff0c18 11323 #define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
mbed_official 146:f64d43ff0c18 11324 #define SIM_SOPT5_UART1TXSRC_MASK 0x30u
mbed_official 146:f64d43ff0c18 11325 #define SIM_SOPT5_UART1TXSRC_SHIFT 4
mbed_official 146:f64d43ff0c18 11326 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
mbed_official 146:f64d43ff0c18 11327 #define SIM_SOPT5_UART1RXSRC_MASK 0xC0u
mbed_official 146:f64d43ff0c18 11328 #define SIM_SOPT5_UART1RXSRC_SHIFT 6
mbed_official 146:f64d43ff0c18 11329 #define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
mbed_official 146:f64d43ff0c18 11330 /* SOPT7 Bit Fields */
mbed_official 146:f64d43ff0c18 11331 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
mbed_official 146:f64d43ff0c18 11332 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
mbed_official 146:f64d43ff0c18 11333 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
mbed_official 146:f64d43ff0c18 11334 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
mbed_official 146:f64d43ff0c18 11335 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
mbed_official 146:f64d43ff0c18 11336 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
mbed_official 146:f64d43ff0c18 11337 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
mbed_official 146:f64d43ff0c18 11338 #define SIM_SOPT7_ADC1TRGSEL_MASK 0xF00u
mbed_official 146:f64d43ff0c18 11339 #define SIM_SOPT7_ADC1TRGSEL_SHIFT 8
mbed_official 146:f64d43ff0c18 11340 #define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
mbed_official 146:f64d43ff0c18 11341 #define SIM_SOPT7_ADC1PRETRGSEL_MASK 0x1000u
mbed_official 146:f64d43ff0c18 11342 #define SIM_SOPT7_ADC1PRETRGSEL_SHIFT 12
mbed_official 146:f64d43ff0c18 11343 #define SIM_SOPT7_ADC1ALTTRGEN_MASK 0x8000u
mbed_official 146:f64d43ff0c18 11344 #define SIM_SOPT7_ADC1ALTTRGEN_SHIFT 15
mbed_official 146:f64d43ff0c18 11345 /* SDID Bit Fields */
mbed_official 146:f64d43ff0c18 11346 #define SIM_SDID_PINID_MASK 0xFu
mbed_official 146:f64d43ff0c18 11347 #define SIM_SDID_PINID_SHIFT 0
mbed_official 146:f64d43ff0c18 11348 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
mbed_official 146:f64d43ff0c18 11349 #define SIM_SDID_FAMID_MASK 0x70u
mbed_official 146:f64d43ff0c18 11350 #define SIM_SDID_FAMID_SHIFT 4
mbed_official 146:f64d43ff0c18 11351 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
mbed_official 146:f64d43ff0c18 11352 #define SIM_SDID_DIEID_MASK 0xF80u
mbed_official 146:f64d43ff0c18 11353 #define SIM_SDID_DIEID_SHIFT 7
mbed_official 146:f64d43ff0c18 11354 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
mbed_official 146:f64d43ff0c18 11355 #define SIM_SDID_REVID_MASK 0xF000u
mbed_official 146:f64d43ff0c18 11356 #define SIM_SDID_REVID_SHIFT 12
mbed_official 146:f64d43ff0c18 11357 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
mbed_official 146:f64d43ff0c18 11358 #define SIM_SDID_SERIESID_MASK 0xF00000u
mbed_official 146:f64d43ff0c18 11359 #define SIM_SDID_SERIESID_SHIFT 20
mbed_official 146:f64d43ff0c18 11360 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
mbed_official 146:f64d43ff0c18 11361 #define SIM_SDID_SUBFAMID_MASK 0xF000000u
mbed_official 146:f64d43ff0c18 11362 #define SIM_SDID_SUBFAMID_SHIFT 24
mbed_official 146:f64d43ff0c18 11363 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
mbed_official 146:f64d43ff0c18 11364 #define SIM_SDID_FAMILYID_MASK 0xF0000000u
mbed_official 146:f64d43ff0c18 11365 #define SIM_SDID_FAMILYID_SHIFT 28
mbed_official 146:f64d43ff0c18 11366 #define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMILYID_SHIFT))&SIM_SDID_FAMILYID_MASK)
mbed_official 146:f64d43ff0c18 11367 /* SCGC1 Bit Fields */
mbed_official 146:f64d43ff0c18 11368 #define SIM_SCGC1_I2C2_MASK 0x40u
mbed_official 146:f64d43ff0c18 11369 #define SIM_SCGC1_I2C2_SHIFT 6
mbed_official 146:f64d43ff0c18 11370 #define SIM_SCGC1_UART4_MASK 0x400u
mbed_official 146:f64d43ff0c18 11371 #define SIM_SCGC1_UART4_SHIFT 10
mbed_official 146:f64d43ff0c18 11372 #define SIM_SCGC1_UART5_MASK 0x800u
mbed_official 146:f64d43ff0c18 11373 #define SIM_SCGC1_UART5_SHIFT 11
mbed_official 146:f64d43ff0c18 11374 /* SCGC2 Bit Fields */
mbed_official 146:f64d43ff0c18 11375 #define SIM_SCGC2_ENET_MASK 0x1u
mbed_official 146:f64d43ff0c18 11376 #define SIM_SCGC2_ENET_SHIFT 0
mbed_official 146:f64d43ff0c18 11377 #define SIM_SCGC2_DAC0_MASK 0x1000u
mbed_official 146:f64d43ff0c18 11378 #define SIM_SCGC2_DAC0_SHIFT 12
mbed_official 146:f64d43ff0c18 11379 #define SIM_SCGC2_DAC1_MASK 0x2000u
mbed_official 146:f64d43ff0c18 11380 #define SIM_SCGC2_DAC1_SHIFT 13
mbed_official 146:f64d43ff0c18 11381 /* SCGC3 Bit Fields */
mbed_official 146:f64d43ff0c18 11382 #define SIM_SCGC3_RNGA_MASK 0x1u
mbed_official 146:f64d43ff0c18 11383 #define SIM_SCGC3_RNGA_SHIFT 0
mbed_official 146:f64d43ff0c18 11384 #define SIM_SCGC3_SPI2_MASK 0x1000u
mbed_official 146:f64d43ff0c18 11385 #define SIM_SCGC3_SPI2_SHIFT 12
mbed_official 146:f64d43ff0c18 11386 #define SIM_SCGC3_SDHC_MASK 0x20000u
mbed_official 146:f64d43ff0c18 11387 #define SIM_SCGC3_SDHC_SHIFT 17
mbed_official 146:f64d43ff0c18 11388 #define SIM_SCGC3_FTM2_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 11389 #define SIM_SCGC3_FTM2_SHIFT 24
mbed_official 146:f64d43ff0c18 11390 #define SIM_SCGC3_FTM3_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 11391 #define SIM_SCGC3_FTM3_SHIFT 25
mbed_official 146:f64d43ff0c18 11392 #define SIM_SCGC3_ADC1_MASK 0x8000000u
mbed_official 146:f64d43ff0c18 11393 #define SIM_SCGC3_ADC1_SHIFT 27
mbed_official 146:f64d43ff0c18 11394 /* SCGC4 Bit Fields */
mbed_official 146:f64d43ff0c18 11395 #define SIM_SCGC4_EWM_MASK 0x2u
mbed_official 146:f64d43ff0c18 11396 #define SIM_SCGC4_EWM_SHIFT 1
mbed_official 146:f64d43ff0c18 11397 #define SIM_SCGC4_CMT_MASK 0x4u
mbed_official 146:f64d43ff0c18 11398 #define SIM_SCGC4_CMT_SHIFT 2
mbed_official 146:f64d43ff0c18 11399 #define SIM_SCGC4_I2C0_MASK 0x40u
mbed_official 146:f64d43ff0c18 11400 #define SIM_SCGC4_I2C0_SHIFT 6
mbed_official 146:f64d43ff0c18 11401 #define SIM_SCGC4_I2C1_MASK 0x80u
mbed_official 146:f64d43ff0c18 11402 #define SIM_SCGC4_I2C1_SHIFT 7
mbed_official 146:f64d43ff0c18 11403 #define SIM_SCGC4_UART0_MASK 0x400u
mbed_official 146:f64d43ff0c18 11404 #define SIM_SCGC4_UART0_SHIFT 10
mbed_official 146:f64d43ff0c18 11405 #define SIM_SCGC4_UART1_MASK 0x800u
mbed_official 146:f64d43ff0c18 11406 #define SIM_SCGC4_UART1_SHIFT 11
mbed_official 146:f64d43ff0c18 11407 #define SIM_SCGC4_UART2_MASK 0x1000u
mbed_official 146:f64d43ff0c18 11408 #define SIM_SCGC4_UART2_SHIFT 12
mbed_official 146:f64d43ff0c18 11409 #define SIM_SCGC4_UART3_MASK 0x2000u
mbed_official 146:f64d43ff0c18 11410 #define SIM_SCGC4_UART3_SHIFT 13
mbed_official 146:f64d43ff0c18 11411 #define SIM_SCGC4_USBOTG_MASK 0x40000u
mbed_official 146:f64d43ff0c18 11412 #define SIM_SCGC4_USBOTG_SHIFT 18
mbed_official 146:f64d43ff0c18 11413 #define SIM_SCGC4_CMP_MASK 0x80000u
mbed_official 146:f64d43ff0c18 11414 #define SIM_SCGC4_CMP_SHIFT 19
mbed_official 146:f64d43ff0c18 11415 #define SIM_SCGC4_VREF_MASK 0x100000u
mbed_official 146:f64d43ff0c18 11416 #define SIM_SCGC4_VREF_SHIFT 20
mbed_official 146:f64d43ff0c18 11417 /* SCGC5 Bit Fields */
mbed_official 146:f64d43ff0c18 11418 #define SIM_SCGC5_LPTMR_MASK 0x1u
mbed_official 146:f64d43ff0c18 11419 #define SIM_SCGC5_LPTMR_SHIFT 0
mbed_official 146:f64d43ff0c18 11420 #define SIM_SCGC5_PORTA_MASK 0x200u
mbed_official 146:f64d43ff0c18 11421 #define SIM_SCGC5_PORTA_SHIFT 9
mbed_official 146:f64d43ff0c18 11422 #define SIM_SCGC5_PORTB_MASK 0x400u
mbed_official 146:f64d43ff0c18 11423 #define SIM_SCGC5_PORTB_SHIFT 10
mbed_official 146:f64d43ff0c18 11424 #define SIM_SCGC5_PORTC_MASK 0x800u
mbed_official 146:f64d43ff0c18 11425 #define SIM_SCGC5_PORTC_SHIFT 11
mbed_official 146:f64d43ff0c18 11426 #define SIM_SCGC5_PORTD_MASK 0x1000u
mbed_official 146:f64d43ff0c18 11427 #define SIM_SCGC5_PORTD_SHIFT 12
mbed_official 146:f64d43ff0c18 11428 #define SIM_SCGC5_PORTE_MASK 0x2000u
mbed_official 146:f64d43ff0c18 11429 #define SIM_SCGC5_PORTE_SHIFT 13
mbed_official 146:f64d43ff0c18 11430 /* SCGC6 Bit Fields */
mbed_official 146:f64d43ff0c18 11431 #define SIM_SCGC6_FTF_MASK 0x1u
mbed_official 146:f64d43ff0c18 11432 #define SIM_SCGC6_FTF_SHIFT 0
mbed_official 146:f64d43ff0c18 11433 #define SIM_SCGC6_DMAMUX_MASK 0x2u
mbed_official 146:f64d43ff0c18 11434 #define SIM_SCGC6_DMAMUX_SHIFT 1
mbed_official 146:f64d43ff0c18 11435 #define SIM_SCGC6_FLEXCAN0_MASK 0x10u
mbed_official 146:f64d43ff0c18 11436 #define SIM_SCGC6_FLEXCAN0_SHIFT 4
mbed_official 146:f64d43ff0c18 11437 #define SIM_SCGC6_RNGA_MASK 0x200u
mbed_official 146:f64d43ff0c18 11438 #define SIM_SCGC6_RNGA_SHIFT 9
mbed_official 146:f64d43ff0c18 11439 #define SIM_SCGC6_SPI0_MASK 0x1000u
mbed_official 146:f64d43ff0c18 11440 #define SIM_SCGC6_SPI0_SHIFT 12
mbed_official 146:f64d43ff0c18 11441 #define SIM_SCGC6_SPI1_MASK 0x2000u
mbed_official 146:f64d43ff0c18 11442 #define SIM_SCGC6_SPI1_SHIFT 13
mbed_official 146:f64d43ff0c18 11443 #define SIM_SCGC6_I2S_MASK 0x8000u
mbed_official 146:f64d43ff0c18 11444 #define SIM_SCGC6_I2S_SHIFT 15
mbed_official 146:f64d43ff0c18 11445 #define SIM_SCGC6_CRC_MASK 0x40000u
mbed_official 146:f64d43ff0c18 11446 #define SIM_SCGC6_CRC_SHIFT 18
mbed_official 146:f64d43ff0c18 11447 #define SIM_SCGC6_USBDCD_MASK 0x200000u
mbed_official 146:f64d43ff0c18 11448 #define SIM_SCGC6_USBDCD_SHIFT 21
mbed_official 146:f64d43ff0c18 11449 #define SIM_SCGC6_PDB_MASK 0x400000u
mbed_official 146:f64d43ff0c18 11450 #define SIM_SCGC6_PDB_SHIFT 22
mbed_official 146:f64d43ff0c18 11451 #define SIM_SCGC6_PIT_MASK 0x800000u
mbed_official 146:f64d43ff0c18 11452 #define SIM_SCGC6_PIT_SHIFT 23
mbed_official 146:f64d43ff0c18 11453 #define SIM_SCGC6_FTM0_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 11454 #define SIM_SCGC6_FTM0_SHIFT 24
mbed_official 146:f64d43ff0c18 11455 #define SIM_SCGC6_FTM1_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 11456 #define SIM_SCGC6_FTM1_SHIFT 25
mbed_official 146:f64d43ff0c18 11457 #define SIM_SCGC6_FTM2_MASK 0x4000000u
mbed_official 146:f64d43ff0c18 11458 #define SIM_SCGC6_FTM2_SHIFT 26
mbed_official 146:f64d43ff0c18 11459 #define SIM_SCGC6_ADC0_MASK 0x8000000u
mbed_official 146:f64d43ff0c18 11460 #define SIM_SCGC6_ADC0_SHIFT 27
mbed_official 146:f64d43ff0c18 11461 #define SIM_SCGC6_RTC_MASK 0x20000000u
mbed_official 146:f64d43ff0c18 11462 #define SIM_SCGC6_RTC_SHIFT 29
mbed_official 146:f64d43ff0c18 11463 #define SIM_SCGC6_DAC0_MASK 0x80000000u
mbed_official 146:f64d43ff0c18 11464 #define SIM_SCGC6_DAC0_SHIFT 31
mbed_official 146:f64d43ff0c18 11465 /* SCGC7 Bit Fields */
mbed_official 146:f64d43ff0c18 11466 #define SIM_SCGC7_FLEXBUS_MASK 0x1u
mbed_official 146:f64d43ff0c18 11467 #define SIM_SCGC7_FLEXBUS_SHIFT 0
mbed_official 146:f64d43ff0c18 11468 #define SIM_SCGC7_DMA_MASK 0x2u
mbed_official 146:f64d43ff0c18 11469 #define SIM_SCGC7_DMA_SHIFT 1
mbed_official 146:f64d43ff0c18 11470 #define SIM_SCGC7_MPU_MASK 0x4u
mbed_official 146:f64d43ff0c18 11471 #define SIM_SCGC7_MPU_SHIFT 2
mbed_official 146:f64d43ff0c18 11472 /* CLKDIV1 Bit Fields */
mbed_official 146:f64d43ff0c18 11473 #define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u
mbed_official 146:f64d43ff0c18 11474 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16
mbed_official 146:f64d43ff0c18 11475 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
mbed_official 146:f64d43ff0c18 11476 #define SIM_CLKDIV1_OUTDIV3_MASK 0xF00000u
mbed_official 146:f64d43ff0c18 11477 #define SIM_CLKDIV1_OUTDIV3_SHIFT 20
mbed_official 146:f64d43ff0c18 11478 #define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV3_SHIFT))&SIM_CLKDIV1_OUTDIV3_MASK)
mbed_official 146:f64d43ff0c18 11479 #define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u
mbed_official 146:f64d43ff0c18 11480 #define SIM_CLKDIV1_OUTDIV2_SHIFT 24
mbed_official 146:f64d43ff0c18 11481 #define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
mbed_official 146:f64d43ff0c18 11482 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
mbed_official 146:f64d43ff0c18 11483 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28
mbed_official 146:f64d43ff0c18 11484 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
mbed_official 146:f64d43ff0c18 11485 /* CLKDIV2 Bit Fields */
mbed_official 146:f64d43ff0c18 11486 #define SIM_CLKDIV2_USBFRAC_MASK 0x1u
mbed_official 146:f64d43ff0c18 11487 #define SIM_CLKDIV2_USBFRAC_SHIFT 0
mbed_official 146:f64d43ff0c18 11488 #define SIM_CLKDIV2_USBDIV_MASK 0xEu
mbed_official 146:f64d43ff0c18 11489 #define SIM_CLKDIV2_USBDIV_SHIFT 1
mbed_official 146:f64d43ff0c18 11490 #define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
mbed_official 146:f64d43ff0c18 11491 /* FCFG1 Bit Fields */
mbed_official 146:f64d43ff0c18 11492 #define SIM_FCFG1_FLASHDIS_MASK 0x1u
mbed_official 146:f64d43ff0c18 11493 #define SIM_FCFG1_FLASHDIS_SHIFT 0
mbed_official 146:f64d43ff0c18 11494 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u
mbed_official 146:f64d43ff0c18 11495 #define SIM_FCFG1_FLASHDOZE_SHIFT 1
mbed_official 146:f64d43ff0c18 11496 #define SIM_FCFG1_DEPART_MASK 0xF00u
mbed_official 146:f64d43ff0c18 11497 #define SIM_FCFG1_DEPART_SHIFT 8
mbed_official 146:f64d43ff0c18 11498 #define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
mbed_official 146:f64d43ff0c18 11499 #define SIM_FCFG1_EESIZE_MASK 0xF0000u
mbed_official 146:f64d43ff0c18 11500 #define SIM_FCFG1_EESIZE_SHIFT 16
mbed_official 146:f64d43ff0c18 11501 #define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
mbed_official 146:f64d43ff0c18 11502 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u
mbed_official 146:f64d43ff0c18 11503 #define SIM_FCFG1_PFSIZE_SHIFT 24
mbed_official 146:f64d43ff0c18 11504 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
mbed_official 146:f64d43ff0c18 11505 #define SIM_FCFG1_NVMSIZE_MASK 0xF0000000u
mbed_official 146:f64d43ff0c18 11506 #define SIM_FCFG1_NVMSIZE_SHIFT 28
mbed_official 146:f64d43ff0c18 11507 #define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)
mbed_official 146:f64d43ff0c18 11508 /* FCFG2 Bit Fields */
mbed_official 146:f64d43ff0c18 11509 #define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
mbed_official 146:f64d43ff0c18 11510 #define SIM_FCFG2_MAXADDR1_SHIFT 16
mbed_official 146:f64d43ff0c18 11511 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
mbed_official 146:f64d43ff0c18 11512 #define SIM_FCFG2_PFLSH_MASK 0x800000u
mbed_official 146:f64d43ff0c18 11513 #define SIM_FCFG2_PFLSH_SHIFT 23
mbed_official 146:f64d43ff0c18 11514 #define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
mbed_official 146:f64d43ff0c18 11515 #define SIM_FCFG2_MAXADDR0_SHIFT 24
mbed_official 146:f64d43ff0c18 11516 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
mbed_official 146:f64d43ff0c18 11517 /* UIDH Bit Fields */
mbed_official 146:f64d43ff0c18 11518 #define SIM_UIDH_UID_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 11519 #define SIM_UIDH_UID_SHIFT 0
mbed_official 146:f64d43ff0c18 11520 #define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
mbed_official 146:f64d43ff0c18 11521 /* UIDMH Bit Fields */
mbed_official 146:f64d43ff0c18 11522 #define SIM_UIDMH_UID_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 11523 #define SIM_UIDMH_UID_SHIFT 0
mbed_official 146:f64d43ff0c18 11524 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
mbed_official 146:f64d43ff0c18 11525 /* UIDML Bit Fields */
mbed_official 146:f64d43ff0c18 11526 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 11527 #define SIM_UIDML_UID_SHIFT 0
mbed_official 146:f64d43ff0c18 11528 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
mbed_official 146:f64d43ff0c18 11529 /* UIDL Bit Fields */
mbed_official 146:f64d43ff0c18 11530 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 11531 #define SIM_UIDL_UID_SHIFT 0
mbed_official 146:f64d43ff0c18 11532 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
mbed_official 146:f64d43ff0c18 11533
mbed_official 146:f64d43ff0c18 11534 /*!
mbed_official 146:f64d43ff0c18 11535 * @}
mbed_official 146:f64d43ff0c18 11536 */ /* end of group SIM_Register_Masks */
mbed_official 146:f64d43ff0c18 11537
mbed_official 146:f64d43ff0c18 11538
mbed_official 146:f64d43ff0c18 11539 /* SIM - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 11540 /** Peripheral SIM base address */
mbed_official 146:f64d43ff0c18 11541 #define SIM_BASE (0x40047000u)
mbed_official 146:f64d43ff0c18 11542 /** Peripheral SIM base pointer */
mbed_official 146:f64d43ff0c18 11543 #define SIM ((SIM_Type *)SIM_BASE)
mbed_official 146:f64d43ff0c18 11544 #define SIM_BASE_PTR (SIM)
mbed_official 146:f64d43ff0c18 11545 /** Array initializer of SIM peripheral base pointers */
mbed_official 146:f64d43ff0c18 11546 #define SIM_BASES { SIM }
mbed_official 146:f64d43ff0c18 11547
mbed_official 146:f64d43ff0c18 11548 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 11549 -- SIM - Register accessor macros
mbed_official 146:f64d43ff0c18 11550 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 11551
mbed_official 146:f64d43ff0c18 11552 /*!
mbed_official 146:f64d43ff0c18 11553 * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
mbed_official 146:f64d43ff0c18 11554 * @{
mbed_official 146:f64d43ff0c18 11555 */
mbed_official 146:f64d43ff0c18 11556
mbed_official 146:f64d43ff0c18 11557
mbed_official 146:f64d43ff0c18 11558 /* SIM - Register instance definitions */
mbed_official 146:f64d43ff0c18 11559 /* SIM */
mbed_official 146:f64d43ff0c18 11560 #define SIM_SOPT1 SIM_SOPT1_REG(SIM)
mbed_official 146:f64d43ff0c18 11561 #define SIM_SOPT1CFG SIM_SOPT1CFG_REG(SIM)
mbed_official 146:f64d43ff0c18 11562 #define SIM_SOPT2 SIM_SOPT2_REG(SIM)
mbed_official 146:f64d43ff0c18 11563 #define SIM_SOPT4 SIM_SOPT4_REG(SIM)
mbed_official 146:f64d43ff0c18 11564 #define SIM_SOPT5 SIM_SOPT5_REG(SIM)
mbed_official 146:f64d43ff0c18 11565 #define SIM_SOPT7 SIM_SOPT7_REG(SIM)
mbed_official 146:f64d43ff0c18 11566 #define SIM_SDID SIM_SDID_REG(SIM)
mbed_official 146:f64d43ff0c18 11567 #define SIM_SCGC1 SIM_SCGC1_REG(SIM)
mbed_official 146:f64d43ff0c18 11568 #define SIM_SCGC2 SIM_SCGC2_REG(SIM)
mbed_official 146:f64d43ff0c18 11569 #define SIM_SCGC3 SIM_SCGC3_REG(SIM)
mbed_official 146:f64d43ff0c18 11570 #define SIM_SCGC4 SIM_SCGC4_REG(SIM)
mbed_official 146:f64d43ff0c18 11571 #define SIM_SCGC5 SIM_SCGC5_REG(SIM)
mbed_official 146:f64d43ff0c18 11572 #define SIM_SCGC6 SIM_SCGC6_REG(SIM)
mbed_official 146:f64d43ff0c18 11573 #define SIM_SCGC7 SIM_SCGC7_REG(SIM)
mbed_official 146:f64d43ff0c18 11574 #define SIM_CLKDIV1 SIM_CLKDIV1_REG(SIM)
mbed_official 146:f64d43ff0c18 11575 #define SIM_CLKDIV2 SIM_CLKDIV2_REG(SIM)
mbed_official 146:f64d43ff0c18 11576 #define SIM_FCFG1 SIM_FCFG1_REG(SIM)
mbed_official 146:f64d43ff0c18 11577 #define SIM_FCFG2 SIM_FCFG2_REG(SIM)
mbed_official 146:f64d43ff0c18 11578 #define SIM_UIDH SIM_UIDH_REG(SIM)
mbed_official 146:f64d43ff0c18 11579 #define SIM_UIDMH SIM_UIDMH_REG(SIM)
mbed_official 146:f64d43ff0c18 11580 #define SIM_UIDML SIM_UIDML_REG(SIM)
mbed_official 146:f64d43ff0c18 11581 #define SIM_UIDL SIM_UIDL_REG(SIM)
mbed_official 146:f64d43ff0c18 11582
mbed_official 146:f64d43ff0c18 11583 /*!
mbed_official 146:f64d43ff0c18 11584 * @}
mbed_official 146:f64d43ff0c18 11585 */ /* end of group SIM_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 11586
mbed_official 146:f64d43ff0c18 11587
mbed_official 146:f64d43ff0c18 11588 /*!
mbed_official 146:f64d43ff0c18 11589 * @}
mbed_official 146:f64d43ff0c18 11590 */ /* end of group SIM_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 11591
mbed_official 146:f64d43ff0c18 11592
mbed_official 146:f64d43ff0c18 11593 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 11594 -- SMC Peripheral Access Layer
mbed_official 146:f64d43ff0c18 11595 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 11596
mbed_official 146:f64d43ff0c18 11597 /*!
mbed_official 146:f64d43ff0c18 11598 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
mbed_official 146:f64d43ff0c18 11599 * @{
mbed_official 146:f64d43ff0c18 11600 */
mbed_official 146:f64d43ff0c18 11601
mbed_official 146:f64d43ff0c18 11602 /** SMC - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 11603 typedef struct {
mbed_official 146:f64d43ff0c18 11604 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
mbed_official 146:f64d43ff0c18 11605 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
mbed_official 146:f64d43ff0c18 11606 __IO uint8_t VLLSCTRL; /**< VLLS Control register, offset: 0x2 */
mbed_official 146:f64d43ff0c18 11607 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
mbed_official 146:f64d43ff0c18 11608 } SMC_Type, *SMC_MemMapPtr;
mbed_official 146:f64d43ff0c18 11609
mbed_official 146:f64d43ff0c18 11610 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 11611 -- SMC - Register accessor macros
mbed_official 146:f64d43ff0c18 11612 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 11613
mbed_official 146:f64d43ff0c18 11614 /*!
mbed_official 146:f64d43ff0c18 11615 * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
mbed_official 146:f64d43ff0c18 11616 * @{
mbed_official 146:f64d43ff0c18 11617 */
mbed_official 146:f64d43ff0c18 11618
mbed_official 146:f64d43ff0c18 11619
mbed_official 146:f64d43ff0c18 11620 /* SMC - Register accessors */
mbed_official 146:f64d43ff0c18 11621 #define SMC_PMPROT_REG(base) ((base)->PMPROT)
mbed_official 146:f64d43ff0c18 11622 #define SMC_PMCTRL_REG(base) ((base)->PMCTRL)
mbed_official 146:f64d43ff0c18 11623 #define SMC_VLLSCTRL_REG(base) ((base)->VLLSCTRL)
mbed_official 146:f64d43ff0c18 11624 #define SMC_PMSTAT_REG(base) ((base)->PMSTAT)
mbed_official 146:f64d43ff0c18 11625
mbed_official 146:f64d43ff0c18 11626 /*!
mbed_official 146:f64d43ff0c18 11627 * @}
mbed_official 146:f64d43ff0c18 11628 */ /* end of group SMC_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 11629
mbed_official 146:f64d43ff0c18 11630
mbed_official 146:f64d43ff0c18 11631 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 11632 -- SMC Register Masks
mbed_official 146:f64d43ff0c18 11633 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 11634
mbed_official 146:f64d43ff0c18 11635 /*!
mbed_official 146:f64d43ff0c18 11636 * @addtogroup SMC_Register_Masks SMC Register Masks
mbed_official 146:f64d43ff0c18 11637 * @{
mbed_official 146:f64d43ff0c18 11638 */
mbed_official 146:f64d43ff0c18 11639
mbed_official 146:f64d43ff0c18 11640 /* PMPROT Bit Fields */
mbed_official 146:f64d43ff0c18 11641 #define SMC_PMPROT_AVLLS_MASK 0x2u
mbed_official 146:f64d43ff0c18 11642 #define SMC_PMPROT_AVLLS_SHIFT 1
mbed_official 146:f64d43ff0c18 11643 #define SMC_PMPROT_ALLS_MASK 0x8u
mbed_official 146:f64d43ff0c18 11644 #define SMC_PMPROT_ALLS_SHIFT 3
mbed_official 146:f64d43ff0c18 11645 #define SMC_PMPROT_AVLP_MASK 0x20u
mbed_official 146:f64d43ff0c18 11646 #define SMC_PMPROT_AVLP_SHIFT 5
mbed_official 146:f64d43ff0c18 11647 /* PMCTRL Bit Fields */
mbed_official 146:f64d43ff0c18 11648 #define SMC_PMCTRL_STOPM_MASK 0x7u
mbed_official 146:f64d43ff0c18 11649 #define SMC_PMCTRL_STOPM_SHIFT 0
mbed_official 146:f64d43ff0c18 11650 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
mbed_official 146:f64d43ff0c18 11651 #define SMC_PMCTRL_STOPA_MASK 0x8u
mbed_official 146:f64d43ff0c18 11652 #define SMC_PMCTRL_STOPA_SHIFT 3
mbed_official 146:f64d43ff0c18 11653 #define SMC_PMCTRL_RUNM_MASK 0x60u
mbed_official 146:f64d43ff0c18 11654 #define SMC_PMCTRL_RUNM_SHIFT 5
mbed_official 146:f64d43ff0c18 11655 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
mbed_official 146:f64d43ff0c18 11656 #define SMC_PMCTRL_LPWUI_MASK 0x80u
mbed_official 146:f64d43ff0c18 11657 #define SMC_PMCTRL_LPWUI_SHIFT 7
mbed_official 146:f64d43ff0c18 11658 /* VLLSCTRL Bit Fields */
mbed_official 146:f64d43ff0c18 11659 #define SMC_VLLSCTRL_VLLSM_MASK 0x7u
mbed_official 146:f64d43ff0c18 11660 #define SMC_VLLSCTRL_VLLSM_SHIFT 0
mbed_official 146:f64d43ff0c18 11661 #define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK)
mbed_official 146:f64d43ff0c18 11662 #define SMC_VLLSCTRL_PORPO_MASK 0x20u
mbed_official 146:f64d43ff0c18 11663 #define SMC_VLLSCTRL_PORPO_SHIFT 5
mbed_official 146:f64d43ff0c18 11664 /* PMSTAT Bit Fields */
mbed_official 146:f64d43ff0c18 11665 #define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
mbed_official 146:f64d43ff0c18 11666 #define SMC_PMSTAT_PMSTAT_SHIFT 0
mbed_official 146:f64d43ff0c18 11667 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
mbed_official 146:f64d43ff0c18 11668
mbed_official 146:f64d43ff0c18 11669 /*!
mbed_official 146:f64d43ff0c18 11670 * @}
mbed_official 146:f64d43ff0c18 11671 */ /* end of group SMC_Register_Masks */
mbed_official 146:f64d43ff0c18 11672
mbed_official 146:f64d43ff0c18 11673
mbed_official 146:f64d43ff0c18 11674 /* SMC - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 11675 /** Peripheral SMC base address */
mbed_official 146:f64d43ff0c18 11676 #define SMC_BASE (0x4007E000u)
mbed_official 146:f64d43ff0c18 11677 /** Peripheral SMC base pointer */
mbed_official 146:f64d43ff0c18 11678 #define SMC ((SMC_Type *)SMC_BASE)
mbed_official 146:f64d43ff0c18 11679 #define SMC_BASE_PTR (SMC)
mbed_official 146:f64d43ff0c18 11680 /** Array initializer of SMC peripheral base pointers */
mbed_official 146:f64d43ff0c18 11681 #define SMC_BASES { SMC }
mbed_official 146:f64d43ff0c18 11682
mbed_official 146:f64d43ff0c18 11683 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 11684 -- SMC - Register accessor macros
mbed_official 146:f64d43ff0c18 11685 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 11686
mbed_official 146:f64d43ff0c18 11687 /*!
mbed_official 146:f64d43ff0c18 11688 * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
mbed_official 146:f64d43ff0c18 11689 * @{
mbed_official 146:f64d43ff0c18 11690 */
mbed_official 146:f64d43ff0c18 11691
mbed_official 146:f64d43ff0c18 11692
mbed_official 146:f64d43ff0c18 11693 /* SMC - Register instance definitions */
mbed_official 146:f64d43ff0c18 11694 /* SMC */
mbed_official 146:f64d43ff0c18 11695 #define SMC_PMPROT SMC_PMPROT_REG(SMC)
mbed_official 146:f64d43ff0c18 11696 #define SMC_PMCTRL SMC_PMCTRL_REG(SMC)
mbed_official 146:f64d43ff0c18 11697 #define SMC_VLLSCTRL SMC_VLLSCTRL_REG(SMC)
mbed_official 146:f64d43ff0c18 11698 #define SMC_PMSTAT SMC_PMSTAT_REG(SMC)
mbed_official 146:f64d43ff0c18 11699
mbed_official 146:f64d43ff0c18 11700 /*!
mbed_official 146:f64d43ff0c18 11701 * @}
mbed_official 146:f64d43ff0c18 11702 */ /* end of group SMC_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 11703
mbed_official 146:f64d43ff0c18 11704
mbed_official 146:f64d43ff0c18 11705 /*!
mbed_official 146:f64d43ff0c18 11706 * @}
mbed_official 146:f64d43ff0c18 11707 */ /* end of group SMC_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 11708
mbed_official 146:f64d43ff0c18 11709
mbed_official 146:f64d43ff0c18 11710 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 11711 -- SPI Peripheral Access Layer
mbed_official 146:f64d43ff0c18 11712 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 11713
mbed_official 146:f64d43ff0c18 11714 /*!
mbed_official 146:f64d43ff0c18 11715 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
mbed_official 146:f64d43ff0c18 11716 * @{
mbed_official 146:f64d43ff0c18 11717 */
mbed_official 146:f64d43ff0c18 11718
mbed_official 146:f64d43ff0c18 11719 /** SPI - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 11720 typedef struct {
mbed_official 146:f64d43ff0c18 11721 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
mbed_official 146:f64d43ff0c18 11722 uint8_t RESERVED_0[4];
mbed_official 146:f64d43ff0c18 11723 __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */
mbed_official 146:f64d43ff0c18 11724 union { /* offset: 0xC */
mbed_official 146:f64d43ff0c18 11725 __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
mbed_official 146:f64d43ff0c18 11726 __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
mbed_official 146:f64d43ff0c18 11727 };
mbed_official 146:f64d43ff0c18 11728 uint8_t RESERVED_1[24];
mbed_official 146:f64d43ff0c18 11729 __IO uint32_t SR; /**< Status Register, offset: 0x2C */
mbed_official 146:f64d43ff0c18 11730 __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
mbed_official 146:f64d43ff0c18 11731 union { /* offset: 0x34 */
mbed_official 146:f64d43ff0c18 11732 __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
mbed_official 146:f64d43ff0c18 11733 __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
mbed_official 146:f64d43ff0c18 11734 };
mbed_official 146:f64d43ff0c18 11735 __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */
mbed_official 146:f64d43ff0c18 11736 __I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */
mbed_official 146:f64d43ff0c18 11737 __I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */
mbed_official 146:f64d43ff0c18 11738 __I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */
mbed_official 146:f64d43ff0c18 11739 __I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */
mbed_official 146:f64d43ff0c18 11740 uint8_t RESERVED_2[48];
mbed_official 146:f64d43ff0c18 11741 __I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */
mbed_official 146:f64d43ff0c18 11742 __I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */
mbed_official 146:f64d43ff0c18 11743 __I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */
mbed_official 146:f64d43ff0c18 11744 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */
mbed_official 146:f64d43ff0c18 11745 } SPI_Type, *SPI_MemMapPtr;
mbed_official 146:f64d43ff0c18 11746
mbed_official 146:f64d43ff0c18 11747 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 11748 -- SPI - Register accessor macros
mbed_official 146:f64d43ff0c18 11749 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 11750
mbed_official 146:f64d43ff0c18 11751 /*!
mbed_official 146:f64d43ff0c18 11752 * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
mbed_official 146:f64d43ff0c18 11753 * @{
mbed_official 146:f64d43ff0c18 11754 */
mbed_official 146:f64d43ff0c18 11755
mbed_official 146:f64d43ff0c18 11756
mbed_official 146:f64d43ff0c18 11757 /* SPI - Register accessors */
mbed_official 146:f64d43ff0c18 11758 #define SPI_MCR_REG(base) ((base)->MCR)
mbed_official 146:f64d43ff0c18 11759 #define SPI_TCR_REG(base) ((base)->TCR)
mbed_official 146:f64d43ff0c18 11760 #define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2])
mbed_official 146:f64d43ff0c18 11761 #define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2])
mbed_official 146:f64d43ff0c18 11762 #define SPI_SR_REG(base) ((base)->SR)
mbed_official 146:f64d43ff0c18 11763 #define SPI_RSER_REG(base) ((base)->RSER)
mbed_official 146:f64d43ff0c18 11764 #define SPI_PUSHR_REG(base) ((base)->PUSHR)
mbed_official 146:f64d43ff0c18 11765 #define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE)
mbed_official 146:f64d43ff0c18 11766 #define SPI_POPR_REG(base) ((base)->POPR)
mbed_official 146:f64d43ff0c18 11767 #define SPI_TXFR0_REG(base) ((base)->TXFR0)
mbed_official 146:f64d43ff0c18 11768 #define SPI_TXFR1_REG(base) ((base)->TXFR1)
mbed_official 146:f64d43ff0c18 11769 #define SPI_TXFR2_REG(base) ((base)->TXFR2)
mbed_official 146:f64d43ff0c18 11770 #define SPI_TXFR3_REG(base) ((base)->TXFR3)
mbed_official 146:f64d43ff0c18 11771 #define SPI_RXFR0_REG(base) ((base)->RXFR0)
mbed_official 146:f64d43ff0c18 11772 #define SPI_RXFR1_REG(base) ((base)->RXFR1)
mbed_official 146:f64d43ff0c18 11773 #define SPI_RXFR2_REG(base) ((base)->RXFR2)
mbed_official 146:f64d43ff0c18 11774 #define SPI_RXFR3_REG(base) ((base)->RXFR3)
mbed_official 146:f64d43ff0c18 11775
mbed_official 146:f64d43ff0c18 11776 /*!
mbed_official 146:f64d43ff0c18 11777 * @}
mbed_official 146:f64d43ff0c18 11778 */ /* end of group SPI_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 11779
mbed_official 146:f64d43ff0c18 11780
mbed_official 146:f64d43ff0c18 11781 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 11782 -- SPI Register Masks
mbed_official 146:f64d43ff0c18 11783 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 11784
mbed_official 146:f64d43ff0c18 11785 /*!
mbed_official 146:f64d43ff0c18 11786 * @addtogroup SPI_Register_Masks SPI Register Masks
mbed_official 146:f64d43ff0c18 11787 * @{
mbed_official 146:f64d43ff0c18 11788 */
mbed_official 146:f64d43ff0c18 11789
mbed_official 146:f64d43ff0c18 11790 /* MCR Bit Fields */
mbed_official 146:f64d43ff0c18 11791 #define SPI_MCR_HALT_MASK 0x1u
mbed_official 146:f64d43ff0c18 11792 #define SPI_MCR_HALT_SHIFT 0
mbed_official 146:f64d43ff0c18 11793 #define SPI_MCR_SMPL_PT_MASK 0x300u
mbed_official 146:f64d43ff0c18 11794 #define SPI_MCR_SMPL_PT_SHIFT 8
mbed_official 146:f64d43ff0c18 11795 #define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
mbed_official 146:f64d43ff0c18 11796 #define SPI_MCR_CLR_RXF_MASK 0x400u
mbed_official 146:f64d43ff0c18 11797 #define SPI_MCR_CLR_RXF_SHIFT 10
mbed_official 146:f64d43ff0c18 11798 #define SPI_MCR_CLR_TXF_MASK 0x800u
mbed_official 146:f64d43ff0c18 11799 #define SPI_MCR_CLR_TXF_SHIFT 11
mbed_official 146:f64d43ff0c18 11800 #define SPI_MCR_DIS_RXF_MASK 0x1000u
mbed_official 146:f64d43ff0c18 11801 #define SPI_MCR_DIS_RXF_SHIFT 12
mbed_official 146:f64d43ff0c18 11802 #define SPI_MCR_DIS_TXF_MASK 0x2000u
mbed_official 146:f64d43ff0c18 11803 #define SPI_MCR_DIS_TXF_SHIFT 13
mbed_official 146:f64d43ff0c18 11804 #define SPI_MCR_MDIS_MASK 0x4000u
mbed_official 146:f64d43ff0c18 11805 #define SPI_MCR_MDIS_SHIFT 14
mbed_official 146:f64d43ff0c18 11806 #define SPI_MCR_DOZE_MASK 0x8000u
mbed_official 146:f64d43ff0c18 11807 #define SPI_MCR_DOZE_SHIFT 15
mbed_official 146:f64d43ff0c18 11808 #define SPI_MCR_PCSIS_MASK 0x3F0000u
mbed_official 146:f64d43ff0c18 11809 #define SPI_MCR_PCSIS_SHIFT 16
mbed_official 146:f64d43ff0c18 11810 #define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
mbed_official 146:f64d43ff0c18 11811 #define SPI_MCR_ROOE_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 11812 #define SPI_MCR_ROOE_SHIFT 24
mbed_official 146:f64d43ff0c18 11813 #define SPI_MCR_PCSSE_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 11814 #define SPI_MCR_PCSSE_SHIFT 25
mbed_official 146:f64d43ff0c18 11815 #define SPI_MCR_MTFE_MASK 0x4000000u
mbed_official 146:f64d43ff0c18 11816 #define SPI_MCR_MTFE_SHIFT 26
mbed_official 146:f64d43ff0c18 11817 #define SPI_MCR_FRZ_MASK 0x8000000u
mbed_official 146:f64d43ff0c18 11818 #define SPI_MCR_FRZ_SHIFT 27
mbed_official 146:f64d43ff0c18 11819 #define SPI_MCR_DCONF_MASK 0x30000000u
mbed_official 146:f64d43ff0c18 11820 #define SPI_MCR_DCONF_SHIFT 28
mbed_official 146:f64d43ff0c18 11821 #define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
mbed_official 146:f64d43ff0c18 11822 #define SPI_MCR_CONT_SCKE_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 11823 #define SPI_MCR_CONT_SCKE_SHIFT 30
mbed_official 146:f64d43ff0c18 11824 #define SPI_MCR_MSTR_MASK 0x80000000u
mbed_official 146:f64d43ff0c18 11825 #define SPI_MCR_MSTR_SHIFT 31
mbed_official 146:f64d43ff0c18 11826 /* TCR Bit Fields */
mbed_official 146:f64d43ff0c18 11827 #define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u
mbed_official 146:f64d43ff0c18 11828 #define SPI_TCR_SPI_TCNT_SHIFT 16
mbed_official 146:f64d43ff0c18 11829 #define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
mbed_official 146:f64d43ff0c18 11830 /* CTAR Bit Fields */
mbed_official 146:f64d43ff0c18 11831 #define SPI_CTAR_BR_MASK 0xFu
mbed_official 146:f64d43ff0c18 11832 #define SPI_CTAR_BR_SHIFT 0
mbed_official 146:f64d43ff0c18 11833 #define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
mbed_official 146:f64d43ff0c18 11834 #define SPI_CTAR_DT_MASK 0xF0u
mbed_official 146:f64d43ff0c18 11835 #define SPI_CTAR_DT_SHIFT 4
mbed_official 146:f64d43ff0c18 11836 #define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
mbed_official 146:f64d43ff0c18 11837 #define SPI_CTAR_ASC_MASK 0xF00u
mbed_official 146:f64d43ff0c18 11838 #define SPI_CTAR_ASC_SHIFT 8
mbed_official 146:f64d43ff0c18 11839 #define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
mbed_official 146:f64d43ff0c18 11840 #define SPI_CTAR_CSSCK_MASK 0xF000u
mbed_official 146:f64d43ff0c18 11841 #define SPI_CTAR_CSSCK_SHIFT 12
mbed_official 146:f64d43ff0c18 11842 #define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
mbed_official 146:f64d43ff0c18 11843 #define SPI_CTAR_PBR_MASK 0x30000u
mbed_official 146:f64d43ff0c18 11844 #define SPI_CTAR_PBR_SHIFT 16
mbed_official 146:f64d43ff0c18 11845 #define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
mbed_official 146:f64d43ff0c18 11846 #define SPI_CTAR_PDT_MASK 0xC0000u
mbed_official 146:f64d43ff0c18 11847 #define SPI_CTAR_PDT_SHIFT 18
mbed_official 146:f64d43ff0c18 11848 #define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
mbed_official 146:f64d43ff0c18 11849 #define SPI_CTAR_PASC_MASK 0x300000u
mbed_official 146:f64d43ff0c18 11850 #define SPI_CTAR_PASC_SHIFT 20
mbed_official 146:f64d43ff0c18 11851 #define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
mbed_official 146:f64d43ff0c18 11852 #define SPI_CTAR_PCSSCK_MASK 0xC00000u
mbed_official 146:f64d43ff0c18 11853 #define SPI_CTAR_PCSSCK_SHIFT 22
mbed_official 146:f64d43ff0c18 11854 #define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
mbed_official 146:f64d43ff0c18 11855 #define SPI_CTAR_LSBFE_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 11856 #define SPI_CTAR_LSBFE_SHIFT 24
mbed_official 146:f64d43ff0c18 11857 #define SPI_CTAR_CPHA_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 11858 #define SPI_CTAR_CPHA_SHIFT 25
mbed_official 146:f64d43ff0c18 11859 #define SPI_CTAR_CPOL_MASK 0x4000000u
mbed_official 146:f64d43ff0c18 11860 #define SPI_CTAR_CPOL_SHIFT 26
mbed_official 146:f64d43ff0c18 11861 #define SPI_CTAR_FMSZ_MASK 0x78000000u
mbed_official 146:f64d43ff0c18 11862 #define SPI_CTAR_FMSZ_SHIFT 27
mbed_official 146:f64d43ff0c18 11863 #define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
mbed_official 146:f64d43ff0c18 11864 #define SPI_CTAR_DBR_MASK 0x80000000u
mbed_official 146:f64d43ff0c18 11865 #define SPI_CTAR_DBR_SHIFT 31
mbed_official 146:f64d43ff0c18 11866 /* CTAR_SLAVE Bit Fields */
mbed_official 146:f64d43ff0c18 11867 #define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 11868 #define SPI_CTAR_SLAVE_CPHA_SHIFT 25
mbed_official 146:f64d43ff0c18 11869 #define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u
mbed_official 146:f64d43ff0c18 11870 #define SPI_CTAR_SLAVE_CPOL_SHIFT 26
mbed_official 146:f64d43ff0c18 11871 #define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u
mbed_official 146:f64d43ff0c18 11872 #define SPI_CTAR_SLAVE_FMSZ_SHIFT 27
mbed_official 146:f64d43ff0c18 11873 #define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
mbed_official 146:f64d43ff0c18 11874 /* SR Bit Fields */
mbed_official 146:f64d43ff0c18 11875 #define SPI_SR_POPNXTPTR_MASK 0xFu
mbed_official 146:f64d43ff0c18 11876 #define SPI_SR_POPNXTPTR_SHIFT 0
mbed_official 146:f64d43ff0c18 11877 #define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
mbed_official 146:f64d43ff0c18 11878 #define SPI_SR_RXCTR_MASK 0xF0u
mbed_official 146:f64d43ff0c18 11879 #define SPI_SR_RXCTR_SHIFT 4
mbed_official 146:f64d43ff0c18 11880 #define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
mbed_official 146:f64d43ff0c18 11881 #define SPI_SR_TXNXTPTR_MASK 0xF00u
mbed_official 146:f64d43ff0c18 11882 #define SPI_SR_TXNXTPTR_SHIFT 8
mbed_official 146:f64d43ff0c18 11883 #define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
mbed_official 146:f64d43ff0c18 11884 #define SPI_SR_TXCTR_MASK 0xF000u
mbed_official 146:f64d43ff0c18 11885 #define SPI_SR_TXCTR_SHIFT 12
mbed_official 146:f64d43ff0c18 11886 #define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
mbed_official 146:f64d43ff0c18 11887 #define SPI_SR_RFDF_MASK 0x20000u
mbed_official 146:f64d43ff0c18 11888 #define SPI_SR_RFDF_SHIFT 17
mbed_official 146:f64d43ff0c18 11889 #define SPI_SR_RFOF_MASK 0x80000u
mbed_official 146:f64d43ff0c18 11890 #define SPI_SR_RFOF_SHIFT 19
mbed_official 146:f64d43ff0c18 11891 #define SPI_SR_TFFF_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 11892 #define SPI_SR_TFFF_SHIFT 25
mbed_official 146:f64d43ff0c18 11893 #define SPI_SR_TFUF_MASK 0x8000000u
mbed_official 146:f64d43ff0c18 11894 #define SPI_SR_TFUF_SHIFT 27
mbed_official 146:f64d43ff0c18 11895 #define SPI_SR_EOQF_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 11896 #define SPI_SR_EOQF_SHIFT 28
mbed_official 146:f64d43ff0c18 11897 #define SPI_SR_TXRXS_MASK 0x40000000u
mbed_official 146:f64d43ff0c18 11898 #define SPI_SR_TXRXS_SHIFT 30
mbed_official 146:f64d43ff0c18 11899 #define SPI_SR_TCF_MASK 0x80000000u
mbed_official 146:f64d43ff0c18 11900 #define SPI_SR_TCF_SHIFT 31
mbed_official 146:f64d43ff0c18 11901 /* RSER Bit Fields */
mbed_official 146:f64d43ff0c18 11902 #define SPI_RSER_RFDF_DIRS_MASK 0x10000u
mbed_official 146:f64d43ff0c18 11903 #define SPI_RSER_RFDF_DIRS_SHIFT 16
mbed_official 146:f64d43ff0c18 11904 #define SPI_RSER_RFDF_RE_MASK 0x20000u
mbed_official 146:f64d43ff0c18 11905 #define SPI_RSER_RFDF_RE_SHIFT 17
mbed_official 146:f64d43ff0c18 11906 #define SPI_RSER_RFOF_RE_MASK 0x80000u
mbed_official 146:f64d43ff0c18 11907 #define SPI_RSER_RFOF_RE_SHIFT 19
mbed_official 146:f64d43ff0c18 11908 #define SPI_RSER_TFFF_DIRS_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 11909 #define SPI_RSER_TFFF_DIRS_SHIFT 24
mbed_official 146:f64d43ff0c18 11910 #define SPI_RSER_TFFF_RE_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 11911 #define SPI_RSER_TFFF_RE_SHIFT 25
mbed_official 146:f64d43ff0c18 11912 #define SPI_RSER_TFUF_RE_MASK 0x8000000u
mbed_official 146:f64d43ff0c18 11913 #define SPI_RSER_TFUF_RE_SHIFT 27
mbed_official 146:f64d43ff0c18 11914 #define SPI_RSER_EOQF_RE_MASK 0x10000000u
mbed_official 146:f64d43ff0c18 11915 #define SPI_RSER_EOQF_RE_SHIFT 28
mbed_official 146:f64d43ff0c18 11916 #define SPI_RSER_TCF_RE_MASK 0x80000000u
mbed_official 146:f64d43ff0c18 11917 #define SPI_RSER_TCF_RE_SHIFT 31
mbed_official 146:f64d43ff0c18 11918 /* PUSHR Bit Fields */
mbed_official 146:f64d43ff0c18 11919 #define SPI_PUSHR_TXDATA_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 11920 #define SPI_PUSHR_TXDATA_SHIFT 0
mbed_official 146:f64d43ff0c18 11921 #define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
mbed_official 146:f64d43ff0c18 11922 #define SPI_PUSHR_PCS_MASK 0x3F0000u
mbed_official 146:f64d43ff0c18 11923 #define SPI_PUSHR_PCS_SHIFT 16
mbed_official 146:f64d43ff0c18 11924 #define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
mbed_official 146:f64d43ff0c18 11925 #define SPI_PUSHR_CTCNT_MASK 0x4000000u
mbed_official 146:f64d43ff0c18 11926 #define SPI_PUSHR_CTCNT_SHIFT 26
mbed_official 146:f64d43ff0c18 11927 #define SPI_PUSHR_EOQ_MASK 0x8000000u
mbed_official 146:f64d43ff0c18 11928 #define SPI_PUSHR_EOQ_SHIFT 27
mbed_official 146:f64d43ff0c18 11929 #define SPI_PUSHR_CTAS_MASK 0x70000000u
mbed_official 146:f64d43ff0c18 11930 #define SPI_PUSHR_CTAS_SHIFT 28
mbed_official 146:f64d43ff0c18 11931 #define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
mbed_official 146:f64d43ff0c18 11932 #define SPI_PUSHR_CONT_MASK 0x80000000u
mbed_official 146:f64d43ff0c18 11933 #define SPI_PUSHR_CONT_SHIFT 31
mbed_official 146:f64d43ff0c18 11934 /* PUSHR_SLAVE Bit Fields */
mbed_official 146:f64d43ff0c18 11935 #define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 11936 #define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0
mbed_official 146:f64d43ff0c18 11937 #define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
mbed_official 146:f64d43ff0c18 11938 /* POPR Bit Fields */
mbed_official 146:f64d43ff0c18 11939 #define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 11940 #define SPI_POPR_RXDATA_SHIFT 0
mbed_official 146:f64d43ff0c18 11941 #define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
mbed_official 146:f64d43ff0c18 11942 /* TXFR0 Bit Fields */
mbed_official 146:f64d43ff0c18 11943 #define SPI_TXFR0_TXDATA_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 11944 #define SPI_TXFR0_TXDATA_SHIFT 0
mbed_official 146:f64d43ff0c18 11945 #define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
mbed_official 146:f64d43ff0c18 11946 #define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u
mbed_official 146:f64d43ff0c18 11947 #define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16
mbed_official 146:f64d43ff0c18 11948 #define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
mbed_official 146:f64d43ff0c18 11949 /* TXFR1 Bit Fields */
mbed_official 146:f64d43ff0c18 11950 #define SPI_TXFR1_TXDATA_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 11951 #define SPI_TXFR1_TXDATA_SHIFT 0
mbed_official 146:f64d43ff0c18 11952 #define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
mbed_official 146:f64d43ff0c18 11953 #define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u
mbed_official 146:f64d43ff0c18 11954 #define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16
mbed_official 146:f64d43ff0c18 11955 #define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
mbed_official 146:f64d43ff0c18 11956 /* TXFR2 Bit Fields */
mbed_official 146:f64d43ff0c18 11957 #define SPI_TXFR2_TXDATA_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 11958 #define SPI_TXFR2_TXDATA_SHIFT 0
mbed_official 146:f64d43ff0c18 11959 #define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
mbed_official 146:f64d43ff0c18 11960 #define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u
mbed_official 146:f64d43ff0c18 11961 #define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16
mbed_official 146:f64d43ff0c18 11962 #define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
mbed_official 146:f64d43ff0c18 11963 /* TXFR3 Bit Fields */
mbed_official 146:f64d43ff0c18 11964 #define SPI_TXFR3_TXDATA_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 11965 #define SPI_TXFR3_TXDATA_SHIFT 0
mbed_official 146:f64d43ff0c18 11966 #define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
mbed_official 146:f64d43ff0c18 11967 #define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u
mbed_official 146:f64d43ff0c18 11968 #define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16
mbed_official 146:f64d43ff0c18 11969 #define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
mbed_official 146:f64d43ff0c18 11970 /* RXFR0 Bit Fields */
mbed_official 146:f64d43ff0c18 11971 #define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 11972 #define SPI_RXFR0_RXDATA_SHIFT 0
mbed_official 146:f64d43ff0c18 11973 #define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
mbed_official 146:f64d43ff0c18 11974 /* RXFR1 Bit Fields */
mbed_official 146:f64d43ff0c18 11975 #define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 11976 #define SPI_RXFR1_RXDATA_SHIFT 0
mbed_official 146:f64d43ff0c18 11977 #define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
mbed_official 146:f64d43ff0c18 11978 /* RXFR2 Bit Fields */
mbed_official 146:f64d43ff0c18 11979 #define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 11980 #define SPI_RXFR2_RXDATA_SHIFT 0
mbed_official 146:f64d43ff0c18 11981 #define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
mbed_official 146:f64d43ff0c18 11982 /* RXFR3 Bit Fields */
mbed_official 146:f64d43ff0c18 11983 #define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu
mbed_official 146:f64d43ff0c18 11984 #define SPI_RXFR3_RXDATA_SHIFT 0
mbed_official 146:f64d43ff0c18 11985 #define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
mbed_official 146:f64d43ff0c18 11986
mbed_official 146:f64d43ff0c18 11987 /*!
mbed_official 146:f64d43ff0c18 11988 * @}
mbed_official 146:f64d43ff0c18 11989 */ /* end of group SPI_Register_Masks */
mbed_official 146:f64d43ff0c18 11990
mbed_official 146:f64d43ff0c18 11991
mbed_official 146:f64d43ff0c18 11992 /* SPI - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 11993 /** Peripheral SPI0 base address */
mbed_official 146:f64d43ff0c18 11994 #define SPI0_BASE (0x4002C000u)
mbed_official 146:f64d43ff0c18 11995 /** Peripheral SPI0 base pointer */
mbed_official 146:f64d43ff0c18 11996 #define SPI0 ((SPI_Type *)SPI0_BASE)
mbed_official 146:f64d43ff0c18 11997 #define SPI0_BASE_PTR (SPI0)
mbed_official 146:f64d43ff0c18 11998 /** Peripheral SPI1 base address */
mbed_official 146:f64d43ff0c18 11999 #define SPI1_BASE (0x4002D000u)
mbed_official 146:f64d43ff0c18 12000 /** Peripheral SPI1 base pointer */
mbed_official 146:f64d43ff0c18 12001 #define SPI1 ((SPI_Type *)SPI1_BASE)
mbed_official 146:f64d43ff0c18 12002 #define SPI1_BASE_PTR (SPI1)
mbed_official 146:f64d43ff0c18 12003 /** Peripheral SPI2 base address */
mbed_official 146:f64d43ff0c18 12004 #define SPI2_BASE (0x400AC000u)
mbed_official 146:f64d43ff0c18 12005 /** Peripheral SPI2 base pointer */
mbed_official 146:f64d43ff0c18 12006 #define SPI2 ((SPI_Type *)SPI2_BASE)
mbed_official 146:f64d43ff0c18 12007 #define SPI2_BASE_PTR (SPI2)
mbed_official 146:f64d43ff0c18 12008 /** Array initializer of SPI peripheral base pointers */
mbed_official 146:f64d43ff0c18 12009 #define SPI_BASES { SPI0, SPI1, SPI2 }
mbed_official 146:f64d43ff0c18 12010
mbed_official 146:f64d43ff0c18 12011 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 12012 -- SPI - Register accessor macros
mbed_official 146:f64d43ff0c18 12013 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 12014
mbed_official 146:f64d43ff0c18 12015 /*!
mbed_official 146:f64d43ff0c18 12016 * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
mbed_official 146:f64d43ff0c18 12017 * @{
mbed_official 146:f64d43ff0c18 12018 */
mbed_official 146:f64d43ff0c18 12019
mbed_official 146:f64d43ff0c18 12020
mbed_official 146:f64d43ff0c18 12021 /* SPI - Register instance definitions */
mbed_official 146:f64d43ff0c18 12022 /* SPI0 */
mbed_official 146:f64d43ff0c18 12023 #define SPI0_MCR SPI_MCR_REG(SPI0)
mbed_official 146:f64d43ff0c18 12024 #define SPI0_TCR SPI_TCR_REG(SPI0)
mbed_official 146:f64d43ff0c18 12025 #define SPI0_CTAR0 SPI_CTAR_REG(SPI0,0)
mbed_official 146:f64d43ff0c18 12026 #define SPI0_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI0,0)
mbed_official 146:f64d43ff0c18 12027 #define SPI0_CTAR1 SPI_CTAR_REG(SPI0,1)
mbed_official 146:f64d43ff0c18 12028 #define SPI0_SR SPI_SR_REG(SPI0)
mbed_official 146:f64d43ff0c18 12029 #define SPI0_RSER SPI_RSER_REG(SPI0)
mbed_official 146:f64d43ff0c18 12030 #define SPI0_PUSHR SPI_PUSHR_REG(SPI0)
mbed_official 146:f64d43ff0c18 12031 #define SPI0_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI0)
mbed_official 146:f64d43ff0c18 12032 #define SPI0_POPR SPI_POPR_REG(SPI0)
mbed_official 146:f64d43ff0c18 12033 #define SPI0_TXFR0 SPI_TXFR0_REG(SPI0)
mbed_official 146:f64d43ff0c18 12034 #define SPI0_TXFR1 SPI_TXFR1_REG(SPI0)
mbed_official 146:f64d43ff0c18 12035 #define SPI0_TXFR2 SPI_TXFR2_REG(SPI0)
mbed_official 146:f64d43ff0c18 12036 #define SPI0_TXFR3 SPI_TXFR3_REG(SPI0)
mbed_official 146:f64d43ff0c18 12037 #define SPI0_RXFR0 SPI_RXFR0_REG(SPI0)
mbed_official 146:f64d43ff0c18 12038 #define SPI0_RXFR1 SPI_RXFR1_REG(SPI0)
mbed_official 146:f64d43ff0c18 12039 #define SPI0_RXFR2 SPI_RXFR2_REG(SPI0)
mbed_official 146:f64d43ff0c18 12040 #define SPI0_RXFR3 SPI_RXFR3_REG(SPI0)
mbed_official 146:f64d43ff0c18 12041 /* SPI1 */
mbed_official 146:f64d43ff0c18 12042 #define SPI1_MCR SPI_MCR_REG(SPI1)
mbed_official 146:f64d43ff0c18 12043 #define SPI1_TCR SPI_TCR_REG(SPI1)
mbed_official 146:f64d43ff0c18 12044 #define SPI1_CTAR0 SPI_CTAR_REG(SPI1,0)
mbed_official 146:f64d43ff0c18 12045 #define SPI1_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI1,0)
mbed_official 146:f64d43ff0c18 12046 #define SPI1_CTAR1 SPI_CTAR_REG(SPI1,1)
mbed_official 146:f64d43ff0c18 12047 #define SPI1_SR SPI_SR_REG(SPI1)
mbed_official 146:f64d43ff0c18 12048 #define SPI1_RSER SPI_RSER_REG(SPI1)
mbed_official 146:f64d43ff0c18 12049 #define SPI1_PUSHR SPI_PUSHR_REG(SPI1)
mbed_official 146:f64d43ff0c18 12050 #define SPI1_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI1)
mbed_official 146:f64d43ff0c18 12051 #define SPI1_POPR SPI_POPR_REG(SPI1)
mbed_official 146:f64d43ff0c18 12052 #define SPI1_TXFR0 SPI_TXFR0_REG(SPI1)
mbed_official 146:f64d43ff0c18 12053 #define SPI1_TXFR1 SPI_TXFR1_REG(SPI1)
mbed_official 146:f64d43ff0c18 12054 #define SPI1_TXFR2 SPI_TXFR2_REG(SPI1)
mbed_official 146:f64d43ff0c18 12055 #define SPI1_TXFR3 SPI_TXFR3_REG(SPI1)
mbed_official 146:f64d43ff0c18 12056 #define SPI1_RXFR0 SPI_RXFR0_REG(SPI1)
mbed_official 146:f64d43ff0c18 12057 #define SPI1_RXFR1 SPI_RXFR1_REG(SPI1)
mbed_official 146:f64d43ff0c18 12058 #define SPI1_RXFR2 SPI_RXFR2_REG(SPI1)
mbed_official 146:f64d43ff0c18 12059 #define SPI1_RXFR3 SPI_RXFR3_REG(SPI1)
mbed_official 146:f64d43ff0c18 12060 /* SPI2 */
mbed_official 146:f64d43ff0c18 12061 #define SPI2_MCR SPI_MCR_REG(SPI2)
mbed_official 146:f64d43ff0c18 12062 #define SPI2_TCR SPI_TCR_REG(SPI2)
mbed_official 146:f64d43ff0c18 12063 #define SPI2_CTAR0 SPI_CTAR_REG(SPI2,0)
mbed_official 146:f64d43ff0c18 12064 #define SPI2_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI2,0)
mbed_official 146:f64d43ff0c18 12065 #define SPI2_CTAR1 SPI_CTAR_REG(SPI2,1)
mbed_official 146:f64d43ff0c18 12066 #define SPI2_SR SPI_SR_REG(SPI2)
mbed_official 146:f64d43ff0c18 12067 #define SPI2_RSER SPI_RSER_REG(SPI2)
mbed_official 146:f64d43ff0c18 12068 #define SPI2_PUSHR SPI_PUSHR_REG(SPI2)
mbed_official 146:f64d43ff0c18 12069 #define SPI2_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI2)
mbed_official 146:f64d43ff0c18 12070 #define SPI2_POPR SPI_POPR_REG(SPI2)
mbed_official 146:f64d43ff0c18 12071 #define SPI2_TXFR0 SPI_TXFR0_REG(SPI2)
mbed_official 146:f64d43ff0c18 12072 #define SPI2_TXFR1 SPI_TXFR1_REG(SPI2)
mbed_official 146:f64d43ff0c18 12073 #define SPI2_TXFR2 SPI_TXFR2_REG(SPI2)
mbed_official 146:f64d43ff0c18 12074 #define SPI2_TXFR3 SPI_TXFR3_REG(SPI2)
mbed_official 146:f64d43ff0c18 12075 #define SPI2_RXFR0 SPI_RXFR0_REG(SPI2)
mbed_official 146:f64d43ff0c18 12076 #define SPI2_RXFR1 SPI_RXFR1_REG(SPI2)
mbed_official 146:f64d43ff0c18 12077 #define SPI2_RXFR2 SPI_RXFR2_REG(SPI2)
mbed_official 146:f64d43ff0c18 12078 #define SPI2_RXFR3 SPI_RXFR3_REG(SPI2)
mbed_official 146:f64d43ff0c18 12079
mbed_official 146:f64d43ff0c18 12080 /* SPI - Register array accessors */
mbed_official 146:f64d43ff0c18 12081 #define SPI0_CTAR(index2) SPI_CTAR_REG(SPI0,index2)
mbed_official 146:f64d43ff0c18 12082 #define SPI1_CTAR(index2) SPI_CTAR_REG(SPI1,index2)
mbed_official 146:f64d43ff0c18 12083 #define SPI2_CTAR(index2) SPI_CTAR_REG(SPI2,index2)
mbed_official 146:f64d43ff0c18 12084 #define SPI0_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI0,index2)
mbed_official 146:f64d43ff0c18 12085 #define SPI1_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI1,index2)
mbed_official 146:f64d43ff0c18 12086 #define SPI2_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI2,index2)
mbed_official 146:f64d43ff0c18 12087
mbed_official 146:f64d43ff0c18 12088 /*!
mbed_official 146:f64d43ff0c18 12089 * @}
mbed_official 146:f64d43ff0c18 12090 */ /* end of group SPI_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 12091
mbed_official 146:f64d43ff0c18 12092
mbed_official 146:f64d43ff0c18 12093 /*!
mbed_official 146:f64d43ff0c18 12094 * @}
mbed_official 146:f64d43ff0c18 12095 */ /* end of group SPI_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 12096
mbed_official 146:f64d43ff0c18 12097
mbed_official 146:f64d43ff0c18 12098 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 12099 -- UART Peripheral Access Layer
mbed_official 146:f64d43ff0c18 12100 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 12101
mbed_official 146:f64d43ff0c18 12102 /*!
mbed_official 146:f64d43ff0c18 12103 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
mbed_official 146:f64d43ff0c18 12104 * @{
mbed_official 146:f64d43ff0c18 12105 */
mbed_official 146:f64d43ff0c18 12106
mbed_official 146:f64d43ff0c18 12107 /** UART - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 12108 typedef struct {
mbed_official 146:f64d43ff0c18 12109 __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */
mbed_official 146:f64d43ff0c18 12110 __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
mbed_official 146:f64d43ff0c18 12111 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
mbed_official 146:f64d43ff0c18 12112 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
mbed_official 146:f64d43ff0c18 12113 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
mbed_official 146:f64d43ff0c18 12114 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
mbed_official 146:f64d43ff0c18 12115 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
mbed_official 146:f64d43ff0c18 12116 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
mbed_official 146:f64d43ff0c18 12117 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
mbed_official 146:f64d43ff0c18 12118 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
mbed_official 146:f64d43ff0c18 12119 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
mbed_official 146:f64d43ff0c18 12120 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
mbed_official 146:f64d43ff0c18 12121 __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
mbed_official 146:f64d43ff0c18 12122 __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
mbed_official 146:f64d43ff0c18 12123 __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
mbed_official 146:f64d43ff0c18 12124 uint8_t RESERVED_0[1];
mbed_official 146:f64d43ff0c18 12125 __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
mbed_official 146:f64d43ff0c18 12126 __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
mbed_official 146:f64d43ff0c18 12127 __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
mbed_official 146:f64d43ff0c18 12128 __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
mbed_official 146:f64d43ff0c18 12129 __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
mbed_official 146:f64d43ff0c18 12130 __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
mbed_official 146:f64d43ff0c18 12131 __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
mbed_official 146:f64d43ff0c18 12132 uint8_t RESERVED_1[1];
mbed_official 146:f64d43ff0c18 12133 __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
mbed_official 146:f64d43ff0c18 12134 __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
mbed_official 146:f64d43ff0c18 12135 __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
mbed_official 146:f64d43ff0c18 12136 union { /* offset: 0x1B */
mbed_official 146:f64d43ff0c18 12137 __IO uint8_t WP7816_T_TYPE0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
mbed_official 146:f64d43ff0c18 12138 __IO uint8_t WP7816_T_TYPE1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
mbed_official 146:f64d43ff0c18 12139 };
mbed_official 146:f64d43ff0c18 12140 __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
mbed_official 146:f64d43ff0c18 12141 __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
mbed_official 146:f64d43ff0c18 12142 __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
mbed_official 146:f64d43ff0c18 12143 __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
mbed_official 146:f64d43ff0c18 12144 } UART_Type, *UART_MemMapPtr;
mbed_official 146:f64d43ff0c18 12145
mbed_official 146:f64d43ff0c18 12146 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 12147 -- UART - Register accessor macros
mbed_official 146:f64d43ff0c18 12148 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 12149
mbed_official 146:f64d43ff0c18 12150 /*!
mbed_official 146:f64d43ff0c18 12151 * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
mbed_official 146:f64d43ff0c18 12152 * @{
mbed_official 146:f64d43ff0c18 12153 */
mbed_official 146:f64d43ff0c18 12154
mbed_official 146:f64d43ff0c18 12155
mbed_official 146:f64d43ff0c18 12156 /* UART - Register accessors */
mbed_official 146:f64d43ff0c18 12157 #define UART_BDH_REG(base) ((base)->BDH)
mbed_official 146:f64d43ff0c18 12158 #define UART_BDL_REG(base) ((base)->BDL)
mbed_official 146:f64d43ff0c18 12159 #define UART_C1_REG(base) ((base)->C1)
mbed_official 146:f64d43ff0c18 12160 #define UART_C2_REG(base) ((base)->C2)
mbed_official 146:f64d43ff0c18 12161 #define UART_S1_REG(base) ((base)->S1)
mbed_official 146:f64d43ff0c18 12162 #define UART_S2_REG(base) ((base)->S2)
mbed_official 146:f64d43ff0c18 12163 #define UART_C3_REG(base) ((base)->C3)
mbed_official 146:f64d43ff0c18 12164 #define UART_D_REG(base) ((base)->D)
mbed_official 146:f64d43ff0c18 12165 #define UART_MA1_REG(base) ((base)->MA1)
mbed_official 146:f64d43ff0c18 12166 #define UART_MA2_REG(base) ((base)->MA2)
mbed_official 146:f64d43ff0c18 12167 #define UART_C4_REG(base) ((base)->C4)
mbed_official 146:f64d43ff0c18 12168 #define UART_C5_REG(base) ((base)->C5)
mbed_official 146:f64d43ff0c18 12169 #define UART_ED_REG(base) ((base)->ED)
mbed_official 146:f64d43ff0c18 12170 #define UART_MODEM_REG(base) ((base)->MODEM)
mbed_official 146:f64d43ff0c18 12171 #define UART_IR_REG(base) ((base)->IR)
mbed_official 146:f64d43ff0c18 12172 #define UART_PFIFO_REG(base) ((base)->PFIFO)
mbed_official 146:f64d43ff0c18 12173 #define UART_CFIFO_REG(base) ((base)->CFIFO)
mbed_official 146:f64d43ff0c18 12174 #define UART_SFIFO_REG(base) ((base)->SFIFO)
mbed_official 146:f64d43ff0c18 12175 #define UART_TWFIFO_REG(base) ((base)->TWFIFO)
mbed_official 146:f64d43ff0c18 12176 #define UART_TCFIFO_REG(base) ((base)->TCFIFO)
mbed_official 146:f64d43ff0c18 12177 #define UART_RWFIFO_REG(base) ((base)->RWFIFO)
mbed_official 146:f64d43ff0c18 12178 #define UART_RCFIFO_REG(base) ((base)->RCFIFO)
mbed_official 146:f64d43ff0c18 12179 #define UART_C7816_REG(base) ((base)->C7816)
mbed_official 146:f64d43ff0c18 12180 #define UART_IE7816_REG(base) ((base)->IE7816)
mbed_official 146:f64d43ff0c18 12181 #define UART_IS7816_REG(base) ((base)->IS7816)
mbed_official 146:f64d43ff0c18 12182 #define UART_WP7816_T_TYPE0_REG(base) ((base)->WP7816_T_TYPE0)
mbed_official 146:f64d43ff0c18 12183 #define UART_WP7816_T_TYPE1_REG(base) ((base)->WP7816_T_TYPE1)
mbed_official 146:f64d43ff0c18 12184 #define UART_WN7816_REG(base) ((base)->WN7816)
mbed_official 146:f64d43ff0c18 12185 #define UART_WF7816_REG(base) ((base)->WF7816)
mbed_official 146:f64d43ff0c18 12186 #define UART_ET7816_REG(base) ((base)->ET7816)
mbed_official 146:f64d43ff0c18 12187 #define UART_TL7816_REG(base) ((base)->TL7816)
mbed_official 146:f64d43ff0c18 12188
mbed_official 146:f64d43ff0c18 12189 /*!
mbed_official 146:f64d43ff0c18 12190 * @}
mbed_official 146:f64d43ff0c18 12191 */ /* end of group UART_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 12192
mbed_official 146:f64d43ff0c18 12193
mbed_official 146:f64d43ff0c18 12194 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 12195 -- UART Register Masks
mbed_official 146:f64d43ff0c18 12196 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 12197
mbed_official 146:f64d43ff0c18 12198 /*!
mbed_official 146:f64d43ff0c18 12199 * @addtogroup UART_Register_Masks UART Register Masks
mbed_official 146:f64d43ff0c18 12200 * @{
mbed_official 146:f64d43ff0c18 12201 */
mbed_official 146:f64d43ff0c18 12202
mbed_official 146:f64d43ff0c18 12203 /* BDH Bit Fields */
mbed_official 146:f64d43ff0c18 12204 #define UART_BDH_SBR_MASK 0x1Fu
mbed_official 146:f64d43ff0c18 12205 #define UART_BDH_SBR_SHIFT 0
mbed_official 146:f64d43ff0c18 12206 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
mbed_official 146:f64d43ff0c18 12207 #define UART_BDH_SBNS_MASK 0x20u
mbed_official 146:f64d43ff0c18 12208 #define UART_BDH_SBNS_SHIFT 5
mbed_official 146:f64d43ff0c18 12209 #define UART_BDH_RXEDGIE_MASK 0x40u
mbed_official 146:f64d43ff0c18 12210 #define UART_BDH_RXEDGIE_SHIFT 6
mbed_official 146:f64d43ff0c18 12211 #define UART_BDH_LBKDIE_MASK 0x80u
mbed_official 146:f64d43ff0c18 12212 #define UART_BDH_LBKDIE_SHIFT 7
mbed_official 146:f64d43ff0c18 12213 /* BDL Bit Fields */
mbed_official 146:f64d43ff0c18 12214 #define UART_BDL_SBR_MASK 0xFFu
mbed_official 146:f64d43ff0c18 12215 #define UART_BDL_SBR_SHIFT 0
mbed_official 146:f64d43ff0c18 12216 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
mbed_official 146:f64d43ff0c18 12217 /* C1 Bit Fields */
mbed_official 146:f64d43ff0c18 12218 #define UART_C1_PT_MASK 0x1u
mbed_official 146:f64d43ff0c18 12219 #define UART_C1_PT_SHIFT 0
mbed_official 146:f64d43ff0c18 12220 #define UART_C1_PE_MASK 0x2u
mbed_official 146:f64d43ff0c18 12221 #define UART_C1_PE_SHIFT 1
mbed_official 146:f64d43ff0c18 12222 #define UART_C1_ILT_MASK 0x4u
mbed_official 146:f64d43ff0c18 12223 #define UART_C1_ILT_SHIFT 2
mbed_official 146:f64d43ff0c18 12224 #define UART_C1_WAKE_MASK 0x8u
mbed_official 146:f64d43ff0c18 12225 #define UART_C1_WAKE_SHIFT 3
mbed_official 146:f64d43ff0c18 12226 #define UART_C1_M_MASK 0x10u
mbed_official 146:f64d43ff0c18 12227 #define UART_C1_M_SHIFT 4
mbed_official 146:f64d43ff0c18 12228 #define UART_C1_RSRC_MASK 0x20u
mbed_official 146:f64d43ff0c18 12229 #define UART_C1_RSRC_SHIFT 5
mbed_official 146:f64d43ff0c18 12230 #define UART_C1_UARTSWAI_MASK 0x40u
mbed_official 146:f64d43ff0c18 12231 #define UART_C1_UARTSWAI_SHIFT 6
mbed_official 146:f64d43ff0c18 12232 #define UART_C1_LOOPS_MASK 0x80u
mbed_official 146:f64d43ff0c18 12233 #define UART_C1_LOOPS_SHIFT 7
mbed_official 146:f64d43ff0c18 12234 /* C2 Bit Fields */
mbed_official 146:f64d43ff0c18 12235 #define UART_C2_SBK_MASK 0x1u
mbed_official 146:f64d43ff0c18 12236 #define UART_C2_SBK_SHIFT 0
mbed_official 146:f64d43ff0c18 12237 #define UART_C2_RWU_MASK 0x2u
mbed_official 146:f64d43ff0c18 12238 #define UART_C2_RWU_SHIFT 1
mbed_official 146:f64d43ff0c18 12239 #define UART_C2_RE_MASK 0x4u
mbed_official 146:f64d43ff0c18 12240 #define UART_C2_RE_SHIFT 2
mbed_official 146:f64d43ff0c18 12241 #define UART_C2_TE_MASK 0x8u
mbed_official 146:f64d43ff0c18 12242 #define UART_C2_TE_SHIFT 3
mbed_official 146:f64d43ff0c18 12243 #define UART_C2_ILIE_MASK 0x10u
mbed_official 146:f64d43ff0c18 12244 #define UART_C2_ILIE_SHIFT 4
mbed_official 146:f64d43ff0c18 12245 #define UART_C2_RIE_MASK 0x20u
mbed_official 146:f64d43ff0c18 12246 #define UART_C2_RIE_SHIFT 5
mbed_official 146:f64d43ff0c18 12247 #define UART_C2_TCIE_MASK 0x40u
mbed_official 146:f64d43ff0c18 12248 #define UART_C2_TCIE_SHIFT 6
mbed_official 146:f64d43ff0c18 12249 #define UART_C2_TIE_MASK 0x80u
mbed_official 146:f64d43ff0c18 12250 #define UART_C2_TIE_SHIFT 7
mbed_official 146:f64d43ff0c18 12251 /* S1 Bit Fields */
mbed_official 146:f64d43ff0c18 12252 #define UART_S1_PF_MASK 0x1u
mbed_official 146:f64d43ff0c18 12253 #define UART_S1_PF_SHIFT 0
mbed_official 146:f64d43ff0c18 12254 #define UART_S1_FE_MASK 0x2u
mbed_official 146:f64d43ff0c18 12255 #define UART_S1_FE_SHIFT 1
mbed_official 146:f64d43ff0c18 12256 #define UART_S1_NF_MASK 0x4u
mbed_official 146:f64d43ff0c18 12257 #define UART_S1_NF_SHIFT 2
mbed_official 146:f64d43ff0c18 12258 #define UART_S1_OR_MASK 0x8u
mbed_official 146:f64d43ff0c18 12259 #define UART_S1_OR_SHIFT 3
mbed_official 146:f64d43ff0c18 12260 #define UART_S1_IDLE_MASK 0x10u
mbed_official 146:f64d43ff0c18 12261 #define UART_S1_IDLE_SHIFT 4
mbed_official 146:f64d43ff0c18 12262 #define UART_S1_RDRF_MASK 0x20u
mbed_official 146:f64d43ff0c18 12263 #define UART_S1_RDRF_SHIFT 5
mbed_official 146:f64d43ff0c18 12264 #define UART_S1_TC_MASK 0x40u
mbed_official 146:f64d43ff0c18 12265 #define UART_S1_TC_SHIFT 6
mbed_official 146:f64d43ff0c18 12266 #define UART_S1_TDRE_MASK 0x80u
mbed_official 146:f64d43ff0c18 12267 #define UART_S1_TDRE_SHIFT 7
mbed_official 146:f64d43ff0c18 12268 /* S2 Bit Fields */
mbed_official 146:f64d43ff0c18 12269 #define UART_S2_RAF_MASK 0x1u
mbed_official 146:f64d43ff0c18 12270 #define UART_S2_RAF_SHIFT 0
mbed_official 146:f64d43ff0c18 12271 #define UART_S2_LBKDE_MASK 0x2u
mbed_official 146:f64d43ff0c18 12272 #define UART_S2_LBKDE_SHIFT 1
mbed_official 146:f64d43ff0c18 12273 #define UART_S2_BRK13_MASK 0x4u
mbed_official 146:f64d43ff0c18 12274 #define UART_S2_BRK13_SHIFT 2
mbed_official 146:f64d43ff0c18 12275 #define UART_S2_RWUID_MASK 0x8u
mbed_official 146:f64d43ff0c18 12276 #define UART_S2_RWUID_SHIFT 3
mbed_official 146:f64d43ff0c18 12277 #define UART_S2_RXINV_MASK 0x10u
mbed_official 146:f64d43ff0c18 12278 #define UART_S2_RXINV_SHIFT 4
mbed_official 146:f64d43ff0c18 12279 #define UART_S2_MSBF_MASK 0x20u
mbed_official 146:f64d43ff0c18 12280 #define UART_S2_MSBF_SHIFT 5
mbed_official 146:f64d43ff0c18 12281 #define UART_S2_RXEDGIF_MASK 0x40u
mbed_official 146:f64d43ff0c18 12282 #define UART_S2_RXEDGIF_SHIFT 6
mbed_official 146:f64d43ff0c18 12283 #define UART_S2_LBKDIF_MASK 0x80u
mbed_official 146:f64d43ff0c18 12284 #define UART_S2_LBKDIF_SHIFT 7
mbed_official 146:f64d43ff0c18 12285 /* C3 Bit Fields */
mbed_official 146:f64d43ff0c18 12286 #define UART_C3_PEIE_MASK 0x1u
mbed_official 146:f64d43ff0c18 12287 #define UART_C3_PEIE_SHIFT 0
mbed_official 146:f64d43ff0c18 12288 #define UART_C3_FEIE_MASK 0x2u
mbed_official 146:f64d43ff0c18 12289 #define UART_C3_FEIE_SHIFT 1
mbed_official 146:f64d43ff0c18 12290 #define UART_C3_NEIE_MASK 0x4u
mbed_official 146:f64d43ff0c18 12291 #define UART_C3_NEIE_SHIFT 2
mbed_official 146:f64d43ff0c18 12292 #define UART_C3_ORIE_MASK 0x8u
mbed_official 146:f64d43ff0c18 12293 #define UART_C3_ORIE_SHIFT 3
mbed_official 146:f64d43ff0c18 12294 #define UART_C3_TXINV_MASK 0x10u
mbed_official 146:f64d43ff0c18 12295 #define UART_C3_TXINV_SHIFT 4
mbed_official 146:f64d43ff0c18 12296 #define UART_C3_TXDIR_MASK 0x20u
mbed_official 146:f64d43ff0c18 12297 #define UART_C3_TXDIR_SHIFT 5
mbed_official 146:f64d43ff0c18 12298 #define UART_C3_T8_MASK 0x40u
mbed_official 146:f64d43ff0c18 12299 #define UART_C3_T8_SHIFT 6
mbed_official 146:f64d43ff0c18 12300 #define UART_C3_R8_MASK 0x80u
mbed_official 146:f64d43ff0c18 12301 #define UART_C3_R8_SHIFT 7
mbed_official 146:f64d43ff0c18 12302 /* D Bit Fields */
mbed_official 146:f64d43ff0c18 12303 #define UART_D_RT_MASK 0xFFu
mbed_official 146:f64d43ff0c18 12304 #define UART_D_RT_SHIFT 0
mbed_official 146:f64d43ff0c18 12305 #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
mbed_official 146:f64d43ff0c18 12306 /* MA1 Bit Fields */
mbed_official 146:f64d43ff0c18 12307 #define UART_MA1_MA_MASK 0xFFu
mbed_official 146:f64d43ff0c18 12308 #define UART_MA1_MA_SHIFT 0
mbed_official 146:f64d43ff0c18 12309 #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
mbed_official 146:f64d43ff0c18 12310 /* MA2 Bit Fields */
mbed_official 146:f64d43ff0c18 12311 #define UART_MA2_MA_MASK 0xFFu
mbed_official 146:f64d43ff0c18 12312 #define UART_MA2_MA_SHIFT 0
mbed_official 146:f64d43ff0c18 12313 #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
mbed_official 146:f64d43ff0c18 12314 /* C4 Bit Fields */
mbed_official 146:f64d43ff0c18 12315 #define UART_C4_BRFA_MASK 0x1Fu
mbed_official 146:f64d43ff0c18 12316 #define UART_C4_BRFA_SHIFT 0
mbed_official 146:f64d43ff0c18 12317 #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
mbed_official 146:f64d43ff0c18 12318 #define UART_C4_M10_MASK 0x20u
mbed_official 146:f64d43ff0c18 12319 #define UART_C4_M10_SHIFT 5
mbed_official 146:f64d43ff0c18 12320 #define UART_C4_MAEN2_MASK 0x40u
mbed_official 146:f64d43ff0c18 12321 #define UART_C4_MAEN2_SHIFT 6
mbed_official 146:f64d43ff0c18 12322 #define UART_C4_MAEN1_MASK 0x80u
mbed_official 146:f64d43ff0c18 12323 #define UART_C4_MAEN1_SHIFT 7
mbed_official 146:f64d43ff0c18 12324 /* C5 Bit Fields */
mbed_official 146:f64d43ff0c18 12325 #define UART_C5_LBKDDMAS_MASK 0x8u
mbed_official 146:f64d43ff0c18 12326 #define UART_C5_LBKDDMAS_SHIFT 3
mbed_official 146:f64d43ff0c18 12327 #define UART_C5_ILDMAS_MASK 0x10u
mbed_official 146:f64d43ff0c18 12328 #define UART_C5_ILDMAS_SHIFT 4
mbed_official 146:f64d43ff0c18 12329 #define UART_C5_RDMAS_MASK 0x20u
mbed_official 146:f64d43ff0c18 12330 #define UART_C5_RDMAS_SHIFT 5
mbed_official 146:f64d43ff0c18 12331 #define UART_C5_TCDMAS_MASK 0x40u
mbed_official 146:f64d43ff0c18 12332 #define UART_C5_TCDMAS_SHIFT 6
mbed_official 146:f64d43ff0c18 12333 #define UART_C5_TDMAS_MASK 0x80u
mbed_official 146:f64d43ff0c18 12334 #define UART_C5_TDMAS_SHIFT 7
mbed_official 146:f64d43ff0c18 12335 /* ED Bit Fields */
mbed_official 146:f64d43ff0c18 12336 #define UART_ED_PARITYE_MASK 0x40u
mbed_official 146:f64d43ff0c18 12337 #define UART_ED_PARITYE_SHIFT 6
mbed_official 146:f64d43ff0c18 12338 #define UART_ED_NOISY_MASK 0x80u
mbed_official 146:f64d43ff0c18 12339 #define UART_ED_NOISY_SHIFT 7
mbed_official 146:f64d43ff0c18 12340 /* MODEM Bit Fields */
mbed_official 146:f64d43ff0c18 12341 #define UART_MODEM_TXCTSE_MASK 0x1u
mbed_official 146:f64d43ff0c18 12342 #define UART_MODEM_TXCTSE_SHIFT 0
mbed_official 146:f64d43ff0c18 12343 #define UART_MODEM_TXRTSE_MASK 0x2u
mbed_official 146:f64d43ff0c18 12344 #define UART_MODEM_TXRTSE_SHIFT 1
mbed_official 146:f64d43ff0c18 12345 #define UART_MODEM_TXRTSPOL_MASK 0x4u
mbed_official 146:f64d43ff0c18 12346 #define UART_MODEM_TXRTSPOL_SHIFT 2
mbed_official 146:f64d43ff0c18 12347 #define UART_MODEM_RXRTSE_MASK 0x8u
mbed_official 146:f64d43ff0c18 12348 #define UART_MODEM_RXRTSE_SHIFT 3
mbed_official 146:f64d43ff0c18 12349 /* IR Bit Fields */
mbed_official 146:f64d43ff0c18 12350 #define UART_IR_TNP_MASK 0x3u
mbed_official 146:f64d43ff0c18 12351 #define UART_IR_TNP_SHIFT 0
mbed_official 146:f64d43ff0c18 12352 #define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
mbed_official 146:f64d43ff0c18 12353 #define UART_IR_IREN_MASK 0x4u
mbed_official 146:f64d43ff0c18 12354 #define UART_IR_IREN_SHIFT 2
mbed_official 146:f64d43ff0c18 12355 /* PFIFO Bit Fields */
mbed_official 146:f64d43ff0c18 12356 #define UART_PFIFO_RXFIFOSIZE_MASK 0x7u
mbed_official 146:f64d43ff0c18 12357 #define UART_PFIFO_RXFIFOSIZE_SHIFT 0
mbed_official 146:f64d43ff0c18 12358 #define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
mbed_official 146:f64d43ff0c18 12359 #define UART_PFIFO_RXFE_MASK 0x8u
mbed_official 146:f64d43ff0c18 12360 #define UART_PFIFO_RXFE_SHIFT 3
mbed_official 146:f64d43ff0c18 12361 #define UART_PFIFO_TXFIFOSIZE_MASK 0x70u
mbed_official 146:f64d43ff0c18 12362 #define UART_PFIFO_TXFIFOSIZE_SHIFT 4
mbed_official 146:f64d43ff0c18 12363 #define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
mbed_official 146:f64d43ff0c18 12364 #define UART_PFIFO_TXFE_MASK 0x80u
mbed_official 146:f64d43ff0c18 12365 #define UART_PFIFO_TXFE_SHIFT 7
mbed_official 146:f64d43ff0c18 12366 /* CFIFO Bit Fields */
mbed_official 146:f64d43ff0c18 12367 #define UART_CFIFO_RXUFE_MASK 0x1u
mbed_official 146:f64d43ff0c18 12368 #define UART_CFIFO_RXUFE_SHIFT 0
mbed_official 146:f64d43ff0c18 12369 #define UART_CFIFO_TXOFE_MASK 0x2u
mbed_official 146:f64d43ff0c18 12370 #define UART_CFIFO_TXOFE_SHIFT 1
mbed_official 146:f64d43ff0c18 12371 #define UART_CFIFO_RXOFE_MASK 0x4u
mbed_official 146:f64d43ff0c18 12372 #define UART_CFIFO_RXOFE_SHIFT 2
mbed_official 146:f64d43ff0c18 12373 #define UART_CFIFO_RXFLUSH_MASK 0x40u
mbed_official 146:f64d43ff0c18 12374 #define UART_CFIFO_RXFLUSH_SHIFT 6
mbed_official 146:f64d43ff0c18 12375 #define UART_CFIFO_TXFLUSH_MASK 0x80u
mbed_official 146:f64d43ff0c18 12376 #define UART_CFIFO_TXFLUSH_SHIFT 7
mbed_official 146:f64d43ff0c18 12377 /* SFIFO Bit Fields */
mbed_official 146:f64d43ff0c18 12378 #define UART_SFIFO_RXUF_MASK 0x1u
mbed_official 146:f64d43ff0c18 12379 #define UART_SFIFO_RXUF_SHIFT 0
mbed_official 146:f64d43ff0c18 12380 #define UART_SFIFO_TXOF_MASK 0x2u
mbed_official 146:f64d43ff0c18 12381 #define UART_SFIFO_TXOF_SHIFT 1
mbed_official 146:f64d43ff0c18 12382 #define UART_SFIFO_RXOF_MASK 0x4u
mbed_official 146:f64d43ff0c18 12383 #define UART_SFIFO_RXOF_SHIFT 2
mbed_official 146:f64d43ff0c18 12384 #define UART_SFIFO_RXEMPT_MASK 0x40u
mbed_official 146:f64d43ff0c18 12385 #define UART_SFIFO_RXEMPT_SHIFT 6
mbed_official 146:f64d43ff0c18 12386 #define UART_SFIFO_TXEMPT_MASK 0x80u
mbed_official 146:f64d43ff0c18 12387 #define UART_SFIFO_TXEMPT_SHIFT 7
mbed_official 146:f64d43ff0c18 12388 /* TWFIFO Bit Fields */
mbed_official 146:f64d43ff0c18 12389 #define UART_TWFIFO_TXWATER_MASK 0xFFu
mbed_official 146:f64d43ff0c18 12390 #define UART_TWFIFO_TXWATER_SHIFT 0
mbed_official 146:f64d43ff0c18 12391 #define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
mbed_official 146:f64d43ff0c18 12392 /* TCFIFO Bit Fields */
mbed_official 146:f64d43ff0c18 12393 #define UART_TCFIFO_TXCOUNT_MASK 0xFFu
mbed_official 146:f64d43ff0c18 12394 #define UART_TCFIFO_TXCOUNT_SHIFT 0
mbed_official 146:f64d43ff0c18 12395 #define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
mbed_official 146:f64d43ff0c18 12396 /* RWFIFO Bit Fields */
mbed_official 146:f64d43ff0c18 12397 #define UART_RWFIFO_RXWATER_MASK 0xFFu
mbed_official 146:f64d43ff0c18 12398 #define UART_RWFIFO_RXWATER_SHIFT 0
mbed_official 146:f64d43ff0c18 12399 #define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
mbed_official 146:f64d43ff0c18 12400 /* RCFIFO Bit Fields */
mbed_official 146:f64d43ff0c18 12401 #define UART_RCFIFO_RXCOUNT_MASK 0xFFu
mbed_official 146:f64d43ff0c18 12402 #define UART_RCFIFO_RXCOUNT_SHIFT 0
mbed_official 146:f64d43ff0c18 12403 #define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
mbed_official 146:f64d43ff0c18 12404 /* C7816 Bit Fields */
mbed_official 146:f64d43ff0c18 12405 #define UART_C7816_ISO_7816E_MASK 0x1u
mbed_official 146:f64d43ff0c18 12406 #define UART_C7816_ISO_7816E_SHIFT 0
mbed_official 146:f64d43ff0c18 12407 #define UART_C7816_TTYPE_MASK 0x2u
mbed_official 146:f64d43ff0c18 12408 #define UART_C7816_TTYPE_SHIFT 1
mbed_official 146:f64d43ff0c18 12409 #define UART_C7816_INIT_MASK 0x4u
mbed_official 146:f64d43ff0c18 12410 #define UART_C7816_INIT_SHIFT 2
mbed_official 146:f64d43ff0c18 12411 #define UART_C7816_ANACK_MASK 0x8u
mbed_official 146:f64d43ff0c18 12412 #define UART_C7816_ANACK_SHIFT 3
mbed_official 146:f64d43ff0c18 12413 #define UART_C7816_ONACK_MASK 0x10u
mbed_official 146:f64d43ff0c18 12414 #define UART_C7816_ONACK_SHIFT 4
mbed_official 146:f64d43ff0c18 12415 /* IE7816 Bit Fields */
mbed_official 146:f64d43ff0c18 12416 #define UART_IE7816_RXTE_MASK 0x1u
mbed_official 146:f64d43ff0c18 12417 #define UART_IE7816_RXTE_SHIFT 0
mbed_official 146:f64d43ff0c18 12418 #define UART_IE7816_TXTE_MASK 0x2u
mbed_official 146:f64d43ff0c18 12419 #define UART_IE7816_TXTE_SHIFT 1
mbed_official 146:f64d43ff0c18 12420 #define UART_IE7816_GTVE_MASK 0x4u
mbed_official 146:f64d43ff0c18 12421 #define UART_IE7816_GTVE_SHIFT 2
mbed_official 146:f64d43ff0c18 12422 #define UART_IE7816_INITDE_MASK 0x10u
mbed_official 146:f64d43ff0c18 12423 #define UART_IE7816_INITDE_SHIFT 4
mbed_official 146:f64d43ff0c18 12424 #define UART_IE7816_BWTE_MASK 0x20u
mbed_official 146:f64d43ff0c18 12425 #define UART_IE7816_BWTE_SHIFT 5
mbed_official 146:f64d43ff0c18 12426 #define UART_IE7816_CWTE_MASK 0x40u
mbed_official 146:f64d43ff0c18 12427 #define UART_IE7816_CWTE_SHIFT 6
mbed_official 146:f64d43ff0c18 12428 #define UART_IE7816_WTE_MASK 0x80u
mbed_official 146:f64d43ff0c18 12429 #define UART_IE7816_WTE_SHIFT 7
mbed_official 146:f64d43ff0c18 12430 /* IS7816 Bit Fields */
mbed_official 146:f64d43ff0c18 12431 #define UART_IS7816_RXT_MASK 0x1u
mbed_official 146:f64d43ff0c18 12432 #define UART_IS7816_RXT_SHIFT 0
mbed_official 146:f64d43ff0c18 12433 #define UART_IS7816_TXT_MASK 0x2u
mbed_official 146:f64d43ff0c18 12434 #define UART_IS7816_TXT_SHIFT 1
mbed_official 146:f64d43ff0c18 12435 #define UART_IS7816_GTV_MASK 0x4u
mbed_official 146:f64d43ff0c18 12436 #define UART_IS7816_GTV_SHIFT 2
mbed_official 146:f64d43ff0c18 12437 #define UART_IS7816_INITD_MASK 0x10u
mbed_official 146:f64d43ff0c18 12438 #define UART_IS7816_INITD_SHIFT 4
mbed_official 146:f64d43ff0c18 12439 #define UART_IS7816_BWT_MASK 0x20u
mbed_official 146:f64d43ff0c18 12440 #define UART_IS7816_BWT_SHIFT 5
mbed_official 146:f64d43ff0c18 12441 #define UART_IS7816_CWT_MASK 0x40u
mbed_official 146:f64d43ff0c18 12442 #define UART_IS7816_CWT_SHIFT 6
mbed_official 146:f64d43ff0c18 12443 #define UART_IS7816_WT_MASK 0x80u
mbed_official 146:f64d43ff0c18 12444 #define UART_IS7816_WT_SHIFT 7
mbed_official 146:f64d43ff0c18 12445 /* WP7816_T_TYPE0 Bit Fields */
mbed_official 146:f64d43ff0c18 12446 #define UART_WP7816_T_TYPE0_WI_MASK 0xFFu
mbed_official 146:f64d43ff0c18 12447 #define UART_WP7816_T_TYPE0_WI_SHIFT 0
mbed_official 146:f64d43ff0c18 12448 #define UART_WP7816_T_TYPE0_WI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE0_WI_SHIFT))&UART_WP7816_T_TYPE0_WI_MASK)
mbed_official 146:f64d43ff0c18 12449 /* WP7816_T_TYPE1 Bit Fields */
mbed_official 146:f64d43ff0c18 12450 #define UART_WP7816_T_TYPE1_BWI_MASK 0xFu
mbed_official 146:f64d43ff0c18 12451 #define UART_WP7816_T_TYPE1_BWI_SHIFT 0
mbed_official 146:f64d43ff0c18 12452 #define UART_WP7816_T_TYPE1_BWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_BWI_SHIFT))&UART_WP7816_T_TYPE1_BWI_MASK)
mbed_official 146:f64d43ff0c18 12453 #define UART_WP7816_T_TYPE1_CWI_MASK 0xF0u
mbed_official 146:f64d43ff0c18 12454 #define UART_WP7816_T_TYPE1_CWI_SHIFT 4
mbed_official 146:f64d43ff0c18 12455 #define UART_WP7816_T_TYPE1_CWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_CWI_SHIFT))&UART_WP7816_T_TYPE1_CWI_MASK)
mbed_official 146:f64d43ff0c18 12456 /* WN7816 Bit Fields */
mbed_official 146:f64d43ff0c18 12457 #define UART_WN7816_GTN_MASK 0xFFu
mbed_official 146:f64d43ff0c18 12458 #define UART_WN7816_GTN_SHIFT 0
mbed_official 146:f64d43ff0c18 12459 #define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
mbed_official 146:f64d43ff0c18 12460 /* WF7816 Bit Fields */
mbed_official 146:f64d43ff0c18 12461 #define UART_WF7816_GTFD_MASK 0xFFu
mbed_official 146:f64d43ff0c18 12462 #define UART_WF7816_GTFD_SHIFT 0
mbed_official 146:f64d43ff0c18 12463 #define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
mbed_official 146:f64d43ff0c18 12464 /* ET7816 Bit Fields */
mbed_official 146:f64d43ff0c18 12465 #define UART_ET7816_RXTHRESHOLD_MASK 0xFu
mbed_official 146:f64d43ff0c18 12466 #define UART_ET7816_RXTHRESHOLD_SHIFT 0
mbed_official 146:f64d43ff0c18 12467 #define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
mbed_official 146:f64d43ff0c18 12468 #define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
mbed_official 146:f64d43ff0c18 12469 #define UART_ET7816_TXTHRESHOLD_SHIFT 4
mbed_official 146:f64d43ff0c18 12470 #define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
mbed_official 146:f64d43ff0c18 12471 /* TL7816 Bit Fields */
mbed_official 146:f64d43ff0c18 12472 #define UART_TL7816_TLEN_MASK 0xFFu
mbed_official 146:f64d43ff0c18 12473 #define UART_TL7816_TLEN_SHIFT 0
mbed_official 146:f64d43ff0c18 12474 #define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
mbed_official 146:f64d43ff0c18 12475
mbed_official 146:f64d43ff0c18 12476 /*!
mbed_official 146:f64d43ff0c18 12477 * @}
mbed_official 146:f64d43ff0c18 12478 */ /* end of group UART_Register_Masks */
mbed_official 146:f64d43ff0c18 12479
mbed_official 146:f64d43ff0c18 12480
mbed_official 146:f64d43ff0c18 12481 /* UART - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 12482 /** Peripheral UART0 base address */
mbed_official 146:f64d43ff0c18 12483 #define UART0_BASE (0x4006A000u)
mbed_official 146:f64d43ff0c18 12484 /** Peripheral UART0 base pointer */
mbed_official 146:f64d43ff0c18 12485 #define UART0 ((UART_Type *)UART0_BASE)
mbed_official 146:f64d43ff0c18 12486 #define UART0_BASE_PTR (UART0)
mbed_official 146:f64d43ff0c18 12487 /** Peripheral UART1 base address */
mbed_official 146:f64d43ff0c18 12488 #define UART1_BASE (0x4006B000u)
mbed_official 146:f64d43ff0c18 12489 /** Peripheral UART1 base pointer */
mbed_official 146:f64d43ff0c18 12490 #define UART1 ((UART_Type *)UART1_BASE)
mbed_official 146:f64d43ff0c18 12491 #define UART1_BASE_PTR (UART1)
mbed_official 146:f64d43ff0c18 12492 /** Peripheral UART2 base address */
mbed_official 146:f64d43ff0c18 12493 #define UART2_BASE (0x4006C000u)
mbed_official 146:f64d43ff0c18 12494 /** Peripheral UART2 base pointer */
mbed_official 146:f64d43ff0c18 12495 #define UART2 ((UART_Type *)UART2_BASE)
mbed_official 146:f64d43ff0c18 12496 #define UART2_BASE_PTR (UART2)
mbed_official 146:f64d43ff0c18 12497 /** Peripheral UART3 base address */
mbed_official 146:f64d43ff0c18 12498 #define UART3_BASE (0x4006D000u)
mbed_official 146:f64d43ff0c18 12499 /** Peripheral UART3 base pointer */
mbed_official 146:f64d43ff0c18 12500 #define UART3 ((UART_Type *)UART3_BASE)
mbed_official 146:f64d43ff0c18 12501 #define UART3_BASE_PTR (UART3)
mbed_official 146:f64d43ff0c18 12502 /** Peripheral UART4 base address */
mbed_official 146:f64d43ff0c18 12503 #define UART4_BASE (0x400EA000u)
mbed_official 146:f64d43ff0c18 12504 /** Peripheral UART4 base pointer */
mbed_official 146:f64d43ff0c18 12505 #define UART4 ((UART_Type *)UART4_BASE)
mbed_official 146:f64d43ff0c18 12506 #define UART4_BASE_PTR (UART4)
mbed_official 146:f64d43ff0c18 12507 /** Peripheral UART5 base address */
mbed_official 146:f64d43ff0c18 12508 #define UART5_BASE (0x400EB000u)
mbed_official 146:f64d43ff0c18 12509 /** Peripheral UART5 base pointer */
mbed_official 146:f64d43ff0c18 12510 #define UART5 ((UART_Type *)UART5_BASE)
mbed_official 146:f64d43ff0c18 12511 #define UART5_BASE_PTR (UART5)
mbed_official 146:f64d43ff0c18 12512 /** Array initializer of UART peripheral base pointers */
mbed_official 146:f64d43ff0c18 12513 #define UART_BASES { UART0, UART1, UART2, UART3, UART4, UART5 }
mbed_official 146:f64d43ff0c18 12514
mbed_official 146:f64d43ff0c18 12515 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 12516 -- UART - Register accessor macros
mbed_official 146:f64d43ff0c18 12517 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 12518
mbed_official 146:f64d43ff0c18 12519 /*!
mbed_official 146:f64d43ff0c18 12520 * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
mbed_official 146:f64d43ff0c18 12521 * @{
mbed_official 146:f64d43ff0c18 12522 */
mbed_official 146:f64d43ff0c18 12523
mbed_official 146:f64d43ff0c18 12524
mbed_official 146:f64d43ff0c18 12525 /* UART - Register instance definitions */
mbed_official 146:f64d43ff0c18 12526 /* UART0 */
mbed_official 146:f64d43ff0c18 12527 #define UART0_BDH UART_BDH_REG(UART0)
mbed_official 146:f64d43ff0c18 12528 #define UART0_BDL UART_BDL_REG(UART0)
mbed_official 146:f64d43ff0c18 12529 #define UART0_C1 UART_C1_REG(UART0)
mbed_official 146:f64d43ff0c18 12530 #define UART0_C2 UART_C2_REG(UART0)
mbed_official 146:f64d43ff0c18 12531 #define UART0_S1 UART_S1_REG(UART0)
mbed_official 146:f64d43ff0c18 12532 #define UART0_S2 UART_S2_REG(UART0)
mbed_official 146:f64d43ff0c18 12533 #define UART0_C3 UART_C3_REG(UART0)
mbed_official 146:f64d43ff0c18 12534 #define UART0_D UART_D_REG(UART0)
mbed_official 146:f64d43ff0c18 12535 #define UART0_MA1 UART_MA1_REG(UART0)
mbed_official 146:f64d43ff0c18 12536 #define UART0_MA2 UART_MA2_REG(UART0)
mbed_official 146:f64d43ff0c18 12537 #define UART0_C4 UART_C4_REG(UART0)
mbed_official 146:f64d43ff0c18 12538 #define UART0_C5 UART_C5_REG(UART0)
mbed_official 146:f64d43ff0c18 12539 #define UART0_ED UART_ED_REG(UART0)
mbed_official 146:f64d43ff0c18 12540 #define UART0_MODEM UART_MODEM_REG(UART0)
mbed_official 146:f64d43ff0c18 12541 #define UART0_IR UART_IR_REG(UART0)
mbed_official 146:f64d43ff0c18 12542 #define UART0_PFIFO UART_PFIFO_REG(UART0)
mbed_official 146:f64d43ff0c18 12543 #define UART0_CFIFO UART_CFIFO_REG(UART0)
mbed_official 146:f64d43ff0c18 12544 #define UART0_SFIFO UART_SFIFO_REG(UART0)
mbed_official 146:f64d43ff0c18 12545 #define UART0_TWFIFO UART_TWFIFO_REG(UART0)
mbed_official 146:f64d43ff0c18 12546 #define UART0_TCFIFO UART_TCFIFO_REG(UART0)
mbed_official 146:f64d43ff0c18 12547 #define UART0_RWFIFO UART_RWFIFO_REG(UART0)
mbed_official 146:f64d43ff0c18 12548 #define UART0_RCFIFO UART_RCFIFO_REG(UART0)
mbed_official 146:f64d43ff0c18 12549 #define UART0_C7816 UART_C7816_REG(UART0)
mbed_official 146:f64d43ff0c18 12550 #define UART0_IE7816 UART_IE7816_REG(UART0)
mbed_official 146:f64d43ff0c18 12551 #define UART0_IS7816 UART_IS7816_REG(UART0)
mbed_official 146:f64d43ff0c18 12552 #define UART0_WP7816T0 UART_WP7816_T_TYPE0_REG(UART0)
mbed_official 146:f64d43ff0c18 12553 #define UART0_WP7816T1 UART_WP7816_T_TYPE1_REG(UART0)
mbed_official 146:f64d43ff0c18 12554 #define UART0_WN7816 UART_WN7816_REG(UART0)
mbed_official 146:f64d43ff0c18 12555 #define UART0_WF7816 UART_WF7816_REG(UART0)
mbed_official 146:f64d43ff0c18 12556 #define UART0_ET7816 UART_ET7816_REG(UART0)
mbed_official 146:f64d43ff0c18 12557 #define UART0_TL7816 UART_TL7816_REG(UART0)
mbed_official 146:f64d43ff0c18 12558 /* UART1 */
mbed_official 146:f64d43ff0c18 12559 #define UART1_BDH UART_BDH_REG(UART1)
mbed_official 146:f64d43ff0c18 12560 #define UART1_BDL UART_BDL_REG(UART1)
mbed_official 146:f64d43ff0c18 12561 #define UART1_C1 UART_C1_REG(UART1)
mbed_official 146:f64d43ff0c18 12562 #define UART1_C2 UART_C2_REG(UART1)
mbed_official 146:f64d43ff0c18 12563 #define UART1_S1 UART_S1_REG(UART1)
mbed_official 146:f64d43ff0c18 12564 #define UART1_S2 UART_S2_REG(UART1)
mbed_official 146:f64d43ff0c18 12565 #define UART1_C3 UART_C3_REG(UART1)
mbed_official 146:f64d43ff0c18 12566 #define UART1_D UART_D_REG(UART1)
mbed_official 146:f64d43ff0c18 12567 #define UART1_MA1 UART_MA1_REG(UART1)
mbed_official 146:f64d43ff0c18 12568 #define UART1_MA2 UART_MA2_REG(UART1)
mbed_official 146:f64d43ff0c18 12569 #define UART1_C4 UART_C4_REG(UART1)
mbed_official 146:f64d43ff0c18 12570 #define UART1_C5 UART_C5_REG(UART1)
mbed_official 146:f64d43ff0c18 12571 #define UART1_ED UART_ED_REG(UART1)
mbed_official 146:f64d43ff0c18 12572 #define UART1_MODEM UART_MODEM_REG(UART1)
mbed_official 146:f64d43ff0c18 12573 #define UART1_IR UART_IR_REG(UART1)
mbed_official 146:f64d43ff0c18 12574 #define UART1_PFIFO UART_PFIFO_REG(UART1)
mbed_official 146:f64d43ff0c18 12575 #define UART1_CFIFO UART_CFIFO_REG(UART1)
mbed_official 146:f64d43ff0c18 12576 #define UART1_SFIFO UART_SFIFO_REG(UART1)
mbed_official 146:f64d43ff0c18 12577 #define UART1_TWFIFO UART_TWFIFO_REG(UART1)
mbed_official 146:f64d43ff0c18 12578 #define UART1_TCFIFO UART_TCFIFO_REG(UART1)
mbed_official 146:f64d43ff0c18 12579 #define UART1_RWFIFO UART_RWFIFO_REG(UART1)
mbed_official 146:f64d43ff0c18 12580 #define UART1_RCFIFO UART_RCFIFO_REG(UART1)
mbed_official 146:f64d43ff0c18 12581 /* UART2 */
mbed_official 146:f64d43ff0c18 12582 #define UART2_BDH UART_BDH_REG(UART2)
mbed_official 146:f64d43ff0c18 12583 #define UART2_BDL UART_BDL_REG(UART2)
mbed_official 146:f64d43ff0c18 12584 #define UART2_C1 UART_C1_REG(UART2)
mbed_official 146:f64d43ff0c18 12585 #define UART2_C2 UART_C2_REG(UART2)
mbed_official 146:f64d43ff0c18 12586 #define UART2_S1 UART_S1_REG(UART2)
mbed_official 146:f64d43ff0c18 12587 #define UART2_S2 UART_S2_REG(UART2)
mbed_official 146:f64d43ff0c18 12588 #define UART2_C3 UART_C3_REG(UART2)
mbed_official 146:f64d43ff0c18 12589 #define UART2_D UART_D_REG(UART2)
mbed_official 146:f64d43ff0c18 12590 #define UART2_MA1 UART_MA1_REG(UART2)
mbed_official 146:f64d43ff0c18 12591 #define UART2_MA2 UART_MA2_REG(UART2)
mbed_official 146:f64d43ff0c18 12592 #define UART2_C4 UART_C4_REG(UART2)
mbed_official 146:f64d43ff0c18 12593 #define UART2_C5 UART_C5_REG(UART2)
mbed_official 146:f64d43ff0c18 12594 #define UART2_ED UART_ED_REG(UART2)
mbed_official 146:f64d43ff0c18 12595 #define UART2_MODEM UART_MODEM_REG(UART2)
mbed_official 146:f64d43ff0c18 12596 #define UART2_IR UART_IR_REG(UART2)
mbed_official 146:f64d43ff0c18 12597 #define UART2_PFIFO UART_PFIFO_REG(UART2)
mbed_official 146:f64d43ff0c18 12598 #define UART2_CFIFO UART_CFIFO_REG(UART2)
mbed_official 146:f64d43ff0c18 12599 #define UART2_SFIFO UART_SFIFO_REG(UART2)
mbed_official 146:f64d43ff0c18 12600 #define UART2_TWFIFO UART_TWFIFO_REG(UART2)
mbed_official 146:f64d43ff0c18 12601 #define UART2_TCFIFO UART_TCFIFO_REG(UART2)
mbed_official 146:f64d43ff0c18 12602 #define UART2_RWFIFO UART_RWFIFO_REG(UART2)
mbed_official 146:f64d43ff0c18 12603 #define UART2_RCFIFO UART_RCFIFO_REG(UART2)
mbed_official 146:f64d43ff0c18 12604 /* UART3 */
mbed_official 146:f64d43ff0c18 12605 #define UART3_BDH UART_BDH_REG(UART3)
mbed_official 146:f64d43ff0c18 12606 #define UART3_BDL UART_BDL_REG(UART3)
mbed_official 146:f64d43ff0c18 12607 #define UART3_C1 UART_C1_REG(UART3)
mbed_official 146:f64d43ff0c18 12608 #define UART3_C2 UART_C2_REG(UART3)
mbed_official 146:f64d43ff0c18 12609 #define UART3_S1 UART_S1_REG(UART3)
mbed_official 146:f64d43ff0c18 12610 #define UART3_S2 UART_S2_REG(UART3)
mbed_official 146:f64d43ff0c18 12611 #define UART3_C3 UART_C3_REG(UART3)
mbed_official 146:f64d43ff0c18 12612 #define UART3_D UART_D_REG(UART3)
mbed_official 146:f64d43ff0c18 12613 #define UART3_MA1 UART_MA1_REG(UART3)
mbed_official 146:f64d43ff0c18 12614 #define UART3_MA2 UART_MA2_REG(UART3)
mbed_official 146:f64d43ff0c18 12615 #define UART3_C4 UART_C4_REG(UART3)
mbed_official 146:f64d43ff0c18 12616 #define UART3_C5 UART_C5_REG(UART3)
mbed_official 146:f64d43ff0c18 12617 #define UART3_ED UART_ED_REG(UART3)
mbed_official 146:f64d43ff0c18 12618 #define UART3_MODEM UART_MODEM_REG(UART3)
mbed_official 146:f64d43ff0c18 12619 #define UART3_IR UART_IR_REG(UART3)
mbed_official 146:f64d43ff0c18 12620 #define UART3_PFIFO UART_PFIFO_REG(UART3)
mbed_official 146:f64d43ff0c18 12621 #define UART3_CFIFO UART_CFIFO_REG(UART3)
mbed_official 146:f64d43ff0c18 12622 #define UART3_SFIFO UART_SFIFO_REG(UART3)
mbed_official 146:f64d43ff0c18 12623 #define UART3_TWFIFO UART_TWFIFO_REG(UART3)
mbed_official 146:f64d43ff0c18 12624 #define UART3_TCFIFO UART_TCFIFO_REG(UART3)
mbed_official 146:f64d43ff0c18 12625 #define UART3_RWFIFO UART_RWFIFO_REG(UART3)
mbed_official 146:f64d43ff0c18 12626 #define UART3_RCFIFO UART_RCFIFO_REG(UART3)
mbed_official 146:f64d43ff0c18 12627 /* UART4 */
mbed_official 146:f64d43ff0c18 12628 #define UART4_BDH UART_BDH_REG(UART4)
mbed_official 146:f64d43ff0c18 12629 #define UART4_BDL UART_BDL_REG(UART4)
mbed_official 146:f64d43ff0c18 12630 #define UART4_C1 UART_C1_REG(UART4)
mbed_official 146:f64d43ff0c18 12631 #define UART4_C2 UART_C2_REG(UART4)
mbed_official 146:f64d43ff0c18 12632 #define UART4_S1 UART_S1_REG(UART4)
mbed_official 146:f64d43ff0c18 12633 #define UART4_S2 UART_S2_REG(UART4)
mbed_official 146:f64d43ff0c18 12634 #define UART4_C3 UART_C3_REG(UART4)
mbed_official 146:f64d43ff0c18 12635 #define UART4_D UART_D_REG(UART4)
mbed_official 146:f64d43ff0c18 12636 #define UART4_MA1 UART_MA1_REG(UART4)
mbed_official 146:f64d43ff0c18 12637 #define UART4_MA2 UART_MA2_REG(UART4)
mbed_official 146:f64d43ff0c18 12638 #define UART4_C4 UART_C4_REG(UART4)
mbed_official 146:f64d43ff0c18 12639 #define UART4_C5 UART_C5_REG(UART4)
mbed_official 146:f64d43ff0c18 12640 #define UART4_ED UART_ED_REG(UART4)
mbed_official 146:f64d43ff0c18 12641 #define UART4_MODEM UART_MODEM_REG(UART4)
mbed_official 146:f64d43ff0c18 12642 #define UART4_IR UART_IR_REG(UART4)
mbed_official 146:f64d43ff0c18 12643 #define UART4_PFIFO UART_PFIFO_REG(UART4)
mbed_official 146:f64d43ff0c18 12644 #define UART4_CFIFO UART_CFIFO_REG(UART4)
mbed_official 146:f64d43ff0c18 12645 #define UART4_SFIFO UART_SFIFO_REG(UART4)
mbed_official 146:f64d43ff0c18 12646 #define UART4_TWFIFO UART_TWFIFO_REG(UART4)
mbed_official 146:f64d43ff0c18 12647 #define UART4_TCFIFO UART_TCFIFO_REG(UART4)
mbed_official 146:f64d43ff0c18 12648 #define UART4_RWFIFO UART_RWFIFO_REG(UART4)
mbed_official 146:f64d43ff0c18 12649 #define UART4_RCFIFO UART_RCFIFO_REG(UART4)
mbed_official 146:f64d43ff0c18 12650 /* UART5 */
mbed_official 146:f64d43ff0c18 12651 #define UART5_BDH UART_BDH_REG(UART5)
mbed_official 146:f64d43ff0c18 12652 #define UART5_BDL UART_BDL_REG(UART5)
mbed_official 146:f64d43ff0c18 12653 #define UART5_C1 UART_C1_REG(UART5)
mbed_official 146:f64d43ff0c18 12654 #define UART5_C2 UART_C2_REG(UART5)
mbed_official 146:f64d43ff0c18 12655 #define UART5_S1 UART_S1_REG(UART5)
mbed_official 146:f64d43ff0c18 12656 #define UART5_S2 UART_S2_REG(UART5)
mbed_official 146:f64d43ff0c18 12657 #define UART5_C3 UART_C3_REG(UART5)
mbed_official 146:f64d43ff0c18 12658 #define UART5_D UART_D_REG(UART5)
mbed_official 146:f64d43ff0c18 12659 #define UART5_MA1 UART_MA1_REG(UART5)
mbed_official 146:f64d43ff0c18 12660 #define UART5_MA2 UART_MA2_REG(UART5)
mbed_official 146:f64d43ff0c18 12661 #define UART5_C4 UART_C4_REG(UART5)
mbed_official 146:f64d43ff0c18 12662 #define UART5_C5 UART_C5_REG(UART5)
mbed_official 146:f64d43ff0c18 12663 #define UART5_ED UART_ED_REG(UART5)
mbed_official 146:f64d43ff0c18 12664 #define UART5_MODEM UART_MODEM_REG(UART5)
mbed_official 146:f64d43ff0c18 12665 #define UART5_IR UART_IR_REG(UART5)
mbed_official 146:f64d43ff0c18 12666 #define UART5_PFIFO UART_PFIFO_REG(UART5)
mbed_official 146:f64d43ff0c18 12667 #define UART5_CFIFO UART_CFIFO_REG(UART5)
mbed_official 146:f64d43ff0c18 12668 #define UART5_SFIFO UART_SFIFO_REG(UART5)
mbed_official 146:f64d43ff0c18 12669 #define UART5_TWFIFO UART_TWFIFO_REG(UART5)
mbed_official 146:f64d43ff0c18 12670 #define UART5_TCFIFO UART_TCFIFO_REG(UART5)
mbed_official 146:f64d43ff0c18 12671 #define UART5_RWFIFO UART_RWFIFO_REG(UART5)
mbed_official 146:f64d43ff0c18 12672 #define UART5_RCFIFO UART_RCFIFO_REG(UART5)
mbed_official 146:f64d43ff0c18 12673
mbed_official 146:f64d43ff0c18 12674 /*!
mbed_official 146:f64d43ff0c18 12675 * @}
mbed_official 146:f64d43ff0c18 12676 */ /* end of group UART_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 12677
mbed_official 146:f64d43ff0c18 12678
mbed_official 146:f64d43ff0c18 12679 /*!
mbed_official 146:f64d43ff0c18 12680 * @}
mbed_official 146:f64d43ff0c18 12681 */ /* end of group UART_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 12682
mbed_official 146:f64d43ff0c18 12683
mbed_official 146:f64d43ff0c18 12684 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 12685 -- USB Peripheral Access Layer
mbed_official 146:f64d43ff0c18 12686 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 12687
mbed_official 146:f64d43ff0c18 12688 /*!
mbed_official 146:f64d43ff0c18 12689 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
mbed_official 146:f64d43ff0c18 12690 * @{
mbed_official 146:f64d43ff0c18 12691 */
mbed_official 146:f64d43ff0c18 12692
mbed_official 146:f64d43ff0c18 12693 /** USB - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 12694 typedef struct {
mbed_official 146:f64d43ff0c18 12695 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
mbed_official 146:f64d43ff0c18 12696 uint8_t RESERVED_0[3];
mbed_official 146:f64d43ff0c18 12697 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
mbed_official 146:f64d43ff0c18 12698 uint8_t RESERVED_1[3];
mbed_official 146:f64d43ff0c18 12699 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
mbed_official 146:f64d43ff0c18 12700 uint8_t RESERVED_2[3];
mbed_official 146:f64d43ff0c18 12701 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
mbed_official 146:f64d43ff0c18 12702 uint8_t RESERVED_3[3];
mbed_official 146:f64d43ff0c18 12703 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
mbed_official 146:f64d43ff0c18 12704 uint8_t RESERVED_4[3];
mbed_official 146:f64d43ff0c18 12705 __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */
mbed_official 146:f64d43ff0c18 12706 uint8_t RESERVED_5[3];
mbed_official 146:f64d43ff0c18 12707 __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
mbed_official 146:f64d43ff0c18 12708 uint8_t RESERVED_6[3];
mbed_official 146:f64d43ff0c18 12709 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
mbed_official 146:f64d43ff0c18 12710 uint8_t RESERVED_7[99];
mbed_official 146:f64d43ff0c18 12711 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
mbed_official 146:f64d43ff0c18 12712 uint8_t RESERVED_8[3];
mbed_official 146:f64d43ff0c18 12713 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
mbed_official 146:f64d43ff0c18 12714 uint8_t RESERVED_9[3];
mbed_official 146:f64d43ff0c18 12715 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
mbed_official 146:f64d43ff0c18 12716 uint8_t RESERVED_10[3];
mbed_official 146:f64d43ff0c18 12717 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
mbed_official 146:f64d43ff0c18 12718 uint8_t RESERVED_11[3];
mbed_official 146:f64d43ff0c18 12719 __I uint8_t STAT; /**< Status register, offset: 0x90 */
mbed_official 146:f64d43ff0c18 12720 uint8_t RESERVED_12[3];
mbed_official 146:f64d43ff0c18 12721 __IO uint8_t CTL; /**< Control register, offset: 0x94 */
mbed_official 146:f64d43ff0c18 12722 uint8_t RESERVED_13[3];
mbed_official 146:f64d43ff0c18 12723 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
mbed_official 146:f64d43ff0c18 12724 uint8_t RESERVED_14[3];
mbed_official 146:f64d43ff0c18 12725 __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
mbed_official 146:f64d43ff0c18 12726 uint8_t RESERVED_15[3];
mbed_official 146:f64d43ff0c18 12727 __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
mbed_official 146:f64d43ff0c18 12728 uint8_t RESERVED_16[3];
mbed_official 146:f64d43ff0c18 12729 __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
mbed_official 146:f64d43ff0c18 12730 uint8_t RESERVED_17[3];
mbed_official 146:f64d43ff0c18 12731 __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
mbed_official 146:f64d43ff0c18 12732 uint8_t RESERVED_18[3];
mbed_official 146:f64d43ff0c18 12733 __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */
mbed_official 146:f64d43ff0c18 12734 uint8_t RESERVED_19[3];
mbed_official 146:f64d43ff0c18 12735 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
mbed_official 146:f64d43ff0c18 12736 uint8_t RESERVED_20[3];
mbed_official 146:f64d43ff0c18 12737 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
mbed_official 146:f64d43ff0c18 12738 uint8_t RESERVED_21[11];
mbed_official 146:f64d43ff0c18 12739 struct { /* offset: 0xC0, array step: 0x4 */
mbed_official 146:f64d43ff0c18 12740 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
mbed_official 146:f64d43ff0c18 12741 uint8_t RESERVED_0[3];
mbed_official 146:f64d43ff0c18 12742 } ENDPOINT[16];
mbed_official 146:f64d43ff0c18 12743 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
mbed_official 146:f64d43ff0c18 12744 uint8_t RESERVED_22[3];
mbed_official 146:f64d43ff0c18 12745 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
mbed_official 146:f64d43ff0c18 12746 uint8_t RESERVED_23[3];
mbed_official 146:f64d43ff0c18 12747 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
mbed_official 146:f64d43ff0c18 12748 uint8_t RESERVED_24[3];
mbed_official 146:f64d43ff0c18 12749 __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
mbed_official 146:f64d43ff0c18 12750 uint8_t RESERVED_25[7];
mbed_official 146:f64d43ff0c18 12751 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
mbed_official 146:f64d43ff0c18 12752 uint8_t RESERVED_26[43];
mbed_official 146:f64d43ff0c18 12753 __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */
mbed_official 146:f64d43ff0c18 12754 uint8_t RESERVED_27[3];
mbed_official 146:f64d43ff0c18 12755 __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */
mbed_official 146:f64d43ff0c18 12756 uint8_t RESERVED_28[23];
mbed_official 146:f64d43ff0c18 12757 __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
mbed_official 146:f64d43ff0c18 12758 } USB_Type, *USB_MemMapPtr;
mbed_official 146:f64d43ff0c18 12759
mbed_official 146:f64d43ff0c18 12760 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 12761 -- USB - Register accessor macros
mbed_official 146:f64d43ff0c18 12762 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 12763
mbed_official 146:f64d43ff0c18 12764 /*!
mbed_official 146:f64d43ff0c18 12765 * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
mbed_official 146:f64d43ff0c18 12766 * @{
mbed_official 146:f64d43ff0c18 12767 */
mbed_official 146:f64d43ff0c18 12768
mbed_official 146:f64d43ff0c18 12769
mbed_official 146:f64d43ff0c18 12770 /* USB - Register accessors */
mbed_official 146:f64d43ff0c18 12771 #define USB_PERID_REG(base) ((base)->PERID)
mbed_official 146:f64d43ff0c18 12772 #define USB_IDCOMP_REG(base) ((base)->IDCOMP)
mbed_official 146:f64d43ff0c18 12773 #define USB_REV_REG(base) ((base)->REV)
mbed_official 146:f64d43ff0c18 12774 #define USB_ADDINFO_REG(base) ((base)->ADDINFO)
mbed_official 146:f64d43ff0c18 12775 #define USB_OTGISTAT_REG(base) ((base)->OTGISTAT)
mbed_official 146:f64d43ff0c18 12776 #define USB_OTGICR_REG(base) ((base)->OTGICR)
mbed_official 146:f64d43ff0c18 12777 #define USB_OTGSTAT_REG(base) ((base)->OTGSTAT)
mbed_official 146:f64d43ff0c18 12778 #define USB_OTGCTL_REG(base) ((base)->OTGCTL)
mbed_official 146:f64d43ff0c18 12779 #define USB_ISTAT_REG(base) ((base)->ISTAT)
mbed_official 146:f64d43ff0c18 12780 #define USB_INTEN_REG(base) ((base)->INTEN)
mbed_official 146:f64d43ff0c18 12781 #define USB_ERRSTAT_REG(base) ((base)->ERRSTAT)
mbed_official 146:f64d43ff0c18 12782 #define USB_ERREN_REG(base) ((base)->ERREN)
mbed_official 146:f64d43ff0c18 12783 #define USB_STAT_REG(base) ((base)->STAT)
mbed_official 146:f64d43ff0c18 12784 #define USB_CTL_REG(base) ((base)->CTL)
mbed_official 146:f64d43ff0c18 12785 #define USB_ADDR_REG(base) ((base)->ADDR)
mbed_official 146:f64d43ff0c18 12786 #define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1)
mbed_official 146:f64d43ff0c18 12787 #define USB_FRMNUML_REG(base) ((base)->FRMNUML)
mbed_official 146:f64d43ff0c18 12788 #define USB_FRMNUMH_REG(base) ((base)->FRMNUMH)
mbed_official 146:f64d43ff0c18 12789 #define USB_TOKEN_REG(base) ((base)->TOKEN)
mbed_official 146:f64d43ff0c18 12790 #define USB_SOFTHLD_REG(base) ((base)->SOFTHLD)
mbed_official 146:f64d43ff0c18 12791 #define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2)
mbed_official 146:f64d43ff0c18 12792 #define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3)
mbed_official 146:f64d43ff0c18 12793 #define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT)
mbed_official 146:f64d43ff0c18 12794 #define USB_USBCTRL_REG(base) ((base)->USBCTRL)
mbed_official 146:f64d43ff0c18 12795 #define USB_OBSERVE_REG(base) ((base)->OBSERVE)
mbed_official 146:f64d43ff0c18 12796 #define USB_CONTROL_REG(base) ((base)->CONTROL)
mbed_official 146:f64d43ff0c18 12797 #define USB_USBTRC0_REG(base) ((base)->USBTRC0)
mbed_official 146:f64d43ff0c18 12798 #define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST)
mbed_official 146:f64d43ff0c18 12799 #define USB_CLK_RECOVER_CTRL_REG(base) ((base)->CLK_RECOVER_CTRL)
mbed_official 146:f64d43ff0c18 12800 #define USB_CLK_RECOVER_IRC_EN_REG(base) ((base)->CLK_RECOVER_IRC_EN)
mbed_official 146:f64d43ff0c18 12801 #define USB_CLK_RECOVER_INT_STATUS_REG(base) ((base)->CLK_RECOVER_INT_STATUS)
mbed_official 146:f64d43ff0c18 12802
mbed_official 146:f64d43ff0c18 12803 /*!
mbed_official 146:f64d43ff0c18 12804 * @}
mbed_official 146:f64d43ff0c18 12805 */ /* end of group USB_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 12806
mbed_official 146:f64d43ff0c18 12807
mbed_official 146:f64d43ff0c18 12808 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 12809 -- USB Register Masks
mbed_official 146:f64d43ff0c18 12810 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 12811
mbed_official 146:f64d43ff0c18 12812 /*!
mbed_official 146:f64d43ff0c18 12813 * @addtogroup USB_Register_Masks USB Register Masks
mbed_official 146:f64d43ff0c18 12814 * @{
mbed_official 146:f64d43ff0c18 12815 */
mbed_official 146:f64d43ff0c18 12816
mbed_official 146:f64d43ff0c18 12817 /* PERID Bit Fields */
mbed_official 146:f64d43ff0c18 12818 #define USB_PERID_ID_MASK 0x3Fu
mbed_official 146:f64d43ff0c18 12819 #define USB_PERID_ID_SHIFT 0
mbed_official 146:f64d43ff0c18 12820 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
mbed_official 146:f64d43ff0c18 12821 /* IDCOMP Bit Fields */
mbed_official 146:f64d43ff0c18 12822 #define USB_IDCOMP_NID_MASK 0x3Fu
mbed_official 146:f64d43ff0c18 12823 #define USB_IDCOMP_NID_SHIFT 0
mbed_official 146:f64d43ff0c18 12824 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
mbed_official 146:f64d43ff0c18 12825 /* REV Bit Fields */
mbed_official 146:f64d43ff0c18 12826 #define USB_REV_REV_MASK 0xFFu
mbed_official 146:f64d43ff0c18 12827 #define USB_REV_REV_SHIFT 0
mbed_official 146:f64d43ff0c18 12828 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
mbed_official 146:f64d43ff0c18 12829 /* ADDINFO Bit Fields */
mbed_official 146:f64d43ff0c18 12830 #define USB_ADDINFO_IEHOST_MASK 0x1u
mbed_official 146:f64d43ff0c18 12831 #define USB_ADDINFO_IEHOST_SHIFT 0
mbed_official 146:f64d43ff0c18 12832 #define USB_ADDINFO_IRQNUM_MASK 0xF8u
mbed_official 146:f64d43ff0c18 12833 #define USB_ADDINFO_IRQNUM_SHIFT 3
mbed_official 146:f64d43ff0c18 12834 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
mbed_official 146:f64d43ff0c18 12835 /* OTGISTAT Bit Fields */
mbed_official 146:f64d43ff0c18 12836 #define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
mbed_official 146:f64d43ff0c18 12837 #define USB_OTGISTAT_AVBUSCHG_SHIFT 0
mbed_official 146:f64d43ff0c18 12838 #define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
mbed_official 146:f64d43ff0c18 12839 #define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
mbed_official 146:f64d43ff0c18 12840 #define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
mbed_official 146:f64d43ff0c18 12841 #define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
mbed_official 146:f64d43ff0c18 12842 #define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
mbed_official 146:f64d43ff0c18 12843 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
mbed_official 146:f64d43ff0c18 12844 #define USB_OTGISTAT_ONEMSEC_MASK 0x40u
mbed_official 146:f64d43ff0c18 12845 #define USB_OTGISTAT_ONEMSEC_SHIFT 6
mbed_official 146:f64d43ff0c18 12846 #define USB_OTGISTAT_IDCHG_MASK 0x80u
mbed_official 146:f64d43ff0c18 12847 #define USB_OTGISTAT_IDCHG_SHIFT 7
mbed_official 146:f64d43ff0c18 12848 /* OTGICR Bit Fields */
mbed_official 146:f64d43ff0c18 12849 #define USB_OTGICR_AVBUSEN_MASK 0x1u
mbed_official 146:f64d43ff0c18 12850 #define USB_OTGICR_AVBUSEN_SHIFT 0
mbed_official 146:f64d43ff0c18 12851 #define USB_OTGICR_BSESSEN_MASK 0x4u
mbed_official 146:f64d43ff0c18 12852 #define USB_OTGICR_BSESSEN_SHIFT 2
mbed_official 146:f64d43ff0c18 12853 #define USB_OTGICR_SESSVLDEN_MASK 0x8u
mbed_official 146:f64d43ff0c18 12854 #define USB_OTGICR_SESSVLDEN_SHIFT 3
mbed_official 146:f64d43ff0c18 12855 #define USB_OTGICR_LINESTATEEN_MASK 0x20u
mbed_official 146:f64d43ff0c18 12856 #define USB_OTGICR_LINESTATEEN_SHIFT 5
mbed_official 146:f64d43ff0c18 12857 #define USB_OTGICR_ONEMSECEN_MASK 0x40u
mbed_official 146:f64d43ff0c18 12858 #define USB_OTGICR_ONEMSECEN_SHIFT 6
mbed_official 146:f64d43ff0c18 12859 #define USB_OTGICR_IDEN_MASK 0x80u
mbed_official 146:f64d43ff0c18 12860 #define USB_OTGICR_IDEN_SHIFT 7
mbed_official 146:f64d43ff0c18 12861 /* OTGSTAT Bit Fields */
mbed_official 146:f64d43ff0c18 12862 #define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
mbed_official 146:f64d43ff0c18 12863 #define USB_OTGSTAT_AVBUSVLD_SHIFT 0
mbed_official 146:f64d43ff0c18 12864 #define USB_OTGSTAT_BSESSEND_MASK 0x4u
mbed_official 146:f64d43ff0c18 12865 #define USB_OTGSTAT_BSESSEND_SHIFT 2
mbed_official 146:f64d43ff0c18 12866 #define USB_OTGSTAT_SESS_VLD_MASK 0x8u
mbed_official 146:f64d43ff0c18 12867 #define USB_OTGSTAT_SESS_VLD_SHIFT 3
mbed_official 146:f64d43ff0c18 12868 #define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
mbed_official 146:f64d43ff0c18 12869 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
mbed_official 146:f64d43ff0c18 12870 #define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
mbed_official 146:f64d43ff0c18 12871 #define USB_OTGSTAT_ONEMSECEN_SHIFT 6
mbed_official 146:f64d43ff0c18 12872 #define USB_OTGSTAT_ID_MASK 0x80u
mbed_official 146:f64d43ff0c18 12873 #define USB_OTGSTAT_ID_SHIFT 7
mbed_official 146:f64d43ff0c18 12874 /* OTGCTL Bit Fields */
mbed_official 146:f64d43ff0c18 12875 #define USB_OTGCTL_OTGEN_MASK 0x4u
mbed_official 146:f64d43ff0c18 12876 #define USB_OTGCTL_OTGEN_SHIFT 2
mbed_official 146:f64d43ff0c18 12877 #define USB_OTGCTL_DMLOW_MASK 0x10u
mbed_official 146:f64d43ff0c18 12878 #define USB_OTGCTL_DMLOW_SHIFT 4
mbed_official 146:f64d43ff0c18 12879 #define USB_OTGCTL_DPLOW_MASK 0x20u
mbed_official 146:f64d43ff0c18 12880 #define USB_OTGCTL_DPLOW_SHIFT 5
mbed_official 146:f64d43ff0c18 12881 #define USB_OTGCTL_DPHIGH_MASK 0x80u
mbed_official 146:f64d43ff0c18 12882 #define USB_OTGCTL_DPHIGH_SHIFT 7
mbed_official 146:f64d43ff0c18 12883 /* ISTAT Bit Fields */
mbed_official 146:f64d43ff0c18 12884 #define USB_ISTAT_USBRST_MASK 0x1u
mbed_official 146:f64d43ff0c18 12885 #define USB_ISTAT_USBRST_SHIFT 0
mbed_official 146:f64d43ff0c18 12886 #define USB_ISTAT_ERROR_MASK 0x2u
mbed_official 146:f64d43ff0c18 12887 #define USB_ISTAT_ERROR_SHIFT 1
mbed_official 146:f64d43ff0c18 12888 #define USB_ISTAT_SOFTOK_MASK 0x4u
mbed_official 146:f64d43ff0c18 12889 #define USB_ISTAT_SOFTOK_SHIFT 2
mbed_official 146:f64d43ff0c18 12890 #define USB_ISTAT_TOKDNE_MASK 0x8u
mbed_official 146:f64d43ff0c18 12891 #define USB_ISTAT_TOKDNE_SHIFT 3
mbed_official 146:f64d43ff0c18 12892 #define USB_ISTAT_SLEEP_MASK 0x10u
mbed_official 146:f64d43ff0c18 12893 #define USB_ISTAT_SLEEP_SHIFT 4
mbed_official 146:f64d43ff0c18 12894 #define USB_ISTAT_RESUME_MASK 0x20u
mbed_official 146:f64d43ff0c18 12895 #define USB_ISTAT_RESUME_SHIFT 5
mbed_official 146:f64d43ff0c18 12896 #define USB_ISTAT_ATTACH_MASK 0x40u
mbed_official 146:f64d43ff0c18 12897 #define USB_ISTAT_ATTACH_SHIFT 6
mbed_official 146:f64d43ff0c18 12898 #define USB_ISTAT_STALL_MASK 0x80u
mbed_official 146:f64d43ff0c18 12899 #define USB_ISTAT_STALL_SHIFT 7
mbed_official 146:f64d43ff0c18 12900 /* INTEN Bit Fields */
mbed_official 146:f64d43ff0c18 12901 #define USB_INTEN_USBRSTEN_MASK 0x1u
mbed_official 146:f64d43ff0c18 12902 #define USB_INTEN_USBRSTEN_SHIFT 0
mbed_official 146:f64d43ff0c18 12903 #define USB_INTEN_ERROREN_MASK 0x2u
mbed_official 146:f64d43ff0c18 12904 #define USB_INTEN_ERROREN_SHIFT 1
mbed_official 146:f64d43ff0c18 12905 #define USB_INTEN_SOFTOKEN_MASK 0x4u
mbed_official 146:f64d43ff0c18 12906 #define USB_INTEN_SOFTOKEN_SHIFT 2
mbed_official 146:f64d43ff0c18 12907 #define USB_INTEN_TOKDNEEN_MASK 0x8u
mbed_official 146:f64d43ff0c18 12908 #define USB_INTEN_TOKDNEEN_SHIFT 3
mbed_official 146:f64d43ff0c18 12909 #define USB_INTEN_SLEEPEN_MASK 0x10u
mbed_official 146:f64d43ff0c18 12910 #define USB_INTEN_SLEEPEN_SHIFT 4
mbed_official 146:f64d43ff0c18 12911 #define USB_INTEN_RESUMEEN_MASK 0x20u
mbed_official 146:f64d43ff0c18 12912 #define USB_INTEN_RESUMEEN_SHIFT 5
mbed_official 146:f64d43ff0c18 12913 #define USB_INTEN_ATTACHEN_MASK 0x40u
mbed_official 146:f64d43ff0c18 12914 #define USB_INTEN_ATTACHEN_SHIFT 6
mbed_official 146:f64d43ff0c18 12915 #define USB_INTEN_STALLEN_MASK 0x80u
mbed_official 146:f64d43ff0c18 12916 #define USB_INTEN_STALLEN_SHIFT 7
mbed_official 146:f64d43ff0c18 12917 /* ERRSTAT Bit Fields */
mbed_official 146:f64d43ff0c18 12918 #define USB_ERRSTAT_PIDERR_MASK 0x1u
mbed_official 146:f64d43ff0c18 12919 #define USB_ERRSTAT_PIDERR_SHIFT 0
mbed_official 146:f64d43ff0c18 12920 #define USB_ERRSTAT_CRC5EOF_MASK 0x2u
mbed_official 146:f64d43ff0c18 12921 #define USB_ERRSTAT_CRC5EOF_SHIFT 1
mbed_official 146:f64d43ff0c18 12922 #define USB_ERRSTAT_CRC16_MASK 0x4u
mbed_official 146:f64d43ff0c18 12923 #define USB_ERRSTAT_CRC16_SHIFT 2
mbed_official 146:f64d43ff0c18 12924 #define USB_ERRSTAT_DFN8_MASK 0x8u
mbed_official 146:f64d43ff0c18 12925 #define USB_ERRSTAT_DFN8_SHIFT 3
mbed_official 146:f64d43ff0c18 12926 #define USB_ERRSTAT_BTOERR_MASK 0x10u
mbed_official 146:f64d43ff0c18 12927 #define USB_ERRSTAT_BTOERR_SHIFT 4
mbed_official 146:f64d43ff0c18 12928 #define USB_ERRSTAT_DMAERR_MASK 0x20u
mbed_official 146:f64d43ff0c18 12929 #define USB_ERRSTAT_DMAERR_SHIFT 5
mbed_official 146:f64d43ff0c18 12930 #define USB_ERRSTAT_BTSERR_MASK 0x80u
mbed_official 146:f64d43ff0c18 12931 #define USB_ERRSTAT_BTSERR_SHIFT 7
mbed_official 146:f64d43ff0c18 12932 /* ERREN Bit Fields */
mbed_official 146:f64d43ff0c18 12933 #define USB_ERREN_PIDERREN_MASK 0x1u
mbed_official 146:f64d43ff0c18 12934 #define USB_ERREN_PIDERREN_SHIFT 0
mbed_official 146:f64d43ff0c18 12935 #define USB_ERREN_CRC5EOFEN_MASK 0x2u
mbed_official 146:f64d43ff0c18 12936 #define USB_ERREN_CRC5EOFEN_SHIFT 1
mbed_official 146:f64d43ff0c18 12937 #define USB_ERREN_CRC16EN_MASK 0x4u
mbed_official 146:f64d43ff0c18 12938 #define USB_ERREN_CRC16EN_SHIFT 2
mbed_official 146:f64d43ff0c18 12939 #define USB_ERREN_DFN8EN_MASK 0x8u
mbed_official 146:f64d43ff0c18 12940 #define USB_ERREN_DFN8EN_SHIFT 3
mbed_official 146:f64d43ff0c18 12941 #define USB_ERREN_BTOERREN_MASK 0x10u
mbed_official 146:f64d43ff0c18 12942 #define USB_ERREN_BTOERREN_SHIFT 4
mbed_official 146:f64d43ff0c18 12943 #define USB_ERREN_DMAERREN_MASK 0x20u
mbed_official 146:f64d43ff0c18 12944 #define USB_ERREN_DMAERREN_SHIFT 5
mbed_official 146:f64d43ff0c18 12945 #define USB_ERREN_BTSERREN_MASK 0x80u
mbed_official 146:f64d43ff0c18 12946 #define USB_ERREN_BTSERREN_SHIFT 7
mbed_official 146:f64d43ff0c18 12947 /* STAT Bit Fields */
mbed_official 146:f64d43ff0c18 12948 #define USB_STAT_ODD_MASK 0x4u
mbed_official 146:f64d43ff0c18 12949 #define USB_STAT_ODD_SHIFT 2
mbed_official 146:f64d43ff0c18 12950 #define USB_STAT_TX_MASK 0x8u
mbed_official 146:f64d43ff0c18 12951 #define USB_STAT_TX_SHIFT 3
mbed_official 146:f64d43ff0c18 12952 #define USB_STAT_ENDP_MASK 0xF0u
mbed_official 146:f64d43ff0c18 12953 #define USB_STAT_ENDP_SHIFT 4
mbed_official 146:f64d43ff0c18 12954 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
mbed_official 146:f64d43ff0c18 12955 /* CTL Bit Fields */
mbed_official 146:f64d43ff0c18 12956 #define USB_CTL_USBENSOFEN_MASK 0x1u
mbed_official 146:f64d43ff0c18 12957 #define USB_CTL_USBENSOFEN_SHIFT 0
mbed_official 146:f64d43ff0c18 12958 #define USB_CTL_ODDRST_MASK 0x2u
mbed_official 146:f64d43ff0c18 12959 #define USB_CTL_ODDRST_SHIFT 1
mbed_official 146:f64d43ff0c18 12960 #define USB_CTL_RESUME_MASK 0x4u
mbed_official 146:f64d43ff0c18 12961 #define USB_CTL_RESUME_SHIFT 2
mbed_official 146:f64d43ff0c18 12962 #define USB_CTL_HOSTMODEEN_MASK 0x8u
mbed_official 146:f64d43ff0c18 12963 #define USB_CTL_HOSTMODEEN_SHIFT 3
mbed_official 146:f64d43ff0c18 12964 #define USB_CTL_RESET_MASK 0x10u
mbed_official 146:f64d43ff0c18 12965 #define USB_CTL_RESET_SHIFT 4
mbed_official 146:f64d43ff0c18 12966 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
mbed_official 146:f64d43ff0c18 12967 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
mbed_official 146:f64d43ff0c18 12968 #define USB_CTL_SE0_MASK 0x40u
mbed_official 146:f64d43ff0c18 12969 #define USB_CTL_SE0_SHIFT 6
mbed_official 146:f64d43ff0c18 12970 #define USB_CTL_JSTATE_MASK 0x80u
mbed_official 146:f64d43ff0c18 12971 #define USB_CTL_JSTATE_SHIFT 7
mbed_official 146:f64d43ff0c18 12972 /* ADDR Bit Fields */
mbed_official 146:f64d43ff0c18 12973 #define USB_ADDR_ADDR_MASK 0x7Fu
mbed_official 146:f64d43ff0c18 12974 #define USB_ADDR_ADDR_SHIFT 0
mbed_official 146:f64d43ff0c18 12975 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
mbed_official 146:f64d43ff0c18 12976 #define USB_ADDR_LSEN_MASK 0x80u
mbed_official 146:f64d43ff0c18 12977 #define USB_ADDR_LSEN_SHIFT 7
mbed_official 146:f64d43ff0c18 12978 /* BDTPAGE1 Bit Fields */
mbed_official 146:f64d43ff0c18 12979 #define USB_BDTPAGE1_BDTBA_MASK 0xFEu
mbed_official 146:f64d43ff0c18 12980 #define USB_BDTPAGE1_BDTBA_SHIFT 1
mbed_official 146:f64d43ff0c18 12981 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
mbed_official 146:f64d43ff0c18 12982 /* FRMNUML Bit Fields */
mbed_official 146:f64d43ff0c18 12983 #define USB_FRMNUML_FRM_MASK 0xFFu
mbed_official 146:f64d43ff0c18 12984 #define USB_FRMNUML_FRM_SHIFT 0
mbed_official 146:f64d43ff0c18 12985 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
mbed_official 146:f64d43ff0c18 12986 /* FRMNUMH Bit Fields */
mbed_official 146:f64d43ff0c18 12987 #define USB_FRMNUMH_FRM_MASK 0x7u
mbed_official 146:f64d43ff0c18 12988 #define USB_FRMNUMH_FRM_SHIFT 0
mbed_official 146:f64d43ff0c18 12989 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
mbed_official 146:f64d43ff0c18 12990 /* TOKEN Bit Fields */
mbed_official 146:f64d43ff0c18 12991 #define USB_TOKEN_TOKENENDPT_MASK 0xFu
mbed_official 146:f64d43ff0c18 12992 #define USB_TOKEN_TOKENENDPT_SHIFT 0
mbed_official 146:f64d43ff0c18 12993 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
mbed_official 146:f64d43ff0c18 12994 #define USB_TOKEN_TOKENPID_MASK 0xF0u
mbed_official 146:f64d43ff0c18 12995 #define USB_TOKEN_TOKENPID_SHIFT 4
mbed_official 146:f64d43ff0c18 12996 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
mbed_official 146:f64d43ff0c18 12997 /* SOFTHLD Bit Fields */
mbed_official 146:f64d43ff0c18 12998 #define USB_SOFTHLD_CNT_MASK 0xFFu
mbed_official 146:f64d43ff0c18 12999 #define USB_SOFTHLD_CNT_SHIFT 0
mbed_official 146:f64d43ff0c18 13000 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
mbed_official 146:f64d43ff0c18 13001 /* BDTPAGE2 Bit Fields */
mbed_official 146:f64d43ff0c18 13002 #define USB_BDTPAGE2_BDTBA_MASK 0xFFu
mbed_official 146:f64d43ff0c18 13003 #define USB_BDTPAGE2_BDTBA_SHIFT 0
mbed_official 146:f64d43ff0c18 13004 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
mbed_official 146:f64d43ff0c18 13005 /* BDTPAGE3 Bit Fields */
mbed_official 146:f64d43ff0c18 13006 #define USB_BDTPAGE3_BDTBA_MASK 0xFFu
mbed_official 146:f64d43ff0c18 13007 #define USB_BDTPAGE3_BDTBA_SHIFT 0
mbed_official 146:f64d43ff0c18 13008 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
mbed_official 146:f64d43ff0c18 13009 /* ENDPT Bit Fields */
mbed_official 146:f64d43ff0c18 13010 #define USB_ENDPT_EPHSHK_MASK 0x1u
mbed_official 146:f64d43ff0c18 13011 #define USB_ENDPT_EPHSHK_SHIFT 0
mbed_official 146:f64d43ff0c18 13012 #define USB_ENDPT_EPSTALL_MASK 0x2u
mbed_official 146:f64d43ff0c18 13013 #define USB_ENDPT_EPSTALL_SHIFT 1
mbed_official 146:f64d43ff0c18 13014 #define USB_ENDPT_EPTXEN_MASK 0x4u
mbed_official 146:f64d43ff0c18 13015 #define USB_ENDPT_EPTXEN_SHIFT 2
mbed_official 146:f64d43ff0c18 13016 #define USB_ENDPT_EPRXEN_MASK 0x8u
mbed_official 146:f64d43ff0c18 13017 #define USB_ENDPT_EPRXEN_SHIFT 3
mbed_official 146:f64d43ff0c18 13018 #define USB_ENDPT_EPCTLDIS_MASK 0x10u
mbed_official 146:f64d43ff0c18 13019 #define USB_ENDPT_EPCTLDIS_SHIFT 4
mbed_official 146:f64d43ff0c18 13020 #define USB_ENDPT_RETRYDIS_MASK 0x40u
mbed_official 146:f64d43ff0c18 13021 #define USB_ENDPT_RETRYDIS_SHIFT 6
mbed_official 146:f64d43ff0c18 13022 #define USB_ENDPT_HOSTWOHUB_MASK 0x80u
mbed_official 146:f64d43ff0c18 13023 #define USB_ENDPT_HOSTWOHUB_SHIFT 7
mbed_official 146:f64d43ff0c18 13024 /* USBCTRL Bit Fields */
mbed_official 146:f64d43ff0c18 13025 #define USB_USBCTRL_PDE_MASK 0x40u
mbed_official 146:f64d43ff0c18 13026 #define USB_USBCTRL_PDE_SHIFT 6
mbed_official 146:f64d43ff0c18 13027 #define USB_USBCTRL_SUSP_MASK 0x80u
mbed_official 146:f64d43ff0c18 13028 #define USB_USBCTRL_SUSP_SHIFT 7
mbed_official 146:f64d43ff0c18 13029 /* OBSERVE Bit Fields */
mbed_official 146:f64d43ff0c18 13030 #define USB_OBSERVE_DMPD_MASK 0x10u
mbed_official 146:f64d43ff0c18 13031 #define USB_OBSERVE_DMPD_SHIFT 4
mbed_official 146:f64d43ff0c18 13032 #define USB_OBSERVE_DPPD_MASK 0x40u
mbed_official 146:f64d43ff0c18 13033 #define USB_OBSERVE_DPPD_SHIFT 6
mbed_official 146:f64d43ff0c18 13034 #define USB_OBSERVE_DPPU_MASK 0x80u
mbed_official 146:f64d43ff0c18 13035 #define USB_OBSERVE_DPPU_SHIFT 7
mbed_official 146:f64d43ff0c18 13036 /* CONTROL Bit Fields */
mbed_official 146:f64d43ff0c18 13037 #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
mbed_official 146:f64d43ff0c18 13038 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
mbed_official 146:f64d43ff0c18 13039 /* USBTRC0 Bit Fields */
mbed_official 146:f64d43ff0c18 13040 #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
mbed_official 146:f64d43ff0c18 13041 #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
mbed_official 146:f64d43ff0c18 13042 #define USB_USBTRC0_SYNC_DET_MASK 0x2u
mbed_official 146:f64d43ff0c18 13043 #define USB_USBTRC0_SYNC_DET_SHIFT 1
mbed_official 146:f64d43ff0c18 13044 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK 0x4u
mbed_official 146:f64d43ff0c18 13045 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT 2
mbed_official 146:f64d43ff0c18 13046 #define USB_USBTRC0_USBRESMEN_MASK 0x20u
mbed_official 146:f64d43ff0c18 13047 #define USB_USBTRC0_USBRESMEN_SHIFT 5
mbed_official 146:f64d43ff0c18 13048 #define USB_USBTRC0_USBRESET_MASK 0x80u
mbed_official 146:f64d43ff0c18 13049 #define USB_USBTRC0_USBRESET_SHIFT 7
mbed_official 146:f64d43ff0c18 13050 /* USBFRMADJUST Bit Fields */
mbed_official 146:f64d43ff0c18 13051 #define USB_USBFRMADJUST_ADJ_MASK 0xFFu
mbed_official 146:f64d43ff0c18 13052 #define USB_USBFRMADJUST_ADJ_SHIFT 0
mbed_official 146:f64d43ff0c18 13053 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
mbed_official 146:f64d43ff0c18 13054 /* CLK_RECOVER_CTRL Bit Fields */
mbed_official 146:f64d43ff0c18 13055 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK 0x20u
mbed_official 146:f64d43ff0c18 13056 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT 5
mbed_official 146:f64d43ff0c18 13057 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK 0x40u
mbed_official 146:f64d43ff0c18 13058 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT 6
mbed_official 146:f64d43ff0c18 13059 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK 0x80u
mbed_official 146:f64d43ff0c18 13060 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT 7
mbed_official 146:f64d43ff0c18 13061 /* CLK_RECOVER_IRC_EN Bit Fields */
mbed_official 146:f64d43ff0c18 13062 #define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK 0x1u
mbed_official 146:f64d43ff0c18 13063 #define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT 0
mbed_official 146:f64d43ff0c18 13064 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK 0x2u
mbed_official 146:f64d43ff0c18 13065 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT 1
mbed_official 146:f64d43ff0c18 13066 /* CLK_RECOVER_INT_STATUS Bit Fields */
mbed_official 146:f64d43ff0c18 13067 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK 0x10u
mbed_official 146:f64d43ff0c18 13068 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT 4
mbed_official 146:f64d43ff0c18 13069
mbed_official 146:f64d43ff0c18 13070 /*!
mbed_official 146:f64d43ff0c18 13071 * @}
mbed_official 146:f64d43ff0c18 13072 */ /* end of group USB_Register_Masks */
mbed_official 146:f64d43ff0c18 13073
mbed_official 146:f64d43ff0c18 13074
mbed_official 146:f64d43ff0c18 13075 /* USB - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 13076 /** Peripheral USB0 base address */
mbed_official 146:f64d43ff0c18 13077 #define USB0_BASE (0x40072000u)
mbed_official 146:f64d43ff0c18 13078 /** Peripheral USB0 base pointer */
mbed_official 146:f64d43ff0c18 13079 #define USB0 ((USB_Type *)USB0_BASE)
mbed_official 146:f64d43ff0c18 13080 #define USB0_BASE_PTR (USB0)
mbed_official 146:f64d43ff0c18 13081 /** Array initializer of USB peripheral base pointers */
mbed_official 146:f64d43ff0c18 13082 #define USB_BASES { USB0 }
mbed_official 146:f64d43ff0c18 13083
mbed_official 146:f64d43ff0c18 13084 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 13085 -- USB - Register accessor macros
mbed_official 146:f64d43ff0c18 13086 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 13087
mbed_official 146:f64d43ff0c18 13088 /*!
mbed_official 146:f64d43ff0c18 13089 * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
mbed_official 146:f64d43ff0c18 13090 * @{
mbed_official 146:f64d43ff0c18 13091 */
mbed_official 146:f64d43ff0c18 13092
mbed_official 146:f64d43ff0c18 13093
mbed_official 146:f64d43ff0c18 13094 /* USB - Register instance definitions */
mbed_official 146:f64d43ff0c18 13095 /* USB0 */
mbed_official 146:f64d43ff0c18 13096 #define USB0_PERID USB_PERID_REG(USB0)
mbed_official 146:f64d43ff0c18 13097 #define USB0_IDCOMP USB_IDCOMP_REG(USB0)
mbed_official 146:f64d43ff0c18 13098 #define USB0_REV USB_REV_REG(USB0)
mbed_official 146:f64d43ff0c18 13099 #define USB0_ADDINFO USB_ADDINFO_REG(USB0)
mbed_official 146:f64d43ff0c18 13100 #define USB0_OTGISTAT USB_OTGISTAT_REG(USB0)
mbed_official 146:f64d43ff0c18 13101 #define USB0_OTGICR USB_OTGICR_REG(USB0)
mbed_official 146:f64d43ff0c18 13102 #define USB0_OTGSTAT USB_OTGSTAT_REG(USB0)
mbed_official 146:f64d43ff0c18 13103 #define USB0_OTGCTL USB_OTGCTL_REG(USB0)
mbed_official 146:f64d43ff0c18 13104 #define USB0_ISTAT USB_ISTAT_REG(USB0)
mbed_official 146:f64d43ff0c18 13105 #define USB0_INTEN USB_INTEN_REG(USB0)
mbed_official 146:f64d43ff0c18 13106 #define USB0_ERRSTAT USB_ERRSTAT_REG(USB0)
mbed_official 146:f64d43ff0c18 13107 #define USB0_ERREN USB_ERREN_REG(USB0)
mbed_official 146:f64d43ff0c18 13108 #define USB0_STAT USB_STAT_REG(USB0)
mbed_official 146:f64d43ff0c18 13109 #define USB0_CTL USB_CTL_REG(USB0)
mbed_official 146:f64d43ff0c18 13110 #define USB0_ADDR USB_ADDR_REG(USB0)
mbed_official 146:f64d43ff0c18 13111 #define USB0_BDTPAGE1 USB_BDTPAGE1_REG(USB0)
mbed_official 146:f64d43ff0c18 13112 #define USB0_FRMNUML USB_FRMNUML_REG(USB0)
mbed_official 146:f64d43ff0c18 13113 #define USB0_FRMNUMH USB_FRMNUMH_REG(USB0)
mbed_official 146:f64d43ff0c18 13114 #define USB0_TOKEN USB_TOKEN_REG(USB0)
mbed_official 146:f64d43ff0c18 13115 #define USB0_SOFTHLD USB_SOFTHLD_REG(USB0)
mbed_official 146:f64d43ff0c18 13116 #define USB0_BDTPAGE2 USB_BDTPAGE2_REG(USB0)
mbed_official 146:f64d43ff0c18 13117 #define USB0_BDTPAGE3 USB_BDTPAGE3_REG(USB0)
mbed_official 146:f64d43ff0c18 13118 #define USB0_ENDPT0 USB_ENDPT_REG(USB0,0)
mbed_official 146:f64d43ff0c18 13119 #define USB0_ENDPT1 USB_ENDPT_REG(USB0,1)
mbed_official 146:f64d43ff0c18 13120 #define USB0_ENDPT2 USB_ENDPT_REG(USB0,2)
mbed_official 146:f64d43ff0c18 13121 #define USB0_ENDPT3 USB_ENDPT_REG(USB0,3)
mbed_official 146:f64d43ff0c18 13122 #define USB0_ENDPT4 USB_ENDPT_REG(USB0,4)
mbed_official 146:f64d43ff0c18 13123 #define USB0_ENDPT5 USB_ENDPT_REG(USB0,5)
mbed_official 146:f64d43ff0c18 13124 #define USB0_ENDPT6 USB_ENDPT_REG(USB0,6)
mbed_official 146:f64d43ff0c18 13125 #define USB0_ENDPT7 USB_ENDPT_REG(USB0,7)
mbed_official 146:f64d43ff0c18 13126 #define USB0_ENDPT8 USB_ENDPT_REG(USB0,8)
mbed_official 146:f64d43ff0c18 13127 #define USB0_ENDPT9 USB_ENDPT_REG(USB0,9)
mbed_official 146:f64d43ff0c18 13128 #define USB0_ENDPT10 USB_ENDPT_REG(USB0,10)
mbed_official 146:f64d43ff0c18 13129 #define USB0_ENDPT11 USB_ENDPT_REG(USB0,11)
mbed_official 146:f64d43ff0c18 13130 #define USB0_ENDPT12 USB_ENDPT_REG(USB0,12)
mbed_official 146:f64d43ff0c18 13131 #define USB0_ENDPT13 USB_ENDPT_REG(USB0,13)
mbed_official 146:f64d43ff0c18 13132 #define USB0_ENDPT14 USB_ENDPT_REG(USB0,14)
mbed_official 146:f64d43ff0c18 13133 #define USB0_ENDPT15 USB_ENDPT_REG(USB0,15)
mbed_official 146:f64d43ff0c18 13134 #define USB0_USBCTRL USB_USBCTRL_REG(USB0)
mbed_official 146:f64d43ff0c18 13135 #define USB0_OBSERVE USB_OBSERVE_REG(USB0)
mbed_official 146:f64d43ff0c18 13136 #define USB0_CONTROL USB_CONTROL_REG(USB0)
mbed_official 146:f64d43ff0c18 13137 #define USB0_USBTRC0 USB_USBTRC0_REG(USB0)
mbed_official 146:f64d43ff0c18 13138 #define USB0_USBFRMADJUST USB_USBFRMADJUST_REG(USB0)
mbed_official 146:f64d43ff0c18 13139 #define USB0_CLK_RECOVER_CTRL USB_CLK_RECOVER_CTRL_REG(USB0)
mbed_official 146:f64d43ff0c18 13140 #define USB0_CLK_RECOVER_IRC_EN USB_CLK_RECOVER_IRC_EN_REG(USB0)
mbed_official 146:f64d43ff0c18 13141 #define USB0_CLK_RECOVER_INT_STATUS USB_CLK_RECOVER_INT_STATUS_REG(USB0)
mbed_official 146:f64d43ff0c18 13142
mbed_official 146:f64d43ff0c18 13143 /* USB - Register array accessors */
mbed_official 146:f64d43ff0c18 13144 #define USB0_ENDPT(index) USB_ENDPT_REG(USB0,index)
mbed_official 146:f64d43ff0c18 13145
mbed_official 146:f64d43ff0c18 13146 /*!
mbed_official 146:f64d43ff0c18 13147 * @}
mbed_official 146:f64d43ff0c18 13148 */ /* end of group USB_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 13149
mbed_official 146:f64d43ff0c18 13150
mbed_official 146:f64d43ff0c18 13151 /*!
mbed_official 146:f64d43ff0c18 13152 * @}
mbed_official 146:f64d43ff0c18 13153 */ /* end of group USB_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 13154
mbed_official 146:f64d43ff0c18 13155
mbed_official 146:f64d43ff0c18 13156 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 13157 -- USBDCD Peripheral Access Layer
mbed_official 146:f64d43ff0c18 13158 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 13159
mbed_official 146:f64d43ff0c18 13160 /*!
mbed_official 146:f64d43ff0c18 13161 * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
mbed_official 146:f64d43ff0c18 13162 * @{
mbed_official 146:f64d43ff0c18 13163 */
mbed_official 146:f64d43ff0c18 13164
mbed_official 146:f64d43ff0c18 13165 /** USBDCD - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 13166 typedef struct {
mbed_official 146:f64d43ff0c18 13167 __IO uint32_t CONTROL; /**< Control register, offset: 0x0 */
mbed_official 146:f64d43ff0c18 13168 __IO uint32_t CLOCK; /**< Clock register, offset: 0x4 */
mbed_official 146:f64d43ff0c18 13169 __I uint32_t STATUS; /**< Status register, offset: 0x8 */
mbed_official 146:f64d43ff0c18 13170 uint8_t RESERVED_0[4];
mbed_official 146:f64d43ff0c18 13171 __IO uint32_t TIMER0; /**< TIMER0 register, offset: 0x10 */
mbed_official 146:f64d43ff0c18 13172 __IO uint32_t TIMER1; /**< TIMER1 register, offset: 0x14 */
mbed_official 146:f64d43ff0c18 13173 union { /* offset: 0x18 */
mbed_official 146:f64d43ff0c18 13174 __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11 register, offset: 0x18 */
mbed_official 146:f64d43ff0c18 13175 __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12 register, offset: 0x18 */
mbed_official 146:f64d43ff0c18 13176 };
mbed_official 146:f64d43ff0c18 13177 } USBDCD_Type, *USBDCD_MemMapPtr;
mbed_official 146:f64d43ff0c18 13178
mbed_official 146:f64d43ff0c18 13179 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 13180 -- USBDCD - Register accessor macros
mbed_official 146:f64d43ff0c18 13181 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 13182
mbed_official 146:f64d43ff0c18 13183 /*!
mbed_official 146:f64d43ff0c18 13184 * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
mbed_official 146:f64d43ff0c18 13185 * @{
mbed_official 146:f64d43ff0c18 13186 */
mbed_official 146:f64d43ff0c18 13187
mbed_official 146:f64d43ff0c18 13188
mbed_official 146:f64d43ff0c18 13189 /* USBDCD - Register accessors */
mbed_official 146:f64d43ff0c18 13190 #define USBDCD_CONTROL_REG(base) ((base)->CONTROL)
mbed_official 146:f64d43ff0c18 13191 #define USBDCD_CLOCK_REG(base) ((base)->CLOCK)
mbed_official 146:f64d43ff0c18 13192 #define USBDCD_STATUS_REG(base) ((base)->STATUS)
mbed_official 146:f64d43ff0c18 13193 #define USBDCD_TIMER0_REG(base) ((base)->TIMER0)
mbed_official 146:f64d43ff0c18 13194 #define USBDCD_TIMER1_REG(base) ((base)->TIMER1)
mbed_official 146:f64d43ff0c18 13195 #define USBDCD_TIMER2_BC11_REG(base) ((base)->TIMER2_BC11)
mbed_official 146:f64d43ff0c18 13196 #define USBDCD_TIMER2_BC12_REG(base) ((base)->TIMER2_BC12)
mbed_official 146:f64d43ff0c18 13197
mbed_official 146:f64d43ff0c18 13198 /*!
mbed_official 146:f64d43ff0c18 13199 * @}
mbed_official 146:f64d43ff0c18 13200 */ /* end of group USBDCD_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 13201
mbed_official 146:f64d43ff0c18 13202
mbed_official 146:f64d43ff0c18 13203 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 13204 -- USBDCD Register Masks
mbed_official 146:f64d43ff0c18 13205 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 13206
mbed_official 146:f64d43ff0c18 13207 /*!
mbed_official 146:f64d43ff0c18 13208 * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
mbed_official 146:f64d43ff0c18 13209 * @{
mbed_official 146:f64d43ff0c18 13210 */
mbed_official 146:f64d43ff0c18 13211
mbed_official 146:f64d43ff0c18 13212 /* CONTROL Bit Fields */
mbed_official 146:f64d43ff0c18 13213 #define USBDCD_CONTROL_IACK_MASK 0x1u
mbed_official 146:f64d43ff0c18 13214 #define USBDCD_CONTROL_IACK_SHIFT 0
mbed_official 146:f64d43ff0c18 13215 #define USBDCD_CONTROL_IF_MASK 0x100u
mbed_official 146:f64d43ff0c18 13216 #define USBDCD_CONTROL_IF_SHIFT 8
mbed_official 146:f64d43ff0c18 13217 #define USBDCD_CONTROL_IE_MASK 0x10000u
mbed_official 146:f64d43ff0c18 13218 #define USBDCD_CONTROL_IE_SHIFT 16
mbed_official 146:f64d43ff0c18 13219 #define USBDCD_CONTROL_BC12_MASK 0x20000u
mbed_official 146:f64d43ff0c18 13220 #define USBDCD_CONTROL_BC12_SHIFT 17
mbed_official 146:f64d43ff0c18 13221 #define USBDCD_CONTROL_START_MASK 0x1000000u
mbed_official 146:f64d43ff0c18 13222 #define USBDCD_CONTROL_START_SHIFT 24
mbed_official 146:f64d43ff0c18 13223 #define USBDCD_CONTROL_SR_MASK 0x2000000u
mbed_official 146:f64d43ff0c18 13224 #define USBDCD_CONTROL_SR_SHIFT 25
mbed_official 146:f64d43ff0c18 13225 /* CLOCK Bit Fields */
mbed_official 146:f64d43ff0c18 13226 #define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u
mbed_official 146:f64d43ff0c18 13227 #define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0
mbed_official 146:f64d43ff0c18 13228 #define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu
mbed_official 146:f64d43ff0c18 13229 #define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2
mbed_official 146:f64d43ff0c18 13230 #define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)
mbed_official 146:f64d43ff0c18 13231 /* STATUS Bit Fields */
mbed_official 146:f64d43ff0c18 13232 #define USBDCD_STATUS_SEQ_RES_MASK 0x30000u
mbed_official 146:f64d43ff0c18 13233 #define USBDCD_STATUS_SEQ_RES_SHIFT 16
mbed_official 146:f64d43ff0c18 13234 #define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)
mbed_official 146:f64d43ff0c18 13235 #define USBDCD_STATUS_SEQ_STAT_MASK 0xC0000u
mbed_official 146:f64d43ff0c18 13236 #define USBDCD_STATUS_SEQ_STAT_SHIFT 18
mbed_official 146:f64d43ff0c18 13237 #define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)
mbed_official 146:f64d43ff0c18 13238 #define USBDCD_STATUS_ERR_MASK 0x100000u
mbed_official 146:f64d43ff0c18 13239 #define USBDCD_STATUS_ERR_SHIFT 20
mbed_official 146:f64d43ff0c18 13240 #define USBDCD_STATUS_TO_MASK 0x200000u
mbed_official 146:f64d43ff0c18 13241 #define USBDCD_STATUS_TO_SHIFT 21
mbed_official 146:f64d43ff0c18 13242 #define USBDCD_STATUS_ACTIVE_MASK 0x400000u
mbed_official 146:f64d43ff0c18 13243 #define USBDCD_STATUS_ACTIVE_SHIFT 22
mbed_official 146:f64d43ff0c18 13244 /* TIMER0 Bit Fields */
mbed_official 146:f64d43ff0c18 13245 #define USBDCD_TIMER0_TUNITCON_MASK 0xFFFu
mbed_official 146:f64d43ff0c18 13246 #define USBDCD_TIMER0_TUNITCON_SHIFT 0
mbed_official 146:f64d43ff0c18 13247 #define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)
mbed_official 146:f64d43ff0c18 13248 #define USBDCD_TIMER0_TSEQ_INIT_MASK 0x3FF0000u
mbed_official 146:f64d43ff0c18 13249 #define USBDCD_TIMER0_TSEQ_INIT_SHIFT 16
mbed_official 146:f64d43ff0c18 13250 #define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)
mbed_official 146:f64d43ff0c18 13251 /* TIMER1 Bit Fields */
mbed_official 146:f64d43ff0c18 13252 #define USBDCD_TIMER1_TVDPSRC_ON_MASK 0x3FFu
mbed_official 146:f64d43ff0c18 13253 #define USBDCD_TIMER1_TVDPSRC_ON_SHIFT 0
mbed_official 146:f64d43ff0c18 13254 #define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)
mbed_official 146:f64d43ff0c18 13255 #define USBDCD_TIMER1_TDCD_DBNC_MASK 0x3FF0000u
mbed_official 146:f64d43ff0c18 13256 #define USBDCD_TIMER1_TDCD_DBNC_SHIFT 16
mbed_official 146:f64d43ff0c18 13257 #define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)
mbed_official 146:f64d43ff0c18 13258 /* TIMER2_BC11 Bit Fields */
mbed_official 146:f64d43ff0c18 13259 #define USBDCD_TIMER2_BC11_CHECK_DM_MASK 0xFu
mbed_official 146:f64d43ff0c18 13260 #define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT 0
mbed_official 146:f64d43ff0c18 13261 #define USBDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_CHECK_DM_SHIFT))&USBDCD_TIMER2_BC11_CHECK_DM_MASK)
mbed_official 146:f64d43ff0c18 13262 #define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK 0x3FF0000u
mbed_official 146:f64d43ff0c18 13263 #define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT 16
mbed_official 146:f64d43ff0c18 13264 #define USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
mbed_official 146:f64d43ff0c18 13265 /* TIMER2_BC12 Bit Fields */
mbed_official 146:f64d43ff0c18 13266 #define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK 0x3FFu
mbed_official 146:f64d43ff0c18 13267 #define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT 0
mbed_official 146:f64d43ff0c18 13268 #define USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT))&USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
mbed_official 146:f64d43ff0c18 13269 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK 0x3FF0000u
mbed_official 146:f64d43ff0c18 13270 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT 16
mbed_official 146:f64d43ff0c18 13271 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT))&USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
mbed_official 146:f64d43ff0c18 13272
mbed_official 146:f64d43ff0c18 13273 /*!
mbed_official 146:f64d43ff0c18 13274 * @}
mbed_official 146:f64d43ff0c18 13275 */ /* end of group USBDCD_Register_Masks */
mbed_official 146:f64d43ff0c18 13276
mbed_official 146:f64d43ff0c18 13277
mbed_official 146:f64d43ff0c18 13278 /* USBDCD - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 13279 /** Peripheral USBDCD base address */
mbed_official 146:f64d43ff0c18 13280 #define USBDCD_BASE (0x40035000u)
mbed_official 146:f64d43ff0c18 13281 /** Peripheral USBDCD base pointer */
mbed_official 146:f64d43ff0c18 13282 #define USBDCD ((USBDCD_Type *)USBDCD_BASE)
mbed_official 146:f64d43ff0c18 13283 #define USBDCD_BASE_PTR (USBDCD)
mbed_official 146:f64d43ff0c18 13284 /** Array initializer of USBDCD peripheral base pointers */
mbed_official 146:f64d43ff0c18 13285 #define USBDCD_BASES { USBDCD }
mbed_official 146:f64d43ff0c18 13286
mbed_official 146:f64d43ff0c18 13287 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 13288 -- USBDCD - Register accessor macros
mbed_official 146:f64d43ff0c18 13289 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 13290
mbed_official 146:f64d43ff0c18 13291 /*!
mbed_official 146:f64d43ff0c18 13292 * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
mbed_official 146:f64d43ff0c18 13293 * @{
mbed_official 146:f64d43ff0c18 13294 */
mbed_official 146:f64d43ff0c18 13295
mbed_official 146:f64d43ff0c18 13296
mbed_official 146:f64d43ff0c18 13297 /* USBDCD - Register instance definitions */
mbed_official 146:f64d43ff0c18 13298 /* USBDCD */
mbed_official 146:f64d43ff0c18 13299 #define USBDCD_CONTROL USBDCD_CONTROL_REG(USBDCD)
mbed_official 146:f64d43ff0c18 13300 #define USBDCD_CLOCK USBDCD_CLOCK_REG(USBDCD)
mbed_official 146:f64d43ff0c18 13301 #define USBDCD_STATUS USBDCD_STATUS_REG(USBDCD)
mbed_official 146:f64d43ff0c18 13302 #define USBDCD_TIMER0 USBDCD_TIMER0_REG(USBDCD)
mbed_official 146:f64d43ff0c18 13303 #define USBDCD_TIMER1 USBDCD_TIMER1_REG(USBDCD)
mbed_official 146:f64d43ff0c18 13304 #define USBDCD_TIMER2_BC11 USBDCD_TIMER2_BC11_REG(USBDCD)
mbed_official 146:f64d43ff0c18 13305 #define USBDCD_TIMER2_BC12 USBDCD_TIMER2_BC12_REG(USBDCD)
mbed_official 146:f64d43ff0c18 13306
mbed_official 146:f64d43ff0c18 13307 /*!
mbed_official 146:f64d43ff0c18 13308 * @}
mbed_official 146:f64d43ff0c18 13309 */ /* end of group USBDCD_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 13310
mbed_official 146:f64d43ff0c18 13311
mbed_official 146:f64d43ff0c18 13312 /*!
mbed_official 146:f64d43ff0c18 13313 * @}
mbed_official 146:f64d43ff0c18 13314 */ /* end of group USBDCD_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 13315
mbed_official 146:f64d43ff0c18 13316
mbed_official 146:f64d43ff0c18 13317 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 13318 -- VREF Peripheral Access Layer
mbed_official 146:f64d43ff0c18 13319 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 13320
mbed_official 146:f64d43ff0c18 13321 /*!
mbed_official 146:f64d43ff0c18 13322 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
mbed_official 146:f64d43ff0c18 13323 * @{
mbed_official 146:f64d43ff0c18 13324 */
mbed_official 146:f64d43ff0c18 13325
mbed_official 146:f64d43ff0c18 13326 /** VREF - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 13327 typedef struct {
mbed_official 146:f64d43ff0c18 13328 __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
mbed_official 146:f64d43ff0c18 13329 __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
mbed_official 146:f64d43ff0c18 13330 } VREF_Type, *VREF_MemMapPtr;
mbed_official 146:f64d43ff0c18 13331
mbed_official 146:f64d43ff0c18 13332 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 13333 -- VREF - Register accessor macros
mbed_official 146:f64d43ff0c18 13334 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 13335
mbed_official 146:f64d43ff0c18 13336 /*!
mbed_official 146:f64d43ff0c18 13337 * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
mbed_official 146:f64d43ff0c18 13338 * @{
mbed_official 146:f64d43ff0c18 13339 */
mbed_official 146:f64d43ff0c18 13340
mbed_official 146:f64d43ff0c18 13341
mbed_official 146:f64d43ff0c18 13342 /* VREF - Register accessors */
mbed_official 146:f64d43ff0c18 13343 #define VREF_TRM_REG(base) ((base)->TRM)
mbed_official 146:f64d43ff0c18 13344 #define VREF_SC_REG(base) ((base)->SC)
mbed_official 146:f64d43ff0c18 13345
mbed_official 146:f64d43ff0c18 13346 /*!
mbed_official 146:f64d43ff0c18 13347 * @}
mbed_official 146:f64d43ff0c18 13348 */ /* end of group VREF_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 13349
mbed_official 146:f64d43ff0c18 13350
mbed_official 146:f64d43ff0c18 13351 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 13352 -- VREF Register Masks
mbed_official 146:f64d43ff0c18 13353 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 13354
mbed_official 146:f64d43ff0c18 13355 /*!
mbed_official 146:f64d43ff0c18 13356 * @addtogroup VREF_Register_Masks VREF Register Masks
mbed_official 146:f64d43ff0c18 13357 * @{
mbed_official 146:f64d43ff0c18 13358 */
mbed_official 146:f64d43ff0c18 13359
mbed_official 146:f64d43ff0c18 13360 /* TRM Bit Fields */
mbed_official 146:f64d43ff0c18 13361 #define VREF_TRM_TRIM_MASK 0x3Fu
mbed_official 146:f64d43ff0c18 13362 #define VREF_TRM_TRIM_SHIFT 0
mbed_official 146:f64d43ff0c18 13363 #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
mbed_official 146:f64d43ff0c18 13364 #define VREF_TRM_CHOPEN_MASK 0x40u
mbed_official 146:f64d43ff0c18 13365 #define VREF_TRM_CHOPEN_SHIFT 6
mbed_official 146:f64d43ff0c18 13366 /* SC Bit Fields */
mbed_official 146:f64d43ff0c18 13367 #define VREF_SC_MODE_LV_MASK 0x3u
mbed_official 146:f64d43ff0c18 13368 #define VREF_SC_MODE_LV_SHIFT 0
mbed_official 146:f64d43ff0c18 13369 #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
mbed_official 146:f64d43ff0c18 13370 #define VREF_SC_VREFST_MASK 0x4u
mbed_official 146:f64d43ff0c18 13371 #define VREF_SC_VREFST_SHIFT 2
mbed_official 146:f64d43ff0c18 13372 #define VREF_SC_ICOMPEN_MASK 0x20u
mbed_official 146:f64d43ff0c18 13373 #define VREF_SC_ICOMPEN_SHIFT 5
mbed_official 146:f64d43ff0c18 13374 #define VREF_SC_REGEN_MASK 0x40u
mbed_official 146:f64d43ff0c18 13375 #define VREF_SC_REGEN_SHIFT 6
mbed_official 146:f64d43ff0c18 13376 #define VREF_SC_VREFEN_MASK 0x80u
mbed_official 146:f64d43ff0c18 13377 #define VREF_SC_VREFEN_SHIFT 7
mbed_official 146:f64d43ff0c18 13378
mbed_official 146:f64d43ff0c18 13379 /*!
mbed_official 146:f64d43ff0c18 13380 * @}
mbed_official 146:f64d43ff0c18 13381 */ /* end of group VREF_Register_Masks */
mbed_official 146:f64d43ff0c18 13382
mbed_official 146:f64d43ff0c18 13383
mbed_official 146:f64d43ff0c18 13384 /* VREF - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 13385 /** Peripheral VREF base address */
mbed_official 146:f64d43ff0c18 13386 #define VREF_BASE (0x40074000u)
mbed_official 146:f64d43ff0c18 13387 /** Peripheral VREF base pointer */
mbed_official 146:f64d43ff0c18 13388 #define VREF ((VREF_Type *)VREF_BASE)
mbed_official 146:f64d43ff0c18 13389 #define VREF_BASE_PTR (VREF)
mbed_official 146:f64d43ff0c18 13390 /** Array initializer of VREF peripheral base pointers */
mbed_official 146:f64d43ff0c18 13391 #define VREF_BASES { VREF }
mbed_official 146:f64d43ff0c18 13392
mbed_official 146:f64d43ff0c18 13393 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 13394 -- VREF - Register accessor macros
mbed_official 146:f64d43ff0c18 13395 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 13396
mbed_official 146:f64d43ff0c18 13397 /*!
mbed_official 146:f64d43ff0c18 13398 * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
mbed_official 146:f64d43ff0c18 13399 * @{
mbed_official 146:f64d43ff0c18 13400 */
mbed_official 146:f64d43ff0c18 13401
mbed_official 146:f64d43ff0c18 13402
mbed_official 146:f64d43ff0c18 13403 /* VREF - Register instance definitions */
mbed_official 146:f64d43ff0c18 13404 /* VREF */
mbed_official 146:f64d43ff0c18 13405 #define VREF_TRM VREF_TRM_REG(VREF)
mbed_official 146:f64d43ff0c18 13406 #define VREF_SC VREF_SC_REG(VREF)
mbed_official 146:f64d43ff0c18 13407
mbed_official 146:f64d43ff0c18 13408 /*!
mbed_official 146:f64d43ff0c18 13409 * @}
mbed_official 146:f64d43ff0c18 13410 */ /* end of group VREF_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 13411
mbed_official 146:f64d43ff0c18 13412
mbed_official 146:f64d43ff0c18 13413 /*!
mbed_official 146:f64d43ff0c18 13414 * @}
mbed_official 146:f64d43ff0c18 13415 */ /* end of group VREF_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 13416
mbed_official 146:f64d43ff0c18 13417
mbed_official 146:f64d43ff0c18 13418 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 13419 -- WDOG Peripheral Access Layer
mbed_official 146:f64d43ff0c18 13420 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 13421
mbed_official 146:f64d43ff0c18 13422 /*!
mbed_official 146:f64d43ff0c18 13423 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
mbed_official 146:f64d43ff0c18 13424 * @{
mbed_official 146:f64d43ff0c18 13425 */
mbed_official 146:f64d43ff0c18 13426
mbed_official 146:f64d43ff0c18 13427 /** WDOG - Register Layout Typedef */
mbed_official 146:f64d43ff0c18 13428 typedef struct {
mbed_official 146:f64d43ff0c18 13429 __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
mbed_official 146:f64d43ff0c18 13430 __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
mbed_official 146:f64d43ff0c18 13431 __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
mbed_official 146:f64d43ff0c18 13432 __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
mbed_official 146:f64d43ff0c18 13433 __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
mbed_official 146:f64d43ff0c18 13434 __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
mbed_official 146:f64d43ff0c18 13435 __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */
mbed_official 146:f64d43ff0c18 13436 __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */
mbed_official 146:f64d43ff0c18 13437 __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
mbed_official 146:f64d43ff0c18 13438 __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
mbed_official 146:f64d43ff0c18 13439 __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */
mbed_official 146:f64d43ff0c18 13440 __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */
mbed_official 146:f64d43ff0c18 13441 } WDOG_Type, *WDOG_MemMapPtr;
mbed_official 146:f64d43ff0c18 13442
mbed_official 146:f64d43ff0c18 13443 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 13444 -- WDOG - Register accessor macros
mbed_official 146:f64d43ff0c18 13445 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 13446
mbed_official 146:f64d43ff0c18 13447 /*!
mbed_official 146:f64d43ff0c18 13448 * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
mbed_official 146:f64d43ff0c18 13449 * @{
mbed_official 146:f64d43ff0c18 13450 */
mbed_official 146:f64d43ff0c18 13451
mbed_official 146:f64d43ff0c18 13452
mbed_official 146:f64d43ff0c18 13453 /* WDOG - Register accessors */
mbed_official 146:f64d43ff0c18 13454 #define WDOG_STCTRLH_REG(base) ((base)->STCTRLH)
mbed_official 146:f64d43ff0c18 13455 #define WDOG_STCTRLL_REG(base) ((base)->STCTRLL)
mbed_official 146:f64d43ff0c18 13456 #define WDOG_TOVALH_REG(base) ((base)->TOVALH)
mbed_official 146:f64d43ff0c18 13457 #define WDOG_TOVALL_REG(base) ((base)->TOVALL)
mbed_official 146:f64d43ff0c18 13458 #define WDOG_WINH_REG(base) ((base)->WINH)
mbed_official 146:f64d43ff0c18 13459 #define WDOG_WINL_REG(base) ((base)->WINL)
mbed_official 146:f64d43ff0c18 13460 #define WDOG_REFRESH_REG(base) ((base)->REFRESH)
mbed_official 146:f64d43ff0c18 13461 #define WDOG_UNLOCK_REG(base) ((base)->UNLOCK)
mbed_official 146:f64d43ff0c18 13462 #define WDOG_TMROUTH_REG(base) ((base)->TMROUTH)
mbed_official 146:f64d43ff0c18 13463 #define WDOG_TMROUTL_REG(base) ((base)->TMROUTL)
mbed_official 146:f64d43ff0c18 13464 #define WDOG_RSTCNT_REG(base) ((base)->RSTCNT)
mbed_official 146:f64d43ff0c18 13465 #define WDOG_PRESC_REG(base) ((base)->PRESC)
mbed_official 146:f64d43ff0c18 13466
mbed_official 146:f64d43ff0c18 13467 /*!
mbed_official 146:f64d43ff0c18 13468 * @}
mbed_official 146:f64d43ff0c18 13469 */ /* end of group WDOG_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 13470
mbed_official 146:f64d43ff0c18 13471
mbed_official 146:f64d43ff0c18 13472 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 13473 -- WDOG Register Masks
mbed_official 146:f64d43ff0c18 13474 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 13475
mbed_official 146:f64d43ff0c18 13476 /*!
mbed_official 146:f64d43ff0c18 13477 * @addtogroup WDOG_Register_Masks WDOG Register Masks
mbed_official 146:f64d43ff0c18 13478 * @{
mbed_official 146:f64d43ff0c18 13479 */
mbed_official 146:f64d43ff0c18 13480
mbed_official 146:f64d43ff0c18 13481 /* STCTRLH Bit Fields */
mbed_official 146:f64d43ff0c18 13482 #define WDOG_STCTRLH_WDOGEN_MASK 0x1u
mbed_official 146:f64d43ff0c18 13483 #define WDOG_STCTRLH_WDOGEN_SHIFT 0
mbed_official 146:f64d43ff0c18 13484 #define WDOG_STCTRLH_CLKSRC_MASK 0x2u
mbed_official 146:f64d43ff0c18 13485 #define WDOG_STCTRLH_CLKSRC_SHIFT 1
mbed_official 146:f64d43ff0c18 13486 #define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
mbed_official 146:f64d43ff0c18 13487 #define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
mbed_official 146:f64d43ff0c18 13488 #define WDOG_STCTRLH_WINEN_MASK 0x8u
mbed_official 146:f64d43ff0c18 13489 #define WDOG_STCTRLH_WINEN_SHIFT 3
mbed_official 146:f64d43ff0c18 13490 #define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
mbed_official 146:f64d43ff0c18 13491 #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
mbed_official 146:f64d43ff0c18 13492 #define WDOG_STCTRLH_DBGEN_MASK 0x20u
mbed_official 146:f64d43ff0c18 13493 #define WDOG_STCTRLH_DBGEN_SHIFT 5
mbed_official 146:f64d43ff0c18 13494 #define WDOG_STCTRLH_STOPEN_MASK 0x40u
mbed_official 146:f64d43ff0c18 13495 #define WDOG_STCTRLH_STOPEN_SHIFT 6
mbed_official 146:f64d43ff0c18 13496 #define WDOG_STCTRLH_WAITEN_MASK 0x80u
mbed_official 146:f64d43ff0c18 13497 #define WDOG_STCTRLH_WAITEN_SHIFT 7
mbed_official 146:f64d43ff0c18 13498 #define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
mbed_official 146:f64d43ff0c18 13499 #define WDOG_STCTRLH_TESTWDOG_SHIFT 10
mbed_official 146:f64d43ff0c18 13500 #define WDOG_STCTRLH_TESTSEL_MASK 0x800u
mbed_official 146:f64d43ff0c18 13501 #define WDOG_STCTRLH_TESTSEL_SHIFT 11
mbed_official 146:f64d43ff0c18 13502 #define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
mbed_official 146:f64d43ff0c18 13503 #define WDOG_STCTRLH_BYTESEL_SHIFT 12
mbed_official 146:f64d43ff0c18 13504 #define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
mbed_official 146:f64d43ff0c18 13505 #define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u
mbed_official 146:f64d43ff0c18 13506 #define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14
mbed_official 146:f64d43ff0c18 13507 /* STCTRLL Bit Fields */
mbed_official 146:f64d43ff0c18 13508 #define WDOG_STCTRLL_INTFLG_MASK 0x8000u
mbed_official 146:f64d43ff0c18 13509 #define WDOG_STCTRLL_INTFLG_SHIFT 15
mbed_official 146:f64d43ff0c18 13510 /* TOVALH Bit Fields */
mbed_official 146:f64d43ff0c18 13511 #define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 13512 #define WDOG_TOVALH_TOVALHIGH_SHIFT 0
mbed_official 146:f64d43ff0c18 13513 #define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
mbed_official 146:f64d43ff0c18 13514 /* TOVALL Bit Fields */
mbed_official 146:f64d43ff0c18 13515 #define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 13516 #define WDOG_TOVALL_TOVALLOW_SHIFT 0
mbed_official 146:f64d43ff0c18 13517 #define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
mbed_official 146:f64d43ff0c18 13518 /* WINH Bit Fields */
mbed_official 146:f64d43ff0c18 13519 #define WDOG_WINH_WINHIGH_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 13520 #define WDOG_WINH_WINHIGH_SHIFT 0
mbed_official 146:f64d43ff0c18 13521 #define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
mbed_official 146:f64d43ff0c18 13522 /* WINL Bit Fields */
mbed_official 146:f64d43ff0c18 13523 #define WDOG_WINL_WINLOW_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 13524 #define WDOG_WINL_WINLOW_SHIFT 0
mbed_official 146:f64d43ff0c18 13525 #define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
mbed_official 146:f64d43ff0c18 13526 /* REFRESH Bit Fields */
mbed_official 146:f64d43ff0c18 13527 #define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 13528 #define WDOG_REFRESH_WDOGREFRESH_SHIFT 0
mbed_official 146:f64d43ff0c18 13529 #define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
mbed_official 146:f64d43ff0c18 13530 /* UNLOCK Bit Fields */
mbed_official 146:f64d43ff0c18 13531 #define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 13532 #define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0
mbed_official 146:f64d43ff0c18 13533 #define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
mbed_official 146:f64d43ff0c18 13534 /* TMROUTH Bit Fields */
mbed_official 146:f64d43ff0c18 13535 #define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 13536 #define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0
mbed_official 146:f64d43ff0c18 13537 #define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
mbed_official 146:f64d43ff0c18 13538 /* TMROUTL Bit Fields */
mbed_official 146:f64d43ff0c18 13539 #define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 13540 #define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0
mbed_official 146:f64d43ff0c18 13541 #define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
mbed_official 146:f64d43ff0c18 13542 /* RSTCNT Bit Fields */
mbed_official 146:f64d43ff0c18 13543 #define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu
mbed_official 146:f64d43ff0c18 13544 #define WDOG_RSTCNT_RSTCNT_SHIFT 0
mbed_official 146:f64d43ff0c18 13545 #define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
mbed_official 146:f64d43ff0c18 13546 /* PRESC Bit Fields */
mbed_official 146:f64d43ff0c18 13547 #define WDOG_PRESC_PRESCVAL_MASK 0x700u
mbed_official 146:f64d43ff0c18 13548 #define WDOG_PRESC_PRESCVAL_SHIFT 8
mbed_official 146:f64d43ff0c18 13549 #define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
mbed_official 146:f64d43ff0c18 13550
mbed_official 146:f64d43ff0c18 13551 /*!
mbed_official 146:f64d43ff0c18 13552 * @}
mbed_official 146:f64d43ff0c18 13553 */ /* end of group WDOG_Register_Masks */
mbed_official 146:f64d43ff0c18 13554
mbed_official 146:f64d43ff0c18 13555
mbed_official 146:f64d43ff0c18 13556 /* WDOG - Peripheral instance base addresses */
mbed_official 146:f64d43ff0c18 13557 /** Peripheral WDOG base address */
mbed_official 146:f64d43ff0c18 13558 #define WDOG_BASE (0x40052000u)
mbed_official 146:f64d43ff0c18 13559 /** Peripheral WDOG base pointer */
mbed_official 146:f64d43ff0c18 13560 #define WDOG ((WDOG_Type *)WDOG_BASE)
mbed_official 146:f64d43ff0c18 13561 #define WDOG_BASE_PTR (WDOG)
mbed_official 146:f64d43ff0c18 13562 /** Array initializer of WDOG peripheral base pointers */
mbed_official 146:f64d43ff0c18 13563 #define WDOG_BASES { WDOG }
mbed_official 146:f64d43ff0c18 13564
mbed_official 146:f64d43ff0c18 13565 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 13566 -- WDOG - Register accessor macros
mbed_official 146:f64d43ff0c18 13567 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 13568
mbed_official 146:f64d43ff0c18 13569 /*!
mbed_official 146:f64d43ff0c18 13570 * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
mbed_official 146:f64d43ff0c18 13571 * @{
mbed_official 146:f64d43ff0c18 13572 */
mbed_official 146:f64d43ff0c18 13573
mbed_official 146:f64d43ff0c18 13574
mbed_official 146:f64d43ff0c18 13575 /* WDOG - Register instance definitions */
mbed_official 146:f64d43ff0c18 13576 /* WDOG */
mbed_official 146:f64d43ff0c18 13577 #define WDOG_STCTRLH WDOG_STCTRLH_REG(WDOG)
mbed_official 146:f64d43ff0c18 13578 #define WDOG_STCTRLL WDOG_STCTRLL_REG(WDOG)
mbed_official 146:f64d43ff0c18 13579 #define WDOG_TOVALH WDOG_TOVALH_REG(WDOG)
mbed_official 146:f64d43ff0c18 13580 #define WDOG_TOVALL WDOG_TOVALL_REG(WDOG)
mbed_official 146:f64d43ff0c18 13581 #define WDOG_WINH WDOG_WINH_REG(WDOG)
mbed_official 146:f64d43ff0c18 13582 #define WDOG_WINL WDOG_WINL_REG(WDOG)
mbed_official 146:f64d43ff0c18 13583 #define WDOG_REFRESH WDOG_REFRESH_REG(WDOG)
mbed_official 146:f64d43ff0c18 13584 #define WDOG_UNLOCK WDOG_UNLOCK_REG(WDOG)
mbed_official 146:f64d43ff0c18 13585 #define WDOG_TMROUTH WDOG_TMROUTH_REG(WDOG)
mbed_official 146:f64d43ff0c18 13586 #define WDOG_TMROUTL WDOG_TMROUTL_REG(WDOG)
mbed_official 146:f64d43ff0c18 13587 #define WDOG_RSTCNT WDOG_RSTCNT_REG(WDOG)
mbed_official 146:f64d43ff0c18 13588 #define WDOG_PRESC WDOG_PRESC_REG(WDOG)
mbed_official 146:f64d43ff0c18 13589
mbed_official 146:f64d43ff0c18 13590 /*!
mbed_official 146:f64d43ff0c18 13591 * @}
mbed_official 146:f64d43ff0c18 13592 */ /* end of group WDOG_Register_Accessor_Macros */
mbed_official 146:f64d43ff0c18 13593
mbed_official 146:f64d43ff0c18 13594
mbed_official 146:f64d43ff0c18 13595 /*!
mbed_official 146:f64d43ff0c18 13596 * @}
mbed_official 146:f64d43ff0c18 13597 */ /* end of group WDOG_Peripheral_Access_Layer */
mbed_official 146:f64d43ff0c18 13598
mbed_official 146:f64d43ff0c18 13599
mbed_official 146:f64d43ff0c18 13600 /*
mbed_official 146:f64d43ff0c18 13601 ** End of section using anonymous unions
mbed_official 146:f64d43ff0c18 13602 */
mbed_official 146:f64d43ff0c18 13603
mbed_official 146:f64d43ff0c18 13604 #if defined(__ARMCC_VERSION)
mbed_official 146:f64d43ff0c18 13605 #pragma pop
mbed_official 146:f64d43ff0c18 13606 #elif defined(__CWCC__)
mbed_official 146:f64d43ff0c18 13607 #pragma pop
mbed_official 146:f64d43ff0c18 13608 #elif defined(__GNUC__)
mbed_official 146:f64d43ff0c18 13609 /* leave anonymous unions enabled */
mbed_official 146:f64d43ff0c18 13610 #elif defined(__IAR_SYSTEMS_ICC__)
mbed_official 146:f64d43ff0c18 13611 #pragma language=default
mbed_official 146:f64d43ff0c18 13612 #else
mbed_official 146:f64d43ff0c18 13613 #error Not supported compiler type
mbed_official 146:f64d43ff0c18 13614 #endif
mbed_official 146:f64d43ff0c18 13615
mbed_official 146:f64d43ff0c18 13616 /*!
mbed_official 146:f64d43ff0c18 13617 * @}
mbed_official 146:f64d43ff0c18 13618 */ /* end of group Peripheral_access_layer */
mbed_official 146:f64d43ff0c18 13619
mbed_official 146:f64d43ff0c18 13620
mbed_official 146:f64d43ff0c18 13621 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 13622 -- Backward Compatibility
mbed_official 146:f64d43ff0c18 13623 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 13624
mbed_official 146:f64d43ff0c18 13625 /*!
mbed_official 146:f64d43ff0c18 13626 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
mbed_official 146:f64d43ff0c18 13627 * @{
mbed_official 146:f64d43ff0c18 13628 */
mbed_official 146:f64d43ff0c18 13629
mbed_official 146:f64d43ff0c18 13630 #define DMA_EARS_REG(base) This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13631 #define DMA_EARS This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13632 #define DMA_EARS_EDREQ_0_MASK This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13633 #define DMA_EARS_EDREQ_0_SHIFT This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13634 #define DMA_EARS_EDREQ_1_MASK This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13635 #define DMA_EARS_EDREQ_1_SHIFT This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13636 #define DMA_EARS_EDREQ_2_MASK This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13637 #define DMA_EARS_EDREQ_2_SHIFT This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13638 #define DMA_EARS_EDREQ_3_MASK This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13639 #define DMA_EARS_EDREQ_3_SHIFT This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13640 #define DMA_EARS_EDREQ_4_MASK This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13641 #define DMA_EARS_EDREQ_4_SHIFT This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13642 #define DMA_EARS_EDREQ_5_MASK This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13643 #define DMA_EARS_EDREQ_5_SHIFT This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13644 #define DMA_EARS_EDREQ_6_MASK This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13645 #define DMA_EARS_EDREQ_6_SHIFT This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13646 #define DMA_EARS_EDREQ_7_MASK This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13647 #define DMA_EARS_EDREQ_7_SHIFT This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13648 #define DMA_EARS_EDREQ_8_MASK This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13649 #define DMA_EARS_EDREQ_8_SHIFT This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13650 #define DMA_EARS_EDREQ_9_MASK This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13651 #define DMA_EARS_EDREQ_9_SHIFT This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13652 #define DMA_EARS_EDREQ_10_MASK This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13653 #define DMA_EARS_EDREQ_10_SHIFT This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13654 #define DMA_EARS_EDREQ_11_MASK This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13655 #define DMA_EARS_EDREQ_11_SHIFT This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13656 #define DMA_EARS_EDREQ_12_MASK This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13657 #define DMA_EARS_EDREQ_12_SHIFT This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13658 #define DMA_EARS_EDREQ_13_MASK This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13659 #define DMA_EARS_EDREQ_13_SHIFT This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13660 #define DMA_EARS_EDREQ_14_MASK This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13661 #define DMA_EARS_EDREQ_14_SHIFT This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13662 #define DMA_EARS_EDREQ_15_MASK This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13663 #define DMA_EARS_EDREQ_15_SHIFT This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13664 #define ENET_RMON_T_DROP_REG(base) This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13665 #define ENET_IEEE_T_DROP_REG(base) This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13666 #define ENET_IEEE_T_SQE_REG(base) This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13667 #define ENET_RMON_R_RESVD_0_REG(base) This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13668 #define ENET_RMON_R_DROP_REG(base) ENET_IEEE_R_DROP_REG(base)
mbed_official 146:f64d43ff0c18 13669 #define ENET_RMON_R_FRAME_OK_REG(base) ENET_IEEE_R_FRAME_OK_REG(base)
mbed_official 146:f64d43ff0c18 13670 #define ENET_RMON_T_DROP This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13671 #define ENET_IEEE_T_DROP This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13672 #define ENET_IEEE_T_SQE This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13673 #define ENET_RMON_R_RESVD_0 This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13674 #define MCG_C9_REG(base) This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13675 #define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK
mbed_official 146:f64d43ff0c18 13676 #define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT
mbed_official 146:f64d43ff0c18 13677 #define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK
mbed_official 146:f64d43ff0c18 13678 #define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT
mbed_official 146:f64d43ff0c18 13679 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
mbed_official 146:f64d43ff0c18 13680 #define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT
mbed_official 146:f64d43ff0c18 13681 #define MCG_C2_RANGE0(x) MCG_C2_RANGE(x)
mbed_official 146:f64d43ff0c18 13682 #define MCG_C9 This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13683 #define MCM_PLACR_REG(base) This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13684 #define MCM_PLACR_ARB_MASK This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13685 #define MCM_PLACR_ARB_SHIFT This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13686 #define MCM_PLACR This_symbol_has_been_deprecated
mbed_official 146:f64d43ff0c18 13687
mbed_official 146:f64d43ff0c18 13688 /*!
mbed_official 146:f64d43ff0c18 13689 * @}
mbed_official 146:f64d43ff0c18 13690 */ /* end of group Backward_Compatibility_Symbols */
mbed_official 146:f64d43ff0c18 13691
mbed_official 146:f64d43ff0c18 13692
mbed_official 146:f64d43ff0c18 13693 #else /* #if !defined(MCU_MK64F12) */
mbed_official 146:f64d43ff0c18 13694 /* There is already included the same memory map. Check if it is compatible (has the same major version) */
mbed_official 146:f64d43ff0c18 13695 #if (MCU_MEM_MAP_VERSION != 0x0200u)
mbed_official 146:f64d43ff0c18 13696 #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
mbed_official 146:f64d43ff0c18 13697 #warning There are included two not compatible versions of memory maps. Please check possible differences.
mbed_official 146:f64d43ff0c18 13698 #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
mbed_official 146:f64d43ff0c18 13699 #endif /* (MCU_MEM_MAP_VERSION != 0x0200u) */
mbed_official 146:f64d43ff0c18 13700 #endif /* #if !defined(MCU_MK64F12) */
mbed_official 146:f64d43ff0c18 13701
mbed_official 146:f64d43ff0c18 13702 #endif /* #if !defined(MK64F12_H_) */
mbed_official 146:f64d43ff0c18 13703
mbed_official 146:f64d43ff0c18 13704 /* MK64F12.h, eof. */