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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.c@633:188f3ef4d258, 2015-09-28 (annotated)

Committer:
mbed_official
Date:
Mon Sep 28 15:00:09 2015 +0100
Revision:
633:188f3ef4d258
Parent:
521:149b1eddda04 
Synchronized with git revision 3ee5d7ac62c3c0576d7f358e3657a0ca8970fe9a



Full URL: https://github.com/mbedmicro/mbed/commit/3ee5d7ac62c3c0576d7f358e3657a0ca8970fe9a/



Added/changed clock set ups for Teensy3.1.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 445:3312ed629f01 1 /*
mbed_official 445:3312ed629f01 2 ** ###################################################################
mbed_official 445:3312ed629f01 3 ** Compilers: ARM Compiler
mbed_official 445:3312ed629f01 4 ** Freescale C/C++ for Embedded ARM
mbed_official 445:3312ed629f01 5 ** GNU C Compiler
mbed_official 445:3312ed629f01 6 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 445:3312ed629f01 7 **
mbed_official 445:3312ed629f01 8 **
mbed_official 445:3312ed629f01 9 **
mbed_official 445:3312ed629f01 10 ** Version: rev. 1.0, 2011-12-15
mbed_official 445:3312ed629f01 11 **
mbed_official 445:3312ed629f01 12 ** Abstract:
mbed_official 445:3312ed629f01 13 ** Provides a system configuration function and a global variable that
mbed_official 445:3312ed629f01 14 ** contains the system frequency. It configures the device and initializes
mbed_official 445:3312ed629f01 15 ** the oscillator (PLL) that is part of the microcontroller device.
mbed_official 445:3312ed629f01 16 **
mbed_official 445:3312ed629f01 17 ** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved.
mbed_official 445:3312ed629f01 18 **
mbed_official 445:3312ed629f01 19 ** http: www.freescale.com
mbed_official 445:3312ed629f01 20 ** mail: support@freescale.com
mbed_official 445:3312ed629f01 21 **
mbed_official 445:3312ed629f01 22 ** Revisions:
mbed_official 445:3312ed629f01 23 ** - rev. 1.0 (2011-12-15)
mbed_official 445:3312ed629f01 24 ** Initial version
mbed_official 445:3312ed629f01 25 **
mbed_official 445:3312ed629f01 26 ** ###################################################################
mbed_official 445:3312ed629f01 27 */
mbed_official 445:3312ed629f01 28
mbed_official 445:3312ed629f01 29 /**
mbed_official 445:3312ed629f01 30 * @file MK20DX256
mbed_official 445:3312ed629f01 31 * @version 1.0
mbed_official 445:3312ed629f01 32 * @date 2011-12-15
mbed_official 445:3312ed629f01 33 * @brief Device specific configuration file for MK20DX256 (implementation file)
mbed_official 445:3312ed629f01 34 *
mbed_official 445:3312ed629f01 35 * Provides a system configuration function and a global variable that contains
mbed_official 445:3312ed629f01 36 * the system frequency. It configures the device and initializes the oscillator
mbed_official 445:3312ed629f01 37 * (PLL) that is part of the microcontroller device.
mbed_official 445:3312ed629f01 38 */
mbed_official 445:3312ed629f01 39
mbed_official 445:3312ed629f01 40 #include <stdint.h>
mbed_official 445:3312ed629f01 41 #include "MK20DX256.h"
mbed_official 445:3312ed629f01 42
mbed_official 445:3312ed629f01 43 #define DISABLE_WDOG 1
mbed_official 445:3312ed629f01 44
mbed_official 633:188f3ef4d258 45 #define CLOCK_SETUP 1
mbed_official 445:3312ed629f01 46 /* Predefined clock setups
mbed_official 445:3312ed629f01 47 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
mbed_official 445:3312ed629f01 48 Reference clock source for MCG module is the slow internal clock source 32.768kHz
mbed_official 445:3312ed629f01 49 Core clock = 41.94MHz, BusClock = 41.94MHz
mbed_official 633:188f3ef4d258 50 Works on Teensy3.1 but no USB support
mbed_official 445:3312ed629f01 51 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
mbed_official 445:3312ed629f01 52 Reference clock source for MCG module is an external crystal 16MHz
mbed_official 633:188f3ef4d258 53 Core clock = 96MHz, BusClock = 48MHz
mbed_official 633:188f3ef4d258 54 Default high speed Teensy3.1 96Mhz set up
mbed_official 633:188f3ef4d258 55 2 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
mbed_official 633:188f3ef4d258 56 Reference clock source for MCG module is an external crystal 16MHz
mbed_official 633:188f3ef4d258 57 Core clock = 72MHz, BusClock = 36MHz
mbed_official 633:188f3ef4d258 58 Alternative standard 'slower' Teensy3.1 72Mhz set up
mbed_official 445:3312ed629f01 59 */
mbed_official 445:3312ed629f01 60
mbed_official 445:3312ed629f01 61 /*----------------------------------------------------------------------------
mbed_official 445:3312ed629f01 62 Define clock source values
mbed_official 445:3312ed629f01 63 *----------------------------------------------------------------------------*/
mbed_official 445:3312ed629f01 64 #if (CLOCK_SETUP == 0)
mbed_official 445:3312ed629f01 65 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
mbed_official 445:3312ed629f01 66 #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
mbed_official 445:3312ed629f01 67 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
mbed_official 445:3312ed629f01 68 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
mbed_official 445:3312ed629f01 69 #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
mbed_official 445:3312ed629f01 70 #elif (CLOCK_SETUP == 1)
mbed_official 445:3312ed629f01 71 #define CPU_XTAL_CLK_HZ 16000000u /* Value of the external crystal or oscillator clock frequency in Hz */
mbed_official 445:3312ed629f01 72 #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
mbed_official 445:3312ed629f01 73 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
mbed_official 445:3312ed629f01 74 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
mbed_official 633:188f3ef4d258 75 #define DEFAULT_SYSTEM_CLOCK 96000000u /* Default System clock value */
mbed_official 633:188f3ef4d258 76 #elif (CLOCK_SETUP == 2)
mbed_official 633:188f3ef4d258 77 #define CPU_XTAL_CLK_HZ 16000000u /* Value of the external crystal or oscillator clock frequency in Hz */
mbed_official 633:188f3ef4d258 78 #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
mbed_official 633:188f3ef4d258 79 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
mbed_official 633:188f3ef4d258 80 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
mbed_official 633:188f3ef4d258 81 #define DEFAULT_SYSTEM_CLOCK 72000000u /* Default System clock value */
mbed_official 445:3312ed629f01 82 #endif /* (CLOCK_SETUP == 2) */
mbed_official 445:3312ed629f01 83
mbed_official 445:3312ed629f01 84
mbed_official 445:3312ed629f01 85 /* ----------------------------------------------------------------------------
mbed_official 445:3312ed629f01 86 -- Core clock
mbed_official 445:3312ed629f01 87 ---------------------------------------------------------------------------- */
mbed_official 445:3312ed629f01 88
mbed_official 445:3312ed629f01 89 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
mbed_official 445:3312ed629f01 90
mbed_official 445:3312ed629f01 91 /* ----------------------------------------------------------------------------
mbed_official 445:3312ed629f01 92 -- SystemInit()
mbed_official 445:3312ed629f01 93 ---------------------------------------------------------------------------- */
mbed_official 445:3312ed629f01 94 void SystemInit (void) {
mbed_official 521:149b1eddda04 95 /* SystemInit MUST NOT use any variables from the .data section, as this section is not loaded yet! */
mbed_official 521:149b1eddda04 96
mbed_official 445:3312ed629f01 97 #if (DISABLE_WDOG)
mbed_official 445:3312ed629f01 98 /* Disable the WDOG module */
mbed_official 445:3312ed629f01 99 /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
mbed_official 445:3312ed629f01 100 WDOG->UNLOCK = (uint16_t)0xC520u; /* Key 1 */
mbed_official 445:3312ed629f01 101 /* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */
mbed_official 445:3312ed629f01 102 WDOG->UNLOCK = (uint16_t)0xD928u; /* Key 2 */
mbed_official 489:119543c9f674 103 /* WDOG_STCTRLH: DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
mbed_official 445:3312ed629f01 104 WDOG->STCTRLH = (uint16_t)0x01D2u;
mbed_official 445:3312ed629f01 105 #endif /* (DISABLE_WDOG) */
mbed_official 489:119543c9f674 106
mbed_official 445:3312ed629f01 107 #if (CLOCK_SETUP == 0)
mbed_official 489:119543c9f674 108 /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 41.94MHz cpu, 41.94MHz system, 20.97MHz flash*/
mbed_official 489:119543c9f674 109 SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV4(1);
mbed_official 445:3312ed629f01 110 /* Switch to FEI Mode */
mbed_official 445:3312ed629f01 111 /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
mbed_official 489:119543c9f674 112 MCG->C1 = MCG_C1_IREFS_MASK | MCG_C1_IRCLKEN_MASK;
mbed_official 489:119543c9f674 113 /* MCG->C2: LOCKRE0=0,RANGE0=0,HGO=0,EREFS=0,LP=0,IRCS=0 */
mbed_official 445:3312ed629f01 114 MCG->C2 = (uint8_t)0x00u;
mbed_official 445:3312ed629f01 115 /* MCG_C4: DMX32=0,DRST_DRS=1 */
mbed_official 445:3312ed629f01 116 MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0u) | (uint8_t)0x20u);
mbed_official 489:119543c9f674 117 /* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
mbed_official 445:3312ed629f01 118 MCG->C5 = (uint8_t)0x00u;
mbed_official 445:3312ed629f01 119 /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
mbed_official 445:3312ed629f01 120 MCG->C6 = (uint8_t)0x00u;
mbed_official 489:119543c9f674 121 while((MCG->S & MCG_S_IREFST_MASK) == 0u) { } /* Check that the source of the FLL reference clock is the internal reference clock. */
mbed_official 489:119543c9f674 122 while((MCG->S & 0x0Cu) != 0x00u) { } /* Wait until output of the FLL is selected */
mbed_official 489:119543c9f674 123
mbed_official 445:3312ed629f01 124 #elif (CLOCK_SETUP == 1)
mbed_official 633:188f3ef4d258 125 /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV4=3 Set Prescalers 96MHz cpu, 48MHz bus, 24MHz flash*/
mbed_official 633:188f3ef4d258 126 SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(3);
mbed_official 633:188f3ef4d258 127 /* SIM->CLKDIV2: USBDIV=2, Divide 96MHz system clock for USB 48MHz */
mbed_official 633:188f3ef4d258 128 SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1);
mbed_official 633:188f3ef4d258 129 /* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=1,SC4P=0,SC8P=1,SC16P=0 10pF loading capacitors for 16MHz system oscillator*/
mbed_official 633:188f3ef4d258 130 OSC0->CR = OSC_CR_SC8P_MASK | OSC_CR_SC2P_MASK;
mbed_official 445:3312ed629f01 131 /* Switch to FBE Mode */
mbed_official 445:3312ed629f01 132 /* MCG->C7: OSCSEL=0 */
mbed_official 445:3312ed629f01 133 MCG->C7 = (uint8_t)0x00u;
mbed_official 489:119543c9f674 134 /* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
mbed_official 633:188f3ef4d258 135 MCG->C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK;
mbed_official 633:188f3ef4d258 136 //MCG->C2 = (uint8_t)0x24u;
mbed_official 445:3312ed629f01 137 /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
mbed_official 489:119543c9f674 138 MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK;
mbed_official 633:188f3ef4d258 139 /* MCG->C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
mbed_official 633:188f3ef4d258 140 MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
mbed_official 633:188f3ef4d258 141 /* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=7 */
mbed_official 633:188f3ef4d258 142 MCG->C5 = MCG_C5_PRDIV0(7);
mbed_official 445:3312ed629f01 143 /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
mbed_official 445:3312ed629f01 144 MCG->C6 = (uint8_t)0x00u;
mbed_official 489:119543c9f674 145 while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } /* Check that the oscillator is running */
mbed_official 489:119543c9f674 146 while((MCG->S & 0x0Cu) != 0x08u) { } /* Wait until external reference clock is selected as MCG output */
mbed_official 445:3312ed629f01 147 /* Switch to PBE Mode */
mbed_official 633:188f3ef4d258 148 /* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=5 */
mbed_official 633:188f3ef4d258 149 MCG->C5 = MCG_C5_PRDIV0(3); // config PLL input for 16 MHz Crystal / 4 = 4 MHz
mbed_official 633:188f3ef4d258 150 /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=3 */
mbed_official 633:188f3ef4d258 151 MCG->C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0);// config PLL for 96 MHz output
mbed_official 489:119543c9f674 152 while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } /* Wait until the source of the PLLS clock has switched to the PLL */
mbed_official 489:119543c9f674 153 while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */
mbed_official 445:3312ed629f01 154 /* Switch to PEE Mode */
mbed_official 633:188f3ef4d258 155 /* MCG->C1: CLKS=0,FRDIV=2,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
mbed_official 633:188f3ef4d258 156 MCG->C1 = MCG_C1_FRDIV(2) | MCG_C1_IRCLKEN_MASK;
mbed_official 489:119543c9f674 157 while((MCG->S & 0x0Cu) != 0x0Cu) { } /* Wait until output of the PLL is selected */
mbed_official 633:188f3ef4d258 158 while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */
mbed_official 489:119543c9f674 159
mbed_official 445:3312ed629f01 160 #elif (CLOCK_SETUP == 2)
mbed_official 633:188f3ef4d258 161 /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 72MHz cpu, 36MHz bus, 24MHz flash*/
mbed_official 633:188f3ef4d258 162 SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(2);
mbed_official 489:119543c9f674 163 /* SIM->CLKDIV2: USBDIV=2,USBFRAC=1 Divide 72MHz system clock for USB 48MHz */
mbed_official 489:119543c9f674 164 SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC_MASK;
mbed_official 489:119543c9f674 165 /* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=1,SC4P=0,SC8P=1,SC16P=0 10pF loading capacitors for 16MHz system oscillator*/
mbed_official 489:119543c9f674 166 OSC0->CR = OSC_CR_SC8P_MASK | OSC_CR_SC2P_MASK;
mbed_official 445:3312ed629f01 167 /* Switch to FBE Mode */
mbed_official 445:3312ed629f01 168 /* MCG->C7: OSCSEL=0 */
mbed_official 445:3312ed629f01 169 MCG->C7 = (uint8_t)0x00u;
mbed_official 489:119543c9f674 170 /* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
mbed_official 489:119543c9f674 171 MCG->C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK;
mbed_official 489:119543c9f674 172 //MCG->C2 = (uint8_t)0x24u;
mbed_official 445:3312ed629f01 173 /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
mbed_official 489:119543c9f674 174 MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK;
mbed_official 489:119543c9f674 175 /* MCG->C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
mbed_official 489:119543c9f674 176 MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
mbed_official 489:119543c9f674 177 /* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=7 */
mbed_official 489:119543c9f674 178 MCG->C5 = MCG_C5_PRDIV0(7);
mbed_official 445:3312ed629f01 179 /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
mbed_official 445:3312ed629f01 180 MCG->C6 = (uint8_t)0x00u;
mbed_official 489:119543c9f674 181 while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } /* Check that the oscillator is running */
mbed_official 489:119543c9f674 182 while((MCG->S & 0x0Cu) != 0x08u) { } /* Wait until external reference clock is selected as MCG output */
mbed_official 445:3312ed629f01 183 /* Switch to PBE Mode */
mbed_official 489:119543c9f674 184 /* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=5 */
mbed_official 489:119543c9f674 185 MCG->C5 = MCG_C5_PRDIV0(5);
mbed_official 489:119543c9f674 186 /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=3 */
mbed_official 489:119543c9f674 187 MCG->C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(3);
mbed_official 489:119543c9f674 188 while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } /* Wait until the source of the PLLS clock has switched to the PLL */
mbed_official 489:119543c9f674 189 while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */
mbed_official 445:3312ed629f01 190 /* Switch to PEE Mode */
mbed_official 489:119543c9f674 191 /* MCG->C1: CLKS=0,FRDIV=2,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
mbed_official 489:119543c9f674 192 MCG->C1 = MCG_C1_FRDIV(2) | MCG_C1_IRCLKEN_MASK;
mbed_official 489:119543c9f674 193 while((MCG->S & 0x0Cu) != 0x0Cu) { } /* Wait until output of the PLL is selected */
mbed_official 633:188f3ef4d258 194 while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */
mbed_official 489:119543c9f674 195 #endif /* (CLOCK_SETUP) */
mbed_official 445:3312ed629f01 196 }
mbed_official 445:3312ed629f01 197
mbed_official 445:3312ed629f01 198 /* ----------------------------------------------------------------------------
mbed_official 445:3312ed629f01 199 -- SystemCoreClockUpdate()
mbed_official 445:3312ed629f01 200 ---------------------------------------------------------------------------- */
mbed_official 445:3312ed629f01 201
mbed_official 445:3312ed629f01 202 void SystemCoreClockUpdate (void) {
mbed_official 445:3312ed629f01 203 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
mbed_official 445:3312ed629f01 204 uint8_t Divider;
mbed_official 445:3312ed629f01 205
mbed_official 445:3312ed629f01 206 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
mbed_official 445:3312ed629f01 207 /* Output of FLL or PLL is selected */
mbed_official 445:3312ed629f01 208 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
mbed_official 445:3312ed629f01 209 /* FLL is selected */
mbed_official 445:3312ed629f01 210 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
mbed_official 445:3312ed629f01 211 /* External reference clock is selected */
mbed_official 445:3312ed629f01 212 if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
mbed_official 445:3312ed629f01 213 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
mbed_official 445:3312ed629f01 214 } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
mbed_official 445:3312ed629f01 215 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
mbed_official 445:3312ed629f01 216 } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
mbed_official 445:3312ed629f01 217 Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
mbed_official 445:3312ed629f01 218 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
mbed_official 445:3312ed629f01 219 if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
mbed_official 445:3312ed629f01 220 MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
mbed_official 445:3312ed629f01 221 } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
mbed_official 445:3312ed629f01 222 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
mbed_official 445:3312ed629f01 223 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
mbed_official 445:3312ed629f01 224 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
mbed_official 445:3312ed629f01 225 /* Select correct multiplier to calculate the MCG output clock */
mbed_official 445:3312ed629f01 226 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
mbed_official 445:3312ed629f01 227 case 0x0u:
mbed_official 445:3312ed629f01 228 MCGOUTClock *= 640u;
mbed_official 445:3312ed629f01 229 break;
mbed_official 445:3312ed629f01 230 case 0x20u:
mbed_official 445:3312ed629f01 231 MCGOUTClock *= 1280u;
mbed_official 445:3312ed629f01 232 break;
mbed_official 445:3312ed629f01 233 case 0x40u:
mbed_official 445:3312ed629f01 234 MCGOUTClock *= 1920u;
mbed_official 445:3312ed629f01 235 break;
mbed_official 445:3312ed629f01 236 case 0x60u:
mbed_official 445:3312ed629f01 237 MCGOUTClock *= 2560u;
mbed_official 445:3312ed629f01 238 break;
mbed_official 445:3312ed629f01 239 case 0x80u:
mbed_official 445:3312ed629f01 240 MCGOUTClock *= 732u;
mbed_official 445:3312ed629f01 241 break;
mbed_official 445:3312ed629f01 242 case 0xA0u:
mbed_official 445:3312ed629f01 243 MCGOUTClock *= 1464u;
mbed_official 445:3312ed629f01 244 break;
mbed_official 445:3312ed629f01 245 case 0xC0u:
mbed_official 445:3312ed629f01 246 MCGOUTClock *= 2197u;
mbed_official 445:3312ed629f01 247 break;
mbed_official 445:3312ed629f01 248 case 0xE0u:
mbed_official 445:3312ed629f01 249 MCGOUTClock *= 2929u;
mbed_official 445:3312ed629f01 250 break;
mbed_official 445:3312ed629f01 251 default:
mbed_official 445:3312ed629f01 252 break;
mbed_official 445:3312ed629f01 253 }
mbed_official 445:3312ed629f01 254 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
mbed_official 445:3312ed629f01 255 /* PLL is selected */
mbed_official 445:3312ed629f01 256 Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
mbed_official 445:3312ed629f01 257 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
mbed_official 445:3312ed629f01 258 Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
mbed_official 445:3312ed629f01 259 MCGOUTClock *= Divider; /* Calculate the MCG output clock */
mbed_official 445:3312ed629f01 260 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
mbed_official 445:3312ed629f01 261 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
mbed_official 445:3312ed629f01 262 /* Internal reference clock is selected */
mbed_official 445:3312ed629f01 263 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
mbed_official 445:3312ed629f01 264 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
mbed_official 445:3312ed629f01 265 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
mbed_official 445:3312ed629f01 266 MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
mbed_official 445:3312ed629f01 267 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
mbed_official 445:3312ed629f01 268 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
mbed_official 445:3312ed629f01 269 /* External reference clock is selected */
mbed_official 445:3312ed629f01 270 if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
mbed_official 445:3312ed629f01 271 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
mbed_official 445:3312ed629f01 272 } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
mbed_official 445:3312ed629f01 273 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
mbed_official 445:3312ed629f01 274 } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
mbed_official 445:3312ed629f01 275 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
mbed_official 445:3312ed629f01 276 /* Reserved value */
mbed_official 445:3312ed629f01 277 return;
mbed_official 445:3312ed629f01 278 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
mbed_official 445:3312ed629f01 279 SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
mbed_official 633:188f3ef4d258 280 }