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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.c@87:085cde657901, 2014-02-08 (annotated)

Committer:
mbed_official
Date:
Sat Feb 08 19:45:06 2014 +0000
Revision:
87:085cde657901
Child:
106:ced8cbb51063
Synchronized with git revision 9272cdeb45ec7e6077641536509413da8fd2ebc2



Full URL: https://github.com/mbedmicro/mbed/commit/9272cdeb45ec7e6077641536509413da8fd2ebc2/



Add NUCLEO_F401RE, improvements

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 87:085cde657901 1 /**
mbed_official 87:085cde657901 2 ******************************************************************************
mbed_official 87:085cde657901 3 * @file stm32f4xx_hal_rcc_ex.c
mbed_official 87:085cde657901 4 * @author MCD Application Team
mbed_official 87:085cde657901 5 * @version V1.0.0RC2
mbed_official 87:085cde657901 6 * @date 04-February-2014
mbed_official 87:085cde657901 7 * @brief Extension RCC HAL module driver.
mbed_official 87:085cde657901 8 * This file provides firmware functions to manage the following
mbed_official 87:085cde657901 9 * functionalities RCC extension peripheral:
mbed_official 87:085cde657901 10 * + Extended Peripheral Control functions
mbed_official 87:085cde657901 11 *
mbed_official 87:085cde657901 12 ******************************************************************************
mbed_official 87:085cde657901 13 * @attention
mbed_official 87:085cde657901 14 *
mbed_official 87:085cde657901 15 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 87:085cde657901 16 *
mbed_official 87:085cde657901 17 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 87:085cde657901 18 * are permitted provided that the following conditions are met:
mbed_official 87:085cde657901 19 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 87:085cde657901 20 * this list of conditions and the following disclaimer.
mbed_official 87:085cde657901 21 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 87:085cde657901 22 * this list of conditions and the following disclaimer in the documentation
mbed_official 87:085cde657901 23 * and/or other materials provided with the distribution.
mbed_official 87:085cde657901 24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 87:085cde657901 25 * may be used to endorse or promote products derived from this software
mbed_official 87:085cde657901 26 * without specific prior written permission.
mbed_official 87:085cde657901 27 *
mbed_official 87:085cde657901 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 87:085cde657901 29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 87:085cde657901 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 87:085cde657901 31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 87:085cde657901 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 87:085cde657901 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 87:085cde657901 34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 87:085cde657901 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 87:085cde657901 36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 87:085cde657901 37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 87:085cde657901 38 *
mbed_official 87:085cde657901 39 ******************************************************************************
mbed_official 87:085cde657901 40 */
mbed_official 87:085cde657901 41
mbed_official 87:085cde657901 42 /* Includes ------------------------------------------------------------------*/
mbed_official 87:085cde657901 43 #include "stm32f4xx_hal.h"
mbed_official 87:085cde657901 44
mbed_official 87:085cde657901 45 /** @addtogroup STM32F4xx_HAL_Driver
mbed_official 87:085cde657901 46 * @{
mbed_official 87:085cde657901 47 */
mbed_official 87:085cde657901 48
mbed_official 87:085cde657901 49 /** @defgroup RCC
mbed_official 87:085cde657901 50 * @brief RCC HAL module driver
mbed_official 87:085cde657901 51 * @{
mbed_official 87:085cde657901 52 */
mbed_official 87:085cde657901 53
mbed_official 87:085cde657901 54 #ifdef HAL_RCC_MODULE_ENABLED
mbed_official 87:085cde657901 55
mbed_official 87:085cde657901 56 /* Private typedef -----------------------------------------------------------*/
mbed_official 87:085cde657901 57 /* Private define ------------------------------------------------------------*/
mbed_official 87:085cde657901 58 #define PLLI2S_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */
mbed_official 87:085cde657901 59 #define PLLSAI_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */
mbed_official 87:085cde657901 60 /* Private macro -------------------------------------------------------------*/
mbed_official 87:085cde657901 61 /* Private variables ---------------------------------------------------------*/
mbed_official 87:085cde657901 62 /* Private function prototypes -----------------------------------------------*/
mbed_official 87:085cde657901 63 /* Private functions ---------------------------------------------------------*/
mbed_official 87:085cde657901 64
mbed_official 87:085cde657901 65 /** @defgroup RCCEx_Private_Functions
mbed_official 87:085cde657901 66 * @{
mbed_official 87:085cde657901 67 */
mbed_official 87:085cde657901 68
mbed_official 87:085cde657901 69 /** @defgroup RCCEx_Group1 Extended Peripheral Control functions
mbed_official 87:085cde657901 70 * @brief Extended Peripheral Control functions
mbed_official 87:085cde657901 71 *
mbed_official 87:085cde657901 72 @verbatim
mbed_official 87:085cde657901 73 ===============================================================================
mbed_official 87:085cde657901 74 ##### Extended Peripheral Control functions #####
mbed_official 87:085cde657901 75 ===============================================================================
mbed_official 87:085cde657901 76 [..]
mbed_official 87:085cde657901 77 This subsection provides a set of functions allowing to control the RCC Clocks
mbed_official 87:085cde657901 78 frequencies.
mbed_official 87:085cde657901 79
mbed_official 87:085cde657901 80 @endverbatim
mbed_official 87:085cde657901 81 * @{
mbed_official 87:085cde657901 82 */
mbed_official 87:085cde657901 83 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
mbed_official 87:085cde657901 84 /**
mbed_official 87:085cde657901 85 * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
mbed_official 87:085cde657901 86 * RCC_PeriphCLKInitTypeDef.
mbed_official 87:085cde657901 87 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
mbed_official 87:085cde657901 88 * contains the configuration information for the Extended Peripherals clocks(I2S, SAI, LTDC RTC and TIM clocks).
mbed_official 87:085cde657901 89 * @retval HAL status
mbed_official 87:085cde657901 90 */
mbed_official 87:085cde657901 91 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
mbed_official 87:085cde657901 92 {
mbed_official 87:085cde657901 93 uint32_t timeout = 0;
mbed_official 87:085cde657901 94 uint32_t tmpreg = 0;
mbed_official 87:085cde657901 95
mbed_official 87:085cde657901 96 /* Check the parameters */
mbed_official 87:085cde657901 97 assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
mbed_official 87:085cde657901 98
mbed_official 87:085cde657901 99 /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------------*/
mbed_official 87:085cde657901 100
mbed_official 87:085cde657901 101 /*----------------------- Common configuration SAI/I2S ---------------------------*/
mbed_official 87:085cde657901 102 /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
mbed_official 87:085cde657901 103 factor is common parameters for both peripherals */
mbed_official 87:085cde657901 104 if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
mbed_official 87:085cde657901 105 (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S))
mbed_official 87:085cde657901 106 {
mbed_official 87:085cde657901 107 /* check for Parameters */
mbed_official 87:085cde657901 108 assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
mbed_official 87:085cde657901 109
mbed_official 87:085cde657901 110 /* Disable the PLLI2S */
mbed_official 87:085cde657901 111 __HAL_RCC_PLLI2S_DISABLE();
mbed_official 87:085cde657901 112 /* Get new Timeout value */
mbed_official 87:085cde657901 113 timeout = HAL_GetTick() + PLLI2S_TIMEOUT_VALUE;
mbed_official 87:085cde657901 114 /* Wait till PLLI2S is disabled */
mbed_official 87:085cde657901 115 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
mbed_official 87:085cde657901 116 {
mbed_official 87:085cde657901 117 if(HAL_GetTick() >= timeout)
mbed_official 87:085cde657901 118 {
mbed_official 87:085cde657901 119 /* return in case of Timeout detected */
mbed_official 87:085cde657901 120 return HAL_TIMEOUT;
mbed_official 87:085cde657901 121 }
mbed_official 87:085cde657901 122 }
mbed_official 87:085cde657901 123
mbed_official 87:085cde657901 124 /*---------------------------- I2S configuration -------------------------------*/
mbed_official 87:085cde657901 125 /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
mbed_official 87:085cde657901 126 only for I2S configuration */
mbed_official 87:085cde657901 127 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
mbed_official 87:085cde657901 128 {
mbed_official 87:085cde657901 129 /* check for Parameters */
mbed_official 87:085cde657901 130 assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
mbed_official 87:085cde657901 131 /* Configure the PLLI2S division factors */
mbed_official 87:085cde657901 132 /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLM) */
mbed_official 87:085cde657901 133 /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
mbed_official 87:085cde657901 134 __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
mbed_official 87:085cde657901 135 }
mbed_official 87:085cde657901 136
mbed_official 87:085cde657901 137 /*---------------------------- SAI configuration -------------------------------*/
mbed_official 87:085cde657901 138 /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
mbed_official 87:085cde657901 139 be added only for SAI configuration */
mbed_official 87:085cde657901 140 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
mbed_official 87:085cde657901 141 {
mbed_official 87:085cde657901 142 /* Check the PLLI2S division factors */
mbed_official 87:085cde657901 143 assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
mbed_official 87:085cde657901 144 assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
mbed_official 87:085cde657901 145
mbed_official 87:085cde657901 146 /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
mbed_official 87:085cde657901 147 tmpreg = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
mbed_official 87:085cde657901 148 /* Configure the PLLI2S division factors */
mbed_official 87:085cde657901 149 /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
mbed_official 87:085cde657901 150 /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
mbed_official 87:085cde657901 151 /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
mbed_official 87:085cde657901 152 __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg);
mbed_official 87:085cde657901 153 /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
mbed_official 87:085cde657901 154 __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
mbed_official 87:085cde657901 155 }
mbed_official 87:085cde657901 156
mbed_official 87:085cde657901 157 /* Enable the PLLI2S */
mbed_official 87:085cde657901 158 __HAL_RCC_PLLI2S_ENABLE();
mbed_official 87:085cde657901 159 /* Get new Timeout value */
mbed_official 87:085cde657901 160 timeout = HAL_GetTick() + PLLI2S_TIMEOUT_VALUE;
mbed_official 87:085cde657901 161 /* Wait till PLLI2S is ready */
mbed_official 87:085cde657901 162 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
mbed_official 87:085cde657901 163 {
mbed_official 87:085cde657901 164 if(HAL_GetTick() >= timeout)
mbed_official 87:085cde657901 165 {
mbed_official 87:085cde657901 166 /* return in case of Timeout detected */
mbed_official 87:085cde657901 167 return HAL_TIMEOUT;
mbed_official 87:085cde657901 168 }
mbed_official 87:085cde657901 169 }
mbed_official 87:085cde657901 170 }
mbed_official 87:085cde657901 171
mbed_official 87:085cde657901 172 /*----------------------- SAI/LTDC Configuration (PLLSAI) -------------------------*/
mbed_official 87:085cde657901 173
mbed_official 87:085cde657901 174 /*----------------------- Common configuration SAI/LTDC ---------------------------*/
mbed_official 87:085cde657901 175 /* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division
mbed_official 87:085cde657901 176 factor is common parameters for both peripherals */
mbed_official 87:085cde657901 177 if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||
mbed_official 87:085cde657901 178 (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC))
mbed_official 87:085cde657901 179 {
mbed_official 87:085cde657901 180 /* Check the PLLSAI division factors */
mbed_official 87:085cde657901 181 assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
mbed_official 87:085cde657901 182
mbed_official 87:085cde657901 183 /* Disable PLLSAI Clock */
mbed_official 87:085cde657901 184 __HAL_RCC_PLLSAI_DISABLE();
mbed_official 87:085cde657901 185 /* Get new Timeout value */
mbed_official 87:085cde657901 186 timeout = HAL_GetTick() + PLLSAI_TIMEOUT_VALUE;
mbed_official 87:085cde657901 187 /* Wait till PLLSAI is disabled */
mbed_official 87:085cde657901 188 while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
mbed_official 87:085cde657901 189 {
mbed_official 87:085cde657901 190 if(HAL_GetTick() >= timeout)
mbed_official 87:085cde657901 191 {
mbed_official 87:085cde657901 192 /* return in case of Timeout detected */
mbed_official 87:085cde657901 193 return HAL_TIMEOUT;
mbed_official 87:085cde657901 194 }
mbed_official 87:085cde657901 195 }
mbed_official 87:085cde657901 196
mbed_official 87:085cde657901 197 /*---------------------------- SAI configuration -------------------------------*/
mbed_official 87:085cde657901 198 /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
mbed_official 87:085cde657901 199 be added only for SAI configuration */
mbed_official 87:085cde657901 200 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
mbed_official 87:085cde657901 201 {
mbed_official 87:085cde657901 202 assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
mbed_official 87:085cde657901 203 assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
mbed_official 87:085cde657901 204
mbed_official 87:085cde657901 205 /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
mbed_official 87:085cde657901 206 tmpreg = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
mbed_official 87:085cde657901 207 /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
mbed_official 87:085cde657901 208 /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
mbed_official 87:085cde657901 209 /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
mbed_official 87:085cde657901 210 __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg);
mbed_official 87:085cde657901 211 /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
mbed_official 87:085cde657901 212 __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
mbed_official 87:085cde657901 213 }
mbed_official 87:085cde657901 214
mbed_official 87:085cde657901 215 /*---------------------------- LTDC configuration -------------------------------*/
mbed_official 87:085cde657901 216 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
mbed_official 87:085cde657901 217 {
mbed_official 87:085cde657901 218 assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
mbed_official 87:085cde657901 219 assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
mbed_official 87:085cde657901 220
mbed_official 87:085cde657901 221 /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
mbed_official 87:085cde657901 222 tmpreg = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
mbed_official 87:085cde657901 223 /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
mbed_official 87:085cde657901 224 /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
mbed_official 87:085cde657901 225 /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
mbed_official 87:085cde657901 226 __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg, PeriphClkInit->PLLSAI.PLLSAIR);
mbed_official 87:085cde657901 227 /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
mbed_official 87:085cde657901 228 __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
mbed_official 87:085cde657901 229 }
mbed_official 87:085cde657901 230 /* Enable PLLSAI Clock */
mbed_official 87:085cde657901 231 __HAL_RCC_PLLSAI_ENABLE();
mbed_official 87:085cde657901 232 /* Get new Timeout value */
mbed_official 87:085cde657901 233 timeout = HAL_GetTick() + PLLSAI_TIMEOUT_VALUE;
mbed_official 87:085cde657901 234 /* Wait till PLLSAI is ready */
mbed_official 87:085cde657901 235 while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
mbed_official 87:085cde657901 236 {
mbed_official 87:085cde657901 237 if(HAL_GetTick() >= timeout)
mbed_official 87:085cde657901 238 {
mbed_official 87:085cde657901 239 /* return in case of Timeout detected */
mbed_official 87:085cde657901 240 return HAL_TIMEOUT;
mbed_official 87:085cde657901 241 }
mbed_official 87:085cde657901 242 }
mbed_official 87:085cde657901 243 }
mbed_official 87:085cde657901 244
mbed_official 87:085cde657901 245
mbed_official 87:085cde657901 246 /*---------------------------- RTC configuration -------------------------------*/
mbed_official 87:085cde657901 247 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
mbed_official 87:085cde657901 248 {
mbed_official 87:085cde657901 249 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
mbed_official 87:085cde657901 250 }
mbed_official 87:085cde657901 251
mbed_official 87:085cde657901 252 /*---------------------------- TIM configuration -------------------------------*/
mbed_official 87:085cde657901 253 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
mbed_official 87:085cde657901 254 {
mbed_official 87:085cde657901 255 __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
mbed_official 87:085cde657901 256 }
mbed_official 87:085cde657901 257 return HAL_OK;
mbed_official 87:085cde657901 258 }
mbed_official 87:085cde657901 259
mbed_official 87:085cde657901 260 /**
mbed_official 87:085cde657901 261 * @brief Configures the RCC_OscInitStruct according to the internal
mbed_official 87:085cde657901 262 * RCC configuration registers.
mbed_official 87:085cde657901 263 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
mbed_official 87:085cde657901 264 * will be configured.
mbed_official 87:085cde657901 265 * @retval None
mbed_official 87:085cde657901 266 */
mbed_official 87:085cde657901 267 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
mbed_official 87:085cde657901 268 {
mbed_official 87:085cde657901 269 uint32_t tempreg;
mbed_official 87:085cde657901 270
mbed_official 87:085cde657901 271 /* Set all possible values for the extended clock type parameter------------*/
mbed_official 87:085cde657901 272 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI | RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC;
mbed_official 87:085cde657901 273
mbed_official 87:085cde657901 274 /* Get the PLLI2S Clock configuration -----------------------------------------------*/
mbed_official 87:085cde657901 275 PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
mbed_official 87:085cde657901 276 PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
mbed_official 87:085cde657901 277 PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
mbed_official 87:085cde657901 278 /* Get the PLLSAI Clock configuration -----------------------------------------------*/
mbed_official 87:085cde657901 279 PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
mbed_official 87:085cde657901 280 PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
mbed_official 87:085cde657901 281 PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
mbed_official 87:085cde657901 282 /* Get the PLLSAI/PLLI2S division factors -----------------------------------------------*/
mbed_official 87:085cde657901 283 PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ));
mbed_official 87:085cde657901 284 PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ));
mbed_official 87:085cde657901 285 PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);
mbed_official 87:085cde657901 286 /* Get the RTC Clock configuration -----------------------------------------------*/
mbed_official 87:085cde657901 287 tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
mbed_official 87:085cde657901 288 PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
mbed_official 87:085cde657901 289
mbed_official 87:085cde657901 290 if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
mbed_official 87:085cde657901 291 {
mbed_official 87:085cde657901 292 PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
mbed_official 87:085cde657901 293 }
mbed_official 87:085cde657901 294 else
mbed_official 87:085cde657901 295 {
mbed_official 87:085cde657901 296 PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
mbed_official 87:085cde657901 297 }
mbed_official 87:085cde657901 298 }
mbed_official 87:085cde657901 299 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 87:085cde657901 300
mbed_official 87:085cde657901 301 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE)
mbed_official 87:085cde657901 302 /**
mbed_official 87:085cde657901 303 * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
mbed_official 87:085cde657901 304 * RCC_PeriphCLKInitTypeDef.
mbed_official 87:085cde657901 305 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
mbed_official 87:085cde657901 306 * contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
mbed_official 87:085cde657901 307 * @retval HAL status
mbed_official 87:085cde657901 308 */
mbed_official 87:085cde657901 309 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
mbed_official 87:085cde657901 310 {
mbed_official 87:085cde657901 311 uint32_t timeout = 0;
mbed_official 87:085cde657901 312
mbed_official 87:085cde657901 313 /* Check the parameters */
mbed_official 87:085cde657901 314 assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
mbed_official 87:085cde657901 315
mbed_official 87:085cde657901 316 /*---------------------------- I2S configuration -------------------------------*/
mbed_official 87:085cde657901 317 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
mbed_official 87:085cde657901 318 {
mbed_official 87:085cde657901 319 /* check for Parameters */
mbed_official 87:085cde657901 320 assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
mbed_official 87:085cde657901 321 assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
mbed_official 87:085cde657901 322
mbed_official 87:085cde657901 323 /* Disable the PLLI2S */
mbed_official 87:085cde657901 324 __HAL_RCC_PLLI2S_DISABLE();
mbed_official 87:085cde657901 325 /* Get new Timeout value */
mbed_official 87:085cde657901 326 timeout = HAL_GetTick() + PLLI2S_TIMEOUT_VALUE;
mbed_official 87:085cde657901 327 /* Wait till PLLI2S is disabled */
mbed_official 87:085cde657901 328 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
mbed_official 87:085cde657901 329 {
mbed_official 87:085cde657901 330 if(HAL_GetTick() >= timeout)
mbed_official 87:085cde657901 331 {
mbed_official 87:085cde657901 332 /* return in case of Timeout detected */
mbed_official 87:085cde657901 333 return HAL_TIMEOUT;
mbed_official 87:085cde657901 334 }
mbed_official 87:085cde657901 335 }
mbed_official 87:085cde657901 336 /* Configure the PLLI2S division factors */
mbed_official 87:085cde657901 337 /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLM) */
mbed_official 87:085cde657901 338 /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
mbed_official 87:085cde657901 339 __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
mbed_official 87:085cde657901 340
mbed_official 87:085cde657901 341 /* Enable the PLLI2S */
mbed_official 87:085cde657901 342 __HAL_RCC_PLLI2S_ENABLE();
mbed_official 87:085cde657901 343 /* Get new Timeout value */
mbed_official 87:085cde657901 344 timeout = HAL_GetTick() + PLLI2S_TIMEOUT_VALUE;
mbed_official 87:085cde657901 345 /* Wait till PLLI2S is ready */
mbed_official 87:085cde657901 346 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
mbed_official 87:085cde657901 347 {
mbed_official 87:085cde657901 348 if(HAL_GetTick() >= timeout)
mbed_official 87:085cde657901 349 {
mbed_official 87:085cde657901 350 /* return in case of Timeout detected */
mbed_official 87:085cde657901 351 return HAL_TIMEOUT;
mbed_official 87:085cde657901 352 }
mbed_official 87:085cde657901 353 }
mbed_official 87:085cde657901 354 }
mbed_official 87:085cde657901 355
mbed_official 87:085cde657901 356 /*---------------------------- RTC configuration -------------------------------*/
mbed_official 87:085cde657901 357 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
mbed_official 87:085cde657901 358 {
mbed_official 87:085cde657901 359 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
mbed_official 87:085cde657901 360 }
mbed_official 87:085cde657901 361
mbed_official 87:085cde657901 362 return HAL_OK;
mbed_official 87:085cde657901 363 }
mbed_official 87:085cde657901 364
mbed_official 87:085cde657901 365 /**
mbed_official 87:085cde657901 366 * @brief Configures the RCC_OscInitStruct according to the internal
mbed_official 87:085cde657901 367 * RCC configuration registers.
mbed_official 87:085cde657901 368 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
mbed_official 87:085cde657901 369 * will be configured.
mbed_official 87:085cde657901 370 * @retval None
mbed_official 87:085cde657901 371 */
mbed_official 87:085cde657901 372 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
mbed_official 87:085cde657901 373 {
mbed_official 87:085cde657901 374 uint32_t tempreg;
mbed_official 87:085cde657901 375
mbed_official 87:085cde657901 376 /* Set all possible values for the extended clock type parameter------------*/
mbed_official 87:085cde657901 377 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_RTC;
mbed_official 87:085cde657901 378
mbed_official 87:085cde657901 379 /* Get the PLLI2S Clock configuration -----------------------------------------------*/
mbed_official 87:085cde657901 380 PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
mbed_official 87:085cde657901 381 PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
mbed_official 87:085cde657901 382
mbed_official 87:085cde657901 383 /* Get the RTC Clock configuration -----------------------------------------------*/
mbed_official 87:085cde657901 384 tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
mbed_official 87:085cde657901 385 PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
mbed_official 87:085cde657901 386
mbed_official 87:085cde657901 387 }
mbed_official 87:085cde657901 388 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */
mbed_official 87:085cde657901 389 /**
mbed_official 87:085cde657901 390 * @}
mbed_official 87:085cde657901 391 */
mbed_official 87:085cde657901 392
mbed_official 87:085cde657901 393 /**
mbed_official 87:085cde657901 394 * @}
mbed_official 87:085cde657901 395 */
mbed_official 87:085cde657901 396
mbed_official 87:085cde657901 397 #endif /* HAL_RCC_MODULE_ENABLED */
mbed_official 87:085cde657901 398 /**
mbed_official 87:085cde657901 399 * @}
mbed_official 87:085cde657901 400 */
mbed_official 87:085cde657901 401
mbed_official 87:085cde657901 402 /**
mbed_official 87:085cde657901 403 * @}
mbed_official 87:085cde657901 404 */
mbed_official 87:085cde657901 405
mbed_official 87:085cde657901 406 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/