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Superseded

This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

Import librarymbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_pwm.h@619:034e698bc035, 2015-09-04 (annotated)

Committer:
mbed_official
Date:
Fri Sep 04 09:30:10 2015 +0100
Revision:
619:034e698bc035
Parent:
targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_pwm.h@558:0880f51c4036 
Synchronized with git revision 92d1bfad30082571776c810a56fd471d30514ccf



Full URL: https://github.com/mbedmicro/mbed/commit/92d1bfad30082571776c810a56fd471d30514ccf/



Change directory structure and move files.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 558:0880f51c4036 1 /**
mbed_official 558:0880f51c4036 2 ******************************************************************************
mbed_official 558:0880f51c4036 3 * @file
mbed_official 558:0880f51c4036 4 * @author
mbed_official 558:0880f51c4036 5 * @version
mbed_official 558:0880f51c4036 6 * @date
mbed_official 558:0880f51c4036 7 * @brief This file contains all the functions prototypes for the UART
mbed_official 558:0880f51c4036 8 * firmware library.
mbed_official 558:0880f51c4036 9 ******************************************************************************
mbed_official 558:0880f51c4036 10 *
mbed_official 558:0880f51c4036 11 ******************************************************************************
mbed_official 558:0880f51c4036 12 */
mbed_official 558:0880f51c4036 13
mbed_official 558:0880f51c4036 14 /* Define to prevent recursive inclusion -------------------------------------*/
mbed_official 558:0880f51c4036 15 #ifndef __W7500X_PWM_H
mbed_official 558:0880f51c4036 16 #define __W7500X_PWM_H
mbed_official 558:0880f51c4036 17
mbed_official 558:0880f51c4036 18 #ifdef __cplusplus
mbed_official 558:0880f51c4036 19 extern "C" {
mbed_official 558:0880f51c4036 20 #endif
mbed_official 558:0880f51c4036 21
mbed_official 558:0880f51c4036 22 /* Includes ------------------------------------------------------------------*/
mbed_official 558:0880f51c4036 23 #include "W7500x.h"
mbed_official 558:0880f51c4036 24
mbed_official 558:0880f51c4036 25 /**********************************************************************************************/
mbed_official 558:0880f51c4036 26 /**********************************************************************************************/
mbed_official 558:0880f51c4036 27 // This structure and define must be in W7500x.h
mbed_official 558:0880f51c4036 28 /**********************************************************************************************/
mbed_official 558:0880f51c4036 29 /**********************************************************************************************/
mbed_official 558:0880f51c4036 30
mbed_official 558:0880f51c4036 31 typedef struct
mbed_official 558:0880f51c4036 32 {
mbed_official 558:0880f51c4036 33 uint32_t PWM_CHn_PEEER;
mbed_official 558:0880f51c4036 34 }PWM_CtrlPWMOutputTypeDef;
mbed_official 558:0880f51c4036 35
mbed_official 558:0880f51c4036 36 typedef struct
mbed_official 558:0880f51c4036 37 {
mbed_official 558:0880f51c4036 38 uint32_t PWM_CHn_PR;
mbed_official 558:0880f51c4036 39 uint32_t PWM_CHn_MR;
mbed_official 558:0880f51c4036 40 uint32_t PWM_CHn_LR;
mbed_official 558:0880f51c4036 41 uint32_t PWM_CHn_UDMR;
mbed_official 558:0880f51c4036 42 uint32_t PWM_CHn_PDMR;
mbed_official 558:0880f51c4036 43 uint32_t PWM_CHn_DZCR;
mbed_official 558:0880f51c4036 44 }PWM_DeadzoneModeInitTypDef;
mbed_official 558:0880f51c4036 45
mbed_official 558:0880f51c4036 46 #define IS_PWM_ALL_CH(CHn) ((CHn == PWM_CH0) || \
mbed_official 558:0880f51c4036 47 (CHn == PWM_CH1) || \
mbed_official 558:0880f51c4036 48 (CHn == PWM_CH2) || \
mbed_official 558:0880f51c4036 49 (CHn == PWM_CH3) || \
mbed_official 558:0880f51c4036 50 (CHn == PWM_CH4) || \
mbed_official 558:0880f51c4036 51 (CHn == PWM_CH5) || \
mbed_official 558:0880f51c4036 52 (CHn == PWM_CH6) || \
mbed_official 558:0880f51c4036 53 (CHn == PWM_CH7))
mbed_official 558:0880f51c4036 54
mbed_official 558:0880f51c4036 55 #define PWM_IER_IE0_Enable (0x1ul << 0)
mbed_official 558:0880f51c4036 56 #define PWM_IER_IE1_Enable (0x1ul << 1)
mbed_official 558:0880f51c4036 57 #define PWM_IER_IE2_Enable (0x1ul << 2)
mbed_official 558:0880f51c4036 58 #define PWM_IER_IE3_Enable (0x1ul << 3)
mbed_official 558:0880f51c4036 59 #define PWM_IER_IE4_Enable (0x1ul << 4)
mbed_official 558:0880f51c4036 60 #define PWM_IER_IE5_Enable (0x1ul << 5)
mbed_official 558:0880f51c4036 61 #define PWM_IER_IE6_Enable (0x1ul << 6)
mbed_official 558:0880f51c4036 62 #define PWM_IER_IE7_Enable (0x1ul << 7)
mbed_official 558:0880f51c4036 63
mbed_official 558:0880f51c4036 64 #define PWM_IER_IE0_Disable ~PWM_IER_IE0_Enable
mbed_official 558:0880f51c4036 65 #define PWM_IER_IE1_Disable ~PWM_IER_IE1_Enable
mbed_official 558:0880f51c4036 66 #define PWM_IER_IE2_Disable ~PWM_IER_IE2_Enable
mbed_official 558:0880f51c4036 67 #define PWM_IER_IE3_Disable ~PWM_IER_IE3_Enable
mbed_official 558:0880f51c4036 68 #define PWM_IER_IE4_Disable ~PWM_IER_IE4_Enable
mbed_official 558:0880f51c4036 69 #define PWM_IER_IE5_Disable ~PWM_IER_IE5_Enable
mbed_official 558:0880f51c4036 70 #define PWM_IER_IE6_Disable ~PWM_IER_IE6_Enable
mbed_official 558:0880f51c4036 71 #define PWM_IER_IE7_Disable ~PWM_IER_IE7_Enable
mbed_official 558:0880f51c4036 72
mbed_official 558:0880f51c4036 73 #define PWM_SSR_SS0_Start (0x1ul << 0)
mbed_official 558:0880f51c4036 74 #define PWM_SSR_SS1_Start (0x1ul << 1)
mbed_official 558:0880f51c4036 75 #define PWM_SSR_SS2_Start (0x1ul << 2)
mbed_official 558:0880f51c4036 76 #define PWM_SSR_SS3_Start (0x1ul << 3)
mbed_official 558:0880f51c4036 77 #define PWM_SSR_SS4_Start (0x1ul << 4)
mbed_official 558:0880f51c4036 78 #define PWM_SSR_SS5_Start (0x1ul << 5)
mbed_official 558:0880f51c4036 79 #define PWM_SSR_SS6_Start (0x1ul << 6)
mbed_official 558:0880f51c4036 80 #define PWM_SSR_SS7_Start (0x1ul << 7)
mbed_official 558:0880f51c4036 81
mbed_official 558:0880f51c4036 82 #define PWM_SSR_SS0_Stop ~PWM_SSR_SS0_Start
mbed_official 558:0880f51c4036 83 #define PWM_SSR_SS1_Stop ~PWM_SSR_SS1_Start
mbed_official 558:0880f51c4036 84 #define PWM_SSR_SS2_Stop ~PWM_SSR_SS2_Start
mbed_official 558:0880f51c4036 85 #define PWM_SSR_SS3_Stop ~PWM_SSR_SS3_Start
mbed_official 558:0880f51c4036 86 #define PWM_SSR_SS4_Stop ~PWM_SSR_SS4_Start
mbed_official 558:0880f51c4036 87 #define PWM_SSR_SS5_Stop ~PWM_SSR_SS5_Start
mbed_official 558:0880f51c4036 88 #define PWM_SSR_SS6_Stop ~PWM_SSR_SS6_Start
mbed_official 558:0880f51c4036 89 #define PWM_SSR_SS7_Stop ~PWM_SSR_SS7_Start
mbed_official 558:0880f51c4036 90
mbed_official 558:0880f51c4036 91 #define IS_SSR_BIT_FLAG(FLAG) (FLAG <= 0xFF)
mbed_official 558:0880f51c4036 92
mbed_official 558:0880f51c4036 93 #define PWM_PSR_PS0_Pause (0x1ul << 0)
mbed_official 558:0880f51c4036 94 #define PWM_PSR_PS1_Pause (0x1ul << 1)
mbed_official 558:0880f51c4036 95 #define PWM_PSR_PS2_Pause (0x1ul << 2)
mbed_official 558:0880f51c4036 96 #define PWM_PSR_PS3_Pause (0x1ul << 3)
mbed_official 558:0880f51c4036 97 #define PWM_PSR_PS4_Pause (0x1ul << 4)
mbed_official 558:0880f51c4036 98 #define PWM_PSR_PS5_Pause (0x1ul << 5)
mbed_official 558:0880f51c4036 99 #define PWM_PSR_PS6_Pause (0x1ul << 6)
mbed_official 558:0880f51c4036 100 #define PWM_PSR_PS7_Pause (0x1ul << 7)
mbed_official 558:0880f51c4036 101
mbed_official 558:0880f51c4036 102 #define PWM_PSR_PS0_Restart ~PWM_PSR_PS0_Pause
mbed_official 558:0880f51c4036 103 #define PWM_PSR_PS1_Restart ~PWM_PSR_PS1_Pause
mbed_official 558:0880f51c4036 104 #define PWM_PSR_PS2_Restart ~PWM_PSR_PS2_Pause
mbed_official 558:0880f51c4036 105 #define PWM_PSR_PS3_Restart ~PWM_PSR_PS3_Pause
mbed_official 558:0880f51c4036 106 #define PWM_PSR_PS4_Restart ~PWM_PSR_PS4_Pause
mbed_official 558:0880f51c4036 107 #define PWM_PSR_PS5_Restart ~PWM_PSR_PS5_Pause
mbed_official 558:0880f51c4036 108 #define PWM_PSR_PS6_Restart ~PWM_PSR_PS6_Pause
mbed_official 558:0880f51c4036 109 #define PWM_PSR_PS7_Restart ~PWM_PSR_PS7_Pause
mbed_official 558:0880f51c4036 110
mbed_official 558:0880f51c4036 111 #define IS_PWM_PSR_BIT_FLAG(FLAG) (FLAG <= 0xFF)
mbed_official 558:0880f51c4036 112
mbed_official 558:0880f51c4036 113 #define PWM_CHn_IER_MIE (0x1ul << 0) ///< Match Interrupt Enable
mbed_official 558:0880f51c4036 114 #define PWM_CHn_IER_OIE (0x1ul << 1) ///< Overflow Interrupt Enable
mbed_official 558:0880f51c4036 115 #define PWM_CHn_IER_CIE (0x1ul << 2) ///< Capture Interrupt Enable
mbed_official 558:0880f51c4036 116 #define IS_PWM_CHn_IER(FLAG) (FLAG <= 0x7)
mbed_official 558:0880f51c4036 117
mbed_official 558:0880f51c4036 118 #define PWM_CHn_IER_MI_Msk (0x1ul << 0) ///< Match Interrupt Enable Mask
mbed_official 558:0880f51c4036 119 #define PWM_CHn_IER_OI_Msk (0x1ul << 1) ///< Overflow Interrupt Enable Mask
mbed_official 558:0880f51c4036 120 #define PWM_CHn_IER_CI_Msk (0x1ul << 2) ///< Capture Interrupt Enable Mask
mbed_official 558:0880f51c4036 121
mbed_official 558:0880f51c4036 122 #define PWM_CHn_ICR_MatchInterruptClear (0x1ul << 0)
mbed_official 558:0880f51c4036 123 #define PWM_CHn_ICR_OverflowInterruptClear (0x1ul << 1)
mbed_official 558:0880f51c4036 124 #define PWM_CHn_ICR_CaptureInterruptClear (0x1ul << 2)
mbed_official 558:0880f51c4036 125 #define IS_PWM_CHn_IntClearFlag(FLAG) FLAG <= 0x7
mbed_official 558:0880f51c4036 126
mbed_official 558:0880f51c4036 127 /*
mbed_official 558:0880f51c4036 128 #define IS_PWM_STOP(CHn) (((CHn == PWM_CH0) && (PWM->SSR & PWM_SSR_SS0)) || \
mbed_official 558:0880f51c4036 129 ((CHn == PWM_CH1) && (PWM->SSR & PWM_SSR_SS1)) || \
mbed_official 558:0880f51c4036 130 ((CHn == PWM_CH2) && (PWM->SSR & PWM_SSR_SS2)) || \
mbed_official 558:0880f51c4036 131 ((CHn == PWM_CH3) && (PWM->SSR & PWM_SSR_SS3)) || \
mbed_official 558:0880f51c4036 132 ((CHn == PWM_CH4) && (PWM->SSR & PWM_SSR_SS4)) || \
mbed_official 558:0880f51c4036 133 ((CHn == PWM_CH5) && (PWM->SSR & PWM_SSR_SS5)) || \
mbed_official 558:0880f51c4036 134 ((CHn == PWM_CH6) && (PWM->SSR & PWM_SSR_SS6)) || \
mbed_official 558:0880f51c4036 135 ((CHn == PWM_CH7) && (PWM->SSR & PWM_SSR_SS7)))
mbed_official 558:0880f51c4036 136 */
mbed_official 558:0880f51c4036 137
mbed_official 558:0880f51c4036 138
mbed_official 558:0880f51c4036 139 #define IS_PWM_PR_FILTER(MAXVAL) (MAXVAL <= 0x1F)
mbed_official 558:0880f51c4036 140
mbed_official 558:0880f51c4036 141
mbed_official 558:0880f51c4036 142 #define PWM_CHn_UDMR_UpCount (0x0ul)
mbed_official 558:0880f51c4036 143 #define PWM_CHn_UDMR_DownCount (0x1ul)
mbed_official 558:0880f51c4036 144 #define IS_PWM_CHn_UDMR(MODE) ((MODE == PWM_CHn_UDMR_UpCount) || \
mbed_official 558:0880f51c4036 145 (MODE == PWM_CHn_UDMR_DownCount))
mbed_official 558:0880f51c4036 146
mbed_official 558:0880f51c4036 147 #define PWM_CHn_TCMR_TimerMode (0x0ul)
mbed_official 558:0880f51c4036 148 #define PWM_CHn_TCMR_RisingCounterMode (0x1ul)
mbed_official 558:0880f51c4036 149 #define PWM_CHn_TCMR_FallingCounterMode (0x2ul)
mbed_official 558:0880f51c4036 150 #define PWM_CHn_TCMR_BothCounterMode (0x3ul)
mbed_official 558:0880f51c4036 151 #define IS_PWM_CHn_TCMR(MODE) ((MODE == PWM_CHn_TCMR_RisingCounterMode) || \
mbed_official 558:0880f51c4036 152 (MODE == PWM_CHn_TCMR_FallingCounterMode) || \
mbed_official 558:0880f51c4036 153 (MODE == PWM_CHn_TCMR_BothCounterMode))
mbed_official 558:0880f51c4036 154
mbed_official 558:0880f51c4036 155 #define PWM_CHn_PEEER_Disable (0x0ul)
mbed_official 558:0880f51c4036 156 #define PWM_CHn_PEEER_ExtEnable (0x1ul)
mbed_official 558:0880f51c4036 157 #define PWM_CHn_PEEER_PWMEnable (0x2ul)
mbed_official 558:0880f51c4036 158 #define IS_PWM_CHn_PEEER(ENABLE) ((ENABLE == PWM_CHn_PEEER_Disable) || \
mbed_official 558:0880f51c4036 159 (ENABLE == PWM_CHn_PEEER_ExtEnable) || \
mbed_official 558:0880f51c4036 160 (ENABLE == PWM_CHn_PEEER_PWMEnable))
mbed_official 558:0880f51c4036 161
mbed_official 558:0880f51c4036 162 #define IS_PWM_Output(ENABLE) ((ENABLE == PWM_CHn_PEEER_Disable) || \
mbed_official 558:0880f51c4036 163 (ENABLE == PWM_CHn_PEEER_PWMEnable))
mbed_official 558:0880f51c4036 164
mbed_official 558:0880f51c4036 165 #define PWM_CHn_CMR_RisingEdge 0x0ul
mbed_official 558:0880f51c4036 166 #define PWM_CHn_CMR_FallingEdge 0x1ul
mbed_official 558:0880f51c4036 167 #define IS_PWM_CHn_CMR(MODE) ((MODE == PWM_CHn_CMR_RisingEdge) || \
mbed_official 558:0880f51c4036 168 (MODE == PWM_CHn_CMR_FallingEdge))
mbed_official 558:0880f51c4036 169
mbed_official 558:0880f51c4036 170 #define PWM_CHn_PDMR_Oneshot (0x0ul)
mbed_official 558:0880f51c4036 171 #define PWM_CHn_PDMR_Periodic (0x1ul)
mbed_official 558:0880f51c4036 172 #define IS_PWM_CHn_PDMR(MODE) ((MODE == PWM_CHn_PDMR_Periodic) || \
mbed_official 558:0880f51c4036 173 (MODE == PWM_CHn_PDMR_Oneshot))
mbed_official 558:0880f51c4036 174
mbed_official 558:0880f51c4036 175 #define PWM_CHn_DZER_Enable (0x1ul)
mbed_official 558:0880f51c4036 176 #define PWM_CHn_DZER_Disable (0x0ul)
mbed_official 558:0880f51c4036 177 #define PWM_CHn_DZER(ENABLE) ((ENABLE == PWM_CHn_DZER_Enable) || \
mbed_official 558:0880f51c4036 178 (ENABLE == PWM_CHn_DZER_Disable))
mbed_official 558:0880f51c4036 179
mbed_official 558:0880f51c4036 180 #define IS_PWM_Deadznoe(CHn) (((CHn == PWM_CH0) && (PWM_CH1->DZER == PWM_CHn_DZER_Disable)) || \
mbed_official 558:0880f51c4036 181 ((CHn == PWM_CH1) && (PWM_CH0->DZER == PWM_CHn_DZER_Disable)) || \
mbed_official 558:0880f51c4036 182 ((CHn == PWM_CH2) && (PWM_CH3->DZER == PWM_CHn_DZER_Disable)) || \
mbed_official 558:0880f51c4036 183 ((CHn == PWM_CH3) && (PWM_CH2->DZER == PWM_CHn_DZER_Disable)) || \
mbed_official 558:0880f51c4036 184 ((CHn == PWM_CH4) && (PWM_CH5->DZER == PWM_CHn_DZER_Disable)) || \
mbed_official 558:0880f51c4036 185 ((CHn == PWM_CH5) && (PWM_CH4->DZER == PWM_CHn_DZER_Disable)) || \
mbed_official 558:0880f51c4036 186 ((CHn == PWM_CH6) && (PWM_CH7->DZER == PWM_CHn_DZER_Disable)) || \
mbed_official 558:0880f51c4036 187 ((CHn == PWM_CH7) && (PWM_CH6->DZER == PWM_CHn_DZER_Disable)))
mbed_official 558:0880f51c4036 188
mbed_official 558:0880f51c4036 189 #define IS_PWM_CHn_DZCR_FILTER(MAXVAL) (MAXVAL <= 0x3FF)
mbed_official 558:0880f51c4036 190
mbed_official 558:0880f51c4036 191
mbed_official 558:0880f51c4036 192
mbed_official 558:0880f51c4036 193
mbed_official 558:0880f51c4036 194
mbed_official 558:0880f51c4036 195
mbed_official 558:0880f51c4036 196 void PWM_DeInit(PWM_CHn_TypeDef* PWM_CHn);
mbed_official 558:0880f51c4036 197 void PWM_TimerModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_TimerModeInitTypeDef* PWM_TimerModeInitStruct);
mbed_official 558:0880f51c4036 198 void PWM_CaptureModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CaptureModeInitTypeDef* PWM_CaptureModeInitStruct);
mbed_official 558:0880f51c4036 199 void PWM_CounterModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CounterModeInitTypeDef* PWM_CounterModeInitStruct);
mbed_official 558:0880f51c4036 200 void PWM_DeadzoneModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_DeadzoneModeInitTypDef* PWM_DeadzoneModeInitStruct);
mbed_official 558:0880f51c4036 201 void PWM_CtrlPWMOutput(PWM_CHn_TypeDef* PWM_CHn, uint32_t outputEnDisable );
mbed_official 558:0880f51c4036 202 void PWM_CtrlPWMOutputEnable(PWM_CHn_TypeDef* PWM_CHn) ;
mbed_official 558:0880f51c4036 203 void PWM_CtrlPWMOutputDisable(PWM_CHn_TypeDef* PWM_CHn) ;
mbed_official 558:0880f51c4036 204 void PWM_IntConfig(PWM_CHn_TypeDef* PWM_CHn, FunctionalState state);
mbed_official 558:0880f51c4036 205 FlagStatus PWM_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn);
mbed_official 558:0880f51c4036 206 void PWM_CHn_IntConfig(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_IER, FunctionalState state);
mbed_official 558:0880f51c4036 207 void PWM_CHn_Start(PWM_CHn_TypeDef* PWM_CHn);
mbed_official 558:0880f51c4036 208 void PWM_Multi_Start(uint32_t ssr_bit_flag);
mbed_official 558:0880f51c4036 209 void PWM_CHn_Stop(PWM_CHn_TypeDef* PWM_CHn);
mbed_official 558:0880f51c4036 210 void PWM_Multi_Stop(uint32_t ssr_bit_flag);
mbed_official 558:0880f51c4036 211 void PWM_CHn_Pause(PWM_CHn_TypeDef* PWM_CHn);
mbed_official 558:0880f51c4036 212 void PWM_Multi_Pause(uint32_t psr_bit_flag);
mbed_official 558:0880f51c4036 213 void PWM_CHn_Restart(PWM_CHn_TypeDef* PWM_CHn);
mbed_official 558:0880f51c4036 214 void PWM_Multi_Restart(uint32_t psr_bit_flag);
mbed_official 558:0880f51c4036 215 uint32_t PWM_CHn_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn);
mbed_official 558:0880f51c4036 216 uint32_t PWM_CHn_GetIntFlagStatus(PWM_CHn_TypeDef* PWM_CHn);
mbed_official 558:0880f51c4036 217 void PWM_CHn_ClearInt(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_ICR);
mbed_official 558:0880f51c4036 218 uint32_t PWM_CHn_GetTCR(PWM_CHn_TypeDef* PWM_CHn);
mbed_official 558:0880f51c4036 219 uint32_t PWM_CHn_GetPCR(PWM_CHn_TypeDef* PWM_CHn);
mbed_official 558:0880f51c4036 220 uint32_t PWM_CHn_GetPR(PWM_CHn_TypeDef* PWM_CHn);
mbed_official 558:0880f51c4036 221 void PWM_CHn_SetPR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PR);
mbed_official 558:0880f51c4036 222 uint32_t PWM_CHn_GetMR(PWM_CHn_TypeDef* PWM_CHn);
mbed_official 558:0880f51c4036 223 void PWM_CHn_SetMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t MR);
mbed_official 558:0880f51c4036 224 uint32_t PWM_CHn_GetLR(PWM_CHn_TypeDef* PWM_CHn);
mbed_official 558:0880f51c4036 225 void PWM_CHn_SetLR(PWM_CHn_TypeDef* PWM_CHn, uint32_t LR);
mbed_official 558:0880f51c4036 226 uint32_t PWM_CHn_GetUDMR(PWM_CHn_TypeDef* PWM_CHn);
mbed_official 558:0880f51c4036 227 void PWM_CHn_SetUDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t UDMR);
mbed_official 558:0880f51c4036 228 uint32_t PWM_CHn_GetTCMR(PWM_CHn_TypeDef* PWM_CHn);
mbed_official 558:0880f51c4036 229 void PWM_CHn_SetTCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t TCMR);
mbed_official 558:0880f51c4036 230 uint32_t PWM_CHn_GetPEEER(PWM_CHn_TypeDef* PWM_CHn);
mbed_official 558:0880f51c4036 231 void PWM_CHn_SetPEEER(PWM_CHn_TypeDef* PWM_CHn, uint32_t PEEER);
mbed_official 558:0880f51c4036 232 uint32_t PWM_CHn_GetCMR(PWM_CHn_TypeDef* PWM_CHn);
mbed_official 558:0880f51c4036 233 void PWM_CHn_SetCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t CMR);
mbed_official 558:0880f51c4036 234 uint32_t PWM_CHn_GetCR(PWM_CHn_TypeDef* PWM_CHn);
mbed_official 558:0880f51c4036 235 uint32_t PWM_CHn_GetPDMR(PWM_CHn_TypeDef* PWM_CHn);
mbed_official 558:0880f51c4036 236 void PWM_CHn_SetPDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PDMR);
mbed_official 558:0880f51c4036 237 void PWM_CHn_SetDZER(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZER);
mbed_official 558:0880f51c4036 238 uint32_t PWM_CHn_GetDZCR(PWM_CHn_TypeDef* PWM_CHn);
mbed_official 558:0880f51c4036 239 void PWM_CHn_SetDZCR(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZCR);
mbed_official 558:0880f51c4036 240 void PWM_CH0_ClearMatchInt(void);
mbed_official 558:0880f51c4036 241 void PWM_CH0_ClearOverflowInt(void);
mbed_official 558:0880f51c4036 242 void PWM_CH0_ClearCaptureInt(void);
mbed_official 558:0880f51c4036 243 void PWM_CH1_ClearMatchInt(void);
mbed_official 558:0880f51c4036 244 void PWM_CH1_ClearOverflowInt(void);
mbed_official 558:0880f51c4036 245 void PWM_CH1_ClearCaptureInt(void);
mbed_official 558:0880f51c4036 246 void PWM_CH2_ClearMatchInt(void);
mbed_official 558:0880f51c4036 247 void PWM_CH2_ClearOverflowInt(void);
mbed_official 558:0880f51c4036 248 void PWM_CH2_ClearCaptureInt(void);
mbed_official 558:0880f51c4036 249 void PWM_CH3_ClearMatchInt(void);
mbed_official 558:0880f51c4036 250 void PWM_CH3_ClearOverflowInt(void);
mbed_official 558:0880f51c4036 251 void PWM_CH3_ClearCaptureInt(void);
mbed_official 558:0880f51c4036 252 void PWM_CH4_ClearMatchInt(void);
mbed_official 558:0880f51c4036 253 void PWM_CH4_ClearOverflowInt(void);
mbed_official 558:0880f51c4036 254 void PWM_CH4_ClearCaptureInt(void);
mbed_official 558:0880f51c4036 255 void PWM_CH5_ClearMatchInt(void);
mbed_official 558:0880f51c4036 256 void PWM_CH5_ClearOverflowInt(void);
mbed_official 558:0880f51c4036 257 void PWM_CH5_ClearCaptureInt(void);
mbed_official 558:0880f51c4036 258 void PWM_CH6_ClearMatchInt(void);
mbed_official 558:0880f51c4036 259 void PWM_CH6_ClearOverflowInt(void);
mbed_official 558:0880f51c4036 260 void PWM_CH6_ClearCaptureInt(void);
mbed_official 558:0880f51c4036 261 void PWM_CH7_ClearMatchInt(void);
mbed_official 558:0880f51c4036 262 void PWM_CH7_ClearOverflowInt(void);
mbed_official 558:0880f51c4036 263 void PWM_CH7_ClearCaptureInt(void);
mbed_official 558:0880f51c4036 264
mbed_official 558:0880f51c4036 265
mbed_official 558:0880f51c4036 266 void PWM0_Handler(void);
mbed_official 558:0880f51c4036 267 void PWM1_Handler(void);
mbed_official 558:0880f51c4036 268 void PWM2_Handler(void);
mbed_official 558:0880f51c4036 269 void PWM3_Handler(void);
mbed_official 558:0880f51c4036 270 void PWM4_Handler(void);
mbed_official 558:0880f51c4036 271 void PWM5_Handler(void);
mbed_official 558:0880f51c4036 272 void PWM6_Handler(void);
mbed_official 558:0880f51c4036 273 void PWM7_Handler(void);
mbed_official 558:0880f51c4036 274
mbed_official 558:0880f51c4036 275
mbed_official 558:0880f51c4036 276
mbed_official 558:0880f51c4036 277
mbed_official 558:0880f51c4036 278 //Temporary macro=======
mbed_official 558:0880f51c4036 279 #define PWM_CH(N) ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + (N * 0x100UL)))
mbed_official 558:0880f51c4036 280 //======================
mbed_official 558:0880f51c4036 281
mbed_official 558:0880f51c4036 282
mbed_official 558:0880f51c4036 283 #ifdef __cplusplus
mbed_official 558:0880f51c4036 284 }
mbed_official 558:0880f51c4036 285 #endif
mbed_official 558:0880f51c4036 286
mbed_official 558:0880f51c4036 287
mbed_official 558:0880f51c4036 288 #endif //__W7500X_PWM_H
mbed_official 558:0880f51c4036 289