Official mbed Real Time Operating System based on the RTX implementation of the CMSIS-RTOS API open standard.
Dependents: denki-yohou_b TestY201 Network-RTOS NTPClient_HelloWorld ... more
Deprecated
This is the mbed 2 rtos library. mbed OS 5 integrates the mbed library with mbed-rtos. With this, we have provided thread safety for all mbed APIs. If you'd like to learn about using mbed OS 5, please see the docs.
Diff: rtx/TARGET_CORTEX_M/rt_HAL_CM.h
- Revision:
- 112:53ace74b190c
- Parent:
- 49:77c8e4604045
- Child:
- 118:6635230e06ba
--- a/rtx/TARGET_CORTEX_M/rt_HAL_CM.h Tue May 03 00:15:52 2016 +0100 +++ b/rtx/TARGET_CORTEX_M/rt_HAL_CM.h Thu May 05 20:45:13 2016 +0100 @@ -1,12 +1,12 @@ /*---------------------------------------------------------------------------- - * RL-ARM - RTX + * CMSIS-RTOS - RTX *---------------------------------------------------------------------------- * Name: RT_HAL_CM.H * Purpose: Hardware Abstraction Layer for Cortex-M definitions - * Rev.: V4.60 + * Rev.: V4.79 *---------------------------------------------------------------------------- * - * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -33,33 +33,38 @@ *---------------------------------------------------------------------------*/ /* Definitions */ -#define INITIAL_xPSR 0x01000000 -#define DEMCR_TRCENA 0x01000000 -#define ITM_ITMENA 0x00000001 -#define MAGIC_WORD 0xE25A2EA5 +#define INITIAL_xPSR 0x01000000U +#define DEMCR_TRCENA 0x01000000U +#define ITM_ITMENA 0x00000001U +#define MAGIC_WORD 0xE25A2EA5U +#define MAGIC_PATTERN 0xCCCCCCCCU #if defined (__CC_ARM) /* ARM Compiler */ -#if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M) && !NO_EXCLUSIVE_ACCESS) +#if ((defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M)) && !defined(NO_EXCLUSIVE_ACCESS)) #define __USE_EXCLUSIVE_ACCESS #else #undef __USE_EXCLUSIVE_ACCESS #endif +#ifndef __CMSIS_GENERIC +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0) +#endif + #elif defined (__GNUC__) /* GNU Compiler */ #undef __USE_EXCLUSIVE_ACCESS #if defined (__CORTEX_M0) || defined (__CORTEX_M0PLUS) -#define __TARGET_ARCH_6S_M 1 -#else -#define __TARGET_ARCH_6S_M 0 +#define __TARGET_ARCH_6S_M #endif #if defined (__VFP_FP__) && !defined(__SOFTFP__) -#define __TARGET_FPU_VFP 1 -#else -#define __TARGET_FPU_VFP 0 +#define __TARGET_FPU_VFP #endif #define __inline inline @@ -81,12 +86,17 @@ return(result & 1); } +__attribute__((always_inline)) static inline void __DMB(void) +{ + __asm volatile ("dmb 0xF":::"memory"); +} + #endif __attribute__(( always_inline)) static inline U8 __clz(U32 value) { U8 result; - + __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value)); return(result); } @@ -97,14 +107,10 @@ #if (__CORE__ == __ARM6M__) #define __TARGET_ARCH_6S_M 1 -#else -#define __TARGET_ARCH_6S_M 0 #endif #if defined __ARMVFP__ #define __TARGET_FPU_VFP 1 -#else -#define __TARGET_FPU_VFP 0 #endif #define __inline inline @@ -119,7 +125,7 @@ static inline U32 __disable_irq(void) { U32 result; - + __asm volatile ("mrs %0, primask" : "=r" (result)); __asm volatile ("cpsid i"); return(result & 1); @@ -130,7 +136,7 @@ static inline U8 __clz(U32 value) { U8 result; - + __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value)); return(result); } @@ -138,59 +144,59 @@ #endif /* NVIC registers */ -#define NVIC_ST_CTRL (*((volatile U32 *)0xE000E010)) -#define NVIC_ST_RELOAD (*((volatile U32 *)0xE000E014)) -#define NVIC_ST_CURRENT (*((volatile U32 *)0xE000E018)) -#define NVIC_ISER ((volatile U32 *)0xE000E100) -#define NVIC_ICER ((volatile U32 *)0xE000E180) -#if (__TARGET_ARCH_6S_M) -#define NVIC_IP ((volatile U32 *)0xE000E400) +#define NVIC_ST_CTRL (*((volatile U32 *)0xE000E010U)) +#define NVIC_ST_RELOAD (*((volatile U32 *)0xE000E014U)) +#define NVIC_ST_CURRENT (*((volatile U32 *)0xE000E018U)) +#define NVIC_ISER ((volatile U32 *)0xE000E100U) +#define NVIC_ICER ((volatile U32 *)0xE000E180U) +#if defined(__TARGET_ARCH_6S_M) +#define NVIC_IP ((volatile U32 *)0xE000E400U) #else -#define NVIC_IP ((volatile U8 *)0xE000E400) +#define NVIC_IP ((volatile U8 *)0xE000E400U) #endif -#define NVIC_INT_CTRL (*((volatile U32 *)0xE000ED04)) -#define NVIC_AIR_CTRL (*((volatile U32 *)0xE000ED0C)) -#define NVIC_SYS_PRI2 (*((volatile U32 *)0xE000ED1C)) -#define NVIC_SYS_PRI3 (*((volatile U32 *)0xE000ED20)) +#define NVIC_INT_CTRL (*((volatile U32 *)0xE000ED04U)) +#define NVIC_AIR_CTRL (*((volatile U32 *)0xE000ED0CU)) +#define NVIC_SYS_PRI2 (*((volatile U32 *)0xE000ED1CU)) +#define NVIC_SYS_PRI3 (*((volatile U32 *)0xE000ED20U)) -#define OS_PEND_IRQ() NVIC_INT_CTRL = (1<<28) -#define OS_PENDING ((NVIC_INT_CTRL >> 26) & (1<<2 | 1)) -#define OS_UNPEND(fl) NVIC_INT_CTRL = (*fl = OS_PENDING) << 25 -#define OS_PEND(fl,p) NVIC_INT_CTRL = (fl | p<<2) << 26 -#define OS_LOCK() NVIC_ST_CTRL = 0x0005 -#define OS_UNLOCK() NVIC_ST_CTRL = 0x0007 +#define OS_PEND_IRQ() NVIC_INT_CTRL = (1UL<<28) +#define OS_PENDING ((NVIC_INT_CTRL >> 26) & 5U) +#define OS_UNPEND(fl) NVIC_INT_CTRL = (U32)(fl = (U8)OS_PENDING) << 25 +#define OS_PEND(fl,p) NVIC_INT_CTRL = (U32)(fl | (U8)(p<<2)) << 26 +#define OS_LOCK() NVIC_ST_CTRL = 0x0005U +#define OS_UNLOCK() NVIC_ST_CTRL = 0x0007U -#define OS_X_PENDING ((NVIC_INT_CTRL >> 28) & 1) -#define OS_X_UNPEND(fl) NVIC_INT_CTRL = (*fl = OS_X_PENDING) << 27 -#define OS_X_PEND(fl,p) NVIC_INT_CTRL = (fl | p) << 28 -#if (__TARGET_ARCH_6S_M) -#define OS_X_INIT(n) NVIC_IP[n>>2] |= 0xFF << (8*(n & 0x03)); \ - NVIC_ISER[n>>5] = 1 << (n & 0x1F) +#define OS_X_PENDING ((NVIC_INT_CTRL >> 28) & 1U) +#define OS_X_UNPEND(fl) NVIC_INT_CTRL = (U32)(fl = (U8)OS_X_PENDING) << 27 +#define OS_X_PEND(fl,p) NVIC_INT_CTRL = (U32)(fl | p) << 28 +#if defined(__TARGET_ARCH_6S_M) +#define OS_X_INIT(n) NVIC_IP[n>>2] |= (U32)0xFFU << ((n & 0x03U) << 3); \ + NVIC_ISER[n>>5] = (U32)1U << (n & 0x1FU) #else -#define OS_X_INIT(n) NVIC_IP[n] = 0xFF; \ - NVIC_ISER[n>>5] = 1 << (n & 0x1F) +#define OS_X_INIT(n) NVIC_IP[n] = 0xFFU; \ + NVIC_ISER[n>>5] = (U32)1U << (n & 0x1FU) #endif -#define OS_X_LOCK(n) NVIC_ICER[n>>5] = 1 << (n & 0x1F) -#define OS_X_UNLOCK(n) NVIC_ISER[n>>5] = 1 << (n & 0x1F) +#define OS_X_LOCK(n) NVIC_ICER[n>>5] = (U32)1U << (n & 0x1FU) +#define OS_X_UNLOCK(n) NVIC_ISER[n>>5] = (U32)1U << (n & 0x1FU) /* Core Debug registers */ -#define DEMCR (*((volatile U32 *)0xE000EDFC)) +#define DEMCR (*((volatile U32 *)0xE000EDFCU)) /* ITM registers */ -#define ITM_CONTROL (*((volatile U32 *)0xE0000E80)) -#define ITM_ENABLE (*((volatile U32 *)0xE0000E00)) -#define ITM_PORT30_U32 (*((volatile U32 *)0xE0000078)) -#define ITM_PORT31_U32 (*((volatile U32 *)0xE000007C)) -#define ITM_PORT31_U16 (*((volatile U16 *)0xE000007C)) -#define ITM_PORT31_U8 (*((volatile U8 *)0xE000007C)) +#define ITM_CONTROL (*((volatile U32 *)0xE0000E80U)) +#define ITM_ENABLE (*((volatile U32 *)0xE0000E00U)) +#define ITM_PORT30_U32 (*((volatile U32 *)0xE0000078U)) +#define ITM_PORT31_U32 (*((volatile U32 *)0xE000007CU)) +#define ITM_PORT31_U16 (*((volatile U16 *)0xE000007CU)) +#define ITM_PORT31_U8 (*((volatile U8 *)0xE000007CU)) /* Variables */ extern BIT dbg_msg; /* Functions */ #ifdef __USE_EXCLUSIVE_ACCESS - #define rt_inc(p) while(__strex((__ldrex(p)+1),p)) - #define rt_dec(p) while(__strex((__ldrex(p)-1),p)) + #define rt_inc(p) while(__strex((__ldrex(p)+1U),p)) + #define rt_dec(p) while(__strex((__ldrex(p)-1U),p)) #else #define rt_inc(p) __disable_irq();(*p)++;__enable_irq(); #define rt_dec(p) __disable_irq();(*p)--;__enable_irq(); @@ -203,18 +209,18 @@ if ((cnt = __ldrex(count)) == size) { __clrex(); return (cnt); } - } while (__strex(cnt+1, count)); + } while (__strex(cnt+1U, count)); do { - c2 = (cnt = __ldrex(first)) + 1; - if (c2 == size) c2 = 0; + c2 = (cnt = __ldrex(first)) + 1U; + if (c2 == size) { c2 = 0U; } } while (__strex(c2, first)); #else __disable_irq(); if ((cnt = *count) < size) { - *count = cnt+1; - c2 = (cnt = *first) + 1; - if (c2 == size) c2 = 0; - *first = c2; + *count = (U8)(cnt+1U); + c2 = (cnt = *first) + 1U; + if (c2 == size) { c2 = 0U; } + *first = (U8)c2; } __enable_irq (); #endif @@ -223,25 +229,33 @@ __inline static void rt_systick_init (void) { NVIC_ST_RELOAD = os_trv; - NVIC_ST_CURRENT = 0; - NVIC_ST_CTRL = 0x0007; - NVIC_SYS_PRI3 |= 0xFF000000; + NVIC_ST_CURRENT = 0U; + NVIC_ST_CTRL = 0x0007U; + NVIC_SYS_PRI3 |= 0xFF000000U; +} + +__inline static U32 rt_systick_val (void) { + return (os_trv - NVIC_ST_CURRENT); +} + +__inline static U32 rt_systick_ovf (void) { + return ((NVIC_INT_CTRL >> 26) & 1U); } __inline static void rt_svc_init (void) { -#if !(__TARGET_ARCH_6S_M) - int sh,prigroup; +#if !defined(__TARGET_ARCH_6S_M) + U32 sh,prigroup; #endif - NVIC_SYS_PRI3 |= 0x00FF0000; -#if (__TARGET_ARCH_6S_M) - NVIC_SYS_PRI2 |= (NVIC_SYS_PRI3<<(8+1)) & 0xFC000000; + NVIC_SYS_PRI3 |= 0x00FF0000U; +#if defined(__TARGET_ARCH_6S_M) + NVIC_SYS_PRI2 |= (NVIC_SYS_PRI3<<(8+1)) & 0xFC000000U; #else - sh = 8 - __clz (~((NVIC_SYS_PRI3 << 8) & 0xFF000000)); - prigroup = ((NVIC_AIR_CTRL >> 8) & 0x07); + sh = 8U - __clz(~((NVIC_SYS_PRI3 << 8) & 0xFF000000U)); + prigroup = ((NVIC_AIR_CTRL >> 8) & 0x07U); if (prigroup >= sh) { - sh = prigroup + 1; + sh = prigroup + 1U; } - NVIC_SYS_PRI2 = ((0xFEFFFFFF << sh) & 0xFF000000) | (NVIC_SYS_PRI2 & 0x00FFFFFF); + NVIC_SYS_PRI2 = ((0xFEFFFFFFU << sh) & 0xFF000000U) | (NVIC_SYS_PRI2 & 0x00FFFFFFU); #endif } @@ -249,7 +263,7 @@ extern U32 rt_get_PSP (void); extern void os_set_env (void); extern void *_alloc_box (void *box_mem); -extern int _free_box (void *box_mem, void *box); +extern U32 _free_box (void *box_mem, void *box); extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body); extern void rt_ret_val (P_TCB p_TCB, U32 v0); @@ -262,8 +276,8 @@ #ifdef DBG_MSG #define DBG_INIT() dbg_init() #define DBG_TASK_NOTIFY(p_tcb,create) if (dbg_msg) dbg_task_notify(p_tcb,create) -#define DBG_TASK_SWITCH(task_id) if (dbg_msg && (os_tsk.new_tsk != os_tsk.run)) \ - dbg_task_switch(task_id) +#define DBG_TASK_SWITCH(task_id) if (dbg_msg && (os_tsk.new_tsk!=os_tsk.run)) \ + dbg_task_switch(task_id) #else #define DBG_INIT() #define DBG_TASK_NOTIFY(p_tcb,create) @@ -273,4 +287,3 @@ /*---------------------------------------------------------------------------- * end of file *---------------------------------------------------------------------------*/ -