Diff: targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c

Revision:

177:d650f5d4c87a

Parent:

174:b96e65c34a4d

Child:

180:96ed750bd169

--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c	Wed Oct 25 14:53:38 2017 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c	Wed Nov 08 13:50:44 2017 +0000
@@ -44,15 +44,25 @@
 
 #elif defined (__ICCARM__)
 
-#pragma section=".ram.bss"
+#pragma section=".bss.sram"
+#pragma section=".bss.dtcm"
+#pragma section=".bss.dram"
 
-uint8_t *__bss_start__;
-uint8_t *__bss_end__;
+uint8_t *__bss_sram_start__;
+uint8_t *__bss_sram_end__;
+uint8_t *__bss_dtcm_start__;
+uint8_t *__bss_dtcm_end__;
+uint8_t *__bss_dram_start__;
+uint8_t *__bss_dram_end__;
 
 void __iar_data_init_app(void)
 {
-    __bss_start__ = (uint8_t *)__section_begin(".ram.bss");
-    __bss_end__   = (uint8_t *)__section_end(".ram.bss");
+    __bss_sram_start__ = (uint8_t *)__section_begin(".bss.sram");
+    __bss_sram_end__   = (uint8_t *)__section_end(".bss.sram");
+    __bss_dtcm_start__ = (uint8_t *)__section_begin(".bss.dtcm");
+    __bss_dtcm_end__   = (uint8_t *)__section_end(".bss.dtcm");
+    __bss_dram_start__ = (uint8_t *)__section_begin(".bss.dram");
+    __bss_dram_end__   = (uint8_t *)__section_end(".bss.dram");
 }
 
 #else
@@ -181,12 +191,10 @@
     // Clear RAM BSS
 #if defined (__ICCARM__)
     __iar_data_init_app();
-    __rtl_memset_v1_00((void *)__bss_start__, 0, __bss_end__ - __bss_start__);
-#else
+#endif
     __rtl_memset_v1_00((void *)__bss_sram_start__, 0, __bss_sram_end__ - __bss_sram_start__);
     __rtl_memset_v1_00((void *)__bss_dtcm_start__, 0, __bss_dtcm_end__ - __bss_dtcm_start__);
     __rtl_memset_v1_00((void *)__bss_dram_start__, 0, __bss_dram_end__ - __bss_dram_start__);
-#endif
 
     extern HAL_TIMER_OP_EXT HalTimerOpExt;
     __rtl_memset_v1_00((void *)&HalTimerOpExt, 0, sizeof(HalTimerOpExt));