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mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/stm32f042x6.h@135:eec55f8ee438, 2016-05-23 (annotated)

Committer:: mbed_official
Date:: Mon May 23 10:45:11 2016 +0100
Revision:: 135:eec55f8ee438
Parent:: 5:ac9f6c2c45e8
Child:: 144:ef7eb2e8f9f7

Synchronized with git revision 275100e9694eca820b966a3fb9abc8b5f3dadff2



Full URL: https://github.com/mbedmicro/mbed/commit/275100e9694eca820b966a3fb9abc8b5f3dadff2/

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	5:ac9f6c2c45e8	1	/**
mbed_official	5:ac9f6c2c45e8	2	******************************************************************************
mbed_official	5:ac9f6c2c45e8	3	* @file stm32f042x6.h
mbed_official	5:ac9f6c2c45e8	4	* @author MCD Application Team
mbed_official	5:ac9f6c2c45e8	5	* @version V2.2.2
mbed_official	5:ac9f6c2c45e8	6	* @date 26-June-2015
mbed_official	5:ac9f6c2c45e8	7	* @brief CMSIS STM32F042x4/STM32F042x6 Devices Peripheral Access Layer Header File.
mbed_official	5:ac9f6c2c45e8	8	*
mbed_official	5:ac9f6c2c45e8	9	* This file contains:
mbed_official	5:ac9f6c2c45e8	10	* - Data structures and the address mapping for all peripherals
mbed_official	5:ac9f6c2c45e8	11	* - Peripheral's registers declarations and bits definition
mbed_official	5:ac9f6c2c45e8	12	* - Macros to access peripherals registers hardware
mbed_official	5:ac9f6c2c45e8	13	*
mbed_official	5:ac9f6c2c45e8	14	******************************************************************************
mbed_official	5:ac9f6c2c45e8	15	* @attention
mbed_official	5:ac9f6c2c45e8	16	*
mbed_official	5:ac9f6c2c45e8	17	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official	5:ac9f6c2c45e8	18	*
mbed_official	5:ac9f6c2c45e8	19	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	5:ac9f6c2c45e8	20	* are permitted provided that the following conditions are met:
mbed_official	5:ac9f6c2c45e8	21	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	5:ac9f6c2c45e8	22	* this list of conditions and the following disclaimer.
mbed_official	5:ac9f6c2c45e8	23	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	5:ac9f6c2c45e8	24	* this list of conditions and the following disclaimer in the documentation
mbed_official	5:ac9f6c2c45e8	25	* and/or other materials provided with the distribution.
mbed_official	5:ac9f6c2c45e8	26	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	5:ac9f6c2c45e8	27	* may be used to endorse or promote products derived from this software
mbed_official	5:ac9f6c2c45e8	28	* without specific prior written permission.
mbed_official	5:ac9f6c2c45e8	29	*
mbed_official	5:ac9f6c2c45e8	30	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	5:ac9f6c2c45e8	31	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	5:ac9f6c2c45e8	32	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	5:ac9f6c2c45e8	33	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	5:ac9f6c2c45e8	34	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	5:ac9f6c2c45e8	35	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	5:ac9f6c2c45e8	36	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	5:ac9f6c2c45e8	37	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	5:ac9f6c2c45e8	38	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	5:ac9f6c2c45e8	39	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	5:ac9f6c2c45e8	40	*
mbed_official	5:ac9f6c2c45e8	41	******************************************************************************
mbed_official	5:ac9f6c2c45e8	42	*/
mbed_official	5:ac9f6c2c45e8	43
mbed_official	5:ac9f6c2c45e8	44	/** @addtogroup CMSIS_Device
mbed_official	5:ac9f6c2c45e8	45	* @{
mbed_official	5:ac9f6c2c45e8	46	*/
mbed_official	5:ac9f6c2c45e8	47
mbed_official	5:ac9f6c2c45e8	48	/** @addtogroup stm32f042x6
mbed_official	5:ac9f6c2c45e8	49	* @{
mbed_official	5:ac9f6c2c45e8	50	*/
mbed_official	5:ac9f6c2c45e8	51
mbed_official	5:ac9f6c2c45e8	52	#ifndef __STM32F042x6_H
mbed_official	5:ac9f6c2c45e8	53	#define __STM32F042x6_H
mbed_official	5:ac9f6c2c45e8	54
mbed_official	5:ac9f6c2c45e8	55	#ifdef __cplusplus
mbed_official	5:ac9f6c2c45e8	56	extern "C" {
mbed_official	5:ac9f6c2c45e8	57	#endif /* __cplusplus */
mbed_official	5:ac9f6c2c45e8	58
mbed_official	5:ac9f6c2c45e8	59	/** @addtogroup Configuration_section_for_CMSIS
mbed_official	5:ac9f6c2c45e8	60	* @{
mbed_official	5:ac9f6c2c45e8	61	*/
mbed_official	5:ac9f6c2c45e8	62	/**
mbed_official	5:ac9f6c2c45e8	63	* @brief Configuration of the Cortex-M0 Processor and Core Peripherals
mbed_official	5:ac9f6c2c45e8	64	*/
mbed_official	5:ac9f6c2c45e8	65	#define __CM0_REV 0 /!< Core Revision r0p0 /
mbed_official	5:ac9f6c2c45e8	66	#define __MPU_PRESENT 0 /!< STM32F0xx do not provide MPU /
mbed_official	5:ac9f6c2c45e8	67	#define __NVIC_PRIO_BITS 2 /!< STM32F0xx uses 2 Bits for the Priority Levels /
mbed_official	5:ac9f6c2c45e8	68	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
mbed_official	5:ac9f6c2c45e8	69
mbed_official	5:ac9f6c2c45e8	70	/**
mbed_official	5:ac9f6c2c45e8	71	* @}
mbed_official	5:ac9f6c2c45e8	72	*/
mbed_official	5:ac9f6c2c45e8	73
mbed_official	5:ac9f6c2c45e8	74	/** @addtogroup Peripheral_interrupt_number_definition
mbed_official	5:ac9f6c2c45e8	75	* @{
mbed_official	5:ac9f6c2c45e8	76	*/
mbed_official	5:ac9f6c2c45e8	77
mbed_official	5:ac9f6c2c45e8	78	/**
mbed_official	5:ac9f6c2c45e8	79	* @brief STM32F042x4/STM32F042x6 device Interrupt Number Definition
mbed_official	5:ac9f6c2c45e8	80	*/
mbed_official	5:ac9f6c2c45e8	81	typedef enum
mbed_official	5:ac9f6c2c45e8	82	{
mbed_official	5:ac9f6c2c45e8	83	/**** Cortex-M0 Processor Exceptions Numbers ************************************************************/
mbed_official	5:ac9f6c2c45e8	84	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
mbed_official	5:ac9f6c2c45e8	85	HardFault_IRQn = -13, /!< 3 Cortex-M0 Hard Fault Interrupt /
mbed_official	5:ac9f6c2c45e8	86	SVC_IRQn = -5, /!< 11 Cortex-M0 SV Call Interrupt /
mbed_official	5:ac9f6c2c45e8	87	PendSV_IRQn = -2, /!< 14 Cortex-M0 Pend SV Interrupt /
mbed_official	5:ac9f6c2c45e8	88	SysTick_IRQn = -1, /!< 15 Cortex-M0 System Tick Interrupt /
mbed_official	5:ac9f6c2c45e8	89
mbed_official	5:ac9f6c2c45e8	90	/**** STM32F042x4/STM32F042x6 specific Interrupt Numbers ************************************************/
mbed_official	5:ac9f6c2c45e8	91	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
mbed_official	5:ac9f6c2c45e8	92	PVD_VDDIO2_IRQn = 1, /!< PVD & VDDIO2 Interrupts through EXTI Lines 16 and 31 /
mbed_official	5:ac9f6c2c45e8	93	RTC_IRQn = 2, /!< RTC Interrupt through EXTI Lines 17, 19 and 20 /
mbed_official	5:ac9f6c2c45e8	94	FLASH_IRQn = 3, /!< FLASH global Interrupt /
mbed_official	5:ac9f6c2c45e8	95	RCC_CRS_IRQn = 4, /!< RCC & CRS Global Interrupts /
mbed_official	5:ac9f6c2c45e8	96	EXTI0_1_IRQn = 5, /!< EXTI Line 0 and 1 Interrupts /
mbed_official	5:ac9f6c2c45e8	97	EXTI2_3_IRQn = 6, /!< EXTI Line 2 and 3 Interrupts /
mbed_official	5:ac9f6c2c45e8	98	EXTI4_15_IRQn = 7, /!< EXTI Line 4 to 15 Interrupts /
mbed_official	5:ac9f6c2c45e8	99	TSC_IRQn = 8, /!< Touch Sensing Controller Interrupts /
mbed_official	5:ac9f6c2c45e8	100	DMA1_Channel1_IRQn = 9, /!< DMA1 Channel 1 Interrupt /
mbed_official	5:ac9f6c2c45e8	101	DMA1_Channel2_3_IRQn = 10, /!< DMA1 Channel 2 and Channel 3 Interrupts /
mbed_official	5:ac9f6c2c45e8	102	DMA1_Channel4_5_IRQn = 11, /!< DMA1 Channel 4 and Channel 5 Interrupts /
mbed_official	5:ac9f6c2c45e8	103	ADC1_IRQn = 12, /!< ADC1 Interrupt /
mbed_official	5:ac9f6c2c45e8	104	TIM1_BRK_UP_TRG_COM_IRQn = 13, /!< TIM1 Break, Update, Trigger and Commutation Interrupts /
mbed_official	5:ac9f6c2c45e8	105	TIM1_CC_IRQn = 14, /!< TIM1 Capture Compare Interrupt /
mbed_official	5:ac9f6c2c45e8	106	TIM2_IRQn = 15, /!< TIM2 global Interrupt /
mbed_official	5:ac9f6c2c45e8	107	TIM3_IRQn = 16, /!< TIM3 global Interrupt /
mbed_official	5:ac9f6c2c45e8	108	TIM14_IRQn = 19, /!< TIM14 global Interrupt /
mbed_official	5:ac9f6c2c45e8	109	TIM16_IRQn = 21, /!< TIM16 global Interrupt /
mbed_official	5:ac9f6c2c45e8	110	TIM17_IRQn = 22, /!< TIM17 global Interrupt /
mbed_official	5:ac9f6c2c45e8	111	I2C1_IRQn = 23, /!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) /
mbed_official	5:ac9f6c2c45e8	112	SPI1_IRQn = 25, /!< SPI1 global Interrupt /
mbed_official	5:ac9f6c2c45e8	113	SPI2_IRQn = 26, /!< SPI2 global Interrupt /
mbed_official	5:ac9f6c2c45e8	114	USART1_IRQn = 27, /!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) /
mbed_official	5:ac9f6c2c45e8	115	USART2_IRQn = 28, /!< USART2 global Interrupt /
mbed_official	5:ac9f6c2c45e8	116	CEC_CAN_IRQn = 30, /!< CEC and CAN global Interrupts & EXTI Line27 Interrupt /
mbed_official	5:ac9f6c2c45e8	117	USB_IRQn = 31 /!< USB global Interrupts & EXTI Line18 Interrupt /
mbed_official	5:ac9f6c2c45e8	118	} IRQn_Type;
mbed_official	5:ac9f6c2c45e8	119
mbed_official	5:ac9f6c2c45e8	120	/**
mbed_official	5:ac9f6c2c45e8	121	* @}
mbed_official	5:ac9f6c2c45e8	122	*/
mbed_official	5:ac9f6c2c45e8	123
mbed_official	5:ac9f6c2c45e8	124	#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
mbed_official	5:ac9f6c2c45e8	125	#include "system_stm32f0xx.h" /* STM32F0xx System Header */
mbed_official	5:ac9f6c2c45e8	126	#include <stdint.h>
mbed_official	5:ac9f6c2c45e8	127
mbed_official	5:ac9f6c2c45e8	128	/** @addtogroup Peripheral_registers_structures
mbed_official	5:ac9f6c2c45e8	129	* @{
mbed_official	5:ac9f6c2c45e8	130	*/
mbed_official	5:ac9f6c2c45e8	131
mbed_official	5:ac9f6c2c45e8	132	/**
mbed_official	5:ac9f6c2c45e8	133	* @brief Analog to Digital Converter
mbed_official	5:ac9f6c2c45e8	134	*/
mbed_official	5:ac9f6c2c45e8	135
mbed_official	5:ac9f6c2c45e8	136	typedef struct
mbed_official	5:ac9f6c2c45e8	137	{
mbed_official	5:ac9f6c2c45e8	138	__IO uint32_t ISR; /!< ADC Interrupt and Status register, Address offset:0x00 /
mbed_official	5:ac9f6c2c45e8	139	__IO uint32_t IER; /!< ADC Interrupt Enable register, Address offset:0x04 /
mbed_official	5:ac9f6c2c45e8	140	__IO uint32_t CR; /!< ADC Control register, Address offset:0x08 /
mbed_official	5:ac9f6c2c45e8	141	__IO uint32_t CFGR1; /!< ADC Configuration register 1, Address offset:0x0C /
mbed_official	5:ac9f6c2c45e8	142	__IO uint32_t CFGR2; /!< ADC Configuration register 2, Address offset:0x10 /
mbed_official	5:ac9f6c2c45e8	143	__IO uint32_t SMPR; /!< ADC Sampling time register, Address offset:0x14 /
mbed_official	5:ac9f6c2c45e8	144	uint32_t RESERVED1; /!< Reserved, 0x18 /
mbed_official	5:ac9f6c2c45e8	145	uint32_t RESERVED2; /!< Reserved, 0x1C /
mbed_official	5:ac9f6c2c45e8	146	__IO uint32_t TR; /!< ADC watchdog threshold register, Address offset:0x20 /
mbed_official	5:ac9f6c2c45e8	147	uint32_t RESERVED3; /!< Reserved, 0x24 /
mbed_official	5:ac9f6c2c45e8	148	__IO uint32_t CHSELR; /!< ADC channel selection register, Address offset:0x28 /
mbed_official	5:ac9f6c2c45e8	149	uint32_t RESERVED4[5]; /!< Reserved, 0x2C /
mbed_official	5:ac9f6c2c45e8	150	__IO uint32_t DR; /!< ADC data register, Address offset:0x40 /
mbed_official	5:ac9f6c2c45e8	151	}ADC_TypeDef;
mbed_official	5:ac9f6c2c45e8	152
mbed_official	5:ac9f6c2c45e8	153	typedef struct
mbed_official	5:ac9f6c2c45e8	154	{
mbed_official	5:ac9f6c2c45e8	155	__IO uint32_t CCR;
mbed_official	5:ac9f6c2c45e8	156	}ADC_Common_TypeDef;
mbed_official	5:ac9f6c2c45e8	157
mbed_official	5:ac9f6c2c45e8	158	/**
mbed_official	5:ac9f6c2c45e8	159	* @brief Controller Area Network TxMailBox
mbed_official	5:ac9f6c2c45e8	160	*/
mbed_official	5:ac9f6c2c45e8	161	typedef struct
mbed_official	5:ac9f6c2c45e8	162	{
mbed_official	5:ac9f6c2c45e8	163	__IO uint32_t TIR; /!< CAN TX mailbox identifier register /
mbed_official	5:ac9f6c2c45e8	164	__IO uint32_t TDTR; /!< CAN mailbox data length control and time stamp register /
mbed_official	5:ac9f6c2c45e8	165	__IO uint32_t TDLR; /!< CAN mailbox data low register /
mbed_official	5:ac9f6c2c45e8	166	__IO uint32_t TDHR; /!< CAN mailbox data high register /
mbed_official	5:ac9f6c2c45e8	167	}CAN_TxMailBox_TypeDef;
mbed_official	5:ac9f6c2c45e8	168
mbed_official	5:ac9f6c2c45e8	169	/**
mbed_official	5:ac9f6c2c45e8	170	* @brief Controller Area Network FIFOMailBox
mbed_official	5:ac9f6c2c45e8	171	*/
mbed_official	5:ac9f6c2c45e8	172	typedef struct
mbed_official	5:ac9f6c2c45e8	173	{
mbed_official	5:ac9f6c2c45e8	174	__IO uint32_t RIR; /!< CAN receive FIFO mailbox identifier register /
mbed_official	5:ac9f6c2c45e8	175	__IO uint32_t RDTR; /!< CAN receive FIFO mailbox data length control and time stamp register /
mbed_official	5:ac9f6c2c45e8	176	__IO uint32_t RDLR; /!< CAN receive FIFO mailbox data low register /
mbed_official	5:ac9f6c2c45e8	177	__IO uint32_t RDHR; /!< CAN receive FIFO mailbox data high register /
mbed_official	5:ac9f6c2c45e8	178	}CAN_FIFOMailBox_TypeDef;
mbed_official	5:ac9f6c2c45e8	179
mbed_official	5:ac9f6c2c45e8	180	/**
mbed_official	5:ac9f6c2c45e8	181	* @brief Controller Area Network FilterRegister
mbed_official	5:ac9f6c2c45e8	182	*/
mbed_official	5:ac9f6c2c45e8	183	typedef struct
mbed_official	5:ac9f6c2c45e8	184	{
mbed_official	5:ac9f6c2c45e8	185	__IO uint32_t FR1; /!< CAN Filter bank register 1 /
mbed_official	5:ac9f6c2c45e8	186	__IO uint32_t FR2; /!< CAN Filter bank register 1 /
mbed_official	5:ac9f6c2c45e8	187	}CAN_FilterRegister_TypeDef;
mbed_official	5:ac9f6c2c45e8	188
mbed_official	5:ac9f6c2c45e8	189	/**
mbed_official	5:ac9f6c2c45e8	190	* @brief Controller Area Network
mbed_official	5:ac9f6c2c45e8	191	*/
mbed_official	5:ac9f6c2c45e8	192	typedef struct
mbed_official	5:ac9f6c2c45e8	193	{
mbed_official	5:ac9f6c2c45e8	194	__IO uint32_t MCR; /!< CAN master control register, Address offset: 0x00 /
mbed_official	5:ac9f6c2c45e8	195	__IO uint32_t MSR; /!< CAN master status register, Address offset: 0x04 /
mbed_official	5:ac9f6c2c45e8	196	__IO uint32_t TSR; /!< CAN transmit status register, Address offset: 0x08 /
mbed_official	5:ac9f6c2c45e8	197	__IO uint32_t RF0R; /!< CAN receive FIFO 0 register, Address offset: 0x0C /
mbed_official	5:ac9f6c2c45e8	198	__IO uint32_t RF1R; /!< CAN receive FIFO 1 register, Address offset: 0x10 /
mbed_official	5:ac9f6c2c45e8	199	__IO uint32_t IER; /!< CAN interrupt enable register, Address offset: 0x14 /
mbed_official	5:ac9f6c2c45e8	200	__IO uint32_t ESR; /!< CAN error status register, Address offset: 0x18 /
mbed_official	5:ac9f6c2c45e8	201	__IO uint32_t BTR; /!< CAN bit timing register, Address offset: 0x1C /
mbed_official	5:ac9f6c2c45e8	202	uint32_t RESERVED0[88]; /!< Reserved, 0x020 - 0x17F /
mbed_official	5:ac9f6c2c45e8	203	CAN_TxMailBox_TypeDef sTxMailBox[3]; /!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC /
mbed_official	5:ac9f6c2c45e8	204	CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC /
mbed_official	5:ac9f6c2c45e8	205	uint32_t RESERVED1[12]; /!< Reserved, 0x1D0 - 0x1FF /
mbed_official	5:ac9f6c2c45e8	206	__IO uint32_t FMR; /!< CAN filter master register, Address offset: 0x200 /
mbed_official	5:ac9f6c2c45e8	207	__IO uint32_t FM1R; /!< CAN filter mode register, Address offset: 0x204 /
mbed_official	5:ac9f6c2c45e8	208	uint32_t RESERVED2; /!< Reserved, 0x208 /
mbed_official	5:ac9f6c2c45e8	209	__IO uint32_t FS1R; /!< CAN filter scale register, Address offset: 0x20C /
mbed_official	5:ac9f6c2c45e8	210	uint32_t RESERVED3; /!< Reserved, 0x210 /
mbed_official	5:ac9f6c2c45e8	211	__IO uint32_t FFA1R; /!< CAN filter FIFO assignment register, Address offset: 0x214 /
mbed_official	5:ac9f6c2c45e8	212	uint32_t RESERVED4; /!< Reserved, 0x218 /
mbed_official	5:ac9f6c2c45e8	213	__IO uint32_t FA1R; /!< CAN filter activation register, Address offset: 0x21C /
mbed_official	5:ac9f6c2c45e8	214	uint32_t RESERVED5[8]; /!< Reserved, 0x220-0x23F /
mbed_official	5:ac9f6c2c45e8	215	CAN_FilterRegister_TypeDef sFilterRegister[28]; /!< CAN Filter Register, Address offset: 0x240-0x31C /
mbed_official	5:ac9f6c2c45e8	216	}CAN_TypeDef;
mbed_official	5:ac9f6c2c45e8	217
mbed_official	5:ac9f6c2c45e8	218	/**
mbed_official	5:ac9f6c2c45e8	219	* @brief HDMI-CEC
mbed_official	5:ac9f6c2c45e8	220	*/
mbed_official	5:ac9f6c2c45e8	221
mbed_official	5:ac9f6c2c45e8	222	typedef struct
mbed_official	5:ac9f6c2c45e8	223	{
mbed_official	5:ac9f6c2c45e8	224	__IO uint32_t CR; /!< CEC control register, Address offset:0x00 /
mbed_official	5:ac9f6c2c45e8	225	__IO uint32_t CFGR; /!< CEC configuration register, Address offset:0x04 /
mbed_official	5:ac9f6c2c45e8	226	__IO uint32_t TXDR; /!< CEC Tx data register , Address offset:0x08 /
mbed_official	5:ac9f6c2c45e8	227	__IO uint32_t RXDR; /!< CEC Rx Data Register, Address offset:0x0C /
mbed_official	5:ac9f6c2c45e8	228	__IO uint32_t ISR; /!< CEC Interrupt and Status Register, Address offset:0x10 /
mbed_official	5:ac9f6c2c45e8	229	__IO uint32_t IER; /!< CEC interrupt enable register, Address offset:0x14 /
mbed_official	5:ac9f6c2c45e8	230	}CEC_TypeDef;
mbed_official	5:ac9f6c2c45e8	231
mbed_official	5:ac9f6c2c45e8	232	/**
mbed_official	5:ac9f6c2c45e8	233	* @brief CRC calculation unit
mbed_official	5:ac9f6c2c45e8	234	*/
mbed_official	5:ac9f6c2c45e8	235
mbed_official	5:ac9f6c2c45e8	236	typedef struct
mbed_official	5:ac9f6c2c45e8	237	{
mbed_official	5:ac9f6c2c45e8	238	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
mbed_official	5:ac9f6c2c45e8	239	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
mbed_official	5:ac9f6c2c45e8	240	uint8_t RESERVED0; /!< Reserved, 0x05 /
mbed_official	5:ac9f6c2c45e8	241	uint16_t RESERVED1; /!< Reserved, 0x06 /
mbed_official	5:ac9f6c2c45e8	242	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
mbed_official	5:ac9f6c2c45e8	243	uint32_t RESERVED2; /!< Reserved, 0x0C /
mbed_official	5:ac9f6c2c45e8	244	__IO uint32_t INIT; /!< Initial CRC value register, Address offset: 0x10 /
mbed_official	5:ac9f6c2c45e8	245	__IO uint32_t POL; /!< CRC polynomial register, Address offset: 0x14 /
mbed_official	5:ac9f6c2c45e8	246	}CRC_TypeDef;
mbed_official	5:ac9f6c2c45e8	247
mbed_official	5:ac9f6c2c45e8	248	/**
mbed_official	5:ac9f6c2c45e8	249	* @brief Clock Recovery System
mbed_official	5:ac9f6c2c45e8	250	*/
mbed_official	5:ac9f6c2c45e8	251	typedef struct
mbed_official	5:ac9f6c2c45e8	252	{
mbed_official	5:ac9f6c2c45e8	253	__IO uint32_t CR; /!< CRS ccontrol register, Address offset: 0x00 /
mbed_official	5:ac9f6c2c45e8	254	__IO uint32_t CFGR; /!< CRS configuration register, Address offset: 0x04 /
mbed_official	5:ac9f6c2c45e8	255	__IO uint32_t ISR; /!< CRS interrupt and status register, Address offset: 0x08 /
mbed_official	5:ac9f6c2c45e8	256	__IO uint32_t ICR; /!< CRS interrupt flag clear register, Address offset: 0x0C /
mbed_official	5:ac9f6c2c45e8	257	}CRS_TypeDef;
mbed_official	5:ac9f6c2c45e8	258
mbed_official	5:ac9f6c2c45e8	259	/**
mbed_official	5:ac9f6c2c45e8	260	* @brief Debug MCU
mbed_official	5:ac9f6c2c45e8	261	*/
mbed_official	5:ac9f6c2c45e8	262
mbed_official	5:ac9f6c2c45e8	263	typedef struct
mbed_official	5:ac9f6c2c45e8	264	{
mbed_official	5:ac9f6c2c45e8	265	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
mbed_official	5:ac9f6c2c45e8	266	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
mbed_official	5:ac9f6c2c45e8	267	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
mbed_official	5:ac9f6c2c45e8	268	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
mbed_official	5:ac9f6c2c45e8	269	}DBGMCU_TypeDef;
mbed_official	5:ac9f6c2c45e8	270
mbed_official	5:ac9f6c2c45e8	271	/**
mbed_official	5:ac9f6c2c45e8	272	* @brief DMA Controller
mbed_official	5:ac9f6c2c45e8	273	*/
mbed_official	5:ac9f6c2c45e8	274
mbed_official	5:ac9f6c2c45e8	275	typedef struct
mbed_official	5:ac9f6c2c45e8	276	{
mbed_official	5:ac9f6c2c45e8	277	__IO uint32_t CCR; /!< DMA channel x configuration register /
mbed_official	5:ac9f6c2c45e8	278	__IO uint32_t CNDTR; /!< DMA channel x number of data register /
mbed_official	5:ac9f6c2c45e8	279	__IO uint32_t CPAR; /!< DMA channel x peripheral address register /
mbed_official	5:ac9f6c2c45e8	280	__IO uint32_t CMAR; /!< DMA channel x memory address register /
mbed_official	5:ac9f6c2c45e8	281	}DMA_Channel_TypeDef;
mbed_official	5:ac9f6c2c45e8	282
mbed_official	5:ac9f6c2c45e8	283	typedef struct
mbed_official	5:ac9f6c2c45e8	284	{
mbed_official	5:ac9f6c2c45e8	285	__IO uint32_t ISR; /!< DMA interrupt status register, Address offset: 0x00 /
mbed_official	5:ac9f6c2c45e8	286	__IO uint32_t IFCR; /!< DMA interrupt flag clear register, Address offset: 0x04 /
mbed_official	5:ac9f6c2c45e8	287	}DMA_TypeDef;
mbed_official	5:ac9f6c2c45e8	288
mbed_official	5:ac9f6c2c45e8	289	/**
mbed_official	5:ac9f6c2c45e8	290	* @brief External Interrupt/Event Controller
mbed_official	5:ac9f6c2c45e8	291	*/
mbed_official	5:ac9f6c2c45e8	292
mbed_official	5:ac9f6c2c45e8	293	typedef struct
mbed_official	5:ac9f6c2c45e8	294	{
mbed_official	5:ac9f6c2c45e8	295	__IO uint32_t IMR; /!<EXTI Interrupt mask register, Address offset: 0x00 /
mbed_official	5:ac9f6c2c45e8	296	__IO uint32_t EMR; /!<EXTI Event mask register, Address offset: 0x04 /
mbed_official	5:ac9f6c2c45e8	297	__IO uint32_t RTSR; /!<EXTI Rising trigger selection register , Address offset: 0x08 /
mbed_official	5:ac9f6c2c45e8	298	__IO uint32_t FTSR; /!<EXTI Falling trigger selection register, Address offset: 0x0C /
mbed_official	5:ac9f6c2c45e8	299	__IO uint32_t SWIER; /!<EXTI Software interrupt event register, Address offset: 0x10 /
mbed_official	5:ac9f6c2c45e8	300	__IO uint32_t PR; /!<EXTI Pending register, Address offset: 0x14 /
mbed_official	5:ac9f6c2c45e8	301	}EXTI_TypeDef;
mbed_official	5:ac9f6c2c45e8	302
mbed_official	5:ac9f6c2c45e8	303	/**
mbed_official	5:ac9f6c2c45e8	304	* @brief FLASH Registers
mbed_official	5:ac9f6c2c45e8	305	*/
mbed_official	5:ac9f6c2c45e8	306	typedef struct
mbed_official	5:ac9f6c2c45e8	307	{
mbed_official	5:ac9f6c2c45e8	308	__IO uint32_t ACR; /!<FLASH access control register, Address offset: 0x00 /
mbed_official	5:ac9f6c2c45e8	309	__IO uint32_t KEYR; /!<FLASH key register, Address offset: 0x04 /
mbed_official	5:ac9f6c2c45e8	310	__IO uint32_t OPTKEYR; /!<FLASH OPT key register, Address offset: 0x08 /
mbed_official	5:ac9f6c2c45e8	311	__IO uint32_t SR; /!<FLASH status register, Address offset: 0x0C /
mbed_official	5:ac9f6c2c45e8	312	__IO uint32_t CR; /!<FLASH control register, Address offset: 0x10 /
mbed_official	5:ac9f6c2c45e8	313	__IO uint32_t AR; /!<FLASH address register, Address offset: 0x14 /
mbed_official	5:ac9f6c2c45e8	314	__IO uint32_t RESERVED; /!< Reserved, 0x18 /
mbed_official	5:ac9f6c2c45e8	315	__IO uint32_t OBR; /!<FLASH option bytes register, Address offset: 0x1C /
mbed_official	5:ac9f6c2c45e8	316	__IO uint32_t WRPR; /!<FLASH option bytes register, Address offset: 0x20 /
mbed_official	5:ac9f6c2c45e8	317	}FLASH_TypeDef;
mbed_official	5:ac9f6c2c45e8	318
mbed_official	5:ac9f6c2c45e8	319
mbed_official	5:ac9f6c2c45e8	320	/**
mbed_official	5:ac9f6c2c45e8	321	* @brief Option Bytes Registers
mbed_official	5:ac9f6c2c45e8	322	*/
mbed_official	5:ac9f6c2c45e8	323	typedef struct
mbed_official	5:ac9f6c2c45e8	324	{
mbed_official	5:ac9f6c2c45e8	325	__IO uint16_t RDP; /!< FLASH option byte Read protection, Address offset: 0x00 /
mbed_official	5:ac9f6c2c45e8	326	__IO uint16_t USER; /!< FLASH option byte user options, Address offset: 0x02 /
mbed_official	5:ac9f6c2c45e8	327	__IO uint16_t DATA0; /!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 /
mbed_official	5:ac9f6c2c45e8	328	__IO uint16_t DATA1; /!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 /
mbed_official	5:ac9f6c2c45e8	329	__IO uint16_t WRP0; /!< FLASH option byte write protection 0, Address offset: 0x08 /
mbed_official	5:ac9f6c2c45e8	330	__IO uint16_t WRP1; /!< FLASH option byte write protection 1, Address offset: 0x0A /
mbed_official	5:ac9f6c2c45e8	331	}OB_TypeDef;
mbed_official	5:ac9f6c2c45e8	332
mbed_official	5:ac9f6c2c45e8	333	/**
mbed_official	5:ac9f6c2c45e8	334	* @brief General Purpose I/O
mbed_official	5:ac9f6c2c45e8	335	*/
mbed_official	5:ac9f6c2c45e8	336
mbed_official	5:ac9f6c2c45e8	337	typedef struct
mbed_official	5:ac9f6c2c45e8	338	{
mbed_official	5:ac9f6c2c45e8	339	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
mbed_official	5:ac9f6c2c45e8	340	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
mbed_official	5:ac9f6c2c45e8	341	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
mbed_official	5:ac9f6c2c45e8	342	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
mbed_official	5:ac9f6c2c45e8	343	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
mbed_official	5:ac9f6c2c45e8	344	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
mbed_official	5:ac9f6c2c45e8	345	__IO uint32_t BSRR; /!< GPIO port bit set/reset register, Address offset: 0x1A /
mbed_official	5:ac9f6c2c45e8	346	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
mbed_official	5:ac9f6c2c45e8	347	__IO uint32_t AFR[2]; /!< GPIO alternate function low register, Address offset: 0x20-0x24 /
mbed_official	5:ac9f6c2c45e8	348	__IO uint32_t BRR; /!< GPIO bit reset register, Address offset: 0x28 /
mbed_official	5:ac9f6c2c45e8	349	}GPIO_TypeDef;
mbed_official	5:ac9f6c2c45e8	350
mbed_official	5:ac9f6c2c45e8	351	/**
mbed_official	5:ac9f6c2c45e8	352	* @brief SysTem Configuration
mbed_official	5:ac9f6c2c45e8	353	*/
mbed_official	5:ac9f6c2c45e8	354
mbed_official	5:ac9f6c2c45e8	355	typedef struct
mbed_official	5:ac9f6c2c45e8	356	{
mbed_official	5:ac9f6c2c45e8	357	__IO uint32_t CFGR1; /!< SYSCFG configuration register 1, Address offset: 0x00 /
mbed_official	5:ac9f6c2c45e8	358	uint32_t RESERVED; /!< Reserved, 0x04 /
mbed_official	5:ac9f6c2c45e8	359	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 /
mbed_official	5:ac9f6c2c45e8	360	__IO uint32_t CFGR2; /!< SYSCFG configuration register 2, Address offset: 0x18 /
mbed_official	5:ac9f6c2c45e8	361	}SYSCFG_TypeDef;
mbed_official	5:ac9f6c2c45e8	362
mbed_official	5:ac9f6c2c45e8	363	/**
mbed_official	5:ac9f6c2c45e8	364	* @brief Inter-integrated Circuit Interface
mbed_official	5:ac9f6c2c45e8	365	*/
mbed_official	5:ac9f6c2c45e8	366
mbed_official	5:ac9f6c2c45e8	367	typedef struct
mbed_official	5:ac9f6c2c45e8	368	{
mbed_official	5:ac9f6c2c45e8	369	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
mbed_official	5:ac9f6c2c45e8	370	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
mbed_official	5:ac9f6c2c45e8	371	__IO uint32_t OAR1; /!< I2C Own address 1 register, Address offset: 0x08 /
mbed_official	5:ac9f6c2c45e8	372	__IO uint32_t OAR2; /!< I2C Own address 2 register, Address offset: 0x0C /
mbed_official	5:ac9f6c2c45e8	373	__IO uint32_t TIMINGR; /!< I2C Timing register, Address offset: 0x10 /
mbed_official	5:ac9f6c2c45e8	374	__IO uint32_t TIMEOUTR; /!< I2C Timeout register, Address offset: 0x14 /
mbed_official	5:ac9f6c2c45e8	375	__IO uint32_t ISR; /!< I2C Interrupt and status register, Address offset: 0x18 /
mbed_official	5:ac9f6c2c45e8	376	__IO uint32_t ICR; /!< I2C Interrupt clear register, Address offset: 0x1C /
mbed_official	5:ac9f6c2c45e8	377	__IO uint32_t PECR; /!< I2C PEC register, Address offset: 0x20 /
mbed_official	5:ac9f6c2c45e8	378	__IO uint32_t RXDR; /!< I2C Receive data register, Address offset: 0x24 /
mbed_official	5:ac9f6c2c45e8	379	__IO uint32_t TXDR; /!< I2C Transmit data register, Address offset: 0x28 /
mbed_official	5:ac9f6c2c45e8	380	}I2C_TypeDef;
mbed_official	5:ac9f6c2c45e8	381
mbed_official	5:ac9f6c2c45e8	382	/**
mbed_official	5:ac9f6c2c45e8	383	* @brief Independent WATCHDOG
mbed_official	5:ac9f6c2c45e8	384	*/
mbed_official	5:ac9f6c2c45e8	385
mbed_official	5:ac9f6c2c45e8	386	typedef struct
mbed_official	5:ac9f6c2c45e8	387	{
mbed_official	5:ac9f6c2c45e8	388	__IO uint32_t KR; /!< IWDG Key register, Address offset: 0x00 /
mbed_official	5:ac9f6c2c45e8	389	__IO uint32_t PR; /!< IWDG Prescaler register, Address offset: 0x04 /
mbed_official	5:ac9f6c2c45e8	390	__IO uint32_t RLR; /!< IWDG Reload register, Address offset: 0x08 /
mbed_official	5:ac9f6c2c45e8	391	__IO uint32_t SR; /!< IWDG Status register, Address offset: 0x0C /
mbed_official	5:ac9f6c2c45e8	392	__IO uint32_t WINR; /!< IWDG Window register, Address offset: 0x10 /
mbed_official	5:ac9f6c2c45e8	393	}IWDG_TypeDef;
mbed_official	5:ac9f6c2c45e8	394
mbed_official	5:ac9f6c2c45e8	395	/**
mbed_official	5:ac9f6c2c45e8	396	* @brief Power Control
mbed_official	5:ac9f6c2c45e8	397	*/
mbed_official	5:ac9f6c2c45e8	398
mbed_official	5:ac9f6c2c45e8	399	typedef struct
mbed_official	5:ac9f6c2c45e8	400	{
mbed_official	5:ac9f6c2c45e8	401	__IO uint32_t CR; /!< PWR power control register, Address offset: 0x00 /
mbed_official	5:ac9f6c2c45e8	402	__IO uint32_t CSR; /!< PWR power control/status register, Address offset: 0x04 /
mbed_official	5:ac9f6c2c45e8	403	}PWR_TypeDef;
mbed_official	5:ac9f6c2c45e8	404
mbed_official	5:ac9f6c2c45e8	405	/**
mbed_official	5:ac9f6c2c45e8	406	* @brief Reset and Clock Control
mbed_official	5:ac9f6c2c45e8	407	*/
mbed_official	5:ac9f6c2c45e8	408
mbed_official	5:ac9f6c2c45e8	409	typedef struct
mbed_official	5:ac9f6c2c45e8	410	{
mbed_official	5:ac9f6c2c45e8	411	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
mbed_official	5:ac9f6c2c45e8	412	__IO uint32_t CFGR; /!< RCC clock configuration register, Address offset: 0x04 /
mbed_official	5:ac9f6c2c45e8	413	__IO uint32_t CIR; /!< RCC clock interrupt register, Address offset: 0x08 /
mbed_official	5:ac9f6c2c45e8	414	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x0C /
mbed_official	5:ac9f6c2c45e8	415	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x10 /
mbed_official	5:ac9f6c2c45e8	416	__IO uint32_t AHBENR; /!< RCC AHB peripheral clock register, Address offset: 0x14 /
mbed_official	5:ac9f6c2c45e8	417	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x18 /
mbed_official	5:ac9f6c2c45e8	418	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x1C /
mbed_official	5:ac9f6c2c45e8	419	__IO uint32_t BDCR; /!< RCC Backup domain control register, Address offset: 0x20 /
mbed_official	5:ac9f6c2c45e8	420	__IO uint32_t CSR; /!< RCC clock control & status register, Address offset: 0x24 /
mbed_official	5:ac9f6c2c45e8	421	__IO uint32_t AHBRSTR; /!< RCC AHB peripheral reset register, Address offset: 0x28 /
mbed_official	5:ac9f6c2c45e8	422	__IO uint32_t CFGR2; /!< RCC clock configuration register 2, Address offset: 0x2C /
mbed_official	5:ac9f6c2c45e8	423	__IO uint32_t CFGR3; /!< RCC clock configuration register 3, Address offset: 0x30 /
mbed_official	5:ac9f6c2c45e8	424	__IO uint32_t CR2; /!< RCC clock control register 2, Address offset: 0x34 /
mbed_official	5:ac9f6c2c45e8	425	}RCC_TypeDef;
mbed_official	5:ac9f6c2c45e8	426
mbed_official	5:ac9f6c2c45e8	427	/**
mbed_official	5:ac9f6c2c45e8	428	* @brief Real-Time Clock
mbed_official	5:ac9f6c2c45e8	429	*/
mbed_official	5:ac9f6c2c45e8	430	typedef struct
mbed_official	5:ac9f6c2c45e8	431	{
mbed_official	5:ac9f6c2c45e8	432	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
mbed_official	5:ac9f6c2c45e8	433	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
mbed_official	5:ac9f6c2c45e8	434	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
mbed_official	5:ac9f6c2c45e8	435	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
mbed_official	5:ac9f6c2c45e8	436	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
mbed_official	5:ac9f6c2c45e8	437	uint32_t RESERVED1; /!< Reserved, Address offset: 0x14 /
mbed_official	5:ac9f6c2c45e8	438	uint32_t RESERVED2; /!< Reserved, Address offset: 0x18 /
mbed_official	5:ac9f6c2c45e8	439	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
mbed_official	5:ac9f6c2c45e8	440	uint32_t RESERVED3; /!< Reserved, Address offset: 0x20 /
mbed_official	5:ac9f6c2c45e8	441	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
mbed_official	5:ac9f6c2c45e8	442	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
mbed_official	5:ac9f6c2c45e8	443	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
mbed_official	5:ac9f6c2c45e8	444	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
mbed_official	5:ac9f6c2c45e8	445	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
mbed_official	5:ac9f6c2c45e8	446	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
mbed_official	5:ac9f6c2c45e8	447	__IO uint32_t CALR; /!< RTC calibration register, Address offset: 0x3C /
mbed_official	5:ac9f6c2c45e8	448	__IO uint32_t TAFCR; /!< RTC tamper and alternate function configuration register, Address offset: 0x40 /
mbed_official	5:ac9f6c2c45e8	449	__IO uint32_t ALRMASSR; /!< RTC alarm A sub second register, Address offset: 0x44 /
mbed_official	5:ac9f6c2c45e8	450	uint32_t RESERVED4; /!< Reserved, Address offset: 0x48 /
mbed_official	5:ac9f6c2c45e8	451	uint32_t RESERVED5; /!< Reserved, Address offset: 0x4C /
mbed_official	5:ac9f6c2c45e8	452	__IO uint32_t BKP0R; /!< RTC backup register 0, Address offset: 0x50 /
mbed_official	5:ac9f6c2c45e8	453	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
mbed_official	5:ac9f6c2c45e8	454	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
mbed_official	5:ac9f6c2c45e8	455	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
mbed_official	5:ac9f6c2c45e8	456	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
mbed_official	5:ac9f6c2c45e8	457	}RTC_TypeDef;
mbed_official	5:ac9f6c2c45e8	458
mbed_official	5:ac9f6c2c45e8	459	/**
mbed_official	5:ac9f6c2c45e8	460	* @brief Serial Peripheral Interface
mbed_official	5:ac9f6c2c45e8	461	*/
mbed_official	5:ac9f6c2c45e8	462
mbed_official	5:ac9f6c2c45e8	463	typedef struct
mbed_official	5:ac9f6c2c45e8	464	{
mbed_official	5:ac9f6c2c45e8	465	__IO uint32_t CR1; /!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 /
mbed_official	5:ac9f6c2c45e8	466	__IO uint32_t CR2; /!< SPI Control register 2, Address offset: 0x04 /
mbed_official	5:ac9f6c2c45e8	467	__IO uint32_t SR; /!< SPI Status register, Address offset: 0x08 /
mbed_official	5:ac9f6c2c45e8	468	__IO uint32_t DR; /!< SPI data register, Address offset: 0x0C /
mbed_official	5:ac9f6c2c45e8	469	__IO uint32_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
mbed_official	5:ac9f6c2c45e8	470	__IO uint32_t RXCRCR; /!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 /
mbed_official	5:ac9f6c2c45e8	471	__IO uint32_t TXCRCR; /!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 /
mbed_official	5:ac9f6c2c45e8	472	__IO uint32_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
mbed_official	5:ac9f6c2c45e8	473	__IO uint32_t I2SPR; /!< SPI_I2S prescaler register, Address offset: 0x20 /
mbed_official	5:ac9f6c2c45e8	474	}SPI_TypeDef;
mbed_official	5:ac9f6c2c45e8	475
mbed_official	5:ac9f6c2c45e8	476	/**
mbed_official	5:ac9f6c2c45e8	477	* @brief TIM
mbed_official	5:ac9f6c2c45e8	478	*/
mbed_official	5:ac9f6c2c45e8	479	typedef struct
mbed_official	5:ac9f6c2c45e8	480	{
mbed_official	5:ac9f6c2c45e8	481	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
mbed_official	5:ac9f6c2c45e8	482	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
mbed_official	5:ac9f6c2c45e8	483	__IO uint32_t SMCR; /!< TIM slave Mode Control register, Address offset: 0x08 /
mbed_official	5:ac9f6c2c45e8	484	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
mbed_official	5:ac9f6c2c45e8	485	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
mbed_official	5:ac9f6c2c45e8	486	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
mbed_official	5:ac9f6c2c45e8	487	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
mbed_official	5:ac9f6c2c45e8	488	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
mbed_official	5:ac9f6c2c45e8	489	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
mbed_official	5:ac9f6c2c45e8	490	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
mbed_official	5:ac9f6c2c45e8	491	__IO uint32_t PSC; /!< TIM prescaler register, Address offset: 0x28 /
mbed_official	5:ac9f6c2c45e8	492	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
mbed_official	5:ac9f6c2c45e8	493	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
mbed_official	5:ac9f6c2c45e8	494	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
mbed_official	5:ac9f6c2c45e8	495	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
mbed_official	5:ac9f6c2c45e8	496	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
mbed_official	5:ac9f6c2c45e8	497	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
mbed_official	5:ac9f6c2c45e8	498	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
mbed_official	5:ac9f6c2c45e8	499	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
mbed_official	5:ac9f6c2c45e8	500	__IO uint32_t DMAR; /!< TIM DMA address for full transfer register, Address offset: 0x4C /
mbed_official	5:ac9f6c2c45e8	501	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
mbed_official	5:ac9f6c2c45e8	502	}TIM_TypeDef;
mbed_official	5:ac9f6c2c45e8	503
mbed_official	5:ac9f6c2c45e8	504	/**
mbed_official	5:ac9f6c2c45e8	505	* @brief Touch Sensing Controller (TSC)
mbed_official	5:ac9f6c2c45e8	506	*/
mbed_official	5:ac9f6c2c45e8	507	typedef struct
mbed_official	5:ac9f6c2c45e8	508	{
mbed_official	5:ac9f6c2c45e8	509	__IO uint32_t CR; /!< TSC control register, Address offset: 0x00 /
mbed_official	5:ac9f6c2c45e8	510	__IO uint32_t IER; /!< TSC interrupt enable register, Address offset: 0x04 /
mbed_official	5:ac9f6c2c45e8	511	__IO uint32_t ICR; /!< TSC interrupt clear register, Address offset: 0x08 /
mbed_official	5:ac9f6c2c45e8	512	__IO uint32_t ISR; /!< TSC interrupt status register, Address offset: 0x0C /
mbed_official	5:ac9f6c2c45e8	513	__IO uint32_t IOHCR; /!< TSC I/O hysteresis control register, Address offset: 0x10 /
mbed_official	5:ac9f6c2c45e8	514	uint32_t RESERVED1; /!< Reserved, Address offset: 0x14 /
mbed_official	5:ac9f6c2c45e8	515	__IO uint32_t IOASCR; /!< TSC I/O analog switch control register, Address offset: 0x18 /
mbed_official	5:ac9f6c2c45e8	516	uint32_t RESERVED2; /!< Reserved, Address offset: 0x1C /
mbed_official	5:ac9f6c2c45e8	517	__IO uint32_t IOSCR; /!< TSC I/O sampling control register, Address offset: 0x20 /
mbed_official	5:ac9f6c2c45e8	518	uint32_t RESERVED3; /!< Reserved, Address offset: 0x24 /
mbed_official	5:ac9f6c2c45e8	519	__IO uint32_t IOCCR; /!< TSC I/O channel control register, Address offset: 0x28 /
mbed_official	5:ac9f6c2c45e8	520	uint32_t RESERVED4; /!< Reserved, Address offset: 0x2C /
mbed_official	5:ac9f6c2c45e8	521	__IO uint32_t IOGCSR; /!< TSC I/O group control status register, Address offset: 0x30 /
mbed_official	5:ac9f6c2c45e8	522	__IO uint32_t IOGXCR[8]; /!< TSC I/O group x counter register, Address offset: 0x34-50 /
mbed_official	5:ac9f6c2c45e8	523	}TSC_TypeDef;
mbed_official	5:ac9f6c2c45e8	524
mbed_official	5:ac9f6c2c45e8	525	/**
mbed_official	5:ac9f6c2c45e8	526	* @brief Universal Synchronous Asynchronous Receiver Transmitter
mbed_official	5:ac9f6c2c45e8	527	*/
mbed_official	5:ac9f6c2c45e8	528
mbed_official	5:ac9f6c2c45e8	529	typedef struct
mbed_official	5:ac9f6c2c45e8	530	{
mbed_official	5:ac9f6c2c45e8	531	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x00 /
mbed_official	5:ac9f6c2c45e8	532	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x04 /
mbed_official	5:ac9f6c2c45e8	533	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x08 /
mbed_official	5:ac9f6c2c45e8	534	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x0C /
mbed_official	5:ac9f6c2c45e8	535	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x10 /
mbed_official	5:ac9f6c2c45e8	536	__IO uint32_t RTOR; /!< USART Receiver Time Out register, Address offset: 0x14 /
mbed_official	5:ac9f6c2c45e8	537	__IO uint32_t RQR; /!< USART Request register, Address offset: 0x18 /
mbed_official	5:ac9f6c2c45e8	538	__IO uint32_t ISR; /!< USART Interrupt and status register, Address offset: 0x1C /
mbed_official	5:ac9f6c2c45e8	539	__IO uint32_t ICR; /!< USART Interrupt flag Clear register, Address offset: 0x20 /
mbed_official	5:ac9f6c2c45e8	540	__IO uint16_t RDR; /!< USART Receive Data register, Address offset: 0x24 /
mbed_official	5:ac9f6c2c45e8	541	uint16_t RESERVED1; /!< Reserved, 0x26 /
mbed_official	5:ac9f6c2c45e8	542	__IO uint16_t TDR; /!< USART Transmit Data register, Address offset: 0x28 /
mbed_official	5:ac9f6c2c45e8	543	uint16_t RESERVED2; /!< Reserved, 0x2A /
mbed_official	5:ac9f6c2c45e8	544	}USART_TypeDef;
mbed_official	5:ac9f6c2c45e8	545
mbed_official	5:ac9f6c2c45e8	546	/**
mbed_official	5:ac9f6c2c45e8	547	* @brief Universal Serial Bus Full Speed Device
mbed_official	5:ac9f6c2c45e8	548	*/
mbed_official	5:ac9f6c2c45e8	549
mbed_official	5:ac9f6c2c45e8	550	typedef struct
mbed_official	5:ac9f6c2c45e8	551	{
mbed_official	5:ac9f6c2c45e8	552	__IO uint16_t EP0R; /!< USB Endpoint 0 register, Address offset: 0x00 /
mbed_official	5:ac9f6c2c45e8	553	__IO uint16_t RESERVED0; /!< Reserved /
mbed_official	5:ac9f6c2c45e8	554	__IO uint16_t EP1R; /!< USB Endpoint 1 register, Address offset: 0x04 /
mbed_official	5:ac9f6c2c45e8	555	__IO uint16_t RESERVED1; /!< Reserved /
mbed_official	5:ac9f6c2c45e8	556	__IO uint16_t EP2R; /!< USB Endpoint 2 register, Address offset: 0x08 /
mbed_official	5:ac9f6c2c45e8	557	__IO uint16_t RESERVED2; /!< Reserved /
mbed_official	5:ac9f6c2c45e8	558	__IO uint16_t EP3R; /!< USB Endpoint 3 register, Address offset: 0x0C /
mbed_official	5:ac9f6c2c45e8	559	__IO uint16_t RESERVED3; /!< Reserved /
mbed_official	5:ac9f6c2c45e8	560	__IO uint16_t EP4R; /!< USB Endpoint 4 register, Address offset: 0x10 /
mbed_official	5:ac9f6c2c45e8	561	__IO uint16_t RESERVED4; /!< Reserved /
mbed_official	5:ac9f6c2c45e8	562	__IO uint16_t EP5R; /!< USB Endpoint 5 register, Address offset: 0x14 /
mbed_official	5:ac9f6c2c45e8	563	__IO uint16_t RESERVED5; /!< Reserved /
mbed_official	5:ac9f6c2c45e8	564	__IO uint16_t EP6R; /!< USB Endpoint 6 register, Address offset: 0x18 /
mbed_official	5:ac9f6c2c45e8	565	__IO uint16_t RESERVED6; /!< Reserved /
mbed_official	5:ac9f6c2c45e8	566	__IO uint16_t EP7R; /!< USB Endpoint 7 register, Address offset: 0x1C /
mbed_official	5:ac9f6c2c45e8	567	__IO uint16_t RESERVED7[17]; /!< Reserved /
mbed_official	5:ac9f6c2c45e8	568	__IO uint16_t CNTR; /!< Control register, Address offset: 0x40 /
mbed_official	5:ac9f6c2c45e8	569	__IO uint16_t RESERVED8; /!< Reserved /
mbed_official	5:ac9f6c2c45e8	570	__IO uint16_t ISTR; /!< Interrupt status register, Address offset: 0x44 /
mbed_official	5:ac9f6c2c45e8	571	__IO uint16_t RESERVED9; /!< Reserved /
mbed_official	5:ac9f6c2c45e8	572	__IO uint16_t FNR; /!< Frame number register, Address offset: 0x48 /
mbed_official	5:ac9f6c2c45e8	573	__IO uint16_t RESERVEDA; /!< Reserved /
mbed_official	5:ac9f6c2c45e8	574	__IO uint16_t DADDR; /!< Device address register, Address offset: 0x4C /
mbed_official	5:ac9f6c2c45e8	575	__IO uint16_t RESERVEDB; /!< Reserved /
mbed_official	5:ac9f6c2c45e8	576	__IO uint16_t BTABLE; /!< Buffer Table address register, Address offset: 0x50 /
mbed_official	5:ac9f6c2c45e8	577	__IO uint16_t RESERVEDC; /!< Reserved /
mbed_official	5:ac9f6c2c45e8	578	__IO uint16_t LPMCSR; /!< LPM Control and Status register, Address offset: 0x54 /
mbed_official	5:ac9f6c2c45e8	579	__IO uint16_t RESERVEDD; /!< Reserved /
mbed_official	5:ac9f6c2c45e8	580	__IO uint16_t BCDR; /!< Battery Charging detector register, Address offset: 0x58 /
mbed_official	5:ac9f6c2c45e8	581	__IO uint16_t RESERVEDE; /!< Reserved /
mbed_official	5:ac9f6c2c45e8	582	}USB_TypeDef;
mbed_official	5:ac9f6c2c45e8	583
mbed_official	5:ac9f6c2c45e8	584	/**
mbed_official	5:ac9f6c2c45e8	585	* @brief Window WATCHDOG
mbed_official	5:ac9f6c2c45e8	586	*/
mbed_official	5:ac9f6c2c45e8	587	typedef struct
mbed_official	5:ac9f6c2c45e8	588	{
mbed_official	5:ac9f6c2c45e8	589	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
mbed_official	5:ac9f6c2c45e8	590	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
mbed_official	5:ac9f6c2c45e8	591	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
mbed_official	5:ac9f6c2c45e8	592	}WWDG_TypeDef;
mbed_official	5:ac9f6c2c45e8	593
mbed_official	5:ac9f6c2c45e8	594	/**
mbed_official	5:ac9f6c2c45e8	595	* @}
mbed_official	5:ac9f6c2c45e8	596	*/
mbed_official	5:ac9f6c2c45e8	597
mbed_official	5:ac9f6c2c45e8	598	/** @addtogroup Peripheral_memory_map
mbed_official	5:ac9f6c2c45e8	599	* @{
mbed_official	5:ac9f6c2c45e8	600	*/
mbed_official	5:ac9f6c2c45e8	601
mbed_official	5:ac9f6c2c45e8	602	#define FLASH_BASE ((uint32_t)0x08000000) /!< FLASH base address in the alias region /
mbed_official	5:ac9f6c2c45e8	603	#define FLASH_BANK1_END ((uint32_t)0x08007FFF) /!< FLASH END address of bank1 /
mbed_official	5:ac9f6c2c45e8	604	#define SRAM_BASE ((uint32_t)0x20000000) /!< SRAM base address in the alias region /
mbed_official	5:ac9f6c2c45e8	605	#define PERIPH_BASE ((uint32_t)0x40000000) /!< Peripheral base address in the alias region /
mbed_official	5:ac9f6c2c45e8	606
mbed_official	5:ac9f6c2c45e8	607	/!< Peripheral memory map /
mbed_official	5:ac9f6c2c45e8	608	#define APBPERIPH_BASE PERIPH_BASE
mbed_official	5:ac9f6c2c45e8	609	#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
mbed_official	5:ac9f6c2c45e8	610	#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
mbed_official	5:ac9f6c2c45e8	611
mbed_official	5:ac9f6c2c45e8	612	#define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
mbed_official	5:ac9f6c2c45e8	613	#define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
mbed_official	5:ac9f6c2c45e8	614	#define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
mbed_official	5:ac9f6c2c45e8	615	#define RTC_BASE (APBPERIPH_BASE + 0x00002800)
mbed_official	5:ac9f6c2c45e8	616	#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
mbed_official	5:ac9f6c2c45e8	617	#define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
mbed_official	5:ac9f6c2c45e8	618	#define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
mbed_official	5:ac9f6c2c45e8	619	#define USART2_BASE (APBPERIPH_BASE + 0x00004400)
mbed_official	5:ac9f6c2c45e8	620	#define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
mbed_official	5:ac9f6c2c45e8	621	#define USB_BASE (APBPERIPH_BASE + 0x00005C00) /!< USB_IP Peripheral Registers base address /
mbed_official	5:ac9f6c2c45e8	622	#define USB_PMAADDR (APBPERIPH_BASE + 0x00006000) /!< USB_IP Packet Memory Area base address /
mbed_official	5:ac9f6c2c45e8	623	#define CAN_BASE (APBPERIPH_BASE + 0x00006400)
mbed_official	5:ac9f6c2c45e8	624	#define CRS_BASE (APBPERIPH_BASE + 0x00006C00)
mbed_official	5:ac9f6c2c45e8	625	#define PWR_BASE (APBPERIPH_BASE + 0x00007000)
mbed_official	5:ac9f6c2c45e8	626	#define CEC_BASE (APBPERIPH_BASE + 0x00007800)
mbed_official	5:ac9f6c2c45e8	627
mbed_official	5:ac9f6c2c45e8	628	#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
mbed_official	5:ac9f6c2c45e8	629	#define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
mbed_official	5:ac9f6c2c45e8	630	#define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
mbed_official	5:ac9f6c2c45e8	631	#define ADC_BASE (APBPERIPH_BASE + 0x00012708)
mbed_official	5:ac9f6c2c45e8	632	#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
mbed_official	5:ac9f6c2c45e8	633	#define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
mbed_official	5:ac9f6c2c45e8	634	#define USART1_BASE (APBPERIPH_BASE + 0x00013800)
mbed_official	5:ac9f6c2c45e8	635	#define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
mbed_official	5:ac9f6c2c45e8	636	#define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
mbed_official	5:ac9f6c2c45e8	637	#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
mbed_official	5:ac9f6c2c45e8	638
mbed_official	5:ac9f6c2c45e8	639	#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
mbed_official	5:ac9f6c2c45e8	640	#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
mbed_official	5:ac9f6c2c45e8	641	#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
mbed_official	5:ac9f6c2c45e8	642	#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
mbed_official	5:ac9f6c2c45e8	643	#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
mbed_official	5:ac9f6c2c45e8	644	#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
mbed_official	5:ac9f6c2c45e8	645	#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
mbed_official	5:ac9f6c2c45e8	646	#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
mbed_official	5:ac9f6c2c45e8	647
mbed_official	5:ac9f6c2c45e8	648	#define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
mbed_official	5:ac9f6c2c45e8	649	#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /!< FLASH registers base address /
mbed_official	5:ac9f6c2c45e8	650	#define OB_BASE ((uint32_t)0x1FFFF800) /!< FLASH Option Bytes base address /
mbed_official	5:ac9f6c2c45e8	651	#define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
mbed_official	5:ac9f6c2c45e8	652	#define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
mbed_official	5:ac9f6c2c45e8	653
mbed_official	5:ac9f6c2c45e8	654	#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
mbed_official	5:ac9f6c2c45e8	655	#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
mbed_official	5:ac9f6c2c45e8	656	#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
mbed_official	5:ac9f6c2c45e8	657	#define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
mbed_official	5:ac9f6c2c45e8	658
mbed_official	5:ac9f6c2c45e8	659	/**
mbed_official	5:ac9f6c2c45e8	660	* @}
mbed_official	5:ac9f6c2c45e8	661	*/
mbed_official	5:ac9f6c2c45e8	662
mbed_official	5:ac9f6c2c45e8	663	/** @addtogroup Peripheral_declaration
mbed_official	5:ac9f6c2c45e8	664	* @{
mbed_official	5:ac9f6c2c45e8	665	*/
mbed_official	5:ac9f6c2c45e8	666
mbed_official	5:ac9f6c2c45e8	667	#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
mbed_official	5:ac9f6c2c45e8	668	#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
mbed_official	5:ac9f6c2c45e8	669	#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
mbed_official	5:ac9f6c2c45e8	670	#define RTC ((RTC_TypeDef *) RTC_BASE)
mbed_official	5:ac9f6c2c45e8	671	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
mbed_official	5:ac9f6c2c45e8	672	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
mbed_official	5:ac9f6c2c45e8	673	#define USART2 ((USART_TypeDef *) USART2_BASE)
mbed_official	5:ac9f6c2c45e8	674	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
mbed_official	135:eec55f8ee438	675	#define CAN1 ((CAN_TypeDef *) CAN_BASE)
mbed_official	5:ac9f6c2c45e8	676	#define CRS ((CRS_TypeDef *) CRS_BASE)
mbed_official	5:ac9f6c2c45e8	677	#define PWR ((PWR_TypeDef *) PWR_BASE)
mbed_official	5:ac9f6c2c45e8	678	#define CEC ((CEC_TypeDef *) CEC_BASE)
mbed_official	5:ac9f6c2c45e8	679	#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
mbed_official	5:ac9f6c2c45e8	680	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
mbed_official	5:ac9f6c2c45e8	681	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
mbed_official	5:ac9f6c2c45e8	682	#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
mbed_official	5:ac9f6c2c45e8	683	#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
mbed_official	5:ac9f6c2c45e8	684	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
mbed_official	5:ac9f6c2c45e8	685	#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
mbed_official	5:ac9f6c2c45e8	686	#define USART1 ((USART_TypeDef *) USART1_BASE)
mbed_official	5:ac9f6c2c45e8	687	#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
mbed_official	5:ac9f6c2c45e8	688	#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
mbed_official	5:ac9f6c2c45e8	689	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
mbed_official	5:ac9f6c2c45e8	690	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
mbed_official	5:ac9f6c2c45e8	691	#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
mbed_official	5:ac9f6c2c45e8	692	#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
mbed_official	5:ac9f6c2c45e8	693	#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
mbed_official	5:ac9f6c2c45e8	694	#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
mbed_official	5:ac9f6c2c45e8	695	#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
mbed_official	5:ac9f6c2c45e8	696	#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
mbed_official	5:ac9f6c2c45e8	697	#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
mbed_official	5:ac9f6c2c45e8	698	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
mbed_official	5:ac9f6c2c45e8	699	#define OB ((OB_TypeDef *) OB_BASE)
mbed_official	5:ac9f6c2c45e8	700	#define RCC ((RCC_TypeDef *) RCC_BASE)
mbed_official	5:ac9f6c2c45e8	701	#define CRC ((CRC_TypeDef *) CRC_BASE)
mbed_official	5:ac9f6c2c45e8	702	#define TSC ((TSC_TypeDef *) TSC_BASE)
mbed_official	5:ac9f6c2c45e8	703	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
mbed_official	5:ac9f6c2c45e8	704	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
mbed_official	5:ac9f6c2c45e8	705	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
mbed_official	5:ac9f6c2c45e8	706	#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
mbed_official	5:ac9f6c2c45e8	707	#define USB ((USB_TypeDef *) USB_BASE)
mbed_official	5:ac9f6c2c45e8	708	/**
mbed_official	5:ac9f6c2c45e8	709	* @}
mbed_official	5:ac9f6c2c45e8	710	*/
mbed_official	5:ac9f6c2c45e8	711
mbed_official	5:ac9f6c2c45e8	712	/** @addtogroup Exported_constants
mbed_official	5:ac9f6c2c45e8	713	* @{
mbed_official	5:ac9f6c2c45e8	714	*/
mbed_official	5:ac9f6c2c45e8	715
mbed_official	5:ac9f6c2c45e8	716	/** @addtogroup Peripheral_Registers_Bits_Definition
mbed_official	5:ac9f6c2c45e8	717	* @{
mbed_official	5:ac9f6c2c45e8	718	*/
mbed_official	5:ac9f6c2c45e8	719
mbed_official	5:ac9f6c2c45e8	720	/******************************************************************************/
mbed_official	5:ac9f6c2c45e8	721	/* Peripheral Registers Bits Definition */
mbed_official	5:ac9f6c2c45e8	722	/******************************************************************************/
mbed_official	5:ac9f6c2c45e8	723	/******************************************************************************/
mbed_official	5:ac9f6c2c45e8	724	/* */
mbed_official	5:ac9f6c2c45e8	725	/* Analog to Digital Converter (ADC) */
mbed_official	5:ac9f6c2c45e8	726	/* */
mbed_official	5:ac9f6c2c45e8	727	/******************************************************************************/
mbed_official	5:ac9f6c2c45e8	728	/****************** Bits definition for ADC_ISR register ****************/
mbed_official	5:ac9f6c2c45e8	729	#define ADC_ISR_AWD ((uint32_t)0x00000080) /!< Analog watchdog flag /
mbed_official	5:ac9f6c2c45e8	730	#define ADC_ISR_OVR ((uint32_t)0x00000010) /!< Overrun flag /
mbed_official	5:ac9f6c2c45e8	731	#define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /!< End of Sequence flag /
mbed_official	5:ac9f6c2c45e8	732	#define ADC_ISR_EOC ((uint32_t)0x00000004) /!< End of Conversion /
mbed_official	5:ac9f6c2c45e8	733	#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /!< End of sampling flag /
mbed_official	5:ac9f6c2c45e8	734	#define ADC_ISR_ADRDY ((uint32_t)0x00000001) /!< ADC Ready /
mbed_official	5:ac9f6c2c45e8	735
mbed_official	5:ac9f6c2c45e8	736	/* Old EOSEQ bit definition, maintained for legacy purpose */
mbed_official	5:ac9f6c2c45e8	737	#define ADC_ISR_EOS ADC_ISR_EOSEQ
mbed_official	5:ac9f6c2c45e8	738
mbed_official	5:ac9f6c2c45e8	739	/****************** Bits definition for ADC_IER register ****************/
mbed_official	5:ac9f6c2c45e8	740	#define ADC_IER_AWDIE ((uint32_t)0x00000080) /!< Analog Watchdog interrupt enable /
mbed_official	5:ac9f6c2c45e8	741	#define ADC_IER_OVRIE ((uint32_t)0x00000010) /!< Overrun interrupt enable /
mbed_official	5:ac9f6c2c45e8	742	#define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /!< End of Sequence of conversion interrupt enable /
mbed_official	5:ac9f6c2c45e8	743	#define ADC_IER_EOCIE ((uint32_t)0x00000004) /!< End of Conversion interrupt enable /
mbed_official	5:ac9f6c2c45e8	744	#define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /!< End of sampling interrupt enable /
mbed_official	5:ac9f6c2c45e8	745	#define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /!< ADC Ready interrupt enable /
mbed_official	5:ac9f6c2c45e8	746
mbed_official	5:ac9f6c2c45e8	747	/* Old EOSEQIE bit definition, maintained for legacy purpose */
mbed_official	5:ac9f6c2c45e8	748	#define ADC_IER_EOSIE ADC_IER_EOSEQIE
mbed_official	5:ac9f6c2c45e8	749
mbed_official	5:ac9f6c2c45e8	750	/****************** Bits definition for ADC_CR register *****************/
mbed_official	5:ac9f6c2c45e8	751	#define ADC_CR_ADCAL ((uint32_t)0x80000000) /!< ADC calibration /
mbed_official	5:ac9f6c2c45e8	752	#define ADC_CR_ADSTP ((uint32_t)0x00000010) /!< ADC stop of conversion command /
mbed_official	5:ac9f6c2c45e8	753	#define ADC_CR_ADSTART ((uint32_t)0x00000004) /!< ADC start of conversion /
mbed_official	5:ac9f6c2c45e8	754	#define ADC_CR_ADDIS ((uint32_t)0x00000002) /!< ADC disable command /
mbed_official	5:ac9f6c2c45e8	755	#define ADC_CR_ADEN ((uint32_t)0x00000001) /!< ADC enable control /
mbed_official	5:ac9f6c2c45e8	756
mbed_official	5:ac9f6c2c45e8	757	/***************** Bits definition for ADC_CFGR1 register ***************/
mbed_official	5:ac9f6c2c45e8	758	#define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /!< AWDCH[4:0] bits (Analog watchdog channel select bits) /
mbed_official	5:ac9f6c2c45e8	759	#define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /!< Bit 0 /
mbed_official	5:ac9f6c2c45e8	760	#define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /!< Bit 1 /
mbed_official	5:ac9f6c2c45e8	761	#define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /!< Bit 2 /
mbed_official	5:ac9f6c2c45e8	762	#define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /!< Bit 3 /
mbed_official	5:ac9f6c2c45e8	763	#define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /!< Bit 4 /
mbed_official	5:ac9f6c2c45e8	764	#define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /!< Analog watchdog enable on regular channels /
mbed_official	5:ac9f6c2c45e8	765	#define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /!< Enable the watchdog on a single channel or on all channels /
mbed_official	5:ac9f6c2c45e8	766	#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /!< Discontinuous mode on regular channels /
mbed_official	5:ac9f6c2c45e8	767	#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /!< ADC auto power off /
mbed_official	5:ac9f6c2c45e8	768	#define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /!< ADC wait conversion mode /
mbed_official	5:ac9f6c2c45e8	769	#define ADC_CFGR1_CONT ((uint32_t)0x00002000) /!< Continuous Conversion /
mbed_official	5:ac9f6c2c45e8	770	#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /!< Overrun mode /
mbed_official	5:ac9f6c2c45e8	771	#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) /
mbed_official	5:ac9f6c2c45e8	772	#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /!< Bit 0 /
mbed_official	5:ac9f6c2c45e8	773	#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /!< Bit 1 /
mbed_official	5:ac9f6c2c45e8	774	#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /!< EXTSEL[2:0] bits (External Event Select for regular group) /
mbed_official	5:ac9f6c2c45e8	775	#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /!< Bit 0 /
mbed_official	5:ac9f6c2c45e8	776	#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /!< Bit 1 /
mbed_official	5:ac9f6c2c45e8	777	#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /!< Bit 2 /
mbed_official	5:ac9f6c2c45e8	778	#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /!< Data Alignment /
mbed_official	5:ac9f6c2c45e8	779	#define ADC_CFGR1_RES ((uint32_t)0x00000018) /!< RES[1:0] bits (Resolution) /
mbed_official	5:ac9f6c2c45e8	780	#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /!< Bit 0 /
mbed_official	5:ac9f6c2c45e8	781	#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /!< Bit 1 /
mbed_official	5:ac9f6c2c45e8	782	#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /!< Sequence scan direction /
mbed_official	5:ac9f6c2c45e8	783	#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /!< Direct memory access configuration /
mbed_official	5:ac9f6c2c45e8	784	#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /!< Direct memory access enable /
mbed_official	5:ac9f6c2c45e8	785
mbed_official	5:ac9f6c2c45e8	786	/* Old WAIT bit definition, maintained for legacy purpose */
mbed_official	5:ac9f6c2c45e8	787	#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
mbed_official	5:ac9f6c2c45e8	788
mbed_official	5:ac9f6c2c45e8	789	/***************** Bits definition for ADC_CFGR2 register ***************/
mbed_official	5:ac9f6c2c45e8	790	#define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /!< ADC clock mode /
mbed_official	5:ac9f6c2c45e8	791	#define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /!< ADC clocked by PCLK div4 /
mbed_official	5:ac9f6c2c45e8	792	#define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /!< ADC clocked by PCLK div2 /
mbed_official	5:ac9f6c2c45e8	793
mbed_official	5:ac9f6c2c45e8	794	/* Old bit definition, maintained for legacy purpose */
mbed_official	5:ac9f6c2c45e8	795	#define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /!< ADC clocked by PCLK div4 /
mbed_official	5:ac9f6c2c45e8	796	#define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /!< ADC clocked by PCLK div2 /
mbed_official	5:ac9f6c2c45e8	797
mbed_official	5:ac9f6c2c45e8	798	/**************** Bit definition for ADC_SMPR register ******************/
mbed_official	5:ac9f6c2c45e8	799	#define ADC_SMPR_SMP ((uint32_t)0x00000007) /!< SMP[2:0] bits (Sampling time selection) /
mbed_official	5:ac9f6c2c45e8	800	#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	5:ac9f6c2c45e8	801	#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	5:ac9f6c2c45e8	802	#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /!< Bit 2 /
mbed_official	5:ac9f6c2c45e8	803
mbed_official	5:ac9f6c2c45e8	804	/* Old bit definition, maintained for legacy purpose */
mbed_official	5:ac9f6c2c45e8	805	#define ADC_SMPR1_SMPR ADC_SMPR_SMP /!< SMP[2:0] bits (Sampling time selection) /
mbed_official	5:ac9f6c2c45e8	806	#define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /!< Bit 0 /
mbed_official	5:ac9f6c2c45e8	807	#define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /!< Bit 1 /
mbed_official	5:ac9f6c2c45e8	808	#define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /!< Bit 2 /
mbed_official	5:ac9f6c2c45e8	809
mbed_official	5:ac9f6c2c45e8	810	/***************** Bit definition for ADC_TR register ******************/
mbed_official	5:ac9f6c2c45e8	811	#define ADC_TR_HT ((uint32_t)0x0FFF0000) /!< Analog watchdog high threshold /
mbed_official	5:ac9f6c2c45e8	812	#define ADC_TR_LT ((uint32_t)0x00000FFF) /!< Analog watchdog low threshold /
mbed_official	5:ac9f6c2c45e8	813
mbed_official	5:ac9f6c2c45e8	814	/* Old bit definition, maintained for legacy purpose */
mbed_official	5:ac9f6c2c45e8	815	#define ADC_HTR_HT ADC_TR_HT /!< Analog watchdog high threshold /
mbed_official	5:ac9f6c2c45e8	816	#define ADC_LTR_LT ADC_TR_LT /!< Analog watchdog low threshold /
mbed_official	5:ac9f6c2c45e8	817
mbed_official	5:ac9f6c2c45e8	818	/**************** Bit definition for ADC_CHSELR register ****************/
mbed_official	5:ac9f6c2c45e8	819	#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /!< Channel 18 selection /
mbed_official	5:ac9f6c2c45e8	820	#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /!< Channel 17 selection /
mbed_official	5:ac9f6c2c45e8	821	#define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /!< Channel 16 selection /
mbed_official	5:ac9f6c2c45e8	822	#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /!< Channel 15 selection /
mbed_official	5:ac9f6c2c45e8	823	#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /!< Channel 14 selection /
mbed_official	5:ac9f6c2c45e8	824	#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /!< Channel 13 selection /
mbed_official	5:ac9f6c2c45e8	825	#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /!< Channel 12 selection /
mbed_official	5:ac9f6c2c45e8	826	#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /!< Channel 11 selection /
mbed_official	5:ac9f6c2c45e8	827	#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /!< Channel 10 selection /
mbed_official	5:ac9f6c2c45e8	828	#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /!< Channel 9 selection /
mbed_official	5:ac9f6c2c45e8	829	#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /!< Channel 8 selection /
mbed_official	5:ac9f6c2c45e8	830	#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /!< Channel 7 selection /
mbed_official	5:ac9f6c2c45e8	831	#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /!< Channel 6 selection /
mbed_official	5:ac9f6c2c45e8	832	#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /!< Channel 5 selection /
mbed_official	5:ac9f6c2c45e8	833	#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /!< Channel 4 selection /
mbed_official	5:ac9f6c2c45e8	834	#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /!< Channel 3 selection /
mbed_official	5:ac9f6c2c45e8	835	#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /!< Channel 2 selection /
mbed_official	5:ac9f6c2c45e8	836	#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /!< Channel 1 selection /
mbed_official	5:ac9f6c2c45e8	837	#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /!< Channel 0 selection /
mbed_official	5:ac9f6c2c45e8	838
mbed_official	5:ac9f6c2c45e8	839	/****************** Bit definition for ADC_DR register ******************/
mbed_official	5:ac9f6c2c45e8	840	#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /!< Regular data /
mbed_official	5:ac9f6c2c45e8	841
mbed_official	5:ac9f6c2c45e8	842	/***************** Bit definition for ADC_CCR register ******************/
mbed_official	5:ac9f6c2c45e8	843	#define ADC_CCR_VBATEN ((uint32_t)0x01000000) /!< Voltage battery enable /
mbed_official	5:ac9f6c2c45e8	844	#define ADC_CCR_TSEN ((uint32_t)0x00800000) /!< Tempurature sensore enable /
mbed_official	5:ac9f6c2c45e8	845	#define ADC_CCR_VREFEN ((uint32_t)0x00400000) /!< Vrefint enable /
mbed_official	5:ac9f6c2c45e8	846
mbed_official	5:ac9f6c2c45e8	847	/******************************************************************************/
mbed_official	5:ac9f6c2c45e8	848	/* */
mbed_official	5:ac9f6c2c45e8	849	/* Controller Area Network (CAN ) */
mbed_official	5:ac9f6c2c45e8	850	/* */
mbed_official	5:ac9f6c2c45e8	851	/******************************************************************************/
mbed_official	5:ac9f6c2c45e8	852	/!<CAN control and status registers /
mbed_official	5:ac9f6c2c45e8	853	/***************** Bit definition for CAN_MCR register ******************/
mbed_official	5:ac9f6c2c45e8	854	#define CAN_MCR_INRQ ((uint32_t)0x00000001) /!<Initialization Request /
mbed_official	5:ac9f6c2c45e8	855	#define CAN_MCR_SLEEP ((uint32_t)0x00000002) /!<Sleep Mode Request /
mbed_official	5:ac9f6c2c45e8	856	#define CAN_MCR_TXFP ((uint32_t)0x00000004) /!<Transmit FIFO Priority /
mbed_official	5:ac9f6c2c45e8	857	#define CAN_MCR_RFLM ((uint32_t)0x00000008) /!<Receive FIFO Locked Mode /
mbed_official	5:ac9f6c2c45e8	858	#define CAN_MCR_NART ((uint32_t)0x00000010) /!<No Automatic Retransmission /
mbed_official	5:ac9f6c2c45e8	859	#define CAN_MCR_AWUM ((uint32_t)0x00000020) /!<Automatic Wakeup Mode /
mbed_official	5:ac9f6c2c45e8	860	#define CAN_MCR_ABOM ((uint32_t)0x00000040) /!<Automatic Bus-Off Management /
mbed_official	5:ac9f6c2c45e8	861	#define CAN_MCR_TTCM ((uint32_t)0x00000080) /!<Time Triggered Communication Mode /
mbed_official	5:ac9f6c2c45e8	862	#define CAN_MCR_RESET ((uint32_t)0x00008000) /!<bxCAN software master reset /
mbed_official	5:ac9f6c2c45e8	863
mbed_official	5:ac9f6c2c45e8	864	/***************** Bit definition for CAN_MSR register ******************/
mbed_official	5:ac9f6c2c45e8	865	#define CAN_MSR_INAK ((uint32_t)0x00000001) /!<Initialization Acknowledge /
mbed_official	5:ac9f6c2c45e8	866	#define CAN_MSR_SLAK ((uint32_t)0x00000002) /!<Sleep Acknowledge /
mbed_official	5:ac9f6c2c45e8	867	#define CAN_MSR_ERRI ((uint32_t)0x00000004) /!<Error Interrupt /
mbed_official	5:ac9f6c2c45e8	868	#define CAN_MSR_WKUI ((uint32_t)0x00000008) /!<Wakeup Interrupt /
mbed_official	5:ac9f6c2c45e8	869	#define CAN_MSR_SLAKI ((uint32_t)0x00000010) /!<Sleep Acknowledge Interrupt /
mbed_official	5:ac9f6c2c45e8	870	#define CAN_MSR_TXM ((uint32_t)0x00000100) /!<Transmit Mode /
mbed_official	5:ac9f6c2c45e8	871	#define CAN_MSR_RXM ((uint32_t)0x00000200) /!<Receive Mode /
mbed_official	5:ac9f6c2c45e8	872	#define CAN_MSR_SAMP ((uint32_t)0x00000400) /!<Last Sample Point /
mbed_official	5:ac9f6c2c45e8	873	#define CAN_MSR_RX ((uint32_t)0x00000800) /!<CAN Rx Signal /
mbed_official	5:ac9f6c2c45e8	874
mbed_official	5:ac9f6c2c45e8	875	/***************** Bit definition for CAN_TSR register ******************/
mbed_official	5:ac9f6c2c45e8	876	#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /!<Request Completed Mailbox0 /
mbed_official	5:ac9f6c2c45e8	877	#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /!<Transmission OK of Mailbox0 /
mbed_official	5:ac9f6c2c45e8	878	#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /!<Arbitration Lost for Mailbox0 /
mbed_official	5:ac9f6c2c45e8	879	#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /!<Transmission Error of Mailbox0 /
mbed_official	5:ac9f6c2c45e8	880	#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /!<Abort Request for Mailbox0 /
mbed_official	5:ac9f6c2c45e8	881	#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /!<Request Completed Mailbox1 /
mbed_official	5:ac9f6c2c45e8	882	#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /!<Transmission OK of Mailbox1 /
mbed_official	5:ac9f6c2c45e8	883	#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /!<Arbitration Lost for Mailbox1 /
mbed_official	5:ac9f6c2c45e8	884	#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /!<Transmission Error of Mailbox1 /
mbed_official	5:ac9f6c2c45e8	885	#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /!<Abort Request for Mailbox 1 /
mbed_official	5:ac9f6c2c45e8	886	#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /!<Request Completed Mailbox2 /
mbed_official	5:ac9f6c2c45e8	887	#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /!<Transmission OK of Mailbox 2 /
mbed_official	5:ac9f6c2c45e8	888	#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /!<Arbitration Lost for mailbox 2 /
mbed_official	5:ac9f6c2c45e8	889	#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /!<Transmission Error of Mailbox 2 /
mbed_official	5:ac9f6c2c45e8	890	#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /!<Abort Request for Mailbox 2 /
mbed_official	5:ac9f6c2c45e8	891	#define CAN_TSR_CODE ((uint32_t)0x03000000) /!<Mailbox Code /
mbed_official	5:ac9f6c2c45e8	892
mbed_official	5:ac9f6c2c45e8	893	#define CAN_TSR_TME ((uint32_t)0x1C000000) /!<TME[2:0] bits /
mbed_official	5:ac9f6c2c45e8	894	#define CAN_TSR_TME0 ((uint32_t)0x04000000) /!<Transmit Mailbox 0 Empty /
mbed_official	5:ac9f6c2c45e8	895	#define CAN_TSR_TME1 ((uint32_t)0x08000000) /!<Transmit Mailbox 1 Empty /
mbed_official	5:ac9f6c2c45e8	896	#define CAN_TSR_TME2 ((uint32_t)0x10000000) /!<Transmit Mailbox 2 Empty /
mbed_official	5:ac9f6c2c45e8	897
mbed_official	5:ac9f6c2c45e8	898	#define CAN_TSR_LOW ((uint32_t)0xE0000000) /!<LOW[2:0] bits /
mbed_official	5:ac9f6c2c45e8	899	#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /!<Lowest Priority Flag for Mailbox 0 /
mbed_official	5:ac9f6c2c45e8	900	#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /!<Lowest Priority Flag for Mailbox 1 /
mbed_official	5:ac9f6c2c45e8	901	#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /!<Lowest Priority Flag for Mailbox 2 /
mbed_official	5:ac9f6c2c45e8	902
mbed_official	5:ac9f6c2c45e8	903	/***************** Bit definition for CAN_RF0R register *****************/
mbed_official	5:ac9f6c2c45e8	904	#define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /!<FIFO 0 Message Pending /
mbed_official	5:ac9f6c2c45e8	905	#define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /!<FIFO 0 Full /
mbed_official	5:ac9f6c2c45e8	906	#define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /!<FIFO 0 Overrun /
mbed_official	5:ac9f6c2c45e8	907	#define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /!<Release FIFO 0 Output Mailbox /
mbed_official	5:ac9f6c2c45e8	908
mbed_official	5:ac9f6c2c45e8	909	/***************** Bit definition for CAN_RF1R register *****************/
mbed_official	5:ac9f6c2c45e8	910	#define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /!<FIFO 1 Message Pending /
mbed_official	5:ac9f6c2c45e8	911	#define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /!<FIFO 1 Full /
mbed_official	5:ac9f6c2c45e8	912	#define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /!<FIFO 1 Overrun /
mbed_official	5:ac9f6c2c45e8	913	#define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /!<Release FIFO 1 Output Mailbox /
mbed_official	5:ac9f6c2c45e8	914
mbed_official	5:ac9f6c2c45e8	915	/****************** Bit definition for CAN_IER register *****************/
mbed_official	5:ac9f6c2c45e8	916	#define CAN_IER_TMEIE ((uint32_t)0x00000001) /!<Transmit Mailbox Empty Interrupt Enable /
mbed_official	5:ac9f6c2c45e8	917	#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /!<FIFO Message Pending Interrupt Enable /
mbed_official	5:ac9f6c2c45e8	918	#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /!<FIFO Full Interrupt Enable /
mbed_official	5:ac9f6c2c45e8	919	#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /!<FIFO Overrun Interrupt Enable /
mbed_official	5:ac9f6c2c45e8	920	#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /!<FIFO Message Pending Interrupt Enable /
mbed_official	5:ac9f6c2c45e8	921	#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /!<FIFO Full Interrupt Enable /
mbed_official	5:ac9f6c2c45e8	922	#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /!<FIFO Overrun Interrupt Enable /
mbed_official	5:ac9f6c2c45e8	923	#define CAN_IER_EWGIE ((uint32_t)0x00000100) /!<Error Warning Interrupt Enable /
mbed_official	5:ac9f6c2c45e8	924	#define CAN_IER_EPVIE ((uint32_t)0x00000200) /!<Error Passive Interrupt Enable /
mbed_official	5:ac9f6c2c45e8	925	#define CAN_IER_BOFIE ((uint32_t)0x00000400) /!<Bus-Off Interrupt Enable /
mbed_official	5:ac9f6c2c45e8	926	#define CAN_IER_LECIE ((uint32_t)0x00000800) /!<Last Error Code Interrupt Enable /
mbed_official	5:ac9f6c2c45e8	927	#define CAN_IER_ERRIE ((uint32_t)0x00008000) /!<Error Interrupt Enable /
mbed_official	5:ac9f6c2c45e8	928	#define CAN_IER_WKUIE ((uint32_t)0x00010000) /!<Wakeup Interrupt Enable /
mbed_official	5:ac9f6c2c45e8	929	#define CAN_IER_SLKIE ((uint32_t)0x00020000) /!<Sleep Interrupt Enable /
mbed_official	5:ac9f6c2c45e8	930
mbed_official	5:ac9f6c2c45e8	931	/****************** Bit definition for CAN_ESR register *****************/
mbed_official	5:ac9f6c2c45e8	932	#define CAN_ESR_EWGF ((uint32_t)0x00000001) /!<Error Warning Flag /
mbed_official	5:ac9f6c2c45e8	933	#define CAN_ESR_EPVF ((uint32_t)0x00000002) /!<Error Passive Flag /
mbed_official	5:ac9f6c2c45e8	934	#define CAN_ESR_BOFF ((uint32_t)0x00000004) /!<Bus-Off Flag /
mbed_official	5:ac9f6c2c45e8	935
mbed_official	5:ac9f6c2c45e8	936	#define CAN_ESR_LEC ((uint32_t)0x00000070) /!<LEC[2:0] bits (Last Error Code) /
mbed_official	5:ac9f6c2c45e8	937	#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	938	#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	939	#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /!<Bit 2 /
mbed_official	5:ac9f6c2c45e8	940
mbed_official	5:ac9f6c2c45e8	941	#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /!<Least significant byte of the 9-bit Transmit Error Counter /
mbed_official	5:ac9f6c2c45e8	942	#define CAN_ESR_REC ((uint32_t)0xFF000000) /!<Receive Error Counter /
mbed_official	5:ac9f6c2c45e8	943
mbed_official	5:ac9f6c2c45e8	944	/***************** Bit definition for CAN_BTR register ******************/
mbed_official	5:ac9f6c2c45e8	945	#define CAN_BTR_BRP ((uint32_t)0x000003FF) /!<Baud Rate Prescaler /
mbed_official	5:ac9f6c2c45e8	946	#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /!<Time Segment 1 /
mbed_official	5:ac9f6c2c45e8	947	#define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /!<Time Segment 1 (Bit 0) /
mbed_official	5:ac9f6c2c45e8	948	#define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /!<Time Segment 1 (Bit 1) /
mbed_official	5:ac9f6c2c45e8	949	#define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /!<Time Segment 1 (Bit 2) /
mbed_official	5:ac9f6c2c45e8	950	#define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /!<Time Segment 1 (Bit 3) /
mbed_official	5:ac9f6c2c45e8	951	#define CAN_BTR_TS2 ((uint32_t)0x00700000) /!<Time Segment 2 /
mbed_official	5:ac9f6c2c45e8	952	#define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /!<Time Segment 2 (Bit 0) /
mbed_official	5:ac9f6c2c45e8	953	#define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /!<Time Segment 2 (Bit 1) /
mbed_official	5:ac9f6c2c45e8	954	#define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /!<Time Segment 2 (Bit 2) /
mbed_official	5:ac9f6c2c45e8	955	#define CAN_BTR_SJW ((uint32_t)0x03000000) /!<Resynchronization Jump Width /
mbed_official	5:ac9f6c2c45e8	956	#define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /!<Resynchronization Jump Width (Bit 0) /
mbed_official	5:ac9f6c2c45e8	957	#define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /!<Resynchronization Jump Width (Bit 1) /
mbed_official	5:ac9f6c2c45e8	958	#define CAN_BTR_LBKM ((uint32_t)0x40000000) /!<Loop Back Mode (Debug) /
mbed_official	5:ac9f6c2c45e8	959	#define CAN_BTR_SILM ((uint32_t)0x80000000) /!<Silent Mode /
mbed_official	5:ac9f6c2c45e8	960
mbed_official	5:ac9f6c2c45e8	961	/!<Mailbox registers /
mbed_official	5:ac9f6c2c45e8	962	/**************** Bit definition for CAN_TI0R register ******************/
mbed_official	5:ac9f6c2c45e8	963	#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /!<Transmit Mailbox Request /
mbed_official	5:ac9f6c2c45e8	964	#define CAN_TI0R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
mbed_official	5:ac9f6c2c45e8	965	#define CAN_TI0R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
mbed_official	5:ac9f6c2c45e8	966	#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /!<Extended Identifier /
mbed_official	5:ac9f6c2c45e8	967	#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
mbed_official	5:ac9f6c2c45e8	968
mbed_official	5:ac9f6c2c45e8	969	/**************** Bit definition for CAN_TDT0R register *****************/
mbed_official	5:ac9f6c2c45e8	970	#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
mbed_official	5:ac9f6c2c45e8	971	#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /!<Transmit Global Time /
mbed_official	5:ac9f6c2c45e8	972	#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
mbed_official	5:ac9f6c2c45e8	973
mbed_official	5:ac9f6c2c45e8	974	/**************** Bit definition for CAN_TDL0R register *****************/
mbed_official	5:ac9f6c2c45e8	975	#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
mbed_official	5:ac9f6c2c45e8	976	#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
mbed_official	5:ac9f6c2c45e8	977	#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
mbed_official	5:ac9f6c2c45e8	978	#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
mbed_official	5:ac9f6c2c45e8	979
mbed_official	5:ac9f6c2c45e8	980	/**************** Bit definition for CAN_TDH0R register *****************/
mbed_official	5:ac9f6c2c45e8	981	#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
mbed_official	5:ac9f6c2c45e8	982	#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
mbed_official	5:ac9f6c2c45e8	983	#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
mbed_official	5:ac9f6c2c45e8	984	#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
mbed_official	5:ac9f6c2c45e8	985
mbed_official	5:ac9f6c2c45e8	986	/***************** Bit definition for CAN_TI1R register *****************/
mbed_official	5:ac9f6c2c45e8	987	#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /!<Transmit Mailbox Request /
mbed_official	5:ac9f6c2c45e8	988	#define CAN_TI1R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
mbed_official	5:ac9f6c2c45e8	989	#define CAN_TI1R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
mbed_official	5:ac9f6c2c45e8	990	#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /!<Extended Identifier /
mbed_official	5:ac9f6c2c45e8	991	#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
mbed_official	5:ac9f6c2c45e8	992
mbed_official	5:ac9f6c2c45e8	993	/***************** Bit definition for CAN_TDT1R register ****************/
mbed_official	5:ac9f6c2c45e8	994	#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
mbed_official	5:ac9f6c2c45e8	995	#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /!<Transmit Global Time /
mbed_official	5:ac9f6c2c45e8	996	#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
mbed_official	5:ac9f6c2c45e8	997
mbed_official	5:ac9f6c2c45e8	998	/***************** Bit definition for CAN_TDL1R register ****************/
mbed_official	5:ac9f6c2c45e8	999	#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
mbed_official	5:ac9f6c2c45e8	1000	#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
mbed_official	5:ac9f6c2c45e8	1001	#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
mbed_official	5:ac9f6c2c45e8	1002	#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
mbed_official	5:ac9f6c2c45e8	1003
mbed_official	5:ac9f6c2c45e8	1004	/***************** Bit definition for CAN_TDH1R register ****************/
mbed_official	5:ac9f6c2c45e8	1005	#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
mbed_official	5:ac9f6c2c45e8	1006	#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
mbed_official	5:ac9f6c2c45e8	1007	#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
mbed_official	5:ac9f6c2c45e8	1008	#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
mbed_official	5:ac9f6c2c45e8	1009
mbed_official	5:ac9f6c2c45e8	1010	/***************** Bit definition for CAN_TI2R register *****************/
mbed_official	5:ac9f6c2c45e8	1011	#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /!<Transmit Mailbox Request /
mbed_official	5:ac9f6c2c45e8	1012	#define CAN_TI2R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
mbed_official	5:ac9f6c2c45e8	1013	#define CAN_TI2R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
mbed_official	5:ac9f6c2c45e8	1014	#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /!<Extended identifier /
mbed_official	5:ac9f6c2c45e8	1015	#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
mbed_official	5:ac9f6c2c45e8	1016
mbed_official	5:ac9f6c2c45e8	1017	/***************** Bit definition for CAN_TDT2R register ****************/
mbed_official	5:ac9f6c2c45e8	1018	#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
mbed_official	5:ac9f6c2c45e8	1019	#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /!<Transmit Global Time /
mbed_official	5:ac9f6c2c45e8	1020	#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
mbed_official	5:ac9f6c2c45e8	1021
mbed_official	5:ac9f6c2c45e8	1022	/***************** Bit definition for CAN_TDL2R register ****************/
mbed_official	5:ac9f6c2c45e8	1023	#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
mbed_official	5:ac9f6c2c45e8	1024	#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
mbed_official	5:ac9f6c2c45e8	1025	#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
mbed_official	5:ac9f6c2c45e8	1026	#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
mbed_official	5:ac9f6c2c45e8	1027
mbed_official	5:ac9f6c2c45e8	1028	/***************** Bit definition for CAN_TDH2R register ****************/
mbed_official	5:ac9f6c2c45e8	1029	#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
mbed_official	5:ac9f6c2c45e8	1030	#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
mbed_official	5:ac9f6c2c45e8	1031	#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
mbed_official	5:ac9f6c2c45e8	1032	#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
mbed_official	5:ac9f6c2c45e8	1033
mbed_official	5:ac9f6c2c45e8	1034	/***************** Bit definition for CAN_RI0R register *****************/
mbed_official	5:ac9f6c2c45e8	1035	#define CAN_RI0R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
mbed_official	5:ac9f6c2c45e8	1036	#define CAN_RI0R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
mbed_official	5:ac9f6c2c45e8	1037	#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /!<Extended Identifier /
mbed_official	5:ac9f6c2c45e8	1038	#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
mbed_official	5:ac9f6c2c45e8	1039
mbed_official	5:ac9f6c2c45e8	1040	/***************** Bit definition for CAN_RDT0R register ****************/
mbed_official	5:ac9f6c2c45e8	1041	#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
mbed_official	5:ac9f6c2c45e8	1042	#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /!<Filter Match Index /
mbed_official	5:ac9f6c2c45e8	1043	#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
mbed_official	5:ac9f6c2c45e8	1044
mbed_official	5:ac9f6c2c45e8	1045	/***************** Bit definition for CAN_RDL0R register ****************/
mbed_official	5:ac9f6c2c45e8	1046	#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
mbed_official	5:ac9f6c2c45e8	1047	#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
mbed_official	5:ac9f6c2c45e8	1048	#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
mbed_official	5:ac9f6c2c45e8	1049	#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
mbed_official	5:ac9f6c2c45e8	1050
mbed_official	5:ac9f6c2c45e8	1051	/***************** Bit definition for CAN_RDH0R register ****************/
mbed_official	5:ac9f6c2c45e8	1052	#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
mbed_official	5:ac9f6c2c45e8	1053	#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
mbed_official	5:ac9f6c2c45e8	1054	#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
mbed_official	5:ac9f6c2c45e8	1055	#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
mbed_official	5:ac9f6c2c45e8	1056
mbed_official	5:ac9f6c2c45e8	1057	/***************** Bit definition for CAN_RI1R register *****************/
mbed_official	5:ac9f6c2c45e8	1058	#define CAN_RI1R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
mbed_official	5:ac9f6c2c45e8	1059	#define CAN_RI1R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
mbed_official	5:ac9f6c2c45e8	1060	#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /!<Extended identifier /
mbed_official	5:ac9f6c2c45e8	1061	#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
mbed_official	5:ac9f6c2c45e8	1062
mbed_official	5:ac9f6c2c45e8	1063	/***************** Bit definition for CAN_RDT1R register ****************/
mbed_official	5:ac9f6c2c45e8	1064	#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
mbed_official	5:ac9f6c2c45e8	1065	#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /!<Filter Match Index /
mbed_official	5:ac9f6c2c45e8	1066	#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
mbed_official	5:ac9f6c2c45e8	1067
mbed_official	5:ac9f6c2c45e8	1068	/***************** Bit definition for CAN_RDL1R register ****************/
mbed_official	5:ac9f6c2c45e8	1069	#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
mbed_official	5:ac9f6c2c45e8	1070	#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
mbed_official	5:ac9f6c2c45e8	1071	#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
mbed_official	5:ac9f6c2c45e8	1072	#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
mbed_official	5:ac9f6c2c45e8	1073
mbed_official	5:ac9f6c2c45e8	1074	/***************** Bit definition for CAN_RDH1R register ****************/
mbed_official	5:ac9f6c2c45e8	1075	#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
mbed_official	5:ac9f6c2c45e8	1076	#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
mbed_official	5:ac9f6c2c45e8	1077	#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
mbed_official	5:ac9f6c2c45e8	1078	#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
mbed_official	5:ac9f6c2c45e8	1079
mbed_official	5:ac9f6c2c45e8	1080	/!<CAN filter registers /
mbed_official	5:ac9f6c2c45e8	1081	/***************** Bit definition for CAN_FMR register ******************/
mbed_official	5:ac9f6c2c45e8	1082	#define CAN_FMR_FINIT ((uint32_t)0x00000001) /!<Filter Init Mode /
mbed_official	5:ac9f6c2c45e8	1083	#define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /!<CAN2 start bank /
mbed_official	5:ac9f6c2c45e8	1084
mbed_official	5:ac9f6c2c45e8	1085	/***************** Bit definition for CAN_FM1R register *****************/
mbed_official	5:ac9f6c2c45e8	1086	#define CAN_FM1R_FBM ((uint32_t)0x0FFFFFFF) /!<Filter Mode /
mbed_official	5:ac9f6c2c45e8	1087	#define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /!<Filter Init Mode bit 0 /
mbed_official	5:ac9f6c2c45e8	1088	#define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /!<Filter Init Mode bit 1 /
mbed_official	5:ac9f6c2c45e8	1089	#define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /!<Filter Init Mode bit 2 /
mbed_official	5:ac9f6c2c45e8	1090	#define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /!<Filter Init Mode bit 3 /
mbed_official	5:ac9f6c2c45e8	1091	#define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /!<Filter Init Mode bit 4 /
mbed_official	5:ac9f6c2c45e8	1092	#define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /!<Filter Init Mode bit 5 /
mbed_official	5:ac9f6c2c45e8	1093	#define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /!<Filter Init Mode bit 6 /
mbed_official	5:ac9f6c2c45e8	1094	#define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /!<Filter Init Mode bit 7 /
mbed_official	5:ac9f6c2c45e8	1095	#define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /!<Filter Init Mode bit 8 /
mbed_official	5:ac9f6c2c45e8	1096	#define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /!<Filter Init Mode bit 9 /
mbed_official	5:ac9f6c2c45e8	1097	#define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /!<Filter Init Mode bit 10 /
mbed_official	5:ac9f6c2c45e8	1098	#define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /!<Filter Init Mode bit 11 /
mbed_official	5:ac9f6c2c45e8	1099	#define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /!<Filter Init Mode bit 12 /
mbed_official	5:ac9f6c2c45e8	1100	#define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /!<Filter Init Mode bit 13 /
mbed_official	5:ac9f6c2c45e8	1101	#define CAN_FM1R_FBM14 ((uint32_t)0x00004000) /!<Filter Init Mode bit 14 /
mbed_official	5:ac9f6c2c45e8	1102	#define CAN_FM1R_FBM15 ((uint32_t)0x00008000) /!<Filter Init Mode bit 15 /
mbed_official	5:ac9f6c2c45e8	1103	#define CAN_FM1R_FBM16 ((uint32_t)0x00010000) /!<Filter Init Mode bit 16 /
mbed_official	5:ac9f6c2c45e8	1104	#define CAN_FM1R_FBM17 ((uint32_t)0x00020000) /!<Filter Init Mode bit 17 /
mbed_official	5:ac9f6c2c45e8	1105	#define CAN_FM1R_FBM18 ((uint32_t)0x00040000) /!<Filter Init Mode bit 18 /
mbed_official	5:ac9f6c2c45e8	1106	#define CAN_FM1R_FBM19 ((uint32_t)0x00080000) /!<Filter Init Mode bit 19 /
mbed_official	5:ac9f6c2c45e8	1107	#define CAN_FM1R_FBM20 ((uint32_t)0x00100000) /!<Filter Init Mode bit 20 /
mbed_official	5:ac9f6c2c45e8	1108	#define CAN_FM1R_FBM21 ((uint32_t)0x00200000) /!<Filter Init Mode bit 21 /
mbed_official	5:ac9f6c2c45e8	1109	#define CAN_FM1R_FBM22 ((uint32_t)0x00400000) /!<Filter Init Mode bit 22 /
mbed_official	5:ac9f6c2c45e8	1110	#define CAN_FM1R_FBM23 ((uint32_t)0x00800000) /!<Filter Init Mode bit 23 /
mbed_official	5:ac9f6c2c45e8	1111	#define CAN_FM1R_FBM24 ((uint32_t)0x01000000) /!<Filter Init Mode bit 24 /
mbed_official	5:ac9f6c2c45e8	1112	#define CAN_FM1R_FBM25 ((uint32_t)0x02000000) /!<Filter Init Mode bit 25 /
mbed_official	5:ac9f6c2c45e8	1113	#define CAN_FM1R_FBM26 ((uint32_t)0x04000000) /!<Filter Init Mode bit 26 /
mbed_official	5:ac9f6c2c45e8	1114	#define CAN_FM1R_FBM27 ((uint32_t)0x08000000) /!<Filter Init Mode bit 27 /
mbed_official	5:ac9f6c2c45e8	1115
mbed_official	5:ac9f6c2c45e8	1116	/***************** Bit definition for CAN_FS1R register *****************/
mbed_official	5:ac9f6c2c45e8	1117	#define CAN_FS1R_FSC ((uint32_t)0x0FFFFFFF) /!<Filter Scale Configuration /
mbed_official	5:ac9f6c2c45e8	1118	#define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /!<Filter Scale Configuration bit 0 /
mbed_official	5:ac9f6c2c45e8	1119	#define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /!<Filter Scale Configuration bit 1 /
mbed_official	5:ac9f6c2c45e8	1120	#define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /!<Filter Scale Configuration bit 2 /
mbed_official	5:ac9f6c2c45e8	1121	#define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /!<Filter Scale Configuration bit 3 /
mbed_official	5:ac9f6c2c45e8	1122	#define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /!<Filter Scale Configuration bit 4 /
mbed_official	5:ac9f6c2c45e8	1123	#define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /!<Filter Scale Configuration bit 5 /
mbed_official	5:ac9f6c2c45e8	1124	#define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /!<Filter Scale Configuration bit 6 /
mbed_official	5:ac9f6c2c45e8	1125	#define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /!<Filter Scale Configuration bit 7 /
mbed_official	5:ac9f6c2c45e8	1126	#define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /!<Filter Scale Configuration bit 8 /
mbed_official	5:ac9f6c2c45e8	1127	#define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /!<Filter Scale Configuration bit 9 /
mbed_official	5:ac9f6c2c45e8	1128	#define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /!<Filter Scale Configuration bit 10 /
mbed_official	5:ac9f6c2c45e8	1129	#define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /!<Filter Scale Configuration bit 11 /
mbed_official	5:ac9f6c2c45e8	1130	#define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /!<Filter Scale Configuration bit 12 /
mbed_official	5:ac9f6c2c45e8	1131	#define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /!<Filter Scale Configuration bit 13 /
mbed_official	5:ac9f6c2c45e8	1132	#define CAN_FS1R_FSC14 ((uint32_t)0x00004000) /!<Filter Scale Configuration bit 14 /
mbed_official	5:ac9f6c2c45e8	1133	#define CAN_FS1R_FSC15 ((uint32_t)0x00008000) /!<Filter Scale Configuration bit 15 /
mbed_official	5:ac9f6c2c45e8	1134	#define CAN_FS1R_FSC16 ((uint32_t)0x00010000) /!<Filter Scale Configuration bit 16 /
mbed_official	5:ac9f6c2c45e8	1135	#define CAN_FS1R_FSC17 ((uint32_t)0x00020000) /!<Filter Scale Configuration bit 17 /
mbed_official	5:ac9f6c2c45e8	1136	#define CAN_FS1R_FSC18 ((uint32_t)0x00040000) /!<Filter Scale Configuration bit 18 /
mbed_official	5:ac9f6c2c45e8	1137	#define CAN_FS1R_FSC19 ((uint32_t)0x00080000) /!<Filter Scale Configuration bit 19 /
mbed_official	5:ac9f6c2c45e8	1138	#define CAN_FS1R_FSC20 ((uint32_t)0x00100000) /!<Filter Scale Configuration bit 20 /
mbed_official	5:ac9f6c2c45e8	1139	#define CAN_FS1R_FSC21 ((uint32_t)0x00200000) /!<Filter Scale Configuration bit 21 /
mbed_official	5:ac9f6c2c45e8	1140	#define CAN_FS1R_FSC22 ((uint32_t)0x00400000) /!<Filter Scale Configuration bit 22 /
mbed_official	5:ac9f6c2c45e8	1141	#define CAN_FS1R_FSC23 ((uint32_t)0x00800000) /!<Filter Scale Configuration bit 23 /
mbed_official	5:ac9f6c2c45e8	1142	#define CAN_FS1R_FSC24 ((uint32_t)0x01000000) /!<Filter Scale Configuration bit 24 /
mbed_official	5:ac9f6c2c45e8	1143	#define CAN_FS1R_FSC25 ((uint32_t)0x02000000) /!<Filter Scale Configuration bit 25 /
mbed_official	5:ac9f6c2c45e8	1144	#define CAN_FS1R_FSC26 ((uint32_t)0x04000000) /!<Filter Scale Configuration bit 26 /
mbed_official	5:ac9f6c2c45e8	1145	#define CAN_FS1R_FSC27 ((uint32_t)0x08000000) /!<Filter Scale Configuration bit 27 /
mbed_official	5:ac9f6c2c45e8	1146
mbed_official	5:ac9f6c2c45e8	1147	/**************** Bit definition for CAN_FFA1R register *****************/
mbed_official	5:ac9f6c2c45e8	1148	#define CAN_FFA1R_FFA ((uint32_t)0x0FFFFFFF) /!<Filter FIFO Assignment /
mbed_official	5:ac9f6c2c45e8	1149	#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /!<Filter FIFO Assignment bit 0 /
mbed_official	5:ac9f6c2c45e8	1150	#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /!<Filter FIFO Assignment bit 1 /
mbed_official	5:ac9f6c2c45e8	1151	#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /!<Filter FIFO Assignment bit 2 /
mbed_official	5:ac9f6c2c45e8	1152	#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /!<Filter FIFO Assignment bit 3 /
mbed_official	5:ac9f6c2c45e8	1153	#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /!<Filter FIFO Assignment bit 4 /
mbed_official	5:ac9f6c2c45e8	1154	#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /!<Filter FIFO Assignment bit 5 /
mbed_official	5:ac9f6c2c45e8	1155	#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /!<Filter FIFO Assignment bit 6 /
mbed_official	5:ac9f6c2c45e8	1156	#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /!<Filter FIFO Assignment bit 7 /
mbed_official	5:ac9f6c2c45e8	1157	#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /!<Filter FIFO Assignment bit 8 /
mbed_official	5:ac9f6c2c45e8	1158	#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /!<Filter FIFO Assignment bit 9 /
mbed_official	5:ac9f6c2c45e8	1159	#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /!<Filter FIFO Assignment bit 10 /
mbed_official	5:ac9f6c2c45e8	1160	#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /!<Filter FIFO Assignment bit 11 /
mbed_official	5:ac9f6c2c45e8	1161	#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /!<Filter FIFO Assignment bit 12 /
mbed_official	5:ac9f6c2c45e8	1162	#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /!<Filter FIFO Assignment bit 13 /
mbed_official	5:ac9f6c2c45e8	1163	#define CAN_FFA1R_FFA14 ((uint32_t)0x00004000) /!<Filter FIFO Assignment bit 14 /
mbed_official	5:ac9f6c2c45e8	1164	#define CAN_FFA1R_FFA15 ((uint32_t)0x00008000) /!<Filter FIFO Assignment bit 15 /
mbed_official	5:ac9f6c2c45e8	1165	#define CAN_FFA1R_FFA16 ((uint32_t)0x00010000) /!<Filter FIFO Assignment bit 16 /
mbed_official	5:ac9f6c2c45e8	1166	#define CAN_FFA1R_FFA17 ((uint32_t)0x00020000) /!<Filter FIFO Assignment bit 17 /
mbed_official	5:ac9f6c2c45e8	1167	#define CAN_FFA1R_FFA18 ((uint32_t)0x00040000) /!<Filter FIFO Assignment bit 18 /
mbed_official	5:ac9f6c2c45e8	1168	#define CAN_FFA1R_FFA19 ((uint32_t)0x00080000) /!<Filter FIFO Assignment bit 19 /
mbed_official	5:ac9f6c2c45e8	1169	#define CAN_FFA1R_FFA20 ((uint32_t)0x00100000) /!<Filter FIFO Assignment bit 20 /
mbed_official	5:ac9f6c2c45e8	1170	#define CAN_FFA1R_FFA21 ((uint32_t)0x00200000) /!<Filter FIFO Assignment bit 21 /
mbed_official	5:ac9f6c2c45e8	1171	#define CAN_FFA1R_FFA22 ((uint32_t)0x00400000) /!<Filter FIFO Assignment bit 22 /
mbed_official	5:ac9f6c2c45e8	1172	#define CAN_FFA1R_FFA23 ((uint32_t)0x00800000) /!<Filter FIFO Assignment bit 23 /
mbed_official	5:ac9f6c2c45e8	1173	#define CAN_FFA1R_FFA24 ((uint32_t)0x01000000) /!<Filter FIFO Assignment bit 24 /
mbed_official	5:ac9f6c2c45e8	1174	#define CAN_FFA1R_FFA25 ((uint32_t)0x02000000) /!<Filter FIFO Assignment bit 25 /
mbed_official	5:ac9f6c2c45e8	1175	#define CAN_FFA1R_FFA26 ((uint32_t)0x04000000) /!<Filter FIFO Assignment bit 26 /
mbed_official	5:ac9f6c2c45e8	1176	#define CAN_FFA1R_FFA27 ((uint32_t)0x08000000) /!<Filter FIFO Assignment bit 27 /
mbed_official	5:ac9f6c2c45e8	1177
mbed_official	5:ac9f6c2c45e8	1178	/***************** Bit definition for CAN_FA1R register *****************/
mbed_official	5:ac9f6c2c45e8	1179	#define CAN_FA1R_FACT ((uint32_t)0x0FFFFFFF) /!<Filter Active /
mbed_official	5:ac9f6c2c45e8	1180	#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /!<Filter Active bit 0 /
mbed_official	5:ac9f6c2c45e8	1181	#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /!<Filter Active bit 1 /
mbed_official	5:ac9f6c2c45e8	1182	#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /!<Filter Active bit 2 /
mbed_official	5:ac9f6c2c45e8	1183	#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /!<Filter Active bit 3 /
mbed_official	5:ac9f6c2c45e8	1184	#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /!<Filter Active bit 4 /
mbed_official	5:ac9f6c2c45e8	1185	#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /!<Filter Active bit 5 /
mbed_official	5:ac9f6c2c45e8	1186	#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /!<Filter Active bit 6 /
mbed_official	5:ac9f6c2c45e8	1187	#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /!<Filter Active bit 7 /
mbed_official	5:ac9f6c2c45e8	1188	#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /!<Filter Active bit 8 /
mbed_official	5:ac9f6c2c45e8	1189	#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /!<Filter Active bit 9 /
mbed_official	5:ac9f6c2c45e8	1190	#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /!<Filter Active bit 10 /
mbed_official	5:ac9f6c2c45e8	1191	#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /!<Filter Active bit 11 /
mbed_official	5:ac9f6c2c45e8	1192	#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /!<Filter Active bit 12 /
mbed_official	5:ac9f6c2c45e8	1193	#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /!<Filter Active bit 13 /
mbed_official	5:ac9f6c2c45e8	1194	#define CAN_FA1R_FACT14 ((uint32_t)0x00004000) /!<Filter Active bit 14 /
mbed_official	5:ac9f6c2c45e8	1195	#define CAN_FA1R_FACT15 ((uint32_t)0x00008000) /!<Filter Active bit 15 /
mbed_official	5:ac9f6c2c45e8	1196	#define CAN_FA1R_FACT16 ((uint32_t)0x00010000) /!<Filter Active bit 16 /
mbed_official	5:ac9f6c2c45e8	1197	#define CAN_FA1R_FACT17 ((uint32_t)0x00020000) /!<Filter Active bit 17 /
mbed_official	5:ac9f6c2c45e8	1198	#define CAN_FA1R_FACT18 ((uint32_t)0x00040000) /!<Filter Active bit 18 /
mbed_official	5:ac9f6c2c45e8	1199	#define CAN_FA1R_FACT19 ((uint32_t)0x00080000) /!<Filter Active bit 19 /
mbed_official	5:ac9f6c2c45e8	1200	#define CAN_FA1R_FACT20 ((uint32_t)0x00100000) /!<Filter Active bit 20 /
mbed_official	5:ac9f6c2c45e8	1201	#define CAN_FA1R_FACT21 ((uint32_t)0x00200000) /!<Filter Active bit 21 /
mbed_official	5:ac9f6c2c45e8	1202	#define CAN_FA1R_FACT22 ((uint32_t)0x00400000) /!<Filter Active bit 22 /
mbed_official	5:ac9f6c2c45e8	1203	#define CAN_FA1R_FACT23 ((uint32_t)0x00800000) /!<Filter Active bit 23 /
mbed_official	5:ac9f6c2c45e8	1204	#define CAN_FA1R_FACT24 ((uint32_t)0x01000000) /!<Filter Active bit 24 /
mbed_official	5:ac9f6c2c45e8	1205	#define CAN_FA1R_FACT25 ((uint32_t)0x02000000) /!<Filter Active bit 25 /
mbed_official	5:ac9f6c2c45e8	1206	#define CAN_FA1R_FACT26 ((uint32_t)0x04000000) /!<Filter Active bit 26 /
mbed_official	5:ac9f6c2c45e8	1207	#define CAN_FA1R_FACT27 ((uint32_t)0x08000000) /!<Filter Active bit 27 /
mbed_official	5:ac9f6c2c45e8	1208
mbed_official	5:ac9f6c2c45e8	1209	/***************** Bit definition for CAN_F0R1 register *****************/
mbed_official	5:ac9f6c2c45e8	1210	#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
mbed_official	5:ac9f6c2c45e8	1211	#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
mbed_official	5:ac9f6c2c45e8	1212	#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
mbed_official	5:ac9f6c2c45e8	1213	#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
mbed_official	5:ac9f6c2c45e8	1214	#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
mbed_official	5:ac9f6c2c45e8	1215	#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
mbed_official	5:ac9f6c2c45e8	1216	#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
mbed_official	5:ac9f6c2c45e8	1217	#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
mbed_official	5:ac9f6c2c45e8	1218	#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
mbed_official	5:ac9f6c2c45e8	1219	#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
mbed_official	5:ac9f6c2c45e8	1220	#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
mbed_official	5:ac9f6c2c45e8	1221	#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
mbed_official	5:ac9f6c2c45e8	1222	#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
mbed_official	5:ac9f6c2c45e8	1223	#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
mbed_official	5:ac9f6c2c45e8	1224	#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
mbed_official	5:ac9f6c2c45e8	1225	#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
mbed_official	5:ac9f6c2c45e8	1226	#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
mbed_official	5:ac9f6c2c45e8	1227	#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
mbed_official	5:ac9f6c2c45e8	1228	#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
mbed_official	5:ac9f6c2c45e8	1229	#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
mbed_official	5:ac9f6c2c45e8	1230	#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
mbed_official	5:ac9f6c2c45e8	1231	#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
mbed_official	5:ac9f6c2c45e8	1232	#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
mbed_official	5:ac9f6c2c45e8	1233	#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
mbed_official	5:ac9f6c2c45e8	1234	#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
mbed_official	5:ac9f6c2c45e8	1235	#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
mbed_official	5:ac9f6c2c45e8	1236	#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
mbed_official	5:ac9f6c2c45e8	1237	#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
mbed_official	5:ac9f6c2c45e8	1238	#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
mbed_official	5:ac9f6c2c45e8	1239	#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
mbed_official	5:ac9f6c2c45e8	1240	#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
mbed_official	5:ac9f6c2c45e8	1241	#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
mbed_official	5:ac9f6c2c45e8	1242
mbed_official	5:ac9f6c2c45e8	1243	/***************** Bit definition for CAN_F1R1 register *****************/
mbed_official	5:ac9f6c2c45e8	1244	#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
mbed_official	5:ac9f6c2c45e8	1245	#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
mbed_official	5:ac9f6c2c45e8	1246	#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
mbed_official	5:ac9f6c2c45e8	1247	#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
mbed_official	5:ac9f6c2c45e8	1248	#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
mbed_official	5:ac9f6c2c45e8	1249	#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
mbed_official	5:ac9f6c2c45e8	1250	#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
mbed_official	5:ac9f6c2c45e8	1251	#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
mbed_official	5:ac9f6c2c45e8	1252	#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
mbed_official	5:ac9f6c2c45e8	1253	#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
mbed_official	5:ac9f6c2c45e8	1254	#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
mbed_official	5:ac9f6c2c45e8	1255	#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
mbed_official	5:ac9f6c2c45e8	1256	#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
mbed_official	5:ac9f6c2c45e8	1257	#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
mbed_official	5:ac9f6c2c45e8	1258	#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
mbed_official	5:ac9f6c2c45e8	1259	#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
mbed_official	5:ac9f6c2c45e8	1260	#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
mbed_official	5:ac9f6c2c45e8	1261	#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
mbed_official	5:ac9f6c2c45e8	1262	#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
mbed_official	5:ac9f6c2c45e8	1263	#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
mbed_official	5:ac9f6c2c45e8	1264	#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
mbed_official	5:ac9f6c2c45e8	1265	#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
mbed_official	5:ac9f6c2c45e8	1266	#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
mbed_official	5:ac9f6c2c45e8	1267	#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
mbed_official	5:ac9f6c2c45e8	1268	#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
mbed_official	5:ac9f6c2c45e8	1269	#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
mbed_official	5:ac9f6c2c45e8	1270	#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
mbed_official	5:ac9f6c2c45e8	1271	#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
mbed_official	5:ac9f6c2c45e8	1272	#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
mbed_official	5:ac9f6c2c45e8	1273	#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
mbed_official	5:ac9f6c2c45e8	1274	#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
mbed_official	5:ac9f6c2c45e8	1275	#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
mbed_official	5:ac9f6c2c45e8	1276
mbed_official	5:ac9f6c2c45e8	1277	/***************** Bit definition for CAN_F2R1 register *****************/
mbed_official	5:ac9f6c2c45e8	1278	#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
mbed_official	5:ac9f6c2c45e8	1279	#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
mbed_official	5:ac9f6c2c45e8	1280	#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
mbed_official	5:ac9f6c2c45e8	1281	#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
mbed_official	5:ac9f6c2c45e8	1282	#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
mbed_official	5:ac9f6c2c45e8	1283	#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
mbed_official	5:ac9f6c2c45e8	1284	#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
mbed_official	5:ac9f6c2c45e8	1285	#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
mbed_official	5:ac9f6c2c45e8	1286	#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
mbed_official	5:ac9f6c2c45e8	1287	#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
mbed_official	5:ac9f6c2c45e8	1288	#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
mbed_official	5:ac9f6c2c45e8	1289	#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
mbed_official	5:ac9f6c2c45e8	1290	#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
mbed_official	5:ac9f6c2c45e8	1291	#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
mbed_official	5:ac9f6c2c45e8	1292	#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
mbed_official	5:ac9f6c2c45e8	1293	#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
mbed_official	5:ac9f6c2c45e8	1294	#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
mbed_official	5:ac9f6c2c45e8	1295	#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
mbed_official	5:ac9f6c2c45e8	1296	#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
mbed_official	5:ac9f6c2c45e8	1297	#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
mbed_official	5:ac9f6c2c45e8	1298	#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
mbed_official	5:ac9f6c2c45e8	1299	#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
mbed_official	5:ac9f6c2c45e8	1300	#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
mbed_official	5:ac9f6c2c45e8	1301	#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
mbed_official	5:ac9f6c2c45e8	1302	#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
mbed_official	5:ac9f6c2c45e8	1303	#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
mbed_official	5:ac9f6c2c45e8	1304	#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
mbed_official	5:ac9f6c2c45e8	1305	#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
mbed_official	5:ac9f6c2c45e8	1306	#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
mbed_official	5:ac9f6c2c45e8	1307	#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
mbed_official	5:ac9f6c2c45e8	1308	#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
mbed_official	5:ac9f6c2c45e8	1309	#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
mbed_official	5:ac9f6c2c45e8	1310
mbed_official	5:ac9f6c2c45e8	1311	/***************** Bit definition for CAN_F3R1 register *****************/
mbed_official	5:ac9f6c2c45e8	1312	#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
mbed_official	5:ac9f6c2c45e8	1313	#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
mbed_official	5:ac9f6c2c45e8	1314	#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
mbed_official	5:ac9f6c2c45e8	1315	#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
mbed_official	5:ac9f6c2c45e8	1316	#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
mbed_official	5:ac9f6c2c45e8	1317	#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
mbed_official	5:ac9f6c2c45e8	1318	#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
mbed_official	5:ac9f6c2c45e8	1319	#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
mbed_official	5:ac9f6c2c45e8	1320	#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
mbed_official	5:ac9f6c2c45e8	1321	#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
mbed_official	5:ac9f6c2c45e8	1322	#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
mbed_official	5:ac9f6c2c45e8	1323	#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
mbed_official	5:ac9f6c2c45e8	1324	#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
mbed_official	5:ac9f6c2c45e8	1325	#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
mbed_official	5:ac9f6c2c45e8	1326	#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
mbed_official	5:ac9f6c2c45e8	1327	#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
mbed_official	5:ac9f6c2c45e8	1328	#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
mbed_official	5:ac9f6c2c45e8	1329	#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
mbed_official	5:ac9f6c2c45e8	1330	#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
mbed_official	5:ac9f6c2c45e8	1331	#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
mbed_official	5:ac9f6c2c45e8	1332	#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
mbed_official	5:ac9f6c2c45e8	1333	#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
mbed_official	5:ac9f6c2c45e8	1334	#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
mbed_official	5:ac9f6c2c45e8	1335	#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
mbed_official	5:ac9f6c2c45e8	1336	#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
mbed_official	5:ac9f6c2c45e8	1337	#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
mbed_official	5:ac9f6c2c45e8	1338	#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
mbed_official	5:ac9f6c2c45e8	1339	#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
mbed_official	5:ac9f6c2c45e8	1340	#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
mbed_official	5:ac9f6c2c45e8	1341	#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
mbed_official	5:ac9f6c2c45e8	1342	#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
mbed_official	5:ac9f6c2c45e8	1343	#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
mbed_official	5:ac9f6c2c45e8	1344
mbed_official	5:ac9f6c2c45e8	1345	/***************** Bit definition for CAN_F4R1 register *****************/
mbed_official	5:ac9f6c2c45e8	1346	#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
mbed_official	5:ac9f6c2c45e8	1347	#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
mbed_official	5:ac9f6c2c45e8	1348	#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
mbed_official	5:ac9f6c2c45e8	1349	#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
mbed_official	5:ac9f6c2c45e8	1350	#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
mbed_official	5:ac9f6c2c45e8	1351	#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
mbed_official	5:ac9f6c2c45e8	1352	#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
mbed_official	5:ac9f6c2c45e8	1353	#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
mbed_official	5:ac9f6c2c45e8	1354	#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
mbed_official	5:ac9f6c2c45e8	1355	#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
mbed_official	5:ac9f6c2c45e8	1356	#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
mbed_official	5:ac9f6c2c45e8	1357	#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
mbed_official	5:ac9f6c2c45e8	1358	#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
mbed_official	5:ac9f6c2c45e8	1359	#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
mbed_official	5:ac9f6c2c45e8	1360	#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
mbed_official	5:ac9f6c2c45e8	1361	#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
mbed_official	5:ac9f6c2c45e8	1362	#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
mbed_official	5:ac9f6c2c45e8	1363	#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
mbed_official	5:ac9f6c2c45e8	1364	#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
mbed_official	5:ac9f6c2c45e8	1365	#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
mbed_official	5:ac9f6c2c45e8	1366	#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
mbed_official	5:ac9f6c2c45e8	1367	#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
mbed_official	5:ac9f6c2c45e8	1368	#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
mbed_official	5:ac9f6c2c45e8	1369	#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
mbed_official	5:ac9f6c2c45e8	1370	#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
mbed_official	5:ac9f6c2c45e8	1371	#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
mbed_official	5:ac9f6c2c45e8	1372	#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
mbed_official	5:ac9f6c2c45e8	1373	#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
mbed_official	5:ac9f6c2c45e8	1374	#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
mbed_official	5:ac9f6c2c45e8	1375	#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
mbed_official	5:ac9f6c2c45e8	1376	#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
mbed_official	5:ac9f6c2c45e8	1377	#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
mbed_official	5:ac9f6c2c45e8	1378
mbed_official	5:ac9f6c2c45e8	1379	/***************** Bit definition for CAN_F5R1 register *****************/
mbed_official	5:ac9f6c2c45e8	1380	#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
mbed_official	5:ac9f6c2c45e8	1381	#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
mbed_official	5:ac9f6c2c45e8	1382	#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
mbed_official	5:ac9f6c2c45e8	1383	#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
mbed_official	5:ac9f6c2c45e8	1384	#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
mbed_official	5:ac9f6c2c45e8	1385	#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
mbed_official	5:ac9f6c2c45e8	1386	#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
mbed_official	5:ac9f6c2c45e8	1387	#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
mbed_official	5:ac9f6c2c45e8	1388	#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
mbed_official	5:ac9f6c2c45e8	1389	#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
mbed_official	5:ac9f6c2c45e8	1390	#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
mbed_official	5:ac9f6c2c45e8	1391	#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
mbed_official	5:ac9f6c2c45e8	1392	#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
mbed_official	5:ac9f6c2c45e8	1393	#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
mbed_official	5:ac9f6c2c45e8	1394	#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
mbed_official	5:ac9f6c2c45e8	1395	#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
mbed_official	5:ac9f6c2c45e8	1396	#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
mbed_official	5:ac9f6c2c45e8	1397	#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
mbed_official	5:ac9f6c2c45e8	1398	#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
mbed_official	5:ac9f6c2c45e8	1399	#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
mbed_official	5:ac9f6c2c45e8	1400	#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
mbed_official	5:ac9f6c2c45e8	1401	#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
mbed_official	5:ac9f6c2c45e8	1402	#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
mbed_official	5:ac9f6c2c45e8	1403	#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
mbed_official	5:ac9f6c2c45e8	1404	#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
mbed_official	5:ac9f6c2c45e8	1405	#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
mbed_official	5:ac9f6c2c45e8	1406	#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
mbed_official	5:ac9f6c2c45e8	1407	#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
mbed_official	5:ac9f6c2c45e8	1408	#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
mbed_official	5:ac9f6c2c45e8	1409	#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
mbed_official	5:ac9f6c2c45e8	1410	#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
mbed_official	5:ac9f6c2c45e8	1411	#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
mbed_official	5:ac9f6c2c45e8	1412
mbed_official	5:ac9f6c2c45e8	1413	/***************** Bit definition for CAN_F6R1 register *****************/
mbed_official	5:ac9f6c2c45e8	1414	#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
mbed_official	5:ac9f6c2c45e8	1415	#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
mbed_official	5:ac9f6c2c45e8	1416	#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
mbed_official	5:ac9f6c2c45e8	1417	#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
mbed_official	5:ac9f6c2c45e8	1418	#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
mbed_official	5:ac9f6c2c45e8	1419	#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
mbed_official	5:ac9f6c2c45e8	1420	#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
mbed_official	5:ac9f6c2c45e8	1421	#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
mbed_official	5:ac9f6c2c45e8	1422	#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
mbed_official	5:ac9f6c2c45e8	1423	#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
mbed_official	5:ac9f6c2c45e8	1424	#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
mbed_official	5:ac9f6c2c45e8	1425	#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
mbed_official	5:ac9f6c2c45e8	1426	#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
mbed_official	5:ac9f6c2c45e8	1427	#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
mbed_official	5:ac9f6c2c45e8	1428	#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
mbed_official	5:ac9f6c2c45e8	1429	#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
mbed_official	5:ac9f6c2c45e8	1430	#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
mbed_official	5:ac9f6c2c45e8	1431	#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
mbed_official	5:ac9f6c2c45e8	1432	#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
mbed_official	5:ac9f6c2c45e8	1433	#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
mbed_official	5:ac9f6c2c45e8	1434	#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
mbed_official	5:ac9f6c2c45e8	1435	#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
mbed_official	5:ac9f6c2c45e8	1436	#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
mbed_official	5:ac9f6c2c45e8	1437	#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
mbed_official	5:ac9f6c2c45e8	1438	#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
mbed_official	5:ac9f6c2c45e8	1439	#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
mbed_official	5:ac9f6c2c45e8	1440	#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
mbed_official	5:ac9f6c2c45e8	1441	#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
mbed_official	5:ac9f6c2c45e8	1442	#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
mbed_official	5:ac9f6c2c45e8	1443	#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
mbed_official	5:ac9f6c2c45e8	1444	#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
mbed_official	5:ac9f6c2c45e8	1445	#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
mbed_official	5:ac9f6c2c45e8	1446
mbed_official	5:ac9f6c2c45e8	1447	/***************** Bit definition for CAN_F7R1 register *****************/
mbed_official	5:ac9f6c2c45e8	1448	#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
mbed_official	5:ac9f6c2c45e8	1449	#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
mbed_official	5:ac9f6c2c45e8	1450	#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
mbed_official	5:ac9f6c2c45e8	1451	#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
mbed_official	5:ac9f6c2c45e8	1452	#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
mbed_official	5:ac9f6c2c45e8	1453	#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
mbed_official	5:ac9f6c2c45e8	1454	#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
mbed_official	5:ac9f6c2c45e8	1455	#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
mbed_official	5:ac9f6c2c45e8	1456	#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
mbed_official	5:ac9f6c2c45e8	1457	#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
mbed_official	5:ac9f6c2c45e8	1458	#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
mbed_official	5:ac9f6c2c45e8	1459	#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
mbed_official	5:ac9f6c2c45e8	1460	#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
mbed_official	5:ac9f6c2c45e8	1461	#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
mbed_official	5:ac9f6c2c45e8	1462	#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
mbed_official	5:ac9f6c2c45e8	1463	#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
mbed_official	5:ac9f6c2c45e8	1464	#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
mbed_official	5:ac9f6c2c45e8	1465	#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
mbed_official	5:ac9f6c2c45e8	1466	#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
mbed_official	5:ac9f6c2c45e8	1467	#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
mbed_official	5:ac9f6c2c45e8	1468	#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
mbed_official	5:ac9f6c2c45e8	1469	#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
mbed_official	5:ac9f6c2c45e8	1470	#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
mbed_official	5:ac9f6c2c45e8	1471	#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
mbed_official	5:ac9f6c2c45e8	1472	#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
mbed_official	5:ac9f6c2c45e8	1473	#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
mbed_official	5:ac9f6c2c45e8	1474	#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
mbed_official	5:ac9f6c2c45e8	1475	#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
mbed_official	5:ac9f6c2c45e8	1476	#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
mbed_official	5:ac9f6c2c45e8	1477	#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
mbed_official	5:ac9f6c2c45e8	1478	#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
mbed_official	5:ac9f6c2c45e8	1479	#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
mbed_official	5:ac9f6c2c45e8	1480
mbed_official	5:ac9f6c2c45e8	1481	/***************** Bit definition for CAN_F8R1 register *****************/
mbed_official	5:ac9f6c2c45e8	1482	#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
mbed_official	5:ac9f6c2c45e8	1483	#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
mbed_official	5:ac9f6c2c45e8	1484	#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
mbed_official	5:ac9f6c2c45e8	1485	#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
mbed_official	5:ac9f6c2c45e8	1486	#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
mbed_official	5:ac9f6c2c45e8	1487	#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
mbed_official	5:ac9f6c2c45e8	1488	#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
mbed_official	5:ac9f6c2c45e8	1489	#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
mbed_official	5:ac9f6c2c45e8	1490	#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
mbed_official	5:ac9f6c2c45e8	1491	#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
mbed_official	5:ac9f6c2c45e8	1492	#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
mbed_official	5:ac9f6c2c45e8	1493	#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
mbed_official	5:ac9f6c2c45e8	1494	#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
mbed_official	5:ac9f6c2c45e8	1495	#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
mbed_official	5:ac9f6c2c45e8	1496	#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
mbed_official	5:ac9f6c2c45e8	1497	#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
mbed_official	5:ac9f6c2c45e8	1498	#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
mbed_official	5:ac9f6c2c45e8	1499	#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
mbed_official	5:ac9f6c2c45e8	1500	#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
mbed_official	5:ac9f6c2c45e8	1501	#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
mbed_official	5:ac9f6c2c45e8	1502	#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
mbed_official	5:ac9f6c2c45e8	1503	#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
mbed_official	5:ac9f6c2c45e8	1504	#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
mbed_official	5:ac9f6c2c45e8	1505	#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
mbed_official	5:ac9f6c2c45e8	1506	#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
mbed_official	5:ac9f6c2c45e8	1507	#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
mbed_official	5:ac9f6c2c45e8	1508	#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
mbed_official	5:ac9f6c2c45e8	1509	#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
mbed_official	5:ac9f6c2c45e8	1510	#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
mbed_official	5:ac9f6c2c45e8	1511	#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
mbed_official	5:ac9f6c2c45e8	1512	#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
mbed_official	5:ac9f6c2c45e8	1513	#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
mbed_official	5:ac9f6c2c45e8	1514
mbed_official	5:ac9f6c2c45e8	1515	/***************** Bit definition for CAN_F9R1 register *****************/
mbed_official	5:ac9f6c2c45e8	1516	#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
mbed_official	5:ac9f6c2c45e8	1517	#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
mbed_official	5:ac9f6c2c45e8	1518	#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
mbed_official	5:ac9f6c2c45e8	1519	#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
mbed_official	5:ac9f6c2c45e8	1520	#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
mbed_official	5:ac9f6c2c45e8	1521	#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
mbed_official	5:ac9f6c2c45e8	1522	#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
mbed_official	5:ac9f6c2c45e8	1523	#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
mbed_official	5:ac9f6c2c45e8	1524	#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
mbed_official	5:ac9f6c2c45e8	1525	#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
mbed_official	5:ac9f6c2c45e8	1526	#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
mbed_official	5:ac9f6c2c45e8	1527	#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
mbed_official	5:ac9f6c2c45e8	1528	#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
mbed_official	5:ac9f6c2c45e8	1529	#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
mbed_official	5:ac9f6c2c45e8	1530	#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
mbed_official	5:ac9f6c2c45e8	1531	#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
mbed_official	5:ac9f6c2c45e8	1532	#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
mbed_official	5:ac9f6c2c45e8	1533	#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
mbed_official	5:ac9f6c2c45e8	1534	#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
mbed_official	5:ac9f6c2c45e8	1535	#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
mbed_official	5:ac9f6c2c45e8	1536	#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
mbed_official	5:ac9f6c2c45e8	1537	#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
mbed_official	5:ac9f6c2c45e8	1538	#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
mbed_official	5:ac9f6c2c45e8	1539	#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
mbed_official	5:ac9f6c2c45e8	1540	#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
mbed_official	5:ac9f6c2c45e8	1541	#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
mbed_official	5:ac9f6c2c45e8	1542	#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
mbed_official	5:ac9f6c2c45e8	1543	#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
mbed_official	5:ac9f6c2c45e8	1544	#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
mbed_official	5:ac9f6c2c45e8	1545	#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
mbed_official	5:ac9f6c2c45e8	1546	#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
mbed_official	5:ac9f6c2c45e8	1547	#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
mbed_official	5:ac9f6c2c45e8	1548
mbed_official	5:ac9f6c2c45e8	1549	/***************** Bit definition for CAN_F10R1 register ****************/
mbed_official	5:ac9f6c2c45e8	1550	#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
mbed_official	5:ac9f6c2c45e8	1551	#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
mbed_official	5:ac9f6c2c45e8	1552	#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
mbed_official	5:ac9f6c2c45e8	1553	#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
mbed_official	5:ac9f6c2c45e8	1554	#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
mbed_official	5:ac9f6c2c45e8	1555	#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
mbed_official	5:ac9f6c2c45e8	1556	#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
mbed_official	5:ac9f6c2c45e8	1557	#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
mbed_official	5:ac9f6c2c45e8	1558	#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
mbed_official	5:ac9f6c2c45e8	1559	#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
mbed_official	5:ac9f6c2c45e8	1560	#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
mbed_official	5:ac9f6c2c45e8	1561	#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
mbed_official	5:ac9f6c2c45e8	1562	#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
mbed_official	5:ac9f6c2c45e8	1563	#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
mbed_official	5:ac9f6c2c45e8	1564	#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
mbed_official	5:ac9f6c2c45e8	1565	#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
mbed_official	5:ac9f6c2c45e8	1566	#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
mbed_official	5:ac9f6c2c45e8	1567	#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
mbed_official	5:ac9f6c2c45e8	1568	#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
mbed_official	5:ac9f6c2c45e8	1569	#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
mbed_official	5:ac9f6c2c45e8	1570	#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
mbed_official	5:ac9f6c2c45e8	1571	#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
mbed_official	5:ac9f6c2c45e8	1572	#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
mbed_official	5:ac9f6c2c45e8	1573	#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
mbed_official	5:ac9f6c2c45e8	1574	#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
mbed_official	5:ac9f6c2c45e8	1575	#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
mbed_official	5:ac9f6c2c45e8	1576	#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
mbed_official	5:ac9f6c2c45e8	1577	#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
mbed_official	5:ac9f6c2c45e8	1578	#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
mbed_official	5:ac9f6c2c45e8	1579	#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
mbed_official	5:ac9f6c2c45e8	1580	#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
mbed_official	5:ac9f6c2c45e8	1581	#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
mbed_official	5:ac9f6c2c45e8	1582
mbed_official	5:ac9f6c2c45e8	1583	/***************** Bit definition for CAN_F11R1 register ****************/
mbed_official	5:ac9f6c2c45e8	1584	#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
mbed_official	5:ac9f6c2c45e8	1585	#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
mbed_official	5:ac9f6c2c45e8	1586	#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
mbed_official	5:ac9f6c2c45e8	1587	#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
mbed_official	5:ac9f6c2c45e8	1588	#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
mbed_official	5:ac9f6c2c45e8	1589	#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
mbed_official	5:ac9f6c2c45e8	1590	#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
mbed_official	5:ac9f6c2c45e8	1591	#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
mbed_official	5:ac9f6c2c45e8	1592	#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
mbed_official	5:ac9f6c2c45e8	1593	#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
mbed_official	5:ac9f6c2c45e8	1594	#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
mbed_official	5:ac9f6c2c45e8	1595	#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
mbed_official	5:ac9f6c2c45e8	1596	#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
mbed_official	5:ac9f6c2c45e8	1597	#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
mbed_official	5:ac9f6c2c45e8	1598	#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
mbed_official	5:ac9f6c2c45e8	1599	#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
mbed_official	5:ac9f6c2c45e8	1600	#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
mbed_official	5:ac9f6c2c45e8	1601	#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
mbed_official	5:ac9f6c2c45e8	1602	#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
mbed_official	5:ac9f6c2c45e8	1603	#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
mbed_official	5:ac9f6c2c45e8	1604	#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
mbed_official	5:ac9f6c2c45e8	1605	#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
mbed_official	5:ac9f6c2c45e8	1606	#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
mbed_official	5:ac9f6c2c45e8	1607	#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
mbed_official	5:ac9f6c2c45e8	1608	#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
mbed_official	5:ac9f6c2c45e8	1609	#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
mbed_official	5:ac9f6c2c45e8	1610	#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
mbed_official	5:ac9f6c2c45e8	1611	#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
mbed_official	5:ac9f6c2c45e8	1612	#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
mbed_official	5:ac9f6c2c45e8	1613	#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
mbed_official	5:ac9f6c2c45e8	1614	#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
mbed_official	5:ac9f6c2c45e8	1615	#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
mbed_official	5:ac9f6c2c45e8	1616
mbed_official	5:ac9f6c2c45e8	1617	/***************** Bit definition for CAN_F12R1 register ****************/
mbed_official	5:ac9f6c2c45e8	1618	#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
mbed_official	5:ac9f6c2c45e8	1619	#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
mbed_official	5:ac9f6c2c45e8	1620	#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
mbed_official	5:ac9f6c2c45e8	1621	#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
mbed_official	5:ac9f6c2c45e8	1622	#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
mbed_official	5:ac9f6c2c45e8	1623	#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
mbed_official	5:ac9f6c2c45e8	1624	#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
mbed_official	5:ac9f6c2c45e8	1625	#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
mbed_official	5:ac9f6c2c45e8	1626	#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
mbed_official	5:ac9f6c2c45e8	1627	#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
mbed_official	5:ac9f6c2c45e8	1628	#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
mbed_official	5:ac9f6c2c45e8	1629	#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
mbed_official	5:ac9f6c2c45e8	1630	#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
mbed_official	5:ac9f6c2c45e8	1631	#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
mbed_official	5:ac9f6c2c45e8	1632	#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
mbed_official	5:ac9f6c2c45e8	1633	#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
mbed_official	5:ac9f6c2c45e8	1634	#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
mbed_official	5:ac9f6c2c45e8	1635	#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
mbed_official	5:ac9f6c2c45e8	1636	#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
mbed_official	5:ac9f6c2c45e8	1637	#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
mbed_official	5:ac9f6c2c45e8	1638	#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
mbed_official	5:ac9f6c2c45e8	1639	#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
mbed_official	5:ac9f6c2c45e8	1640	#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
mbed_official	5:ac9f6c2c45e8	1641	#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
mbed_official	5:ac9f6c2c45e8	1642	#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
mbed_official	5:ac9f6c2c45e8	1643	#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
mbed_official	5:ac9f6c2c45e8	1644	#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
mbed_official	5:ac9f6c2c45e8	1645	#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
mbed_official	5:ac9f6c2c45e8	1646	#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
mbed_official	5:ac9f6c2c45e8	1647	#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
mbed_official	5:ac9f6c2c45e8	1648	#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
mbed_official	5:ac9f6c2c45e8	1649	#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
mbed_official	5:ac9f6c2c45e8	1650
mbed_official	5:ac9f6c2c45e8	1651	/***************** Bit definition for CAN_F13R1 register ****************/
mbed_official	5:ac9f6c2c45e8	1652	#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
mbed_official	5:ac9f6c2c45e8	1653	#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
mbed_official	5:ac9f6c2c45e8	1654	#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
mbed_official	5:ac9f6c2c45e8	1655	#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
mbed_official	5:ac9f6c2c45e8	1656	#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
mbed_official	5:ac9f6c2c45e8	1657	#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
mbed_official	5:ac9f6c2c45e8	1658	#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
mbed_official	5:ac9f6c2c45e8	1659	#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
mbed_official	5:ac9f6c2c45e8	1660	#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
mbed_official	5:ac9f6c2c45e8	1661	#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
mbed_official	5:ac9f6c2c45e8	1662	#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
mbed_official	5:ac9f6c2c45e8	1663	#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
mbed_official	5:ac9f6c2c45e8	1664	#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
mbed_official	5:ac9f6c2c45e8	1665	#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
mbed_official	5:ac9f6c2c45e8	1666	#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
mbed_official	5:ac9f6c2c45e8	1667	#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
mbed_official	5:ac9f6c2c45e8	1668	#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
mbed_official	5:ac9f6c2c45e8	1669	#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
mbed_official	5:ac9f6c2c45e8	1670	#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
mbed_official	5:ac9f6c2c45e8	1671	#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
mbed_official	5:ac9f6c2c45e8	1672	#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
mbed_official	5:ac9f6c2c45e8	1673	#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
mbed_official	5:ac9f6c2c45e8	1674	#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
mbed_official	5:ac9f6c2c45e8	1675	#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
mbed_official	5:ac9f6c2c45e8	1676	#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
mbed_official	5:ac9f6c2c45e8	1677	#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
mbed_official	5:ac9f6c2c45e8	1678	#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
mbed_official	5:ac9f6c2c45e8	1679	#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
mbed_official	5:ac9f6c2c45e8	1680	#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
mbed_official	5:ac9f6c2c45e8	1681	#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
mbed_official	5:ac9f6c2c45e8	1682	#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
mbed_official	5:ac9f6c2c45e8	1683	#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
mbed_official	5:ac9f6c2c45e8	1684
mbed_official	5:ac9f6c2c45e8	1685	/***************** Bit definition for CAN_F0R2 register *****************/
mbed_official	5:ac9f6c2c45e8	1686	#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
mbed_official	5:ac9f6c2c45e8	1687	#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
mbed_official	5:ac9f6c2c45e8	1688	#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
mbed_official	5:ac9f6c2c45e8	1689	#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
mbed_official	5:ac9f6c2c45e8	1690	#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
mbed_official	5:ac9f6c2c45e8	1691	#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
mbed_official	5:ac9f6c2c45e8	1692	#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
mbed_official	5:ac9f6c2c45e8	1693	#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
mbed_official	5:ac9f6c2c45e8	1694	#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
mbed_official	5:ac9f6c2c45e8	1695	#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
mbed_official	5:ac9f6c2c45e8	1696	#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
mbed_official	5:ac9f6c2c45e8	1697	#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
mbed_official	5:ac9f6c2c45e8	1698	#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
mbed_official	5:ac9f6c2c45e8	1699	#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
mbed_official	5:ac9f6c2c45e8	1700	#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
mbed_official	5:ac9f6c2c45e8	1701	#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
mbed_official	5:ac9f6c2c45e8	1702	#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
mbed_official	5:ac9f6c2c45e8	1703	#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
mbed_official	5:ac9f6c2c45e8	1704	#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
mbed_official	5:ac9f6c2c45e8	1705	#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
mbed_official	5:ac9f6c2c45e8	1706	#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
mbed_official	5:ac9f6c2c45e8	1707	#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
mbed_official	5:ac9f6c2c45e8	1708	#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
mbed_official	5:ac9f6c2c45e8	1709	#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
mbed_official	5:ac9f6c2c45e8	1710	#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
mbed_official	5:ac9f6c2c45e8	1711	#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
mbed_official	5:ac9f6c2c45e8	1712	#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
mbed_official	5:ac9f6c2c45e8	1713	#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
mbed_official	5:ac9f6c2c45e8	1714	#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
mbed_official	5:ac9f6c2c45e8	1715	#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
mbed_official	5:ac9f6c2c45e8	1716	#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
mbed_official	5:ac9f6c2c45e8	1717	#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
mbed_official	5:ac9f6c2c45e8	1718
mbed_official	5:ac9f6c2c45e8	1719	/***************** Bit definition for CAN_F1R2 register *****************/
mbed_official	5:ac9f6c2c45e8	1720	#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
mbed_official	5:ac9f6c2c45e8	1721	#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
mbed_official	5:ac9f6c2c45e8	1722	#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
mbed_official	5:ac9f6c2c45e8	1723	#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
mbed_official	5:ac9f6c2c45e8	1724	#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
mbed_official	5:ac9f6c2c45e8	1725	#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
mbed_official	5:ac9f6c2c45e8	1726	#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
mbed_official	5:ac9f6c2c45e8	1727	#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
mbed_official	5:ac9f6c2c45e8	1728	#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
mbed_official	5:ac9f6c2c45e8	1729	#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
mbed_official	5:ac9f6c2c45e8	1730	#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
mbed_official	5:ac9f6c2c45e8	1731	#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
mbed_official	5:ac9f6c2c45e8	1732	#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
mbed_official	5:ac9f6c2c45e8	1733	#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
mbed_official	5:ac9f6c2c45e8	1734	#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
mbed_official	5:ac9f6c2c45e8	1735	#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
mbed_official	5:ac9f6c2c45e8	1736	#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
mbed_official	5:ac9f6c2c45e8	1737	#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
mbed_official	5:ac9f6c2c45e8	1738	#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
mbed_official	5:ac9f6c2c45e8	1739	#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
mbed_official	5:ac9f6c2c45e8	1740	#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
mbed_official	5:ac9f6c2c45e8	1741	#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
mbed_official	5:ac9f6c2c45e8	1742	#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
mbed_official	5:ac9f6c2c45e8	1743	#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
mbed_official	5:ac9f6c2c45e8	1744	#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
mbed_official	5:ac9f6c2c45e8	1745	#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
mbed_official	5:ac9f6c2c45e8	1746	#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
mbed_official	5:ac9f6c2c45e8	1747	#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
mbed_official	5:ac9f6c2c45e8	1748	#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
mbed_official	5:ac9f6c2c45e8	1749	#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
mbed_official	5:ac9f6c2c45e8	1750	#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
mbed_official	5:ac9f6c2c45e8	1751	#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
mbed_official	5:ac9f6c2c45e8	1752
mbed_official	5:ac9f6c2c45e8	1753	/***************** Bit definition for CAN_F2R2 register *****************/
mbed_official	5:ac9f6c2c45e8	1754	#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
mbed_official	5:ac9f6c2c45e8	1755	#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
mbed_official	5:ac9f6c2c45e8	1756	#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
mbed_official	5:ac9f6c2c45e8	1757	#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
mbed_official	5:ac9f6c2c45e8	1758	#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
mbed_official	5:ac9f6c2c45e8	1759	#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
mbed_official	5:ac9f6c2c45e8	1760	#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
mbed_official	5:ac9f6c2c45e8	1761	#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
mbed_official	5:ac9f6c2c45e8	1762	#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
mbed_official	5:ac9f6c2c45e8	1763	#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
mbed_official	5:ac9f6c2c45e8	1764	#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
mbed_official	5:ac9f6c2c45e8	1765	#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
mbed_official	5:ac9f6c2c45e8	1766	#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
mbed_official	5:ac9f6c2c45e8	1767	#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
mbed_official	5:ac9f6c2c45e8	1768	#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
mbed_official	5:ac9f6c2c45e8	1769	#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
mbed_official	5:ac9f6c2c45e8	1770	#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
mbed_official	5:ac9f6c2c45e8	1771	#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
mbed_official	5:ac9f6c2c45e8	1772	#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
mbed_official	5:ac9f6c2c45e8	1773	#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
mbed_official	5:ac9f6c2c45e8	1774	#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
mbed_official	5:ac9f6c2c45e8	1775	#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
mbed_official	5:ac9f6c2c45e8	1776	#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
mbed_official	5:ac9f6c2c45e8	1777	#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
mbed_official	5:ac9f6c2c45e8	1778	#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
mbed_official	5:ac9f6c2c45e8	1779	#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
mbed_official	5:ac9f6c2c45e8	1780	#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
mbed_official	5:ac9f6c2c45e8	1781	#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
mbed_official	5:ac9f6c2c45e8	1782	#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
mbed_official	5:ac9f6c2c45e8	1783	#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
mbed_official	5:ac9f6c2c45e8	1784	#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
mbed_official	5:ac9f6c2c45e8	1785	#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
mbed_official	5:ac9f6c2c45e8	1786
mbed_official	5:ac9f6c2c45e8	1787	/***************** Bit definition for CAN_F3R2 register *****************/
mbed_official	5:ac9f6c2c45e8	1788	#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
mbed_official	5:ac9f6c2c45e8	1789	#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
mbed_official	5:ac9f6c2c45e8	1790	#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
mbed_official	5:ac9f6c2c45e8	1791	#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
mbed_official	5:ac9f6c2c45e8	1792	#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
mbed_official	5:ac9f6c2c45e8	1793	#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
mbed_official	5:ac9f6c2c45e8	1794	#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
mbed_official	5:ac9f6c2c45e8	1795	#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
mbed_official	5:ac9f6c2c45e8	1796	#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
mbed_official	5:ac9f6c2c45e8	1797	#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
mbed_official	5:ac9f6c2c45e8	1798	#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
mbed_official	5:ac9f6c2c45e8	1799	#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
mbed_official	5:ac9f6c2c45e8	1800	#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
mbed_official	5:ac9f6c2c45e8	1801	#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
mbed_official	5:ac9f6c2c45e8	1802	#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
mbed_official	5:ac9f6c2c45e8	1803	#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
mbed_official	5:ac9f6c2c45e8	1804	#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
mbed_official	5:ac9f6c2c45e8	1805	#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
mbed_official	5:ac9f6c2c45e8	1806	#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
mbed_official	5:ac9f6c2c45e8	1807	#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
mbed_official	5:ac9f6c2c45e8	1808	#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
mbed_official	5:ac9f6c2c45e8	1809	#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
mbed_official	5:ac9f6c2c45e8	1810	#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
mbed_official	5:ac9f6c2c45e8	1811	#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
mbed_official	5:ac9f6c2c45e8	1812	#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
mbed_official	5:ac9f6c2c45e8	1813	#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
mbed_official	5:ac9f6c2c45e8	1814	#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
mbed_official	5:ac9f6c2c45e8	1815	#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
mbed_official	5:ac9f6c2c45e8	1816	#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
mbed_official	5:ac9f6c2c45e8	1817	#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
mbed_official	5:ac9f6c2c45e8	1818	#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
mbed_official	5:ac9f6c2c45e8	1819	#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
mbed_official	5:ac9f6c2c45e8	1820
mbed_official	5:ac9f6c2c45e8	1821	/***************** Bit definition for CAN_F4R2 register *****************/
mbed_official	5:ac9f6c2c45e8	1822	#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
mbed_official	5:ac9f6c2c45e8	1823	#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
mbed_official	5:ac9f6c2c45e8	1824	#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
mbed_official	5:ac9f6c2c45e8	1825	#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
mbed_official	5:ac9f6c2c45e8	1826	#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
mbed_official	5:ac9f6c2c45e8	1827	#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
mbed_official	5:ac9f6c2c45e8	1828	#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
mbed_official	5:ac9f6c2c45e8	1829	#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
mbed_official	5:ac9f6c2c45e8	1830	#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
mbed_official	5:ac9f6c2c45e8	1831	#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
mbed_official	5:ac9f6c2c45e8	1832	#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
mbed_official	5:ac9f6c2c45e8	1833	#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
mbed_official	5:ac9f6c2c45e8	1834	#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
mbed_official	5:ac9f6c2c45e8	1835	#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
mbed_official	5:ac9f6c2c45e8	1836	#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
mbed_official	5:ac9f6c2c45e8	1837	#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
mbed_official	5:ac9f6c2c45e8	1838	#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
mbed_official	5:ac9f6c2c45e8	1839	#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
mbed_official	5:ac9f6c2c45e8	1840	#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
mbed_official	5:ac9f6c2c45e8	1841	#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
mbed_official	5:ac9f6c2c45e8	1842	#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
mbed_official	5:ac9f6c2c45e8	1843	#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
mbed_official	5:ac9f6c2c45e8	1844	#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
mbed_official	5:ac9f6c2c45e8	1845	#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
mbed_official	5:ac9f6c2c45e8	1846	#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
mbed_official	5:ac9f6c2c45e8	1847	#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
mbed_official	5:ac9f6c2c45e8	1848	#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
mbed_official	5:ac9f6c2c45e8	1849	#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
mbed_official	5:ac9f6c2c45e8	1850	#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
mbed_official	5:ac9f6c2c45e8	1851	#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
mbed_official	5:ac9f6c2c45e8	1852	#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
mbed_official	5:ac9f6c2c45e8	1853	#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
mbed_official	5:ac9f6c2c45e8	1854
mbed_official	5:ac9f6c2c45e8	1855	/***************** Bit definition for CAN_F5R2 register *****************/
mbed_official	5:ac9f6c2c45e8	1856	#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
mbed_official	5:ac9f6c2c45e8	1857	#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
mbed_official	5:ac9f6c2c45e8	1858	#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
mbed_official	5:ac9f6c2c45e8	1859	#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
mbed_official	5:ac9f6c2c45e8	1860	#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
mbed_official	5:ac9f6c2c45e8	1861	#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
mbed_official	5:ac9f6c2c45e8	1862	#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
mbed_official	5:ac9f6c2c45e8	1863	#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
mbed_official	5:ac9f6c2c45e8	1864	#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
mbed_official	5:ac9f6c2c45e8	1865	#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
mbed_official	5:ac9f6c2c45e8	1866	#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
mbed_official	5:ac9f6c2c45e8	1867	#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
mbed_official	5:ac9f6c2c45e8	1868	#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
mbed_official	5:ac9f6c2c45e8	1869	#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
mbed_official	5:ac9f6c2c45e8	1870	#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
mbed_official	5:ac9f6c2c45e8	1871	#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
mbed_official	5:ac9f6c2c45e8	1872	#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
mbed_official	5:ac9f6c2c45e8	1873	#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
mbed_official	5:ac9f6c2c45e8	1874	#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
mbed_official	5:ac9f6c2c45e8	1875	#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
mbed_official	5:ac9f6c2c45e8	1876	#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
mbed_official	5:ac9f6c2c45e8	1877	#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
mbed_official	5:ac9f6c2c45e8	1878	#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
mbed_official	5:ac9f6c2c45e8	1879	#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
mbed_official	5:ac9f6c2c45e8	1880	#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
mbed_official	5:ac9f6c2c45e8	1881	#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
mbed_official	5:ac9f6c2c45e8	1882	#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
mbed_official	5:ac9f6c2c45e8	1883	#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
mbed_official	5:ac9f6c2c45e8	1884	#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
mbed_official	5:ac9f6c2c45e8	1885	#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
mbed_official	5:ac9f6c2c45e8	1886	#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
mbed_official	5:ac9f6c2c45e8	1887	#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
mbed_official	5:ac9f6c2c45e8	1888
mbed_official	5:ac9f6c2c45e8	1889	/***************** Bit definition for CAN_F6R2 register *****************/
mbed_official	5:ac9f6c2c45e8	1890	#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
mbed_official	5:ac9f6c2c45e8	1891	#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
mbed_official	5:ac9f6c2c45e8	1892	#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
mbed_official	5:ac9f6c2c45e8	1893	#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
mbed_official	5:ac9f6c2c45e8	1894	#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
mbed_official	5:ac9f6c2c45e8	1895	#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
mbed_official	5:ac9f6c2c45e8	1896	#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
mbed_official	5:ac9f6c2c45e8	1897	#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
mbed_official	5:ac9f6c2c45e8	1898	#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
mbed_official	5:ac9f6c2c45e8	1899	#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
mbed_official	5:ac9f6c2c45e8	1900	#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
mbed_official	5:ac9f6c2c45e8	1901	#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
mbed_official	5:ac9f6c2c45e8	1902	#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
mbed_official	5:ac9f6c2c45e8	1903	#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
mbed_official	5:ac9f6c2c45e8	1904	#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
mbed_official	5:ac9f6c2c45e8	1905	#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
mbed_official	5:ac9f6c2c45e8	1906	#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
mbed_official	5:ac9f6c2c45e8	1907	#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
mbed_official	5:ac9f6c2c45e8	1908	#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
mbed_official	5:ac9f6c2c45e8	1909	#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
mbed_official	5:ac9f6c2c45e8	1910	#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
mbed_official	5:ac9f6c2c45e8	1911	#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
mbed_official	5:ac9f6c2c45e8	1912	#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
mbed_official	5:ac9f6c2c45e8	1913	#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
mbed_official	5:ac9f6c2c45e8	1914	#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
mbed_official	5:ac9f6c2c45e8	1915	#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
mbed_official	5:ac9f6c2c45e8	1916	#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
mbed_official	5:ac9f6c2c45e8	1917	#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
mbed_official	5:ac9f6c2c45e8	1918	#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
mbed_official	5:ac9f6c2c45e8	1919	#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
mbed_official	5:ac9f6c2c45e8	1920	#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
mbed_official	5:ac9f6c2c45e8	1921	#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
mbed_official	5:ac9f6c2c45e8	1922
mbed_official	5:ac9f6c2c45e8	1923	/***************** Bit definition for CAN_F7R2 register *****************/
mbed_official	5:ac9f6c2c45e8	1924	#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
mbed_official	5:ac9f6c2c45e8	1925	#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
mbed_official	5:ac9f6c2c45e8	1926	#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
mbed_official	5:ac9f6c2c45e8	1927	#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
mbed_official	5:ac9f6c2c45e8	1928	#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
mbed_official	5:ac9f6c2c45e8	1929	#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
mbed_official	5:ac9f6c2c45e8	1930	#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
mbed_official	5:ac9f6c2c45e8	1931	#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
mbed_official	5:ac9f6c2c45e8	1932	#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
mbed_official	5:ac9f6c2c45e8	1933	#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
mbed_official	5:ac9f6c2c45e8	1934	#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
mbed_official	5:ac9f6c2c45e8	1935	#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
mbed_official	5:ac9f6c2c45e8	1936	#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
mbed_official	5:ac9f6c2c45e8	1937	#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
mbed_official	5:ac9f6c2c45e8	1938	#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
mbed_official	5:ac9f6c2c45e8	1939	#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
mbed_official	5:ac9f6c2c45e8	1940	#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
mbed_official	5:ac9f6c2c45e8	1941	#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
mbed_official	5:ac9f6c2c45e8	1942	#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
mbed_official	5:ac9f6c2c45e8	1943	#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
mbed_official	5:ac9f6c2c45e8	1944	#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
mbed_official	5:ac9f6c2c45e8	1945	#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
mbed_official	5:ac9f6c2c45e8	1946	#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
mbed_official	5:ac9f6c2c45e8	1947	#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
mbed_official	5:ac9f6c2c45e8	1948	#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
mbed_official	5:ac9f6c2c45e8	1949	#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
mbed_official	5:ac9f6c2c45e8	1950	#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
mbed_official	5:ac9f6c2c45e8	1951	#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
mbed_official	5:ac9f6c2c45e8	1952	#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
mbed_official	5:ac9f6c2c45e8	1953	#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
mbed_official	5:ac9f6c2c45e8	1954	#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
mbed_official	5:ac9f6c2c45e8	1955	#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
mbed_official	5:ac9f6c2c45e8	1956
mbed_official	5:ac9f6c2c45e8	1957	/***************** Bit definition for CAN_F8R2 register *****************/
mbed_official	5:ac9f6c2c45e8	1958	#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
mbed_official	5:ac9f6c2c45e8	1959	#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
mbed_official	5:ac9f6c2c45e8	1960	#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
mbed_official	5:ac9f6c2c45e8	1961	#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
mbed_official	5:ac9f6c2c45e8	1962	#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
mbed_official	5:ac9f6c2c45e8	1963	#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
mbed_official	5:ac9f6c2c45e8	1964	#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
mbed_official	5:ac9f6c2c45e8	1965	#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
mbed_official	5:ac9f6c2c45e8	1966	#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
mbed_official	5:ac9f6c2c45e8	1967	#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
mbed_official	5:ac9f6c2c45e8	1968	#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
mbed_official	5:ac9f6c2c45e8	1969	#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
mbed_official	5:ac9f6c2c45e8	1970	#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
mbed_official	5:ac9f6c2c45e8	1971	#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
mbed_official	5:ac9f6c2c45e8	1972	#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
mbed_official	5:ac9f6c2c45e8	1973	#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
mbed_official	5:ac9f6c2c45e8	1974	#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
mbed_official	5:ac9f6c2c45e8	1975	#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
mbed_official	5:ac9f6c2c45e8	1976	#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
mbed_official	5:ac9f6c2c45e8	1977	#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
mbed_official	5:ac9f6c2c45e8	1978	#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
mbed_official	5:ac9f6c2c45e8	1979	#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
mbed_official	5:ac9f6c2c45e8	1980	#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
mbed_official	5:ac9f6c2c45e8	1981	#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
mbed_official	5:ac9f6c2c45e8	1982	#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
mbed_official	5:ac9f6c2c45e8	1983	#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
mbed_official	5:ac9f6c2c45e8	1984	#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
mbed_official	5:ac9f6c2c45e8	1985	#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
mbed_official	5:ac9f6c2c45e8	1986	#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
mbed_official	5:ac9f6c2c45e8	1987	#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
mbed_official	5:ac9f6c2c45e8	1988	#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
mbed_official	5:ac9f6c2c45e8	1989	#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
mbed_official	5:ac9f6c2c45e8	1990
mbed_official	5:ac9f6c2c45e8	1991	/***************** Bit definition for CAN_F9R2 register *****************/
mbed_official	5:ac9f6c2c45e8	1992	#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
mbed_official	5:ac9f6c2c45e8	1993	#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
mbed_official	5:ac9f6c2c45e8	1994	#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
mbed_official	5:ac9f6c2c45e8	1995	#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
mbed_official	5:ac9f6c2c45e8	1996	#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
mbed_official	5:ac9f6c2c45e8	1997	#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
mbed_official	5:ac9f6c2c45e8	1998	#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
mbed_official	5:ac9f6c2c45e8	1999	#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
mbed_official	5:ac9f6c2c45e8	2000	#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
mbed_official	5:ac9f6c2c45e8	2001	#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
mbed_official	5:ac9f6c2c45e8	2002	#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
mbed_official	5:ac9f6c2c45e8	2003	#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
mbed_official	5:ac9f6c2c45e8	2004	#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
mbed_official	5:ac9f6c2c45e8	2005	#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
mbed_official	5:ac9f6c2c45e8	2006	#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
mbed_official	5:ac9f6c2c45e8	2007	#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
mbed_official	5:ac9f6c2c45e8	2008	#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
mbed_official	5:ac9f6c2c45e8	2009	#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
mbed_official	5:ac9f6c2c45e8	2010	#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
mbed_official	5:ac9f6c2c45e8	2011	#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
mbed_official	5:ac9f6c2c45e8	2012	#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
mbed_official	5:ac9f6c2c45e8	2013	#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
mbed_official	5:ac9f6c2c45e8	2014	#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
mbed_official	5:ac9f6c2c45e8	2015	#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
mbed_official	5:ac9f6c2c45e8	2016	#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
mbed_official	5:ac9f6c2c45e8	2017	#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
mbed_official	5:ac9f6c2c45e8	2018	#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
mbed_official	5:ac9f6c2c45e8	2019	#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
mbed_official	5:ac9f6c2c45e8	2020	#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
mbed_official	5:ac9f6c2c45e8	2021	#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
mbed_official	5:ac9f6c2c45e8	2022	#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
mbed_official	5:ac9f6c2c45e8	2023	#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
mbed_official	5:ac9f6c2c45e8	2024
mbed_official	5:ac9f6c2c45e8	2025	/***************** Bit definition for CAN_F10R2 register ****************/
mbed_official	5:ac9f6c2c45e8	2026	#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
mbed_official	5:ac9f6c2c45e8	2027	#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
mbed_official	5:ac9f6c2c45e8	2028	#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
mbed_official	5:ac9f6c2c45e8	2029	#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
mbed_official	5:ac9f6c2c45e8	2030	#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
mbed_official	5:ac9f6c2c45e8	2031	#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
mbed_official	5:ac9f6c2c45e8	2032	#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
mbed_official	5:ac9f6c2c45e8	2033	#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
mbed_official	5:ac9f6c2c45e8	2034	#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
mbed_official	5:ac9f6c2c45e8	2035	#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
mbed_official	5:ac9f6c2c45e8	2036	#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
mbed_official	5:ac9f6c2c45e8	2037	#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
mbed_official	5:ac9f6c2c45e8	2038	#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
mbed_official	5:ac9f6c2c45e8	2039	#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
mbed_official	5:ac9f6c2c45e8	2040	#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
mbed_official	5:ac9f6c2c45e8	2041	#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
mbed_official	5:ac9f6c2c45e8	2042	#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
mbed_official	5:ac9f6c2c45e8	2043	#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
mbed_official	5:ac9f6c2c45e8	2044	#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
mbed_official	5:ac9f6c2c45e8	2045	#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
mbed_official	5:ac9f6c2c45e8	2046	#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
mbed_official	5:ac9f6c2c45e8	2047	#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
mbed_official	5:ac9f6c2c45e8	2048	#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
mbed_official	5:ac9f6c2c45e8	2049	#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
mbed_official	5:ac9f6c2c45e8	2050	#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
mbed_official	5:ac9f6c2c45e8	2051	#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
mbed_official	5:ac9f6c2c45e8	2052	#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
mbed_official	5:ac9f6c2c45e8	2053	#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
mbed_official	5:ac9f6c2c45e8	2054	#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
mbed_official	5:ac9f6c2c45e8	2055	#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
mbed_official	5:ac9f6c2c45e8	2056	#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
mbed_official	5:ac9f6c2c45e8	2057	#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
mbed_official	5:ac9f6c2c45e8	2058
mbed_official	5:ac9f6c2c45e8	2059	/***************** Bit definition for CAN_F11R2 register ****************/
mbed_official	5:ac9f6c2c45e8	2060	#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
mbed_official	5:ac9f6c2c45e8	2061	#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
mbed_official	5:ac9f6c2c45e8	2062	#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
mbed_official	5:ac9f6c2c45e8	2063	#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
mbed_official	5:ac9f6c2c45e8	2064	#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
mbed_official	5:ac9f6c2c45e8	2065	#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
mbed_official	5:ac9f6c2c45e8	2066	#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
mbed_official	5:ac9f6c2c45e8	2067	#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
mbed_official	5:ac9f6c2c45e8	2068	#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
mbed_official	5:ac9f6c2c45e8	2069	#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
mbed_official	5:ac9f6c2c45e8	2070	#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
mbed_official	5:ac9f6c2c45e8	2071	#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
mbed_official	5:ac9f6c2c45e8	2072	#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
mbed_official	5:ac9f6c2c45e8	2073	#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
mbed_official	5:ac9f6c2c45e8	2074	#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
mbed_official	5:ac9f6c2c45e8	2075	#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
mbed_official	5:ac9f6c2c45e8	2076	#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
mbed_official	5:ac9f6c2c45e8	2077	#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
mbed_official	5:ac9f6c2c45e8	2078	#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
mbed_official	5:ac9f6c2c45e8	2079	#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
mbed_official	5:ac9f6c2c45e8	2080	#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
mbed_official	5:ac9f6c2c45e8	2081	#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
mbed_official	5:ac9f6c2c45e8	2082	#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
mbed_official	5:ac9f6c2c45e8	2083	#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
mbed_official	5:ac9f6c2c45e8	2084	#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
mbed_official	5:ac9f6c2c45e8	2085	#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
mbed_official	5:ac9f6c2c45e8	2086	#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
mbed_official	5:ac9f6c2c45e8	2087	#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
mbed_official	5:ac9f6c2c45e8	2088	#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
mbed_official	5:ac9f6c2c45e8	2089	#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
mbed_official	5:ac9f6c2c45e8	2090	#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
mbed_official	5:ac9f6c2c45e8	2091	#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
mbed_official	5:ac9f6c2c45e8	2092
mbed_official	5:ac9f6c2c45e8	2093	/***************** Bit definition for CAN_F12R2 register ****************/
mbed_official	5:ac9f6c2c45e8	2094	#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
mbed_official	5:ac9f6c2c45e8	2095	#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
mbed_official	5:ac9f6c2c45e8	2096	#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
mbed_official	5:ac9f6c2c45e8	2097	#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
mbed_official	5:ac9f6c2c45e8	2098	#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
mbed_official	5:ac9f6c2c45e8	2099	#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
mbed_official	5:ac9f6c2c45e8	2100	#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
mbed_official	5:ac9f6c2c45e8	2101	#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
mbed_official	5:ac9f6c2c45e8	2102	#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
mbed_official	5:ac9f6c2c45e8	2103	#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
mbed_official	5:ac9f6c2c45e8	2104	#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
mbed_official	5:ac9f6c2c45e8	2105	#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
mbed_official	5:ac9f6c2c45e8	2106	#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
mbed_official	5:ac9f6c2c45e8	2107	#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
mbed_official	5:ac9f6c2c45e8	2108	#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
mbed_official	5:ac9f6c2c45e8	2109	#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
mbed_official	5:ac9f6c2c45e8	2110	#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
mbed_official	5:ac9f6c2c45e8	2111	#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
mbed_official	5:ac9f6c2c45e8	2112	#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
mbed_official	5:ac9f6c2c45e8	2113	#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
mbed_official	5:ac9f6c2c45e8	2114	#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
mbed_official	5:ac9f6c2c45e8	2115	#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
mbed_official	5:ac9f6c2c45e8	2116	#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
mbed_official	5:ac9f6c2c45e8	2117	#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
mbed_official	5:ac9f6c2c45e8	2118	#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
mbed_official	5:ac9f6c2c45e8	2119	#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
mbed_official	5:ac9f6c2c45e8	2120	#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
mbed_official	5:ac9f6c2c45e8	2121	#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
mbed_official	5:ac9f6c2c45e8	2122	#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
mbed_official	5:ac9f6c2c45e8	2123	#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
mbed_official	5:ac9f6c2c45e8	2124	#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
mbed_official	5:ac9f6c2c45e8	2125	#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
mbed_official	5:ac9f6c2c45e8	2126
mbed_official	5:ac9f6c2c45e8	2127	/***************** Bit definition for CAN_F13R2 register ****************/
mbed_official	5:ac9f6c2c45e8	2128	#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
mbed_official	5:ac9f6c2c45e8	2129	#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
mbed_official	5:ac9f6c2c45e8	2130	#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
mbed_official	5:ac9f6c2c45e8	2131	#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
mbed_official	5:ac9f6c2c45e8	2132	#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
mbed_official	5:ac9f6c2c45e8	2133	#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
mbed_official	5:ac9f6c2c45e8	2134	#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
mbed_official	5:ac9f6c2c45e8	2135	#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
mbed_official	5:ac9f6c2c45e8	2136	#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
mbed_official	5:ac9f6c2c45e8	2137	#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
mbed_official	5:ac9f6c2c45e8	2138	#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
mbed_official	5:ac9f6c2c45e8	2139	#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
mbed_official	5:ac9f6c2c45e8	2140	#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
mbed_official	5:ac9f6c2c45e8	2141	#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
mbed_official	5:ac9f6c2c45e8	2142	#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
mbed_official	5:ac9f6c2c45e8	2143	#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
mbed_official	5:ac9f6c2c45e8	2144	#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
mbed_official	5:ac9f6c2c45e8	2145	#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
mbed_official	5:ac9f6c2c45e8	2146	#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
mbed_official	5:ac9f6c2c45e8	2147	#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
mbed_official	5:ac9f6c2c45e8	2148	#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
mbed_official	5:ac9f6c2c45e8	2149	#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
mbed_official	5:ac9f6c2c45e8	2150	#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
mbed_official	5:ac9f6c2c45e8	2151	#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
mbed_official	5:ac9f6c2c45e8	2152	#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
mbed_official	5:ac9f6c2c45e8	2153	#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
mbed_official	5:ac9f6c2c45e8	2154	#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
mbed_official	5:ac9f6c2c45e8	2155	#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
mbed_official	5:ac9f6c2c45e8	2156	#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
mbed_official	5:ac9f6c2c45e8	2157	#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
mbed_official	5:ac9f6c2c45e8	2158	#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
mbed_official	5:ac9f6c2c45e8	2159	#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
mbed_official	5:ac9f6c2c45e8	2160
mbed_official	5:ac9f6c2c45e8	2161	/******************************************************************************/
mbed_official	5:ac9f6c2c45e8	2162	/* */
mbed_official	5:ac9f6c2c45e8	2163	/* HDMI-CEC (CEC) */
mbed_official	5:ac9f6c2c45e8	2164	/* */
mbed_official	5:ac9f6c2c45e8	2165	/******************************************************************************/
mbed_official	5:ac9f6c2c45e8	2166
mbed_official	5:ac9f6c2c45e8	2167	/***************** Bit definition for CEC_CR register *******************/
mbed_official	5:ac9f6c2c45e8	2168	#define CEC_CR_CECEN ((uint32_t)0x00000001) /!< CEC Enable /
mbed_official	5:ac9f6c2c45e8	2169	#define CEC_CR_TXSOM ((uint32_t)0x00000002) /!< CEC Tx Start Of Message /
mbed_official	5:ac9f6c2c45e8	2170	#define CEC_CR_TXEOM ((uint32_t)0x00000004) /!< CEC Tx End Of Message /
mbed_official	5:ac9f6c2c45e8	2171
mbed_official	5:ac9f6c2c45e8	2172	/***************** Bit definition for CEC_CFGR register *****************/
mbed_official	5:ac9f6c2c45e8	2173	#define CEC_CFGR_SFT ((uint32_t)0x00000007) /!< CEC Signal Free Time /
mbed_official	5:ac9f6c2c45e8	2174	#define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /!< CEC Tolerance /
mbed_official	5:ac9f6c2c45e8	2175	#define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /!< CEC Rx Stop /
mbed_official	5:ac9f6c2c45e8	2176	#define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /!< CEC Bit Rising Error generation /
mbed_official	5:ac9f6c2c45e8	2177	#define CEC_CFGR_LBPEGEN ((uint32_t)0x00000040) /!< CEC Long Bit Period Error gener. /
mbed_official	5:ac9f6c2c45e8	2178	#define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /!< CEC Broadcast No Error generation /
mbed_official	5:ac9f6c2c45e8	2179	#define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /!< CEC Signal Free Time optional /
mbed_official	5:ac9f6c2c45e8	2180	#define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /!< CEC Own Address /
mbed_official	5:ac9f6c2c45e8	2181	#define CEC_CFGR_LSTN ((uint32_t)0x80000000) /!< CEC Listen mode /
mbed_official	5:ac9f6c2c45e8	2182
mbed_official	5:ac9f6c2c45e8	2183	/***************** Bit definition for CEC_TXDR register *****************/
mbed_official	5:ac9f6c2c45e8	2184	#define CEC_TXDR_TXD ((uint32_t)0x000000FF) /!< CEC Tx Data /
mbed_official	5:ac9f6c2c45e8	2185
mbed_official	5:ac9f6c2c45e8	2186	/***************** Bit definition for CEC_RXDR register *****************/
mbed_official	5:ac9f6c2c45e8	2187	#define CEC_TXDR_RXD ((uint32_t)0x000000FF) /!< CEC Rx Data /
mbed_official	5:ac9f6c2c45e8	2188
mbed_official	5:ac9f6c2c45e8	2189	/***************** Bit definition for CEC_ISR register ******************/
mbed_official	5:ac9f6c2c45e8	2190	#define CEC_ISR_RXBR ((uint32_t)0x00000001) /!< CEC Rx-Byte Received /
mbed_official	5:ac9f6c2c45e8	2191	#define CEC_ISR_RXEND ((uint32_t)0x00000002) /!< CEC End Of Reception /
mbed_official	5:ac9f6c2c45e8	2192	#define CEC_ISR_RXOVR ((uint32_t)0x00000004) /!< CEC Rx-Overrun /
mbed_official	5:ac9f6c2c45e8	2193	#define CEC_ISR_BRE ((uint32_t)0x00000008) /!< CEC Rx Bit Rising Error /
mbed_official	5:ac9f6c2c45e8	2194	#define CEC_ISR_SBPE ((uint32_t)0x00000010) /!< CEC Rx Short Bit period Error /
mbed_official	5:ac9f6c2c45e8	2195	#define CEC_ISR_LBPE ((uint32_t)0x00000020) /!< CEC Rx Long Bit period Error /
mbed_official	5:ac9f6c2c45e8	2196	#define CEC_ISR_RXACKE ((uint32_t)0x00000040) /!< CEC Rx Missing Acknowledge /
mbed_official	5:ac9f6c2c45e8	2197	#define CEC_ISR_ARBLST ((uint32_t)0x00000080) /!< CEC Arbitration Lost /
mbed_official	5:ac9f6c2c45e8	2198	#define CEC_ISR_TXBR ((uint32_t)0x00000100) /!< CEC Tx Byte Request /
mbed_official	5:ac9f6c2c45e8	2199	#define CEC_ISR_TXEND ((uint32_t)0x00000200) /!< CEC End of Transmission /
mbed_official	5:ac9f6c2c45e8	2200	#define CEC_ISR_TXUDR ((uint32_t)0x00000400) /!< CEC Tx-Buffer Underrun /
mbed_official	5:ac9f6c2c45e8	2201	#define CEC_ISR_TXERR ((uint32_t)0x00000800) /!< CEC Tx-Error /
mbed_official	5:ac9f6c2c45e8	2202	#define CEC_ISR_TXACKE ((uint32_t)0x00001000) /!< CEC Tx Missing Acknowledge /
mbed_official	5:ac9f6c2c45e8	2203
mbed_official	5:ac9f6c2c45e8	2204	/***************** Bit definition for CEC_IER register ******************/
mbed_official	5:ac9f6c2c45e8	2205	#define CEC_IER_RXBRIE ((uint32_t)0x00000001) /!< CEC Rx-Byte Received IT Enable /
mbed_official	5:ac9f6c2c45e8	2206	#define CEC_IER_RXENDIE ((uint32_t)0x00000002) /!< CEC End Of Reception IT Enable /
mbed_official	5:ac9f6c2c45e8	2207	#define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /!< CEC Rx-Overrun IT Enable /
mbed_official	5:ac9f6c2c45e8	2208	#define CEC_IER_BREIE ((uint32_t)0x00000008) /!< CEC Rx Bit Rising Error IT Enable /
mbed_official	5:ac9f6c2c45e8	2209	#define CEC_IER_SBPEIE ((uint32_t)0x00000010) /!< CEC Rx Short Bit period Error IT Enable/
mbed_official	5:ac9f6c2c45e8	2210	#define CEC_IER_LBPEIE ((uint32_t)0x00000020) /!< CEC Rx Long Bit period Error IT Enable /
mbed_official	5:ac9f6c2c45e8	2211	#define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /!< CEC Rx Missing Acknowledge IT Enable /
mbed_official	5:ac9f6c2c45e8	2212	#define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /!< CEC Arbitration Lost IT Enable /
mbed_official	5:ac9f6c2c45e8	2213	#define CEC_IER_TXBRIE ((uint32_t)0x00000100) /!< CEC Tx Byte Request IT Enable /
mbed_official	5:ac9f6c2c45e8	2214	#define CEC_IER_TXENDIE ((uint32_t)0x00000200) /!< CEC End of Transmission IT Enable /
mbed_official	5:ac9f6c2c45e8	2215	#define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /!< CEC Tx-Buffer Underrun IT Enable /
mbed_official	5:ac9f6c2c45e8	2216	#define CEC_IER_TXERRIE ((uint32_t)0x00000800) /!< CEC Tx-Error IT Enable /
mbed_official	5:ac9f6c2c45e8	2217	#define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /!< CEC Tx Missing Acknowledge IT Enable /
mbed_official	5:ac9f6c2c45e8	2218
mbed_official	5:ac9f6c2c45e8	2219	/******************************************************************************/
mbed_official	5:ac9f6c2c45e8	2220	/* */
mbed_official	5:ac9f6c2c45e8	2221	/* CRC calculation unit (CRC) */
mbed_official	5:ac9f6c2c45e8	2222	/* */
mbed_official	5:ac9f6c2c45e8	2223	/******************************************************************************/
mbed_official	5:ac9f6c2c45e8	2224	/***************** Bit definition for CRC_DR register *******************/
mbed_official	5:ac9f6c2c45e8	2225	#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /!< Data register bits /
mbed_official	5:ac9f6c2c45e8	2226
mbed_official	5:ac9f6c2c45e8	2227	/***************** Bit definition for CRC_IDR register ******************/
mbed_official	5:ac9f6c2c45e8	2228	#define CRC_IDR_IDR ((uint8_t)0xFF) /!< General-purpose 8-bit data register bits /
mbed_official	5:ac9f6c2c45e8	2229
mbed_official	5:ac9f6c2c45e8	2230	/****************** Bit definition for CRC_CR register ******************/
mbed_official	5:ac9f6c2c45e8	2231	#define CRC_CR_RESET ((uint32_t)0x00000001) /!< RESET the CRC computation unit bit /
mbed_official	5:ac9f6c2c45e8	2232	#define CRC_CR_REV_IN ((uint32_t)0x00000060) /!< REV_IN Reverse Input Data bits /
mbed_official	5:ac9f6c2c45e8	2233	#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /!< REV_IN Bit 0 /
mbed_official	5:ac9f6c2c45e8	2234	#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /!< REV_IN Bit 1 /
mbed_official	5:ac9f6c2c45e8	2235	#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /!< REV_OUT Reverse Output Data bits /
mbed_official	5:ac9f6c2c45e8	2236
mbed_official	5:ac9f6c2c45e8	2237	/***************** Bit definition for CRC_INIT register *****************/
mbed_official	5:ac9f6c2c45e8	2238	#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /!< Initial CRC value bits /
mbed_official	5:ac9f6c2c45e8	2239
mbed_official	5:ac9f6c2c45e8	2240	/******************************************************************************/
mbed_official	5:ac9f6c2c45e8	2241	/* */
mbed_official	5:ac9f6c2c45e8	2242	/* CRS Clock Recovery System */
mbed_official	5:ac9f6c2c45e8	2243	/******************************************************************************/
mbed_official	5:ac9f6c2c45e8	2244
mbed_official	5:ac9f6c2c45e8	2245	/***************** Bit definition for CRS_CR register *******************/
mbed_official	5:ac9f6c2c45e8	2246	#define CRS_CR_SYNCOKIE ((uint32_t)0x00000001) /* SYNC event OK interrupt enable */
mbed_official	5:ac9f6c2c45e8	2247	#define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002) /* SYNC warning interrupt enable */
mbed_official	5:ac9f6c2c45e8	2248	#define CRS_CR_ERRIE ((uint32_t)0x00000004) /* SYNC error interrupt enable */
mbed_official	5:ac9f6c2c45e8	2249	#define CRS_CR_ESYNCIE ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/
mbed_official	5:ac9f6c2c45e8	2250	#define CRS_CR_CEN ((uint32_t)0x00000020) /* Frequency error counter enable */
mbed_official	5:ac9f6c2c45e8	2251	#define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040) /* Automatic trimming enable */
mbed_official	5:ac9f6c2c45e8	2252	#define CRS_CR_SWSYNC ((uint32_t)0x00000080) /* A Software SYNC event is generated */
mbed_official	5:ac9f6c2c45e8	2253	#define CRS_CR_TRIM ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming */
mbed_official	5:ac9f6c2c45e8	2254
mbed_official	5:ac9f6c2c45e8	2255	/***************** Bit definition for CRS_CFGR register *******************/
mbed_official	5:ac9f6c2c45e8	2256	#define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFF) /* Counter reload value */
mbed_official	5:ac9f6c2c45e8	2257	#define CRS_CFGR_FELIM ((uint32_t)0x00FF0000) /* Frequency error limit */
mbed_official	5:ac9f6c2c45e8	2258
mbed_official	5:ac9f6c2c45e8	2259	#define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000) /* SYNC divider */
mbed_official	5:ac9f6c2c45e8	2260	#define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000) /* Bit 0 */
mbed_official	5:ac9f6c2c45e8	2261	#define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000) /* Bit 1 */
mbed_official	5:ac9f6c2c45e8	2262	#define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000) /* Bit 2 */
mbed_official	5:ac9f6c2c45e8	2263
mbed_official	5:ac9f6c2c45e8	2264	#define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000) /* SYNC signal source selection */
mbed_official	5:ac9f6c2c45e8	2265	#define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000) /* Bit 0 */
mbed_official	5:ac9f6c2c45e8	2266	#define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000) /* Bit 1 */
mbed_official	5:ac9f6c2c45e8	2267
mbed_official	5:ac9f6c2c45e8	2268	#define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000) /* SYNC polarity selection */
mbed_official	5:ac9f6c2c45e8	2269
mbed_official	5:ac9f6c2c45e8	2270	/***************** Bit definition for CRS_ISR register *******************/
mbed_official	5:ac9f6c2c45e8	2271	#define CRS_ISR_SYNCOKF ((uint32_t)0x00000001) /* SYNC event OK flag */
mbed_official	5:ac9f6c2c45e8	2272	#define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002) /* SYNC warning */
mbed_official	5:ac9f6c2c45e8	2273	#define CRS_ISR_ERRF ((uint32_t)0x00000004) /* SYNC error flag */
mbed_official	5:ac9f6c2c45e8	2274	#define CRS_ISR_ESYNCF ((uint32_t)0x00000008) /* Expected SYNC flag */
mbed_official	5:ac9f6c2c45e8	2275	#define CRS_ISR_SYNCERR ((uint32_t)0x00000100) /* SYNC error */
mbed_official	5:ac9f6c2c45e8	2276	#define CRS_ISR_SYNCMISS ((uint32_t)0x00000200) /* SYNC missed */
mbed_official	5:ac9f6c2c45e8	2277	#define CRS_ISR_TRIMOVF ((uint32_t)0x00000400) /* Trimming overflow or underflow */
mbed_official	5:ac9f6c2c45e8	2278	#define CRS_ISR_FEDIR ((uint32_t)0x00008000) /* Frequency error direction */
mbed_official	5:ac9f6c2c45e8	2279	#define CRS_ISR_FECAP ((uint32_t)0xFFFF0000) /* Frequency error capture */
mbed_official	5:ac9f6c2c45e8	2280
mbed_official	5:ac9f6c2c45e8	2281	/***************** Bit definition for CRS_ICR register *******************/
mbed_official	5:ac9f6c2c45e8	2282	#define CRS_ICR_SYNCOKC ((uint32_t)0x00000001) /* SYNC event OK clear flag */
mbed_official	5:ac9f6c2c45e8	2283	#define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002) /* SYNC warning clear flag */
mbed_official	5:ac9f6c2c45e8	2284	#define CRS_ICR_ERRC ((uint32_t)0x00000004) /* Error clear flag */
mbed_official	5:ac9f6c2c45e8	2285	#define CRS_ICR_ESYNCC ((uint32_t)0x00000008) /* Expected SYNC clear flag */
mbed_official	5:ac9f6c2c45e8	2286
mbed_official	5:ac9f6c2c45e8	2287	/******************************************************************************/
mbed_official	5:ac9f6c2c45e8	2288	/* */
mbed_official	5:ac9f6c2c45e8	2289	/* Debug MCU (DBGMCU) */
mbed_official	5:ac9f6c2c45e8	2290	/* */
mbed_official	5:ac9f6c2c45e8	2291	/******************************************************************************/
mbed_official	5:ac9f6c2c45e8	2292
mbed_official	5:ac9f6c2c45e8	2293	/************** Bit definition for DBGMCU_IDCODE register ***************/
mbed_official	5:ac9f6c2c45e8	2294	#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /!< Device Identifier /
mbed_official	5:ac9f6c2c45e8	2295
mbed_official	5:ac9f6c2c45e8	2296	#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /!< REV_ID[15:0] bits (Revision Identifier) /
mbed_official	5:ac9f6c2c45e8	2297	#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /!< Bit 0 /
mbed_official	5:ac9f6c2c45e8	2298	#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /!< Bit 1 /
mbed_official	5:ac9f6c2c45e8	2299	#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /!< Bit 2 /
mbed_official	5:ac9f6c2c45e8	2300	#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /!< Bit 3 /
mbed_official	5:ac9f6c2c45e8	2301	#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /!< Bit 4 /
mbed_official	5:ac9f6c2c45e8	2302	#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /!< Bit 5 /
mbed_official	5:ac9f6c2c45e8	2303	#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /!< Bit 6 /
mbed_official	5:ac9f6c2c45e8	2304	#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /!< Bit 7 /
mbed_official	5:ac9f6c2c45e8	2305	#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /!< Bit 8 /
mbed_official	5:ac9f6c2c45e8	2306	#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /!< Bit 9 /
mbed_official	5:ac9f6c2c45e8	2307	#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /!< Bit 10 /
mbed_official	5:ac9f6c2c45e8	2308	#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /!< Bit 11 /
mbed_official	5:ac9f6c2c45e8	2309	#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /!< Bit 12 /
mbed_official	5:ac9f6c2c45e8	2310	#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /!< Bit 13 /
mbed_official	5:ac9f6c2c45e8	2311	#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /!< Bit 14 /
mbed_official	5:ac9f6c2c45e8	2312	#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /!< Bit 15 /
mbed_official	5:ac9f6c2c45e8	2313
mbed_official	5:ac9f6c2c45e8	2314	/**************** Bit definition for DBGMCU_CR register *****************/
mbed_official	5:ac9f6c2c45e8	2315	#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /!< Debug Stop Mode /
mbed_official	5:ac9f6c2c45e8	2316	#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /!< Debug Standby mode /
mbed_official	5:ac9f6c2c45e8	2317
mbed_official	5:ac9f6c2c45e8	2318	/**************** Bit definition for DBGMCU_APB1_FZ register ************/
mbed_official	5:ac9f6c2c45e8	2319	#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /!< TIM2 counter stopped when core is halted /
mbed_official	5:ac9f6c2c45e8	2320	#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /!< TIM3 counter stopped when core is halted /
mbed_official	5:ac9f6c2c45e8	2321	#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /!< TIM14 counter stopped when core is halted /
mbed_official	5:ac9f6c2c45e8	2322	#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /!< RTC Calendar frozen when core is halted /
mbed_official	5:ac9f6c2c45e8	2323	#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /!< Debug Window Watchdog stopped when Core is halted /
mbed_official	5:ac9f6c2c45e8	2324	#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /!< Debug Independent Watchdog stopped when Core is halted /
mbed_official	5:ac9f6c2c45e8	2325	#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /!< I2C1 SMBUS timeout mode stopped when Core is halted /
mbed_official	5:ac9f6c2c45e8	2326	#define DBGMCU_APB1_FZ_DBG_CAN_STOP ((uint32_t)0x02000000) /!< CAN debug stopped when Core is halted /
mbed_official	5:ac9f6c2c45e8	2327
mbed_official	5:ac9f6c2c45e8	2328	/**************** Bit definition for DBGMCU_APB2_FZ register ************/
mbed_official	5:ac9f6c2c45e8	2329	#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /!< TIM1 counter stopped when core is halted /
mbed_official	5:ac9f6c2c45e8	2330	#define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /!< TIM16 counter stopped when core is halted /
mbed_official	5:ac9f6c2c45e8	2331	#define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /!< TIM17 counter stopped when core is halted /
mbed_official	5:ac9f6c2c45e8	2332
mbed_official	5:ac9f6c2c45e8	2333	/******************************************************************************/
mbed_official	5:ac9f6c2c45e8	2334	/* */
mbed_official	5:ac9f6c2c45e8	2335	/* DMA Controller (DMA) */
mbed_official	5:ac9f6c2c45e8	2336	/* */
mbed_official	5:ac9f6c2c45e8	2337	/******************************************************************************/
mbed_official	5:ac9f6c2c45e8	2338	/***************** Bit definition for DMA_ISR register ******************/
mbed_official	5:ac9f6c2c45e8	2339	#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt flag /
mbed_official	5:ac9f6c2c45e8	2340	#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete flag /
mbed_official	5:ac9f6c2c45e8	2341	#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer flag /
mbed_official	5:ac9f6c2c45e8	2342	#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error flag /
mbed_official	5:ac9f6c2c45e8	2343	#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt flag /
mbed_official	5:ac9f6c2c45e8	2344	#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete flag /
mbed_official	5:ac9f6c2c45e8	2345	#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer flag /
mbed_official	5:ac9f6c2c45e8	2346	#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error flag /
mbed_official	5:ac9f6c2c45e8	2347	#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt flag /
mbed_official	5:ac9f6c2c45e8	2348	#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete flag /
mbed_official	5:ac9f6c2c45e8	2349	#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer flag /
mbed_official	5:ac9f6c2c45e8	2350	#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error flag /
mbed_official	5:ac9f6c2c45e8	2351	#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt flag /
mbed_official	5:ac9f6c2c45e8	2352	#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete flag /
mbed_official	5:ac9f6c2c45e8	2353	#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer flag /
mbed_official	5:ac9f6c2c45e8	2354	#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error flag /
mbed_official	5:ac9f6c2c45e8	2355	#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt flag /
mbed_official	5:ac9f6c2c45e8	2356	#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete flag /
mbed_official	5:ac9f6c2c45e8	2357	#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer flag /
mbed_official	5:ac9f6c2c45e8	2358	#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error flag /
mbed_official	5:ac9f6c2c45e8	2359	#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt flag /
mbed_official	5:ac9f6c2c45e8	2360	#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete flag /
mbed_official	5:ac9f6c2c45e8	2361	#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer flag /
mbed_official	5:ac9f6c2c45e8	2362	#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error flag /
mbed_official	5:ac9f6c2c45e8	2363	#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt flag /
mbed_official	5:ac9f6c2c45e8	2364	#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete flag /
mbed_official	5:ac9f6c2c45e8	2365	#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer flag /
mbed_official	5:ac9f6c2c45e8	2366	#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error flag /
mbed_official	5:ac9f6c2c45e8	2367
mbed_official	5:ac9f6c2c45e8	2368	/***************** Bit definition for DMA_IFCR register *****************/
mbed_official	5:ac9f6c2c45e8	2369	#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt clear /
mbed_official	5:ac9f6c2c45e8	2370	#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete clear /
mbed_official	5:ac9f6c2c45e8	2371	#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer clear /
mbed_official	5:ac9f6c2c45e8	2372	#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error clear /
mbed_official	5:ac9f6c2c45e8	2373	#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt clear /
mbed_official	5:ac9f6c2c45e8	2374	#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete clear /
mbed_official	5:ac9f6c2c45e8	2375	#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer clear /
mbed_official	5:ac9f6c2c45e8	2376	#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error clear /
mbed_official	5:ac9f6c2c45e8	2377	#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt clear /
mbed_official	5:ac9f6c2c45e8	2378	#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete clear /
mbed_official	5:ac9f6c2c45e8	2379	#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer clear /
mbed_official	5:ac9f6c2c45e8	2380	#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error clear /
mbed_official	5:ac9f6c2c45e8	2381	#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt clear /
mbed_official	5:ac9f6c2c45e8	2382	#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete clear /
mbed_official	5:ac9f6c2c45e8	2383	#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer clear /
mbed_official	5:ac9f6c2c45e8	2384	#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error clear /
mbed_official	5:ac9f6c2c45e8	2385	#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt clear /
mbed_official	5:ac9f6c2c45e8	2386	#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete clear /
mbed_official	5:ac9f6c2c45e8	2387	#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer clear /
mbed_official	5:ac9f6c2c45e8	2388	#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error clear /
mbed_official	5:ac9f6c2c45e8	2389	#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt clear /
mbed_official	5:ac9f6c2c45e8	2390	#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete clear /
mbed_official	5:ac9f6c2c45e8	2391	#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer clear /
mbed_official	5:ac9f6c2c45e8	2392	#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error clear /
mbed_official	5:ac9f6c2c45e8	2393	#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt clear /
mbed_official	5:ac9f6c2c45e8	2394	#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete clear /
mbed_official	5:ac9f6c2c45e8	2395	#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer clear /
mbed_official	5:ac9f6c2c45e8	2396	#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error clear /
mbed_official	5:ac9f6c2c45e8	2397
mbed_official	5:ac9f6c2c45e8	2398	/***************** Bit definition for DMA_CCR register ******************/
mbed_official	5:ac9f6c2c45e8	2399	#define DMA_CCR_EN ((uint32_t)0x00000001) /!< Channel enable /
mbed_official	5:ac9f6c2c45e8	2400	#define DMA_CCR_TCIE ((uint32_t)0x00000002) /!< Transfer complete interrupt enable /
mbed_official	5:ac9f6c2c45e8	2401	#define DMA_CCR_HTIE ((uint32_t)0x00000004) /!< Half Transfer interrupt enable /
mbed_official	5:ac9f6c2c45e8	2402	#define DMA_CCR_TEIE ((uint32_t)0x00000008) /!< Transfer error interrupt enable /
mbed_official	5:ac9f6c2c45e8	2403	#define DMA_CCR_DIR ((uint32_t)0x00000010) /!< Data transfer direction /
mbed_official	5:ac9f6c2c45e8	2404	#define DMA_CCR_CIRC ((uint32_t)0x00000020) /!< Circular mode /
mbed_official	5:ac9f6c2c45e8	2405	#define DMA_CCR_PINC ((uint32_t)0x00000040) /!< Peripheral increment mode /
mbed_official	5:ac9f6c2c45e8	2406	#define DMA_CCR_MINC ((uint32_t)0x00000080) /!< Memory increment mode /
mbed_official	5:ac9f6c2c45e8	2407
mbed_official	5:ac9f6c2c45e8	2408	#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /!< PSIZE[1:0] bits (Peripheral size) /
mbed_official	5:ac9f6c2c45e8	2409	#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /!< Bit 0 /
mbed_official	5:ac9f6c2c45e8	2410	#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /!< Bit 1 /
mbed_official	5:ac9f6c2c45e8	2411
mbed_official	5:ac9f6c2c45e8	2412	#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /!< MSIZE[1:0] bits (Memory size) /
mbed_official	5:ac9f6c2c45e8	2413	#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /!< Bit 0 /
mbed_official	5:ac9f6c2c45e8	2414	#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /!< Bit 1 /
mbed_official	5:ac9f6c2c45e8	2415
mbed_official	5:ac9f6c2c45e8	2416	#define DMA_CCR_PL ((uint32_t)0x00003000) /!< PL[1:0] bits(Channel Priority level)/
mbed_official	5:ac9f6c2c45e8	2417	#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /!< Bit 0 /
mbed_official	5:ac9f6c2c45e8	2418	#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /!< Bit 1 /
mbed_official	5:ac9f6c2c45e8	2419
mbed_official	5:ac9f6c2c45e8	2420	#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /!< Memory to memory mode /
mbed_official	5:ac9f6c2c45e8	2421
mbed_official	5:ac9f6c2c45e8	2422	/**************** Bit definition for DMA_CNDTR register *****************/
mbed_official	5:ac9f6c2c45e8	2423	#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /!< Number of data to Transfer /
mbed_official	5:ac9f6c2c45e8	2424
mbed_official	5:ac9f6c2c45e8	2425	/**************** Bit definition for DMA_CPAR register ******************/
mbed_official	5:ac9f6c2c45e8	2426	#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
mbed_official	5:ac9f6c2c45e8	2427
mbed_official	5:ac9f6c2c45e8	2428	/**************** Bit definition for DMA_CMAR register ******************/
mbed_official	5:ac9f6c2c45e8	2429	#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
mbed_official	5:ac9f6c2c45e8	2430
mbed_official	5:ac9f6c2c45e8	2431	/******************************************************************************/
mbed_official	5:ac9f6c2c45e8	2432	/* */
mbed_official	5:ac9f6c2c45e8	2433	/* External Interrupt/Event Controller (EXTI) */
mbed_official	5:ac9f6c2c45e8	2434	/* */
mbed_official	5:ac9f6c2c45e8	2435	/******************************************************************************/
mbed_official	5:ac9f6c2c45e8	2436	/***************** Bit definition for EXTI_IMR register *****************/
mbed_official	5:ac9f6c2c45e8	2437	#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /!< Interrupt Mask on line 0 /
mbed_official	5:ac9f6c2c45e8	2438	#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /!< Interrupt Mask on line 1 /
mbed_official	5:ac9f6c2c45e8	2439	#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /!< Interrupt Mask on line 2 /
mbed_official	5:ac9f6c2c45e8	2440	#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /!< Interrupt Mask on line 3 /
mbed_official	5:ac9f6c2c45e8	2441	#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /!< Interrupt Mask on line 4 /
mbed_official	5:ac9f6c2c45e8	2442	#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /!< Interrupt Mask on line 5 /
mbed_official	5:ac9f6c2c45e8	2443	#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /!< Interrupt Mask on line 6 /
mbed_official	5:ac9f6c2c45e8	2444	#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /!< Interrupt Mask on line 7 /
mbed_official	5:ac9f6c2c45e8	2445	#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /!< Interrupt Mask on line 8 /
mbed_official	5:ac9f6c2c45e8	2446	#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /!< Interrupt Mask on line 9 /
mbed_official	5:ac9f6c2c45e8	2447	#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /!< Interrupt Mask on line 10 /
mbed_official	5:ac9f6c2c45e8	2448	#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /!< Interrupt Mask on line 11 /
mbed_official	5:ac9f6c2c45e8	2449	#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /!< Interrupt Mask on line 12 /
mbed_official	5:ac9f6c2c45e8	2450	#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /!< Interrupt Mask on line 13 /
mbed_official	5:ac9f6c2c45e8	2451	#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /!< Interrupt Mask on line 14 /
mbed_official	5:ac9f6c2c45e8	2452	#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /!< Interrupt Mask on line 15 /
mbed_official	5:ac9f6c2c45e8	2453	#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /!< Interrupt Mask on line 16 /
mbed_official	5:ac9f6c2c45e8	2454	#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /!< Interrupt Mask on line 17 /
mbed_official	5:ac9f6c2c45e8	2455	#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /!< Interrupt Mask on line 19 /
mbed_official	5:ac9f6c2c45e8	2456	#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /!< Interrupt Mask on line 21 /
mbed_official	5:ac9f6c2c45e8	2457	#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /!< Interrupt Mask on line 22 /
mbed_official	5:ac9f6c2c45e8	2458	#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /!< Interrupt Mask on line 23 /
mbed_official	5:ac9f6c2c45e8	2459	#define EXTI_IMR_MR25 ((uint32_t)0x02000000) /!< Interrupt Mask on line 25 /
mbed_official	5:ac9f6c2c45e8	2460	#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /!< Interrupt Mask on line 27 /
mbed_official	5:ac9f6c2c45e8	2461	#define EXTI_IMR_MR31 ((uint32_t)0x80000000) /!< Interrupt Mask on line 31 /
mbed_official	5:ac9f6c2c45e8	2462
mbed_official	5:ac9f6c2c45e8	2463	/**************** Bit definition for EXTI_EMR register ******************/
mbed_official	5:ac9f6c2c45e8	2464	#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /!< Event Mask on line 0 /
mbed_official	5:ac9f6c2c45e8	2465	#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /!< Event Mask on line 1 /
mbed_official	5:ac9f6c2c45e8	2466	#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /!< Event Mask on line 2 /
mbed_official	5:ac9f6c2c45e8	2467	#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /!< Event Mask on line 3 /
mbed_official	5:ac9f6c2c45e8	2468	#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /!< Event Mask on line 4 /
mbed_official	5:ac9f6c2c45e8	2469	#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /!< Event Mask on line 5 /
mbed_official	5:ac9f6c2c45e8	2470	#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /!< Event Mask on line 6 /
mbed_official	5:ac9f6c2c45e8	2471	#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /!< Event Mask on line 7 /
mbed_official	5:ac9f6c2c45e8	2472	#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /!< Event Mask on line 8 /
mbed_official	5:ac9f6c2c45e8	2473	#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /!< Event Mask on line 9 /
mbed_official	5:ac9f6c2c45e8	2474	#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /!< Event Mask on line 10 /
mbed_official	5:ac9f6c2c45e8	2475	#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /!< Event Mask on line 11 /
mbed_official	5:ac9f6c2c45e8	2476	#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /!< Event Mask on line 12 /
mbed_official	5:ac9f6c2c45e8	2477	#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /!< Event Mask on line 13 /
mbed_official	5:ac9f6c2c45e8	2478	#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /!< Event Mask on line 14 /
mbed_official	5:ac9f6c2c45e8	2479	#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /!< Event Mask on line 15 /
mbed_official	5:ac9f6c2c45e8	2480	#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /!< Event Mask on line 16 /
mbed_official	5:ac9f6c2c45e8	2481	#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /!< Event Mask on line 17 /
mbed_official	5:ac9f6c2c45e8	2482	#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /!< Event Mask on line 19 /
mbed_official	5:ac9f6c2c45e8	2483	#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /!< Event Mask on line 21 /
mbed_official	5:ac9f6c2c45e8	2484	#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /!< Event Mask on line 22 /
mbed_official	5:ac9f6c2c45e8	2485	#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /!< Event Mask on line 23 /
mbed_official	5:ac9f6c2c45e8	2486	#define EXTI_EMR_MR25 ((uint32_t)0x02000000) /!< Event Mask on line 25 /
mbed_official	5:ac9f6c2c45e8	2487	#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /!< Event Mask on line 27 /
mbed_official	5:ac9f6c2c45e8	2488
mbed_official	5:ac9f6c2c45e8	2489	/***************** Bit definition for EXTI_RTSR register ****************/
mbed_official	5:ac9f6c2c45e8	2490	#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /!< Rising trigger event configuration bit of line 0 /
mbed_official	5:ac9f6c2c45e8	2491	#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /!< Rising trigger event configuration bit of line 1 /
mbed_official	5:ac9f6c2c45e8	2492	#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /!< Rising trigger event configuration bit of line 2 /
mbed_official	5:ac9f6c2c45e8	2493	#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /!< Rising trigger event configuration bit of line 3 /
mbed_official	5:ac9f6c2c45e8	2494	#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /!< Rising trigger event configuration bit of line 4 /
mbed_official	5:ac9f6c2c45e8	2495	#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /!< Rising trigger event configuration bit of line 5 /
mbed_official	5:ac9f6c2c45e8	2496	#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /!< Rising trigger event configuration bit of line 6 /
mbed_official	5:ac9f6c2c45e8	2497	#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /!< Rising trigger event configuration bit of line 7 /
mbed_official	5:ac9f6c2c45e8	2498	#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /!< Rising trigger event configuration bit of line 8 /
mbed_official	5:ac9f6c2c45e8	2499	#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /!< Rising trigger event configuration bit of line 9 /
mbed_official	5:ac9f6c2c45e8	2500	#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /!< Rising trigger event configuration bit of line 10 /
mbed_official	5:ac9f6c2c45e8	2501	#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /!< Rising trigger event configuration bit of line 11 /
mbed_official	5:ac9f6c2c45e8	2502	#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /!< Rising trigger event configuration bit of line 12 /
mbed_official	5:ac9f6c2c45e8	2503	#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /!< Rising trigger event configuration bit of line 13 /
mbed_official	5:ac9f6c2c45e8	2504	#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /!< Rising trigger event configuration bit of line 14 /
mbed_official	5:ac9f6c2c45e8	2505	#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /!< Rising trigger event configuration bit of line 15 /
mbed_official	5:ac9f6c2c45e8	2506	#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /!< Rising trigger event configuration bit of line 16 /
mbed_official	5:ac9f6c2c45e8	2507	#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /!< Rising trigger event configuration bit of line 17 /
mbed_official	5:ac9f6c2c45e8	2508	#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /!< Rising trigger event configuration bit of line 19 /
mbed_official	5:ac9f6c2c45e8	2509
mbed_official	5:ac9f6c2c45e8	2510	/***************** Bit definition for EXTI_FTSR register *****************/
mbed_official	5:ac9f6c2c45e8	2511	#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /!< Falling trigger event configuration bit of line 0 /
mbed_official	5:ac9f6c2c45e8	2512	#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /!< Falling trigger event configuration bit of line 1 /
mbed_official	5:ac9f6c2c45e8	2513	#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /!< Falling trigger event configuration bit of line 2 /
mbed_official	5:ac9f6c2c45e8	2514	#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /!< Falling trigger event configuration bit of line 3 /
mbed_official	5:ac9f6c2c45e8	2515	#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /!< Falling trigger event configuration bit of line 4 /
mbed_official	5:ac9f6c2c45e8	2516	#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /!< Falling trigger event configuration bit of line 5 /
mbed_official	5:ac9f6c2c45e8	2517	#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /!< Falling trigger event configuration bit of line 6 /
mbed_official	5:ac9f6c2c45e8	2518	#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /!< Falling trigger event configuration bit of line 7 /
mbed_official	5:ac9f6c2c45e8	2519	#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /!< Falling trigger event configuration bit of line 8 /
mbed_official	5:ac9f6c2c45e8	2520	#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /!< Falling trigger event configuration bit of line 9 /
mbed_official	5:ac9f6c2c45e8	2521	#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /!< Falling trigger event configuration bit of line 10 /
mbed_official	5:ac9f6c2c45e8	2522	#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /!< Falling trigger event configuration bit of line 11 /
mbed_official	5:ac9f6c2c45e8	2523	#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /!< Falling trigger event configuration bit of line 12 /
mbed_official	5:ac9f6c2c45e8	2524	#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /!< Falling trigger event configuration bit of line 13 /
mbed_official	5:ac9f6c2c45e8	2525	#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /!< Falling trigger event configuration bit of line 14 /
mbed_official	5:ac9f6c2c45e8	2526	#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /!< Falling trigger event configuration bit of line 15 /
mbed_official	5:ac9f6c2c45e8	2527	#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /!< Falling trigger event configuration bit of line 16 /
mbed_official	5:ac9f6c2c45e8	2528	#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /!< Falling trigger event configuration bit of line 17 /
mbed_official	5:ac9f6c2c45e8	2529	#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /!< Falling trigger event configuration bit of line 19 /
mbed_official	5:ac9f6c2c45e8	2530
mbed_official	5:ac9f6c2c45e8	2531	/***************** Bit definition for EXTI_SWIER register *****************/
mbed_official	5:ac9f6c2c45e8	2532	#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /!< Software Interrupt on line 0 /
mbed_official	5:ac9f6c2c45e8	2533	#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /!< Software Interrupt on line 1 /
mbed_official	5:ac9f6c2c45e8	2534	#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /!< Software Interrupt on line 2 /
mbed_official	5:ac9f6c2c45e8	2535	#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /!< Software Interrupt on line 3 /
mbed_official	5:ac9f6c2c45e8	2536	#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /!< Software Interrupt on line 4 /
mbed_official	5:ac9f6c2c45e8	2537	#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /!< Software Interrupt on line 5 /
mbed_official	5:ac9f6c2c45e8	2538	#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /!< Software Interrupt on line 6 /
mbed_official	5:ac9f6c2c45e8	2539	#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /!< Software Interrupt on line 7 /
mbed_official	5:ac9f6c2c45e8	2540	#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /!< Software Interrupt on line 8 /
mbed_official	5:ac9f6c2c45e8	2541	#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /!< Software Interrupt on line 9 /
mbed_official	5:ac9f6c2c45e8	2542	#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /!< Software Interrupt on line 10 /
mbed_official	5:ac9f6c2c45e8	2543	#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /!< Software Interrupt on line 11 /
mbed_official	5:ac9f6c2c45e8	2544	#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /!< Software Interrupt on line 12 /
mbed_official	5:ac9f6c2c45e8	2545	#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /!< Software Interrupt on line 13 /
mbed_official	5:ac9f6c2c45e8	2546	#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /!< Software Interrupt on line 14 /
mbed_official	5:ac9f6c2c45e8	2547	#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /!< Software Interrupt on line 15 /
mbed_official	5:ac9f6c2c45e8	2548	#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /!< Software Interrupt on line 16 /
mbed_official	5:ac9f6c2c45e8	2549	#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /!< Software Interrupt on line 17 /
mbed_official	5:ac9f6c2c45e8	2550	#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /!< Software Interrupt on line 19 /
mbed_official	5:ac9f6c2c45e8	2551
mbed_official	5:ac9f6c2c45e8	2552	/**************** Bit definition for EXTI_PR register *******************/
mbed_official	5:ac9f6c2c45e8	2553	#define EXTI_PR_PR0 ((uint32_t)0x00000001) /!< Pending bit 0 /
mbed_official	5:ac9f6c2c45e8	2554	#define EXTI_PR_PR1 ((uint32_t)0x00000002) /!< Pending bit 1 /
mbed_official	5:ac9f6c2c45e8	2555	#define EXTI_PR_PR2 ((uint32_t)0x00000004) /!< Pending bit 2 /
mbed_official	5:ac9f6c2c45e8	2556	#define EXTI_PR_PR3 ((uint32_t)0x00000008) /!< Pending bit 3 /
mbed_official	5:ac9f6c2c45e8	2557	#define EXTI_PR_PR4 ((uint32_t)0x00000010) /!< Pending bit 4 /
mbed_official	5:ac9f6c2c45e8	2558	#define EXTI_PR_PR5 ((uint32_t)0x00000020) /!< Pending bit 5 /
mbed_official	5:ac9f6c2c45e8	2559	#define EXTI_PR_PR6 ((uint32_t)0x00000040) /!< Pending bit 6 /
mbed_official	5:ac9f6c2c45e8	2560	#define EXTI_PR_PR7 ((uint32_t)0x00000080) /!< Pending bit 7 /
mbed_official	5:ac9f6c2c45e8	2561	#define EXTI_PR_PR8 ((uint32_t)0x00000100) /!< Pending bit 8 /
mbed_official	5:ac9f6c2c45e8	2562	#define EXTI_PR_PR9 ((uint32_t)0x00000200) /!< Pending bit 9 /
mbed_official	5:ac9f6c2c45e8	2563	#define EXTI_PR_PR10 ((uint32_t)0x00000400) /!< Pending bit 10 /
mbed_official	5:ac9f6c2c45e8	2564	#define EXTI_PR_PR11 ((uint32_t)0x00000800) /!< Pending bit 11 /
mbed_official	5:ac9f6c2c45e8	2565	#define EXTI_PR_PR12 ((uint32_t)0x00001000) /!< Pending bit 12 /
mbed_official	5:ac9f6c2c45e8	2566	#define EXTI_PR_PR13 ((uint32_t)0x00002000) /!< Pending bit 13 /
mbed_official	5:ac9f6c2c45e8	2567	#define EXTI_PR_PR14 ((uint32_t)0x00004000) /!< Pending bit 14 /
mbed_official	5:ac9f6c2c45e8	2568	#define EXTI_PR_PR15 ((uint32_t)0x00008000) /!< Pending bit 15 /
mbed_official	5:ac9f6c2c45e8	2569	#define EXTI_PR_PR16 ((uint32_t)0x00010000) /!< Pending bit 16 /
mbed_official	5:ac9f6c2c45e8	2570	#define EXTI_PR_PR17 ((uint32_t)0x00020000) /!< Pending bit 17 /
mbed_official	5:ac9f6c2c45e8	2571	#define EXTI_PR_PR19 ((uint32_t)0x00080000) /!< Pending bit 19 /
mbed_official	5:ac9f6c2c45e8	2572
mbed_official	5:ac9f6c2c45e8	2573	/******************************************************************************/
mbed_official	5:ac9f6c2c45e8	2574	/* */
mbed_official	5:ac9f6c2c45e8	2575	/* FLASH and Option Bytes Registers */
mbed_official	5:ac9f6c2c45e8	2576	/* */
mbed_official	5:ac9f6c2c45e8	2577	/******************************************************************************/
mbed_official	5:ac9f6c2c45e8	2578
mbed_official	5:ac9f6c2c45e8	2579	/***************** Bit definition for FLASH_ACR register ****************/
mbed_official	5:ac9f6c2c45e8	2580	#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /!< LATENCY bit (Latency) /
mbed_official	5:ac9f6c2c45e8	2581
mbed_official	5:ac9f6c2c45e8	2582	#define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /!< Prefetch Buffer Enable /
mbed_official	5:ac9f6c2c45e8	2583	#define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /!< Prefetch Buffer Status /
mbed_official	5:ac9f6c2c45e8	2584
mbed_official	5:ac9f6c2c45e8	2585	/**************** Bit definition for FLASH_KEYR register ****************/
mbed_official	5:ac9f6c2c45e8	2586	#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /!< FPEC Key /
mbed_official	5:ac9f6c2c45e8	2587
mbed_official	5:ac9f6c2c45e8	2588	/*************** Bit definition for FLASH_OPTKEYR register **************/
mbed_official	5:ac9f6c2c45e8	2589	#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /!< Option Byte Key /
mbed_official	5:ac9f6c2c45e8	2590
mbed_official	5:ac9f6c2c45e8	2591	/**************** FLASH Keys ********************************************/
mbed_official	5:ac9f6c2c45e8	2592	#define FLASH_KEY1 ((uint32_t)0x45670123) /!< Flash program erase key1 /
mbed_official	5:ac9f6c2c45e8	2593	#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
mbed_official	5:ac9f6c2c45e8	2594	to unlock the write access to the FPEC. */
mbed_official	5:ac9f6c2c45e8	2595
mbed_official	5:ac9f6c2c45e8	2596	#define FLASH_OPTKEY1 ((uint32_t)0x45670123) /!< Flash option key1 /
mbed_official	5:ac9f6c2c45e8	2597	#define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to
mbed_official	5:ac9f6c2c45e8	2598	unlock the write access to the option byte block */
mbed_official	5:ac9f6c2c45e8	2599
mbed_official	5:ac9f6c2c45e8	2600	/**************** Bit definition for FLASH_SR register *****************/
mbed_official	5:ac9f6c2c45e8	2601	#define FLASH_SR_BSY ((uint32_t)0x00000001) /!< Busy /
mbed_official	5:ac9f6c2c45e8	2602	#define FLASH_SR_PGERR ((uint32_t)0x00000004) /!< Programming Error /
mbed_official	5:ac9f6c2c45e8	2603	#define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /!< Write Protection Error /
mbed_official	5:ac9f6c2c45e8	2604	#define FLASH_SR_EOP ((uint32_t)0x00000020) /!< End of operation /
mbed_official	5:ac9f6c2c45e8	2605	#define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /!< Legacy of Write Protection Error /
mbed_official	5:ac9f6c2c45e8	2606
mbed_official	5:ac9f6c2c45e8	2607	/***************** Bit definition for FLASH_CR register *****************/
mbed_official	5:ac9f6c2c45e8	2608	#define FLASH_CR_PG ((uint32_t)0x00000001) /!< Programming /
mbed_official	5:ac9f6c2c45e8	2609	#define FLASH_CR_PER ((uint32_t)0x00000002) /!< Page Erase /
mbed_official	5:ac9f6c2c45e8	2610	#define FLASH_CR_MER ((uint32_t)0x00000004) /!< Mass Erase /
mbed_official	5:ac9f6c2c45e8	2611	#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /!< Option Byte Programming /
mbed_official	5:ac9f6c2c45e8	2612	#define FLASH_CR_OPTER ((uint32_t)0x00000020) /!< Option Byte Erase /
mbed_official	5:ac9f6c2c45e8	2613	#define FLASH_CR_STRT ((uint32_t)0x00000040) /!< Start /
mbed_official	5:ac9f6c2c45e8	2614	#define FLASH_CR_LOCK ((uint32_t)0x00000080) /!< Lock /
mbed_official	5:ac9f6c2c45e8	2615	#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /!< Option Bytes Write Enable /
mbed_official	5:ac9f6c2c45e8	2616	#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /!< Error Interrupt Enable /
mbed_official	5:ac9f6c2c45e8	2617	#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /!< End of operation interrupt enable /
mbed_official	5:ac9f6c2c45e8	2618	#define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /!< Option Bytes Loader Launch /
mbed_official	5:ac9f6c2c45e8	2619
mbed_official	5:ac9f6c2c45e8	2620	/***************** Bit definition for FLASH_AR register *****************/
mbed_official	5:ac9f6c2c45e8	2621	#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /!< Flash Address /
mbed_official	5:ac9f6c2c45e8	2622
mbed_official	5:ac9f6c2c45e8	2623	/**************** Bit definition for FLASH_OBR register *****************/
mbed_official	5:ac9f6c2c45e8	2624	#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /!< Option Byte Error /
mbed_official	5:ac9f6c2c45e8	2625	#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /!< Read protection Level 1 /
mbed_official	5:ac9f6c2c45e8	2626	#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /!< Read protection Level 2 /
mbed_official	5:ac9f6c2c45e8	2627
mbed_official	5:ac9f6c2c45e8	2628	#define FLASH_OBR_USER ((uint32_t)0x0000FF00) /!< User Option Bytes /
mbed_official	5:ac9f6c2c45e8	2629	#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /!< IWDG SW /
mbed_official	5:ac9f6c2c45e8	2630	#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /!< nRST_STOP /
mbed_official	5:ac9f6c2c45e8	2631	#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /!< nRST_STDBY /
mbed_official	5:ac9f6c2c45e8	2632	#define FLASH_OBR_nBOOT0 ((uint32_t)0x00001000) /!< nBOOT0 /
mbed_official	5:ac9f6c2c45e8	2633	#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /!< nBOOT1 /
mbed_official	5:ac9f6c2c45e8	2634	#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /!< VDDA power supply supervisor /
mbed_official	5:ac9f6c2c45e8	2635	#define FLASH_OBR_RAM_PARITY_CHECK ((uint32_t)0x00004000) /!< RAM parity check /
mbed_official	5:ac9f6c2c45e8	2636	#define FLASH_OBR_BOOT_SEL ((uint32_t)0x00008000) /!< BOOT selection /
mbed_official	5:ac9f6c2c45e8	2637
mbed_official	5:ac9f6c2c45e8	2638	/* Old BOOT1 bit definition, maintained for legacy purpose */
mbed_official	5:ac9f6c2c45e8	2639	#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
mbed_official	5:ac9f6c2c45e8	2640
mbed_official	5:ac9f6c2c45e8	2641	/* Old OBR_VDDA bit definition, maintained for legacy purpose */
mbed_official	5:ac9f6c2c45e8	2642	#define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
mbed_official	5:ac9f6c2c45e8	2643
mbed_official	5:ac9f6c2c45e8	2644	/**************** Bit definition for FLASH_WRPR register ****************/
mbed_official	5:ac9f6c2c45e8	2645	#define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /!< Write Protect /
mbed_official	5:ac9f6c2c45e8	2646
mbed_official	5:ac9f6c2c45e8	2647	/----------------------------------------------------------------------------/
mbed_official	5:ac9f6c2c45e8	2648
mbed_official	5:ac9f6c2c45e8	2649	/**************** Bit definition for OB_RDP register ********************/
mbed_official	5:ac9f6c2c45e8	2650	#define OB_RDP_RDP ((uint32_t)0x000000FF) /!< Read protection option byte /
mbed_official	5:ac9f6c2c45e8	2651	#define OB_RDP_nRDP ((uint32_t)0x0000FF00) /!< Read protection complemented option byte /
mbed_official	5:ac9f6c2c45e8	2652
mbed_official	5:ac9f6c2c45e8	2653	/**************** Bit definition for OB_USER register *******************/
mbed_official	5:ac9f6c2c45e8	2654	#define OB_USER_USER ((uint32_t)0x00FF0000) /!< User option byte /
mbed_official	5:ac9f6c2c45e8	2655	#define OB_USER_nUSER ((uint32_t)0xFF000000) /!< User complemented option byte /
mbed_official	5:ac9f6c2c45e8	2656
mbed_official	5:ac9f6c2c45e8	2657	/**************** Bit definition for OB_WRP0 register *******************/
mbed_official	5:ac9f6c2c45e8	2658	#define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /!< Flash memory write protection option bytes /
mbed_official	5:ac9f6c2c45e8	2659	#define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /!< Flash memory write protection complemented option bytes /
mbed_official	5:ac9f6c2c45e8	2660
mbed_official	5:ac9f6c2c45e8	2661	/******************************************************************************/
mbed_official	5:ac9f6c2c45e8	2662	/* */
mbed_official	5:ac9f6c2c45e8	2663	/* General Purpose IOs (GPIO) */
mbed_official	5:ac9f6c2c45e8	2664	/* */
mbed_official	5:ac9f6c2c45e8	2665	/******************************************************************************/
mbed_official	5:ac9f6c2c45e8	2666	/***************** Bit definition for GPIO_MODER register ***************/
mbed_official	5:ac9f6c2c45e8	2667	#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
mbed_official	5:ac9f6c2c45e8	2668	#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
mbed_official	5:ac9f6c2c45e8	2669	#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
mbed_official	5:ac9f6c2c45e8	2670	#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
mbed_official	5:ac9f6c2c45e8	2671	#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
mbed_official	5:ac9f6c2c45e8	2672	#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
mbed_official	5:ac9f6c2c45e8	2673	#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
mbed_official	5:ac9f6c2c45e8	2674	#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
mbed_official	5:ac9f6c2c45e8	2675	#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
mbed_official	5:ac9f6c2c45e8	2676	#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
mbed_official	5:ac9f6c2c45e8	2677	#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
mbed_official	5:ac9f6c2c45e8	2678	#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
mbed_official	5:ac9f6c2c45e8	2679	#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
mbed_official	5:ac9f6c2c45e8	2680	#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
mbed_official	5:ac9f6c2c45e8	2681	#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
mbed_official	5:ac9f6c2c45e8	2682	#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
mbed_official	5:ac9f6c2c45e8	2683	#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
mbed_official	5:ac9f6c2c45e8	2684	#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
mbed_official	5:ac9f6c2c45e8	2685	#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
mbed_official	5:ac9f6c2c45e8	2686	#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
mbed_official	5:ac9f6c2c45e8	2687	#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
mbed_official	5:ac9f6c2c45e8	2688	#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
mbed_official	5:ac9f6c2c45e8	2689	#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
mbed_official	5:ac9f6c2c45e8	2690	#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
mbed_official	5:ac9f6c2c45e8	2691	#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
mbed_official	5:ac9f6c2c45e8	2692	#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
mbed_official	5:ac9f6c2c45e8	2693	#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
mbed_official	5:ac9f6c2c45e8	2694	#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
mbed_official	5:ac9f6c2c45e8	2695	#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
mbed_official	5:ac9f6c2c45e8	2696	#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
mbed_official	5:ac9f6c2c45e8	2697	#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
mbed_official	5:ac9f6c2c45e8	2698	#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
mbed_official	5:ac9f6c2c45e8	2699	#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
mbed_official	5:ac9f6c2c45e8	2700	#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
mbed_official	5:ac9f6c2c45e8	2701	#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
mbed_official	5:ac9f6c2c45e8	2702	#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
mbed_official	5:ac9f6c2c45e8	2703	#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
mbed_official	5:ac9f6c2c45e8	2704	#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
mbed_official	5:ac9f6c2c45e8	2705	#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
mbed_official	5:ac9f6c2c45e8	2706	#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
mbed_official	5:ac9f6c2c45e8	2707	#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
mbed_official	5:ac9f6c2c45e8	2708	#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
mbed_official	5:ac9f6c2c45e8	2709	#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
mbed_official	5:ac9f6c2c45e8	2710	#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
mbed_official	5:ac9f6c2c45e8	2711	#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
mbed_official	5:ac9f6c2c45e8	2712	#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
mbed_official	5:ac9f6c2c45e8	2713	#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
mbed_official	5:ac9f6c2c45e8	2714	#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
mbed_official	5:ac9f6c2c45e8	2715
mbed_official	5:ac9f6c2c45e8	2716	/**************** Bit definition for GPIO_OTYPER register ***************/
mbed_official	5:ac9f6c2c45e8	2717	#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
mbed_official	5:ac9f6c2c45e8	2718	#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
mbed_official	5:ac9f6c2c45e8	2719	#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
mbed_official	5:ac9f6c2c45e8	2720	#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
mbed_official	5:ac9f6c2c45e8	2721	#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
mbed_official	5:ac9f6c2c45e8	2722	#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
mbed_official	5:ac9f6c2c45e8	2723	#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
mbed_official	5:ac9f6c2c45e8	2724	#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
mbed_official	5:ac9f6c2c45e8	2725	#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
mbed_official	5:ac9f6c2c45e8	2726	#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
mbed_official	5:ac9f6c2c45e8	2727	#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
mbed_official	5:ac9f6c2c45e8	2728	#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
mbed_official	5:ac9f6c2c45e8	2729	#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
mbed_official	5:ac9f6c2c45e8	2730	#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
mbed_official	5:ac9f6c2c45e8	2731	#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
mbed_official	5:ac9f6c2c45e8	2732	#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
mbed_official	5:ac9f6c2c45e8	2733
mbed_official	5:ac9f6c2c45e8	2734	/************** Bit definition for GPIO_OSPEEDR register ****************/
mbed_official	5:ac9f6c2c45e8	2735	#define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003)
mbed_official	5:ac9f6c2c45e8	2736	#define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001)
mbed_official	5:ac9f6c2c45e8	2737	#define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002)
mbed_official	5:ac9f6c2c45e8	2738	#define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C)
mbed_official	5:ac9f6c2c45e8	2739	#define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004)
mbed_official	5:ac9f6c2c45e8	2740	#define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008)
mbed_official	5:ac9f6c2c45e8	2741	#define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030)
mbed_official	5:ac9f6c2c45e8	2742	#define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010)
mbed_official	5:ac9f6c2c45e8	2743	#define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020)
mbed_official	5:ac9f6c2c45e8	2744	#define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0)
mbed_official	5:ac9f6c2c45e8	2745	#define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040)
mbed_official	5:ac9f6c2c45e8	2746	#define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080)
mbed_official	5:ac9f6c2c45e8	2747	#define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300)
mbed_official	5:ac9f6c2c45e8	2748	#define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100)
mbed_official	5:ac9f6c2c45e8	2749	#define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200)
mbed_official	5:ac9f6c2c45e8	2750	#define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00)
mbed_official	5:ac9f6c2c45e8	2751	#define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400)
mbed_official	5:ac9f6c2c45e8	2752	#define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800)
mbed_official	5:ac9f6c2c45e8	2753	#define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000)
mbed_official	5:ac9f6c2c45e8	2754	#define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000)
mbed_official	5:ac9f6c2c45e8	2755	#define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000)
mbed_official	5:ac9f6c2c45e8	2756	#define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000)
mbed_official	5:ac9f6c2c45e8	2757	#define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000)
mbed_official	5:ac9f6c2c45e8	2758	#define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000)
mbed_official	5:ac9f6c2c45e8	2759	#define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000)
mbed_official	5:ac9f6c2c45e8	2760	#define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000)
mbed_official	5:ac9f6c2c45e8	2761	#define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000)
mbed_official	5:ac9f6c2c45e8	2762	#define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000)
mbed_official	5:ac9f6c2c45e8	2763	#define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000)
mbed_official	5:ac9f6c2c45e8	2764	#define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000)
mbed_official	5:ac9f6c2c45e8	2765	#define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000)
mbed_official	5:ac9f6c2c45e8	2766	#define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000)
mbed_official	5:ac9f6c2c45e8	2767	#define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000)
mbed_official	5:ac9f6c2c45e8	2768	#define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000)
mbed_official	5:ac9f6c2c45e8	2769	#define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000)
mbed_official	5:ac9f6c2c45e8	2770	#define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000)
mbed_official	5:ac9f6c2c45e8	2771	#define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000)
mbed_official	5:ac9f6c2c45e8	2772	#define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000)
mbed_official	5:ac9f6c2c45e8	2773	#define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000)
mbed_official	5:ac9f6c2c45e8	2774	#define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000)
mbed_official	5:ac9f6c2c45e8	2775	#define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000)
mbed_official	5:ac9f6c2c45e8	2776	#define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000)
mbed_official	5:ac9f6c2c45e8	2777	#define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000)
mbed_official	5:ac9f6c2c45e8	2778	#define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000)
mbed_official	5:ac9f6c2c45e8	2779	#define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000)
mbed_official	5:ac9f6c2c45e8	2780	#define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000)
mbed_official	5:ac9f6c2c45e8	2781	#define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000)
mbed_official	5:ac9f6c2c45e8	2782	#define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000)
mbed_official	5:ac9f6c2c45e8	2783
mbed_official	5:ac9f6c2c45e8	2784	/* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
mbed_official	5:ac9f6c2c45e8	2785	#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
mbed_official	5:ac9f6c2c45e8	2786	#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
mbed_official	5:ac9f6c2c45e8	2787	#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
mbed_official	5:ac9f6c2c45e8	2788	#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
mbed_official	5:ac9f6c2c45e8	2789	#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
mbed_official	5:ac9f6c2c45e8	2790	#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
mbed_official	5:ac9f6c2c45e8	2791	#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
mbed_official	5:ac9f6c2c45e8	2792	#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
mbed_official	5:ac9f6c2c45e8	2793	#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
mbed_official	5:ac9f6c2c45e8	2794	#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
mbed_official	5:ac9f6c2c45e8	2795	#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
mbed_official	5:ac9f6c2c45e8	2796	#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
mbed_official	5:ac9f6c2c45e8	2797	#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
mbed_official	5:ac9f6c2c45e8	2798	#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
mbed_official	5:ac9f6c2c45e8	2799	#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
mbed_official	5:ac9f6c2c45e8	2800	#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
mbed_official	5:ac9f6c2c45e8	2801	#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
mbed_official	5:ac9f6c2c45e8	2802	#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
mbed_official	5:ac9f6c2c45e8	2803	#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
mbed_official	5:ac9f6c2c45e8	2804	#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
mbed_official	5:ac9f6c2c45e8	2805	#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
mbed_official	5:ac9f6c2c45e8	2806	#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
mbed_official	5:ac9f6c2c45e8	2807	#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
mbed_official	5:ac9f6c2c45e8	2808	#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
mbed_official	5:ac9f6c2c45e8	2809	#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
mbed_official	5:ac9f6c2c45e8	2810	#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
mbed_official	5:ac9f6c2c45e8	2811	#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
mbed_official	5:ac9f6c2c45e8	2812	#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
mbed_official	5:ac9f6c2c45e8	2813	#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
mbed_official	5:ac9f6c2c45e8	2814	#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
mbed_official	5:ac9f6c2c45e8	2815	#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
mbed_official	5:ac9f6c2c45e8	2816	#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
mbed_official	5:ac9f6c2c45e8	2817	#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
mbed_official	5:ac9f6c2c45e8	2818	#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
mbed_official	5:ac9f6c2c45e8	2819	#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
mbed_official	5:ac9f6c2c45e8	2820	#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
mbed_official	5:ac9f6c2c45e8	2821	#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
mbed_official	5:ac9f6c2c45e8	2822	#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
mbed_official	5:ac9f6c2c45e8	2823	#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
mbed_official	5:ac9f6c2c45e8	2824	#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
mbed_official	5:ac9f6c2c45e8	2825	#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
mbed_official	5:ac9f6c2c45e8	2826	#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
mbed_official	5:ac9f6c2c45e8	2827	#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
mbed_official	5:ac9f6c2c45e8	2828	#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
mbed_official	5:ac9f6c2c45e8	2829	#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
mbed_official	5:ac9f6c2c45e8	2830	#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
mbed_official	5:ac9f6c2c45e8	2831	#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
mbed_official	5:ac9f6c2c45e8	2832	#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
mbed_official	5:ac9f6c2c45e8	2833
mbed_official	5:ac9f6c2c45e8	2834	/***************** Bit definition for GPIO_PUPDR register ****************/
mbed_official	5:ac9f6c2c45e8	2835	#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
mbed_official	5:ac9f6c2c45e8	2836	#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
mbed_official	5:ac9f6c2c45e8	2837	#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
mbed_official	5:ac9f6c2c45e8	2838	#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
mbed_official	5:ac9f6c2c45e8	2839	#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
mbed_official	5:ac9f6c2c45e8	2840	#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
mbed_official	5:ac9f6c2c45e8	2841	#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
mbed_official	5:ac9f6c2c45e8	2842	#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
mbed_official	5:ac9f6c2c45e8	2843	#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
mbed_official	5:ac9f6c2c45e8	2844	#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
mbed_official	5:ac9f6c2c45e8	2845	#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
mbed_official	5:ac9f6c2c45e8	2846	#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
mbed_official	5:ac9f6c2c45e8	2847	#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
mbed_official	5:ac9f6c2c45e8	2848	#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
mbed_official	5:ac9f6c2c45e8	2849	#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
mbed_official	5:ac9f6c2c45e8	2850	#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
mbed_official	5:ac9f6c2c45e8	2851	#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
mbed_official	5:ac9f6c2c45e8	2852	#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
mbed_official	5:ac9f6c2c45e8	2853	#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
mbed_official	5:ac9f6c2c45e8	2854	#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
mbed_official	5:ac9f6c2c45e8	2855	#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
mbed_official	5:ac9f6c2c45e8	2856	#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
mbed_official	5:ac9f6c2c45e8	2857	#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
mbed_official	5:ac9f6c2c45e8	2858	#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
mbed_official	5:ac9f6c2c45e8	2859	#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
mbed_official	5:ac9f6c2c45e8	2860	#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
mbed_official	5:ac9f6c2c45e8	2861	#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
mbed_official	5:ac9f6c2c45e8	2862	#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
mbed_official	5:ac9f6c2c45e8	2863	#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
mbed_official	5:ac9f6c2c45e8	2864	#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
mbed_official	5:ac9f6c2c45e8	2865	#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
mbed_official	5:ac9f6c2c45e8	2866	#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
mbed_official	5:ac9f6c2c45e8	2867	#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
mbed_official	5:ac9f6c2c45e8	2868	#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
mbed_official	5:ac9f6c2c45e8	2869	#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
mbed_official	5:ac9f6c2c45e8	2870	#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
mbed_official	5:ac9f6c2c45e8	2871	#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
mbed_official	5:ac9f6c2c45e8	2872	#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
mbed_official	5:ac9f6c2c45e8	2873	#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
mbed_official	5:ac9f6c2c45e8	2874	#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
mbed_official	5:ac9f6c2c45e8	2875	#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
mbed_official	5:ac9f6c2c45e8	2876	#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
mbed_official	5:ac9f6c2c45e8	2877	#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
mbed_official	5:ac9f6c2c45e8	2878	#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
mbed_official	5:ac9f6c2c45e8	2879	#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
mbed_official	5:ac9f6c2c45e8	2880	#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
mbed_official	5:ac9f6c2c45e8	2881	#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
mbed_official	5:ac9f6c2c45e8	2882	#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
mbed_official	5:ac9f6c2c45e8	2883
mbed_official	5:ac9f6c2c45e8	2884	/***************** Bit definition for GPIO_IDR register *****************/
mbed_official	5:ac9f6c2c45e8	2885	#define GPIO_IDR_0 ((uint32_t)0x00000001)
mbed_official	5:ac9f6c2c45e8	2886	#define GPIO_IDR_1 ((uint32_t)0x00000002)
mbed_official	5:ac9f6c2c45e8	2887	#define GPIO_IDR_2 ((uint32_t)0x00000004)
mbed_official	5:ac9f6c2c45e8	2888	#define GPIO_IDR_3 ((uint32_t)0x00000008)
mbed_official	5:ac9f6c2c45e8	2889	#define GPIO_IDR_4 ((uint32_t)0x00000010)
mbed_official	5:ac9f6c2c45e8	2890	#define GPIO_IDR_5 ((uint32_t)0x00000020)
mbed_official	5:ac9f6c2c45e8	2891	#define GPIO_IDR_6 ((uint32_t)0x00000040)
mbed_official	5:ac9f6c2c45e8	2892	#define GPIO_IDR_7 ((uint32_t)0x00000080)
mbed_official	5:ac9f6c2c45e8	2893	#define GPIO_IDR_8 ((uint32_t)0x00000100)
mbed_official	5:ac9f6c2c45e8	2894	#define GPIO_IDR_9 ((uint32_t)0x00000200)
mbed_official	5:ac9f6c2c45e8	2895	#define GPIO_IDR_10 ((uint32_t)0x00000400)
mbed_official	5:ac9f6c2c45e8	2896	#define GPIO_IDR_11 ((uint32_t)0x00000800)
mbed_official	5:ac9f6c2c45e8	2897	#define GPIO_IDR_12 ((uint32_t)0x00001000)
mbed_official	5:ac9f6c2c45e8	2898	#define GPIO_IDR_13 ((uint32_t)0x00002000)
mbed_official	5:ac9f6c2c45e8	2899	#define GPIO_IDR_14 ((uint32_t)0x00004000)
mbed_official	5:ac9f6c2c45e8	2900	#define GPIO_IDR_15 ((uint32_t)0x00008000)
mbed_official	5:ac9f6c2c45e8	2901
mbed_official	5:ac9f6c2c45e8	2902	/**************** Bit definition for GPIO_ODR register ******************/
mbed_official	5:ac9f6c2c45e8	2903	#define GPIO_ODR_0 ((uint32_t)0x00000001)
mbed_official	5:ac9f6c2c45e8	2904	#define GPIO_ODR_1 ((uint32_t)0x00000002)
mbed_official	5:ac9f6c2c45e8	2905	#define GPIO_ODR_2 ((uint32_t)0x00000004)
mbed_official	5:ac9f6c2c45e8	2906	#define GPIO_ODR_3 ((uint32_t)0x00000008)
mbed_official	5:ac9f6c2c45e8	2907	#define GPIO_ODR_4 ((uint32_t)0x00000010)
mbed_official	5:ac9f6c2c45e8	2908	#define GPIO_ODR_5 ((uint32_t)0x00000020)
mbed_official	5:ac9f6c2c45e8	2909	#define GPIO_ODR_6 ((uint32_t)0x00000040)
mbed_official	5:ac9f6c2c45e8	2910	#define GPIO_ODR_7 ((uint32_t)0x00000080)
mbed_official	5:ac9f6c2c45e8	2911	#define GPIO_ODR_8 ((uint32_t)0x00000100)
mbed_official	5:ac9f6c2c45e8	2912	#define GPIO_ODR_9 ((uint32_t)0x00000200)
mbed_official	5:ac9f6c2c45e8	2913	#define GPIO_ODR_10 ((uint32_t)0x00000400)
mbed_official	5:ac9f6c2c45e8	2914	#define GPIO_ODR_11 ((uint32_t)0x00000800)
mbed_official	5:ac9f6c2c45e8	2915	#define GPIO_ODR_12 ((uint32_t)0x00001000)
mbed_official	5:ac9f6c2c45e8	2916	#define GPIO_ODR_13 ((uint32_t)0x00002000)
mbed_official	5:ac9f6c2c45e8	2917	#define GPIO_ODR_14 ((uint32_t)0x00004000)
mbed_official	5:ac9f6c2c45e8	2918	#define GPIO_ODR_15 ((uint32_t)0x00008000)
mbed_official	5:ac9f6c2c45e8	2919
mbed_official	5:ac9f6c2c45e8	2920	/**************** Bit definition for GPIO_BSRR register ******************/
mbed_official	5:ac9f6c2c45e8	2921	#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
mbed_official	5:ac9f6c2c45e8	2922	#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
mbed_official	5:ac9f6c2c45e8	2923	#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
mbed_official	5:ac9f6c2c45e8	2924	#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
mbed_official	5:ac9f6c2c45e8	2925	#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
mbed_official	5:ac9f6c2c45e8	2926	#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
mbed_official	5:ac9f6c2c45e8	2927	#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
mbed_official	5:ac9f6c2c45e8	2928	#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
mbed_official	5:ac9f6c2c45e8	2929	#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
mbed_official	5:ac9f6c2c45e8	2930	#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
mbed_official	5:ac9f6c2c45e8	2931	#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
mbed_official	5:ac9f6c2c45e8	2932	#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
mbed_official	5:ac9f6c2c45e8	2933	#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
mbed_official	5:ac9f6c2c45e8	2934	#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
mbed_official	5:ac9f6c2c45e8	2935	#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
mbed_official	5:ac9f6c2c45e8	2936	#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
mbed_official	5:ac9f6c2c45e8	2937	#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
mbed_official	5:ac9f6c2c45e8	2938	#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
mbed_official	5:ac9f6c2c45e8	2939	#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
mbed_official	5:ac9f6c2c45e8	2940	#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
mbed_official	5:ac9f6c2c45e8	2941	#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
mbed_official	5:ac9f6c2c45e8	2942	#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
mbed_official	5:ac9f6c2c45e8	2943	#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
mbed_official	5:ac9f6c2c45e8	2944	#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
mbed_official	5:ac9f6c2c45e8	2945	#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
mbed_official	5:ac9f6c2c45e8	2946	#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
mbed_official	5:ac9f6c2c45e8	2947	#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
mbed_official	5:ac9f6c2c45e8	2948	#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
mbed_official	5:ac9f6c2c45e8	2949	#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
mbed_official	5:ac9f6c2c45e8	2950	#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
mbed_official	5:ac9f6c2c45e8	2951	#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
mbed_official	5:ac9f6c2c45e8	2952	#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
mbed_official	5:ac9f6c2c45e8	2953
mbed_official	5:ac9f6c2c45e8	2954	/**************** Bit definition for GPIO_LCKR register ******************/
mbed_official	5:ac9f6c2c45e8	2955	#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
mbed_official	5:ac9f6c2c45e8	2956	#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
mbed_official	5:ac9f6c2c45e8	2957	#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
mbed_official	5:ac9f6c2c45e8	2958	#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
mbed_official	5:ac9f6c2c45e8	2959	#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
mbed_official	5:ac9f6c2c45e8	2960	#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
mbed_official	5:ac9f6c2c45e8	2961	#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
mbed_official	5:ac9f6c2c45e8	2962	#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
mbed_official	5:ac9f6c2c45e8	2963	#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
mbed_official	5:ac9f6c2c45e8	2964	#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
mbed_official	5:ac9f6c2c45e8	2965	#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
mbed_official	5:ac9f6c2c45e8	2966	#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
mbed_official	5:ac9f6c2c45e8	2967	#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
mbed_official	5:ac9f6c2c45e8	2968	#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
mbed_official	5:ac9f6c2c45e8	2969	#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
mbed_official	5:ac9f6c2c45e8	2970	#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
mbed_official	5:ac9f6c2c45e8	2971	#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
mbed_official	5:ac9f6c2c45e8	2972
mbed_official	5:ac9f6c2c45e8	2973	/**************** Bit definition for GPIO_AFRL register ******************/
mbed_official	5:ac9f6c2c45e8	2974	#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
mbed_official	5:ac9f6c2c45e8	2975	#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
mbed_official	5:ac9f6c2c45e8	2976	#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
mbed_official	5:ac9f6c2c45e8	2977	#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
mbed_official	5:ac9f6c2c45e8	2978	#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
mbed_official	5:ac9f6c2c45e8	2979	#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
mbed_official	5:ac9f6c2c45e8	2980	#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
mbed_official	5:ac9f6c2c45e8	2981	#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
mbed_official	5:ac9f6c2c45e8	2982
mbed_official	5:ac9f6c2c45e8	2983	/**************** Bit definition for GPIO_AFRH register ******************/
mbed_official	5:ac9f6c2c45e8	2984	#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
mbed_official	5:ac9f6c2c45e8	2985	#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
mbed_official	5:ac9f6c2c45e8	2986	#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
mbed_official	5:ac9f6c2c45e8	2987	#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
mbed_official	5:ac9f6c2c45e8	2988	#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
mbed_official	5:ac9f6c2c45e8	2989	#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
mbed_official	5:ac9f6c2c45e8	2990	#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
mbed_official	5:ac9f6c2c45e8	2991	#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
mbed_official	5:ac9f6c2c45e8	2992
mbed_official	5:ac9f6c2c45e8	2993	/**************** Bit definition for GPIO_BRR register *******************/
mbed_official	5:ac9f6c2c45e8	2994	#define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
mbed_official	5:ac9f6c2c45e8	2995	#define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
mbed_official	5:ac9f6c2c45e8	2996	#define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
mbed_official	5:ac9f6c2c45e8	2997	#define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
mbed_official	5:ac9f6c2c45e8	2998	#define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
mbed_official	5:ac9f6c2c45e8	2999	#define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
mbed_official	5:ac9f6c2c45e8	3000	#define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
mbed_official	5:ac9f6c2c45e8	3001	#define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
mbed_official	5:ac9f6c2c45e8	3002	#define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
mbed_official	5:ac9f6c2c45e8	3003	#define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
mbed_official	5:ac9f6c2c45e8	3004	#define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
mbed_official	5:ac9f6c2c45e8	3005	#define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
mbed_official	5:ac9f6c2c45e8	3006	#define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
mbed_official	5:ac9f6c2c45e8	3007	#define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
mbed_official	5:ac9f6c2c45e8	3008	#define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
mbed_official	5:ac9f6c2c45e8	3009	#define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
mbed_official	5:ac9f6c2c45e8	3010
mbed_official	5:ac9f6c2c45e8	3011	/******************************************************************************/
mbed_official	5:ac9f6c2c45e8	3012	/* */
mbed_official	5:ac9f6c2c45e8	3013	/* Inter-integrated Circuit Interface (I2C) */
mbed_official	5:ac9f6c2c45e8	3014	/* */
mbed_official	5:ac9f6c2c45e8	3015	/******************************************************************************/
mbed_official	5:ac9f6c2c45e8	3016
mbed_official	5:ac9f6c2c45e8	3017	/***************** Bit definition for I2C_CR1 register *****************/
mbed_official	5:ac9f6c2c45e8	3018	#define I2C_CR1_PE ((uint32_t)0x00000001) /!< Peripheral enable /
mbed_official	5:ac9f6c2c45e8	3019	#define I2C_CR1_TXIE ((uint32_t)0x00000002) /!< TX interrupt enable /
mbed_official	5:ac9f6c2c45e8	3020	#define I2C_CR1_RXIE ((uint32_t)0x00000004) /!< RX interrupt enable /
mbed_official	5:ac9f6c2c45e8	3021	#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /!< Address match interrupt enable /
mbed_official	5:ac9f6c2c45e8	3022	#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /!< NACK received interrupt enable /
mbed_official	5:ac9f6c2c45e8	3023	#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /!< STOP detection interrupt enable /
mbed_official	5:ac9f6c2c45e8	3024	#define I2C_CR1_TCIE ((uint32_t)0x00000040) /!< Transfer complete interrupt enable /
mbed_official	5:ac9f6c2c45e8	3025	#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /!< Errors interrupt enable /
mbed_official	5:ac9f6c2c45e8	3026	#define I2C_CR1_DFN ((uint32_t)0x00000F00) /!< Digital noise filter /
mbed_official	5:ac9f6c2c45e8	3027	#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /!< Analog noise filter OFF /
mbed_official	5:ac9f6c2c45e8	3028	#define I2C_CR1_SWRST ((uint32_t)0x00002000) /!< Software reset /
mbed_official	5:ac9f6c2c45e8	3029	#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /!< DMA transmission requests enable /
mbed_official	5:ac9f6c2c45e8	3030	#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /!< DMA reception requests enable /
mbed_official	5:ac9f6c2c45e8	3031	#define I2C_CR1_SBC ((uint32_t)0x00010000) /!< Slave byte control /
mbed_official	5:ac9f6c2c45e8	3032	#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /!< Clock stretching disable /
mbed_official	5:ac9f6c2c45e8	3033	#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /!< Wakeup from STOP enable /
mbed_official	5:ac9f6c2c45e8	3034	#define I2C_CR1_GCEN ((uint32_t)0x00080000) /!< General call enable /
mbed_official	5:ac9f6c2c45e8	3035	#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /!< SMBus host address enable /
mbed_official	5:ac9f6c2c45e8	3036	#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /!< SMBus device default address enable /
mbed_official	5:ac9f6c2c45e8	3037	#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /!< SMBus alert enable /
mbed_official	5:ac9f6c2c45e8	3038	#define I2C_CR1_PECEN ((uint32_t)0x00800000) /!< PEC enable /
mbed_official	5:ac9f6c2c45e8	3039
mbed_official	5:ac9f6c2c45e8	3040	/**************** Bit definition for I2C_CR2 register ******************/
mbed_official	5:ac9f6c2c45e8	3041	#define I2C_CR2_SADD ((uint32_t)0x000003FF) /!< Slave address (master mode) /
mbed_official	5:ac9f6c2c45e8	3042	#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /!< Transfer direction (master mode) /
mbed_official	5:ac9f6c2c45e8	3043	#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /!< 10-bit addressing mode (master mode) /
mbed_official	5:ac9f6c2c45e8	3044	#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /!< 10-bit address header only read direction (master mode) /
mbed_official	5:ac9f6c2c45e8	3045	#define I2C_CR2_START ((uint32_t)0x00002000) /!< START generation /
mbed_official	5:ac9f6c2c45e8	3046	#define I2C_CR2_STOP ((uint32_t)0x00004000) /!< STOP generation (master mode) /
mbed_official	5:ac9f6c2c45e8	3047	#define I2C_CR2_NACK ((uint32_t)0x00008000) /!< NACK generation (slave mode) /
mbed_official	5:ac9f6c2c45e8	3048	#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /!< Number of bytes /
mbed_official	5:ac9f6c2c45e8	3049	#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /!< NBYTES reload mode /
mbed_official	5:ac9f6c2c45e8	3050	#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /!< Automatic end mode (master mode) /
mbed_official	5:ac9f6c2c45e8	3051	#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /!< Packet error checking byte /
mbed_official	5:ac9f6c2c45e8	3052
mbed_official	5:ac9f6c2c45e8	3053	/***************** Bit definition for I2C_OAR1 register ****************/
mbed_official	5:ac9f6c2c45e8	3054	#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /!< Interface own address 1 /
mbed_official	5:ac9f6c2c45e8	3055	#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /!< Own address 1 10-bit mode /
mbed_official	5:ac9f6c2c45e8	3056	#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /!< Own address 1 enable /
mbed_official	5:ac9f6c2c45e8	3057
mbed_official	5:ac9f6c2c45e8	3058	/***************** Bit definition for I2C_OAR2 register ****************/
mbed_official	5:ac9f6c2c45e8	3059	#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /!< Interface own address 2 /
mbed_official	5:ac9f6c2c45e8	3060	#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /!< Own address 2 masks /
mbed_official	5:ac9f6c2c45e8	3061	#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /!< Own address 2 enable /
mbed_official	5:ac9f6c2c45e8	3062
mbed_official	5:ac9f6c2c45e8	3063	/***************** Bit definition for I2C_TIMINGR register **************/
mbed_official	5:ac9f6c2c45e8	3064	#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /!< SCL low period (master mode) /
mbed_official	5:ac9f6c2c45e8	3065	#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /!< SCL high period (master mode) /
mbed_official	5:ac9f6c2c45e8	3066	#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /!< Data hold time /
mbed_official	5:ac9f6c2c45e8	3067	#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /!< Data setup time /
mbed_official	5:ac9f6c2c45e8	3068	#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /!< Timings prescaler /
mbed_official	5:ac9f6c2c45e8	3069
mbed_official	5:ac9f6c2c45e8	3070	/***************** Bit definition for I2C_TIMEOUTR register **************/
mbed_official	5:ac9f6c2c45e8	3071	#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /!< Bus timeout A /
mbed_official	5:ac9f6c2c45e8	3072	#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /!< Idle clock timeout detection /
mbed_official	5:ac9f6c2c45e8	3073	#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /!< Clock timeout enable /
mbed_official	5:ac9f6c2c45e8	3074	#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /!< Bus timeout B/
mbed_official	5:ac9f6c2c45e8	3075	#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /!< Extended clock timeout enable /
mbed_official	5:ac9f6c2c45e8	3076
mbed_official	5:ac9f6c2c45e8	3077	/**************** Bit definition for I2C_ISR register ******************/
mbed_official	5:ac9f6c2c45e8	3078	#define I2C_ISR_TXE ((uint32_t)0x00000001) /!< Transmit data register empty /
mbed_official	5:ac9f6c2c45e8	3079	#define I2C_ISR_TXIS ((uint32_t)0x00000002) /!< Transmit interrupt status /
mbed_official	5:ac9f6c2c45e8	3080	#define I2C_ISR_RXNE ((uint32_t)0x00000004) /!< Receive data register not empty /
mbed_official	5:ac9f6c2c45e8	3081	#define I2C_ISR_ADDR ((uint32_t)0x00000008) /!< Address matched (slave mode)/
mbed_official	5:ac9f6c2c45e8	3082	#define I2C_ISR_NACKF ((uint32_t)0x00000010) /!< NACK received flag /
mbed_official	5:ac9f6c2c45e8	3083	#define I2C_ISR_STOPF ((uint32_t)0x00000020) /!< STOP detection flag /
mbed_official	5:ac9f6c2c45e8	3084	#define I2C_ISR_TC ((uint32_t)0x00000040) /!< Transfer complete (master mode) /
mbed_official	5:ac9f6c2c45e8	3085	#define I2C_ISR_TCR ((uint32_t)0x00000080) /!< Transfer complete reload /
mbed_official	5:ac9f6c2c45e8	3086	#define I2C_ISR_BERR ((uint32_t)0x00000100) /!< Bus error /
mbed_official	5:ac9f6c2c45e8	3087	#define I2C_ISR_ARLO ((uint32_t)0x00000200) /!< Arbitration lost /
mbed_official	5:ac9f6c2c45e8	3088	#define I2C_ISR_OVR ((uint32_t)0x00000400) /!< Overrun/Underrun /
mbed_official	5:ac9f6c2c45e8	3089	#define I2C_ISR_PECERR ((uint32_t)0x00000800) /!< PEC error in reception /
mbed_official	5:ac9f6c2c45e8	3090	#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /!< Timeout or Tlow detection flag /
mbed_official	5:ac9f6c2c45e8	3091	#define I2C_ISR_ALERT ((uint32_t)0x00002000) /!< SMBus alert /
mbed_official	5:ac9f6c2c45e8	3092	#define I2C_ISR_BUSY ((uint32_t)0x00008000) /!< Bus busy /
mbed_official	5:ac9f6c2c45e8	3093	#define I2C_ISR_DIR ((uint32_t)0x00010000) /!< Transfer direction (slave mode) /
mbed_official	5:ac9f6c2c45e8	3094	#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /!< Address match code (slave mode) /
mbed_official	5:ac9f6c2c45e8	3095
mbed_official	5:ac9f6c2c45e8	3096	/**************** Bit definition for I2C_ICR register ******************/
mbed_official	5:ac9f6c2c45e8	3097	#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /!< Address matched clear flag /
mbed_official	5:ac9f6c2c45e8	3098	#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /!< NACK clear flag /
mbed_official	5:ac9f6c2c45e8	3099	#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /!< STOP detection clear flag /
mbed_official	5:ac9f6c2c45e8	3100	#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /!< Bus error clear flag /
mbed_official	5:ac9f6c2c45e8	3101	#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /!< Arbitration lost clear flag /
mbed_official	5:ac9f6c2c45e8	3102	#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /!< Overrun/Underrun clear flag /
mbed_official	5:ac9f6c2c45e8	3103	#define I2C_ICR_PECCF ((uint32_t)0x00000800) /!< PAC error clear flag /
mbed_official	5:ac9f6c2c45e8	3104	#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /!< Timeout clear flag /
mbed_official	5:ac9f6c2c45e8	3105	#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /!< Alert clear flag /
mbed_official	5:ac9f6c2c45e8	3106
mbed_official	5:ac9f6c2c45e8	3107	/**************** Bit definition for I2C_PECR register *****************/
mbed_official	5:ac9f6c2c45e8	3108	#define I2C_PECR_PEC ((uint32_t)0x000000FF) /!< PEC register /
mbed_official	5:ac9f6c2c45e8	3109
mbed_official	5:ac9f6c2c45e8	3110	/**************** Bit definition for I2C_RXDR register *******************/
mbed_official	5:ac9f6c2c45e8	3111	#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /!< 8-bit receive data /
mbed_official	5:ac9f6c2c45e8	3112
mbed_official	5:ac9f6c2c45e8	3113	/**************** Bit definition for I2C_TXDR register *****************/
mbed_official	5:ac9f6c2c45e8	3114	#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /!< 8-bit transmit data /
mbed_official	5:ac9f6c2c45e8	3115
mbed_official	5:ac9f6c2c45e8	3116	/*****************************************************************************/
mbed_official	5:ac9f6c2c45e8	3117	/* */
mbed_official	5:ac9f6c2c45e8	3118	/* Independent WATCHDOG (IWDG) */
mbed_official	5:ac9f6c2c45e8	3119	/* */
mbed_official	5:ac9f6c2c45e8	3120	/*****************************************************************************/
mbed_official	5:ac9f6c2c45e8	3121	/***************** Bit definition for IWDG_KR register *****************/
mbed_official	5:ac9f6c2c45e8	3122	#define IWDG_KR_KEY ((uint32_t)0xFFFF) /!< Key value (write only, read 0000h) /
mbed_official	5:ac9f6c2c45e8	3123
mbed_official	5:ac9f6c2c45e8	3124	/***************** Bit definition for IWDG_PR register *****************/
mbed_official	5:ac9f6c2c45e8	3125	#define IWDG_PR_PR ((uint32_t)0x07) /!< PR[2:0] (Prescaler divider) /
mbed_official	5:ac9f6c2c45e8	3126	#define IWDG_PR_PR_0 ((uint32_t)0x01) /!< Bit 0 /
mbed_official	5:ac9f6c2c45e8	3127	#define IWDG_PR_PR_1 ((uint32_t)0x02) /!< Bit 1 /
mbed_official	5:ac9f6c2c45e8	3128	#define IWDG_PR_PR_2 ((uint32_t)0x04) /!< Bit 2 /
mbed_official	5:ac9f6c2c45e8	3129
mbed_official	5:ac9f6c2c45e8	3130	/***************** Bit definition for IWDG_RLR register ****************/
mbed_official	5:ac9f6c2c45e8	3131	#define IWDG_RLR_RL ((uint32_t)0x0FFF) /!< Watchdog counter reload value /
mbed_official	5:ac9f6c2c45e8	3132
mbed_official	5:ac9f6c2c45e8	3133	/***************** Bit definition for IWDG_SR register *****************/
mbed_official	5:ac9f6c2c45e8	3134	#define IWDG_SR_PVU ((uint32_t)0x01) /!< Watchdog prescaler value update /
mbed_official	5:ac9f6c2c45e8	3135	#define IWDG_SR_RVU ((uint32_t)0x02) /!< Watchdog counter reload value update /
mbed_official	5:ac9f6c2c45e8	3136	#define IWDG_SR_WVU ((uint32_t)0x04) /!< Watchdog counter window value update /
mbed_official	5:ac9f6c2c45e8	3137
mbed_official	5:ac9f6c2c45e8	3138	/***************** Bit definition for IWDG_KR register *****************/
mbed_official	5:ac9f6c2c45e8	3139	#define IWDG_WINR_WIN ((uint32_t)0x0FFF) /!< Watchdog counter window value /
mbed_official	5:ac9f6c2c45e8	3140
mbed_official	5:ac9f6c2c45e8	3141	/*****************************************************************************/
mbed_official	5:ac9f6c2c45e8	3142	/* */
mbed_official	5:ac9f6c2c45e8	3143	/* Power Control (PWR) */
mbed_official	5:ac9f6c2c45e8	3144	/* */
mbed_official	5:ac9f6c2c45e8	3145	/*****************************************************************************/
mbed_official	5:ac9f6c2c45e8	3146
mbed_official	5:ac9f6c2c45e8	3147	/****************** Bit definition for PWR_CR register *****************/
mbed_official	5:ac9f6c2c45e8	3148	#define PWR_CR_LPDS ((uint32_t)0x00000001) /!< Low-power Deepsleep /
mbed_official	5:ac9f6c2c45e8	3149	#define PWR_CR_PDDS ((uint32_t)0x00000002) /!< Power Down Deepsleep /
mbed_official	5:ac9f6c2c45e8	3150	#define PWR_CR_CWUF ((uint32_t)0x00000004) /!< Clear Wakeup Flag /
mbed_official	5:ac9f6c2c45e8	3151	#define PWR_CR_CSBF ((uint32_t)0x00000008) /!< Clear Standby Flag /
mbed_official	5:ac9f6c2c45e8	3152	#define PWR_CR_PVDE ((uint32_t)0x00000010) /!< Power Voltage Detector Enable /
mbed_official	5:ac9f6c2c45e8	3153
mbed_official	5:ac9f6c2c45e8	3154	#define PWR_CR_PLS ((uint32_t)0x000000E0) /!< PLS[2:0] bits (PVD Level Selection) /
mbed_official	5:ac9f6c2c45e8	3155	#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /!< Bit 0 /
mbed_official	5:ac9f6c2c45e8	3156	#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /!< Bit 1 /
mbed_official	5:ac9f6c2c45e8	3157	#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /!< Bit 2 /
mbed_official	5:ac9f6c2c45e8	3158
mbed_official	5:ac9f6c2c45e8	3159	/!< PVD level configuration /
mbed_official	5:ac9f6c2c45e8	3160	#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /!< PVD level 0 /
mbed_official	5:ac9f6c2c45e8	3161	#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /!< PVD level 1 /
mbed_official	5:ac9f6c2c45e8	3162	#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /!< PVD level 2 /
mbed_official	5:ac9f6c2c45e8	3163	#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /!< PVD level 3 /
mbed_official	5:ac9f6c2c45e8	3164	#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /!< PVD level 4 /
mbed_official	5:ac9f6c2c45e8	3165	#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /!< PVD level 5 /
mbed_official	5:ac9f6c2c45e8	3166	#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /!< PVD level 6 /
mbed_official	5:ac9f6c2c45e8	3167	#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /!< PVD level 7 /
mbed_official	5:ac9f6c2c45e8	3168
mbed_official	5:ac9f6c2c45e8	3169	#define PWR_CR_DBP ((uint32_t)0x00000100) /!< Disable Backup Domain write protection /
mbed_official	5:ac9f6c2c45e8	3170
mbed_official	5:ac9f6c2c45e8	3171	/***************** Bit definition for PWR_CSR register *****************/
mbed_official	5:ac9f6c2c45e8	3172	#define PWR_CSR_WUF ((uint32_t)0x00000001) /!< Wakeup Flag /
mbed_official	5:ac9f6c2c45e8	3173	#define PWR_CSR_SBF ((uint32_t)0x00000002) /!< Standby Flag /
mbed_official	5:ac9f6c2c45e8	3174	#define PWR_CSR_PVDO ((uint32_t)0x00000004) /!< PVD Output /
mbed_official	5:ac9f6c2c45e8	3175	#define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /!< Internal voltage reference (VREFINT) ready flag /
mbed_official	5:ac9f6c2c45e8	3176
mbed_official	5:ac9f6c2c45e8	3177	#define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /!< Enable WKUP pin 1 /
mbed_official	5:ac9f6c2c45e8	3178	#define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /!< Enable WKUP pin 2 /
mbed_official	5:ac9f6c2c45e8	3179	#define PWR_CSR_EWUP3 ((uint32_t)0x00000400) /!< Enable WKUP pin 3 /
mbed_official	5:ac9f6c2c45e8	3180	#define PWR_CSR_EWUP4 ((uint32_t)0x00000800) /!< Enable WKUP pin 4 /
mbed_official	5:ac9f6c2c45e8	3181	#define PWR_CSR_EWUP5 ((uint32_t)0x00001000) /!< Enable WKUP pin 5 /
mbed_official	5:ac9f6c2c45e8	3182	#define PWR_CSR_EWUP6 ((uint32_t)0x00002000) /!< Enable WKUP pin 6 /
mbed_official	5:ac9f6c2c45e8	3183	#define PWR_CSR_EWUP7 ((uint32_t)0x00004000) /!< Enable WKUP pin 7 /
mbed_official	5:ac9f6c2c45e8	3184	#define PWR_CSR_EWUP8 ((uint32_t)0x00008000) /!< Enable WKUP pin 8 /
mbed_official	5:ac9f6c2c45e8	3185
mbed_official	5:ac9f6c2c45e8	3186	/*****************************************************************************/
mbed_official	5:ac9f6c2c45e8	3187	/* */
mbed_official	5:ac9f6c2c45e8	3188	/* Reset and Clock Control */
mbed_official	5:ac9f6c2c45e8	3189	/* */
mbed_official	5:ac9f6c2c45e8	3190	/*****************************************************************************/
mbed_official	5:ac9f6c2c45e8	3191
mbed_official	5:ac9f6c2c45e8	3192	/****************** Bit definition for RCC_CR register *****************/
mbed_official	5:ac9f6c2c45e8	3193	#define RCC_CR_HSION ((uint32_t)0x00000001) /!< Internal High Speed clock enable /
mbed_official	5:ac9f6c2c45e8	3194	#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /!< Internal High Speed clock ready flag /
mbed_official	5:ac9f6c2c45e8	3195
mbed_official	5:ac9f6c2c45e8	3196	#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /!< Internal High Speed clock trimming /
mbed_official	5:ac9f6c2c45e8	3197	#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	3198	#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	3199	#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /!<Bit 2 /
mbed_official	5:ac9f6c2c45e8	3200	#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /!<Bit 3 /
mbed_official	5:ac9f6c2c45e8	3201	#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /!<Bit 4 /
mbed_official	5:ac9f6c2c45e8	3202
mbed_official	5:ac9f6c2c45e8	3203	#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /!< Internal High Speed clock Calibration /
mbed_official	5:ac9f6c2c45e8	3204	#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	3205	#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	3206	#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /!<Bit 2 /
mbed_official	5:ac9f6c2c45e8	3207	#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /!<Bit 3 /
mbed_official	5:ac9f6c2c45e8	3208	#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /!<Bit 4 /
mbed_official	5:ac9f6c2c45e8	3209	#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /!<Bit 5 /
mbed_official	5:ac9f6c2c45e8	3210	#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /!<Bit 6 /
mbed_official	5:ac9f6c2c45e8	3211	#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /!<Bit 7 /
mbed_official	5:ac9f6c2c45e8	3212
mbed_official	5:ac9f6c2c45e8	3213	#define RCC_CR_HSEON ((uint32_t)0x00010000) /!< External High Speed clock enable /
mbed_official	5:ac9f6c2c45e8	3214	#define RCC_CR_HSERDY ((uint32_t)0x00020000) /!< External High Speed clock ready flag /
mbed_official	5:ac9f6c2c45e8	3215	#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /!< External High Speed clock Bypass /
mbed_official	5:ac9f6c2c45e8	3216	#define RCC_CR_CSSON ((uint32_t)0x00080000) /!< Clock Security System enable /
mbed_official	5:ac9f6c2c45e8	3217	#define RCC_CR_PLLON ((uint32_t)0x01000000) /!< PLL enable /
mbed_official	5:ac9f6c2c45e8	3218	#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /!< PLL clock ready flag /
mbed_official	5:ac9f6c2c45e8	3219
mbed_official	5:ac9f6c2c45e8	3220	/****************** Bit definition for RCC_CFGR register ***************/
mbed_official	5:ac9f6c2c45e8	3221	/!< SW configuration /
mbed_official	5:ac9f6c2c45e8	3222	#define RCC_CFGR_SW ((uint32_t)0x00000003) /!< SW[1:0] bits (System clock Switch) /
mbed_official	5:ac9f6c2c45e8	3223	#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	5:ac9f6c2c45e8	3224	#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	5:ac9f6c2c45e8	3225
mbed_official	5:ac9f6c2c45e8	3226	#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /!< HSI selected as system clock /
mbed_official	5:ac9f6c2c45e8	3227	#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /!< HSE selected as system clock /
mbed_official	5:ac9f6c2c45e8	3228	#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /!< PLL selected as system clock /
mbed_official	5:ac9f6c2c45e8	3229	#define RCC_CFGR_SW_HSI48 ((uint32_t)0x00000003) /!< HSI48 selected as system clock /
mbed_official	5:ac9f6c2c45e8	3230
mbed_official	5:ac9f6c2c45e8	3231	/!< SWS configuration /
mbed_official	5:ac9f6c2c45e8	3232	#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /!< SWS[1:0] bits (System Clock Switch Status) /
mbed_official	5:ac9f6c2c45e8	3233	#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /!< Bit 0 /
mbed_official	5:ac9f6c2c45e8	3234	#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /!< Bit 1 /
mbed_official	5:ac9f6c2c45e8	3235
mbed_official	5:ac9f6c2c45e8	3236	#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /!< HSI oscillator used as system clock /
mbed_official	5:ac9f6c2c45e8	3237	#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /!< HSE oscillator used as system clock /
mbed_official	5:ac9f6c2c45e8	3238	#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /!< PLL used as system clock /
mbed_official	5:ac9f6c2c45e8	3239	#define RCC_CFGR_SWS_HSI48 ((uint32_t)0x0000000C) /!< HSI48 oscillator used as system clock /
mbed_official	5:ac9f6c2c45e8	3240
mbed_official	5:ac9f6c2c45e8	3241	/!< HPRE configuration /
mbed_official	5:ac9f6c2c45e8	3242	#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /!< HPRE[3:0] bits (AHB prescaler) /
mbed_official	5:ac9f6c2c45e8	3243	#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /!< Bit 0 /
mbed_official	5:ac9f6c2c45e8	3244	#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /!< Bit 1 /
mbed_official	5:ac9f6c2c45e8	3245	#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /!< Bit 2 /
mbed_official	5:ac9f6c2c45e8	3246	#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /!< Bit 3 /
mbed_official	5:ac9f6c2c45e8	3247
mbed_official	5:ac9f6c2c45e8	3248	#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /!< SYSCLK not divided /
mbed_official	5:ac9f6c2c45e8	3249	#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /!< SYSCLK divided by 2 /
mbed_official	5:ac9f6c2c45e8	3250	#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /!< SYSCLK divided by 4 /
mbed_official	5:ac9f6c2c45e8	3251	#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /!< SYSCLK divided by 8 /
mbed_official	5:ac9f6c2c45e8	3252	#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /!< SYSCLK divided by 16 /
mbed_official	5:ac9f6c2c45e8	3253	#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /!< SYSCLK divided by 64 /
mbed_official	5:ac9f6c2c45e8	3254	#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /!< SYSCLK divided by 128 /
mbed_official	5:ac9f6c2c45e8	3255	#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /!< SYSCLK divided by 256 /
mbed_official	5:ac9f6c2c45e8	3256	#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /!< SYSCLK divided by 512 /
mbed_official	5:ac9f6c2c45e8	3257
mbed_official	5:ac9f6c2c45e8	3258	/!< PPRE configuration /
mbed_official	5:ac9f6c2c45e8	3259	#define RCC_CFGR_PPRE ((uint32_t)0x00000700) /!< PRE[2:0] bits (APB prescaler) /
mbed_official	5:ac9f6c2c45e8	3260	#define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /!< Bit 0 /
mbed_official	5:ac9f6c2c45e8	3261	#define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /!< Bit 1 /
mbed_official	5:ac9f6c2c45e8	3262	#define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /!< Bit 2 /
mbed_official	5:ac9f6c2c45e8	3263
mbed_official	5:ac9f6c2c45e8	3264	#define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
mbed_official	5:ac9f6c2c45e8	3265	#define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /!< HCLK divided by 2 /
mbed_official	5:ac9f6c2c45e8	3266	#define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /!< HCLK divided by 4 /
mbed_official	5:ac9f6c2c45e8	3267	#define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /!< HCLK divided by 8 /
mbed_official	5:ac9f6c2c45e8	3268	#define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /!< HCLK divided by 16 /
mbed_official	5:ac9f6c2c45e8	3269
mbed_official	5:ac9f6c2c45e8	3270	/!< ADCPPRE configuration /
mbed_official	5:ac9f6c2c45e8	3271	#define RCC_CFGR_ADCPRE ((uint32_t)0x00004000) /!< ADCPRE bit (ADC prescaler) /
mbed_official	5:ac9f6c2c45e8	3272
mbed_official	5:ac9f6c2c45e8	3273	#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /!< PCLK divided by 2 /
mbed_official	5:ac9f6c2c45e8	3274	#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /!< PCLK divided by 4 /
mbed_official	5:ac9f6c2c45e8	3275
mbed_official	5:ac9f6c2c45e8	3276	#define RCC_CFGR_PLLSRC ((uint32_t)0x00018000) /!< PLL entry clock source /
mbed_official	5:ac9f6c2c45e8	3277	#define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /!< HSI clock divided by 2 selected as PLL entry clock source /
mbed_official	5:ac9f6c2c45e8	3278	#define RCC_CFGR_PLLSRC_HSI_PREDIV ((uint32_t)0x00008000) /!< HSI/PREDIV clock selected as PLL entry clock source /
mbed_official	5:ac9f6c2c45e8	3279	#define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /!< HSE/PREDIV clock selected as PLL entry clock source /
mbed_official	5:ac9f6c2c45e8	3280	#define RCC_CFGR_PLLSRC_HSI48_PREDIV ((uint32_t)0x00018000) /!< HSI48/PREDIV clock selected as PLL entry clock source /
mbed_official	5:ac9f6c2c45e8	3281
mbed_official	5:ac9f6c2c45e8	3282	#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /!< HSE divider for PLL entry /
mbed_official	5:ac9f6c2c45e8	3283	#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /!< HSE/PREDIV clock not divided for PLL entry /
mbed_official	5:ac9f6c2c45e8	3284	#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /!< HSE/PREDIV clock divided by 2 for PLL entry /
mbed_official	5:ac9f6c2c45e8	3285
mbed_official	5:ac9f6c2c45e8	3286	/!< PLLMUL configuration /
mbed_official	5:ac9f6c2c45e8	3287	#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /!< PLLMUL[3:0] bits (PLL multiplication factor) /
mbed_official	5:ac9f6c2c45e8	3288	#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /!< Bit 0 /
mbed_official	5:ac9f6c2c45e8	3289	#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /!< Bit 1 /
mbed_official	5:ac9f6c2c45e8	3290	#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /!< Bit 2 /
mbed_official	5:ac9f6c2c45e8	3291	#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /!< Bit 3 /
mbed_official	5:ac9f6c2c45e8	3292
mbed_official	5:ac9f6c2c45e8	3293	#define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /!< PLL input clock2 */
mbed_official	5:ac9f6c2c45e8	3294	#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /!< PLL input clock3 */
mbed_official	5:ac9f6c2c45e8	3295	#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /!< PLL input clock4 */
mbed_official	5:ac9f6c2c45e8	3296	#define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /!< PLL input clock5 */
mbed_official	5:ac9f6c2c45e8	3297	#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /!< PLL input clock6 */
mbed_official	5:ac9f6c2c45e8	3298	#define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /!< PLL input clock7 */
mbed_official	5:ac9f6c2c45e8	3299	#define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /!< PLL input clock8 */
mbed_official	5:ac9f6c2c45e8	3300	#define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /!< PLL input clock9 */
mbed_official	5:ac9f6c2c45e8	3301	#define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /!< PLL input clock10 /
mbed_official	5:ac9f6c2c45e8	3302	#define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /!< PLL input clock11 */
mbed_official	5:ac9f6c2c45e8	3303	#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /!< PLL input clock12 */
mbed_official	5:ac9f6c2c45e8	3304	#define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /!< PLL input clock13 */
mbed_official	5:ac9f6c2c45e8	3305	#define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /!< PLL input clock14 */
mbed_official	5:ac9f6c2c45e8	3306	#define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /!< PLL input clock15 */
mbed_official	5:ac9f6c2c45e8	3307	#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /!< PLL input clock16 */
mbed_official	5:ac9f6c2c45e8	3308
mbed_official	5:ac9f6c2c45e8	3309	/!< USB configuration /
mbed_official	5:ac9f6c2c45e8	3310	#define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /!< USB prescaler /
mbed_official	5:ac9f6c2c45e8	3311
mbed_official	5:ac9f6c2c45e8	3312	/!< MCO configuration /
mbed_official	5:ac9f6c2c45e8	3313	#define RCC_CFGR_MCO ((uint32_t)0x0F000000) /!< MCO[3:0] bits (Microcontroller Clock Output) /
mbed_official	5:ac9f6c2c45e8	3314	#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /!< Bit 0 /
mbed_official	5:ac9f6c2c45e8	3315	#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /!< Bit 1 /
mbed_official	5:ac9f6c2c45e8	3316	#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /!< Bit 2 /
mbed_official	5:ac9f6c2c45e8	3317	#define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /!< Bit 3 /
mbed_official	5:ac9f6c2c45e8	3318
mbed_official	5:ac9f6c2c45e8	3319	#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
mbed_official	5:ac9f6c2c45e8	3320	#define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /!< HSI14 clock selected as MCO source /
mbed_official	5:ac9f6c2c45e8	3321	#define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /!< LSI clock selected as MCO source /
mbed_official	5:ac9f6c2c45e8	3322	#define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /!< LSE clock selected as MCO source /
mbed_official	5:ac9f6c2c45e8	3323	#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /!< System clock selected as MCO source /
mbed_official	5:ac9f6c2c45e8	3324	#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /!< HSI clock selected as MCO source /
mbed_official	5:ac9f6c2c45e8	3325	#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /!< HSE clock selected as MCO source /
mbed_official	5:ac9f6c2c45e8	3326	#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /!< PLL clock divided by 2 selected as MCO source /
mbed_official	5:ac9f6c2c45e8	3327	#define RCC_CFGR_MCO_HSI48 ((uint32_t)0x08000000) /!< HSI48 clock selected as MCO source /
mbed_official	5:ac9f6c2c45e8	3328
mbed_official	5:ac9f6c2c45e8	3329	#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /!< MCO prescaler /
mbed_official	5:ac9f6c2c45e8	3330	#define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000) /!< MCO is divided by 1 /
mbed_official	5:ac9f6c2c45e8	3331	#define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000) /!< MCO is divided by 2 /
mbed_official	5:ac9f6c2c45e8	3332	#define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000) /!< MCO is divided by 4 /
mbed_official	5:ac9f6c2c45e8	3333	#define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000) /!< MCO is divided by 8 /
mbed_official	5:ac9f6c2c45e8	3334	#define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000) /!< MCO is divided by 16 /
mbed_official	5:ac9f6c2c45e8	3335	#define RCC_CFGR_MCOPRE_DIV32 ((uint32_t)0x50000000) /!< MCO is divided by 32 /
mbed_official	5:ac9f6c2c45e8	3336	#define RCC_CFGR_MCOPRE_DIV64 ((uint32_t)0x60000000) /!< MCO is divided by 64 /
mbed_official	5:ac9f6c2c45e8	3337	#define RCC_CFGR_MCOPRE_DIV128 ((uint32_t)0x70000000) /!< MCO is divided by 128 /
mbed_official	5:ac9f6c2c45e8	3338
mbed_official	5:ac9f6c2c45e8	3339	#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /!< PLL is not divided to MCO /
mbed_official	5:ac9f6c2c45e8	3340
mbed_official	5:ac9f6c2c45e8	3341	/!<*************** Bit definition for RCC_CIR register ***************/
mbed_official	5:ac9f6c2c45e8	3342	#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /!< LSI Ready Interrupt flag /
mbed_official	5:ac9f6c2c45e8	3343	#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /!< LSE Ready Interrupt flag /
mbed_official	5:ac9f6c2c45e8	3344	#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /!< HSI Ready Interrupt flag /
mbed_official	5:ac9f6c2c45e8	3345	#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /!< HSE Ready Interrupt flag /
mbed_official	5:ac9f6c2c45e8	3346	#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /!< PLL Ready Interrupt flag /
mbed_official	5:ac9f6c2c45e8	3347	#define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /!< HSI14 Ready Interrupt flag /
mbed_official	5:ac9f6c2c45e8	3348	#define RCC_CIR_HSI48RDYF ((uint32_t)0x00000040) /!< HSI48 Ready Interrupt flag /
mbed_official	5:ac9f6c2c45e8	3349	#define RCC_CIR_CSSF ((uint32_t)0x00000080) /!< Clock Security System Interrupt flag /
mbed_official	5:ac9f6c2c45e8	3350	#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /!< LSI Ready Interrupt Enable /
mbed_official	5:ac9f6c2c45e8	3351	#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /!< LSE Ready Interrupt Enable /
mbed_official	5:ac9f6c2c45e8	3352	#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /!< HSI Ready Interrupt Enable /
mbed_official	5:ac9f6c2c45e8	3353	#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /!< HSE Ready Interrupt Enable /
mbed_official	5:ac9f6c2c45e8	3354	#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /!< PLL Ready Interrupt Enable /
mbed_official	5:ac9f6c2c45e8	3355	#define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /!< HSI14 Ready Interrupt Enable /
mbed_official	5:ac9f6c2c45e8	3356	#define RCC_CIR_HSI48RDYIE ((uint32_t)0x00004000) /!< HSI48 Ready Interrupt Enable /
mbed_official	5:ac9f6c2c45e8	3357	#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /!< LSI Ready Interrupt Clear /
mbed_official	5:ac9f6c2c45e8	3358	#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /!< LSE Ready Interrupt Clear /
mbed_official	5:ac9f6c2c45e8	3359	#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /!< HSI Ready Interrupt Clear /
mbed_official	5:ac9f6c2c45e8	3360	#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /!< HSE Ready Interrupt Clear /
mbed_official	5:ac9f6c2c45e8	3361	#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /!< PLL Ready Interrupt Clear /
mbed_official	5:ac9f6c2c45e8	3362	#define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /!< HSI14 Ready Interrupt Clear /
mbed_official	5:ac9f6c2c45e8	3363	#define RCC_CIR_HSI48RDYC ((uint32_t)0x00400000) /!< HSI48 Ready Interrupt Clear /
mbed_official	5:ac9f6c2c45e8	3364	#define RCC_CIR_CSSC ((uint32_t)0x00800000) /!< Clock Security System Interrupt Clear /
mbed_official	5:ac9f6c2c45e8	3365
mbed_official	5:ac9f6c2c45e8	3366	/*************** Bit definition for RCC_APB2RSTR register **************/
mbed_official	5:ac9f6c2c45e8	3367	#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /!< SYSCFG clock reset /
mbed_official	5:ac9f6c2c45e8	3368	#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /!< ADC clock reset /
mbed_official	5:ac9f6c2c45e8	3369	#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /!< TIM1 clock reset /
mbed_official	5:ac9f6c2c45e8	3370	#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /!< SPI1 clock reset /
mbed_official	5:ac9f6c2c45e8	3371	#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /!< USART1 clock reset /
mbed_official	5:ac9f6c2c45e8	3372	#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /!< TIM16 clock reset /
mbed_official	5:ac9f6c2c45e8	3373	#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /!< TIM17 clock reset /
mbed_official	5:ac9f6c2c45e8	3374	#define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /!< DBGMCU clock reset /
mbed_official	5:ac9f6c2c45e8	3375
mbed_official	5:ac9f6c2c45e8	3376	/!< Old ADC1 clock reset bit definition maintained for legacy purpose /
mbed_official	5:ac9f6c2c45e8	3377	#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
mbed_official	5:ac9f6c2c45e8	3378
mbed_official	5:ac9f6c2c45e8	3379	/*************** Bit definition for RCC_APB1RSTR register **************/
mbed_official	5:ac9f6c2c45e8	3380	#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /!< Timer 2 clock reset /
mbed_official	5:ac9f6c2c45e8	3381	#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /!< Timer 3 clock reset /
mbed_official	5:ac9f6c2c45e8	3382	#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /!< Timer 14 clock reset /
mbed_official	5:ac9f6c2c45e8	3383	#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /!< Window Watchdog clock reset /
mbed_official	5:ac9f6c2c45e8	3384	#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /!< SPI2 clock reset /
mbed_official	5:ac9f6c2c45e8	3385	#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /!< USART 2 clock reset /
mbed_official	5:ac9f6c2c45e8	3386	#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /!< USART 3 clock reset /
mbed_official	5:ac9f6c2c45e8	3387	#define RCC_APB1RSTR_USART4RST ((uint32_t)0x00080000) /!< USART 4 clock reset /
mbed_official	5:ac9f6c2c45e8	3388	#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /!< I2C 1 clock reset /
mbed_official	5:ac9f6c2c45e8	3389	#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /!< I2C 2 clock reset /
mbed_official	5:ac9f6c2c45e8	3390	#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /!< USB clock reset /
mbed_official	5:ac9f6c2c45e8	3391	#define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /!< CAN clock reset /
mbed_official	5:ac9f6c2c45e8	3392	#define RCC_APB1RSTR_CRSRST ((uint32_t)0x08000000) /!< CRS clock reset /
mbed_official	5:ac9f6c2c45e8	3393	#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /!< PWR clock reset /
mbed_official	5:ac9f6c2c45e8	3394	#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /!< DAC clock reset /
mbed_official	5:ac9f6c2c45e8	3395	#define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /!< CEC clock reset /
mbed_official	5:ac9f6c2c45e8	3396
mbed_official	5:ac9f6c2c45e8	3397	/**************** Bit definition for RCC_AHBENR register ***************/
mbed_official	5:ac9f6c2c45e8	3398	#define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /!< DMA1 clock enable /
mbed_official	5:ac9f6c2c45e8	3399	#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /!< SRAM interface clock enable /
mbed_official	5:ac9f6c2c45e8	3400	#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /!< FLITF clock enable /
mbed_official	5:ac9f6c2c45e8	3401	#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /!< CRC clock enable /
mbed_official	5:ac9f6c2c45e8	3402	#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /!< GPIOA clock enable /
mbed_official	5:ac9f6c2c45e8	3403	#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /!< GPIOB clock enable /
mbed_official	5:ac9f6c2c45e8	3404	#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /!< GPIOC clock enable /
mbed_official	5:ac9f6c2c45e8	3405	#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /!< GPIOF clock enable /
mbed_official	5:ac9f6c2c45e8	3406	#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /!< TS controller clock enable /
mbed_official	5:ac9f6c2c45e8	3407
mbed_official	5:ac9f6c2c45e8	3408	/* Old Bit definition maintained for legacy purpose */
mbed_official	5:ac9f6c2c45e8	3409	#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /!< DMA1 clock enable /
mbed_official	5:ac9f6c2c45e8	3410	#define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /!< TS clock enable /
mbed_official	5:ac9f6c2c45e8	3411
mbed_official	5:ac9f6c2c45e8	3412	/*************** Bit definition for RCC_APB2ENR register ***************/
mbed_official	5:ac9f6c2c45e8	3413	#define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /!< SYSCFG and comparator clock enable /
mbed_official	5:ac9f6c2c45e8	3414	#define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /!< ADC1 clock enable /
mbed_official	5:ac9f6c2c45e8	3415	#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /!< TIM1 clock enable /
mbed_official	5:ac9f6c2c45e8	3416	#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /!< SPI1 clock enable /
mbed_official	5:ac9f6c2c45e8	3417	#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /!< USART1 clock enable /
mbed_official	5:ac9f6c2c45e8	3418	#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /!< TIM16 clock enable /
mbed_official	5:ac9f6c2c45e8	3419	#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /!< TIM17 clock enable /
mbed_official	5:ac9f6c2c45e8	3420	#define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /!< DBGMCU clock enable /
mbed_official	5:ac9f6c2c45e8	3421
mbed_official	5:ac9f6c2c45e8	3422	/* Old Bit definition maintained for legacy purpose */
mbed_official	5:ac9f6c2c45e8	3423	#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /!< SYSCFG clock enable /
mbed_official	5:ac9f6c2c45e8	3424	#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /!< ADC1 clock enable /
mbed_official	5:ac9f6c2c45e8	3425
mbed_official	5:ac9f6c2c45e8	3426	/*************** Bit definition for RCC_APB1ENR register ***************/
mbed_official	5:ac9f6c2c45e8	3427	#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /!< Timer 2 clock enable /
mbed_official	5:ac9f6c2c45e8	3428	#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /!< Timer 3 clock enable /
mbed_official	5:ac9f6c2c45e8	3429	#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /!< Timer 14 clock enable /
mbed_official	5:ac9f6c2c45e8	3430	#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /!< Window Watchdog clock enable /
mbed_official	5:ac9f6c2c45e8	3431	#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /!< SPI2 clock enable /
mbed_official	5:ac9f6c2c45e8	3432	#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /!< USART2 clock enable /
mbed_official	5:ac9f6c2c45e8	3433	#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /!< USART3 clock enable /
mbed_official	5:ac9f6c2c45e8	3434	#define RCC_APB1ENR_USART4EN ((uint32_t)0x00080000) /!< USART4 clock enable /
mbed_official	5:ac9f6c2c45e8	3435	#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /!< I2C1 clock enable /
mbed_official	5:ac9f6c2c45e8	3436	#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /!< I2C2 clock enable /
mbed_official	5:ac9f6c2c45e8	3437	#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /!< USB clock enable /
mbed_official	5:ac9f6c2c45e8	3438	#define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /!< CAN clock enable /
mbed_official	5:ac9f6c2c45e8	3439	#define RCC_APB1ENR_CRSEN ((uint32_t)0x08000000) /!< CRS clock enable /
mbed_official	5:ac9f6c2c45e8	3440	#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /!< PWR clock enable /
mbed_official	5:ac9f6c2c45e8	3441	#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /!< DAC clock enable /
mbed_official	5:ac9f6c2c45e8	3442	#define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /!< CEC clock enable /
mbed_official	5:ac9f6c2c45e8	3443
mbed_official	5:ac9f6c2c45e8	3444	/***************** Bit definition for RCC_BDCR register ****************/
mbed_official	5:ac9f6c2c45e8	3445	#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /!< External Low Speed oscillator enable /
mbed_official	5:ac9f6c2c45e8	3446	#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /!< External Low Speed oscillator Ready /
mbed_official	5:ac9f6c2c45e8	3447	#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /!< External Low Speed oscillator Bypass /
mbed_official	5:ac9f6c2c45e8	3448
mbed_official	5:ac9f6c2c45e8	3449	#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /!< LSEDRV[1:0] bits (LSE Osc. drive capability) /
mbed_official	5:ac9f6c2c45e8	3450	#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /!< Bit 0 /
mbed_official	5:ac9f6c2c45e8	3451	#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /!< Bit 1 /
mbed_official	5:ac9f6c2c45e8	3452
mbed_official	5:ac9f6c2c45e8	3453	#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /!< RTCSEL[1:0] bits (RTC clock source selection) /
mbed_official	5:ac9f6c2c45e8	3454	#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /!< Bit 0 /
mbed_official	5:ac9f6c2c45e8	3455	#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /!< Bit 1 /
mbed_official	5:ac9f6c2c45e8	3456
mbed_official	5:ac9f6c2c45e8	3457	/!< RTC configuration /
mbed_official	5:ac9f6c2c45e8	3458	#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
mbed_official	5:ac9f6c2c45e8	3459	#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /!< LSE oscillator clock used as RTC clock /
mbed_official	5:ac9f6c2c45e8	3460	#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /!< LSI oscillator clock used as RTC clock /
mbed_official	5:ac9f6c2c45e8	3461	#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /!< HSE oscillator clock divided by 128 used as RTC clock /
mbed_official	5:ac9f6c2c45e8	3462
mbed_official	5:ac9f6c2c45e8	3463	#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /!< RTC clock enable /
mbed_official	5:ac9f6c2c45e8	3464	#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /!< Backup domain software reset /
mbed_official	5:ac9f6c2c45e8	3465
mbed_official	5:ac9f6c2c45e8	3466	/***************** Bit definition for RCC_CSR register *****************/
mbed_official	5:ac9f6c2c45e8	3467	#define RCC_CSR_LSION ((uint32_t)0x00000001) /!< Internal Low Speed oscillator enable /
mbed_official	5:ac9f6c2c45e8	3468	#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /!< Internal Low Speed oscillator Ready /
mbed_official	5:ac9f6c2c45e8	3469	#define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /!< V1.8 power domain reset flag /
mbed_official	5:ac9f6c2c45e8	3470	#define RCC_CSR_RMVF ((uint32_t)0x01000000) /!< Remove reset flag /
mbed_official	5:ac9f6c2c45e8	3471	#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /!< OBL reset flag /
mbed_official	5:ac9f6c2c45e8	3472	#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /!< PIN reset flag /
mbed_official	5:ac9f6c2c45e8	3473	#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /!< POR/PDR reset flag /
mbed_official	5:ac9f6c2c45e8	3474	#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /!< Software Reset flag /
mbed_official	5:ac9f6c2c45e8	3475	#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /!< Independent Watchdog reset flag /
mbed_official	5:ac9f6c2c45e8	3476	#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /!< Window watchdog reset flag /
mbed_official	5:ac9f6c2c45e8	3477	#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /!< Low-Power reset flag /
mbed_official	5:ac9f6c2c45e8	3478
mbed_official	5:ac9f6c2c45e8	3479	/* Old Bit definition maintained for legacy purpose */
mbed_official	5:ac9f6c2c45e8	3480	#define RCC_CSR_OBL RCC_CSR_OBLRSTF /!< OBL reset flag /
mbed_official	5:ac9f6c2c45e8	3481
mbed_official	5:ac9f6c2c45e8	3482	/***************** Bit definition for RCC_AHBRSTR register *************/
mbed_official	5:ac9f6c2c45e8	3483	#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /!< GPIOA clock reset /
mbed_official	5:ac9f6c2c45e8	3484	#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /!< GPIOB clock reset /
mbed_official	5:ac9f6c2c45e8	3485	#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /!< GPIOC clock reset /
mbed_official	5:ac9f6c2c45e8	3486	#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /!< GPIOF clock reset /
mbed_official	5:ac9f6c2c45e8	3487	#define RCC_AHBRSTR_TSCRST ((uint32_t)0x01000000) /!< TS clock reset /
mbed_official	5:ac9f6c2c45e8	3488
mbed_official	5:ac9f6c2c45e8	3489	/* Old Bit definition maintained for legacy purpose */
mbed_official	5:ac9f6c2c45e8	3490	#define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /!< TS clock reset /
mbed_official	5:ac9f6c2c45e8	3491
mbed_official	5:ac9f6c2c45e8	3492	/***************** Bit definition for RCC_CFGR2 register ***************/
mbed_official	5:ac9f6c2c45e8	3493	/!< PREDIV configuration /
mbed_official	5:ac9f6c2c45e8	3494	#define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /!< PREDIV[3:0] bits /
mbed_official	5:ac9f6c2c45e8	3495	#define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	5:ac9f6c2c45e8	3496	#define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	5:ac9f6c2c45e8	3497	#define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /!< Bit 2 /
mbed_official	5:ac9f6c2c45e8	3498	#define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /!< Bit 3 /
mbed_official	5:ac9f6c2c45e8	3499
mbed_official	5:ac9f6c2c45e8	3500	#define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /!< PREDIV input clock not divided /
mbed_official	5:ac9f6c2c45e8	3501	#define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /!< PREDIV input clock divided by 2 /
mbed_official	5:ac9f6c2c45e8	3502	#define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /!< PREDIV input clock divided by 3 /
mbed_official	5:ac9f6c2c45e8	3503	#define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /!< PREDIV input clock divided by 4 /
mbed_official	5:ac9f6c2c45e8	3504	#define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /!< PREDIV input clock divided by 5 /
mbed_official	5:ac9f6c2c45e8	3505	#define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /!< PREDIV input clock divided by 6 /
mbed_official	5:ac9f6c2c45e8	3506	#define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /!< PREDIV input clock divided by 7 /
mbed_official	5:ac9f6c2c45e8	3507	#define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /!< PREDIV input clock divided by 8 /
mbed_official	5:ac9f6c2c45e8	3508	#define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /!< PREDIV input clock divided by 9 /
mbed_official	5:ac9f6c2c45e8	3509	#define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /!< PREDIV input clock divided by 10 /
mbed_official	5:ac9f6c2c45e8	3510	#define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /!< PREDIV input clock divided by 11 /
mbed_official	5:ac9f6c2c45e8	3511	#define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /!< PREDIV input clock divided by 12 /
mbed_official	5:ac9f6c2c45e8	3512	#define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /!< PREDIV input clock divided by 13 /
mbed_official	5:ac9f6c2c45e8	3513	#define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /!< PREDIV input clock divided by 14 /
mbed_official	5:ac9f6c2c45e8	3514	#define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /!< PREDIV input clock divided by 15 /
mbed_official	5:ac9f6c2c45e8	3515	#define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /!< PREDIV input clock divided by 16 /
mbed_official	5:ac9f6c2c45e8	3516
mbed_official	5:ac9f6c2c45e8	3517	/***************** Bit definition for RCC_CFGR3 register ***************/
mbed_official	5:ac9f6c2c45e8	3518	/!< USART1 Clock source selection /
mbed_official	5:ac9f6c2c45e8	3519	#define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /!< USART1SW[1:0] bits /
mbed_official	5:ac9f6c2c45e8	3520	#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	5:ac9f6c2c45e8	3521	#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	5:ac9f6c2c45e8	3522
mbed_official	5:ac9f6c2c45e8	3523	#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /!< PCLK clock used as USART1 clock source /
mbed_official	5:ac9f6c2c45e8	3524	#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /!< System clock selected as USART1 clock source /
mbed_official	5:ac9f6c2c45e8	3525	#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /!< LSE oscillator clock used as USART1 clock source /
mbed_official	5:ac9f6c2c45e8	3526	#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /!< HSI oscillator clock used as USART1 clock source /
mbed_official	5:ac9f6c2c45e8	3527
mbed_official	5:ac9f6c2c45e8	3528	/!< I2C1 Clock source selection /
mbed_official	5:ac9f6c2c45e8	3529	#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /!< I2C1SW bits /
mbed_official	5:ac9f6c2c45e8	3530
mbed_official	5:ac9f6c2c45e8	3531	#define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /!< HSI oscillator clock used as I2C1 clock source /
mbed_official	5:ac9f6c2c45e8	3532	#define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /!< System clock selected as I2C1 clock source /
mbed_official	5:ac9f6c2c45e8	3533
mbed_official	5:ac9f6c2c45e8	3534	/!< CEC Clock source selection /
mbed_official	5:ac9f6c2c45e8	3535	#define RCC_CFGR3_CECSW ((uint32_t)0x00000040) /!< CECSW bits /
mbed_official	5:ac9f6c2c45e8	3536
mbed_official	5:ac9f6c2c45e8	3537	#define RCC_CFGR3_CECSW_HSI_DIV244 ((uint32_t)0x00000000) /!< HSI clock divided by 244 selected as HDMI CEC entry clock source /
mbed_official	5:ac9f6c2c45e8	3538	#define RCC_CFGR3_CECSW_LSE ((uint32_t)0x00000040) /!< LSE clock selected as HDMI CEC entry clock source /
mbed_official	5:ac9f6c2c45e8	3539
mbed_official	5:ac9f6c2c45e8	3540	/!< USB Clock source selection /
mbed_official	5:ac9f6c2c45e8	3541	#define RCC_CFGR3_USBSW ((uint32_t)0x00000080) /!< USBSW bits /
mbed_official	5:ac9f6c2c45e8	3542
mbed_official	5:ac9f6c2c45e8	3543	#define RCC_CFGR3_USBSW_HSI48 ((uint32_t)0x00000000) /!< HSI48 oscillator clock used as USB clock source /
mbed_official	5:ac9f6c2c45e8	3544	#define RCC_CFGR3_USBSW_PLLCLK ((uint32_t)0x00000080) /!< PLLCLK selected as USB clock source /
mbed_official	5:ac9f6c2c45e8	3545
mbed_official	5:ac9f6c2c45e8	3546	/***************** Bit definition for RCC_CR2 register *****************/
mbed_official	5:ac9f6c2c45e8	3547	#define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /!< Internal High Speed 14MHz clock enable /
mbed_official	5:ac9f6c2c45e8	3548	#define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /!< Internal High Speed 14MHz clock ready flag /
mbed_official	5:ac9f6c2c45e8	3549	#define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /!< Internal High Speed 14MHz clock disable /
mbed_official	5:ac9f6c2c45e8	3550	#define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /!< Internal High Speed 14MHz clock trimming /
mbed_official	5:ac9f6c2c45e8	3551	#define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /!< Internal High Speed 14MHz clock Calibration /
mbed_official	5:ac9f6c2c45e8	3552	#define RCC_CR2_HSI48ON ((uint32_t)0x00010000) /!< Internal High Speed 48MHz clock enable /
mbed_official	5:ac9f6c2c45e8	3553	#define RCC_CR2_HSI48RDY ((uint32_t)0x00020000) /!< Internal High Speed 48MHz clock ready flag /
mbed_official	5:ac9f6c2c45e8	3554	#define RCC_CR2_HSI48CAL ((uint32_t)0xFF000000) /!< Internal High Speed 48MHz clock Calibration /
mbed_official	5:ac9f6c2c45e8	3555
mbed_official	5:ac9f6c2c45e8	3556	/*****************************************************************************/
mbed_official	5:ac9f6c2c45e8	3557	/* */
mbed_official	5:ac9f6c2c45e8	3558	/* Real-Time Clock (RTC) */
mbed_official	5:ac9f6c2c45e8	3559	/* */
mbed_official	5:ac9f6c2c45e8	3560	/*****************************************************************************/
mbed_official	5:ac9f6c2c45e8	3561	/****************** Bits definition for RTC_TR register ****************/
mbed_official	5:ac9f6c2c45e8	3562	#define RTC_TR_PM ((uint32_t)0x00400000)
mbed_official	5:ac9f6c2c45e8	3563	#define RTC_TR_HT ((uint32_t)0x00300000)
mbed_official	5:ac9f6c2c45e8	3564	#define RTC_TR_HT_0 ((uint32_t)0x00100000)
mbed_official	5:ac9f6c2c45e8	3565	#define RTC_TR_HT_1 ((uint32_t)0x00200000)
mbed_official	5:ac9f6c2c45e8	3566	#define RTC_TR_HU ((uint32_t)0x000F0000)
mbed_official	5:ac9f6c2c45e8	3567	#define RTC_TR_HU_0 ((uint32_t)0x00010000)
mbed_official	5:ac9f6c2c45e8	3568	#define RTC_TR_HU_1 ((uint32_t)0x00020000)
mbed_official	5:ac9f6c2c45e8	3569	#define RTC_TR_HU_2 ((uint32_t)0x00040000)
mbed_official	5:ac9f6c2c45e8	3570	#define RTC_TR_HU_3 ((uint32_t)0x00080000)
mbed_official	5:ac9f6c2c45e8	3571	#define RTC_TR_MNT ((uint32_t)0x00007000)
mbed_official	5:ac9f6c2c45e8	3572	#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
mbed_official	5:ac9f6c2c45e8	3573	#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
mbed_official	5:ac9f6c2c45e8	3574	#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
mbed_official	5:ac9f6c2c45e8	3575	#define RTC_TR_MNU ((uint32_t)0x00000F00)
mbed_official	5:ac9f6c2c45e8	3576	#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
mbed_official	5:ac9f6c2c45e8	3577	#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
mbed_official	5:ac9f6c2c45e8	3578	#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
mbed_official	5:ac9f6c2c45e8	3579	#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
mbed_official	5:ac9f6c2c45e8	3580	#define RTC_TR_ST ((uint32_t)0x00000070)
mbed_official	5:ac9f6c2c45e8	3581	#define RTC_TR_ST_0 ((uint32_t)0x00000010)
mbed_official	5:ac9f6c2c45e8	3582	#define RTC_TR_ST_1 ((uint32_t)0x00000020)
mbed_official	5:ac9f6c2c45e8	3583	#define RTC_TR_ST_2 ((uint32_t)0x00000040)
mbed_official	5:ac9f6c2c45e8	3584	#define RTC_TR_SU ((uint32_t)0x0000000F)
mbed_official	5:ac9f6c2c45e8	3585	#define RTC_TR_SU_0 ((uint32_t)0x00000001)
mbed_official	5:ac9f6c2c45e8	3586	#define RTC_TR_SU_1 ((uint32_t)0x00000002)
mbed_official	5:ac9f6c2c45e8	3587	#define RTC_TR_SU_2 ((uint32_t)0x00000004)
mbed_official	5:ac9f6c2c45e8	3588	#define RTC_TR_SU_3 ((uint32_t)0x00000008)
mbed_official	5:ac9f6c2c45e8	3589
mbed_official	5:ac9f6c2c45e8	3590	/****************** Bits definition for RTC_DR register ****************/
mbed_official	5:ac9f6c2c45e8	3591	#define RTC_DR_YT ((uint32_t)0x00F00000)
mbed_official	5:ac9f6c2c45e8	3592	#define RTC_DR_YT_0 ((uint32_t)0x00100000)
mbed_official	5:ac9f6c2c45e8	3593	#define RTC_DR_YT_1 ((uint32_t)0x00200000)
mbed_official	5:ac9f6c2c45e8	3594	#define RTC_DR_YT_2 ((uint32_t)0x00400000)
mbed_official	5:ac9f6c2c45e8	3595	#define RTC_DR_YT_3 ((uint32_t)0x00800000)
mbed_official	5:ac9f6c2c45e8	3596	#define RTC_DR_YU ((uint32_t)0x000F0000)
mbed_official	5:ac9f6c2c45e8	3597	#define RTC_DR_YU_0 ((uint32_t)0x00010000)
mbed_official	5:ac9f6c2c45e8	3598	#define RTC_DR_YU_1 ((uint32_t)0x00020000)
mbed_official	5:ac9f6c2c45e8	3599	#define RTC_DR_YU_2 ((uint32_t)0x00040000)
mbed_official	5:ac9f6c2c45e8	3600	#define RTC_DR_YU_3 ((uint32_t)0x00080000)
mbed_official	5:ac9f6c2c45e8	3601	#define RTC_DR_WDU ((uint32_t)0x0000E000)
mbed_official	5:ac9f6c2c45e8	3602	#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
mbed_official	5:ac9f6c2c45e8	3603	#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
mbed_official	5:ac9f6c2c45e8	3604	#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
mbed_official	5:ac9f6c2c45e8	3605	#define RTC_DR_MT ((uint32_t)0x00001000)
mbed_official	5:ac9f6c2c45e8	3606	#define RTC_DR_MU ((uint32_t)0x00000F00)
mbed_official	5:ac9f6c2c45e8	3607	#define RTC_DR_MU_0 ((uint32_t)0x00000100)
mbed_official	5:ac9f6c2c45e8	3608	#define RTC_DR_MU_1 ((uint32_t)0x00000200)
mbed_official	5:ac9f6c2c45e8	3609	#define RTC_DR_MU_2 ((uint32_t)0x00000400)
mbed_official	5:ac9f6c2c45e8	3610	#define RTC_DR_MU_3 ((uint32_t)0x00000800)
mbed_official	5:ac9f6c2c45e8	3611	#define RTC_DR_DT ((uint32_t)0x00000030)
mbed_official	5:ac9f6c2c45e8	3612	#define RTC_DR_DT_0 ((uint32_t)0x00000010)
mbed_official	5:ac9f6c2c45e8	3613	#define RTC_DR_DT_1 ((uint32_t)0x00000020)
mbed_official	5:ac9f6c2c45e8	3614	#define RTC_DR_DU ((uint32_t)0x0000000F)
mbed_official	5:ac9f6c2c45e8	3615	#define RTC_DR_DU_0 ((uint32_t)0x00000001)
mbed_official	5:ac9f6c2c45e8	3616	#define RTC_DR_DU_1 ((uint32_t)0x00000002)
mbed_official	5:ac9f6c2c45e8	3617	#define RTC_DR_DU_2 ((uint32_t)0x00000004)
mbed_official	5:ac9f6c2c45e8	3618	#define RTC_DR_DU_3 ((uint32_t)0x00000008)
mbed_official	5:ac9f6c2c45e8	3619
mbed_official	5:ac9f6c2c45e8	3620	/****************** Bits definition for RTC_CR register ****************/
mbed_official	5:ac9f6c2c45e8	3621	#define RTC_CR_COE ((uint32_t)0x00800000)
mbed_official	5:ac9f6c2c45e8	3622	#define RTC_CR_OSEL ((uint32_t)0x00600000)
mbed_official	5:ac9f6c2c45e8	3623	#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
mbed_official	5:ac9f6c2c45e8	3624	#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
mbed_official	5:ac9f6c2c45e8	3625	#define RTC_CR_POL ((uint32_t)0x00100000)
mbed_official	5:ac9f6c2c45e8	3626	#define RTC_CR_COSEL ((uint32_t)0x00080000)
mbed_official	5:ac9f6c2c45e8	3627	#define RTC_CR_BCK ((uint32_t)0x00040000)
mbed_official	5:ac9f6c2c45e8	3628	#define RTC_CR_SUB1H ((uint32_t)0x00020000)
mbed_official	5:ac9f6c2c45e8	3629	#define RTC_CR_ADD1H ((uint32_t)0x00010000)
mbed_official	5:ac9f6c2c45e8	3630	#define RTC_CR_TSIE ((uint32_t)0x00008000)
mbed_official	5:ac9f6c2c45e8	3631	#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
mbed_official	5:ac9f6c2c45e8	3632	#define RTC_CR_TSE ((uint32_t)0x00000800)
mbed_official	5:ac9f6c2c45e8	3633	#define RTC_CR_ALRAE ((uint32_t)0x00000100)
mbed_official	5:ac9f6c2c45e8	3634	#define RTC_CR_FMT ((uint32_t)0x00000040)
mbed_official	5:ac9f6c2c45e8	3635	#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
mbed_official	5:ac9f6c2c45e8	3636	#define RTC_CR_REFCKON ((uint32_t)0x00000010)
mbed_official	5:ac9f6c2c45e8	3637	#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
mbed_official	5:ac9f6c2c45e8	3638
mbed_official	5:ac9f6c2c45e8	3639	/****************** Bits definition for RTC_ISR register ***************/
mbed_official	5:ac9f6c2c45e8	3640	#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
mbed_official	5:ac9f6c2c45e8	3641	#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
mbed_official	5:ac9f6c2c45e8	3642	#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
mbed_official	5:ac9f6c2c45e8	3643	#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
mbed_official	5:ac9f6c2c45e8	3644	#define RTC_ISR_TSF ((uint32_t)0x00000800)
mbed_official	5:ac9f6c2c45e8	3645	#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
mbed_official	5:ac9f6c2c45e8	3646	#define RTC_ISR_INIT ((uint32_t)0x00000080)
mbed_official	5:ac9f6c2c45e8	3647	#define RTC_ISR_INITF ((uint32_t)0x00000040)
mbed_official	5:ac9f6c2c45e8	3648	#define RTC_ISR_RSF ((uint32_t)0x00000020)
mbed_official	5:ac9f6c2c45e8	3649	#define RTC_ISR_INITS ((uint32_t)0x00000010)
mbed_official	5:ac9f6c2c45e8	3650	#define RTC_ISR_SHPF ((uint32_t)0x00000008)
mbed_official	5:ac9f6c2c45e8	3651	#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
mbed_official	5:ac9f6c2c45e8	3652
mbed_official	5:ac9f6c2c45e8	3653	/****************** Bits definition for RTC_PRER register **************/
mbed_official	5:ac9f6c2c45e8	3654	#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
mbed_official	5:ac9f6c2c45e8	3655	#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
mbed_official	5:ac9f6c2c45e8	3656
mbed_official	5:ac9f6c2c45e8	3657	/****************** Bits definition for RTC_ALRMAR register ************/
mbed_official	5:ac9f6c2c45e8	3658	#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
mbed_official	5:ac9f6c2c45e8	3659	#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
mbed_official	5:ac9f6c2c45e8	3660	#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
mbed_official	5:ac9f6c2c45e8	3661	#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
mbed_official	5:ac9f6c2c45e8	3662	#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
mbed_official	5:ac9f6c2c45e8	3663	#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
mbed_official	5:ac9f6c2c45e8	3664	#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
mbed_official	5:ac9f6c2c45e8	3665	#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
mbed_official	5:ac9f6c2c45e8	3666	#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
mbed_official	5:ac9f6c2c45e8	3667	#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
mbed_official	5:ac9f6c2c45e8	3668	#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
mbed_official	5:ac9f6c2c45e8	3669	#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
mbed_official	5:ac9f6c2c45e8	3670	#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
mbed_official	5:ac9f6c2c45e8	3671	#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
mbed_official	5:ac9f6c2c45e8	3672	#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
mbed_official	5:ac9f6c2c45e8	3673	#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
mbed_official	5:ac9f6c2c45e8	3674	#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
mbed_official	5:ac9f6c2c45e8	3675	#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
mbed_official	5:ac9f6c2c45e8	3676	#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
mbed_official	5:ac9f6c2c45e8	3677	#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
mbed_official	5:ac9f6c2c45e8	3678	#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
mbed_official	5:ac9f6c2c45e8	3679	#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
mbed_official	5:ac9f6c2c45e8	3680	#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
mbed_official	5:ac9f6c2c45e8	3681	#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
mbed_official	5:ac9f6c2c45e8	3682	#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
mbed_official	5:ac9f6c2c45e8	3683	#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
mbed_official	5:ac9f6c2c45e8	3684	#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
mbed_official	5:ac9f6c2c45e8	3685	#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
mbed_official	5:ac9f6c2c45e8	3686	#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
mbed_official	5:ac9f6c2c45e8	3687	#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
mbed_official	5:ac9f6c2c45e8	3688	#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
mbed_official	5:ac9f6c2c45e8	3689	#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
mbed_official	5:ac9f6c2c45e8	3690	#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
mbed_official	5:ac9f6c2c45e8	3691	#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
mbed_official	5:ac9f6c2c45e8	3692	#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
mbed_official	5:ac9f6c2c45e8	3693	#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
mbed_official	5:ac9f6c2c45e8	3694	#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
mbed_official	5:ac9f6c2c45e8	3695	#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
mbed_official	5:ac9f6c2c45e8	3696	#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
mbed_official	5:ac9f6c2c45e8	3697	#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
mbed_official	5:ac9f6c2c45e8	3698
mbed_official	5:ac9f6c2c45e8	3699	/****************** Bits definition for RTC_WPR register ***************/
mbed_official	5:ac9f6c2c45e8	3700	#define RTC_WPR_KEY ((uint32_t)0x000000FF)
mbed_official	5:ac9f6c2c45e8	3701
mbed_official	5:ac9f6c2c45e8	3702	/****************** Bits definition for RTC_SSR register ***************/
mbed_official	5:ac9f6c2c45e8	3703	#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
mbed_official	5:ac9f6c2c45e8	3704
mbed_official	5:ac9f6c2c45e8	3705	/****************** Bits definition for RTC_SHIFTR register ************/
mbed_official	5:ac9f6c2c45e8	3706	#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
mbed_official	5:ac9f6c2c45e8	3707	#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
mbed_official	5:ac9f6c2c45e8	3708
mbed_official	5:ac9f6c2c45e8	3709	/****************** Bits definition for RTC_TSTR register **************/
mbed_official	5:ac9f6c2c45e8	3710	#define RTC_TSTR_PM ((uint32_t)0x00400000)
mbed_official	5:ac9f6c2c45e8	3711	#define RTC_TSTR_HT ((uint32_t)0x00300000)
mbed_official	5:ac9f6c2c45e8	3712	#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
mbed_official	5:ac9f6c2c45e8	3713	#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
mbed_official	5:ac9f6c2c45e8	3714	#define RTC_TSTR_HU ((uint32_t)0x000F0000)
mbed_official	5:ac9f6c2c45e8	3715	#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
mbed_official	5:ac9f6c2c45e8	3716	#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
mbed_official	5:ac9f6c2c45e8	3717	#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
mbed_official	5:ac9f6c2c45e8	3718	#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
mbed_official	5:ac9f6c2c45e8	3719	#define RTC_TSTR_MNT ((uint32_t)0x00007000)
mbed_official	5:ac9f6c2c45e8	3720	#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
mbed_official	5:ac9f6c2c45e8	3721	#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
mbed_official	5:ac9f6c2c45e8	3722	#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
mbed_official	5:ac9f6c2c45e8	3723	#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
mbed_official	5:ac9f6c2c45e8	3724	#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
mbed_official	5:ac9f6c2c45e8	3725	#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
mbed_official	5:ac9f6c2c45e8	3726	#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
mbed_official	5:ac9f6c2c45e8	3727	#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
mbed_official	5:ac9f6c2c45e8	3728	#define RTC_TSTR_ST ((uint32_t)0x00000070)
mbed_official	5:ac9f6c2c45e8	3729	#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
mbed_official	5:ac9f6c2c45e8	3730	#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
mbed_official	5:ac9f6c2c45e8	3731	#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
mbed_official	5:ac9f6c2c45e8	3732	#define RTC_TSTR_SU ((uint32_t)0x0000000F)
mbed_official	5:ac9f6c2c45e8	3733	#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
mbed_official	5:ac9f6c2c45e8	3734	#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
mbed_official	5:ac9f6c2c45e8	3735	#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
mbed_official	5:ac9f6c2c45e8	3736	#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
mbed_official	5:ac9f6c2c45e8	3737
mbed_official	5:ac9f6c2c45e8	3738	/****************** Bits definition for RTC_TSDR register **************/
mbed_official	5:ac9f6c2c45e8	3739	#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
mbed_official	5:ac9f6c2c45e8	3740	#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
mbed_official	5:ac9f6c2c45e8	3741	#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
mbed_official	5:ac9f6c2c45e8	3742	#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
mbed_official	5:ac9f6c2c45e8	3743	#define RTC_TSDR_MT ((uint32_t)0x00001000)
mbed_official	5:ac9f6c2c45e8	3744	#define RTC_TSDR_MU ((uint32_t)0x00000F00)
mbed_official	5:ac9f6c2c45e8	3745	#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
mbed_official	5:ac9f6c2c45e8	3746	#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
mbed_official	5:ac9f6c2c45e8	3747	#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
mbed_official	5:ac9f6c2c45e8	3748	#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
mbed_official	5:ac9f6c2c45e8	3749	#define RTC_TSDR_DT ((uint32_t)0x00000030)
mbed_official	5:ac9f6c2c45e8	3750	#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
mbed_official	5:ac9f6c2c45e8	3751	#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
mbed_official	5:ac9f6c2c45e8	3752	#define RTC_TSDR_DU ((uint32_t)0x0000000F)
mbed_official	5:ac9f6c2c45e8	3753	#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
mbed_official	5:ac9f6c2c45e8	3754	#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
mbed_official	5:ac9f6c2c45e8	3755	#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
mbed_official	5:ac9f6c2c45e8	3756	#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
mbed_official	5:ac9f6c2c45e8	3757
mbed_official	5:ac9f6c2c45e8	3758	/****************** Bits definition for RTC_TSSSR register *************/
mbed_official	5:ac9f6c2c45e8	3759	#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
mbed_official	5:ac9f6c2c45e8	3760
mbed_official	5:ac9f6c2c45e8	3761	/****************** Bits definition for RTC_CALR register **************/
mbed_official	5:ac9f6c2c45e8	3762	#define RTC_CALR_CALP ((uint32_t)0x00008000)
mbed_official	5:ac9f6c2c45e8	3763	#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
mbed_official	5:ac9f6c2c45e8	3764	#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
mbed_official	5:ac9f6c2c45e8	3765	#define RTC_CALR_CALM ((uint32_t)0x000001FF)
mbed_official	5:ac9f6c2c45e8	3766	#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
mbed_official	5:ac9f6c2c45e8	3767	#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
mbed_official	5:ac9f6c2c45e8	3768	#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
mbed_official	5:ac9f6c2c45e8	3769	#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
mbed_official	5:ac9f6c2c45e8	3770	#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
mbed_official	5:ac9f6c2c45e8	3771	#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
mbed_official	5:ac9f6c2c45e8	3772	#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
mbed_official	5:ac9f6c2c45e8	3773	#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
mbed_official	5:ac9f6c2c45e8	3774	#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
mbed_official	5:ac9f6c2c45e8	3775
mbed_official	5:ac9f6c2c45e8	3776	/****************** Bits definition for RTC_TAFCR register *************/
mbed_official	5:ac9f6c2c45e8	3777	#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
mbed_official	5:ac9f6c2c45e8	3778	#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
mbed_official	5:ac9f6c2c45e8	3779	#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
mbed_official	5:ac9f6c2c45e8	3780	#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
mbed_official	5:ac9f6c2c45e8	3781	#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
mbed_official	5:ac9f6c2c45e8	3782	#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
mbed_official	5:ac9f6c2c45e8	3783	#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
mbed_official	5:ac9f6c2c45e8	3784	#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
mbed_official	5:ac9f6c2c45e8	3785	#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
mbed_official	5:ac9f6c2c45e8	3786	#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
mbed_official	5:ac9f6c2c45e8	3787	#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
mbed_official	5:ac9f6c2c45e8	3788	#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
mbed_official	5:ac9f6c2c45e8	3789	#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
mbed_official	5:ac9f6c2c45e8	3790	#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
mbed_official	5:ac9f6c2c45e8	3791	#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
mbed_official	5:ac9f6c2c45e8	3792	#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
mbed_official	5:ac9f6c2c45e8	3793	#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
mbed_official	5:ac9f6c2c45e8	3794	#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
mbed_official	5:ac9f6c2c45e8	3795
mbed_official	5:ac9f6c2c45e8	3796	/****************** Bits definition for RTC_ALRMASSR register **********/
mbed_official	5:ac9f6c2c45e8	3797	#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
mbed_official	5:ac9f6c2c45e8	3798	#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
mbed_official	5:ac9f6c2c45e8	3799	#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
mbed_official	5:ac9f6c2c45e8	3800	#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
mbed_official	5:ac9f6c2c45e8	3801	#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
mbed_official	5:ac9f6c2c45e8	3802	#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
mbed_official	5:ac9f6c2c45e8	3803
mbed_official	5:ac9f6c2c45e8	3804	/****************** Bits definition for RTC_BKP0R register *************/
mbed_official	5:ac9f6c2c45e8	3805	#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
mbed_official	5:ac9f6c2c45e8	3806
mbed_official	5:ac9f6c2c45e8	3807	/****************** Bits definition for RTC_BKP1R register *************/
mbed_official	5:ac9f6c2c45e8	3808	#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
mbed_official	5:ac9f6c2c45e8	3809
mbed_official	5:ac9f6c2c45e8	3810	/****************** Bits definition for RTC_BKP2R register *************/
mbed_official	5:ac9f6c2c45e8	3811	#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
mbed_official	5:ac9f6c2c45e8	3812
mbed_official	5:ac9f6c2c45e8	3813	/****************** Bits definition for RTC_BKP3R register *************/
mbed_official	5:ac9f6c2c45e8	3814	#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
mbed_official	5:ac9f6c2c45e8	3815
mbed_official	5:ac9f6c2c45e8	3816	/****************** Bits definition for RTC_BKP4R register *************/
mbed_official	5:ac9f6c2c45e8	3817	#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
mbed_official	5:ac9f6c2c45e8	3818
mbed_official	5:ac9f6c2c45e8	3819	/****************** Number of backup registers ****************************/
mbed_official	5:ac9f6c2c45e8	3820	#define RTC_BKP_NUMBER ((uint32_t)0x00000005)
mbed_official	5:ac9f6c2c45e8	3821
mbed_official	5:ac9f6c2c45e8	3822	/*****************************************************************************/
mbed_official	5:ac9f6c2c45e8	3823	/* */
mbed_official	5:ac9f6c2c45e8	3824	/* Serial Peripheral Interface (SPI) */
mbed_official	5:ac9f6c2c45e8	3825	/* */
mbed_official	5:ac9f6c2c45e8	3826	/*****************************************************************************/
mbed_official	5:ac9f6c2c45e8	3827	/***************** Bit definition for SPI_CR1 register *****************/
mbed_official	5:ac9f6c2c45e8	3828	#define SPI_CR1_CPHA ((uint32_t)0x00000001) /!< Clock Phase /
mbed_official	5:ac9f6c2c45e8	3829	#define SPI_CR1_CPOL ((uint32_t)0x00000002) /!< Clock Polarity /
mbed_official	5:ac9f6c2c45e8	3830	#define SPI_CR1_MSTR ((uint32_t)0x00000004) /!< Master Selection /
mbed_official	5:ac9f6c2c45e8	3831	#define SPI_CR1_BR ((uint32_t)0x00000038) /!< BR[2:0] bits (Baud Rate Control) /
mbed_official	5:ac9f6c2c45e8	3832	#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /!< Bit 0 /
mbed_official	5:ac9f6c2c45e8	3833	#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /!< Bit 1 /
mbed_official	5:ac9f6c2c45e8	3834	#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /!< Bit 2 /
mbed_official	5:ac9f6c2c45e8	3835	#define SPI_CR1_SPE ((uint32_t)0x00000040) /!< SPI Enable /
mbed_official	5:ac9f6c2c45e8	3836	#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /!< Frame Format /
mbed_official	5:ac9f6c2c45e8	3837	#define SPI_CR1_SSI ((uint32_t)0x00000100) /!< Internal slave select /
mbed_official	5:ac9f6c2c45e8	3838	#define SPI_CR1_SSM ((uint32_t)0x00000200) /!< Software slave management /
mbed_official	5:ac9f6c2c45e8	3839	#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /!< Receive only /
mbed_official	5:ac9f6c2c45e8	3840	#define SPI_CR1_CRCL ((uint32_t)0x00000800) /!< CRC Length /
mbed_official	5:ac9f6c2c45e8	3841	#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /!< Transmit CRC next /
mbed_official	5:ac9f6c2c45e8	3842	#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /!< Hardware CRC calculation enable /
mbed_official	5:ac9f6c2c45e8	3843	#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /!< Output enable in bidirectional mode /
mbed_official	5:ac9f6c2c45e8	3844	#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /!< Bidirectional data mode enable /
mbed_official	5:ac9f6c2c45e8	3845
mbed_official	5:ac9f6c2c45e8	3846	/***************** Bit definition for SPI_CR2 register *****************/
mbed_official	5:ac9f6c2c45e8	3847	#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /!< Rx Buffer DMA Enable /
mbed_official	5:ac9f6c2c45e8	3848	#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /!< Tx Buffer DMA Enable /
mbed_official	5:ac9f6c2c45e8	3849	#define SPI_CR2_SSOE ((uint32_t)0x00000004) /!< SS Output Enable /
mbed_official	5:ac9f6c2c45e8	3850	#define SPI_CR2_NSSP ((uint32_t)0x00000008) /!< NSS pulse management Enable /
mbed_official	5:ac9f6c2c45e8	3851	#define SPI_CR2_FRF ((uint32_t)0x00000010) /!< Frame Format Enable /
mbed_official	5:ac9f6c2c45e8	3852	#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /!< Error Interrupt Enable /
mbed_official	5:ac9f6c2c45e8	3853	#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /!< RX buffer Not Empty Interrupt Enable /
mbed_official	5:ac9f6c2c45e8	3854	#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /!< Tx buffer Empty Interrupt Enable /
mbed_official	5:ac9f6c2c45e8	3855	#define SPI_CR2_DS ((uint32_t)0x00000F00) /!< DS[3:0] Data Size /
mbed_official	5:ac9f6c2c45e8	3856	#define SPI_CR2_DS_0 ((uint32_t)0x00000100) /!< Bit 0 /
mbed_official	5:ac9f6c2c45e8	3857	#define SPI_CR2_DS_1 ((uint32_t)0x00000200) /!< Bit 1 /
mbed_official	5:ac9f6c2c45e8	3858	#define SPI_CR2_DS_2 ((uint32_t)0x00000400) /!< Bit 2 /
mbed_official	5:ac9f6c2c45e8	3859	#define SPI_CR2_DS_3 ((uint32_t)0x00000800) /!< Bit 3 /
mbed_official	5:ac9f6c2c45e8	3860	#define SPI_CR2_FRXTH ((uint32_t)0x00001000) /!< FIFO reception Threshold /
mbed_official	5:ac9f6c2c45e8	3861	#define SPI_CR2_LDMARX ((uint32_t)0x00002000) /!< Last DMA transfer for reception /
mbed_official	5:ac9f6c2c45e8	3862	#define SPI_CR2_LDMATX ((uint32_t)0x00004000) /!< Last DMA transfer for transmission /
mbed_official	5:ac9f6c2c45e8	3863
mbed_official	5:ac9f6c2c45e8	3864	/****************** Bit definition for SPI_SR register *****************/
mbed_official	5:ac9f6c2c45e8	3865	#define SPI_SR_RXNE ((uint32_t)0x00000001) /!< Receive buffer Not Empty /
mbed_official	5:ac9f6c2c45e8	3866	#define SPI_SR_TXE ((uint32_t)0x00000002) /!< Transmit buffer Empty /
mbed_official	5:ac9f6c2c45e8	3867	#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /!< Channel side /
mbed_official	5:ac9f6c2c45e8	3868	#define SPI_SR_UDR ((uint32_t)0x00000008) /!< Underrun flag /
mbed_official	5:ac9f6c2c45e8	3869	#define SPI_SR_CRCERR ((uint32_t)0x00000010) /!< CRC Error flag /
mbed_official	5:ac9f6c2c45e8	3870	#define SPI_SR_MODF ((uint32_t)0x00000020) /!< Mode fault /
mbed_official	5:ac9f6c2c45e8	3871	#define SPI_SR_OVR ((uint32_t)0x00000040) /!< Overrun flag /
mbed_official	5:ac9f6c2c45e8	3872	#define SPI_SR_BSY ((uint32_t)0x00000080) /!< Busy flag /
mbed_official	5:ac9f6c2c45e8	3873	#define SPI_SR_FRE ((uint32_t)0x00000100) /!< TI frame format error /
mbed_official	5:ac9f6c2c45e8	3874	#define SPI_SR_FRLVL ((uint32_t)0x00000600) /!< FIFO Reception Level /
mbed_official	5:ac9f6c2c45e8	3875	#define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /!< Bit 0 /
mbed_official	5:ac9f6c2c45e8	3876	#define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /!< Bit 1 /
mbed_official	5:ac9f6c2c45e8	3877	#define SPI_SR_FTLVL ((uint32_t)0x00001800) /!< FIFO Transmission Level /
mbed_official	5:ac9f6c2c45e8	3878	#define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /!< Bit 0 /
mbed_official	5:ac9f6c2c45e8	3879	#define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /!< Bit 1 /
mbed_official	5:ac9f6c2c45e8	3880
mbed_official	5:ac9f6c2c45e8	3881	/****************** Bit definition for SPI_DR register *****************/
mbed_official	5:ac9f6c2c45e8	3882	#define SPI_DR_DR ((uint32_t)0xFFFFFFFF) /!< Data Register /
mbed_official	5:ac9f6c2c45e8	3883
mbed_official	5:ac9f6c2c45e8	3884	/***************** Bit definition for SPI_CRCPR register ***************/
mbed_official	5:ac9f6c2c45e8	3885	#define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFFFFFF) /!< CRC polynomial register /
mbed_official	5:ac9f6c2c45e8	3886
mbed_official	5:ac9f6c2c45e8	3887	/**************** Bit definition for SPI_RXCRCR register ***************/
mbed_official	5:ac9f6c2c45e8	3888	#define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFFFFFF) /!< Rx CRC Register /
mbed_official	5:ac9f6c2c45e8	3889
mbed_official	5:ac9f6c2c45e8	3890	/**************** Bit definition for SPI_TXCRCR register ***************/
mbed_official	5:ac9f6c2c45e8	3891	#define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFFFFFF) /!< Tx CRC Register /
mbed_official	5:ac9f6c2c45e8	3892
mbed_official	5:ac9f6c2c45e8	3893	/**************** Bit definition for SPI_I2SCFGR register **************/
mbed_official	5:ac9f6c2c45e8	3894	#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /!<Channel length (number of bits per audio channel) /
mbed_official	5:ac9f6c2c45e8	3895	#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /!<DATLEN[1:0] bits (Data length to be transferred) /
mbed_official	5:ac9f6c2c45e8	3896	#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	3897	#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	3898	#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /!<steady state clock polarity /
mbed_official	5:ac9f6c2c45e8	3899	#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /!<I2SSTD[1:0] bits (I2S standard selection) /
mbed_official	5:ac9f6c2c45e8	3900	#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	3901	#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	3902	#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /!<PCM frame synchronization /
mbed_official	5:ac9f6c2c45e8	3903	#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /!<I2SCFG[1:0] bits (I2S configuration mode) /
mbed_official	5:ac9f6c2c45e8	3904	#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	3905	#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	3906	#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /!<I2S Enable /
mbed_official	5:ac9f6c2c45e8	3907	#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /!<I2S mode selection /
mbed_official	5:ac9f6c2c45e8	3908
mbed_official	5:ac9f6c2c45e8	3909	/**************** Bit definition for SPI_I2SPR register ****************/
mbed_official	5:ac9f6c2c45e8	3910	#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /!<I2S Linear prescaler /
mbed_official	5:ac9f6c2c45e8	3911	#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /!<Odd factor for the prescaler /
mbed_official	5:ac9f6c2c45e8	3912	#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /!<Master Clock Output Enable /
mbed_official	5:ac9f6c2c45e8	3913
mbed_official	5:ac9f6c2c45e8	3914	/*****************************************************************************/
mbed_official	5:ac9f6c2c45e8	3915	/* */
mbed_official	5:ac9f6c2c45e8	3916	/* System Configuration (SYSCFG) */
mbed_official	5:ac9f6c2c45e8	3917	/* */
mbed_official	5:ac9f6c2c45e8	3918	/*****************************************************************************/
mbed_official	5:ac9f6c2c45e8	3919	/*************** Bit definition for SYSCFG_CFGR1 register **************/
mbed_official	5:ac9f6c2c45e8	3920	#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /!< SYSCFG_Memory Remap Config /
mbed_official	5:ac9f6c2c45e8	3921	#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /!< SYSCFG_Memory Remap Config Bit 0 /
mbed_official	5:ac9f6c2c45e8	3922	#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /!< SYSCFG_Memory Remap Config Bit 1 /
mbed_official	5:ac9f6c2c45e8	3923
mbed_official	5:ac9f6c2c45e8	3924	#define SYSCFG_CFGR1_PA11_PA12_RMP ((uint32_t)0x00000010) /!< PA11 and PA12 remap on QFN28 and TSSOP20 packages /
mbed_official	5:ac9f6c2c45e8	3925
mbed_official	5:ac9f6c2c45e8	3926	#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00001F00) /!< DMA remap mask /
mbed_official	5:ac9f6c2c45e8	3927	#define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /!< ADC DMA remap /
mbed_official	5:ac9f6c2c45e8	3928	#define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /!< USART1 TX DMA remap /
mbed_official	5:ac9f6c2c45e8	3929	#define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /!< USART1 RX DMA remap /
mbed_official	5:ac9f6c2c45e8	3930	#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /!< Timer 16 DMA remap /
mbed_official	5:ac9f6c2c45e8	3931	#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /!< Timer 17 DMA remap /
mbed_official	5:ac9f6c2c45e8	3932
mbed_official	5:ac9f6c2c45e8	3933	#define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /!< I2C PB6 Fast mode plus /
mbed_official	5:ac9f6c2c45e8	3934	#define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /!< I2C PB7 Fast mode plus /
mbed_official	5:ac9f6c2c45e8	3935	#define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /!< I2C PB8 Fast mode plus /
mbed_official	5:ac9f6c2c45e8	3936	#define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /!< I2C PB9 Fast mode plus /
mbed_official	5:ac9f6c2c45e8	3937	#define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 /
mbed_official	5:ac9f6c2c45e8	3938	#define SYSCFG_CFGR1_I2C_FMP_I2C2 ((uint32_t)0x00200000) /!< Enable I2C2 Fast mode plus /
mbed_official	5:ac9f6c2c45e8	3939	#define SYSCFG_CFGR1_I2C_FMP_PA9 ((uint32_t)0x00400000) /!< Enable Fast Mode Plus on PA9 /
mbed_official	5:ac9f6c2c45e8	3940	#define SYSCFG_CFGR1_I2C_FMP_PA10 ((uint32_t)0x00800000) /!< Enable Fast Mode Plus on PA10 /
mbed_official	5:ac9f6c2c45e8	3941
mbed_official	5:ac9f6c2c45e8	3942	/*************** Bit definition for SYSCFG_EXTICR1 register ************/
mbed_official	5:ac9f6c2c45e8	3943	#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /!< EXTI 0 configuration /
mbed_official	5:ac9f6c2c45e8	3944	#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /!< EXTI 1 configuration /
mbed_official	5:ac9f6c2c45e8	3945	#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /!< EXTI 2 configuration /
mbed_official	5:ac9f6c2c45e8	3946	#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /!< EXTI 3 configuration /
mbed_official	5:ac9f6c2c45e8	3947
mbed_official	5:ac9f6c2c45e8	3948	/**
mbed_official	5:ac9f6c2c45e8	3949	* @brief EXTI0 configuration
mbed_official	5:ac9f6c2c45e8	3950	*/
mbed_official	5:ac9f6c2c45e8	3951	#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /!< PA[0] pin /
mbed_official	5:ac9f6c2c45e8	3952	#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /!< PB[0] pin /
mbed_official	5:ac9f6c2c45e8	3953	#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /!< PC[0] pin /
mbed_official	5:ac9f6c2c45e8	3954	#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /!< PD[0] pin /
mbed_official	5:ac9f6c2c45e8	3955	#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /!< PE[0] pin /
mbed_official	5:ac9f6c2c45e8	3956	#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /!< PF[0] pin /
mbed_official	5:ac9f6c2c45e8	3957
mbed_official	5:ac9f6c2c45e8	3958	/**
mbed_official	5:ac9f6c2c45e8	3959	* @brief EXTI1 configuration
mbed_official	5:ac9f6c2c45e8	3960	*/
mbed_official	5:ac9f6c2c45e8	3961	#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /!< PA[1] pin /
mbed_official	5:ac9f6c2c45e8	3962	#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /!< PB[1] pin /
mbed_official	5:ac9f6c2c45e8	3963	#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /!< PC[1] pin /
mbed_official	5:ac9f6c2c45e8	3964	#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /!< PD[1] pin /
mbed_official	5:ac9f6c2c45e8	3965	#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /!< PE[1] pin /
mbed_official	5:ac9f6c2c45e8	3966	#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /!< PF[1] pin /
mbed_official	5:ac9f6c2c45e8	3967
mbed_official	5:ac9f6c2c45e8	3968	/**
mbed_official	5:ac9f6c2c45e8	3969	* @brief EXTI2 configuration
mbed_official	5:ac9f6c2c45e8	3970	*/
mbed_official	5:ac9f6c2c45e8	3971	#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /!< PA[2] pin /
mbed_official	5:ac9f6c2c45e8	3972	#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /!< PB[2] pin /
mbed_official	5:ac9f6c2c45e8	3973	#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /!< PC[2] pin /
mbed_official	5:ac9f6c2c45e8	3974	#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /!< PD[2] pin /
mbed_official	5:ac9f6c2c45e8	3975	#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /!< PE[2] pin /
mbed_official	5:ac9f6c2c45e8	3976	#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /!< PF[2] pin /
mbed_official	5:ac9f6c2c45e8	3977
mbed_official	5:ac9f6c2c45e8	3978	/**
mbed_official	5:ac9f6c2c45e8	3979	* @brief EXTI3 configuration
mbed_official	5:ac9f6c2c45e8	3980	*/
mbed_official	5:ac9f6c2c45e8	3981	#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /!< PA[3] pin /
mbed_official	5:ac9f6c2c45e8	3982	#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /!< PB[3] pin /
mbed_official	5:ac9f6c2c45e8	3983	#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /!< PC[3] pin /
mbed_official	5:ac9f6c2c45e8	3984	#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /!< PD[3] pin /
mbed_official	5:ac9f6c2c45e8	3985	#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /!< PE[3] pin /
mbed_official	5:ac9f6c2c45e8	3986	#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /!< PF[3] pin /
mbed_official	5:ac9f6c2c45e8	3987
mbed_official	5:ac9f6c2c45e8	3988	/*************** Bit definition for SYSCFG_EXTICR2 register ************/
mbed_official	5:ac9f6c2c45e8	3989	#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /!< EXTI 4 configuration /
mbed_official	5:ac9f6c2c45e8	3990	#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /!< EXTI 5 configuration /
mbed_official	5:ac9f6c2c45e8	3991	#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /!< EXTI 6 configuration /
mbed_official	5:ac9f6c2c45e8	3992	#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /!< EXTI 7 configuration /
mbed_official	5:ac9f6c2c45e8	3993
mbed_official	5:ac9f6c2c45e8	3994	/**
mbed_official	5:ac9f6c2c45e8	3995	* @brief EXTI4 configuration
mbed_official	5:ac9f6c2c45e8	3996	*/
mbed_official	5:ac9f6c2c45e8	3997	#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /!< PA[4] pin /
mbed_official	5:ac9f6c2c45e8	3998	#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /!< PB[4] pin /
mbed_official	5:ac9f6c2c45e8	3999	#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /!< PC[4] pin /
mbed_official	5:ac9f6c2c45e8	4000	#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /!< PD[4] pin /
mbed_official	5:ac9f6c2c45e8	4001	#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /!< PE[4] pin /
mbed_official	5:ac9f6c2c45e8	4002	#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /!< PF[4] pin /
mbed_official	5:ac9f6c2c45e8	4003
mbed_official	5:ac9f6c2c45e8	4004	/**
mbed_official	5:ac9f6c2c45e8	4005	* @brief EXTI5 configuration
mbed_official	5:ac9f6c2c45e8	4006	*/
mbed_official	5:ac9f6c2c45e8	4007	#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /!< PA[5] pin /
mbed_official	5:ac9f6c2c45e8	4008	#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /!< PB[5] pin /
mbed_official	5:ac9f6c2c45e8	4009	#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /!< PC[5] pin /
mbed_official	5:ac9f6c2c45e8	4010	#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /!< PD[5] pin /
mbed_official	5:ac9f6c2c45e8	4011	#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /!< PE[5] pin /
mbed_official	5:ac9f6c2c45e8	4012	#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /!< PF[5] pin /
mbed_official	5:ac9f6c2c45e8	4013
mbed_official	5:ac9f6c2c45e8	4014	/**
mbed_official	5:ac9f6c2c45e8	4015	* @brief EXTI6 configuration
mbed_official	5:ac9f6c2c45e8	4016	*/
mbed_official	5:ac9f6c2c45e8	4017	#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /!< PA[6] pin /
mbed_official	5:ac9f6c2c45e8	4018	#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /!< PB[6] pin /
mbed_official	5:ac9f6c2c45e8	4019	#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /!< PC[6] pin /
mbed_official	5:ac9f6c2c45e8	4020	#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /!< PD[6] pin /
mbed_official	5:ac9f6c2c45e8	4021	#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /!< PE[6] pin /
mbed_official	5:ac9f6c2c45e8	4022	#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /!< PF[6] pin /
mbed_official	5:ac9f6c2c45e8	4023
mbed_official	5:ac9f6c2c45e8	4024	/**
mbed_official	5:ac9f6c2c45e8	4025	* @brief EXTI7 configuration
mbed_official	5:ac9f6c2c45e8	4026	*/
mbed_official	5:ac9f6c2c45e8	4027	#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /!< PA[7] pin /
mbed_official	5:ac9f6c2c45e8	4028	#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /!< PB[7] pin /
mbed_official	5:ac9f6c2c45e8	4029	#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /!< PC[7] pin /
mbed_official	5:ac9f6c2c45e8	4030	#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /!< PD[7] pin /
mbed_official	5:ac9f6c2c45e8	4031	#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /!< PE[7] pin /
mbed_official	5:ac9f6c2c45e8	4032	#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /!< PF[7] pin /
mbed_official	5:ac9f6c2c45e8	4033
mbed_official	5:ac9f6c2c45e8	4034	/*************** Bit definition for SYSCFG_EXTICR3 register ************/
mbed_official	5:ac9f6c2c45e8	4035	#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /!< EXTI 8 configuration /
mbed_official	5:ac9f6c2c45e8	4036	#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /!< EXTI 9 configuration /
mbed_official	5:ac9f6c2c45e8	4037	#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /!< EXTI 10 configuration /
mbed_official	5:ac9f6c2c45e8	4038	#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /!< EXTI 11 configuration /
mbed_official	5:ac9f6c2c45e8	4039
mbed_official	5:ac9f6c2c45e8	4040	/**
mbed_official	5:ac9f6c2c45e8	4041	* @brief EXTI8 configuration
mbed_official	5:ac9f6c2c45e8	4042	*/
mbed_official	5:ac9f6c2c45e8	4043	#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /!< PA[8] pin /
mbed_official	5:ac9f6c2c45e8	4044	#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /!< PB[8] pin /
mbed_official	5:ac9f6c2c45e8	4045	#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /!< PC[8] pin /
mbed_official	5:ac9f6c2c45e8	4046	#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /!< PD[8] pin /
mbed_official	5:ac9f6c2c45e8	4047	#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /!< PE[8] pin /
mbed_official	5:ac9f6c2c45e8	4048
mbed_official	5:ac9f6c2c45e8	4049	/**
mbed_official	5:ac9f6c2c45e8	4050	* @brief EXTI9 configuration
mbed_official	5:ac9f6c2c45e8	4051	*/
mbed_official	5:ac9f6c2c45e8	4052	#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /!< PA[9] pin /
mbed_official	5:ac9f6c2c45e8	4053	#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /!< PB[9] pin /
mbed_official	5:ac9f6c2c45e8	4054	#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /!< PC[9] pin /
mbed_official	5:ac9f6c2c45e8	4055	#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /!< PD[9] pin /
mbed_official	5:ac9f6c2c45e8	4056	#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /!< PE[9] pin /
mbed_official	5:ac9f6c2c45e8	4057	#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /!< PF[9] pin /
mbed_official	5:ac9f6c2c45e8	4058
mbed_official	5:ac9f6c2c45e8	4059	/**
mbed_official	5:ac9f6c2c45e8	4060	* @brief EXTI10 configuration
mbed_official	5:ac9f6c2c45e8	4061	*/
mbed_official	5:ac9f6c2c45e8	4062	#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /!< PA[10] pin /
mbed_official	5:ac9f6c2c45e8	4063	#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /!< PB[10] pin /
mbed_official	5:ac9f6c2c45e8	4064	#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /!< PC[10] pin /
mbed_official	5:ac9f6c2c45e8	4065	#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /!< PE[10] pin /
mbed_official	5:ac9f6c2c45e8	4066	#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /!< PD[10] pin /
mbed_official	5:ac9f6c2c45e8	4067	#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /!< PF[10] pin /
mbed_official	5:ac9f6c2c45e8	4068
mbed_official	5:ac9f6c2c45e8	4069	/**
mbed_official	5:ac9f6c2c45e8	4070	* @brief EXTI11 configuration
mbed_official	5:ac9f6c2c45e8	4071	*/
mbed_official	5:ac9f6c2c45e8	4072	#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /!< PA[11] pin /
mbed_official	5:ac9f6c2c45e8	4073	#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /!< PB[11] pin /
mbed_official	5:ac9f6c2c45e8	4074	#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /!< PC[11] pin /
mbed_official	5:ac9f6c2c45e8	4075	#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /!< PD[11] pin /
mbed_official	5:ac9f6c2c45e8	4076	#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /!< PE[11] pin /
mbed_official	5:ac9f6c2c45e8	4077
mbed_official	5:ac9f6c2c45e8	4078	/*************** Bit definition for SYSCFG_EXTICR4 register ************/
mbed_official	5:ac9f6c2c45e8	4079	#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /!< EXTI 12 configuration /
mbed_official	5:ac9f6c2c45e8	4080	#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /!< EXTI 13 configuration /
mbed_official	5:ac9f6c2c45e8	4081	#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /!< EXTI 14 configuration /
mbed_official	5:ac9f6c2c45e8	4082	#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /!< EXTI 15 configuration /
mbed_official	5:ac9f6c2c45e8	4083
mbed_official	5:ac9f6c2c45e8	4084	/**
mbed_official	5:ac9f6c2c45e8	4085	* @brief EXTI12 configuration
mbed_official	5:ac9f6c2c45e8	4086	*/
mbed_official	5:ac9f6c2c45e8	4087	#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /!< PA[12] pin /
mbed_official	5:ac9f6c2c45e8	4088	#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /!< PB[12] pin /
mbed_official	5:ac9f6c2c45e8	4089	#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /!< PC[12] pin /
mbed_official	5:ac9f6c2c45e8	4090	#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /!< PD[12] pin /
mbed_official	5:ac9f6c2c45e8	4091	#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /!< PE[12] pin /
mbed_official	5:ac9f6c2c45e8	4092
mbed_official	5:ac9f6c2c45e8	4093	/**
mbed_official	5:ac9f6c2c45e8	4094	* @brief EXTI13 configuration
mbed_official	5:ac9f6c2c45e8	4095	*/
mbed_official	5:ac9f6c2c45e8	4096	#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /!< PA[13] pin /
mbed_official	5:ac9f6c2c45e8	4097	#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /!< PB[13] pin /
mbed_official	5:ac9f6c2c45e8	4098	#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /!< PC[13] pin /
mbed_official	5:ac9f6c2c45e8	4099	#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /!< PD[13] pin /
mbed_official	5:ac9f6c2c45e8	4100	#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /!< PE[13] pin /
mbed_official	5:ac9f6c2c45e8	4101
mbed_official	5:ac9f6c2c45e8	4102	/**
mbed_official	5:ac9f6c2c45e8	4103	* @brief EXTI14 configuration
mbed_official	5:ac9f6c2c45e8	4104	*/
mbed_official	5:ac9f6c2c45e8	4105	#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /!< PA[14] pin /
mbed_official	5:ac9f6c2c45e8	4106	#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /!< PB[14] pin /
mbed_official	5:ac9f6c2c45e8	4107	#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /!< PC[14] pin /
mbed_official	5:ac9f6c2c45e8	4108	#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /!< PD[14] pin /
mbed_official	5:ac9f6c2c45e8	4109	#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /!< PE[14] pin /
mbed_official	5:ac9f6c2c45e8	4110
mbed_official	5:ac9f6c2c45e8	4111	/**
mbed_official	5:ac9f6c2c45e8	4112	* @brief EXTI15 configuration
mbed_official	5:ac9f6c2c45e8	4113	*/
mbed_official	5:ac9f6c2c45e8	4114	#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /!< PA[15] pin /
mbed_official	5:ac9f6c2c45e8	4115	#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /!< PB[15] pin /
mbed_official	5:ac9f6c2c45e8	4116	#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /!< PC[15] pin /
mbed_official	5:ac9f6c2c45e8	4117	#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /!< PD[15] pin /
mbed_official	5:ac9f6c2c45e8	4118	#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /!< PE[15] pin /
mbed_official	5:ac9f6c2c45e8	4119
mbed_official	5:ac9f6c2c45e8	4120	/*************** Bit definition for SYSCFG_CFGR2 register **************/
mbed_official	5:ac9f6c2c45e8	4121	#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 /
mbed_official	5:ac9f6c2c45e8	4122	#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 /
mbed_official	5:ac9f6c2c45e8	4123	#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface /
mbed_official	5:ac9f6c2c45e8	4124	#define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /!< SRAM Parity error flag /
mbed_official	5:ac9f6c2c45e8	4125	#define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /!< SRAM Parity error flag (define maintained for legacy purpose) /
mbed_official	5:ac9f6c2c45e8	4126
mbed_official	5:ac9f6c2c45e8	4127	/*****************************************************************************/
mbed_official	5:ac9f6c2c45e8	4128	/* */
mbed_official	5:ac9f6c2c45e8	4129	/* Timers (TIM) */
mbed_official	5:ac9f6c2c45e8	4130	/* */
mbed_official	5:ac9f6c2c45e8	4131	/*****************************************************************************/
mbed_official	5:ac9f6c2c45e8	4132	/***************** Bit definition for TIM_CR1 register *****************/
mbed_official	5:ac9f6c2c45e8	4133	#define TIM_CR1_CEN ((uint32_t)0x00000001) /!<Counter enable /
mbed_official	5:ac9f6c2c45e8	4134	#define TIM_CR1_UDIS ((uint32_t)0x00000002) /!<Update disable /
mbed_official	5:ac9f6c2c45e8	4135	#define TIM_CR1_URS ((uint32_t)0x00000004) /!<Update request source /
mbed_official	5:ac9f6c2c45e8	4136	#define TIM_CR1_OPM ((uint32_t)0x00000008) /!<One pulse mode /
mbed_official	5:ac9f6c2c45e8	4137	#define TIM_CR1_DIR ((uint32_t)0x00000010) /!<Direction /
mbed_official	5:ac9f6c2c45e8	4138
mbed_official	5:ac9f6c2c45e8	4139	#define TIM_CR1_CMS ((uint32_t)0x00000060) /!<CMS[1:0] bits (Center-aligned mode selection) /
mbed_official	5:ac9f6c2c45e8	4140	#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	4141	#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	4142
mbed_official	5:ac9f6c2c45e8	4143	#define TIM_CR1_ARPE ((uint32_t)0x00000080) /!<Auto-reload preload enable /
mbed_official	5:ac9f6c2c45e8	4144
mbed_official	5:ac9f6c2c45e8	4145	#define TIM_CR1_CKD ((uint32_t)0x00000300) /!<CKD[1:0] bits (clock division) /
mbed_official	5:ac9f6c2c45e8	4146	#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	4147	#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	4148
mbed_official	5:ac9f6c2c45e8	4149	/***************** Bit definition for TIM_CR2 register *****************/
mbed_official	5:ac9f6c2c45e8	4150	#define TIM_CR2_CCPC ((uint32_t)0x00000001) /!<Capture/Compare Preloaded Control /
mbed_official	5:ac9f6c2c45e8	4151	#define TIM_CR2_CCUS ((uint32_t)0x00000004) /!<Capture/Compare Control Update Selection /
mbed_official	5:ac9f6c2c45e8	4152	#define TIM_CR2_CCDS ((uint32_t)0x00000008) /!<Capture/Compare DMA Selection /
mbed_official	5:ac9f6c2c45e8	4153
mbed_official	5:ac9f6c2c45e8	4154	#define TIM_CR2_MMS ((uint32_t)0x00000070) /!<MMS[2:0] bits (Master Mode Selection) /
mbed_official	5:ac9f6c2c45e8	4155	#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	4156	#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	4157	#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /!<Bit 2 /
mbed_official	5:ac9f6c2c45e8	4158
mbed_official	5:ac9f6c2c45e8	4159	#define TIM_CR2_TI1S ((uint32_t)0x00000080) /!<TI1 Selection /
mbed_official	5:ac9f6c2c45e8	4160	#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /!<Output Idle state 1 (OC1 output) /
mbed_official	5:ac9f6c2c45e8	4161	#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /!<Output Idle state 1 (OC1N output) /
mbed_official	5:ac9f6c2c45e8	4162	#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /!<Output Idle state 2 (OC2 output) /
mbed_official	5:ac9f6c2c45e8	4163	#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /!<Output Idle state 2 (OC2N output) /
mbed_official	5:ac9f6c2c45e8	4164	#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /!<Output Idle state 3 (OC3 output) /
mbed_official	5:ac9f6c2c45e8	4165	#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /!<Output Idle state 3 (OC3N output) /
mbed_official	5:ac9f6c2c45e8	4166	#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /!<Output Idle state 4 (OC4 output) /
mbed_official	5:ac9f6c2c45e8	4167
mbed_official	5:ac9f6c2c45e8	4168	/***************** Bit definition for TIM_SMCR register ****************/
mbed_official	5:ac9f6c2c45e8	4169	#define TIM_SMCR_SMS ((uint32_t)0x00000007) /!<SMS[2:0] bits (Slave mode selection) /
mbed_official	5:ac9f6c2c45e8	4170	#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	4171	#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	4172	#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /!<Bit 2 /
mbed_official	5:ac9f6c2c45e8	4173
mbed_official	5:ac9f6c2c45e8	4174	#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /!< OCREF clear selection /
mbed_official	5:ac9f6c2c45e8	4175
mbed_official	5:ac9f6c2c45e8	4176	#define TIM_SMCR_TS ((uint32_t)0x00000070) /!<TS[2:0] bits (Trigger selection) /
mbed_official	5:ac9f6c2c45e8	4177	#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	4178	#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	4179	#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /!<Bit 2 /
mbed_official	5:ac9f6c2c45e8	4180
mbed_official	5:ac9f6c2c45e8	4181	#define TIM_SMCR_MSM ((uint32_t)0x00000080) /!<Master/slave mode /
mbed_official	5:ac9f6c2c45e8	4182
mbed_official	5:ac9f6c2c45e8	4183	#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /!<ETF[3:0] bits (External trigger filter) /
mbed_official	5:ac9f6c2c45e8	4184	#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	4185	#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	4186	#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /!<Bit 2 /
mbed_official	5:ac9f6c2c45e8	4187	#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /!<Bit 3 /
mbed_official	5:ac9f6c2c45e8	4188
mbed_official	5:ac9f6c2c45e8	4189	#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /!<ETPS[1:0] bits (External trigger prescaler) /
mbed_official	5:ac9f6c2c45e8	4190	#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	4191	#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	4192
mbed_official	5:ac9f6c2c45e8	4193	#define TIM_SMCR_ECE ((uint32_t)0x00004000) /!<External clock enable /
mbed_official	5:ac9f6c2c45e8	4194	#define TIM_SMCR_ETP ((uint32_t)0x00008000) /!<External trigger polarity /
mbed_official	5:ac9f6c2c45e8	4195
mbed_official	5:ac9f6c2c45e8	4196	/***************** Bit definition for TIM_DIER register ****************/
mbed_official	5:ac9f6c2c45e8	4197	#define TIM_DIER_UIE ((uint32_t)0x00000001) /!<Update interrupt enable /
mbed_official	5:ac9f6c2c45e8	4198	#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt enable /
mbed_official	5:ac9f6c2c45e8	4199	#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt enable /
mbed_official	5:ac9f6c2c45e8	4200	#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt enable /
mbed_official	5:ac9f6c2c45e8	4201	#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt enable /
mbed_official	5:ac9f6c2c45e8	4202	#define TIM_DIER_COMIE ((uint32_t)0x00000020) /!<COM interrupt enable /
mbed_official	5:ac9f6c2c45e8	4203	#define TIM_DIER_TIE ((uint32_t)0x00000040) /!<Trigger interrupt enable /
mbed_official	5:ac9f6c2c45e8	4204	#define TIM_DIER_BIE ((uint32_t)0x00000080) /!<Break interrupt enable /
mbed_official	5:ac9f6c2c45e8	4205	#define TIM_DIER_UDE ((uint32_t)0x00000100) /!<Update DMA request enable /
mbed_official	5:ac9f6c2c45e8	4206	#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /!<Capture/Compare 1 DMA request enable /
mbed_official	5:ac9f6c2c45e8	4207	#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /!<Capture/Compare 2 DMA request enable /
mbed_official	5:ac9f6c2c45e8	4208	#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /!<Capture/Compare 3 DMA request enable /
mbed_official	5:ac9f6c2c45e8	4209	#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /!<Capture/Compare 4 DMA request enable /
mbed_official	5:ac9f6c2c45e8	4210	#define TIM_DIER_COMDE ((uint32_t)0x00002000) /!<COM DMA request enable /
mbed_official	5:ac9f6c2c45e8	4211	#define TIM_DIER_TDE ((uint32_t)0x00004000) /!<Trigger DMA request enable /
mbed_official	5:ac9f6c2c45e8	4212
mbed_official	5:ac9f6c2c45e8	4213	/****************** Bit definition for TIM_SR register *****************/
mbed_official	5:ac9f6c2c45e8	4214	#define TIM_SR_UIF ((uint32_t)0x00000001) /!<Update interrupt Flag /
mbed_official	5:ac9f6c2c45e8	4215	#define TIM_SR_CC1IF ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt Flag /
mbed_official	5:ac9f6c2c45e8	4216	#define TIM_SR_CC2IF ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt Flag /
mbed_official	5:ac9f6c2c45e8	4217	#define TIM_SR_CC3IF ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt Flag /
mbed_official	5:ac9f6c2c45e8	4218	#define TIM_SR_CC4IF ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt Flag /
mbed_official	5:ac9f6c2c45e8	4219	#define TIM_SR_COMIF ((uint32_t)0x00000020) /!<COM interrupt Flag /
mbed_official	5:ac9f6c2c45e8	4220	#define TIM_SR_TIF ((uint32_t)0x00000040) /!<Trigger interrupt Flag /
mbed_official	5:ac9f6c2c45e8	4221	#define TIM_SR_BIF ((uint32_t)0x00000080) /!<Break interrupt Flag /
mbed_official	5:ac9f6c2c45e8	4222	#define TIM_SR_CC1OF ((uint32_t)0x00000200) /!<Capture/Compare 1 Overcapture Flag /
mbed_official	5:ac9f6c2c45e8	4223	#define TIM_SR_CC2OF ((uint32_t)0x00000400) /!<Capture/Compare 2 Overcapture Flag /
mbed_official	5:ac9f6c2c45e8	4224	#define TIM_SR_CC3OF ((uint32_t)0x00000800) /!<Capture/Compare 3 Overcapture Flag /
mbed_official	5:ac9f6c2c45e8	4225	#define TIM_SR_CC4OF ((uint32_t)0x00001000) /!<Capture/Compare 4 Overcapture Flag /
mbed_official	5:ac9f6c2c45e8	4226
mbed_official	5:ac9f6c2c45e8	4227	/***************** Bit definition for TIM_EGR register *****************/
mbed_official	5:ac9f6c2c45e8	4228	#define TIM_EGR_UG ((uint32_t)0x00000001) /!<Update Generation /
mbed_official	5:ac9f6c2c45e8	4229	#define TIM_EGR_CC1G ((uint32_t)0x00000002) /!<Capture/Compare 1 Generation /
mbed_official	5:ac9f6c2c45e8	4230	#define TIM_EGR_CC2G ((uint32_t)0x00000004) /!<Capture/Compare 2 Generation /
mbed_official	5:ac9f6c2c45e8	4231	#define TIM_EGR_CC3G ((uint32_t)0x00000008) /!<Capture/Compare 3 Generation /
mbed_official	5:ac9f6c2c45e8	4232	#define TIM_EGR_CC4G ((uint32_t)0x00000010) /!<Capture/Compare 4 Generation /
mbed_official	5:ac9f6c2c45e8	4233	#define TIM_EGR_COMG ((uint32_t)0x00000020) /!<Capture/Compare Control Update Generation /
mbed_official	5:ac9f6c2c45e8	4234	#define TIM_EGR_TG ((uint32_t)0x00000040) /!<Trigger Generation /
mbed_official	5:ac9f6c2c45e8	4235	#define TIM_EGR_BG ((uint32_t)0x00000080) /!<Break Generation /
mbed_official	5:ac9f6c2c45e8	4236
mbed_official	5:ac9f6c2c45e8	4237	/**************** Bit definition for TIM_CCMR1 register ****************/
mbed_official	5:ac9f6c2c45e8	4238	#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
mbed_official	5:ac9f6c2c45e8	4239	#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	4240	#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	4241
mbed_official	5:ac9f6c2c45e8	4242	#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /!<Output Compare 1 Fast enable /
mbed_official	5:ac9f6c2c45e8	4243	#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /!<Output Compare 1 Preload enable /
mbed_official	5:ac9f6c2c45e8	4244
mbed_official	5:ac9f6c2c45e8	4245	#define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /!<OC1M[2:0] bits (Output Compare 1 Mode) /
mbed_official	5:ac9f6c2c45e8	4246	#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	4247	#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	4248	#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /!<Bit 2 /
mbed_official	5:ac9f6c2c45e8	4249
mbed_official	5:ac9f6c2c45e8	4250	#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /!<Output Compare 1Clear Enable /
mbed_official	5:ac9f6c2c45e8	4251
mbed_official	5:ac9f6c2c45e8	4252	#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
mbed_official	5:ac9f6c2c45e8	4253	#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	4254	#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	4255
mbed_official	5:ac9f6c2c45e8	4256	#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /!<Output Compare 2 Fast enable /
mbed_official	5:ac9f6c2c45e8	4257	#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /!<Output Compare 2 Preload enable /
mbed_official	5:ac9f6c2c45e8	4258
mbed_official	5:ac9f6c2c45e8	4259	#define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /!<OC2M[2:0] bits (Output Compare 2 Mode) /
mbed_official	5:ac9f6c2c45e8	4260	#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	4261	#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	4262	#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /!<Bit 2 /
mbed_official	5:ac9f6c2c45e8	4263
mbed_official	5:ac9f6c2c45e8	4264	#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /!<Output Compare 2 Clear Enable /
mbed_official	5:ac9f6c2c45e8	4265
mbed_official	5:ac9f6c2c45e8	4266	/---------------------------------------------------------------------------/
mbed_official	5:ac9f6c2c45e8	4267
mbed_official	5:ac9f6c2c45e8	4268	#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
mbed_official	5:ac9f6c2c45e8	4269	#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	4270	#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	4271
mbed_official	5:ac9f6c2c45e8	4272	#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /!<IC1F[3:0] bits (Input Capture 1 Filter) /
mbed_official	5:ac9f6c2c45e8	4273	#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	4274	#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	4275	#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /!<Bit 2 /
mbed_official	5:ac9f6c2c45e8	4276	#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /!<Bit 3 /
mbed_official	5:ac9f6c2c45e8	4277
mbed_official	5:ac9f6c2c45e8	4278	#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
mbed_official	5:ac9f6c2c45e8	4279	#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	4280	#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	4281
mbed_official	5:ac9f6c2c45e8	4282	#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /!<IC2F[3:0] bits (Input Capture 2 Filter) /
mbed_official	5:ac9f6c2c45e8	4283	#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	4284	#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	4285	#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /!<Bit 2 /
mbed_official	5:ac9f6c2c45e8	4286	#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /!<Bit 3 /
mbed_official	5:ac9f6c2c45e8	4287
mbed_official	5:ac9f6c2c45e8	4288	/**************** Bit definition for TIM_CCMR2 register ****************/
mbed_official	5:ac9f6c2c45e8	4289	#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
mbed_official	5:ac9f6c2c45e8	4290	#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	4291	#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	4292
mbed_official	5:ac9f6c2c45e8	4293	#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /!<Output Compare 3 Fast enable /
mbed_official	5:ac9f6c2c45e8	4294	#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /!<Output Compare 3 Preload enable /
mbed_official	5:ac9f6c2c45e8	4295
mbed_official	5:ac9f6c2c45e8	4296	#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /!<OC3M[2:0] bits (Output Compare 3 Mode) /
mbed_official	5:ac9f6c2c45e8	4297	#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	4298	#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	4299	#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /!<Bit 2 /
mbed_official	5:ac9f6c2c45e8	4300
mbed_official	5:ac9f6c2c45e8	4301	#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /!<Output Compare 3 Clear Enable /
mbed_official	5:ac9f6c2c45e8	4302
mbed_official	5:ac9f6c2c45e8	4303	#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
mbed_official	5:ac9f6c2c45e8	4304	#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	4305	#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	4306
mbed_official	5:ac9f6c2c45e8	4307	#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /!<Output Compare 4 Fast enable /
mbed_official	5:ac9f6c2c45e8	4308	#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /!<Output Compare 4 Preload enable /
mbed_official	5:ac9f6c2c45e8	4309
mbed_official	5:ac9f6c2c45e8	4310	#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /!<OC4M[2:0] bits (Output Compare 4 Mode) /
mbed_official	5:ac9f6c2c45e8	4311	#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	4312	#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	4313	#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /!<Bit 2 /
mbed_official	5:ac9f6c2c45e8	4314
mbed_official	5:ac9f6c2c45e8	4315	#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /!<Output Compare 4 Clear Enable /
mbed_official	5:ac9f6c2c45e8	4316
mbed_official	5:ac9f6c2c45e8	4317	/---------------------------------------------------------------------------/
mbed_official	5:ac9f6c2c45e8	4318
mbed_official	5:ac9f6c2c45e8	4319	#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
mbed_official	5:ac9f6c2c45e8	4320	#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	4321	#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	4322
mbed_official	5:ac9f6c2c45e8	4323	#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /!<IC3F[3:0] bits (Input Capture 3 Filter) /
mbed_official	5:ac9f6c2c45e8	4324	#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	4325	#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	4326	#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /!<Bit 2 /
mbed_official	5:ac9f6c2c45e8	4327	#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /!<Bit 3 /
mbed_official	5:ac9f6c2c45e8	4328
mbed_official	5:ac9f6c2c45e8	4329	#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
mbed_official	5:ac9f6c2c45e8	4330	#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	4331	#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	4332
mbed_official	5:ac9f6c2c45e8	4333	#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /!<IC4F[3:0] bits (Input Capture 4 Filter) /
mbed_official	5:ac9f6c2c45e8	4334	#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	4335	#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	4336	#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /!<Bit 2 /
mbed_official	5:ac9f6c2c45e8	4337	#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /!<Bit 3 /
mbed_official	5:ac9f6c2c45e8	4338
mbed_official	5:ac9f6c2c45e8	4339	/***************** Bit definition for TIM_CCER register ****************/
mbed_official	5:ac9f6c2c45e8	4340	#define TIM_CCER_CC1E ((uint32_t)0x00000001) /!<Capture/Compare 1 output enable /
mbed_official	5:ac9f6c2c45e8	4341	#define TIM_CCER_CC1P ((uint32_t)0x00000002) /!<Capture/Compare 1 output Polarity /
mbed_official	5:ac9f6c2c45e8	4342	#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /!<Capture/Compare 1 Complementary output enable /
mbed_official	5:ac9f6c2c45e8	4343	#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /!<Capture/Compare 1 Complementary output Polarity /
mbed_official	5:ac9f6c2c45e8	4344	#define TIM_CCER_CC2E ((uint32_t)0x00000010) /!<Capture/Compare 2 output enable /
mbed_official	5:ac9f6c2c45e8	4345	#define TIM_CCER_CC2P ((uint32_t)0x00000020) /!<Capture/Compare 2 output Polarity /
mbed_official	5:ac9f6c2c45e8	4346	#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /!<Capture/Compare 2 Complementary output enable /
mbed_official	5:ac9f6c2c45e8	4347	#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /!<Capture/Compare 2 Complementary output Polarity /
mbed_official	5:ac9f6c2c45e8	4348	#define TIM_CCER_CC3E ((uint32_t)0x00000100) /!<Capture/Compare 3 output enable /
mbed_official	5:ac9f6c2c45e8	4349	#define TIM_CCER_CC3P ((uint32_t)0x00000200) /!<Capture/Compare 3 output Polarity /
mbed_official	5:ac9f6c2c45e8	4350	#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /!<Capture/Compare 3 Complementary output enable /
mbed_official	5:ac9f6c2c45e8	4351	#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /!<Capture/Compare 3 Complementary output Polarity /
mbed_official	5:ac9f6c2c45e8	4352	#define TIM_CCER_CC4E ((uint32_t)0x00001000) /!<Capture/Compare 4 output enable /
mbed_official	5:ac9f6c2c45e8	4353	#define TIM_CCER_CC4P ((uint32_t)0x00002000) /!<Capture/Compare 4 output Polarity /
mbed_official	5:ac9f6c2c45e8	4354	#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /!<Capture/Compare 4 Complementary output Polarity /
mbed_official	5:ac9f6c2c45e8	4355
mbed_official	5:ac9f6c2c45e8	4356	/***************** Bit definition for TIM_CNT register *****************/
mbed_official	5:ac9f6c2c45e8	4357	#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /!<Counter Value /
mbed_official	5:ac9f6c2c45e8	4358
mbed_official	5:ac9f6c2c45e8	4359	/***************** Bit definition for TIM_PSC register *****************/
mbed_official	5:ac9f6c2c45e8	4360	#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /!<Prescaler Value /
mbed_official	5:ac9f6c2c45e8	4361
mbed_official	5:ac9f6c2c45e8	4362	/***************** Bit definition for TIM_ARR register *****************/
mbed_official	5:ac9f6c2c45e8	4363	#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /!<actual auto-reload Value /
mbed_official	5:ac9f6c2c45e8	4364
mbed_official	5:ac9f6c2c45e8	4365	/***************** Bit definition for TIM_RCR register *****************/
mbed_official	5:ac9f6c2c45e8	4366	#define TIM_RCR_REP ((uint32_t)0x000000FF) /!<Repetition Counter Value /
mbed_official	5:ac9f6c2c45e8	4367
mbed_official	5:ac9f6c2c45e8	4368	/***************** Bit definition for TIM_CCR1 register ****************/
mbed_official	5:ac9f6c2c45e8	4369	#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /!<Capture/Compare 1 Value /
mbed_official	5:ac9f6c2c45e8	4370
mbed_official	5:ac9f6c2c45e8	4371	/***************** Bit definition for TIM_CCR2 register ****************/
mbed_official	5:ac9f6c2c45e8	4372	#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /!<Capture/Compare 2 Value /
mbed_official	5:ac9f6c2c45e8	4373
mbed_official	5:ac9f6c2c45e8	4374	/***************** Bit definition for TIM_CCR3 register ****************/
mbed_official	5:ac9f6c2c45e8	4375	#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /!<Capture/Compare 3 Value /
mbed_official	5:ac9f6c2c45e8	4376
mbed_official	5:ac9f6c2c45e8	4377	/***************** Bit definition for TIM_CCR4 register ****************/
mbed_official	5:ac9f6c2c45e8	4378	#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /!<Capture/Compare 4 Value /
mbed_official	5:ac9f6c2c45e8	4379
mbed_official	5:ac9f6c2c45e8	4380	/***************** Bit definition for TIM_BDTR register ****************/
mbed_official	5:ac9f6c2c45e8	4381	#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /!<DTG[0:7] bits (Dead-Time Generator set-up) /
mbed_official	5:ac9f6c2c45e8	4382	#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	4383	#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	4384	#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /!<Bit 2 /
mbed_official	5:ac9f6c2c45e8	4385	#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /!<Bit 3 /
mbed_official	5:ac9f6c2c45e8	4386	#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /!<Bit 4 /
mbed_official	5:ac9f6c2c45e8	4387	#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /!<Bit 5 /
mbed_official	5:ac9f6c2c45e8	4388	#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /!<Bit 6 /
mbed_official	5:ac9f6c2c45e8	4389	#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /!<Bit 7 /
mbed_official	5:ac9f6c2c45e8	4390
mbed_official	5:ac9f6c2c45e8	4391	#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /!<LOCK[1:0] bits (Lock Configuration) /
mbed_official	5:ac9f6c2c45e8	4392	#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	4393	#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	4394
mbed_official	5:ac9f6c2c45e8	4395	#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /!<Off-State Selection for Idle mode /
mbed_official	5:ac9f6c2c45e8	4396	#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /!<Off-State Selection for Run mode /
mbed_official	5:ac9f6c2c45e8	4397	#define TIM_BDTR_BKE ((uint32_t)0x00001000) /!<Break enable /
mbed_official	5:ac9f6c2c45e8	4398	#define TIM_BDTR_BKP ((uint32_t)0x00002000) /!<Break Polarity /
mbed_official	5:ac9f6c2c45e8	4399	#define TIM_BDTR_AOE ((uint32_t)0x00004000) /!<Automatic Output enable /
mbed_official	5:ac9f6c2c45e8	4400	#define TIM_BDTR_MOE ((uint32_t)0x00008000) /!<Main Output enable /
mbed_official	5:ac9f6c2c45e8	4401
mbed_official	5:ac9f6c2c45e8	4402	/***************** Bit definition for TIM_DCR register *****************/
mbed_official	5:ac9f6c2c45e8	4403	#define TIM_DCR_DBA ((uint32_t)0x0000001F) /!<DBA[4:0] bits (DMA Base Address) /
mbed_official	5:ac9f6c2c45e8	4404	#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	4405	#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	4406	#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /!<Bit 2 /
mbed_official	5:ac9f6c2c45e8	4407	#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /!<Bit 3 /
mbed_official	5:ac9f6c2c45e8	4408	#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /!<Bit 4 /
mbed_official	5:ac9f6c2c45e8	4409
mbed_official	5:ac9f6c2c45e8	4410	#define TIM_DCR_DBL ((uint32_t)0x00001F00) /!<DBL[4:0] bits (DMA Burst Length) /
mbed_official	5:ac9f6c2c45e8	4411	#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	4412	#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	4413	#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /!<Bit 2 /
mbed_official	5:ac9f6c2c45e8	4414	#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /!<Bit 3 /
mbed_official	5:ac9f6c2c45e8	4415	#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /!<Bit 4 /
mbed_official	5:ac9f6c2c45e8	4416
mbed_official	5:ac9f6c2c45e8	4417	/***************** Bit definition for TIM_DMAR register ****************/
mbed_official	5:ac9f6c2c45e8	4418	#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /!<DMA register for burst accesses /
mbed_official	5:ac9f6c2c45e8	4419
mbed_official	5:ac9f6c2c45e8	4420	/***************** Bit definition for TIM14_OR register ******************/
mbed_official	5:ac9f6c2c45e8	4421	#define TIM14_OR_TI1_RMP ((uint32_t)0x00000003) /!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) /
mbed_official	5:ac9f6c2c45e8	4422	#define TIM14_OR_TI1_RMP_0 ((uint32_t)0x00000001) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	4423	#define TIM14_OR_TI1_RMP_1 ((uint32_t)0x00000002) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	4424
mbed_official	5:ac9f6c2c45e8	4425	/******************************************************************************/
mbed_official	5:ac9f6c2c45e8	4426	/* */
mbed_official	5:ac9f6c2c45e8	4427	/* Touch Sensing Controller (TSC) */
mbed_official	5:ac9f6c2c45e8	4428	/* */
mbed_official	5:ac9f6c2c45e8	4429	/******************************************************************************/
mbed_official	5:ac9f6c2c45e8	4430	/***************** Bit definition for TSC_CR register *******************/
mbed_official	5:ac9f6c2c45e8	4431	#define TSC_CR_TSCE ((uint32_t)0x00000001) /!<Touch sensing controller enable /
mbed_official	5:ac9f6c2c45e8	4432	#define TSC_CR_START ((uint32_t)0x00000002) /!<Start acquisition /
mbed_official	5:ac9f6c2c45e8	4433	#define TSC_CR_AM ((uint32_t)0x00000004) /!<Acquisition mode /
mbed_official	5:ac9f6c2c45e8	4434	#define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /!<Synchronization pin polarity /
mbed_official	5:ac9f6c2c45e8	4435	#define TSC_CR_IODEF ((uint32_t)0x00000010) /!<IO default mode /
mbed_official	5:ac9f6c2c45e8	4436
mbed_official	5:ac9f6c2c45e8	4437	#define TSC_CR_MCV ((uint32_t)0x000000E0) /!<MCV[2:0] bits (Max Count Value) /
mbed_official	5:ac9f6c2c45e8	4438	#define TSC_CR_MCV_0 ((uint32_t)0x00000020) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	4439	#define TSC_CR_MCV_1 ((uint32_t)0x00000040) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	4440	#define TSC_CR_MCV_2 ((uint32_t)0x00000080) /!<Bit 2 /
mbed_official	5:ac9f6c2c45e8	4441
mbed_official	5:ac9f6c2c45e8	4442	#define TSC_CR_PGPSC ((uint32_t)0x00007000) /!<PGPSC[2:0] bits (Pulse Generator Prescaler) /
mbed_official	5:ac9f6c2c45e8	4443	#define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	4444	#define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	4445	#define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /!<Bit 2 /
mbed_official	5:ac9f6c2c45e8	4446
mbed_official	5:ac9f6c2c45e8	4447	#define TSC_CR_SSPSC ((uint32_t)0x00008000) /!<Spread Spectrum Prescaler /
mbed_official	5:ac9f6c2c45e8	4448	#define TSC_CR_SSE ((uint32_t)0x00010000) /!<Spread Spectrum Enable /
mbed_official	5:ac9f6c2c45e8	4449
mbed_official	5:ac9f6c2c45e8	4450	#define TSC_CR_SSD ((uint32_t)0x00FE0000) /!<SSD[6:0] bits (Spread Spectrum Deviation) /
mbed_official	5:ac9f6c2c45e8	4451	#define TSC_CR_SSD_0 ((uint32_t)0x00020000) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	4452	#define TSC_CR_SSD_1 ((uint32_t)0x00040000) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	4453	#define TSC_CR_SSD_2 ((uint32_t)0x00080000) /!<Bit 2 /
mbed_official	5:ac9f6c2c45e8	4454	#define TSC_CR_SSD_3 ((uint32_t)0x00100000) /!<Bit 3 /
mbed_official	5:ac9f6c2c45e8	4455	#define TSC_CR_SSD_4 ((uint32_t)0x00200000) /!<Bit 4 /
mbed_official	5:ac9f6c2c45e8	4456	#define TSC_CR_SSD_5 ((uint32_t)0x00400000) /!<Bit 5 /
mbed_official	5:ac9f6c2c45e8	4457	#define TSC_CR_SSD_6 ((uint32_t)0x00800000) /!<Bit 6 /
mbed_official	5:ac9f6c2c45e8	4458
mbed_official	5:ac9f6c2c45e8	4459	#define TSC_CR_CTPL ((uint32_t)0x0F000000) /!<CTPL[3:0] bits (Charge Transfer pulse low) /
mbed_official	5:ac9f6c2c45e8	4460	#define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	4461	#define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	4462	#define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /!<Bit 2 /
mbed_official	5:ac9f6c2c45e8	4463	#define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /!<Bit 3 /
mbed_official	5:ac9f6c2c45e8	4464
mbed_official	5:ac9f6c2c45e8	4465	#define TSC_CR_CTPH ((uint32_t)0xF0000000) /!<CTPH[3:0] bits (Charge Transfer pulse high) /
mbed_official	5:ac9f6c2c45e8	4466	#define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	4467	#define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	4468	#define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /!<Bit 2 /
mbed_official	5:ac9f6c2c45e8	4469	#define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /!<Bit 3 /
mbed_official	5:ac9f6c2c45e8	4470
mbed_official	5:ac9f6c2c45e8	4471	/***************** Bit definition for TSC_IER register ******************/
mbed_official	5:ac9f6c2c45e8	4472	#define TSC_IER_EOAIE ((uint32_t)0x00000001) /!<End of acquisition interrupt enable /
mbed_official	5:ac9f6c2c45e8	4473	#define TSC_IER_MCEIE ((uint32_t)0x00000002) /!<Max count error interrupt enable /
mbed_official	5:ac9f6c2c45e8	4474
mbed_official	5:ac9f6c2c45e8	4475	/***************** Bit definition for TSC_ICR register ******************/
mbed_official	5:ac9f6c2c45e8	4476	#define TSC_ICR_EOAIC ((uint32_t)0x00000001) /!<End of acquisition interrupt clear /
mbed_official	5:ac9f6c2c45e8	4477	#define TSC_ICR_MCEIC ((uint32_t)0x00000002) /!<Max count error interrupt clear /
mbed_official	5:ac9f6c2c45e8	4478
mbed_official	5:ac9f6c2c45e8	4479	/***************** Bit definition for TSC_ISR register ******************/
mbed_official	5:ac9f6c2c45e8	4480	#define TSC_ISR_EOAF ((uint32_t)0x00000001) /!<End of acquisition flag /
mbed_official	5:ac9f6c2c45e8	4481	#define TSC_ISR_MCEF ((uint32_t)0x00000002) /!<Max count error flag /
mbed_official	5:ac9f6c2c45e8	4482
mbed_official	5:ac9f6c2c45e8	4483	/***************** Bit definition for TSC_IOHCR register ****************/
mbed_official	5:ac9f6c2c45e8	4484	#define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /!<GROUP1_IO1 schmitt trigger hysteresis mode /
mbed_official	5:ac9f6c2c45e8	4485	#define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /!<GROUP1_IO2 schmitt trigger hysteresis mode /
mbed_official	5:ac9f6c2c45e8	4486	#define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /!<GROUP1_IO3 schmitt trigger hysteresis mode /
mbed_official	5:ac9f6c2c45e8	4487	#define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /!<GROUP1_IO4 schmitt trigger hysteresis mode /
mbed_official	5:ac9f6c2c45e8	4488	#define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /!<GROUP2_IO1 schmitt trigger hysteresis mode /
mbed_official	5:ac9f6c2c45e8	4489	#define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /!<GROUP2_IO2 schmitt trigger hysteresis mode /
mbed_official	5:ac9f6c2c45e8	4490	#define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /!<GROUP2_IO3 schmitt trigger hysteresis mode /
mbed_official	5:ac9f6c2c45e8	4491	#define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /!<GROUP2_IO4 schmitt trigger hysteresis mode /
mbed_official	5:ac9f6c2c45e8	4492	#define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /!<GROUP3_IO1 schmitt trigger hysteresis mode /
mbed_official	5:ac9f6c2c45e8	4493	#define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /!<GROUP3_IO2 schmitt trigger hysteresis mode /
mbed_official	5:ac9f6c2c45e8	4494	#define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /!<GROUP3_IO3 schmitt trigger hysteresis mode /
mbed_official	5:ac9f6c2c45e8	4495	#define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /!<GROUP3_IO4 schmitt trigger hysteresis mode /
mbed_official	5:ac9f6c2c45e8	4496	#define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /!<GROUP4_IO1 schmitt trigger hysteresis mode /
mbed_official	5:ac9f6c2c45e8	4497	#define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /!<GROUP4_IO2 schmitt trigger hysteresis mode /
mbed_official	5:ac9f6c2c45e8	4498	#define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /!<GROUP4_IO3 schmitt trigger hysteresis mode /
mbed_official	5:ac9f6c2c45e8	4499	#define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /!<GROUP4_IO4 schmitt trigger hysteresis mode /
mbed_official	5:ac9f6c2c45e8	4500	#define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /!<GROUP5_IO1 schmitt trigger hysteresis mode /
mbed_official	5:ac9f6c2c45e8	4501	#define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /!<GROUP5_IO2 schmitt trigger hysteresis mode /
mbed_official	5:ac9f6c2c45e8	4502	#define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /!<GROUP5_IO3 schmitt trigger hysteresis mode /
mbed_official	5:ac9f6c2c45e8	4503	#define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /!<GROUP5_IO4 schmitt trigger hysteresis mode /
mbed_official	5:ac9f6c2c45e8	4504	#define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /!<GROUP6_IO1 schmitt trigger hysteresis mode /
mbed_official	5:ac9f6c2c45e8	4505	#define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /!<GROUP6_IO2 schmitt trigger hysteresis mode /
mbed_official	5:ac9f6c2c45e8	4506	#define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /!<GROUP6_IO3 schmitt trigger hysteresis mode /
mbed_official	5:ac9f6c2c45e8	4507	#define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /!<GROUP6_IO4 schmitt trigger hysteresis mode /
mbed_official	5:ac9f6c2c45e8	4508	#define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /!<GROUP7_IO1 schmitt trigger hysteresis mode /
mbed_official	5:ac9f6c2c45e8	4509	#define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /!<GROUP7_IO2 schmitt trigger hysteresis mode /
mbed_official	5:ac9f6c2c45e8	4510	#define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /!<GROUP7_IO3 schmitt trigger hysteresis mode /
mbed_official	5:ac9f6c2c45e8	4511	#define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /!<GROUP7_IO4 schmitt trigger hysteresis mode /
mbed_official	5:ac9f6c2c45e8	4512	#define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /!<GROUP8_IO1 schmitt trigger hysteresis mode /
mbed_official	5:ac9f6c2c45e8	4513	#define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /!<GROUP8_IO2 schmitt trigger hysteresis mode /
mbed_official	5:ac9f6c2c45e8	4514	#define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /!<GROUP8_IO3 schmitt trigger hysteresis mode /
mbed_official	5:ac9f6c2c45e8	4515	#define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /!<GROUP8_IO4 schmitt trigger hysteresis mode /
mbed_official	5:ac9f6c2c45e8	4516
mbed_official	5:ac9f6c2c45e8	4517	/***************** Bit definition for TSC_IOASCR register ***************/
mbed_official	5:ac9f6c2c45e8	4518	#define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /!<GROUP1_IO1 analog switch enable /
mbed_official	5:ac9f6c2c45e8	4519	#define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /!<GROUP1_IO2 analog switch enable /
mbed_official	5:ac9f6c2c45e8	4520	#define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /!<GROUP1_IO3 analog switch enable /
mbed_official	5:ac9f6c2c45e8	4521	#define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /!<GROUP1_IO4 analog switch enable /
mbed_official	5:ac9f6c2c45e8	4522	#define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /!<GROUP2_IO1 analog switch enable /
mbed_official	5:ac9f6c2c45e8	4523	#define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /!<GROUP2_IO2 analog switch enable /
mbed_official	5:ac9f6c2c45e8	4524	#define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /!<GROUP2_IO3 analog switch enable /
mbed_official	5:ac9f6c2c45e8	4525	#define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /!<GROUP2_IO4 analog switch enable /
mbed_official	5:ac9f6c2c45e8	4526	#define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /!<GROUP3_IO1 analog switch enable /
mbed_official	5:ac9f6c2c45e8	4527	#define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /!<GROUP3_IO2 analog switch enable /
mbed_official	5:ac9f6c2c45e8	4528	#define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /!<GROUP3_IO3 analog switch enable /
mbed_official	5:ac9f6c2c45e8	4529	#define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /!<GROUP3_IO4 analog switch enable /
mbed_official	5:ac9f6c2c45e8	4530	#define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /!<GROUP4_IO1 analog switch enable /
mbed_official	5:ac9f6c2c45e8	4531	#define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /!<GROUP4_IO2 analog switch enable /
mbed_official	5:ac9f6c2c45e8	4532	#define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /!<GROUP4_IO3 analog switch enable /
mbed_official	5:ac9f6c2c45e8	4533	#define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /!<GROUP4_IO4 analog switch enable /
mbed_official	5:ac9f6c2c45e8	4534	#define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /!<GROUP5_IO1 analog switch enable /
mbed_official	5:ac9f6c2c45e8	4535	#define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /!<GROUP5_IO2 analog switch enable /
mbed_official	5:ac9f6c2c45e8	4536	#define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /!<GROUP5_IO3 analog switch enable /
mbed_official	5:ac9f6c2c45e8	4537	#define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /!<GROUP5_IO4 analog switch enable /
mbed_official	5:ac9f6c2c45e8	4538	#define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /!<GROUP6_IO1 analog switch enable /
mbed_official	5:ac9f6c2c45e8	4539	#define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /!<GROUP6_IO2 analog switch enable /
mbed_official	5:ac9f6c2c45e8	4540	#define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /!<GROUP6_IO3 analog switch enable /
mbed_official	5:ac9f6c2c45e8	4541	#define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /!<GROUP6_IO4 analog switch enable /
mbed_official	5:ac9f6c2c45e8	4542	#define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /!<GROUP7_IO1 analog switch enable /
mbed_official	5:ac9f6c2c45e8	4543	#define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /!<GROUP7_IO2 analog switch enable /
mbed_official	5:ac9f6c2c45e8	4544	#define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /!<GROUP7_IO3 analog switch enable /
mbed_official	5:ac9f6c2c45e8	4545	#define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /!<GROUP7_IO4 analog switch enable /
mbed_official	5:ac9f6c2c45e8	4546	#define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /!<GROUP8_IO1 analog switch enable /
mbed_official	5:ac9f6c2c45e8	4547	#define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /!<GROUP8_IO2 analog switch enable /
mbed_official	5:ac9f6c2c45e8	4548	#define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /!<GROUP8_IO3 analog switch enable /
mbed_official	5:ac9f6c2c45e8	4549	#define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /!<GROUP8_IO4 analog switch enable /
mbed_official	5:ac9f6c2c45e8	4550
mbed_official	5:ac9f6c2c45e8	4551	/***************** Bit definition for TSC_IOSCR register ****************/
mbed_official	5:ac9f6c2c45e8	4552	#define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /!<GROUP1_IO1 sampling mode /
mbed_official	5:ac9f6c2c45e8	4553	#define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /!<GROUP1_IO2 sampling mode /
mbed_official	5:ac9f6c2c45e8	4554	#define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /!<GROUP1_IO3 sampling mode /
mbed_official	5:ac9f6c2c45e8	4555	#define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /!<GROUP1_IO4 sampling mode /
mbed_official	5:ac9f6c2c45e8	4556	#define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /!<GROUP2_IO1 sampling mode /
mbed_official	5:ac9f6c2c45e8	4557	#define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /!<GROUP2_IO2 sampling mode /
mbed_official	5:ac9f6c2c45e8	4558	#define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /!<GROUP2_IO3 sampling mode /
mbed_official	5:ac9f6c2c45e8	4559	#define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /!<GROUP2_IO4 sampling mode /
mbed_official	5:ac9f6c2c45e8	4560	#define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /!<GROUP3_IO1 sampling mode /
mbed_official	5:ac9f6c2c45e8	4561	#define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /!<GROUP3_IO2 sampling mode /
mbed_official	5:ac9f6c2c45e8	4562	#define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /!<GROUP3_IO3 sampling mode /
mbed_official	5:ac9f6c2c45e8	4563	#define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /!<GROUP3_IO4 sampling mode /
mbed_official	5:ac9f6c2c45e8	4564	#define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /!<GROUP4_IO1 sampling mode /
mbed_official	5:ac9f6c2c45e8	4565	#define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /!<GROUP4_IO2 sampling mode /
mbed_official	5:ac9f6c2c45e8	4566	#define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /!<GROUP4_IO3 sampling mode /
mbed_official	5:ac9f6c2c45e8	4567	#define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /!<GROUP4_IO4 sampling mode /
mbed_official	5:ac9f6c2c45e8	4568	#define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /!<GROUP5_IO1 sampling mode /
mbed_official	5:ac9f6c2c45e8	4569	#define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /!<GROUP5_IO2 sampling mode /
mbed_official	5:ac9f6c2c45e8	4570	#define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /!<GROUP5_IO3 sampling mode /
mbed_official	5:ac9f6c2c45e8	4571	#define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /!<GROUP5_IO4 sampling mode /
mbed_official	5:ac9f6c2c45e8	4572	#define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /!<GROUP6_IO1 sampling mode /
mbed_official	5:ac9f6c2c45e8	4573	#define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /!<GROUP6_IO2 sampling mode /
mbed_official	5:ac9f6c2c45e8	4574	#define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /!<GROUP6_IO3 sampling mode /
mbed_official	5:ac9f6c2c45e8	4575	#define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /!<GROUP6_IO4 sampling mode /
mbed_official	5:ac9f6c2c45e8	4576	#define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /!<GROUP7_IO1 sampling mode /
mbed_official	5:ac9f6c2c45e8	4577	#define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /!<GROUP7_IO2 sampling mode /
mbed_official	5:ac9f6c2c45e8	4578	#define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /!<GROUP7_IO3 sampling mode /
mbed_official	5:ac9f6c2c45e8	4579	#define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /!<GROUP7_IO4 sampling mode /
mbed_official	5:ac9f6c2c45e8	4580	#define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /!<GROUP8_IO1 sampling mode /
mbed_official	5:ac9f6c2c45e8	4581	#define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /!<GROUP8_IO2 sampling mode /
mbed_official	5:ac9f6c2c45e8	4582	#define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /!<GROUP8_IO3 sampling mode /
mbed_official	5:ac9f6c2c45e8	4583	#define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /!<GROUP8_IO4 sampling mode /
mbed_official	5:ac9f6c2c45e8	4584
mbed_official	5:ac9f6c2c45e8	4585	/***************** Bit definition for TSC_IOCCR register ****************/
mbed_official	5:ac9f6c2c45e8	4586	#define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /!<GROUP1_IO1 channel mode /
mbed_official	5:ac9f6c2c45e8	4587	#define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /!<GROUP1_IO2 channel mode /
mbed_official	5:ac9f6c2c45e8	4588	#define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /!<GROUP1_IO3 channel mode /
mbed_official	5:ac9f6c2c45e8	4589	#define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /!<GROUP1_IO4 channel mode /
mbed_official	5:ac9f6c2c45e8	4590	#define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /!<GROUP2_IO1 channel mode /
mbed_official	5:ac9f6c2c45e8	4591	#define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /!<GROUP2_IO2 channel mode /
mbed_official	5:ac9f6c2c45e8	4592	#define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /!<GROUP2_IO3 channel mode /
mbed_official	5:ac9f6c2c45e8	4593	#define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /!<GROUP2_IO4 channel mode /
mbed_official	5:ac9f6c2c45e8	4594	#define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /!<GROUP3_IO1 channel mode /
mbed_official	5:ac9f6c2c45e8	4595	#define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /!<GROUP3_IO2 channel mode /
mbed_official	5:ac9f6c2c45e8	4596	#define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /!<GROUP3_IO3 channel mode /
mbed_official	5:ac9f6c2c45e8	4597	#define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /!<GROUP3_IO4 channel mode /
mbed_official	5:ac9f6c2c45e8	4598	#define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /!<GROUP4_IO1 channel mode /
mbed_official	5:ac9f6c2c45e8	4599	#define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /!<GROUP4_IO2 channel mode /
mbed_official	5:ac9f6c2c45e8	4600	#define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /!<GROUP4_IO3 channel mode /
mbed_official	5:ac9f6c2c45e8	4601	#define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /!<GROUP4_IO4 channel mode /
mbed_official	5:ac9f6c2c45e8	4602	#define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /!<GROUP5_IO1 channel mode /
mbed_official	5:ac9f6c2c45e8	4603	#define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /!<GROUP5_IO2 channel mode /
mbed_official	5:ac9f6c2c45e8	4604	#define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /!<GROUP5_IO3 channel mode /
mbed_official	5:ac9f6c2c45e8	4605	#define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /!<GROUP5_IO4 channel mode /
mbed_official	5:ac9f6c2c45e8	4606	#define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /!<GROUP6_IO1 channel mode /
mbed_official	5:ac9f6c2c45e8	4607	#define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /!<GROUP6_IO2 channel mode /
mbed_official	5:ac9f6c2c45e8	4608	#define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /!<GROUP6_IO3 channel mode /
mbed_official	5:ac9f6c2c45e8	4609	#define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /!<GROUP6_IO4 channel mode /
mbed_official	5:ac9f6c2c45e8	4610	#define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /!<GROUP7_IO1 channel mode /
mbed_official	5:ac9f6c2c45e8	4611	#define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /!<GROUP7_IO2 channel mode /
mbed_official	5:ac9f6c2c45e8	4612	#define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /!<GROUP7_IO3 channel mode /
mbed_official	5:ac9f6c2c45e8	4613	#define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /!<GROUP7_IO4 channel mode /
mbed_official	5:ac9f6c2c45e8	4614	#define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /!<GROUP8_IO1 channel mode /
mbed_official	5:ac9f6c2c45e8	4615	#define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /!<GROUP8_IO2 channel mode /
mbed_official	5:ac9f6c2c45e8	4616	#define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /!<GROUP8_IO3 channel mode /
mbed_official	5:ac9f6c2c45e8	4617	#define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /!<GROUP8_IO4 channel mode /
mbed_official	5:ac9f6c2c45e8	4618
mbed_official	5:ac9f6c2c45e8	4619	/***************** Bit definition for TSC_IOGCSR register ***************/
mbed_official	5:ac9f6c2c45e8	4620	#define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /!<Analog IO GROUP1 enable /
mbed_official	5:ac9f6c2c45e8	4621	#define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /!<Analog IO GROUP2 enable /
mbed_official	5:ac9f6c2c45e8	4622	#define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /!<Analog IO GROUP3 enable /
mbed_official	5:ac9f6c2c45e8	4623	#define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /!<Analog IO GROUP4 enable /
mbed_official	5:ac9f6c2c45e8	4624	#define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /!<Analog IO GROUP5 enable /
mbed_official	5:ac9f6c2c45e8	4625	#define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /!<Analog IO GROUP6 enable /
mbed_official	5:ac9f6c2c45e8	4626	#define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /!<Analog IO GROUP7 enable /
mbed_official	5:ac9f6c2c45e8	4627	#define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /!<Analog IO GROUP8 enable /
mbed_official	5:ac9f6c2c45e8	4628	#define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /!<Analog IO GROUP1 status /
mbed_official	5:ac9f6c2c45e8	4629	#define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /!<Analog IO GROUP2 status /
mbed_official	5:ac9f6c2c45e8	4630	#define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /!<Analog IO GROUP3 status /
mbed_official	5:ac9f6c2c45e8	4631	#define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /!<Analog IO GROUP4 status /
mbed_official	5:ac9f6c2c45e8	4632	#define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /!<Analog IO GROUP5 status /
mbed_official	5:ac9f6c2c45e8	4633	#define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /!<Analog IO GROUP6 status /
mbed_official	5:ac9f6c2c45e8	4634	#define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /!<Analog IO GROUP7 status /
mbed_official	5:ac9f6c2c45e8	4635	#define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /!<Analog IO GROUP8 status /
mbed_official	5:ac9f6c2c45e8	4636
mbed_official	5:ac9f6c2c45e8	4637	/***************** Bit definition for TSC_IOGXCR register ***************/
mbed_official	5:ac9f6c2c45e8	4638	#define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /!<CNT[13:0] bits (Counter value) /
mbed_official	5:ac9f6c2c45e8	4639
mbed_official	5:ac9f6c2c45e8	4640	/******************************************************************************/
mbed_official	5:ac9f6c2c45e8	4641	/* */
mbed_official	5:ac9f6c2c45e8	4642	/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
mbed_official	5:ac9f6c2c45e8	4643	/* */
mbed_official	5:ac9f6c2c45e8	4644	/******************************************************************************/
mbed_official	5:ac9f6c2c45e8	4645	/**************** Bit definition for USART_CR1 register *****************/
mbed_official	5:ac9f6c2c45e8	4646	#define USART_CR1_UE ((uint32_t)0x00000001) /!< USART Enable /
mbed_official	5:ac9f6c2c45e8	4647	#define USART_CR1_UESM ((uint32_t)0x00000002) /!< USART Enable in STOP Mode /
mbed_official	5:ac9f6c2c45e8	4648	#define USART_CR1_RE ((uint32_t)0x00000004) /!< Receiver Enable /
mbed_official	5:ac9f6c2c45e8	4649	#define USART_CR1_TE ((uint32_t)0x00000008) /!< Transmitter Enable /
mbed_official	5:ac9f6c2c45e8	4650	#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /!< IDLE Interrupt Enable /
mbed_official	5:ac9f6c2c45e8	4651	#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /!< RXNE Interrupt Enable /
mbed_official	5:ac9f6c2c45e8	4652	#define USART_CR1_TCIE ((uint32_t)0x00000040) /!< Transmission Complete Interrupt Enable /
mbed_official	5:ac9f6c2c45e8	4653	#define USART_CR1_TXEIE ((uint32_t)0x00000080) /!< TXE Interrupt Enable /
mbed_official	5:ac9f6c2c45e8	4654	#define USART_CR1_PEIE ((uint32_t)0x00000100) /!< PE Interrupt Enable /
mbed_official	5:ac9f6c2c45e8	4655	#define USART_CR1_PS ((uint32_t)0x00000200) /!< Parity Selection /
mbed_official	5:ac9f6c2c45e8	4656	#define USART_CR1_PCE ((uint32_t)0x00000400) /!< Parity Control Enable /
mbed_official	5:ac9f6c2c45e8	4657	#define USART_CR1_WAKE ((uint32_t)0x00000800) /!< Receiver Wakeup method /
mbed_official	5:ac9f6c2c45e8	4658	#define USART_CR1_M0 ((uint32_t)0x00001000) /!< Word length bit 0 /
mbed_official	5:ac9f6c2c45e8	4659	#define USART_CR1_MME ((uint32_t)0x00002000) /!< Mute Mode Enable /
mbed_official	5:ac9f6c2c45e8	4660	#define USART_CR1_CMIE ((uint32_t)0x00004000) /!< Character match interrupt enable /
mbed_official	5:ac9f6c2c45e8	4661	#define USART_CR1_OVER8 ((uint32_t)0x00008000) /!< Oversampling by 8-bit or 16-bit mode /
mbed_official	5:ac9f6c2c45e8	4662	#define USART_CR1_DEDT ((uint32_t)0x001F0000) /!< DEDT[4:0] bits (Driver Enable Deassertion Time) /
mbed_official	5:ac9f6c2c45e8	4663	#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /!< Bit 0 /
mbed_official	5:ac9f6c2c45e8	4664	#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /!< Bit 1 /
mbed_official	5:ac9f6c2c45e8	4665	#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /!< Bit 2 /
mbed_official	5:ac9f6c2c45e8	4666	#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /!< Bit 3 /
mbed_official	5:ac9f6c2c45e8	4667	#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /!< Bit 4 /
mbed_official	5:ac9f6c2c45e8	4668	#define USART_CR1_DEAT ((uint32_t)0x03E00000) /!< DEAT[4:0] bits (Driver Enable Assertion Time) /
mbed_official	5:ac9f6c2c45e8	4669	#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /!< Bit 0 /
mbed_official	5:ac9f6c2c45e8	4670	#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /!< Bit 1 /
mbed_official	5:ac9f6c2c45e8	4671	#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /!< Bit 2 /
mbed_official	5:ac9f6c2c45e8	4672	#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /!< Bit 3 /
mbed_official	5:ac9f6c2c45e8	4673	#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /!< Bit 4 /
mbed_official	5:ac9f6c2c45e8	4674	#define USART_CR1_RTOIE ((uint32_t)0x04000000) /!< Receive Time Out interrupt enable /
mbed_official	5:ac9f6c2c45e8	4675	#define USART_CR1_EOBIE ((uint32_t)0x08000000) /!< End of Block interrupt enable /
mbed_official	5:ac9f6c2c45e8	4676	#define USART_CR1_M1 ((uint32_t)0x10000000) /!< Word length bit 1 /
mbed_official	5:ac9f6c2c45e8	4677	#define USART_CR1_M ((uint32_t)0x10001000) /!< [M1:M0] Word length /
mbed_official	5:ac9f6c2c45e8	4678
mbed_official	5:ac9f6c2c45e8	4679	/**************** Bit definition for USART_CR2 register *****************/
mbed_official	5:ac9f6c2c45e8	4680	#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /!< 7-bit or 4-bit Address Detection /
mbed_official	5:ac9f6c2c45e8	4681	#define USART_CR2_LBDL ((uint32_t)0x00000020) /!< LIN Break Detection Length /
mbed_official	5:ac9f6c2c45e8	4682	#define USART_CR2_LBDIE ((uint32_t)0x00000040) /!< LIN Break Detection Interrupt Enable /
mbed_official	5:ac9f6c2c45e8	4683	#define USART_CR2_LBCL ((uint32_t)0x00000100) /!< Last Bit Clock pulse /
mbed_official	5:ac9f6c2c45e8	4684	#define USART_CR2_CPHA ((uint32_t)0x00000200) /!< Clock Phase /
mbed_official	5:ac9f6c2c45e8	4685	#define USART_CR2_CPOL ((uint32_t)0x00000400) /!< Clock Polarity /
mbed_official	5:ac9f6c2c45e8	4686	#define USART_CR2_CLKEN ((uint32_t)0x00000800) /!< Clock Enable /
mbed_official	5:ac9f6c2c45e8	4687	#define USART_CR2_STOP ((uint32_t)0x00003000) /!< STOP[1:0] bits (STOP bits) /
mbed_official	5:ac9f6c2c45e8	4688	#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /!< Bit 0 /
mbed_official	5:ac9f6c2c45e8	4689	#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /!< Bit 1 /
mbed_official	5:ac9f6c2c45e8	4690	#define USART_CR2_LINEN ((uint32_t)0x00004000) /!< LIN mode enable /
mbed_official	5:ac9f6c2c45e8	4691	#define USART_CR2_SWAP ((uint32_t)0x00008000) /!< SWAP TX/RX pins /
mbed_official	5:ac9f6c2c45e8	4692	#define USART_CR2_RXINV ((uint32_t)0x00010000) /!< RX pin active level inversion /
mbed_official	5:ac9f6c2c45e8	4693	#define USART_CR2_TXINV ((uint32_t)0x00020000) /!< TX pin active level inversion /
mbed_official	5:ac9f6c2c45e8	4694	#define USART_CR2_DATAINV ((uint32_t)0x00040000) /!< Binary data inversion /
mbed_official	5:ac9f6c2c45e8	4695	#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /!< Most Significant Bit First /
mbed_official	5:ac9f6c2c45e8	4696	#define USART_CR2_ABREN ((uint32_t)0x00100000) /!< Auto Baud-Rate Enable/
mbed_official	5:ac9f6c2c45e8	4697	#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) /
mbed_official	5:ac9f6c2c45e8	4698	#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /!< Bit 0 /
mbed_official	5:ac9f6c2c45e8	4699	#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /!< Bit 1 /
mbed_official	5:ac9f6c2c45e8	4700	#define USART_CR2_RTOEN ((uint32_t)0x00800000) /!< Receiver Time-Out enable /
mbed_official	5:ac9f6c2c45e8	4701	#define USART_CR2_ADD ((uint32_t)0xFF000000) /!< Address of the USART node /
mbed_official	5:ac9f6c2c45e8	4702
mbed_official	5:ac9f6c2c45e8	4703	/**************** Bit definition for USART_CR3 register *****************/
mbed_official	5:ac9f6c2c45e8	4704	#define USART_CR3_EIE ((uint32_t)0x00000001) /!< Error Interrupt Enable /
mbed_official	5:ac9f6c2c45e8	4705	#define USART_CR3_IREN ((uint32_t)0x00000002) /!< IrDA mode Enable /
mbed_official	5:ac9f6c2c45e8	4706	#define USART_CR3_IRLP ((uint32_t)0x00000004) /!< IrDA Low-Power /
mbed_official	5:ac9f6c2c45e8	4707	#define USART_CR3_HDSEL ((uint32_t)0x00000008) /!< Half-Duplex Selection /
mbed_official	5:ac9f6c2c45e8	4708	#define USART_CR3_NACK ((uint32_t)0x00000010) /!< SmartCard NACK enable /
mbed_official	5:ac9f6c2c45e8	4709	#define USART_CR3_SCEN ((uint32_t)0x00000020) /!< SmartCard mode enable /
mbed_official	5:ac9f6c2c45e8	4710	#define USART_CR3_DMAR ((uint32_t)0x00000040) /!< DMA Enable Receiver /
mbed_official	5:ac9f6c2c45e8	4711	#define USART_CR3_DMAT ((uint32_t)0x00000080) /!< DMA Enable Transmitter /
mbed_official	5:ac9f6c2c45e8	4712	#define USART_CR3_RTSE ((uint32_t)0x00000100) /!< RTS Enable /
mbed_official	5:ac9f6c2c45e8	4713	#define USART_CR3_CTSE ((uint32_t)0x00000200) /!< CTS Enable /
mbed_official	5:ac9f6c2c45e8	4714	#define USART_CR3_CTSIE ((uint32_t)0x00000400) /!< CTS Interrupt Enable /
mbed_official	5:ac9f6c2c45e8	4715	#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /!< One sample bit method enable /
mbed_official	5:ac9f6c2c45e8	4716	#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /!< Overrun Disable /
mbed_official	5:ac9f6c2c45e8	4717	#define USART_CR3_DDRE ((uint32_t)0x00002000) /!< DMA Disable on Reception Error /
mbed_official	5:ac9f6c2c45e8	4718	#define USART_CR3_DEM ((uint32_t)0x00004000) /!< Driver Enable Mode /
mbed_official	5:ac9f6c2c45e8	4719	#define USART_CR3_DEP ((uint32_t)0x00008000) /!< Driver Enable Polarity Selection /
mbed_official	5:ac9f6c2c45e8	4720	#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) /
mbed_official	5:ac9f6c2c45e8	4721	#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /!< Bit 0 /
mbed_official	5:ac9f6c2c45e8	4722	#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /!< Bit 1 /
mbed_official	5:ac9f6c2c45e8	4723	#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /!< Bit 2 /
mbed_official	5:ac9f6c2c45e8	4724	#define USART_CR3_WUS ((uint32_t)0x00300000) /!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) /
mbed_official	5:ac9f6c2c45e8	4725	#define USART_CR3_WUS_0 ((uint32_t)0x00100000) /!< Bit 0 /
mbed_official	5:ac9f6c2c45e8	4726	#define USART_CR3_WUS_1 ((uint32_t)0x00200000) /!< Bit 1 /
mbed_official	5:ac9f6c2c45e8	4727	#define USART_CR3_WUFIE ((uint32_t)0x00400000) /!< Wake Up Interrupt Enable /
mbed_official	5:ac9f6c2c45e8	4728
mbed_official	5:ac9f6c2c45e8	4729	/**************** Bit definition for USART_BRR register *****************/
mbed_official	5:ac9f6c2c45e8	4730	#define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /!< Fraction of USARTDIV /
mbed_official	5:ac9f6c2c45e8	4731	#define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /!< Mantissa of USARTDIV /
mbed_official	5:ac9f6c2c45e8	4732
mbed_official	5:ac9f6c2c45e8	4733	/**************** Bit definition for USART_GTPR register ****************/
mbed_official	5:ac9f6c2c45e8	4734	#define USART_GTPR_PSC ((uint32_t)0x000000FF) /!< PSC[7:0] bits (Prescaler value) /
mbed_official	5:ac9f6c2c45e8	4735	#define USART_GTPR_GT ((uint32_t)0x0000FF00) /!< GT[7:0] bits (Guard time value) /
mbed_official	5:ac9f6c2c45e8	4736
mbed_official	5:ac9f6c2c45e8	4737
mbed_official	5:ac9f6c2c45e8	4738	/***************** Bit definition for USART_RTOR register ***************/
mbed_official	5:ac9f6c2c45e8	4739	#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /!< Receiver Time Out Value /
mbed_official	5:ac9f6c2c45e8	4740	#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /!< Block Length /
mbed_official	5:ac9f6c2c45e8	4741
mbed_official	5:ac9f6c2c45e8	4742	/***************** Bit definition for USART_RQR register ****************/
mbed_official	5:ac9f6c2c45e8	4743	#define USART_RQR_ABRRQ ((uint32_t)0x00000001) /!< Auto-Baud Rate Request /
mbed_official	5:ac9f6c2c45e8	4744	#define USART_RQR_SBKRQ ((uint32_t)0x00000002) /!< Send Break Request /
mbed_official	5:ac9f6c2c45e8	4745	#define USART_RQR_MMRQ ((uint32_t)0x00000004) /!< Mute Mode Request /
mbed_official	5:ac9f6c2c45e8	4746	#define USART_RQR_RXFRQ ((uint32_t)0x00000008) /!< Receive Data flush Request /
mbed_official	5:ac9f6c2c45e8	4747	#define USART_RQR_TXFRQ ((uint32_t)0x00000010) /!< Transmit data flush Request /
mbed_official	5:ac9f6c2c45e8	4748
mbed_official	5:ac9f6c2c45e8	4749	/***************** Bit definition for USART_ISR register ****************/
mbed_official	5:ac9f6c2c45e8	4750	#define USART_ISR_PE ((uint32_t)0x00000001) /!< Parity Error /
mbed_official	5:ac9f6c2c45e8	4751	#define USART_ISR_FE ((uint32_t)0x00000002) /!< Framing Error /
mbed_official	5:ac9f6c2c45e8	4752	#define USART_ISR_NE ((uint32_t)0x00000004) /!< Noise detected Flag /
mbed_official	5:ac9f6c2c45e8	4753	#define USART_ISR_ORE ((uint32_t)0x00000008) /!< OverRun Error /
mbed_official	5:ac9f6c2c45e8	4754	#define USART_ISR_IDLE ((uint32_t)0x00000010) /!< IDLE line detected /
mbed_official	5:ac9f6c2c45e8	4755	#define USART_ISR_RXNE ((uint32_t)0x00000020) /!< Read Data Register Not Empty /
mbed_official	5:ac9f6c2c45e8	4756	#define USART_ISR_TC ((uint32_t)0x00000040) /!< Transmission Complete /
mbed_official	5:ac9f6c2c45e8	4757	#define USART_ISR_TXE ((uint32_t)0x00000080) /!< Transmit Data Register Empty /
mbed_official	5:ac9f6c2c45e8	4758	#define USART_ISR_LBDF ((uint32_t)0x00000100) /!< LIN Break Detection Flag /
mbed_official	5:ac9f6c2c45e8	4759	#define USART_ISR_CTSIF ((uint32_t)0x00000200) /!< CTS interrupt flag /
mbed_official	5:ac9f6c2c45e8	4760	#define USART_ISR_CTS ((uint32_t)0x00000400) /!< CTS flag /
mbed_official	5:ac9f6c2c45e8	4761	#define USART_ISR_RTOF ((uint32_t)0x00000800) /!< Receiver Time Out /
mbed_official	5:ac9f6c2c45e8	4762	#define USART_ISR_EOBF ((uint32_t)0x00001000) /!< End Of Block Flag /
mbed_official	5:ac9f6c2c45e8	4763	#define USART_ISR_ABRE ((uint32_t)0x00004000) /!< Auto-Baud Rate Error /
mbed_official	5:ac9f6c2c45e8	4764	#define USART_ISR_ABRF ((uint32_t)0x00008000) /!< Auto-Baud Rate Flag /
mbed_official	5:ac9f6c2c45e8	4765	#define USART_ISR_BUSY ((uint32_t)0x00010000) /!< Busy Flag /
mbed_official	5:ac9f6c2c45e8	4766	#define USART_ISR_CMF ((uint32_t)0x00020000) /!< Character Match Flag /
mbed_official	5:ac9f6c2c45e8	4767	#define USART_ISR_SBKF ((uint32_t)0x00040000) /!< Send Break Flag /
mbed_official	5:ac9f6c2c45e8	4768	#define USART_ISR_RWU ((uint32_t)0x00080000) /!< Receive Wake Up from mute mode Flag /
mbed_official	5:ac9f6c2c45e8	4769	#define USART_ISR_WUF ((uint32_t)0x00100000) /!< Wake Up from stop mode Flag /
mbed_official	5:ac9f6c2c45e8	4770	#define USART_ISR_TEACK ((uint32_t)0x00200000) /!< Transmit Enable Acknowledge Flag /
mbed_official	5:ac9f6c2c45e8	4771	#define USART_ISR_REACK ((uint32_t)0x00400000) /!< Receive Enable Acknowledge Flag /
mbed_official	5:ac9f6c2c45e8	4772
mbed_official	5:ac9f6c2c45e8	4773	/***************** Bit definition for USART_ICR register ****************/
mbed_official	5:ac9f6c2c45e8	4774	#define USART_ICR_PECF ((uint32_t)0x00000001) /!< Parity Error Clear Flag /
mbed_official	5:ac9f6c2c45e8	4775	#define USART_ICR_FECF ((uint32_t)0x00000002) /!< Framing Error Clear Flag /
mbed_official	5:ac9f6c2c45e8	4776	#define USART_ICR_NCF ((uint32_t)0x00000004) /!< Noise detected Clear Flag /
mbed_official	5:ac9f6c2c45e8	4777	#define USART_ICR_ORECF ((uint32_t)0x00000008) /!< OverRun Error Clear Flag /
mbed_official	5:ac9f6c2c45e8	4778	#define USART_ICR_IDLECF ((uint32_t)0x00000010) /!< IDLE line detected Clear Flag /
mbed_official	5:ac9f6c2c45e8	4779	#define USART_ICR_TCCF ((uint32_t)0x00000040) /!< Transmission Complete Clear Flag /
mbed_official	5:ac9f6c2c45e8	4780	#define USART_ICR_LBDCF ((uint32_t)0x00000100) /!< LIN Break Detection Clear Flag /
mbed_official	5:ac9f6c2c45e8	4781	#define USART_ICR_CTSCF ((uint32_t)0x00000200) /!< CTS Interrupt Clear Flag /
mbed_official	5:ac9f6c2c45e8	4782	#define USART_ICR_RTOCF ((uint32_t)0x00000800) /!< Receiver Time Out Clear Flag /
mbed_official	5:ac9f6c2c45e8	4783	#define USART_ICR_EOBCF ((uint32_t)0x00001000) /!< End Of Block Clear Flag /
mbed_official	5:ac9f6c2c45e8	4784	#define USART_ICR_CMCF ((uint32_t)0x00020000) /!< Character Match Clear Flag /
mbed_official	5:ac9f6c2c45e8	4785	#define USART_ICR_WUCF ((uint32_t)0x00100000) /!< Wake Up from stop mode Clear Flag /
mbed_official	5:ac9f6c2c45e8	4786
mbed_official	5:ac9f6c2c45e8	4787	/***************** Bit definition for USART_RDR register ****************/
mbed_official	5:ac9f6c2c45e8	4788	#define USART_RDR_RDR ((uint16_t)0x01FF) /!< RDR[8:0] bits (Receive Data value) /
mbed_official	5:ac9f6c2c45e8	4789
mbed_official	5:ac9f6c2c45e8	4790	/***************** Bit definition for USART_TDR register ****************/
mbed_official	5:ac9f6c2c45e8	4791	#define USART_TDR_TDR ((uint16_t)0x01FF) /!< TDR[8:0] bits (Transmit Data value) /
mbed_official	5:ac9f6c2c45e8	4792
mbed_official	5:ac9f6c2c45e8	4793	/******************************************************************************/
mbed_official	5:ac9f6c2c45e8	4794	/* */
mbed_official	5:ac9f6c2c45e8	4795	/* USB Device General registers */
mbed_official	5:ac9f6c2c45e8	4796	/* */
mbed_official	5:ac9f6c2c45e8	4797	/******************************************************************************/
mbed_official	5:ac9f6c2c45e8	4798	#define USB_CNTR (USB_BASE + 0x40) /!< Control register /
mbed_official	5:ac9f6c2c45e8	4799	#define USB_ISTR (USB_BASE + 0x44) /!< Interrupt status register /
mbed_official	5:ac9f6c2c45e8	4800	#define USB_FNR (USB_BASE + 0x48) /!< Frame number register /
mbed_official	5:ac9f6c2c45e8	4801	#define USB_DADDR (USB_BASE + 0x4C) /!< Device address register /
mbed_official	5:ac9f6c2c45e8	4802	#define USB_BTABLE (USB_BASE + 0x50) /!< Buffer Table address register /
mbed_official	5:ac9f6c2c45e8	4803	#define USB_LPMCSR (USB_BASE + 0x54) /!< LPM Control and Status register /
mbed_official	5:ac9f6c2c45e8	4804	#define USB_BCDR (USB_BASE + 0x58) /!< Battery Charging detector register/
mbed_official	5:ac9f6c2c45e8	4805
mbed_official	5:ac9f6c2c45e8	4806	/************************** ISTR interrupt events ***********************/
mbed_official	5:ac9f6c2c45e8	4807	#define USB_ISTR_CTR ((uint16_t)0x8000) /!< Correct TRansfer (clear-only bit) /
mbed_official	5:ac9f6c2c45e8	4808	#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /!< DMA OVeR/underrun (clear-only bit) /
mbed_official	5:ac9f6c2c45e8	4809	#define USB_ISTR_ERR ((uint16_t)0x2000) /!< ERRor (clear-only bit) /
mbed_official	5:ac9f6c2c45e8	4810	#define USB_ISTR_WKUP ((uint16_t)0x1000) /!< WaKe UP (clear-only bit) /
mbed_official	5:ac9f6c2c45e8	4811	#define USB_ISTR_SUSP ((uint16_t)0x0800) /!< SUSPend (clear-only bit) /
mbed_official	5:ac9f6c2c45e8	4812	#define USB_ISTR_RESET ((uint16_t)0x0400) /!< RESET (clear-only bit) /
mbed_official	5:ac9f6c2c45e8	4813	#define USB_ISTR_SOF ((uint16_t)0x0200) /!< Start Of Frame (clear-only bit) /
mbed_official	5:ac9f6c2c45e8	4814	#define USB_ISTR_ESOF ((uint16_t)0x0100) /!< Expected Start Of Frame (clear-only bit) /
mbed_official	5:ac9f6c2c45e8	4815	#define USB_ISTR_L1REQ ((uint16_t)0x0080) /!< LPM L1 state request /
mbed_official	5:ac9f6c2c45e8	4816	#define USB_ISTR_DIR ((uint16_t)0x0010) /!< DIRection of transaction (read-only bit) /
mbed_official	5:ac9f6c2c45e8	4817	#define USB_ISTR_EP_ID ((uint16_t)0x000F) /!< EndPoint IDentifier (read-only bit) /
mbed_official	5:ac9f6c2c45e8	4818
mbed_official	5:ac9f6c2c45e8	4819	#define USB_CLR_CTR (~USB_ISTR_CTR) /!< clear Correct TRansfer bit /
mbed_official	5:ac9f6c2c45e8	4820	#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /!< clear DMA OVeR/underrun bit/
mbed_official	5:ac9f6c2c45e8	4821	#define USB_CLR_ERR (~USB_ISTR_ERR) /!< clear ERRor bit /
mbed_official	5:ac9f6c2c45e8	4822	#define USB_CLR_WKUP (~USB_ISTR_WKUP) /!< clear WaKe UP bit /
mbed_official	5:ac9f6c2c45e8	4823	#define USB_CLR_SUSP (~USB_ISTR_SUSP) /!< clear SUSPend bit /
mbed_official	5:ac9f6c2c45e8	4824	#define USB_CLR_RESET (~USB_ISTR_RESET) /!< clear RESET bit /
mbed_official	5:ac9f6c2c45e8	4825	#define USB_CLR_SOF (~USB_ISTR_SOF) /!< clear Start Of Frame bit /
mbed_official	5:ac9f6c2c45e8	4826	#define USB_CLR_ESOF (~USB_ISTR_ESOF) /!< clear Expected Start Of Frame bit /
mbed_official	5:ac9f6c2c45e8	4827	#define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /!< clear LPM L1 bit /
mbed_official	5:ac9f6c2c45e8	4828
mbed_official	5:ac9f6c2c45e8	4829	/*********************** CNTR control register bits definitions *********/
mbed_official	5:ac9f6c2c45e8	4830	#define USB_CNTR_CTRM ((uint16_t)0x8000) /!< Correct TRansfer Mask /
mbed_official	5:ac9f6c2c45e8	4831	#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /!< DMA OVeR/underrun Mask /
mbed_official	5:ac9f6c2c45e8	4832	#define USB_CNTR_ERRM ((uint16_t)0x2000) /!< ERRor Mask /
mbed_official	5:ac9f6c2c45e8	4833	#define USB_CNTR_WKUPM ((uint16_t)0x1000) /!< WaKe UP Mask /
mbed_official	5:ac9f6c2c45e8	4834	#define USB_CNTR_SUSPM ((uint16_t)0x0800) /!< SUSPend Mask /
mbed_official	5:ac9f6c2c45e8	4835	#define USB_CNTR_RESETM ((uint16_t)0x0400) /!< RESET Mask /
mbed_official	5:ac9f6c2c45e8	4836	#define USB_CNTR_SOFM ((uint16_t)0x0200) /!< Start Of Frame Mask /
mbed_official	5:ac9f6c2c45e8	4837	#define USB_CNTR_ESOFM ((uint16_t)0x0100) /!< Expected Start Of Frame Mask /
mbed_official	5:ac9f6c2c45e8	4838	#define USB_CNTR_L1REQM ((uint16_t)0x0080) /!< LPM L1 state request interrupt mask /
mbed_official	5:ac9f6c2c45e8	4839	#define USB_CNTR_L1RESUME ((uint16_t)0x0020) /!< LPM L1 Resume request /
mbed_official	5:ac9f6c2c45e8	4840	#define USB_CNTR_RESUME ((uint16_t)0x0010) /!< RESUME request /
mbed_official	5:ac9f6c2c45e8	4841	#define USB_CNTR_FSUSP ((uint16_t)0x0008) /!< Force SUSPend /
mbed_official	5:ac9f6c2c45e8	4842	#define USB_CNTR_LPMODE ((uint16_t)0x0004) /!< Low-power MODE /
mbed_official	5:ac9f6c2c45e8	4843	#define USB_CNTR_PDWN ((uint16_t)0x0002) /!< Power DoWN /
mbed_official	5:ac9f6c2c45e8	4844	#define USB_CNTR_FRES ((uint16_t)0x0001) /!< Force USB RESet /
mbed_official	5:ac9f6c2c45e8	4845
mbed_official	5:ac9f6c2c45e8	4846	/*********************** BCDR control register bits definitions *********/
mbed_official	5:ac9f6c2c45e8	4847	#define USB_BCDR_DPPU ((uint16_t)0x8000) /!< DP Pull-up Enable /
mbed_official	5:ac9f6c2c45e8	4848	#define USB_BCDR_PS2DET ((uint16_t)0x0080) /!< PS2 port or proprietary charger detected /
mbed_official	5:ac9f6c2c45e8	4849	#define USB_BCDR_SDET ((uint16_t)0x0040) /!< Secondary detection (SD) status /
mbed_official	5:ac9f6c2c45e8	4850	#define USB_BCDR_PDET ((uint16_t)0x0020) /!< Primary detection (PD) status /
mbed_official	5:ac9f6c2c45e8	4851	#define USB_BCDR_DCDET ((uint16_t)0x0010) /!< Data contact detection (DCD) status /
mbed_official	5:ac9f6c2c45e8	4852	#define USB_BCDR_SDEN ((uint16_t)0x0008) /!< Secondary detection (SD) mode enable /
mbed_official	5:ac9f6c2c45e8	4853	#define USB_BCDR_PDEN ((uint16_t)0x0004) /!< Primary detection (PD) mode enable /
mbed_official	5:ac9f6c2c45e8	4854	#define USB_BCDR_DCDEN ((uint16_t)0x0002) /!< Data contact detection (DCD) mode enable /
mbed_official	5:ac9f6c2c45e8	4855	#define USB_BCDR_BCDEN ((uint16_t)0x0001) /!< Battery charging detector (BCD) enable /
mbed_official	5:ac9f6c2c45e8	4856
mbed_official	5:ac9f6c2c45e8	4857	/************************* LPM register bits definitions ****************/
mbed_official	5:ac9f6c2c45e8	4858	#define USB_LPMCSR_BESL ((uint16_t)0x00F0) /!< BESL value received with last ACKed LPM Token /
mbed_official	5:ac9f6c2c45e8	4859	#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008) /!< bRemoteWake value received with last ACKed LPM Token /
mbed_official	5:ac9f6c2c45e8	4860	#define USB_LPMCSR_LPMACK ((uint16_t)0x0002) /!< LPM Token acknowledge enable/
mbed_official	5:ac9f6c2c45e8	4861	#define USB_LPMCSR_LMPEN ((uint16_t)0x0001) /!< LPM support enable /
mbed_official	5:ac9f6c2c45e8	4862
mbed_official	5:ac9f6c2c45e8	4863	/****************** FNR Frame Number Register bit definitions **********/
mbed_official	5:ac9f6c2c45e8	4864	#define USB_FNR_RXDP ((uint16_t)0x8000) /!< status of D+ data line /
mbed_official	5:ac9f6c2c45e8	4865	#define USB_FNR_RXDM ((uint16_t)0x4000) /!< status of D- data line /
mbed_official	5:ac9f6c2c45e8	4866	#define USB_FNR_LCK ((uint16_t)0x2000) /!< LoCKed /
mbed_official	5:ac9f6c2c45e8	4867	#define USB_FNR_LSOF ((uint16_t)0x1800) /!< Lost SOF /
mbed_official	5:ac9f6c2c45e8	4868	#define USB_FNR_FN ((uint16_t)0x07FF) /!< Frame Number /
mbed_official	5:ac9f6c2c45e8	4869
mbed_official	5:ac9f6c2c45e8	4870	/****************** DADDR Device ADDRess bit definitions **************/
mbed_official	5:ac9f6c2c45e8	4871	#define USB_DADDR_EF ((uint8_t)0x80) /!< USB device address Enable Function /
mbed_official	5:ac9f6c2c45e8	4872	#define USB_DADDR_ADD ((uint8_t)0x7F) /!< USB device address /
mbed_official	5:ac9f6c2c45e8	4873
mbed_official	5:ac9f6c2c45e8	4874	/**************************** Endpoint register ***********************/
mbed_official	5:ac9f6c2c45e8	4875	#define USB_EP0R USB_BASE /!< endpoint 0 register address /
mbed_official	5:ac9f6c2c45e8	4876	#define USB_EP1R (USB_BASE + 0x04) /!< endpoint 1 register address /
mbed_official	5:ac9f6c2c45e8	4877	#define USB_EP2R (USB_BASE + 0x08) /!< endpoint 2 register address /
mbed_official	5:ac9f6c2c45e8	4878	#define USB_EP3R (USB_BASE + 0x0C) /!< endpoint 3 register address /
mbed_official	5:ac9f6c2c45e8	4879	#define USB_EP4R (USB_BASE + 0x10) /!< endpoint 4 register address /
mbed_official	5:ac9f6c2c45e8	4880	#define USB_EP5R (USB_BASE + 0x14) /!< endpoint 5 register address /
mbed_official	5:ac9f6c2c45e8	4881	#define USB_EP6R (USB_BASE + 0x18) /!< endpoint 6 register address /
mbed_official	5:ac9f6c2c45e8	4882	#define USB_EP7R (USB_BASE + 0x1C) /!< endpoint 7 register address /
mbed_official	5:ac9f6c2c45e8	4883	/* bit positions */
mbed_official	5:ac9f6c2c45e8	4884	#define USB_EP_CTR_RX ((uint16_t)0x8000) /!< EndPoint Correct TRansfer RX /
mbed_official	5:ac9f6c2c45e8	4885	#define USB_EP_DTOG_RX ((uint16_t)0x4000) /!< EndPoint Data TOGGLE RX /
mbed_official	5:ac9f6c2c45e8	4886	#define USB_EPRX_STAT ((uint16_t)0x3000) /!< EndPoint RX STATus bit field /
mbed_official	5:ac9f6c2c45e8	4887	#define USB_EP_SETUP ((uint16_t)0x0800) /!< EndPoint SETUP /
mbed_official	5:ac9f6c2c45e8	4888	#define USB_EP_T_FIELD ((uint16_t)0x0600) /!< EndPoint TYPE /
mbed_official	5:ac9f6c2c45e8	4889	#define USB_EP_KIND ((uint16_t)0x0100) /!< EndPoint KIND /
mbed_official	5:ac9f6c2c45e8	4890	#define USB_EP_CTR_TX ((uint16_t)0x0080) /!< EndPoint Correct TRansfer TX /
mbed_official	5:ac9f6c2c45e8	4891	#define USB_EP_DTOG_TX ((uint16_t)0x0040) /!< EndPoint Data TOGGLE TX /
mbed_official	5:ac9f6c2c45e8	4892	#define USB_EPTX_STAT ((uint16_t)0x0030) /!< EndPoint TX STATus bit field /
mbed_official	5:ac9f6c2c45e8	4893	#define USB_EPADDR_FIELD ((uint16_t)0x000F) /!< EndPoint ADDRess FIELD /
mbed_official	5:ac9f6c2c45e8	4894
mbed_official	5:ac9f6c2c45e8	4895	/* EndPoint REGister MASK (no toggle fields) */
mbed_official	5:ac9f6c2c45e8	4896	#define USB_EPREG_MASK (USB_EP_CTR_RX\|USB_EP_SETUP\|USB_EP_T_FIELD\|USB_EP_KIND\|USB_EP_CTR_TX\|USB_EPADDR_FIELD)
mbed_official	5:ac9f6c2c45e8	4897	/!< EP_TYPE[1:0] EndPoint TYPE /
mbed_official	5:ac9f6c2c45e8	4898	#define USB_EP_TYPE_MASK ((uint16_t)0x0600) /!< EndPoint TYPE Mask /
mbed_official	5:ac9f6c2c45e8	4899	#define USB_EP_BULK ((uint16_t)0x0000) /!< EndPoint BULK /
mbed_official	5:ac9f6c2c45e8	4900	#define USB_EP_CONTROL ((uint16_t)0x0200) /!< EndPoint CONTROL /
mbed_official	5:ac9f6c2c45e8	4901	#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400) /!< EndPoint ISOCHRONOUS /
mbed_official	5:ac9f6c2c45e8	4902	#define USB_EP_INTERRUPT ((uint16_t)0x0600) /!< EndPoint INTERRUPT /
mbed_official	5:ac9f6c2c45e8	4903	#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
mbed_official	5:ac9f6c2c45e8	4904
mbed_official	5:ac9f6c2c45e8	4905	#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /!< EP_KIND EndPoint KIND /
mbed_official	5:ac9f6c2c45e8	4906	/!< STAT_TX[1:0] STATus for TX transfer /
mbed_official	5:ac9f6c2c45e8	4907	#define USB_EP_TX_DIS ((uint16_t)0x0000) /!< EndPoint TX DISabled /
mbed_official	5:ac9f6c2c45e8	4908	#define USB_EP_TX_STALL ((uint16_t)0x0010) /!< EndPoint TX STALLed /
mbed_official	5:ac9f6c2c45e8	4909	#define USB_EP_TX_NAK ((uint16_t)0x0020) /!< EndPoint TX NAKed /
mbed_official	5:ac9f6c2c45e8	4910	#define USB_EP_TX_VALID ((uint16_t)0x0030) /!< EndPoint TX VALID /
mbed_official	5:ac9f6c2c45e8	4911	#define USB_EPTX_DTOG1 ((uint16_t)0x0010) /!< EndPoint TX Data TOGgle bit1 /
mbed_official	5:ac9f6c2c45e8	4912	#define USB_EPTX_DTOG2 ((uint16_t)0x0020) /!< EndPoint TX Data TOGgle bit2 /
mbed_official	5:ac9f6c2c45e8	4913	#define USB_EPTX_DTOGMASK (USB_EPTX_STAT\|USB_EPREG_MASK)
mbed_official	5:ac9f6c2c45e8	4914	/!< STAT_RX[1:0] STATus for RX transfer /
mbed_official	5:ac9f6c2c45e8	4915	#define USB_EP_RX_DIS ((uint16_t)0x0000) /!< EndPoint RX DISabled /
mbed_official	5:ac9f6c2c45e8	4916	#define USB_EP_RX_STALL ((uint16_t)0x1000) /!< EndPoint RX STALLed /
mbed_official	5:ac9f6c2c45e8	4917	#define USB_EP_RX_NAK ((uint16_t)0x2000) /!< EndPoint RX NAKed /
mbed_official	5:ac9f6c2c45e8	4918	#define USB_EP_RX_VALID ((uint16_t)0x3000) /!< EndPoint RX VALID /
mbed_official	5:ac9f6c2c45e8	4919	#define USB_EPRX_DTOG1 ((uint16_t)0x1000) /!< EndPoint RX Data TOGgle bit1 /
mbed_official	5:ac9f6c2c45e8	4920	#define USB_EPRX_DTOG2 ((uint16_t)0x2000) /!< EndPoint RX Data TOGgle bit1 /
mbed_official	5:ac9f6c2c45e8	4921	#define USB_EPRX_DTOGMASK (USB_EPRX_STAT\|USB_EPREG_MASK)
mbed_official	5:ac9f6c2c45e8	4922
mbed_official	5:ac9f6c2c45e8	4923	/******************************************************************************/
mbed_official	5:ac9f6c2c45e8	4924	/* */
mbed_official	5:ac9f6c2c45e8	4925	/* Window WATCHDOG (WWDG) */
mbed_official	5:ac9f6c2c45e8	4926	/* */
mbed_official	5:ac9f6c2c45e8	4927	/******************************************************************************/
mbed_official	5:ac9f6c2c45e8	4928	/***************** Bit definition for WWDG_CR register ******************/
mbed_official	5:ac9f6c2c45e8	4929	#define WWDG_CR_T ((uint32_t)0x7F) /!<T[6:0] bits (7-Bit counter (MSB to LSB)) /
mbed_official	5:ac9f6c2c45e8	4930	#define WWDG_CR_T0 ((uint32_t)0x01) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	4931	#define WWDG_CR_T1 ((uint32_t)0x02) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	4932	#define WWDG_CR_T2 ((uint32_t)0x04) /!<Bit 2 /
mbed_official	5:ac9f6c2c45e8	4933	#define WWDG_CR_T3 ((uint32_t)0x08) /!<Bit 3 /
mbed_official	5:ac9f6c2c45e8	4934	#define WWDG_CR_T4 ((uint32_t)0x10) /!<Bit 4 /
mbed_official	5:ac9f6c2c45e8	4935	#define WWDG_CR_T5 ((uint32_t)0x20) /!<Bit 5 /
mbed_official	5:ac9f6c2c45e8	4936	#define WWDG_CR_T6 ((uint32_t)0x40) /!<Bit 6 /
mbed_official	5:ac9f6c2c45e8	4937
mbed_official	5:ac9f6c2c45e8	4938	#define WWDG_CR_WDGA ((uint32_t)0x80) /!<Activation bit /
mbed_official	5:ac9f6c2c45e8	4939
mbed_official	5:ac9f6c2c45e8	4940	/***************** Bit definition for WWDG_CFR register *****************/
mbed_official	5:ac9f6c2c45e8	4941	#define WWDG_CFR_W ((uint32_t)0x007F) /!<W[6:0] bits (7-bit window value) /
mbed_official	5:ac9f6c2c45e8	4942	#define WWDG_CFR_W0 ((uint32_t)0x0001) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	4943	#define WWDG_CFR_W1 ((uint32_t)0x0002) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	4944	#define WWDG_CFR_W2 ((uint32_t)0x0004) /!<Bit 2 /
mbed_official	5:ac9f6c2c45e8	4945	#define WWDG_CFR_W3 ((uint32_t)0x0008) /!<Bit 3 /
mbed_official	5:ac9f6c2c45e8	4946	#define WWDG_CFR_W4 ((uint32_t)0x0010) /!<Bit 4 /
mbed_official	5:ac9f6c2c45e8	4947	#define WWDG_CFR_W5 ((uint32_t)0x0020) /!<Bit 5 /
mbed_official	5:ac9f6c2c45e8	4948	#define WWDG_CFR_W6 ((uint32_t)0x0040) /!<Bit 6 /
mbed_official	5:ac9f6c2c45e8	4949
mbed_official	5:ac9f6c2c45e8	4950	#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /!<WDGTB[1:0] bits (Timer Base) /
mbed_official	5:ac9f6c2c45e8	4951	#define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /!<Bit 0 /
mbed_official	5:ac9f6c2c45e8	4952	#define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /!<Bit 1 /
mbed_official	5:ac9f6c2c45e8	4953
mbed_official	5:ac9f6c2c45e8	4954	#define WWDG_CFR_EWI ((uint32_t)0x0200) /!<Early Wakeup Interrupt /
mbed_official	5:ac9f6c2c45e8	4955
mbed_official	5:ac9f6c2c45e8	4956	/***************** Bit definition for WWDG_SR register ******************/
mbed_official	5:ac9f6c2c45e8	4957	#define WWDG_SR_EWIF ((uint32_t)0x01) /!<Early Wakeup Interrupt Flag /
mbed_official	5:ac9f6c2c45e8	4958
mbed_official	5:ac9f6c2c45e8	4959	/**
mbed_official	5:ac9f6c2c45e8	4960	* @}
mbed_official	5:ac9f6c2c45e8	4961	*/
mbed_official	5:ac9f6c2c45e8	4962
mbed_official	5:ac9f6c2c45e8	4963	/**
mbed_official	5:ac9f6c2c45e8	4964	* @}
mbed_official	5:ac9f6c2c45e8	4965	*/
mbed_official	5:ac9f6c2c45e8	4966
mbed_official	5:ac9f6c2c45e8	4967
mbed_official	5:ac9f6c2c45e8	4968	/** @addtogroup Exported_macro
mbed_official	5:ac9f6c2c45e8	4969	* @{
mbed_official	5:ac9f6c2c45e8	4970	*/
mbed_official	5:ac9f6c2c45e8	4971
mbed_official	5:ac9f6c2c45e8	4972	/**************************** ADC Instances *******************************/
mbed_official	5:ac9f6c2c45e8	4973	#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
mbed_official	5:ac9f6c2c45e8	4974
mbed_official	5:ac9f6c2c45e8	4975	#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
mbed_official	5:ac9f6c2c45e8	4976
mbed_official	5:ac9f6c2c45e8	4977	/***************************** CAN Instances ******************************/
mbed_official	5:ac9f6c2c45e8	4978	#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
mbed_official	5:ac9f6c2c45e8	4979
mbed_official	5:ac9f6c2c45e8	4980	/**************************** CEC Instances *******************************/
mbed_official	5:ac9f6c2c45e8	4981	#define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
mbed_official	5:ac9f6c2c45e8	4982
mbed_official	5:ac9f6c2c45e8	4983	/**************************** CRC Instances *******************************/
mbed_official	5:ac9f6c2c45e8	4984	#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
mbed_official	5:ac9f6c2c45e8	4985
mbed_official	5:ac9f6c2c45e8	4986	/***************************** DMA Instances ****************************/
mbed_official	5:ac9f6c2c45e8	4987	#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) \|\| \
mbed_official	5:ac9f6c2c45e8	4988	((INSTANCE) == DMA1_Channel2) \|\| \
mbed_official	5:ac9f6c2c45e8	4989	((INSTANCE) == DMA1_Channel3) \|\| \
mbed_official	5:ac9f6c2c45e8	4990	((INSTANCE) == DMA1_Channel4) \|\| \
mbed_official	5:ac9f6c2c45e8	4991	((INSTANCE) == DMA1_Channel5))
mbed_official	5:ac9f6c2c45e8	4992
mbed_official	5:ac9f6c2c45e8	4993	/**************************** GPIO Instances ******************************/
mbed_official	5:ac9f6c2c45e8	4994	#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
mbed_official	5:ac9f6c2c45e8	4995	((INSTANCE) == GPIOB) \|\| \
mbed_official	5:ac9f6c2c45e8	4996	((INSTANCE) == GPIOC) \|\| \
mbed_official	5:ac9f6c2c45e8	4997	((INSTANCE) == GPIOF))
mbed_official	5:ac9f6c2c45e8	4998
mbed_official	5:ac9f6c2c45e8	4999	#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
mbed_official	5:ac9f6c2c45e8	5000	((INSTANCE) == GPIOB) \|\| \
mbed_official	5:ac9f6c2c45e8	5001	((INSTANCE) == GPIOF))
mbed_official	5:ac9f6c2c45e8	5002
mbed_official	5:ac9f6c2c45e8	5003	#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
mbed_official	5:ac9f6c2c45e8	5004	((INSTANCE) == GPIOB))
mbed_official	5:ac9f6c2c45e8	5005
mbed_official	5:ac9f6c2c45e8	5006	/**************************** I2C Instances *******************************/
mbed_official	5:ac9f6c2c45e8	5007	#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
mbed_official	5:ac9f6c2c45e8	5008
mbed_official	5:ac9f6c2c45e8	5009	/**************************** I2S Instances *******************************/
mbed_official	5:ac9f6c2c45e8	5010	#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
mbed_official	5:ac9f6c2c45e8	5011
mbed_official	5:ac9f6c2c45e8	5012	/**************************** IWDG Instances ******************************/
mbed_official	5:ac9f6c2c45e8	5013	#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
mbed_official	5:ac9f6c2c45e8	5014
mbed_official	5:ac9f6c2c45e8	5015	/**************************** RTC Instances *******************************/
mbed_official	5:ac9f6c2c45e8	5016	#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
mbed_official	5:ac9f6c2c45e8	5017
mbed_official	5:ac9f6c2c45e8	5018	/**************************** SMBUS Instances *******************************/
mbed_official	5:ac9f6c2c45e8	5019	#define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
mbed_official	5:ac9f6c2c45e8	5020
mbed_official	5:ac9f6c2c45e8	5021	/**************************** SPI Instances *******************************/
mbed_official	5:ac9f6c2c45e8	5022	#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) \|\| \
mbed_official	5:ac9f6c2c45e8	5023	((INSTANCE) == SPI2))
mbed_official	5:ac9f6c2c45e8	5024
mbed_official	5:ac9f6c2c45e8	5025	/**************************** TIM Instances *******************************/
mbed_official	5:ac9f6c2c45e8	5026	#define IS_TIM_INSTANCE(INSTANCE)\
mbed_official	5:ac9f6c2c45e8	5027	(((INSTANCE) == TIM1) \|\| \
mbed_official	5:ac9f6c2c45e8	5028	((INSTANCE) == TIM2) \|\| \
mbed_official	5:ac9f6c2c45e8	5029	((INSTANCE) == TIM3) \|\| \
mbed_official	5:ac9f6c2c45e8	5030	((INSTANCE) == TIM14) \|\| \
mbed_official	5:ac9f6c2c45e8	5031	((INSTANCE) == TIM16) \|\| \
mbed_official	5:ac9f6c2c45e8	5032	((INSTANCE) == TIM17))
mbed_official	5:ac9f6c2c45e8	5033
mbed_official	5:ac9f6c2c45e8	5034	#define IS_TIM_CC1_INSTANCE(INSTANCE)\
mbed_official	5:ac9f6c2c45e8	5035	(((INSTANCE) == TIM1) \|\| \
mbed_official	5:ac9f6c2c45e8	5036	((INSTANCE) == TIM2) \|\| \
mbed_official	5:ac9f6c2c45e8	5037	((INSTANCE) == TIM3) \|\| \
mbed_official	5:ac9f6c2c45e8	5038	((INSTANCE) == TIM14) \|\| \
mbed_official	5:ac9f6c2c45e8	5039	((INSTANCE) == TIM16) \|\| \
mbed_official	5:ac9f6c2c45e8	5040	((INSTANCE) == TIM17))
mbed_official	5:ac9f6c2c45e8	5041
mbed_official	5:ac9f6c2c45e8	5042	#define IS_TIM_CC2_INSTANCE(INSTANCE)\
mbed_official	5:ac9f6c2c45e8	5043	(((INSTANCE) == TIM1) \|\| \
mbed_official	5:ac9f6c2c45e8	5044	((INSTANCE) == TIM2) \|\| \
mbed_official	5:ac9f6c2c45e8	5045	((INSTANCE) == TIM3))
mbed_official	5:ac9f6c2c45e8	5046
mbed_official	5:ac9f6c2c45e8	5047	#define IS_TIM_CC3_INSTANCE(INSTANCE)\
mbed_official	5:ac9f6c2c45e8	5048	(((INSTANCE) == TIM1) \|\| \
mbed_official	5:ac9f6c2c45e8	5049	((INSTANCE) == TIM2) \|\| \
mbed_official	5:ac9f6c2c45e8	5050	((INSTANCE) == TIM3))
mbed_official	5:ac9f6c2c45e8	5051
mbed_official	5:ac9f6c2c45e8	5052	#define IS_TIM_CC4_INSTANCE(INSTANCE)\
mbed_official	5:ac9f6c2c45e8	5053	(((INSTANCE) == TIM1) \|\| \
mbed_official	5:ac9f6c2c45e8	5054	((INSTANCE) == TIM2) \|\| \
mbed_official	5:ac9f6c2c45e8	5055	((INSTANCE) == TIM3))
mbed_official	5:ac9f6c2c45e8	5056
mbed_official	5:ac9f6c2c45e8	5057	#define IS_TIM_CC5_INSTANCE(INSTANCE)\
mbed_official	5:ac9f6c2c45e8	5058	(((INSTANCE) == TIM1))
mbed_official	5:ac9f6c2c45e8	5059
mbed_official	5:ac9f6c2c45e8	5060	#define IS_TIM_CC6_INSTANCE(INSTANCE)\
mbed_official	5:ac9f6c2c45e8	5061	(((INSTANCE) == TIM1))
mbed_official	5:ac9f6c2c45e8	5062
mbed_official	5:ac9f6c2c45e8	5063	#define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
mbed_official	5:ac9f6c2c45e8	5064	(((INSTANCE) == TIM1) \|\| \
mbed_official	5:ac9f6c2c45e8	5065	((INSTANCE) == TIM2) \|\| \
mbed_official	5:ac9f6c2c45e8	5066	((INSTANCE) == TIM3))
mbed_official	5:ac9f6c2c45e8	5067
mbed_official	5:ac9f6c2c45e8	5068	#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
mbed_official	5:ac9f6c2c45e8	5069	(((INSTANCE) == TIM1) \|\| \
mbed_official	5:ac9f6c2c45e8	5070	((INSTANCE) == TIM2) \|\| \
mbed_official	5:ac9f6c2c45e8	5071	((INSTANCE) == TIM3))
mbed_official	5:ac9f6c2c45e8	5072
mbed_official	5:ac9f6c2c45e8	5073	#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
mbed_official	5:ac9f6c2c45e8	5074	(((INSTANCE) == TIM1) \|\| \
mbed_official	5:ac9f6c2c45e8	5075	((INSTANCE) == TIM2) \|\| \
mbed_official	5:ac9f6c2c45e8	5076	((INSTANCE) == TIM3))
mbed_official	5:ac9f6c2c45e8	5077
mbed_official	5:ac9f6c2c45e8	5078	#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
mbed_official	5:ac9f6c2c45e8	5079	(((INSTANCE) == TIM1) \|\| \
mbed_official	5:ac9f6c2c45e8	5080	((INSTANCE) == TIM2) \|\| \
mbed_official	5:ac9f6c2c45e8	5081	((INSTANCE) == TIM3))
mbed_official	5:ac9f6c2c45e8	5082
mbed_official	5:ac9f6c2c45e8	5083	#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
mbed_official	5:ac9f6c2c45e8	5084	(((INSTANCE) == TIM1) \|\| \
mbed_official	5:ac9f6c2c45e8	5085	((INSTANCE) == TIM2) \|\| \
mbed_official	5:ac9f6c2c45e8	5086	((INSTANCE) == TIM3))
mbed_official	5:ac9f6c2c45e8	5087
mbed_official	5:ac9f6c2c45e8	5088	#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
mbed_official	5:ac9f6c2c45e8	5089	(((INSTANCE) == TIM1) \|\| \
mbed_official	5:ac9f6c2c45e8	5090	((INSTANCE) == TIM2) \|\| \
mbed_official	5:ac9f6c2c45e8	5091	((INSTANCE) == TIM3))
mbed_official	5:ac9f6c2c45e8	5092
mbed_official	5:ac9f6c2c45e8	5093	#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
mbed_official	5:ac9f6c2c45e8	5094	(((INSTANCE) == TIM1) \|\| \
mbed_official	5:ac9f6c2c45e8	5095	((INSTANCE) == TIM2) \|\| \
mbed_official	5:ac9f6c2c45e8	5096	((INSTANCE) == TIM3))
mbed_official	5:ac9f6c2c45e8	5097
mbed_official	5:ac9f6c2c45e8	5098	#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
mbed_official	5:ac9f6c2c45e8	5099	(((INSTANCE) == TIM1))
mbed_official	5:ac9f6c2c45e8	5100
mbed_official	5:ac9f6c2c45e8	5101	#define IS_TIM_XOR_INSTANCE(INSTANCE)\
mbed_official	5:ac9f6c2c45e8	5102	(((INSTANCE) == TIM1) \|\| \
mbed_official	5:ac9f6c2c45e8	5103	((INSTANCE) == TIM2) \|\| \
mbed_official	5:ac9f6c2c45e8	5104	((INSTANCE) == TIM3))
mbed_official	5:ac9f6c2c45e8	5105
mbed_official	5:ac9f6c2c45e8	5106	#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
mbed_official	5:ac9f6c2c45e8	5107	(((INSTANCE) == TIM1) \|\| \
mbed_official	5:ac9f6c2c45e8	5108	((INSTANCE) == TIM2) \|\| \
mbed_official	5:ac9f6c2c45e8	5109	((INSTANCE) == TIM3))
mbed_official	5:ac9f6c2c45e8	5110
mbed_official	5:ac9f6c2c45e8	5111	#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
mbed_official	5:ac9f6c2c45e8	5112	(((INSTANCE) == TIM1) \|\| \
mbed_official	5:ac9f6c2c45e8	5113	((INSTANCE) == TIM2) \|\| \
mbed_official	5:ac9f6c2c45e8	5114	((INSTANCE) == TIM3))
mbed_official	5:ac9f6c2c45e8	5115
mbed_official	5:ac9f6c2c45e8	5116	#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\
mbed_official	5:ac9f6c2c45e8	5117	(((INSTANCE) == TIM1) \|\| \
mbed_official	5:ac9f6c2c45e8	5118	((INSTANCE) == TIM2) \|\| \
mbed_official	5:ac9f6c2c45e8	5119	((INSTANCE) == TIM3))
mbed_official	5:ac9f6c2c45e8	5120
mbed_official	5:ac9f6c2c45e8	5121	#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
mbed_official	5:ac9f6c2c45e8	5122	((INSTANCE) == TIM2)
mbed_official	5:ac9f6c2c45e8	5123
mbed_official	5:ac9f6c2c45e8	5124	#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
mbed_official	5:ac9f6c2c45e8	5125	(((INSTANCE) == TIM1) \|\| \
mbed_official	5:ac9f6c2c45e8	5126	((INSTANCE) == TIM2) \|\| \
mbed_official	5:ac9f6c2c45e8	5127	((INSTANCE) == TIM3) \|\| \
mbed_official	5:ac9f6c2c45e8	5128	((INSTANCE) == TIM16) \|\| \
mbed_official	5:ac9f6c2c45e8	5129	((INSTANCE) == TIM17))
mbed_official	5:ac9f6c2c45e8	5130
mbed_official	5:ac9f6c2c45e8	5131	#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
mbed_official	5:ac9f6c2c45e8	5132	(((INSTANCE) == TIM1) \|\| \
mbed_official	5:ac9f6c2c45e8	5133	((INSTANCE) == TIM16) \|\| \
mbed_official	5:ac9f6c2c45e8	5134	((INSTANCE) == TIM17))
mbed_official	5:ac9f6c2c45e8	5135
mbed_official	5:ac9f6c2c45e8	5136	#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
mbed_official	5:ac9f6c2c45e8	5137	((((INSTANCE) == TIM1) && \
mbed_official	5:ac9f6c2c45e8	5138	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	5:ac9f6c2c45e8	5139	((CHANNEL) == TIM_CHANNEL_2) \|\| \
mbed_official	5:ac9f6c2c45e8	5140	((CHANNEL) == TIM_CHANNEL_3) \|\| \
mbed_official	5:ac9f6c2c45e8	5141	((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official	5:ac9f6c2c45e8	5142	\|\| \
mbed_official	5:ac9f6c2c45e8	5143	(((INSTANCE) == TIM2) && \
mbed_official	5:ac9f6c2c45e8	5144	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	5:ac9f6c2c45e8	5145	((CHANNEL) == TIM_CHANNEL_2) \|\| \
mbed_official	5:ac9f6c2c45e8	5146	((CHANNEL) == TIM_CHANNEL_3) \|\| \
mbed_official	5:ac9f6c2c45e8	5147	((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official	5:ac9f6c2c45e8	5148	\|\| \
mbed_official	5:ac9f6c2c45e8	5149	(((INSTANCE) == TIM3) && \
mbed_official	5:ac9f6c2c45e8	5150	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	5:ac9f6c2c45e8	5151	((CHANNEL) == TIM_CHANNEL_2) \|\| \
mbed_official	5:ac9f6c2c45e8	5152	((CHANNEL) == TIM_CHANNEL_3) \|\| \
mbed_official	5:ac9f6c2c45e8	5153	((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official	5:ac9f6c2c45e8	5154	\|\| \
mbed_official	5:ac9f6c2c45e8	5155	(((INSTANCE) == TIM16) && \
mbed_official	5:ac9f6c2c45e8	5156	(((CHANNEL) == TIM_CHANNEL_1))) \
mbed_official	5:ac9f6c2c45e8	5157	\|\| \
mbed_official	5:ac9f6c2c45e8	5158	(((INSTANCE) == TIM17) && \
mbed_official	5:ac9f6c2c45e8	5159	(((CHANNEL) == TIM_CHANNEL_1))))
mbed_official	5:ac9f6c2c45e8	5160
mbed_official	5:ac9f6c2c45e8	5161	#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
mbed_official	5:ac9f6c2c45e8	5162	((((INSTANCE) == TIM1) && \
mbed_official	5:ac9f6c2c45e8	5163	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	5:ac9f6c2c45e8	5164	((CHANNEL) == TIM_CHANNEL_2) \|\| \
mbed_official	5:ac9f6c2c45e8	5165	((CHANNEL) == TIM_CHANNEL_3))) \
mbed_official	5:ac9f6c2c45e8	5166	\|\| \
mbed_official	5:ac9f6c2c45e8	5167	(((INSTANCE) == TIM16) && \
mbed_official	5:ac9f6c2c45e8	5168	((CHANNEL) == TIM_CHANNEL_1)) \
mbed_official	5:ac9f6c2c45e8	5169	\|\| \
mbed_official	5:ac9f6c2c45e8	5170	(((INSTANCE) == TIM17) && \
mbed_official	5:ac9f6c2c45e8	5171	((CHANNEL) == TIM_CHANNEL_1)))
mbed_official	5:ac9f6c2c45e8	5172
mbed_official	5:ac9f6c2c45e8	5173	#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
mbed_official	5:ac9f6c2c45e8	5174	(((INSTANCE) == TIM1) \|\| \
mbed_official	5:ac9f6c2c45e8	5175	((INSTANCE) == TIM2) \|\| \
mbed_official	5:ac9f6c2c45e8	5176	((INSTANCE) == TIM3))
mbed_official	5:ac9f6c2c45e8	5177
mbed_official	5:ac9f6c2c45e8	5178	#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
mbed_official	5:ac9f6c2c45e8	5179	(((INSTANCE) == TIM1) \|\| \
mbed_official	5:ac9f6c2c45e8	5180	((INSTANCE) == TIM16) \|\| \
mbed_official	5:ac9f6c2c45e8	5181	((INSTANCE) == TIM17))
mbed_official	5:ac9f6c2c45e8	5182
mbed_official	5:ac9f6c2c45e8	5183	#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
mbed_official	5:ac9f6c2c45e8	5184	(((INSTANCE) == TIM1) \|\| \
mbed_official	5:ac9f6c2c45e8	5185	((INSTANCE) == TIM2) \|\| \
mbed_official	5:ac9f6c2c45e8	5186	((INSTANCE) == TIM3) \|\| \
mbed_official	5:ac9f6c2c45e8	5187	((INSTANCE) == TIM14) \|\| \
mbed_official	5:ac9f6c2c45e8	5188	((INSTANCE) == TIM16) \|\| \
mbed_official	5:ac9f6c2c45e8	5189	((INSTANCE) == TIM17))
mbed_official	5:ac9f6c2c45e8	5190
mbed_official	5:ac9f6c2c45e8	5191	#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
mbed_official	5:ac9f6c2c45e8	5192	(((INSTANCE) == TIM1))
mbed_official	5:ac9f6c2c45e8	5193
mbed_official	5:ac9f6c2c45e8	5194	#define IS_TIM_TRGO2_INSTANCE(INSTANCE)\
mbed_official	5:ac9f6c2c45e8	5195	(((INSTANCE) == TIM1))
mbed_official	5:ac9f6c2c45e8	5196
mbed_official	5:ac9f6c2c45e8	5197	#define IS_TIM_DMA_INSTANCE(INSTANCE)\
mbed_official	5:ac9f6c2c45e8	5198	(((INSTANCE) == TIM1) \|\| \
mbed_official	5:ac9f6c2c45e8	5199	((INSTANCE) == TIM2) \|\| \
mbed_official	5:ac9f6c2c45e8	5200	((INSTANCE) == TIM3) \|\| \
mbed_official	5:ac9f6c2c45e8	5201	((INSTANCE) == TIM16) \|\| \
mbed_official	5:ac9f6c2c45e8	5202	((INSTANCE) == TIM17))
mbed_official	5:ac9f6c2c45e8	5203
mbed_official	5:ac9f6c2c45e8	5204	#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
mbed_official	5:ac9f6c2c45e8	5205	(((INSTANCE) == TIM1) \|\| \
mbed_official	5:ac9f6c2c45e8	5206	((INSTANCE) == TIM2) \|\| \
mbed_official	5:ac9f6c2c45e8	5207	((INSTANCE) == TIM3) \|\| \
mbed_official	5:ac9f6c2c45e8	5208	((INSTANCE) == TIM16) \|\| \
mbed_official	5:ac9f6c2c45e8	5209	((INSTANCE) == TIM17))
mbed_official	5:ac9f6c2c45e8	5210
mbed_official	5:ac9f6c2c45e8	5211	#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
mbed_official	5:ac9f6c2c45e8	5212	(((INSTANCE) == TIM1) \|\| \
mbed_official	5:ac9f6c2c45e8	5213	((INSTANCE) == TIM16) \|\| \
mbed_official	5:ac9f6c2c45e8	5214	((INSTANCE) == TIM17))
mbed_official	5:ac9f6c2c45e8	5215
mbed_official	5:ac9f6c2c45e8	5216	#define IS_TIM_REMAP_INSTANCE(INSTANCE)\
mbed_official	5:ac9f6c2c45e8	5217	(((INSTANCE) == TIM1) \|\| \
mbed_official	5:ac9f6c2c45e8	5218	((INSTANCE) == TIM14))
mbed_official	5:ac9f6c2c45e8	5219
mbed_official	5:ac9f6c2c45e8	5220	/**************************** TSC Instances *******************************/
mbed_official	5:ac9f6c2c45e8	5221	#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
mbed_official	5:ac9f6c2c45e8	5222
mbed_official	5:ac9f6c2c45e8	5223	/********************* UART Instances : IRDA mode *************************/
mbed_official	5:ac9f6c2c45e8	5224	#define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
mbed_official	5:ac9f6c2c45e8	5225
mbed_official	5:ac9f6c2c45e8	5226	/******************* UART Instances : Smard card mode *********************/
mbed_official	5:ac9f6c2c45e8	5227	#define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
mbed_official	5:ac9f6c2c45e8	5228
mbed_official	5:ac9f6c2c45e8	5229	/****************** USART Instances : Synchronous mode ********************/
mbed_official	5:ac9f6c2c45e8	5230	#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
mbed_official	5:ac9f6c2c45e8	5231	((INSTANCE) == USART2))
mbed_official	5:ac9f6c2c45e8	5232
mbed_official	5:ac9f6c2c45e8	5233	/****************** USART Instances : auto Baud rate detection ************/
mbed_official	5:ac9f6c2c45e8	5234	#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
mbed_official	5:ac9f6c2c45e8	5235
mbed_official	5:ac9f6c2c45e8	5236	/****************** UART Instances : Asynchronous mode ********************/
mbed_official	5:ac9f6c2c45e8	5237	#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
mbed_official	5:ac9f6c2c45e8	5238	((INSTANCE) == USART2))
mbed_official	5:ac9f6c2c45e8	5239
mbed_official	5:ac9f6c2c45e8	5240	/****************** UART Instances : Half-Duplex mode ********************/
mbed_official	5:ac9f6c2c45e8	5241	#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
mbed_official	5:ac9f6c2c45e8	5242	((INSTANCE) == USART2))
mbed_official	5:ac9f6c2c45e8	5243
mbed_official	5:ac9f6c2c45e8	5244	/**************** UART Instances : Hardware Flow control ******************/
mbed_official	5:ac9f6c2c45e8	5245	#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
mbed_official	5:ac9f6c2c45e8	5246	((INSTANCE) == USART2))
mbed_official	5:ac9f6c2c45e8	5247
mbed_official	5:ac9f6c2c45e8	5248	/**************** UART Instances : LIN mode ******************/
mbed_official	5:ac9f6c2c45e8	5249	#define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
mbed_official	5:ac9f6c2c45e8	5250
mbed_official	5:ac9f6c2c45e8	5251	/**************** UART Instances : wakeup from stop mode ******************/
mbed_official	5:ac9f6c2c45e8	5252	#define IS_UART_WAKEUP_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
mbed_official	5:ac9f6c2c45e8	5253
mbed_official	5:ac9f6c2c45e8	5254	/**************** UART Instances : Auto Baud Rate detection ******************/
mbed_official	5:ac9f6c2c45e8	5255	#define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
mbed_official	5:ac9f6c2c45e8	5256
mbed_official	5:ac9f6c2c45e8	5257	/**************** UART Instances : Driver enable detection ******************/
mbed_official	5:ac9f6c2c45e8	5258	#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
mbed_official	5:ac9f6c2c45e8	5259	((INSTANCE) == USART2))
mbed_official	5:ac9f6c2c45e8	5260	/**************************** USB Instances ******************************/
mbed_official	5:ac9f6c2c45e8	5261	#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
mbed_official	5:ac9f6c2c45e8	5262
mbed_official	5:ac9f6c2c45e8	5263	/**************************** WWDG Instances ******************************/
mbed_official	5:ac9f6c2c45e8	5264	#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
mbed_official	5:ac9f6c2c45e8	5265
mbed_official	5:ac9f6c2c45e8	5266	/**
mbed_official	5:ac9f6c2c45e8	5267	* @}
mbed_official	5:ac9f6c2c45e8	5268	*/
mbed_official	5:ac9f6c2c45e8	5269
mbed_official	5:ac9f6c2c45e8	5270
mbed_official	5:ac9f6c2c45e8	5271	/******************************************************************************/
mbed_official	5:ac9f6c2c45e8	5272	/* For a painless codes migration between the STM32F0xx device product */
mbed_official	5:ac9f6c2c45e8	5273	/* lines, the aliases defined below are put in place to overcome the */
mbed_official	5:ac9f6c2c45e8	5274	/* differences in the interrupt handlers and IRQn definitions. */
mbed_official	5:ac9f6c2c45e8	5275	/* No need to update developed interrupt code when moving across */
mbed_official	5:ac9f6c2c45e8	5276	/* product lines within the same STM32F0 Family */
mbed_official	5:ac9f6c2c45e8	5277	/******************************************************************************/
mbed_official	5:ac9f6c2c45e8	5278
mbed_official	5:ac9f6c2c45e8	5279	/* Aliases for __IRQn */
mbed_official	5:ac9f6c2c45e8	5280	#define PVD_IRQn PVD_VDDIO2_IRQn
mbed_official	5:ac9f6c2c45e8	5281	#define VDDIO2_IRQn PVD_VDDIO2_IRQn
mbed_official	5:ac9f6c2c45e8	5282	#define RCC_IRQn RCC_CRS_IRQn
mbed_official	5:ac9f6c2c45e8	5283	#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
mbed_official	5:ac9f6c2c45e8	5284	#define ADC1_COMP_IRQn ADC1_IRQn
mbed_official	5:ac9f6c2c45e8	5285
mbed_official	5:ac9f6c2c45e8	5286	/* Aliases for __IRQHandler */
mbed_official	5:ac9f6c2c45e8	5287	#define PVD_IRQHandler PVD_VDDIO2_IRQHandler
mbed_official	5:ac9f6c2c45e8	5288	#define VDDIO2_IRQHandler PVD_VDDIO2_IRQHandler
mbed_official	5:ac9f6c2c45e8	5289	#define RCC_IRQHandler RCC_CRS_IRQHandler
mbed_official	5:ac9f6c2c45e8	5290	#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
mbed_official	5:ac9f6c2c45e8	5291	#define ADC1_COMP_IRQHandler ADC1_IRQHandler
mbed_official	5:ac9f6c2c45e8	5292
mbed_official	5:ac9f6c2c45e8	5293	#ifdef __cplusplus
mbed_official	5:ac9f6c2c45e8	5294	}
mbed_official	5:ac9f6c2c45e8	5295	#endif /* __cplusplus */
mbed_official	5:ac9f6c2c45e8	5296
mbed_official	5:ac9f6c2c45e8	5297	#endif /* __STM32F042x6_H */
mbed_official	5:ac9f6c2c45e8	5298
mbed_official	5:ac9f6c2c45e8	5299	/**
mbed_official	5:ac9f6c2c45e8	5300	* @}
mbed_official	5:ac9f6c2c45e8	5301	*/
mbed_official	5:ac9f6c2c45e8	5302
mbed_official	5:ac9f6c2c45e8	5303	/**
mbed_official	5:ac9f6c2c45e8	5304	* @}
mbed_official	5:ac9f6c2c45e8	5305	*/
mbed_official	5:ac9f6c2c45e8	5306
mbed_official	5:ac9f6c2c45e8	5307	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/