mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_NORDIC/TARGET_NRF5_SDK13/us_ticker.c@163:74e0ce7f98e8, 2017-04-28 (annotated)

Committer:
Anna Bridge
Date:
Fri Apr 28 14:04:18 2017 +0100
Revision:
163:74e0ce7f98e8
Parent:
162:e13f6fdb2ac4 
This updates the lib to the mbed lib v141

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 162:e13f6fdb2ac4 1 /*
<> 162:e13f6fdb2ac4 2 * Copyright (c) 2013 Nordic Semiconductor ASA
<> 162:e13f6fdb2ac4 3 * All rights reserved.
<> 162:e13f6fdb2ac4 4 *
<> 162:e13f6fdb2ac4 5 * Redistribution and use in source and binary forms, with or without modification,
<> 162:e13f6fdb2ac4 6 * are permitted provided that the following conditions are met:
<> 162:e13f6fdb2ac4 7 *
<> 162:e13f6fdb2ac4 8 * 1. Redistributions of source code must retain the above copyright notice, this list
<> 162:e13f6fdb2ac4 9 * of conditions and the following disclaimer.
<> 162:e13f6fdb2ac4 10 *
<> 162:e13f6fdb2ac4 11 * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
<> 162:e13f6fdb2ac4 12 * integrated circuit in a product or a software update for such product, must reproduce
<> 162:e13f6fdb2ac4 13 * the above copyright notice, this list of conditions and the following disclaimer in
<> 162:e13f6fdb2ac4 14 * the documentation and/or other materials provided with the distribution.
<> 162:e13f6fdb2ac4 15 *
<> 162:e13f6fdb2ac4 16 * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
<> 162:e13f6fdb2ac4 17 * used to endorse or promote products derived from this software without specific prior
<> 162:e13f6fdb2ac4 18 * written permission.
<> 162:e13f6fdb2ac4 19 *
<> 162:e13f6fdb2ac4 20 * 4. This software, with or without modification, must only be used with a
<> 162:e13f6fdb2ac4 21 * Nordic Semiconductor ASA integrated circuit.
<> 162:e13f6fdb2ac4 22 *
<> 162:e13f6fdb2ac4 23 * 5. Any software provided in binary or object form under this license must not be reverse
<> 162:e13f6fdb2ac4 24 * engineered, decompiled, modified and/or disassembled.
<> 162:e13f6fdb2ac4 25 *
<> 162:e13f6fdb2ac4 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 162:e13f6fdb2ac4 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 162:e13f6fdb2ac4 28 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 162:e13f6fdb2ac4 29 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 162:e13f6fdb2ac4 30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 162:e13f6fdb2ac4 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 162:e13f6fdb2ac4 32 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 162:e13f6fdb2ac4 33 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 162:e13f6fdb2ac4 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 162:e13f6fdb2ac4 35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 162:e13f6fdb2ac4 36 *
<> 162:e13f6fdb2ac4 37 */
<> 162:e13f6fdb2ac4 38
<> 162:e13f6fdb2ac4 39 #include "us_ticker_api.h"
<> 162:e13f6fdb2ac4 40 #include "common_rtc.h"
<> 162:e13f6fdb2ac4 41 #include "app_util.h"
<> 162:e13f6fdb2ac4 42 #include "nrf_drv_common.h"
<> 162:e13f6fdb2ac4 43 #include "lp_ticker_api.h"
<> 162:e13f6fdb2ac4 44 #include "mbed_critical.h"
<> 162:e13f6fdb2ac4 45
<> 162:e13f6fdb2ac4 46 #if defined(NRF52_ERRATA_20)
<> 162:e13f6fdb2ac4 47 #include "softdevice_handler.h"
<> 162:e13f6fdb2ac4 48 #endif
<> 162:e13f6fdb2ac4 49
<> 162:e13f6fdb2ac4 50 //------------------------------------------------------------------------------
<> 162:e13f6fdb2ac4 51 // Common stuff used also by lp_ticker and rtc_api (see "common_rtc.h").
<> 162:e13f6fdb2ac4 52 //
<> 162:e13f6fdb2ac4 53 #include "app_util_platform.h"
<> 162:e13f6fdb2ac4 54
<> 162:e13f6fdb2ac4 55 bool m_common_rtc_enabled = false;
<> 162:e13f6fdb2ac4 56 uint32_t volatile m_common_rtc_overflows = 0;
<> 162:e13f6fdb2ac4 57
Anna Bridge 163:74e0ce7f98e8 58 __STATIC_INLINE void rtc_ovf_event_check(void)
Anna Bridge 163:74e0ce7f98e8 59 {
Anna Bridge 163:74e0ce7f98e8 60 if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW)) {
Anna Bridge 163:74e0ce7f98e8 61 nrf_rtc_event_clear(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW);
Anna Bridge 163:74e0ce7f98e8 62 // Don't disable this event. It shall occur periodically.
Anna Bridge 163:74e0ce7f98e8 63
Anna Bridge 163:74e0ce7f98e8 64 ++m_common_rtc_overflows;
Anna Bridge 163:74e0ce7f98e8 65 }
Anna Bridge 163:74e0ce7f98e8 66 }
Anna Bridge 163:74e0ce7f98e8 67
<> 162:e13f6fdb2ac4 68 #if defined(TARGET_MCU_NRF51822)
<> 162:e13f6fdb2ac4 69 void common_rtc_irq_handler(void)
<> 162:e13f6fdb2ac4 70 #else
<> 162:e13f6fdb2ac4 71 void COMMON_RTC_IRQ_HANDLER(void)
<> 162:e13f6fdb2ac4 72 #endif
<> 162:e13f6fdb2ac4 73 {
Anna Bridge 163:74e0ce7f98e8 74
Anna Bridge 163:74e0ce7f98e8 75 rtc_ovf_event_check();
Anna Bridge 163:74e0ce7f98e8 76
Anna Bridge 163:74e0ce7f98e8 77 if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, US_TICKER_EVENT)) {
<> 162:e13f6fdb2ac4 78 us_ticker_irq_handler();
<> 162:e13f6fdb2ac4 79 }
<> 162:e13f6fdb2ac4 80
<> 162:e13f6fdb2ac4 81 #if DEVICE_LOWPOWERTIMER
Anna Bridge 163:74e0ce7f98e8 82 if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, LP_TICKER_EVENT)) {
<> 162:e13f6fdb2ac4 83
<> 162:e13f6fdb2ac4 84 lp_ticker_irq_handler();
<> 162:e13f6fdb2ac4 85 }
<> 162:e13f6fdb2ac4 86 #endif
<> 162:e13f6fdb2ac4 87
<> 162:e13f6fdb2ac4 88 }
<> 162:e13f6fdb2ac4 89
<> 162:e13f6fdb2ac4 90 // Function for fix errata 20: RTC Register values are invalid
<> 162:e13f6fdb2ac4 91 __STATIC_INLINE void errata_20(void)
<> 162:e13f6fdb2ac4 92 {
<> 162:e13f6fdb2ac4 93 #if defined(NRF52_ERRATA_20)
<> 162:e13f6fdb2ac4 94 if (!softdevice_handler_is_enabled())
<> 162:e13f6fdb2ac4 95 {
<> 162:e13f6fdb2ac4 96 NRF_CLOCK->EVENTS_LFCLKSTARTED = 0;
<> 162:e13f6fdb2ac4 97 NRF_CLOCK->TASKS_LFCLKSTART = 1;
<> 162:e13f6fdb2ac4 98
<> 162:e13f6fdb2ac4 99 while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0)
<> 162:e13f6fdb2ac4 100 {
<> 162:e13f6fdb2ac4 101 }
<> 162:e13f6fdb2ac4 102 }
<> 162:e13f6fdb2ac4 103 NRF_RTC1->TASKS_STOP = 0;
<> 162:e13f6fdb2ac4 104 #endif
<> 162:e13f6fdb2ac4 105 }
<> 162:e13f6fdb2ac4 106
<> 162:e13f6fdb2ac4 107 #if (defined (__ICCARM__)) && defined(TARGET_MCU_NRF51822)//IAR
<> 162:e13f6fdb2ac4 108 __stackless __task
<> 162:e13f6fdb2ac4 109 #endif
<> 162:e13f6fdb2ac4 110 void RTC1_IRQHandler(void);
<> 162:e13f6fdb2ac4 111
<> 162:e13f6fdb2ac4 112 void common_rtc_init(void)
<> 162:e13f6fdb2ac4 113 {
Anna Bridge 163:74e0ce7f98e8 114 if (m_common_rtc_enabled) {
<> 162:e13f6fdb2ac4 115 return;
<> 162:e13f6fdb2ac4 116 }
<> 162:e13f6fdb2ac4 117
<> 162:e13f6fdb2ac4 118 errata_20();
<> 162:e13f6fdb2ac4 119
<> 162:e13f6fdb2ac4 120 NVIC_SetVector(RTC1_IRQn, (uint32_t)RTC1_IRQHandler);
<> 162:e13f6fdb2ac4 121
<> 162:e13f6fdb2ac4 122 // RTC is driven by the low frequency (32.768 kHz) clock, a proper request
<> 162:e13f6fdb2ac4 123 // must be made to have it running.
<> 162:e13f6fdb2ac4 124 // Currently this clock is started in 'SystemInit' (see "system_nrf51.c"
<> 162:e13f6fdb2ac4 125 // or "system_nrf52.c", respectively).
<> 162:e13f6fdb2ac4 126
<> 162:e13f6fdb2ac4 127 nrf_rtc_prescaler_set(COMMON_RTC_INSTANCE, 0);
<> 162:e13f6fdb2ac4 128
<> 162:e13f6fdb2ac4 129 nrf_rtc_event_clear(COMMON_RTC_INSTANCE, US_TICKER_EVENT);
<> 162:e13f6fdb2ac4 130 #if defined(TARGET_MCU_NRF51822)
<> 162:e13f6fdb2ac4 131 nrf_rtc_event_clear(COMMON_RTC_INSTANCE, OS_TICK_EVENT);
<> 162:e13f6fdb2ac4 132 #endif
<> 162:e13f6fdb2ac4 133 #if DEVICE_LOWPOWERTIMER
<> 162:e13f6fdb2ac4 134 nrf_rtc_event_clear(COMMON_RTC_INSTANCE, LP_TICKER_EVENT);
<> 162:e13f6fdb2ac4 135 #endif
<> 162:e13f6fdb2ac4 136 nrf_rtc_event_clear(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW);
<> 162:e13f6fdb2ac4 137
<> 162:e13f6fdb2ac4 138 // Interrupts on all related events are enabled permanently. Particular
<> 162:e13f6fdb2ac4 139 // events will be enabled or disabled as needed (such approach is more
<> 162:e13f6fdb2ac4 140 // energy efficient).
<> 162:e13f6fdb2ac4 141 nrf_rtc_int_enable(COMMON_RTC_INSTANCE,
<> 162:e13f6fdb2ac4 142 #if DEVICE_LOWPOWERTIMER
<> 162:e13f6fdb2ac4 143 LP_TICKER_INT_MASK |
<> 162:e13f6fdb2ac4 144 #endif
<> 162:e13f6fdb2ac4 145 US_TICKER_INT_MASK |
<> 162:e13f6fdb2ac4 146 NRF_RTC_INT_OVERFLOW_MASK);
<> 162:e13f6fdb2ac4 147
<> 162:e13f6fdb2ac4 148 // This event is enabled permanently, since overflow indications are needed
<> 162:e13f6fdb2ac4 149 // continuously.
<> 162:e13f6fdb2ac4 150 nrf_rtc_event_enable(COMMON_RTC_INSTANCE, NRF_RTC_INT_OVERFLOW_MASK);
<> 162:e13f6fdb2ac4 151 // All other relevant events are initially disabled.
<> 162:e13f6fdb2ac4 152 nrf_rtc_event_disable(COMMON_RTC_INSTANCE,
<> 162:e13f6fdb2ac4 153 #if defined(TARGET_MCU_NRF51822)
<> 162:e13f6fdb2ac4 154 OS_TICK_INT_MASK |
<> 162:e13f6fdb2ac4 155 #endif
<> 162:e13f6fdb2ac4 156 #if DEVICE_LOWPOWERTIMER
<> 162:e13f6fdb2ac4 157 LP_TICKER_INT_MASK |
<> 162:e13f6fdb2ac4 158 #endif
<> 162:e13f6fdb2ac4 159 US_TICKER_INT_MASK);
<> 162:e13f6fdb2ac4 160
<> 162:e13f6fdb2ac4 161 nrf_drv_common_irq_enable(nrf_drv_get_IRQn(COMMON_RTC_INSTANCE),
<> 162:e13f6fdb2ac4 162 #ifdef NRF51
<> 162:e13f6fdb2ac4 163 APP_IRQ_PRIORITY_LOW
<> 162:e13f6fdb2ac4 164 #elif defined(NRF52) || defined(NRF52840_XXAA)
<> 162:e13f6fdb2ac4 165 APP_IRQ_PRIORITY_LOWEST
<> 162:e13f6fdb2ac4 166 #endif
<> 162:e13f6fdb2ac4 167 );
<> 162:e13f6fdb2ac4 168
<> 162:e13f6fdb2ac4 169 nrf_rtc_task_trigger(COMMON_RTC_INSTANCE, NRF_RTC_TASK_START);
<> 162:e13f6fdb2ac4 170
<> 162:e13f6fdb2ac4 171 m_common_rtc_enabled = true;
<> 162:e13f6fdb2ac4 172 }
<> 162:e13f6fdb2ac4 173
Anna Bridge 163:74e0ce7f98e8 174 __STATIC_INLINE void rtc_ovf_event_safe_check(void)
Anna Bridge 163:74e0ce7f98e8 175 {
Anna Bridge 163:74e0ce7f98e8 176 core_util_critical_section_enter();
Anna Bridge 163:74e0ce7f98e8 177
Anna Bridge 163:74e0ce7f98e8 178 rtc_ovf_event_check();
Anna Bridge 163:74e0ce7f98e8 179
Anna Bridge 163:74e0ce7f98e8 180 core_util_critical_section_exit();
Anna Bridge 163:74e0ce7f98e8 181 }
Anna Bridge 163:74e0ce7f98e8 182
Anna Bridge 163:74e0ce7f98e8 183
<> 162:e13f6fdb2ac4 184 uint32_t common_rtc_32bit_ticks_get(void)
<> 162:e13f6fdb2ac4 185 {
Anna Bridge 163:74e0ce7f98e8 186 uint32_t ticks;
Anna Bridge 163:74e0ce7f98e8 187 uint32_t prev_overflows;
Anna Bridge 163:74e0ce7f98e8 188
Anna Bridge 163:74e0ce7f98e8 189 do {
Anna Bridge 163:74e0ce7f98e8 190 prev_overflows = m_common_rtc_overflows;
Anna Bridge 163:74e0ce7f98e8 191
Anna Bridge 163:74e0ce7f98e8 192 ticks = nrf_rtc_counter_get(COMMON_RTC_INSTANCE);
Anna Bridge 163:74e0ce7f98e8 193 // The counter used for time measurements is less than 32 bit wide,
Anna Bridge 163:74e0ce7f98e8 194 // so its value is complemented with the number of registered overflows
Anna Bridge 163:74e0ce7f98e8 195 // of the counter.
Anna Bridge 163:74e0ce7f98e8 196 ticks += (m_common_rtc_overflows << RTC_COUNTER_BITS);
Anna Bridge 163:74e0ce7f98e8 197
Anna Bridge 163:74e0ce7f98e8 198 // Check in case that OVF occurred during execution of a RTC handler (apply if call was from RTC handler)
Anna Bridge 163:74e0ce7f98e8 199 // m_common_rtc_overflows might been updated in this call.
Anna Bridge 163:74e0ce7f98e8 200 rtc_ovf_event_safe_check();
Anna Bridge 163:74e0ce7f98e8 201
Anna Bridge 163:74e0ce7f98e8 202 // If call was made from a low priority level m_common_rtc_overflows might have been updated in RTC handler.
Anna Bridge 163:74e0ce7f98e8 203 } while (m_common_rtc_overflows != prev_overflows);
Anna Bridge 163:74e0ce7f98e8 204
<> 162:e13f6fdb2ac4 205 return ticks;
<> 162:e13f6fdb2ac4 206 }
<> 162:e13f6fdb2ac4 207
<> 162:e13f6fdb2ac4 208 uint64_t common_rtc_64bit_us_get(void)
<> 162:e13f6fdb2ac4 209 {
<> 162:e13f6fdb2ac4 210 uint32_t ticks = common_rtc_32bit_ticks_get();
<> 162:e13f6fdb2ac4 211 // [ticks -> microseconds]
<> 162:e13f6fdb2ac4 212 return ROUNDED_DIV(((uint64_t)ticks) * 1000000, RTC_INPUT_FREQ);
<> 162:e13f6fdb2ac4 213 }
<> 162:e13f6fdb2ac4 214
<> 162:e13f6fdb2ac4 215 void common_rtc_set_interrupt(uint32_t us_timestamp, uint32_t cc_channel,
<> 162:e13f6fdb2ac4 216 uint32_t int_mask)
<> 162:e13f6fdb2ac4 217 {
<> 162:e13f6fdb2ac4 218 // The internal counter is clocked with a frequency that cannot be easily
<> 162:e13f6fdb2ac4 219 // multiplied to 1 MHz, therefore besides the translation of values
<> 162:e13f6fdb2ac4 220 // (microsecond <-> ticks) a special care of overflows handling must be
<> 162:e13f6fdb2ac4 221 // taken. Here the 32-bit timestamp value is complemented with information
<> 162:e13f6fdb2ac4 222 // about current the system up time of (ticks + number of overflows of tick
<> 162:e13f6fdb2ac4 223 // counter on upper bits, converted to microseconds), and such 64-bit value
<> 162:e13f6fdb2ac4 224 // is then translated to counter ticks. Finally, the lower 24 bits of thus
<> 162:e13f6fdb2ac4 225 // calculated value is written to the counter compare register to prepare
<> 162:e13f6fdb2ac4 226 // the interrupt generation.
<> 162:e13f6fdb2ac4 227 uint64_t current_time64 = common_rtc_64bit_us_get();
<> 162:e13f6fdb2ac4 228 // [add upper 32 bits from the current time to the timestamp value]
<> 162:e13f6fdb2ac4 229 uint64_t timestamp64 = us_timestamp +
Anna Bridge 163:74e0ce7f98e8 230 (current_time64 & ~(uint64_t)0xFFFFFFFF);
<> 162:e13f6fdb2ac4 231 // [if the original timestamp value happens to be after the 32 bit counter
<> 162:e13f6fdb2ac4 232 // of microsends overflows, correct the upper 32 bits accordingly]
Anna Bridge 163:74e0ce7f98e8 233 if (us_timestamp < (uint32_t)(current_time64 & 0xFFFFFFFF)) {
<> 162:e13f6fdb2ac4 234 timestamp64 += ((uint64_t)1 << 32);
<> 162:e13f6fdb2ac4 235 }
<> 162:e13f6fdb2ac4 236 // [microseconds -> ticks, always round the result up to avoid too early
<> 162:e13f6fdb2ac4 237 // interrupt generation]
<> 162:e13f6fdb2ac4 238 uint32_t compare_value =
<> 162:e13f6fdb2ac4 239 (uint32_t)CEIL_DIV((timestamp64) * RTC_INPUT_FREQ, 1000000);
<> 162:e13f6fdb2ac4 240
Anna Bridge 163:74e0ce7f98e8 241 core_util_critical_section_enter();
<> 162:e13f6fdb2ac4 242 // The COMPARE event occurs when the value in compare register is N and
<> 162:e13f6fdb2ac4 243 // the counter value changes from N-1 to N. Therefore, the minimal safe
<> 162:e13f6fdb2ac4 244 // difference between the compare value to be set and the current counter
<> 162:e13f6fdb2ac4 245 // value is 2 ticks. This guarantees that the compare trigger is properly
<> 162:e13f6fdb2ac4 246 // setup before the compare condition occurs.
<> 162:e13f6fdb2ac4 247 uint32_t closest_safe_compare = common_rtc_32bit_ticks_get() + 2;
Anna Bridge 163:74e0ce7f98e8 248 if ((int)(compare_value - closest_safe_compare) <= 0) {
<> 162:e13f6fdb2ac4 249 compare_value = closest_safe_compare;
<> 162:e13f6fdb2ac4 250 }
<> 162:e13f6fdb2ac4 251
<> 162:e13f6fdb2ac4 252 nrf_rtc_cc_set(COMMON_RTC_INSTANCE, cc_channel, RTC_WRAP(compare_value));
<> 162:e13f6fdb2ac4 253 nrf_rtc_event_enable(COMMON_RTC_INSTANCE, int_mask);
Anna Bridge 163:74e0ce7f98e8 254 core_util_critical_section_exit();
<> 162:e13f6fdb2ac4 255 }
<> 162:e13f6fdb2ac4 256 //------------------------------------------------------------------------------
<> 162:e13f6fdb2ac4 257
<> 162:e13f6fdb2ac4 258
<> 162:e13f6fdb2ac4 259 void us_ticker_init(void)
<> 162:e13f6fdb2ac4 260 {
<> 162:e13f6fdb2ac4 261 common_rtc_init();
<> 162:e13f6fdb2ac4 262 }
<> 162:e13f6fdb2ac4 263
<> 162:e13f6fdb2ac4 264 uint32_t us_ticker_read()
<> 162:e13f6fdb2ac4 265 {
<> 162:e13f6fdb2ac4 266 us_ticker_init();
<> 162:e13f6fdb2ac4 267 return (uint32_t)common_rtc_64bit_us_get();
<> 162:e13f6fdb2ac4 268 }
<> 162:e13f6fdb2ac4 269
<> 162:e13f6fdb2ac4 270 void us_ticker_set_interrupt(timestamp_t timestamp)
<> 162:e13f6fdb2ac4 271 {
<> 162:e13f6fdb2ac4 272 common_rtc_set_interrupt(timestamp,
<> 162:e13f6fdb2ac4 273 US_TICKER_CC_CHANNEL, US_TICKER_INT_MASK);
<> 162:e13f6fdb2ac4 274 }
<> 162:e13f6fdb2ac4 275
<> 162:e13f6fdb2ac4 276 void us_ticker_disable_interrupt(void)
<> 162:e13f6fdb2ac4 277 {
<> 162:e13f6fdb2ac4 278 nrf_rtc_event_disable(COMMON_RTC_INSTANCE, US_TICKER_INT_MASK);
<> 162:e13f6fdb2ac4 279 }
<> 162:e13f6fdb2ac4 280
<> 162:e13f6fdb2ac4 281 void us_ticker_clear_interrupt(void)
<> 162:e13f6fdb2ac4 282 {
<> 162:e13f6fdb2ac4 283 nrf_rtc_event_clear(COMMON_RTC_INSTANCE, US_TICKER_EVENT);
<> 162:e13f6fdb2ac4 284 }
<> 162:e13f6fdb2ac4 285
<> 162:e13f6fdb2ac4 286
<> 162:e13f6fdb2ac4 287 // Since there is no SysTick on NRF51, the RTC1 channel 1 is used as an
<> 162:e13f6fdb2ac4 288 // alternative source of RTOS ticks.
<> 162:e13f6fdb2ac4 289 #if defined(TARGET_MCU_NRF51822)
<> 162:e13f6fdb2ac4 290
<> 162:e13f6fdb2ac4 291 #include "mbed_toolchain.h"
<> 162:e13f6fdb2ac4 292
<> 162:e13f6fdb2ac4 293
<> 162:e13f6fdb2ac4 294 #define MAX_RTC_COUNTER_VAL ((1uL << RTC_COUNTER_BITS) - 1)
<> 162:e13f6fdb2ac4 295
<> 162:e13f6fdb2ac4 296 /**
<> 162:e13f6fdb2ac4 297 * The value previously set in the capture compare register of channel 1
<> 162:e13f6fdb2ac4 298 */
<> 162:e13f6fdb2ac4 299 static uint32_t previous_tick_cc_value = 0;
<> 162:e13f6fdb2ac4 300
<> 162:e13f6fdb2ac4 301 /*
<> 162:e13f6fdb2ac4 302 RTX provide the following definitions which are used by the tick code:
<> 162:e13f6fdb2ac4 303 * os_trv: The number (minus 1) of clock cycle between two tick.
<> 162:e13f6fdb2ac4 304 * os_clockrate: Time duration between two ticks (in us).
<> 162:e13f6fdb2ac4 305 * OS_Tick_Handler: The function which handle a tick event.
<> 162:e13f6fdb2ac4 306 This function is special because it never returns.
<> 162:e13f6fdb2ac4 307 Those definitions are used by the code which handle the os tick.
<> 162:e13f6fdb2ac4 308 To allow compilation of us_ticker programs without RTOS, those symbols are
<> 162:e13f6fdb2ac4 309 exported from this module as weak ones.
<> 162:e13f6fdb2ac4 310 */
<> 162:e13f6fdb2ac4 311 MBED_WEAK uint32_t const os_trv;
<> 162:e13f6fdb2ac4 312 MBED_WEAK uint32_t const os_clockrate;
Anna Bridge 163:74e0ce7f98e8 313 MBED_WEAK void OS_Tick_Handler(void)
<> 162:e13f6fdb2ac4 314 {
<> 162:e13f6fdb2ac4 315 }
<> 162:e13f6fdb2ac4 316
<> 162:e13f6fdb2ac4 317
<> 162:e13f6fdb2ac4 318 #if defined (__CC_ARM) /* ARMCC Compiler */
<> 162:e13f6fdb2ac4 319
<> 162:e13f6fdb2ac4 320 __asm void COMMON_RTC_IRQ_HANDLER(void)
<> 162:e13f6fdb2ac4 321 {
<> 162:e13f6fdb2ac4 322 IMPORT OS_Tick_Handler
<> 162:e13f6fdb2ac4 323 IMPORT common_rtc_irq_handler
<> 162:e13f6fdb2ac4 324
<> 162:e13f6fdb2ac4 325 /**
<> 162:e13f6fdb2ac4 326 * Chanel 1 of RTC1 is used by RTX as a systick.
<> 162:e13f6fdb2ac4 327 * If the compare event on channel 1 is set, then branch to OS_Tick_Handler.
<> 162:e13f6fdb2ac4 328 * Otherwise, just execute common_rtc_irq_handler.
<> 162:e13f6fdb2ac4 329 * This function has to be written in assembly and tagged as naked because OS_Tick_Handler
<> 162:e13f6fdb2ac4 330 * will never return.
<> 162:e13f6fdb2ac4 331 * A c function would put lr on the stack before calling OS_Tick_Handler and this value
<> 162:e13f6fdb2ac4 332 * would never been dequeued.
<> 162:e13f6fdb2ac4 333 *
<> 162:e13f6fdb2ac4 334 * \code
<> 162:e13f6fdb2ac4 335 * void COMMON_RTC_IRQ_HANDLER(void) {
<> 162:e13f6fdb2ac4 336 if(NRF_RTC1->EVENTS_COMPARE[1]) {
<> 162:e13f6fdb2ac4 337 // never return...
<> 162:e13f6fdb2ac4 338 OS_Tick_Handler();
<> 162:e13f6fdb2ac4 339 } else {
<> 162:e13f6fdb2ac4 340 common_rtc_irq_handler();
<> 162:e13f6fdb2ac4 341 }
<> 162:e13f6fdb2ac4 342 }
<> 162:e13f6fdb2ac4 343 * \endcode
<> 162:e13f6fdb2ac4 344 */
<> 162:e13f6fdb2ac4 345 ldr r0,=0x40011144
<> 162:e13f6fdb2ac4 346 ldr r1, [r0, #0]
<> 162:e13f6fdb2ac4 347 cmp r1, #0
<> 162:e13f6fdb2ac4 348 beq US_TICKER_HANDLER
<> 162:e13f6fdb2ac4 349 bl OS_Tick_Handler
<> 162:e13f6fdb2ac4 350 US_TICKER_HANDLER
<> 162:e13f6fdb2ac4 351 push {r3, lr}
<> 162:e13f6fdb2ac4 352 bl common_rtc_irq_handler
<> 162:e13f6fdb2ac4 353 pop {r3, pc}
<> 162:e13f6fdb2ac4 354 ; ALIGN ;
<> 162:e13f6fdb2ac4 355 }
<> 162:e13f6fdb2ac4 356
<> 162:e13f6fdb2ac4 357 #elif defined (__GNUC__) /* GNU Compiler */
<> 162:e13f6fdb2ac4 358
<> 162:e13f6fdb2ac4 359 __attribute__((naked)) void COMMON_RTC_IRQ_HANDLER(void)
<> 162:e13f6fdb2ac4 360 {
<> 162:e13f6fdb2ac4 361 /**
<> 162:e13f6fdb2ac4 362 * Chanel 1 of RTC1 is used by RTX as a systick.
<> 162:e13f6fdb2ac4 363 * If the compare event on channel 1 is set, then branch to OS_Tick_Handler.
<> 162:e13f6fdb2ac4 364 * Otherwise, just execute common_rtc_irq_handler.
<> 162:e13f6fdb2ac4 365 * This function has to be written in assembly and tagged as naked because OS_Tick_Handler
<> 162:e13f6fdb2ac4 366 * will never return.
<> 162:e13f6fdb2ac4 367 * A c function would put lr on the stack before calling OS_Tick_Handler and this value
<> 162:e13f6fdb2ac4 368 * would never been dequeued.
<> 162:e13f6fdb2ac4 369 *
<> 162:e13f6fdb2ac4 370 * \code
<> 162:e13f6fdb2ac4 371 * void COMMON_RTC_IRQ_HANDLER(void) {
<> 162:e13f6fdb2ac4 372 if(NRF_RTC1->EVENTS_COMPARE[1]) {
<> 162:e13f6fdb2ac4 373 // never return...
<> 162:e13f6fdb2ac4 374 OS_Tick_Handler();
<> 162:e13f6fdb2ac4 375 } else {
<> 162:e13f6fdb2ac4 376 common_rtc_irq_handler();
<> 162:e13f6fdb2ac4 377 }
<> 162:e13f6fdb2ac4 378 }
<> 162:e13f6fdb2ac4 379 * \endcode
<> 162:e13f6fdb2ac4 380 */
<> 162:e13f6fdb2ac4 381 __asm__ (
<> 162:e13f6fdb2ac4 382 "ldr r0,=0x40011144\n"
<> 162:e13f6fdb2ac4 383 "ldr r1, [r0, #0]\n"
<> 162:e13f6fdb2ac4 384 "cmp r1, #0\n"
<> 162:e13f6fdb2ac4 385 "beq US_TICKER_HANDLER\n"
<> 162:e13f6fdb2ac4 386 "bl OS_Tick_Handler\n"
<> 162:e13f6fdb2ac4 387 "US_TICKER_HANDLER:\n"
<> 162:e13f6fdb2ac4 388 "push {r3, lr}\n"
<> 162:e13f6fdb2ac4 389 "bl common_rtc_irq_handler\n"
<> 162:e13f6fdb2ac4 390 "pop {r3, pc}\n"
<> 162:e13f6fdb2ac4 391 "nop"
<> 162:e13f6fdb2ac4 392 );
<> 162:e13f6fdb2ac4 393 }
<> 162:e13f6fdb2ac4 394
<> 162:e13f6fdb2ac4 395 #elif defined (__ICCARM__)//IAR
<> 162:e13f6fdb2ac4 396 void common_rtc_irq_handler(void);
<> 162:e13f6fdb2ac4 397
<> 162:e13f6fdb2ac4 398 __stackless __task void COMMON_RTC_IRQ_HANDLER(void)
<> 162:e13f6fdb2ac4 399 {
<> 162:e13f6fdb2ac4 400 uint32_t temp;
<> 162:e13f6fdb2ac4 401
<> 162:e13f6fdb2ac4 402 __asm volatile(
<> 162:e13f6fdb2ac4 403 " ldr %[temp], [%[reg2check]] \n"
<> 162:e13f6fdb2ac4 404 " cmp %[temp], #0 \n"
<> 162:e13f6fdb2ac4 405 " beq 1f \n"
<> 162:e13f6fdb2ac4 406 " bl.w OS_Tick_Handler \n"
<> 162:e13f6fdb2ac4 407 "1: \n"
<> 162:e13f6fdb2ac4 408 " push {r3, lr}\n"
<> 162:e13f6fdb2ac4 409 " blx %[rtc_irq] \n"
<> 162:e13f6fdb2ac4 410 " pop {r3, pc}\n"
<> 162:e13f6fdb2ac4 411
<> 162:e13f6fdb2ac4 412 : /* Outputs */
<> 162:e13f6fdb2ac4 413 [temp] "=&r"(temp)
<> 162:e13f6fdb2ac4 414 : /* Inputs */
<> 162:e13f6fdb2ac4 415 [reg2check] "r"(0x40011144),
<> 162:e13f6fdb2ac4 416 [rtc_irq] "r"(common_rtc_irq_handler)
<> 162:e13f6fdb2ac4 417 : /* Clobbers */
<> 162:e13f6fdb2ac4 418 "cc"
<> 162:e13f6fdb2ac4 419 );
<> 162:e13f6fdb2ac4 420 (void)temp;
<> 162:e13f6fdb2ac4 421 }
<> 162:e13f6fdb2ac4 422
<> 162:e13f6fdb2ac4 423
<> 162:e13f6fdb2ac4 424 #else
<> 162:e13f6fdb2ac4 425
<> 162:e13f6fdb2ac4 426 #error Compiler not supported.
<> 162:e13f6fdb2ac4 427 #error Provide a definition of COMMON_RTC_IRQ_HANDLER.
<> 162:e13f6fdb2ac4 428
<> 162:e13f6fdb2ac4 429 /*
<> 162:e13f6fdb2ac4 430 * Chanel 1 of RTC1 is used by RTX as a systick.
<> 162:e13f6fdb2ac4 431 * If the compare event on channel 1 is set, then branch to OS_Tick_Handler.
<> 162:e13f6fdb2ac4 432 * Otherwise, just execute common_rtc_irq_handler.
<> 162:e13f6fdb2ac4 433 * This function has to be written in assembly and tagged as naked because OS_Tick_Handler
<> 162:e13f6fdb2ac4 434 * will never return.
<> 162:e13f6fdb2ac4 435 * A c function would put lr on the stack before calling OS_Tick_Handler and this value
<> 162:e13f6fdb2ac4 436 * will never been dequeued. After a certain time a stack overflow will happen.
<> 162:e13f6fdb2ac4 437 *
<> 162:e13f6fdb2ac4 438 * \code
<> 162:e13f6fdb2ac4 439 * void COMMON_RTC_IRQ_HANDLER(void) {
<> 162:e13f6fdb2ac4 440 if(NRF_RTC1->EVENTS_COMPARE[1]) {
<> 162:e13f6fdb2ac4 441 // never return...
<> 162:e13f6fdb2ac4 442 OS_Tick_Handler();
<> 162:e13f6fdb2ac4 443 } else {
<> 162:e13f6fdb2ac4 444 common_rtc_irq_handler();
<> 162:e13f6fdb2ac4 445 }
<> 162:e13f6fdb2ac4 446 }
<> 162:e13f6fdb2ac4 447 * \endcode
<> 162:e13f6fdb2ac4 448 */
<> 162:e13f6fdb2ac4 449
<> 162:e13f6fdb2ac4 450 #endif
<> 162:e13f6fdb2ac4 451
<> 162:e13f6fdb2ac4 452 /**
<> 162:e13f6fdb2ac4 453 * Return the next number of clock cycle needed for the next tick.
<> 162:e13f6fdb2ac4 454 * @note This function has been carrefuly optimized for a systick occuring every 1000us.
<> 162:e13f6fdb2ac4 455 */
<> 162:e13f6fdb2ac4 456 static uint32_t get_next_tick_cc_delta()
<> 162:e13f6fdb2ac4 457 {
<> 162:e13f6fdb2ac4 458 uint32_t delta = 0;
<> 162:e13f6fdb2ac4 459
Anna Bridge 163:74e0ce7f98e8 460 if (os_clockrate != 1000) {
<> 162:e13f6fdb2ac4 461 // In RTX, by default SYSTICK is is used.
<> 162:e13f6fdb2ac4 462 // A tick event is generated every os_trv + 1 clock cycles of the system timer.
<> 162:e13f6fdb2ac4 463 delta = os_trv + 1;
Anna Bridge 163:74e0ce7f98e8 464 } else {
<> 162:e13f6fdb2ac4 465 // If the clockrate is set to 1000us then 1000 tick should happen every second.
<> 162:e13f6fdb2ac4 466 // Unfortunatelly, when clockrate is set to 1000, os_trv is equal to 31.
<> 162:e13f6fdb2ac4 467 // If (os_trv + 1) is used as the delta value between two ticks, 1000 ticks will be
<> 162:e13f6fdb2ac4 468 // generated in 32000 clock cycle instead of 32768 clock cycles.
<> 162:e13f6fdb2ac4 469 // As a result, if a user schedule an OS timer to start in 100s, the timer will start
<> 162:e13f6fdb2ac4 470 // instead after 97.656s
<> 162:e13f6fdb2ac4 471 // The code below fix this issue, a clock rate of 1000s will generate 1000 ticks in 32768
<> 162:e13f6fdb2ac4 472 // clock cycles.
<> 162:e13f6fdb2ac4 473 // The strategy is simple, for 1000 ticks:
<> 162:e13f6fdb2ac4 474 // * 768 ticks will occur 33 clock cycles after the previous tick
<> 162:e13f6fdb2ac4 475 // * 232 ticks will occur 32 clock cycles after the previous tick
<> 162:e13f6fdb2ac4 476 // By default every delta is equal to 33.
<> 162:e13f6fdb2ac4 477 // Every five ticks (20%, 200 delta in one second), the delta is equal to 32
<> 162:e13f6fdb2ac4 478 // The remaining (32) deltas equal to 32 are distributed using primes numbers.
<> 162:e13f6fdb2ac4 479 static uint32_t counter = 0;
Anna Bridge 163:74e0ce7f98e8 480 if ((counter % 5) == 0 || (counter % 31) == 0 || (counter % 139) == 0 || (counter == 503)) {
<> 162:e13f6fdb2ac4 481 delta = 32;
Anna Bridge 163:74e0ce7f98e8 482 } else {
<> 162:e13f6fdb2ac4 483 delta = 33;
<> 162:e13f6fdb2ac4 484 }
<> 162:e13f6fdb2ac4 485 ++counter;
Anna Bridge 163:74e0ce7f98e8 486 if (counter == 1000) {
<> 162:e13f6fdb2ac4 487 counter = 0;
<> 162:e13f6fdb2ac4 488 }
<> 162:e13f6fdb2ac4 489 }
<> 162:e13f6fdb2ac4 490 return delta;
<> 162:e13f6fdb2ac4 491 }
<> 162:e13f6fdb2ac4 492
<> 162:e13f6fdb2ac4 493 static inline void clear_tick_interrupt()
<> 162:e13f6fdb2ac4 494 {
<> 162:e13f6fdb2ac4 495 nrf_rtc_event_clear(COMMON_RTC_INSTANCE, OS_TICK_EVENT);
<> 162:e13f6fdb2ac4 496 nrf_rtc_event_disable(COMMON_RTC_INSTANCE, OS_TICK_INT_MASK);
<> 162:e13f6fdb2ac4 497 }
<> 162:e13f6fdb2ac4 498
<> 162:e13f6fdb2ac4 499 /**
<> 162:e13f6fdb2ac4 500 * Indicate if a value is included in a range which can be wrapped.
<> 162:e13f6fdb2ac4 501 * @param begin start of the range
<> 162:e13f6fdb2ac4 502 * @param end end of the range
<> 162:e13f6fdb2ac4 503 * @param val value to check
<> 162:e13f6fdb2ac4 504 * @return true if the value is included in the range and false otherwise.
<> 162:e13f6fdb2ac4 505 */
<> 162:e13f6fdb2ac4 506 static inline bool is_in_wrapped_range(uint32_t begin, uint32_t end, uint32_t val)
<> 162:e13f6fdb2ac4 507 {
<> 162:e13f6fdb2ac4 508 // regular case, begin < end
<> 162:e13f6fdb2ac4 509 // return true if begin <= val < end
Anna Bridge 163:74e0ce7f98e8 510 if (begin < end) {
Anna Bridge 163:74e0ce7f98e8 511 if (begin <= val && val < end) {
<> 162:e13f6fdb2ac4 512 return true;
Anna Bridge 163:74e0ce7f98e8 513 } else {
<> 162:e13f6fdb2ac4 514 return false;
<> 162:e13f6fdb2ac4 515 }
Anna Bridge 163:74e0ce7f98e8 516 } else {
<> 162:e13f6fdb2ac4 517 // In this case end < begin because it has wrap around the limits
<> 162:e13f6fdb2ac4 518 // return false if end < val < begin
Anna Bridge 163:74e0ce7f98e8 519 if (end < val && val < begin) {
<> 162:e13f6fdb2ac4 520 return false;
Anna Bridge 163:74e0ce7f98e8 521 } else {
<> 162:e13f6fdb2ac4 522 return true;
<> 162:e13f6fdb2ac4 523 }
<> 162:e13f6fdb2ac4 524 }
<> 162:e13f6fdb2ac4 525
<> 162:e13f6fdb2ac4 526 }
<> 162:e13f6fdb2ac4 527
<> 162:e13f6fdb2ac4 528 /**
<> 162:e13f6fdb2ac4 529 * Register the next tick.
<> 162:e13f6fdb2ac4 530 */
<> 162:e13f6fdb2ac4 531 static void register_next_tick()
<> 162:e13f6fdb2ac4 532 {
<> 162:e13f6fdb2ac4 533 previous_tick_cc_value = nrf_rtc_cc_get(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL);
<> 162:e13f6fdb2ac4 534 uint32_t delta = get_next_tick_cc_delta();
<> 162:e13f6fdb2ac4 535 uint32_t new_compare_value = (previous_tick_cc_value + delta) & MAX_RTC_COUNTER_VAL;
<> 162:e13f6fdb2ac4 536
<> 162:e13f6fdb2ac4 537 // Disable irq directly for few cycles,
<> 162:e13f6fdb2ac4 538 // Validation of the new CC value against the COUNTER,
<> 162:e13f6fdb2ac4 539 // Setting the new CC value and enabling CC IRQ should be an atomic operation
<> 162:e13f6fdb2ac4 540 // Otherwise, there is a possibility to set an invalid CC value because
<> 162:e13f6fdb2ac4 541 // the RTC1 keeps running.
<> 162:e13f6fdb2ac4 542 // This code is very short 20-38 cycles in the worst case, it shouldn't
<> 162:e13f6fdb2ac4 543 // disturb softdevice.
<> 162:e13f6fdb2ac4 544 core_util_critical_section_enter();
<> 162:e13f6fdb2ac4 545 uint32_t current_counter = nrf_rtc_counter_get(COMMON_RTC_INSTANCE);
<> 162:e13f6fdb2ac4 546
<> 162:e13f6fdb2ac4 547 // If an overflow occur, set the next tick in COUNTER + delta clock cycles
Anna Bridge 163:74e0ce7f98e8 548 if (is_in_wrapped_range(previous_tick_cc_value, new_compare_value, current_counter + 1) == false) {
<> 162:e13f6fdb2ac4 549 new_compare_value = current_counter + delta;
<> 162:e13f6fdb2ac4 550 }
<> 162:e13f6fdb2ac4 551 nrf_rtc_cc_set(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL, new_compare_value);
<> 162:e13f6fdb2ac4 552 // Enable generation of the compare event for the value set above (this
<> 162:e13f6fdb2ac4 553 // event will trigger the interrupt).
<> 162:e13f6fdb2ac4 554 nrf_rtc_event_enable(COMMON_RTC_INSTANCE, OS_TICK_INT_MASK);
<> 162:e13f6fdb2ac4 555 core_util_critical_section_exit();
<> 162:e13f6fdb2ac4 556 }
<> 162:e13f6fdb2ac4 557
<> 162:e13f6fdb2ac4 558 /**
<> 162:e13f6fdb2ac4 559 * Initialize alternative hardware timer as RTX kernel timer
<> 162:e13f6fdb2ac4 560 * This function is directly called by RTX.
<> 162:e13f6fdb2ac4 561 * @note this function shouldn't be called directly.
<> 162:e13f6fdb2ac4 562 * @return IRQ number of the alternative hardware timer
<> 162:e13f6fdb2ac4 563 */
<> 162:e13f6fdb2ac4 564 int os_tick_init (void)
<> 162:e13f6fdb2ac4 565 {
<> 162:e13f6fdb2ac4 566 common_rtc_init();
<> 162:e13f6fdb2ac4 567 nrf_rtc_int_enable(COMMON_RTC_INSTANCE, OS_TICK_INT_MASK);
<> 162:e13f6fdb2ac4 568
<> 162:e13f6fdb2ac4 569 nrf_rtc_cc_set(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL, 0);
<> 162:e13f6fdb2ac4 570 register_next_tick();
<> 162:e13f6fdb2ac4 571
<> 162:e13f6fdb2ac4 572 return nrf_drv_get_IRQn(COMMON_RTC_INSTANCE);
<> 162:e13f6fdb2ac4 573 }
<> 162:e13f6fdb2ac4 574
<> 162:e13f6fdb2ac4 575 /**
<> 162:e13f6fdb2ac4 576 * Acknowledge the tick interrupt.
<> 162:e13f6fdb2ac4 577 * This function is called by the function OS_Tick_Handler of RTX.
<> 162:e13f6fdb2ac4 578 * @note this function shouldn't be called directly.
<> 162:e13f6fdb2ac4 579 */
<> 162:e13f6fdb2ac4 580 void os_tick_irqack(void)
<> 162:e13f6fdb2ac4 581 {
<> 162:e13f6fdb2ac4 582 clear_tick_interrupt();
<> 162:e13f6fdb2ac4 583 register_next_tick();
<> 162:e13f6fdb2ac4 584 }
<> 162:e13f6fdb2ac4 585
<> 162:e13f6fdb2ac4 586 /**
<> 162:e13f6fdb2ac4 587 * Returns the overflow flag of the alternative hardware timer.
<> 162:e13f6fdb2ac4 588 * @note This function is exposed by RTX kernel.
<> 162:e13f6fdb2ac4 589 * @return 1 if the timer has overflowed and 0 otherwise.
<> 162:e13f6fdb2ac4 590 */
<> 162:e13f6fdb2ac4 591 uint32_t os_tick_ovf(void)
<> 162:e13f6fdb2ac4 592 {
<> 162:e13f6fdb2ac4 593 uint32_t current_counter = nrf_rtc_counter_get(COMMON_RTC_INSTANCE);
<> 162:e13f6fdb2ac4 594 uint32_t next_tick_cc_value = nrf_rtc_cc_get(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL);
<> 162:e13f6fdb2ac4 595
<> 162:e13f6fdb2ac4 596 return is_in_wrapped_range(previous_tick_cc_value, next_tick_cc_value, current_counter) ? 0 : 1;
<> 162:e13f6fdb2ac4 597 }
<> 162:e13f6fdb2ac4 598
<> 162:e13f6fdb2ac4 599 /**
<> 162:e13f6fdb2ac4 600 * Return the value of the alternative hardware timer.
<> 162:e13f6fdb2ac4 601 * @note The documentation is not very clear about what is expected as a result,
<> 162:e13f6fdb2ac4 602 * is it an ascending counter, a descending one ?
<> 162:e13f6fdb2ac4 603 * None of this is specified.
<> 162:e13f6fdb2ac4 604 * The default systick is a descending counter and this function return values in
<> 162:e13f6fdb2ac4 605 * descending order, even if the internal counter used is an ascending one.
<> 162:e13f6fdb2ac4 606 * @return the value of the alternative hardware timer.
<> 162:e13f6fdb2ac4 607 */
<> 162:e13f6fdb2ac4 608 uint32_t os_tick_val(void)
<> 162:e13f6fdb2ac4 609 {
<> 162:e13f6fdb2ac4 610 uint32_t current_counter = nrf_rtc_counter_get(COMMON_RTC_INSTANCE);
<> 162:e13f6fdb2ac4 611 uint32_t next_tick_cc_value = nrf_rtc_cc_get(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL);
<> 162:e13f6fdb2ac4 612
<> 162:e13f6fdb2ac4 613 // do not use os_tick_ovf because its counter value can be different
Anna Bridge 163:74e0ce7f98e8 614 if(is_in_wrapped_range(previous_tick_cc_value, next_tick_cc_value, current_counter)) {
Anna Bridge 163:74e0ce7f98e8 615 if (next_tick_cc_value > previous_tick_cc_value) {
<> 162:e13f6fdb2ac4 616 return next_tick_cc_value - current_counter;
Anna Bridge 163:74e0ce7f98e8 617 } else if(current_counter <= next_tick_cc_value) {
<> 162:e13f6fdb2ac4 618 return next_tick_cc_value - current_counter;
Anna Bridge 163:74e0ce7f98e8 619 } else {
<> 162:e13f6fdb2ac4 620 return next_tick_cc_value + (MAX_RTC_COUNTER_VAL - current_counter);
<> 162:e13f6fdb2ac4 621 }
Anna Bridge 163:74e0ce7f98e8 622 } else {
<> 162:e13f6fdb2ac4 623 // use (os_trv + 1) has the base step, can be totally inacurate ...
<> 162:e13f6fdb2ac4 624 uint32_t clock_cycles_by_tick = os_trv + 1;
<> 162:e13f6fdb2ac4 625
<> 162:e13f6fdb2ac4 626 // if current counter has wrap arround, add the limit to it.
Anna Bridge 163:74e0ce7f98e8 627 if (current_counter < next_tick_cc_value) {
<> 162:e13f6fdb2ac4 628 current_counter = current_counter + MAX_RTC_COUNTER_VAL;
<> 162:e13f6fdb2ac4 629 }
<> 162:e13f6fdb2ac4 630
<> 162:e13f6fdb2ac4 631 return clock_cycles_by_tick - ((current_counter - next_tick_cc_value) % clock_cycles_by_tick);
<> 162:e13f6fdb2ac4 632 }
<> 162:e13f6fdb2ac4 633
<> 162:e13f6fdb2ac4 634 }
<> 162:e13f6fdb2ac4 635
<> 162:e13f6fdb2ac4 636 #endif // defined(TARGET_MCU_NRF51822)