mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/TARGET_MCU_K22F512/device/TOOLCHAIN_ARM_STD/MK22FN512xxx12.sct@163:74e0ce7f98e8, 2017-04-28 (annotated)

Committer:
Anna Bridge
Date:
Fri Apr 28 14:04:18 2017 +0100
Revision:
163:74e0ce7f98e8
Parent:
154:37f96f9d4de2
Child:
187:0387e8f68319
This updates the lib to the mbed lib v141

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 154:37f96f9d4de2 1 #! armcc -E
<> 154:37f96f9d4de2 2 /*
<> 154:37f96f9d4de2 3 ** ###################################################################
<> 154:37f96f9d4de2 4 ** Processors: MK22FN512CAP12
<> 154:37f96f9d4de2 5 ** MK22FN512VDC12
<> 154:37f96f9d4de2 6 ** MK22FN512VFX12
<> 154:37f96f9d4de2 7 ** MK22FN512VLH12
<> 154:37f96f9d4de2 8 ** MK22FN512VLL12
<> 154:37f96f9d4de2 9 ** MK22FN512VMP12
<> 154:37f96f9d4de2 10 **
<> 154:37f96f9d4de2 11 ** Compiler: Keil ARM C/C++ Compiler
<> 154:37f96f9d4de2 12 ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
<> 154:37f96f9d4de2 13 ** Version: rev. 2.9, 2016-03-21
<> 154:37f96f9d4de2 14 ** Build: b160406
<> 154:37f96f9d4de2 15 **
<> 154:37f96f9d4de2 16 ** Abstract:
<> 154:37f96f9d4de2 17 ** Linker file for the Keil ARM C/C++ Compiler
<> 154:37f96f9d4de2 18 **
<> 154:37f96f9d4de2 19 ** Copyright (c) 2016 Freescale Semiconductor, Inc.
<> 154:37f96f9d4de2 20 ** All rights reserved.
<> 154:37f96f9d4de2 21 **
<> 154:37f96f9d4de2 22 ** Redistribution and use in source and binary forms, with or without modification,
<> 154:37f96f9d4de2 23 ** are permitted provided that the following conditions are met:
<> 154:37f96f9d4de2 24 **
<> 154:37f96f9d4de2 25 ** o Redistributions of source code must retain the above copyright notice, this list
<> 154:37f96f9d4de2 26 ** of conditions and the following disclaimer.
<> 154:37f96f9d4de2 27 **
<> 154:37f96f9d4de2 28 ** o Redistributions in binary form must reproduce the above copyright notice, this
<> 154:37f96f9d4de2 29 ** list of conditions and the following disclaimer in the documentation and/or
<> 154:37f96f9d4de2 30 ** other materials provided with the distribution.
<> 154:37f96f9d4de2 31 **
<> 154:37f96f9d4de2 32 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 154:37f96f9d4de2 33 ** contributors may be used to endorse or promote products derived from this
<> 154:37f96f9d4de2 34 ** software without specific prior written permission.
<> 154:37f96f9d4de2 35 **
<> 154:37f96f9d4de2 36 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 154:37f96f9d4de2 37 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 154:37f96f9d4de2 38 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 154:37f96f9d4de2 39 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 154:37f96f9d4de2 40 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 154:37f96f9d4de2 41 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 154:37f96f9d4de2 42 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 154:37f96f9d4de2 43 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 154:37f96f9d4de2 44 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 154:37f96f9d4de2 45 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 154:37f96f9d4de2 46 **
<> 154:37f96f9d4de2 47 ** http: www.freescale.com
<> 154:37f96f9d4de2 48 ** mail: support@freescale.com
<> 154:37f96f9d4de2 49 **
<> 154:37f96f9d4de2 50 ** ###################################################################
<> 154:37f96f9d4de2 51 */
<> 154:37f96f9d4de2 52 #define __ram_vector_table__ 1
<> 154:37f96f9d4de2 53
<> 154:37f96f9d4de2 54 #if (defined(__ram_vector_table__))
<> 154:37f96f9d4de2 55 #define __ram_vector_table_size__ 0x00000400
<> 154:37f96f9d4de2 56 #else
<> 154:37f96f9d4de2 57 #define __ram_vector_table_size__ 0x00000000
<> 154:37f96f9d4de2 58 #endif
<> 154:37f96f9d4de2 59
<> 154:37f96f9d4de2 60 #define m_interrupts_start 0x00000000
<> 154:37f96f9d4de2 61 #define m_interrupts_size 0x00000400
<> 154:37f96f9d4de2 62
<> 154:37f96f9d4de2 63 #define m_flash_config_start 0x00000400
<> 154:37f96f9d4de2 64 #define m_flash_config_size 0x00000010
<> 154:37f96f9d4de2 65
<> 154:37f96f9d4de2 66 #define m_text_start 0x00000410
<> 154:37f96f9d4de2 67 #define m_text_size 0x0007FBF0
<> 154:37f96f9d4de2 68
<> 154:37f96f9d4de2 69 #define m_interrupts_ram_start 0x1FFF0000
<> 154:37f96f9d4de2 70 #define m_interrupts_ram_size __ram_vector_table_size__
<> 154:37f96f9d4de2 71
<> 154:37f96f9d4de2 72 #define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size)
<> 154:37f96f9d4de2 73 #define m_data_size (0x00010000 - m_interrupts_ram_size)
<> 154:37f96f9d4de2 74
<> 154:37f96f9d4de2 75 #define m_data_2_start 0x20000000
<> 154:37f96f9d4de2 76 #define m_data_2_size 0x00010000
<> 154:37f96f9d4de2 77
<> 154:37f96f9d4de2 78 /* Sizes */
<> 154:37f96f9d4de2 79 #if (defined(__stack_size__))
<> 154:37f96f9d4de2 80 #define Stack_Size __stack_size__
<> 154:37f96f9d4de2 81 #else
<> 154:37f96f9d4de2 82 #define Stack_Size 0x0400
<> 154:37f96f9d4de2 83 #endif
<> 154:37f96f9d4de2 84
<> 154:37f96f9d4de2 85 #if (defined(__heap_size__))
<> 154:37f96f9d4de2 86 #define Heap_Size __heap_size__
<> 154:37f96f9d4de2 87 #else
<> 154:37f96f9d4de2 88 #define Heap_Size 0x0400
<> 154:37f96f9d4de2 89 #endif
<> 154:37f96f9d4de2 90
<> 154:37f96f9d4de2 91 LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
<> 154:37f96f9d4de2 92 VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
<> 154:37f96f9d4de2 93 * (RESET,+FIRST)
<> 154:37f96f9d4de2 94 }
<> 154:37f96f9d4de2 95 ER_m_flash_config m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
<> 154:37f96f9d4de2 96 * (FlashConfig)
<> 154:37f96f9d4de2 97 }
<> 154:37f96f9d4de2 98 ER_m_text m_text_start m_text_size { ; load address = execution address
<> 154:37f96f9d4de2 99 * (InRoot$$Sections)
<> 154:37f96f9d4de2 100 .ANY (+RO)
<> 154:37f96f9d4de2 101 }
<> 154:37f96f9d4de2 102
<> 154:37f96f9d4de2 103 #if (defined(__ram_vector_table__))
<> 154:37f96f9d4de2 104 VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
<> 154:37f96f9d4de2 105 }
<> 154:37f96f9d4de2 106 #else
<> 154:37f96f9d4de2 107 VECTOR_RAM m_interrupts_start EMPTY 0 {
<> 154:37f96f9d4de2 108 }
<> 154:37f96f9d4de2 109 #endif
<> 154:37f96f9d4de2 110 RW_m_data m_data_start m_data_size { ; RW data
<> 154:37f96f9d4de2 111 .ANY (+RW +ZI)
<> 154:37f96f9d4de2 112 }
<> 154:37f96f9d4de2 113 RW_m_data_2 m_data_2_start m_data_2_size-Stack_Size-Heap_Size { ; RW data
<> 154:37f96f9d4de2 114 .ANY (+RW +ZI)
<> 154:37f96f9d4de2 115 }
<> 154:37f96f9d4de2 116 RW_IRAM1 ImageLimit(RW_m_data_2) { ; Heap region growing up
<> 154:37f96f9d4de2 117 }
<> 154:37f96f9d4de2 118 }
<> 154:37f96f9d4de2 119