mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/stm32l151xc.h@148:21d94c44109e, 2016-09-30 (annotated)

Committer:
<>
Date:
Fri Sep 30 18:07:01 2016 +0100
Revision:
148:21d94c44109e
This updates the lib to the mbed lib v127

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 148:21d94c44109e 1 /**
<> 148:21d94c44109e 2 ******************************************************************************
<> 148:21d94c44109e 3 * @file stm32l151xc.h
<> 148:21d94c44109e 4 * @author MCD Application Team
<> 148:21d94c44109e 5 * @version V2.2.0
<> 148:21d94c44109e 6 * @date 01-July-2016
<> 148:21d94c44109e 7 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
<> 148:21d94c44109e 8 * This file contains all the peripheral register's definitions, bits
<> 148:21d94c44109e 9 * definitions and memory mapping for STM32L1xx devices.
<> 148:21d94c44109e 10 *
<> 148:21d94c44109e 11 * This file contains:
<> 148:21d94c44109e 12 * - Data structures and the address mapping for all peripherals
<> 148:21d94c44109e 13 * - Peripheral's registers declarations and bits definition
<> 148:21d94c44109e 14 * - Macros to access peripheral’s registers hardware
<> 148:21d94c44109e 15 *
<> 148:21d94c44109e 16 ******************************************************************************
<> 148:21d94c44109e 17 * @attention
<> 148:21d94c44109e 18 *
<> 148:21d94c44109e 19 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 148:21d94c44109e 20 *
<> 148:21d94c44109e 21 * Redistribution and use in source and binary forms, with or without modification,
<> 148:21d94c44109e 22 * are permitted provided that the following conditions are met:
<> 148:21d94c44109e 23 * 1. Redistributions of source code must retain the above copyright notice,
<> 148:21d94c44109e 24 * this list of conditions and the following disclaimer.
<> 148:21d94c44109e 25 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 148:21d94c44109e 26 * this list of conditions and the following disclaimer in the documentation
<> 148:21d94c44109e 27 * and/or other materials provided with the distribution.
<> 148:21d94c44109e 28 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 148:21d94c44109e 29 * may be used to endorse or promote products derived from this software
<> 148:21d94c44109e 30 * without specific prior written permission.
<> 148:21d94c44109e 31 *
<> 148:21d94c44109e 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 148:21d94c44109e 33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 148:21d94c44109e 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 148:21d94c44109e 35 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 148:21d94c44109e 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 148:21d94c44109e 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 148:21d94c44109e 38 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 148:21d94c44109e 39 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 148:21d94c44109e 40 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 148:21d94c44109e 41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 148:21d94c44109e 42 *
<> 148:21d94c44109e 43 ******************************************************************************
<> 148:21d94c44109e 44 */
<> 148:21d94c44109e 45
<> 148:21d94c44109e 46 /** @addtogroup CMSIS
<> 148:21d94c44109e 47 * @{
<> 148:21d94c44109e 48 */
<> 148:21d94c44109e 49
<> 148:21d94c44109e 50 /** @addtogroup stm32l151xc
<> 148:21d94c44109e 51 * @{
<> 148:21d94c44109e 52 */
<> 148:21d94c44109e 53
<> 148:21d94c44109e 54 #ifndef __STM32L151xC_H
<> 148:21d94c44109e 55 #define __STM32L151xC_H
<> 148:21d94c44109e 56
<> 148:21d94c44109e 57 #ifdef __cplusplus
<> 148:21d94c44109e 58 extern "C" {
<> 148:21d94c44109e 59 #endif
<> 148:21d94c44109e 60
<> 148:21d94c44109e 61
<> 148:21d94c44109e 62 /** @addtogroup Configuration_section_for_CMSIS
<> 148:21d94c44109e 63 * @{
<> 148:21d94c44109e 64 */
<> 148:21d94c44109e 65 /**
<> 148:21d94c44109e 66 * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
<> 148:21d94c44109e 67 */
<> 148:21d94c44109e 68 #define __CM3_REV 0x200U /*!< Cortex-M3 Revision r2p0 */
<> 148:21d94c44109e 69 #define __MPU_PRESENT 1U /*!< STM32L1xx provides MPU */
<> 148:21d94c44109e 70 #define __NVIC_PRIO_BITS 4U /*!< STM32L1xx uses 4 Bits for the Priority Levels */
<> 148:21d94c44109e 71 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
<> 148:21d94c44109e 72
<> 148:21d94c44109e 73 /**
<> 148:21d94c44109e 74 * @}
<> 148:21d94c44109e 75 */
<> 148:21d94c44109e 76
<> 148:21d94c44109e 77 /** @addtogroup Peripheral_interrupt_number_definition
<> 148:21d94c44109e 78 * @{
<> 148:21d94c44109e 79 */
<> 148:21d94c44109e 80
<> 148:21d94c44109e 81 /**
<> 148:21d94c44109e 82 * @brief STM32L1xx Interrupt Number Definition, according to the selected device
<> 148:21d94c44109e 83 * in @ref Library_configuration_section
<> 148:21d94c44109e 84 */
<> 148:21d94c44109e 85
<> 148:21d94c44109e 86 /*!< Interrupt Number Definition */
<> 148:21d94c44109e 87 typedef enum
<> 148:21d94c44109e 88 {
<> 148:21d94c44109e 89 /****** Cortex-M3 Processor Exceptions Numbers ******************************************************/
<> 148:21d94c44109e 90 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
<> 148:21d94c44109e 91 HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
<> 148:21d94c44109e 92 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
<> 148:21d94c44109e 93 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
<> 148:21d94c44109e 94 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
<> 148:21d94c44109e 95 SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
<> 148:21d94c44109e 96 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
<> 148:21d94c44109e 97 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
<> 148:21d94c44109e 98 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
<> 148:21d94c44109e 99
<> 148:21d94c44109e 100 /****** STM32L specific Interrupt Numbers ***********************************************************/
<> 148:21d94c44109e 101 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
<> 148:21d94c44109e 102 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
<> 148:21d94c44109e 103 TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
<> 148:21d94c44109e 104 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */
<> 148:21d94c44109e 105 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
<> 148:21d94c44109e 106 RCC_IRQn = 5, /*!< RCC global Interrupt */
<> 148:21d94c44109e 107 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
<> 148:21d94c44109e 108 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
<> 148:21d94c44109e 109 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
<> 148:21d94c44109e 110 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
<> 148:21d94c44109e 111 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
<> 148:21d94c44109e 112 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
<> 148:21d94c44109e 113 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
<> 148:21d94c44109e 114 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
<> 148:21d94c44109e 115 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
<> 148:21d94c44109e 116 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
<> 148:21d94c44109e 117 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
<> 148:21d94c44109e 118 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
<> 148:21d94c44109e 119 ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
<> 148:21d94c44109e 120 USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */
<> 148:21d94c44109e 121 USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */
<> 148:21d94c44109e 122 DAC_IRQn = 21, /*!< DAC Interrupt */
<> 148:21d94c44109e 123 COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */
<> 148:21d94c44109e 124 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
<> 148:21d94c44109e 125 TIM9_IRQn = 25, /*!< TIM9 global Interrupt */
<> 148:21d94c44109e 126 TIM10_IRQn = 26, /*!< TIM10 global Interrupt */
<> 148:21d94c44109e 127 TIM11_IRQn = 27, /*!< TIM11 global Interrupt */
<> 148:21d94c44109e 128 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
<> 148:21d94c44109e 129 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
<> 148:21d94c44109e 130 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
<> 148:21d94c44109e 131 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
<> 148:21d94c44109e 132 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
<> 148:21d94c44109e 133 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
<> 148:21d94c44109e 134 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
<> 148:21d94c44109e 135 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
<> 148:21d94c44109e 136 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
<> 148:21d94c44109e 137 USART1_IRQn = 37, /*!< USART1 global Interrupt */
<> 148:21d94c44109e 138 USART2_IRQn = 38, /*!< USART2 global Interrupt */
<> 148:21d94c44109e 139 USART3_IRQn = 39, /*!< USART3 global Interrupt */
<> 148:21d94c44109e 140 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
<> 148:21d94c44109e 141 RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
<> 148:21d94c44109e 142 USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */
<> 148:21d94c44109e 143 TIM6_IRQn = 43, /*!< TIM6 global Interrupt */
<> 148:21d94c44109e 144 TIM7_IRQn = 44, /*!< TIM7 global Interrupt */
<> 148:21d94c44109e 145 TIM5_IRQn = 46, /*!< TIM5 global Interrupt */
<> 148:21d94c44109e 146 SPI3_IRQn = 47, /*!< SPI3 global Interrupt */
<> 148:21d94c44109e 147 DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */
<> 148:21d94c44109e 148 DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */
<> 148:21d94c44109e 149 DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */
<> 148:21d94c44109e 150 DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */
<> 148:21d94c44109e 151 DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */
<> 148:21d94c44109e 152 COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */
<> 148:21d94c44109e 153 } IRQn_Type;
<> 148:21d94c44109e 154
<> 148:21d94c44109e 155 /**
<> 148:21d94c44109e 156 * @}
<> 148:21d94c44109e 157 */
<> 148:21d94c44109e 158
<> 148:21d94c44109e 159 #include "core_cm3.h"
<> 148:21d94c44109e 160 #include "system_stm32l1xx.h"
<> 148:21d94c44109e 161 #include <stdint.h>
<> 148:21d94c44109e 162
<> 148:21d94c44109e 163 /** @addtogroup Peripheral_registers_structures
<> 148:21d94c44109e 164 * @{
<> 148:21d94c44109e 165 */
<> 148:21d94c44109e 166
<> 148:21d94c44109e 167 /**
<> 148:21d94c44109e 168 * @brief Analog to Digital Converter
<> 148:21d94c44109e 169 */
<> 148:21d94c44109e 170
<> 148:21d94c44109e 171 typedef struct
<> 148:21d94c44109e 172 {
<> 148:21d94c44109e 173 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
<> 148:21d94c44109e 174 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
<> 148:21d94c44109e 175 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
<> 148:21d94c44109e 176 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
<> 148:21d94c44109e 177 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
<> 148:21d94c44109e 178 __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */
<> 148:21d94c44109e 179 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
<> 148:21d94c44109e 180 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
<> 148:21d94c44109e 181 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
<> 148:21d94c44109e 182 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
<> 148:21d94c44109e 183 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */
<> 148:21d94c44109e 184 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */
<> 148:21d94c44109e 185 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
<> 148:21d94c44109e 186 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
<> 148:21d94c44109e 187 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
<> 148:21d94c44109e 188 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
<> 148:21d94c44109e 189 __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */
<> 148:21d94c44109e 190 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */
<> 148:21d94c44109e 191 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */
<> 148:21d94c44109e 192 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */
<> 148:21d94c44109e 193 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */
<> 148:21d94c44109e 194 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */
<> 148:21d94c44109e 195 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */
<> 148:21d94c44109e 196 uint32_t RESERVED; /*!< Reserved, Address offset: 0x5C */
<> 148:21d94c44109e 197 } ADC_TypeDef;
<> 148:21d94c44109e 198
<> 148:21d94c44109e 199 typedef struct
<> 148:21d94c44109e 200 {
<> 148:21d94c44109e 201 __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */
<> 148:21d94c44109e 202 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
<> 148:21d94c44109e 203 } ADC_Common_TypeDef;
<> 148:21d94c44109e 204
<> 148:21d94c44109e 205 /**
<> 148:21d94c44109e 206 * @brief Comparator
<> 148:21d94c44109e 207 */
<> 148:21d94c44109e 208
<> 148:21d94c44109e 209 typedef struct
<> 148:21d94c44109e 210 {
<> 148:21d94c44109e 211 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
<> 148:21d94c44109e 212 } COMP_TypeDef;
<> 148:21d94c44109e 213
<> 148:21d94c44109e 214 typedef struct
<> 148:21d94c44109e 215 {
<> 148:21d94c44109e 216 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
<> 148:21d94c44109e 217 } COMP_Common_TypeDef;
<> 148:21d94c44109e 218
<> 148:21d94c44109e 219 /**
<> 148:21d94c44109e 220 * @brief CRC calculation unit
<> 148:21d94c44109e 221 */
<> 148:21d94c44109e 222
<> 148:21d94c44109e 223 typedef struct
<> 148:21d94c44109e 224 {
<> 148:21d94c44109e 225 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
<> 148:21d94c44109e 226 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
<> 148:21d94c44109e 227 uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */
<> 148:21d94c44109e 228 uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */
<> 148:21d94c44109e 229 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
<> 148:21d94c44109e 230 } CRC_TypeDef;
<> 148:21d94c44109e 231
<> 148:21d94c44109e 232 /**
<> 148:21d94c44109e 233 * @brief Digital to Analog Converter
<> 148:21d94c44109e 234 */
<> 148:21d94c44109e 235
<> 148:21d94c44109e 236 typedef struct
<> 148:21d94c44109e 237 {
<> 148:21d94c44109e 238 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
<> 148:21d94c44109e 239 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
<> 148:21d94c44109e 240 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
<> 148:21d94c44109e 241 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
<> 148:21d94c44109e 242 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
<> 148:21d94c44109e 243 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
<> 148:21d94c44109e 244 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
<> 148:21d94c44109e 245 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
<> 148:21d94c44109e 246 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
<> 148:21d94c44109e 247 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
<> 148:21d94c44109e 248 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
<> 148:21d94c44109e 249 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
<> 148:21d94c44109e 250 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
<> 148:21d94c44109e 251 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
<> 148:21d94c44109e 252 } DAC_TypeDef;
<> 148:21d94c44109e 253
<> 148:21d94c44109e 254 /**
<> 148:21d94c44109e 255 * @brief Debug MCU
<> 148:21d94c44109e 256 */
<> 148:21d94c44109e 257
<> 148:21d94c44109e 258 typedef struct
<> 148:21d94c44109e 259 {
<> 148:21d94c44109e 260 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
<> 148:21d94c44109e 261 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
<> 148:21d94c44109e 262 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
<> 148:21d94c44109e 263 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
<> 148:21d94c44109e 264 }DBGMCU_TypeDef;
<> 148:21d94c44109e 265
<> 148:21d94c44109e 266 /**
<> 148:21d94c44109e 267 * @brief DMA Controller
<> 148:21d94c44109e 268 */
<> 148:21d94c44109e 269
<> 148:21d94c44109e 270 typedef struct
<> 148:21d94c44109e 271 {
<> 148:21d94c44109e 272 __IO uint32_t CCR; /*!< DMA channel x configuration register */
<> 148:21d94c44109e 273 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
<> 148:21d94c44109e 274 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
<> 148:21d94c44109e 275 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
<> 148:21d94c44109e 276 } DMA_Channel_TypeDef;
<> 148:21d94c44109e 277
<> 148:21d94c44109e 278 typedef struct
<> 148:21d94c44109e 279 {
<> 148:21d94c44109e 280 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
<> 148:21d94c44109e 281 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
<> 148:21d94c44109e 282 } DMA_TypeDef;
<> 148:21d94c44109e 283
<> 148:21d94c44109e 284 /**
<> 148:21d94c44109e 285 * @brief External Interrupt/Event Controller
<> 148:21d94c44109e 286 */
<> 148:21d94c44109e 287
<> 148:21d94c44109e 288 typedef struct
<> 148:21d94c44109e 289 {
<> 148:21d94c44109e 290 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
<> 148:21d94c44109e 291 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
<> 148:21d94c44109e 292 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
<> 148:21d94c44109e 293 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
<> 148:21d94c44109e 294 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
<> 148:21d94c44109e 295 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
<> 148:21d94c44109e 296 } EXTI_TypeDef;
<> 148:21d94c44109e 297
<> 148:21d94c44109e 298 /**
<> 148:21d94c44109e 299 * @brief FLASH Registers
<> 148:21d94c44109e 300 */
<> 148:21d94c44109e 301 typedef struct
<> 148:21d94c44109e 302 {
<> 148:21d94c44109e 303 __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
<> 148:21d94c44109e 304 __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
<> 148:21d94c44109e 305 __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
<> 148:21d94c44109e 306 __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
<> 148:21d94c44109e 307 __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
<> 148:21d94c44109e 308 __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
<> 148:21d94c44109e 309 __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
<> 148:21d94c44109e 310 __IO uint32_t OBR; /*!< Option byte register, Address offset: 0x1c */
<> 148:21d94c44109e 311 __IO uint32_t WRPR1; /*!< Write protection register 1, Address offset: 0x20 */
<> 148:21d94c44109e 312 uint32_t RESERVED[23]; /*!< Reserved, Address offset: 0x24 */
<> 148:21d94c44109e 313 __IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x80 */
<> 148:21d94c44109e 314 } FLASH_TypeDef;
<> 148:21d94c44109e 315
<> 148:21d94c44109e 316 /**
<> 148:21d94c44109e 317 * @brief Option Bytes Registers
<> 148:21d94c44109e 318 */
<> 148:21d94c44109e 319 typedef struct
<> 148:21d94c44109e 320 {
<> 148:21d94c44109e 321 __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
<> 148:21d94c44109e 322 __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
<> 148:21d94c44109e 323 __IO uint32_t WRP01; /*!< write protection register 0 1, Address offset: 0x08 */
<> 148:21d94c44109e 324 __IO uint32_t WRP23; /*!< write protection register 2 3, Address offset: 0x0C */
<> 148:21d94c44109e 325 __IO uint32_t WRP45; /*!< write protection register 4 5, Address offset: 0x10 */
<> 148:21d94c44109e 326 __IO uint32_t WRP67; /*!< write protection register 6 7, Address offset: 0x14 */
<> 148:21d94c44109e 327 } OB_TypeDef;
<> 148:21d94c44109e 328
<> 148:21d94c44109e 329 /**
<> 148:21d94c44109e 330 * @brief Operational Amplifier (OPAMP)
<> 148:21d94c44109e 331 */
<> 148:21d94c44109e 332 typedef struct
<> 148:21d94c44109e 333 {
<> 148:21d94c44109e 334 __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */
<> 148:21d94c44109e 335 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
<> 148:21d94c44109e 336 __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
<> 148:21d94c44109e 337 } OPAMP_TypeDef;
<> 148:21d94c44109e 338
<> 148:21d94c44109e 339 typedef struct
<> 148:21d94c44109e 340 {
<> 148:21d94c44109e 341 __IO uint32_t CSR; /*!< OPAMP control and status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
<> 148:21d94c44109e 342 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, used for bits common to several OPAMP instances, Address offset: 0x04 */
<> 148:21d94c44109e 343 } OPAMP_Common_TypeDef;
<> 148:21d94c44109e 344
<> 148:21d94c44109e 345 /**
<> 148:21d94c44109e 346 * @brief General Purpose IO
<> 148:21d94c44109e 347 */
<> 148:21d94c44109e 348
<> 148:21d94c44109e 349 typedef struct
<> 148:21d94c44109e 350 {
<> 148:21d94c44109e 351 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
<> 148:21d94c44109e 352 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
<> 148:21d94c44109e 353 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
<> 148:21d94c44109e 354 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
<> 148:21d94c44109e 355 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
<> 148:21d94c44109e 356 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
<> 148:21d94c44109e 357 __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
<> 148:21d94c44109e 358 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
<> 148:21d94c44109e 359 __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
<> 148:21d94c44109e 360 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
<> 148:21d94c44109e 361 } GPIO_TypeDef;
<> 148:21d94c44109e 362
<> 148:21d94c44109e 363 /**
<> 148:21d94c44109e 364 * @brief SysTem Configuration
<> 148:21d94c44109e 365 */
<> 148:21d94c44109e 366
<> 148:21d94c44109e 367 typedef struct
<> 148:21d94c44109e 368 {
<> 148:21d94c44109e 369 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
<> 148:21d94c44109e 370 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
<> 148:21d94c44109e 371 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
<> 148:21d94c44109e 372 } SYSCFG_TypeDef;
<> 148:21d94c44109e 373
<> 148:21d94c44109e 374 /**
<> 148:21d94c44109e 375 * @brief Inter-integrated Circuit Interface
<> 148:21d94c44109e 376 */
<> 148:21d94c44109e 377
<> 148:21d94c44109e 378 typedef struct
<> 148:21d94c44109e 379 {
<> 148:21d94c44109e 380 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
<> 148:21d94c44109e 381 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
<> 148:21d94c44109e 382 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
<> 148:21d94c44109e 383 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
<> 148:21d94c44109e 384 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
<> 148:21d94c44109e 385 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
<> 148:21d94c44109e 386 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
<> 148:21d94c44109e 387 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
<> 148:21d94c44109e 388 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
<> 148:21d94c44109e 389 } I2C_TypeDef;
<> 148:21d94c44109e 390
<> 148:21d94c44109e 391 /**
<> 148:21d94c44109e 392 * @brief Independent WATCHDOG
<> 148:21d94c44109e 393 */
<> 148:21d94c44109e 394
<> 148:21d94c44109e 395 typedef struct
<> 148:21d94c44109e 396 {
<> 148:21d94c44109e 397 __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
<> 148:21d94c44109e 398 __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
<> 148:21d94c44109e 399 __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
<> 148:21d94c44109e 400 __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
<> 148:21d94c44109e 401 } IWDG_TypeDef;
<> 148:21d94c44109e 402
<> 148:21d94c44109e 403 /**
<> 148:21d94c44109e 404 * @brief Power Control
<> 148:21d94c44109e 405 */
<> 148:21d94c44109e 406
<> 148:21d94c44109e 407 typedef struct
<> 148:21d94c44109e 408 {
<> 148:21d94c44109e 409 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
<> 148:21d94c44109e 410 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
<> 148:21d94c44109e 411 } PWR_TypeDef;
<> 148:21d94c44109e 412
<> 148:21d94c44109e 413 /**
<> 148:21d94c44109e 414 * @brief Reset and Clock Control
<> 148:21d94c44109e 415 */
<> 148:21d94c44109e 416
<> 148:21d94c44109e 417 typedef struct
<> 148:21d94c44109e 418 {
<> 148:21d94c44109e 419 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
<> 148:21d94c44109e 420 __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
<> 148:21d94c44109e 421 __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x08 */
<> 148:21d94c44109e 422 __IO uint32_t CIR; /*!< RCC Clock interrupt register, Address offset: 0x0C */
<> 148:21d94c44109e 423 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x10 */
<> 148:21d94c44109e 424 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x14 */
<> 148:21d94c44109e 425 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x18 */
<> 148:21d94c44109e 426 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x1C */
<> 148:21d94c44109e 427 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x20 */
<> 148:21d94c44109e 428 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x24 */
<> 148:21d94c44109e 429 __IO uint32_t AHBLPENR; /*!< RCC AHB peripheral clock enable in low power mode register, Address offset: 0x28 */
<> 148:21d94c44109e 430 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x2C */
<> 148:21d94c44109e 431 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x30 */
<> 148:21d94c44109e 432 __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x34 */
<> 148:21d94c44109e 433 } RCC_TypeDef;
<> 148:21d94c44109e 434
<> 148:21d94c44109e 435 /**
<> 148:21d94c44109e 436 * @brief Routing Interface
<> 148:21d94c44109e 437 */
<> 148:21d94c44109e 438
<> 148:21d94c44109e 439 typedef struct
<> 148:21d94c44109e 440 {
<> 148:21d94c44109e 441 __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */
<> 148:21d94c44109e 442 __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */
<> 148:21d94c44109e 443 __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */
<> 148:21d94c44109e 444 __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */
<> 148:21d94c44109e 445 __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */
<> 148:21d94c44109e 446 __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */
<> 148:21d94c44109e 447 uint32_t RESERVED1; /*!< Reserved, 0x18 */
<> 148:21d94c44109e 448 __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */
<> 148:21d94c44109e 449 __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */
<> 148:21d94c44109e 450 __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */
<> 148:21d94c44109e 451 __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */
<> 148:21d94c44109e 452 __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */
<> 148:21d94c44109e 453 __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */
<> 148:21d94c44109e 454 __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */
<> 148:21d94c44109e 455 __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */
<> 148:21d94c44109e 456 __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */
<> 148:21d94c44109e 457 } RI_TypeDef;
<> 148:21d94c44109e 458
<> 148:21d94c44109e 459 /**
<> 148:21d94c44109e 460 * @brief Real-Time Clock
<> 148:21d94c44109e 461 */
<> 148:21d94c44109e 462 typedef struct
<> 148:21d94c44109e 463 {
<> 148:21d94c44109e 464 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
<> 148:21d94c44109e 465 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
<> 148:21d94c44109e 466 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
<> 148:21d94c44109e 467 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
<> 148:21d94c44109e 468 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
<> 148:21d94c44109e 469 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
<> 148:21d94c44109e 470 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
<> 148:21d94c44109e 471 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
<> 148:21d94c44109e 472 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
<> 148:21d94c44109e 473 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
<> 148:21d94c44109e 474 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
<> 148:21d94c44109e 475 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
<> 148:21d94c44109e 476 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
<> 148:21d94c44109e 477 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
<> 148:21d94c44109e 478 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
<> 148:21d94c44109e 479 __IO uint32_t CALR; /*!< RRTC calibration register, Address offset: 0x3C */
<> 148:21d94c44109e 480 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
<> 148:21d94c44109e 481 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
<> 148:21d94c44109e 482 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
<> 148:21d94c44109e 483 uint32_t RESERVED7; /*!< Reserved, 0x4C */
<> 148:21d94c44109e 484 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
<> 148:21d94c44109e 485 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
<> 148:21d94c44109e 486 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
<> 148:21d94c44109e 487 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
<> 148:21d94c44109e 488 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
<> 148:21d94c44109e 489 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
<> 148:21d94c44109e 490 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
<> 148:21d94c44109e 491 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
<> 148:21d94c44109e 492 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
<> 148:21d94c44109e 493 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
<> 148:21d94c44109e 494 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
<> 148:21d94c44109e 495 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
<> 148:21d94c44109e 496 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
<> 148:21d94c44109e 497 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
<> 148:21d94c44109e 498 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
<> 148:21d94c44109e 499 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
<> 148:21d94c44109e 500 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
<> 148:21d94c44109e 501 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
<> 148:21d94c44109e 502 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
<> 148:21d94c44109e 503 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
<> 148:21d94c44109e 504 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
<> 148:21d94c44109e 505 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
<> 148:21d94c44109e 506 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
<> 148:21d94c44109e 507 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
<> 148:21d94c44109e 508 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
<> 148:21d94c44109e 509 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
<> 148:21d94c44109e 510 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
<> 148:21d94c44109e 511 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
<> 148:21d94c44109e 512 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
<> 148:21d94c44109e 513 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
<> 148:21d94c44109e 514 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
<> 148:21d94c44109e 515 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
<> 148:21d94c44109e 516 } RTC_TypeDef;
<> 148:21d94c44109e 517
<> 148:21d94c44109e 518 /**
<> 148:21d94c44109e 519 * @brief Serial Peripheral Interface
<> 148:21d94c44109e 520 */
<> 148:21d94c44109e 521
<> 148:21d94c44109e 522 typedef struct
<> 148:21d94c44109e 523 {
<> 148:21d94c44109e 524 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
<> 148:21d94c44109e 525 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
<> 148:21d94c44109e 526 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
<> 148:21d94c44109e 527 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
<> 148:21d94c44109e 528 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
<> 148:21d94c44109e 529 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
<> 148:21d94c44109e 530 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
<> 148:21d94c44109e 531 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
<> 148:21d94c44109e 532 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
<> 148:21d94c44109e 533 } SPI_TypeDef;
<> 148:21d94c44109e 534
<> 148:21d94c44109e 535 /**
<> 148:21d94c44109e 536 * @brief TIM
<> 148:21d94c44109e 537 */
<> 148:21d94c44109e 538 typedef struct
<> 148:21d94c44109e 539 {
<> 148:21d94c44109e 540 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
<> 148:21d94c44109e 541 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
<> 148:21d94c44109e 542 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
<> 148:21d94c44109e 543 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
<> 148:21d94c44109e 544 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
<> 148:21d94c44109e 545 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
<> 148:21d94c44109e 546 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
<> 148:21d94c44109e 547 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
<> 148:21d94c44109e 548 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
<> 148:21d94c44109e 549 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
<> 148:21d94c44109e 550 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
<> 148:21d94c44109e 551 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
<> 148:21d94c44109e 552 uint32_t RESERVED12; /*!< Reserved, 0x30 */
<> 148:21d94c44109e 553 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
<> 148:21d94c44109e 554 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
<> 148:21d94c44109e 555 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
<> 148:21d94c44109e 556 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
<> 148:21d94c44109e 557 uint32_t RESERVED17; /*!< Reserved, 0x44 */
<> 148:21d94c44109e 558 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
<> 148:21d94c44109e 559 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
<> 148:21d94c44109e 560 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
<> 148:21d94c44109e 561 } TIM_TypeDef;
<> 148:21d94c44109e 562 /**
<> 148:21d94c44109e 563 * @brief Universal Synchronous Asynchronous Receiver Transmitter
<> 148:21d94c44109e 564 */
<> 148:21d94c44109e 565
<> 148:21d94c44109e 566 typedef struct
<> 148:21d94c44109e 567 {
<> 148:21d94c44109e 568 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
<> 148:21d94c44109e 569 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
<> 148:21d94c44109e 570 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
<> 148:21d94c44109e 571 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
<> 148:21d94c44109e 572 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
<> 148:21d94c44109e 573 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
<> 148:21d94c44109e 574 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
<> 148:21d94c44109e 575 } USART_TypeDef;
<> 148:21d94c44109e 576
<> 148:21d94c44109e 577 /**
<> 148:21d94c44109e 578 * @brief Universal Serial Bus Full Speed Device
<> 148:21d94c44109e 579 */
<> 148:21d94c44109e 580
<> 148:21d94c44109e 581 typedef struct
<> 148:21d94c44109e 582 {
<> 148:21d94c44109e 583 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
<> 148:21d94c44109e 584 __IO uint16_t RESERVED0; /*!< Reserved */
<> 148:21d94c44109e 585 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
<> 148:21d94c44109e 586 __IO uint16_t RESERVED1; /*!< Reserved */
<> 148:21d94c44109e 587 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
<> 148:21d94c44109e 588 __IO uint16_t RESERVED2; /*!< Reserved */
<> 148:21d94c44109e 589 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
<> 148:21d94c44109e 590 __IO uint16_t RESERVED3; /*!< Reserved */
<> 148:21d94c44109e 591 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
<> 148:21d94c44109e 592 __IO uint16_t RESERVED4; /*!< Reserved */
<> 148:21d94c44109e 593 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
<> 148:21d94c44109e 594 __IO uint16_t RESERVED5; /*!< Reserved */
<> 148:21d94c44109e 595 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
<> 148:21d94c44109e 596 __IO uint16_t RESERVED6; /*!< Reserved */
<> 148:21d94c44109e 597 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
<> 148:21d94c44109e 598 __IO uint16_t RESERVED7[17]; /*!< Reserved */
<> 148:21d94c44109e 599 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
<> 148:21d94c44109e 600 __IO uint16_t RESERVED8; /*!< Reserved */
<> 148:21d94c44109e 601 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
<> 148:21d94c44109e 602 __IO uint16_t RESERVED9; /*!< Reserved */
<> 148:21d94c44109e 603 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
<> 148:21d94c44109e 604 __IO uint16_t RESERVEDA; /*!< Reserved */
<> 148:21d94c44109e 605 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
<> 148:21d94c44109e 606 __IO uint16_t RESERVEDB; /*!< Reserved */
<> 148:21d94c44109e 607 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
<> 148:21d94c44109e 608 __IO uint16_t RESERVEDC; /*!< Reserved */
<> 148:21d94c44109e 609 } USB_TypeDef;
<> 148:21d94c44109e 610
<> 148:21d94c44109e 611 /**
<> 148:21d94c44109e 612 * @brief Window WATCHDOG
<> 148:21d94c44109e 613 */
<> 148:21d94c44109e 614 typedef struct
<> 148:21d94c44109e 615 {
<> 148:21d94c44109e 616 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
<> 148:21d94c44109e 617 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
<> 148:21d94c44109e 618 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
<> 148:21d94c44109e 619 } WWDG_TypeDef;
<> 148:21d94c44109e 620
<> 148:21d94c44109e 621 /**
<> 148:21d94c44109e 622 * @brief Universal Serial Bus Full Speed Device
<> 148:21d94c44109e 623 */
<> 148:21d94c44109e 624 /**
<> 148:21d94c44109e 625 * @}
<> 148:21d94c44109e 626 */
<> 148:21d94c44109e 627
<> 148:21d94c44109e 628 /** @addtogroup Peripheral_memory_map
<> 148:21d94c44109e 629 * @{
<> 148:21d94c44109e 630 */
<> 148:21d94c44109e 631
<> 148:21d94c44109e 632 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */
<> 148:21d94c44109e 633 #define FLASH_EEPROM_BASE ((uint32_t)(FLASH_BASE + 0x80000U)) /*!< FLASH EEPROM base address in the alias region */
<> 148:21d94c44109e 634 #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */
<> 148:21d94c44109e 635 #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */
<> 148:21d94c44109e 636 #define SRAM_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM base address in the bit-band region */
<> 148:21d94c44109e 637 #define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
<> 148:21d94c44109e 638 #define FLASH_END ((uint32_t)0x0803FFFFU) /*!< Program end FLASH address for Cat3 */
<> 148:21d94c44109e 639 #define FLASH_EEPROM_END ((uint32_t)0x08081FFFU) /*!< FLASH EEPROM end address (8KB) */
<> 148:21d94c44109e 640
<> 148:21d94c44109e 641 /*!< Peripheral memory map */
<> 148:21d94c44109e 642 #define APB1PERIPH_BASE PERIPH_BASE
<> 148:21d94c44109e 643 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
<> 148:21d94c44109e 644 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
<> 148:21d94c44109e 645
<> 148:21d94c44109e 646 /*!< APB1 peripherals */
<> 148:21d94c44109e 647 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U)
<> 148:21d94c44109e 648 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U)
<> 148:21d94c44109e 649 #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U)
<> 148:21d94c44109e 650 #define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00U)
<> 148:21d94c44109e 651 #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000U)
<> 148:21d94c44109e 652 #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400U)
<> 148:21d94c44109e 653 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800U)
<> 148:21d94c44109e 654 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U)
<> 148:21d94c44109e 655 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)
<> 148:21d94c44109e 656 #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U)
<> 148:21d94c44109e 657 #define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00U)
<> 148:21d94c44109e 658 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400U)
<> 148:21d94c44109e 659 #define USART3_BASE (APB1PERIPH_BASE + 0x00004800U)
<> 148:21d94c44109e 660 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U)
<> 148:21d94c44109e 661 #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800U)
<> 148:21d94c44109e 662
<> 148:21d94c44109e 663 /* USB device FS */
<> 148:21d94c44109e 664 #define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */
<> 148:21d94c44109e 665 #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */
<> 148:21d94c44109e 666
<> 148:21d94c44109e 667 /* USB device FS SRAM */
<> 148:21d94c44109e 668 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000U)
<> 148:21d94c44109e 669 #define DAC_BASE (APB1PERIPH_BASE + 0x00007400U)
<> 148:21d94c44109e 670 #define COMP_BASE (APB1PERIPH_BASE + 0x00007C00U)
<> 148:21d94c44109e 671 #define RI_BASE (APB1PERIPH_BASE + 0x00007C04U)
<> 148:21d94c44109e 672 #define OPAMP_BASE (APB1PERIPH_BASE + 0x00007C5CU)
<> 148:21d94c44109e 673
<> 148:21d94c44109e 674 /*!< APB2 peripherals */
<> 148:21d94c44109e 675 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000U)
<> 148:21d94c44109e 676 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U)
<> 148:21d94c44109e 677 #define TIM9_BASE (APB2PERIPH_BASE + 0x00000800U)
<> 148:21d94c44109e 678 #define TIM10_BASE (APB2PERIPH_BASE + 0x00000C00U)
<> 148:21d94c44109e 679 #define TIM11_BASE (APB2PERIPH_BASE + 0x00001000U)
<> 148:21d94c44109e 680 #define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U)
<> 148:21d94c44109e 681 #define ADC_BASE (APB2PERIPH_BASE + 0x00002700U)
<> 148:21d94c44109e 682 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U)
<> 148:21d94c44109e 683 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800U)
<> 148:21d94c44109e 684
<> 148:21d94c44109e 685 /*!< AHB peripherals */
<> 148:21d94c44109e 686 #define GPIOA_BASE (AHBPERIPH_BASE + 0x00000000U)
<> 148:21d94c44109e 687 #define GPIOB_BASE (AHBPERIPH_BASE + 0x00000400U)
<> 148:21d94c44109e 688 #define GPIOC_BASE (AHBPERIPH_BASE + 0x00000800U)
<> 148:21d94c44109e 689 #define GPIOD_BASE (AHBPERIPH_BASE + 0x00000C00U)
<> 148:21d94c44109e 690 #define GPIOE_BASE (AHBPERIPH_BASE + 0x00001000U)
<> 148:21d94c44109e 691 #define GPIOH_BASE (AHBPERIPH_BASE + 0x00001400U)
<> 148:21d94c44109e 692 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
<> 148:21d94c44109e 693 #define RCC_BASE (AHBPERIPH_BASE + 0x00003800U)
<> 148:21d94c44109e 694 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00U) /*!< FLASH registers base address */
<> 148:21d94c44109e 695 #define OB_BASE ((uint32_t)0x1FF80000U) /*!< FLASH Option Bytes base address */
<> 148:21d94c44109e 696 #define FLASHSIZE_BASE ((uint32_t)0x1FF800CCU) /*!< FLASH Size register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
<> 148:21d94c44109e 697 #define UID_BASE ((uint32_t)0x1FF800D0U) /*!< Unique device ID register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
<> 148:21d94c44109e 698 #define DMA1_BASE (AHBPERIPH_BASE + 0x00006000U)
<> 148:21d94c44109e 699 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008U)
<> 148:21d94c44109e 700 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU)
<> 148:21d94c44109e 701 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030U)
<> 148:21d94c44109e 702 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044U)
<> 148:21d94c44109e 703 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058U)
<> 148:21d94c44109e 704 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CU)
<> 148:21d94c44109e 705 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080U)
<> 148:21d94c44109e 706 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400U)
<> 148:21d94c44109e 707 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008U)
<> 148:21d94c44109e 708 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CU)
<> 148:21d94c44109e 709 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030U)
<> 148:21d94c44109e 710 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044U)
<> 148:21d94c44109e 711 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058U)
<> 148:21d94c44109e 712 #define DBGMCU_BASE ((uint32_t)0xE0042000U) /*!< Debug MCU registers base address */
<> 148:21d94c44109e 713
<> 148:21d94c44109e 714 /**
<> 148:21d94c44109e 715 * @}
<> 148:21d94c44109e 716 */
<> 148:21d94c44109e 717
<> 148:21d94c44109e 718 /** @addtogroup Peripheral_declaration
<> 148:21d94c44109e 719 * @{
<> 148:21d94c44109e 720 */
<> 148:21d94c44109e 721
<> 148:21d94c44109e 722 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
<> 148:21d94c44109e 723 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
<> 148:21d94c44109e 724 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
<> 148:21d94c44109e 725 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
<> 148:21d94c44109e 726 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
<> 148:21d94c44109e 727 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
<> 148:21d94c44109e 728 #define RTC ((RTC_TypeDef *) RTC_BASE)
<> 148:21d94c44109e 729 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
<> 148:21d94c44109e 730 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
<> 148:21d94c44109e 731 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
<> 148:21d94c44109e 732 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
<> 148:21d94c44109e 733 #define USART2 ((USART_TypeDef *) USART2_BASE)
<> 148:21d94c44109e 734 #define USART3 ((USART_TypeDef *) USART3_BASE)
<> 148:21d94c44109e 735 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
<> 148:21d94c44109e 736 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
<> 148:21d94c44109e 737 /* USB device FS */
<> 148:21d94c44109e 738 #define USB ((USB_TypeDef *) USB_BASE)
<> 148:21d94c44109e 739 /* USB device FS SRAM */
<> 148:21d94c44109e 740 #define PWR ((PWR_TypeDef *) PWR_BASE)
<> 148:21d94c44109e 741
<> 148:21d94c44109e 742 #define DAC1 ((DAC_TypeDef *) DAC_BASE)
<> 148:21d94c44109e 743 /* Legacy define */
<> 148:21d94c44109e 744 #define DAC DAC1
<> 148:21d94c44109e 745
<> 148:21d94c44109e 746 #define COMP ((COMP_TypeDef *) COMP_BASE) /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */
<> 148:21d94c44109e 747 #define COMP1 ((COMP_TypeDef *) COMP_BASE) /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
<> 148:21d94c44109e 748 #define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
<> 148:21d94c44109e 749 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP_BASE) /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */
<> 148:21d94c44109e 750
<> 148:21d94c44109e 751 #define RI ((RI_TypeDef *) RI_BASE)
<> 148:21d94c44109e 752
<> 148:21d94c44109e 753 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
<> 148:21d94c44109e 754 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP_BASE)
<> 148:21d94c44109e 755 #define OPAMP2 ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001U))
<> 148:21d94c44109e 756 #define OPAMP12_COMMON ((OPAMP_Common_TypeDef *) OPAMP_BASE)
<> 148:21d94c44109e 757 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
<> 148:21d94c44109e 758 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
<> 148:21d94c44109e 759 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
<> 148:21d94c44109e 760 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
<> 148:21d94c44109e 761 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
<> 148:21d94c44109e 762
<> 148:21d94c44109e 763 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
<> 148:21d94c44109e 764 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
<> 148:21d94c44109e 765 /* Legacy defines */
<> 148:21d94c44109e 766 #define ADC ADC1_COMMON
<> 148:21d94c44109e 767
<> 148:21d94c44109e 768 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
<> 148:21d94c44109e 769 #define USART1 ((USART_TypeDef *) USART1_BASE)
<> 148:21d94c44109e 770 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
<> 148:21d94c44109e 771 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
<> 148:21d94c44109e 772 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
<> 148:21d94c44109e 773 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
<> 148:21d94c44109e 774 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
<> 148:21d94c44109e 775 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
<> 148:21d94c44109e 776 #define CRC ((CRC_TypeDef *) CRC_BASE)
<> 148:21d94c44109e 777 #define RCC ((RCC_TypeDef *) RCC_BASE)
<> 148:21d94c44109e 778 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
<> 148:21d94c44109e 779 #define OB ((OB_TypeDef *) OB_BASE)
<> 148:21d94c44109e 780 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
<> 148:21d94c44109e 781 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
<> 148:21d94c44109e 782 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
<> 148:21d94c44109e 783 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
<> 148:21d94c44109e 784 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
<> 148:21d94c44109e 785 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
<> 148:21d94c44109e 786 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
<> 148:21d94c44109e 787 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
<> 148:21d94c44109e 788 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
<> 148:21d94c44109e 789 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
<> 148:21d94c44109e 790 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
<> 148:21d94c44109e 791 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
<> 148:21d94c44109e 792 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
<> 148:21d94c44109e 793 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
<> 148:21d94c44109e 794 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
<> 148:21d94c44109e 795
<> 148:21d94c44109e 796 /**
<> 148:21d94c44109e 797 * @}
<> 148:21d94c44109e 798 */
<> 148:21d94c44109e 799
<> 148:21d94c44109e 800 /** @addtogroup Exported_constants
<> 148:21d94c44109e 801 * @{
<> 148:21d94c44109e 802 */
<> 148:21d94c44109e 803
<> 148:21d94c44109e 804 /** @addtogroup Peripheral_Registers_Bits_Definition
<> 148:21d94c44109e 805 * @{
<> 148:21d94c44109e 806 */
<> 148:21d94c44109e 807
<> 148:21d94c44109e 808 /******************************************************************************/
<> 148:21d94c44109e 809 /* Peripheral Registers Bits Definition */
<> 148:21d94c44109e 810 /******************************************************************************/
<> 148:21d94c44109e 811 /******************************************************************************/
<> 148:21d94c44109e 812 /* */
<> 148:21d94c44109e 813 /* Analog to Digital Converter (ADC) */
<> 148:21d94c44109e 814 /* */
<> 148:21d94c44109e 815 /******************************************************************************/
<> 148:21d94c44109e 816
<> 148:21d94c44109e 817 /******************** Bit definition for ADC_SR register ********************/
<> 148:21d94c44109e 818 #define ADC_SR_AWD_Pos (0U)
<> 148:21d94c44109e 819 #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 820 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */
<> 148:21d94c44109e 821 #define ADC_SR_EOCS_Pos (1U)
<> 148:21d94c44109e 822 #define ADC_SR_EOCS_Msk (0x1U << ADC_SR_EOCS_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 823 #define ADC_SR_EOCS ADC_SR_EOCS_Msk /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */
<> 148:21d94c44109e 824 #define ADC_SR_JEOS_Pos (2U)
<> 148:21d94c44109e 825 #define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 826 #define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
<> 148:21d94c44109e 827 #define ADC_SR_JSTRT_Pos (3U)
<> 148:21d94c44109e 828 #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 829 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */
<> 148:21d94c44109e 830 #define ADC_SR_STRT_Pos (4U)
<> 148:21d94c44109e 831 #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 832 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */
<> 148:21d94c44109e 833 #define ADC_SR_OVR_Pos (5U)
<> 148:21d94c44109e 834 #define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 835 #define ADC_SR_OVR ADC_SR_OVR_Msk /*!< ADC group regular overrun flag */
<> 148:21d94c44109e 836 #define ADC_SR_ADONS_Pos (6U)
<> 148:21d94c44109e 837 #define ADC_SR_ADONS_Msk (0x1U << ADC_SR_ADONS_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 838 #define ADC_SR_ADONS ADC_SR_ADONS_Msk /*!< ADC ready flag */
<> 148:21d94c44109e 839 #define ADC_SR_RCNR_Pos (8U)
<> 148:21d94c44109e 840 #define ADC_SR_RCNR_Msk (0x1U << ADC_SR_RCNR_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 841 #define ADC_SR_RCNR ADC_SR_RCNR_Msk /*!< ADC group regular not ready flag */
<> 148:21d94c44109e 842 #define ADC_SR_JCNR_Pos (9U)
<> 148:21d94c44109e 843 #define ADC_SR_JCNR_Msk (0x1U << ADC_SR_JCNR_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 844 #define ADC_SR_JCNR ADC_SR_JCNR_Msk /*!< ADC group injected not ready flag */
<> 148:21d94c44109e 845
<> 148:21d94c44109e 846 /* Legacy defines */
<> 148:21d94c44109e 847 #define ADC_SR_EOC (ADC_SR_EOCS)
<> 148:21d94c44109e 848 #define ADC_SR_JEOC (ADC_SR_JEOS)
<> 148:21d94c44109e 849
<> 148:21d94c44109e 850 /******************* Bit definition for ADC_CR1 register ********************/
<> 148:21d94c44109e 851 #define ADC_CR1_AWDCH_Pos (0U)
<> 148:21d94c44109e 852 #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
<> 148:21d94c44109e 853 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
<> 148:21d94c44109e 854 #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 855 #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 856 #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 857 #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 858 #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 859
<> 148:21d94c44109e 860 #define ADC_CR1_EOCSIE_Pos (5U)
<> 148:21d94c44109e 861 #define ADC_CR1_EOCSIE_Msk (0x1U << ADC_CR1_EOCSIE_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 862 #define ADC_CR1_EOCSIE ADC_CR1_EOCSIE_Msk /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */
<> 148:21d94c44109e 863 #define ADC_CR1_AWDIE_Pos (6U)
<> 148:21d94c44109e 864 #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 865 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */
<> 148:21d94c44109e 866 #define ADC_CR1_JEOSIE_Pos (7U)
<> 148:21d94c44109e 867 #define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 868 #define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
<> 148:21d94c44109e 869 #define ADC_CR1_SCAN_Pos (8U)
<> 148:21d94c44109e 870 #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 871 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */
<> 148:21d94c44109e 872 #define ADC_CR1_AWDSGL_Pos (9U)
<> 148:21d94c44109e 873 #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 874 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
<> 148:21d94c44109e 875 #define ADC_CR1_JAUTO_Pos (10U)
<> 148:21d94c44109e 876 #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 877 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
<> 148:21d94c44109e 878 #define ADC_CR1_DISCEN_Pos (11U)
<> 148:21d94c44109e 879 #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 880 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
<> 148:21d94c44109e 881 #define ADC_CR1_JDISCEN_Pos (12U)
<> 148:21d94c44109e 882 #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 883 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
<> 148:21d94c44109e 884
<> 148:21d94c44109e 885 #define ADC_CR1_DISCNUM_Pos (13U)
<> 148:21d94c44109e 886 #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
<> 148:21d94c44109e 887 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
<> 148:21d94c44109e 888 #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 889 #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 890 #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 891
<> 148:21d94c44109e 892 #define ADC_CR1_PDD_Pos (16U)
<> 148:21d94c44109e 893 #define ADC_CR1_PDD_Msk (0x1U << ADC_CR1_PDD_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 894 #define ADC_CR1_PDD ADC_CR1_PDD_Msk /*!< ADC power down during auto delay phase */
<> 148:21d94c44109e 895 #define ADC_CR1_PDI_Pos (17U)
<> 148:21d94c44109e 896 #define ADC_CR1_PDI_Msk (0x1U << ADC_CR1_PDI_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 897 #define ADC_CR1_PDI ADC_CR1_PDI_Msk /*!< ADC power down during idle phase */
<> 148:21d94c44109e 898
<> 148:21d94c44109e 899 #define ADC_CR1_JAWDEN_Pos (22U)
<> 148:21d94c44109e 900 #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 901 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
<> 148:21d94c44109e 902 #define ADC_CR1_AWDEN_Pos (23U)
<> 148:21d94c44109e 903 #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 904 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
<> 148:21d94c44109e 905
<> 148:21d94c44109e 906 #define ADC_CR1_RES_Pos (24U)
<> 148:21d94c44109e 907 #define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
<> 148:21d94c44109e 908 #define ADC_CR1_RES ADC_CR1_RES_Msk /*!< ADC resolution */
<> 148:21d94c44109e 909 #define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
<> 148:21d94c44109e 910 #define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
<> 148:21d94c44109e 911
<> 148:21d94c44109e 912 #define ADC_CR1_OVRIE_Pos (26U)
<> 148:21d94c44109e 913 #define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
<> 148:21d94c44109e 914 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!< ADC group regular overrun interrupt */
<> 148:21d94c44109e 915
<> 148:21d94c44109e 916 /* Legacy defines */
<> 148:21d94c44109e 917 #define ADC_CR1_EOCIE (ADC_CR1_EOCSIE)
<> 148:21d94c44109e 918 #define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
<> 148:21d94c44109e 919
<> 148:21d94c44109e 920 /******************* Bit definition for ADC_CR2 register ********************/
<> 148:21d94c44109e 921 #define ADC_CR2_ADON_Pos (0U)
<> 148:21d94c44109e 922 #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 923 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */
<> 148:21d94c44109e 924 #define ADC_CR2_CONT_Pos (1U)
<> 148:21d94c44109e 925 #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 926 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */
<> 148:21d94c44109e 927 #define ADC_CR2_CFG_Pos (2U)
<> 148:21d94c44109e 928 #define ADC_CR2_CFG_Msk (0x1U << ADC_CR2_CFG_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 929 #define ADC_CR2_CFG ADC_CR2_CFG_Msk /*!< ADC channels bank selection */
<> 148:21d94c44109e 930
<> 148:21d94c44109e 931 #define ADC_CR2_DELS_Pos (4U)
<> 148:21d94c44109e 932 #define ADC_CR2_DELS_Msk (0x7U << ADC_CR2_DELS_Pos) /*!< 0x00000070 */
<> 148:21d94c44109e 933 #define ADC_CR2_DELS ADC_CR2_DELS_Msk /*!< ADC auto delay selection */
<> 148:21d94c44109e 934 #define ADC_CR2_DELS_0 (0x1U << ADC_CR2_DELS_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 935 #define ADC_CR2_DELS_1 (0x2U << ADC_CR2_DELS_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 936 #define ADC_CR2_DELS_2 (0x4U << ADC_CR2_DELS_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 937
<> 148:21d94c44109e 938 #define ADC_CR2_DMA_Pos (8U)
<> 148:21d94c44109e 939 #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 940 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
<> 148:21d94c44109e 941 #define ADC_CR2_DDS_Pos (9U)
<> 148:21d94c44109e 942 #define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 943 #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!< ADC DMA transfer configuration */
<> 148:21d94c44109e 944 #define ADC_CR2_EOCS_Pos (10U)
<> 148:21d94c44109e 945 #define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 946 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */
<> 148:21d94c44109e 947 #define ADC_CR2_ALIGN_Pos (11U)
<> 148:21d94c44109e 948 #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 949 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
<> 148:21d94c44109e 950
<> 148:21d94c44109e 951 #define ADC_CR2_JEXTSEL_Pos (16U)
<> 148:21d94c44109e 952 #define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
<> 148:21d94c44109e 953 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */
<> 148:21d94c44109e 954 #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 955 #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 956 #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 957 #define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 958
<> 148:21d94c44109e 959 #define ADC_CR2_JEXTEN_Pos (20U)
<> 148:21d94c44109e 960 #define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
<> 148:21d94c44109e 961 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
<> 148:21d94c44109e 962 #define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 963 #define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 964
<> 148:21d94c44109e 965 #define ADC_CR2_JSWSTART_Pos (22U)
<> 148:21d94c44109e 966 #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 967 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */
<> 148:21d94c44109e 968
<> 148:21d94c44109e 969 #define ADC_CR2_EXTSEL_Pos (24U)
<> 148:21d94c44109e 970 #define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
<> 148:21d94c44109e 971 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */
<> 148:21d94c44109e 972 #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
<> 148:21d94c44109e 973 #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
<> 148:21d94c44109e 974 #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
<> 148:21d94c44109e 975 #define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
<> 148:21d94c44109e 976
<> 148:21d94c44109e 977 #define ADC_CR2_EXTEN_Pos (28U)
<> 148:21d94c44109e 978 #define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
<> 148:21d94c44109e 979 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!< ADC group regular external trigger polarity */
<> 148:21d94c44109e 980 #define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
<> 148:21d94c44109e 981 #define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
<> 148:21d94c44109e 982
<> 148:21d94c44109e 983 #define ADC_CR2_SWSTART_Pos (30U)
<> 148:21d94c44109e 984 #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
<> 148:21d94c44109e 985 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */
<> 148:21d94c44109e 986
<> 148:21d94c44109e 987 /****************** Bit definition for ADC_SMPR1 register *******************/
<> 148:21d94c44109e 988 #define ADC_SMPR1_SMP20_Pos (0U)
<> 148:21d94c44109e 989 #define ADC_SMPR1_SMP20_Msk (0x7U << ADC_SMPR1_SMP20_Pos) /*!< 0x00000007 */
<> 148:21d94c44109e 990 #define ADC_SMPR1_SMP20 ADC_SMPR1_SMP20_Msk /*!< ADC channel 20 sampling time selection */
<> 148:21d94c44109e 991 #define ADC_SMPR1_SMP20_0 (0x1U << ADC_SMPR1_SMP20_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 992 #define ADC_SMPR1_SMP20_1 (0x2U << ADC_SMPR1_SMP20_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 993 #define ADC_SMPR1_SMP20_2 (0x4U << ADC_SMPR1_SMP20_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 994
<> 148:21d94c44109e 995 #define ADC_SMPR1_SMP21_Pos (3U)
<> 148:21d94c44109e 996 #define ADC_SMPR1_SMP21_Msk (0x7U << ADC_SMPR1_SMP21_Pos) /*!< 0x00000038 */
<> 148:21d94c44109e 997 #define ADC_SMPR1_SMP21 ADC_SMPR1_SMP21_Msk /*!< ADC channel 21 sampling time selection */
<> 148:21d94c44109e 998 #define ADC_SMPR1_SMP21_0 (0x1U << ADC_SMPR1_SMP21_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 999 #define ADC_SMPR1_SMP21_1 (0x2U << ADC_SMPR1_SMP21_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 1000 #define ADC_SMPR1_SMP21_2 (0x4U << ADC_SMPR1_SMP21_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 1001
<> 148:21d94c44109e 1002 #define ADC_SMPR1_SMP22_Pos (6U)
<> 148:21d94c44109e 1003 #define ADC_SMPR1_SMP22_Msk (0x7U << ADC_SMPR1_SMP22_Pos) /*!< 0x000001C0 */
<> 148:21d94c44109e 1004 #define ADC_SMPR1_SMP22 ADC_SMPR1_SMP22_Msk /*!< ADC channel 22 sampling time selection */
<> 148:21d94c44109e 1005 #define ADC_SMPR1_SMP22_0 (0x1U << ADC_SMPR1_SMP22_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 1006 #define ADC_SMPR1_SMP22_1 (0x2U << ADC_SMPR1_SMP22_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 1007 #define ADC_SMPR1_SMP22_2 (0x4U << ADC_SMPR1_SMP22_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 1008
<> 148:21d94c44109e 1009 #define ADC_SMPR1_SMP23_Pos (9U)
<> 148:21d94c44109e 1010 #define ADC_SMPR1_SMP23_Msk (0x7U << ADC_SMPR1_SMP23_Pos) /*!< 0x00000E00 */
<> 148:21d94c44109e 1011 #define ADC_SMPR1_SMP23 ADC_SMPR1_SMP23_Msk /*!< ADC channel 23 sampling time selection */
<> 148:21d94c44109e 1012 #define ADC_SMPR1_SMP23_0 (0x1U << ADC_SMPR1_SMP23_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 1013 #define ADC_SMPR1_SMP23_1 (0x2U << ADC_SMPR1_SMP23_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 1014 #define ADC_SMPR1_SMP23_2 (0x4U << ADC_SMPR1_SMP23_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 1015
<> 148:21d94c44109e 1016 #define ADC_SMPR1_SMP24_Pos (12U)
<> 148:21d94c44109e 1017 #define ADC_SMPR1_SMP24_Msk (0x7U << ADC_SMPR1_SMP24_Pos) /*!< 0x00007000 */
<> 148:21d94c44109e 1018 #define ADC_SMPR1_SMP24 ADC_SMPR1_SMP24_Msk /*!< ADC channel 24 sampling time selection */
<> 148:21d94c44109e 1019 #define ADC_SMPR1_SMP24_0 (0x1U << ADC_SMPR1_SMP24_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 1020 #define ADC_SMPR1_SMP24_1 (0x2U << ADC_SMPR1_SMP24_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 1021 #define ADC_SMPR1_SMP24_2 (0x4U << ADC_SMPR1_SMP24_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 1022
<> 148:21d94c44109e 1023 #define ADC_SMPR1_SMP25_Pos (15U)
<> 148:21d94c44109e 1024 #define ADC_SMPR1_SMP25_Msk (0x7U << ADC_SMPR1_SMP25_Pos) /*!< 0x00038000 */
<> 148:21d94c44109e 1025 #define ADC_SMPR1_SMP25 ADC_SMPR1_SMP25_Msk /*!< ADC channel 25 sampling time selection */
<> 148:21d94c44109e 1026 #define ADC_SMPR1_SMP25_0 (0x1U << ADC_SMPR1_SMP25_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 1027 #define ADC_SMPR1_SMP25_1 (0x2U << ADC_SMPR1_SMP25_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 1028 #define ADC_SMPR1_SMP25_2 (0x4U << ADC_SMPR1_SMP25_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 1029
<> 148:21d94c44109e 1030 #define ADC_SMPR1_SMP26_Pos (18U)
<> 148:21d94c44109e 1031 #define ADC_SMPR1_SMP26_Msk (0x7U << ADC_SMPR1_SMP26_Pos) /*!< 0x001C0000 */
<> 148:21d94c44109e 1032 #define ADC_SMPR1_SMP26 ADC_SMPR1_SMP26_Msk /*!< ADC channel 26 sampling time selection */
<> 148:21d94c44109e 1033 #define ADC_SMPR1_SMP26_0 (0x1U << ADC_SMPR1_SMP26_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 1034 #define ADC_SMPR1_SMP26_1 (0x2U << ADC_SMPR1_SMP26_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 1035 #define ADC_SMPR1_SMP26_2 (0x4U << ADC_SMPR1_SMP26_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 1036
<> 148:21d94c44109e 1037 /****************** Bit definition for ADC_SMPR2 register *******************/
<> 148:21d94c44109e 1038 #define ADC_SMPR2_SMP10_Pos (0U)
<> 148:21d94c44109e 1039 #define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
<> 148:21d94c44109e 1040 #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
<> 148:21d94c44109e 1041 #define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 1042 #define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 1043 #define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 1044
<> 148:21d94c44109e 1045 #define ADC_SMPR2_SMP11_Pos (3U)
<> 148:21d94c44109e 1046 #define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
<> 148:21d94c44109e 1047 #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
<> 148:21d94c44109e 1048 #define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 1049 #define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 1050 #define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 1051
<> 148:21d94c44109e 1052 #define ADC_SMPR2_SMP12_Pos (6U)
<> 148:21d94c44109e 1053 #define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
<> 148:21d94c44109e 1054 #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
<> 148:21d94c44109e 1055 #define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 1056 #define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 1057 #define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 1058
<> 148:21d94c44109e 1059 #define ADC_SMPR2_SMP13_Pos (9U)
<> 148:21d94c44109e 1060 #define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
<> 148:21d94c44109e 1061 #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
<> 148:21d94c44109e 1062 #define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 1063 #define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 1064 #define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 1065
<> 148:21d94c44109e 1066 #define ADC_SMPR2_SMP14_Pos (12U)
<> 148:21d94c44109e 1067 #define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
<> 148:21d94c44109e 1068 #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
<> 148:21d94c44109e 1069 #define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 1070 #define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 1071 #define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 1072
<> 148:21d94c44109e 1073 #define ADC_SMPR2_SMP15_Pos (15U)
<> 148:21d94c44109e 1074 #define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
<> 148:21d94c44109e 1075 #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 5 sampling time selection */
<> 148:21d94c44109e 1076 #define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 1077 #define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 1078 #define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 1079
<> 148:21d94c44109e 1080 #define ADC_SMPR2_SMP16_Pos (18U)
<> 148:21d94c44109e 1081 #define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
<> 148:21d94c44109e 1082 #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
<> 148:21d94c44109e 1083 #define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 1084 #define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 1085 #define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 1086
<> 148:21d94c44109e 1087 #define ADC_SMPR2_SMP17_Pos (21U)
<> 148:21d94c44109e 1088 #define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
<> 148:21d94c44109e 1089 #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
<> 148:21d94c44109e 1090 #define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 1091 #define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 1092 #define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 1093
<> 148:21d94c44109e 1094 #define ADC_SMPR2_SMP18_Pos (24U)
<> 148:21d94c44109e 1095 #define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
<> 148:21d94c44109e 1096 #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
<> 148:21d94c44109e 1097 #define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
<> 148:21d94c44109e 1098 #define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
<> 148:21d94c44109e 1099 #define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
<> 148:21d94c44109e 1100
<> 148:21d94c44109e 1101 #define ADC_SMPR2_SMP19_Pos (27U)
<> 148:21d94c44109e 1102 #define ADC_SMPR2_SMP19_Msk (0x7U << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */
<> 148:21d94c44109e 1103 #define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC channel 19 sampling time selection */
<> 148:21d94c44109e 1104 #define ADC_SMPR2_SMP19_0 (0x1U << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */
<> 148:21d94c44109e 1105 #define ADC_SMPR2_SMP19_1 (0x2U << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */
<> 148:21d94c44109e 1106 #define ADC_SMPR2_SMP19_2 (0x4U << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */
<> 148:21d94c44109e 1107
<> 148:21d94c44109e 1108 /****************** Bit definition for ADC_SMPR3 register *******************/
<> 148:21d94c44109e 1109 #define ADC_SMPR3_SMP0_Pos (0U)
<> 148:21d94c44109e 1110 #define ADC_SMPR3_SMP0_Msk (0x7U << ADC_SMPR3_SMP0_Pos) /*!< 0x00000007 */
<> 148:21d94c44109e 1111 #define ADC_SMPR3_SMP0 ADC_SMPR3_SMP0_Msk /*!< ADC channel 0 sampling time selection */
<> 148:21d94c44109e 1112 #define ADC_SMPR3_SMP0_0 (0x1U << ADC_SMPR3_SMP0_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 1113 #define ADC_SMPR3_SMP0_1 (0x2U << ADC_SMPR3_SMP0_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 1114 #define ADC_SMPR3_SMP0_2 (0x4U << ADC_SMPR3_SMP0_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 1115
<> 148:21d94c44109e 1116 #define ADC_SMPR3_SMP1_Pos (3U)
<> 148:21d94c44109e 1117 #define ADC_SMPR3_SMP1_Msk (0x7U << ADC_SMPR3_SMP1_Pos) /*!< 0x00000038 */
<> 148:21d94c44109e 1118 #define ADC_SMPR3_SMP1 ADC_SMPR3_SMP1_Msk /*!< ADC channel 1 sampling time selection */
<> 148:21d94c44109e 1119 #define ADC_SMPR3_SMP1_0 (0x1U << ADC_SMPR3_SMP1_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 1120 #define ADC_SMPR3_SMP1_1 (0x2U << ADC_SMPR3_SMP1_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 1121 #define ADC_SMPR3_SMP1_2 (0x4U << ADC_SMPR3_SMP1_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 1122
<> 148:21d94c44109e 1123 #define ADC_SMPR3_SMP2_Pos (6U)
<> 148:21d94c44109e 1124 #define ADC_SMPR3_SMP2_Msk (0x7U << ADC_SMPR3_SMP2_Pos) /*!< 0x000001C0 */
<> 148:21d94c44109e 1125 #define ADC_SMPR3_SMP2 ADC_SMPR3_SMP2_Msk /*!< ADC channel 2 sampling time selection */
<> 148:21d94c44109e 1126 #define ADC_SMPR3_SMP2_0 (0x1U << ADC_SMPR3_SMP2_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 1127 #define ADC_SMPR3_SMP2_1 (0x2U << ADC_SMPR3_SMP2_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 1128 #define ADC_SMPR3_SMP2_2 (0x4U << ADC_SMPR3_SMP2_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 1129
<> 148:21d94c44109e 1130 #define ADC_SMPR3_SMP3_Pos (9U)
<> 148:21d94c44109e 1131 #define ADC_SMPR3_SMP3_Msk (0x7U << ADC_SMPR3_SMP3_Pos) /*!< 0x00000E00 */
<> 148:21d94c44109e 1132 #define ADC_SMPR3_SMP3 ADC_SMPR3_SMP3_Msk /*!< ADC channel 3 sampling time selection */
<> 148:21d94c44109e 1133 #define ADC_SMPR3_SMP3_0 (0x1U << ADC_SMPR3_SMP3_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 1134 #define ADC_SMPR3_SMP3_1 (0x2U << ADC_SMPR3_SMP3_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 1135 #define ADC_SMPR3_SMP3_2 (0x4U << ADC_SMPR3_SMP3_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 1136
<> 148:21d94c44109e 1137 #define ADC_SMPR3_SMP4_Pos (12U)
<> 148:21d94c44109e 1138 #define ADC_SMPR3_SMP4_Msk (0x7U << ADC_SMPR3_SMP4_Pos) /*!< 0x00007000 */
<> 148:21d94c44109e 1139 #define ADC_SMPR3_SMP4 ADC_SMPR3_SMP4_Msk /*!< ADC channel 4 sampling time selection */
<> 148:21d94c44109e 1140 #define ADC_SMPR3_SMP4_0 (0x1U << ADC_SMPR3_SMP4_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 1141 #define ADC_SMPR3_SMP4_1 (0x2U << ADC_SMPR3_SMP4_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 1142 #define ADC_SMPR3_SMP4_2 (0x4U << ADC_SMPR3_SMP4_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 1143
<> 148:21d94c44109e 1144 #define ADC_SMPR3_SMP5_Pos (15U)
<> 148:21d94c44109e 1145 #define ADC_SMPR3_SMP5_Msk (0x7U << ADC_SMPR3_SMP5_Pos) /*!< 0x00038000 */
<> 148:21d94c44109e 1146 #define ADC_SMPR3_SMP5 ADC_SMPR3_SMP5_Msk /*!< ADC channel 5 sampling time selection */
<> 148:21d94c44109e 1147 #define ADC_SMPR3_SMP5_0 (0x1U << ADC_SMPR3_SMP5_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 1148 #define ADC_SMPR3_SMP5_1 (0x2U << ADC_SMPR3_SMP5_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 1149 #define ADC_SMPR3_SMP5_2 (0x4U << ADC_SMPR3_SMP5_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 1150
<> 148:21d94c44109e 1151 #define ADC_SMPR3_SMP6_Pos (18U)
<> 148:21d94c44109e 1152 #define ADC_SMPR3_SMP6_Msk (0x7U << ADC_SMPR3_SMP6_Pos) /*!< 0x001C0000 */
<> 148:21d94c44109e 1153 #define ADC_SMPR3_SMP6 ADC_SMPR3_SMP6_Msk /*!< ADC channel 6 sampling time selection */
<> 148:21d94c44109e 1154 #define ADC_SMPR3_SMP6_0 (0x1U << ADC_SMPR3_SMP6_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 1155 #define ADC_SMPR3_SMP6_1 (0x2U << ADC_SMPR3_SMP6_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 1156 #define ADC_SMPR3_SMP6_2 (0x4U << ADC_SMPR3_SMP6_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 1157
<> 148:21d94c44109e 1158 #define ADC_SMPR3_SMP7_Pos (21U)
<> 148:21d94c44109e 1159 #define ADC_SMPR3_SMP7_Msk (0x7U << ADC_SMPR3_SMP7_Pos) /*!< 0x00E00000 */
<> 148:21d94c44109e 1160 #define ADC_SMPR3_SMP7 ADC_SMPR3_SMP7_Msk /*!< ADC channel 7 sampling time selection */
<> 148:21d94c44109e 1161 #define ADC_SMPR3_SMP7_0 (0x1U << ADC_SMPR3_SMP7_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 1162 #define ADC_SMPR3_SMP7_1 (0x2U << ADC_SMPR3_SMP7_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 1163 #define ADC_SMPR3_SMP7_2 (0x4U << ADC_SMPR3_SMP7_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 1164
<> 148:21d94c44109e 1165 #define ADC_SMPR3_SMP8_Pos (24U)
<> 148:21d94c44109e 1166 #define ADC_SMPR3_SMP8_Msk (0x7U << ADC_SMPR3_SMP8_Pos) /*!< 0x07000000 */
<> 148:21d94c44109e 1167 #define ADC_SMPR3_SMP8 ADC_SMPR3_SMP8_Msk /*!< ADC channel 8 sampling time selection */
<> 148:21d94c44109e 1168 #define ADC_SMPR3_SMP8_0 (0x1U << ADC_SMPR3_SMP8_Pos) /*!< 0x01000000 */
<> 148:21d94c44109e 1169 #define ADC_SMPR3_SMP8_1 (0x2U << ADC_SMPR3_SMP8_Pos) /*!< 0x02000000 */
<> 148:21d94c44109e 1170 #define ADC_SMPR3_SMP8_2 (0x4U << ADC_SMPR3_SMP8_Pos) /*!< 0x04000000 */
<> 148:21d94c44109e 1171
<> 148:21d94c44109e 1172 #define ADC_SMPR3_SMP9_Pos (27U)
<> 148:21d94c44109e 1173 #define ADC_SMPR3_SMP9_Msk (0x7U << ADC_SMPR3_SMP9_Pos) /*!< 0x38000000 */
<> 148:21d94c44109e 1174 #define ADC_SMPR3_SMP9 ADC_SMPR3_SMP9_Msk /*!< ADC channel 9 sampling time selection */
<> 148:21d94c44109e 1175 #define ADC_SMPR3_SMP9_0 (0x1U << ADC_SMPR3_SMP9_Pos) /*!< 0x08000000 */
<> 148:21d94c44109e 1176 #define ADC_SMPR3_SMP9_1 (0x2U << ADC_SMPR3_SMP9_Pos) /*!< 0x10000000 */
<> 148:21d94c44109e 1177 #define ADC_SMPR3_SMP9_2 (0x4U << ADC_SMPR3_SMP9_Pos) /*!< 0x20000000 */
<> 148:21d94c44109e 1178
<> 148:21d94c44109e 1179 /****************** Bit definition for ADC_JOFR1 register *******************/
<> 148:21d94c44109e 1180 #define ADC_JOFR1_JOFFSET1_Pos (0U)
<> 148:21d94c44109e 1181 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
<> 148:21d94c44109e 1182 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */
<> 148:21d94c44109e 1183
<> 148:21d94c44109e 1184 /****************** Bit definition for ADC_JOFR2 register *******************/
<> 148:21d94c44109e 1185 #define ADC_JOFR2_JOFFSET2_Pos (0U)
<> 148:21d94c44109e 1186 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
<> 148:21d94c44109e 1187 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */
<> 148:21d94c44109e 1188
<> 148:21d94c44109e 1189 /****************** Bit definition for ADC_JOFR3 register *******************/
<> 148:21d94c44109e 1190 #define ADC_JOFR3_JOFFSET3_Pos (0U)
<> 148:21d94c44109e 1191 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
<> 148:21d94c44109e 1192 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */
<> 148:21d94c44109e 1193
<> 148:21d94c44109e 1194 /****************** Bit definition for ADC_JOFR4 register *******************/
<> 148:21d94c44109e 1195 #define ADC_JOFR4_JOFFSET4_Pos (0U)
<> 148:21d94c44109e 1196 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
<> 148:21d94c44109e 1197 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */
<> 148:21d94c44109e 1198
<> 148:21d94c44109e 1199 /******************* Bit definition for ADC_HTR register ********************/
<> 148:21d94c44109e 1200 #define ADC_HTR_HT_Pos (0U)
<> 148:21d94c44109e 1201 #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
<> 148:21d94c44109e 1202 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */
<> 148:21d94c44109e 1203
<> 148:21d94c44109e 1204 /******************* Bit definition for ADC_LTR register ********************/
<> 148:21d94c44109e 1205 #define ADC_LTR_LT_Pos (0U)
<> 148:21d94c44109e 1206 #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
<> 148:21d94c44109e 1207 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */
<> 148:21d94c44109e 1208
<> 148:21d94c44109e 1209 /******************* Bit definition for ADC_SQR1 register *******************/
<> 148:21d94c44109e 1210 #define ADC_SQR1_L_Pos (20U)
<> 148:21d94c44109e 1211 #define ADC_SQR1_L_Msk (0x1FU << ADC_SQR1_L_Pos) /*!< 0x01F00000 */
<> 148:21d94c44109e 1212 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
<> 148:21d94c44109e 1213 #define ADC_SQR1_L_0 (0x01U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 1214 #define ADC_SQR1_L_1 (0x02U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 1215 #define ADC_SQR1_L_2 (0x04U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 1216 #define ADC_SQR1_L_3 (0x08U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 1217 #define ADC_SQR1_L_4 (0x10U << ADC_SQR1_L_Pos) /*!< 0x01000000 */
<> 148:21d94c44109e 1218
<> 148:21d94c44109e 1219 #define ADC_SQR1_SQ28_Pos (15U)
<> 148:21d94c44109e 1220 #define ADC_SQR1_SQ28_Msk (0x1FU << ADC_SQR1_SQ28_Pos) /*!< 0x000F8000 */
<> 148:21d94c44109e 1221 #define ADC_SQR1_SQ28 ADC_SQR1_SQ28_Msk /*!< ADC group regular sequencer rank 28 */
<> 148:21d94c44109e 1222 #define ADC_SQR1_SQ28_0 (0x01U << ADC_SQR1_SQ28_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 1223 #define ADC_SQR1_SQ28_1 (0x02U << ADC_SQR1_SQ28_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 1224 #define ADC_SQR1_SQ28_2 (0x04U << ADC_SQR1_SQ28_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 1225 #define ADC_SQR1_SQ28_3 (0x08U << ADC_SQR1_SQ28_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 1226 #define ADC_SQR1_SQ28_4 (0x10U << ADC_SQR1_SQ28_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 1227
<> 148:21d94c44109e 1228 #define ADC_SQR1_SQ27_Pos (10U)
<> 148:21d94c44109e 1229 #define ADC_SQR1_SQ27_Msk (0x1FU << ADC_SQR1_SQ27_Pos) /*!< 0x00007C00 */
<> 148:21d94c44109e 1230 #define ADC_SQR1_SQ27 ADC_SQR1_SQ27_Msk /*!< ADC group regular sequencer rank 27 */
<> 148:21d94c44109e 1231 #define ADC_SQR1_SQ27_0 (0x01U << ADC_SQR1_SQ27_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 1232 #define ADC_SQR1_SQ27_1 (0x02U << ADC_SQR1_SQ27_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 1233 #define ADC_SQR1_SQ27_2 (0x04U << ADC_SQR1_SQ27_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 1234 #define ADC_SQR1_SQ27_3 (0x08U << ADC_SQR1_SQ27_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 1235 #define ADC_SQR1_SQ27_4 (0x10U << ADC_SQR1_SQ27_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 1236
<> 148:21d94c44109e 1237 #define ADC_SQR1_SQ26_Pos (5U)
<> 148:21d94c44109e 1238 #define ADC_SQR1_SQ26_Msk (0x1FU << ADC_SQR1_SQ26_Pos) /*!< 0x000003E0 */
<> 148:21d94c44109e 1239 #define ADC_SQR1_SQ26 ADC_SQR1_SQ26_Msk /*!< ADC group regular sequencer rank 26 */
<> 148:21d94c44109e 1240 #define ADC_SQR1_SQ26_0 (0x01U << ADC_SQR1_SQ26_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 1241 #define ADC_SQR1_SQ26_1 (0x02U << ADC_SQR1_SQ26_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 1242 #define ADC_SQR1_SQ26_2 (0x04U << ADC_SQR1_SQ26_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 1243 #define ADC_SQR1_SQ26_3 (0x08U << ADC_SQR1_SQ26_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 1244 #define ADC_SQR1_SQ26_4 (0x10U << ADC_SQR1_SQ26_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 1245
<> 148:21d94c44109e 1246 #define ADC_SQR1_SQ25_Pos (0U)
<> 148:21d94c44109e 1247 #define ADC_SQR1_SQ25_Msk (0x1FU << ADC_SQR1_SQ25_Pos) /*!< 0x0000001F */
<> 148:21d94c44109e 1248 #define ADC_SQR1_SQ25 ADC_SQR1_SQ25_Msk /*!< ADC group regular sequencer rank 25 */
<> 148:21d94c44109e 1249 #define ADC_SQR1_SQ25_0 (0x01U << ADC_SQR1_SQ25_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 1250 #define ADC_SQR1_SQ25_1 (0x02U << ADC_SQR1_SQ25_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 1251 #define ADC_SQR1_SQ25_2 (0x04U << ADC_SQR1_SQ25_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 1252 #define ADC_SQR1_SQ25_3 (0x08U << ADC_SQR1_SQ25_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 1253 #define ADC_SQR1_SQ25_4 (0x10U << ADC_SQR1_SQ25_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 1254
<> 148:21d94c44109e 1255 /******************* Bit definition for ADC_SQR2 register *******************/
<> 148:21d94c44109e 1256 #define ADC_SQR2_SQ19_Pos (0U)
<> 148:21d94c44109e 1257 #define ADC_SQR2_SQ19_Msk (0x1FU << ADC_SQR2_SQ19_Pos) /*!< 0x0000001F */
<> 148:21d94c44109e 1258 #define ADC_SQR2_SQ19 ADC_SQR2_SQ19_Msk /*!< ADC group regular sequencer rank 19 */
<> 148:21d94c44109e 1259 #define ADC_SQR2_SQ19_0 (0x01U << ADC_SQR2_SQ19_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 1260 #define ADC_SQR2_SQ19_1 (0x02U << ADC_SQR2_SQ19_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 1261 #define ADC_SQR2_SQ19_2 (0x04U << ADC_SQR2_SQ19_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 1262 #define ADC_SQR2_SQ19_3 (0x08U << ADC_SQR2_SQ19_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 1263 #define ADC_SQR2_SQ19_4 (0x10U << ADC_SQR2_SQ19_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 1264
<> 148:21d94c44109e 1265 #define ADC_SQR2_SQ20_Pos (5U)
<> 148:21d94c44109e 1266 #define ADC_SQR2_SQ20_Msk (0x1FU << ADC_SQR2_SQ20_Pos) /*!< 0x000003E0 */
<> 148:21d94c44109e 1267 #define ADC_SQR2_SQ20 ADC_SQR2_SQ20_Msk /*!< ADC group regular sequencer rank 20 */
<> 148:21d94c44109e 1268 #define ADC_SQR2_SQ20_0 (0x01U << ADC_SQR2_SQ20_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 1269 #define ADC_SQR2_SQ20_1 (0x02U << ADC_SQR2_SQ20_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 1270 #define ADC_SQR2_SQ20_2 (0x04U << ADC_SQR2_SQ20_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 1271 #define ADC_SQR2_SQ20_3 (0x08U << ADC_SQR2_SQ20_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 1272 #define ADC_SQR2_SQ20_4 (0x10U << ADC_SQR2_SQ20_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 1273
<> 148:21d94c44109e 1274 #define ADC_SQR2_SQ21_Pos (10U)
<> 148:21d94c44109e 1275 #define ADC_SQR2_SQ21_Msk (0x1FU << ADC_SQR2_SQ21_Pos) /*!< 0x00007C00 */
<> 148:21d94c44109e 1276 #define ADC_SQR2_SQ21 ADC_SQR2_SQ21_Msk /*!< ADC group regular sequencer rank 21 */
<> 148:21d94c44109e 1277 #define ADC_SQR2_SQ21_0 (0x01U << ADC_SQR2_SQ21_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 1278 #define ADC_SQR2_SQ21_1 (0x02U << ADC_SQR2_SQ21_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 1279 #define ADC_SQR2_SQ21_2 (0x04U << ADC_SQR2_SQ21_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 1280 #define ADC_SQR2_SQ21_3 (0x08U << ADC_SQR2_SQ21_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 1281 #define ADC_SQR2_SQ21_4 (0x10U << ADC_SQR2_SQ21_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 1282
<> 148:21d94c44109e 1283 #define ADC_SQR2_SQ22_Pos (15U)
<> 148:21d94c44109e 1284 #define ADC_SQR2_SQ22_Msk (0x1FU << ADC_SQR2_SQ22_Pos) /*!< 0x000F8000 */
<> 148:21d94c44109e 1285 #define ADC_SQR2_SQ22 ADC_SQR2_SQ22_Msk /*!< ADC group regular sequencer rank 22 */
<> 148:21d94c44109e 1286 #define ADC_SQR2_SQ22_0 (0x01U << ADC_SQR2_SQ22_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 1287 #define ADC_SQR2_SQ22_1 (0x02U << ADC_SQR2_SQ22_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 1288 #define ADC_SQR2_SQ22_2 (0x04U << ADC_SQR2_SQ22_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 1289 #define ADC_SQR2_SQ22_3 (0x08U << ADC_SQR2_SQ22_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 1290 #define ADC_SQR2_SQ22_4 (0x10U << ADC_SQR2_SQ22_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 1291
<> 148:21d94c44109e 1292 #define ADC_SQR2_SQ23_Pos (20U)
<> 148:21d94c44109e 1293 #define ADC_SQR2_SQ23_Msk (0x1FU << ADC_SQR2_SQ23_Pos) /*!< 0x01F00000 */
<> 148:21d94c44109e 1294 #define ADC_SQR2_SQ23 ADC_SQR2_SQ23_Msk /*!< ADC group regular sequencer rank 23 */
<> 148:21d94c44109e 1295 #define ADC_SQR2_SQ23_0 (0x01U << ADC_SQR2_SQ23_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 1296 #define ADC_SQR2_SQ23_1 (0x02U << ADC_SQR2_SQ23_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 1297 #define ADC_SQR2_SQ23_2 (0x04U << ADC_SQR2_SQ23_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 1298 #define ADC_SQR2_SQ23_3 (0x08U << ADC_SQR2_SQ23_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 1299 #define ADC_SQR2_SQ23_4 (0x10U << ADC_SQR2_SQ23_Pos) /*!< 0x01000000 */
<> 148:21d94c44109e 1300
<> 148:21d94c44109e 1301 #define ADC_SQR2_SQ24_Pos (25U)
<> 148:21d94c44109e 1302 #define ADC_SQR2_SQ24_Msk (0x1FU << ADC_SQR2_SQ24_Pos) /*!< 0x3E000000 */
<> 148:21d94c44109e 1303 #define ADC_SQR2_SQ24 ADC_SQR2_SQ24_Msk /*!< ADC group regular sequencer rank 24 */
<> 148:21d94c44109e 1304 #define ADC_SQR2_SQ24_0 (0x01U << ADC_SQR2_SQ24_Pos) /*!< 0x02000000 */
<> 148:21d94c44109e 1305 #define ADC_SQR2_SQ24_1 (0x02U << ADC_SQR2_SQ24_Pos) /*!< 0x04000000 */
<> 148:21d94c44109e 1306 #define ADC_SQR2_SQ24_2 (0x04U << ADC_SQR2_SQ24_Pos) /*!< 0x08000000 */
<> 148:21d94c44109e 1307 #define ADC_SQR2_SQ24_3 (0x08U << ADC_SQR2_SQ24_Pos) /*!< 0x10000000 */
<> 148:21d94c44109e 1308 #define ADC_SQR2_SQ24_4 (0x10U << ADC_SQR2_SQ24_Pos) /*!< 0x20000000 */
<> 148:21d94c44109e 1309
<> 148:21d94c44109e 1310 /******************* Bit definition for ADC_SQR3 register *******************/
<> 148:21d94c44109e 1311 #define ADC_SQR3_SQ13_Pos (0U)
<> 148:21d94c44109e 1312 #define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x0000001F */
<> 148:21d94c44109e 1313 #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
<> 148:21d94c44109e 1314 #define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 1315 #define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 1316 #define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 1317 #define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 1318 #define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 1319
<> 148:21d94c44109e 1320 #define ADC_SQR3_SQ14_Pos (5U)
<> 148:21d94c44109e 1321 #define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x000003E0 */
<> 148:21d94c44109e 1322 #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
<> 148:21d94c44109e 1323 #define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 1324 #define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 1325 #define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 1326 #define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 1327 #define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 1328
<> 148:21d94c44109e 1329 #define ADC_SQR3_SQ15_Pos (10U)
<> 148:21d94c44109e 1330 #define ADC_SQR3_SQ15_Msk (0x1FU << ADC_SQR3_SQ15_Pos) /*!< 0x00007C00 */
<> 148:21d94c44109e 1331 #define ADC_SQR3_SQ15 ADC_SQR3_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
<> 148:21d94c44109e 1332 #define ADC_SQR3_SQ15_0 (0x01U << ADC_SQR3_SQ15_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 1333 #define ADC_SQR3_SQ15_1 (0x02U << ADC_SQR3_SQ15_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 1334 #define ADC_SQR3_SQ15_2 (0x04U << ADC_SQR3_SQ15_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 1335 #define ADC_SQR3_SQ15_3 (0x08U << ADC_SQR3_SQ15_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 1336 #define ADC_SQR3_SQ15_4 (0x10U << ADC_SQR3_SQ15_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 1337
<> 148:21d94c44109e 1338 #define ADC_SQR3_SQ16_Pos (15U)
<> 148:21d94c44109e 1339 #define ADC_SQR3_SQ16_Msk (0x1FU << ADC_SQR3_SQ16_Pos) /*!< 0x000F8000 */
<> 148:21d94c44109e 1340 #define ADC_SQR3_SQ16 ADC_SQR3_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
<> 148:21d94c44109e 1341 #define ADC_SQR3_SQ16_0 (0x01U << ADC_SQR3_SQ16_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 1342 #define ADC_SQR3_SQ16_1 (0x02U << ADC_SQR3_SQ16_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 1343 #define ADC_SQR3_SQ16_2 (0x04U << ADC_SQR3_SQ16_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 1344 #define ADC_SQR3_SQ16_3 (0x08U << ADC_SQR3_SQ16_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 1345 #define ADC_SQR3_SQ16_4 (0x10U << ADC_SQR3_SQ16_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 1346
<> 148:21d94c44109e 1347 #define ADC_SQR3_SQ17_Pos (20U)
<> 148:21d94c44109e 1348 #define ADC_SQR3_SQ17_Msk (0x1FU << ADC_SQR3_SQ17_Pos) /*!< 0x01F00000 */
<> 148:21d94c44109e 1349 #define ADC_SQR3_SQ17 ADC_SQR3_SQ17_Msk /*!< ADC group regular sequencer rank 17 */
<> 148:21d94c44109e 1350 #define ADC_SQR3_SQ17_0 (0x01U << ADC_SQR3_SQ17_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 1351 #define ADC_SQR3_SQ17_1 (0x02U << ADC_SQR3_SQ17_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 1352 #define ADC_SQR3_SQ17_2 (0x04U << ADC_SQR3_SQ17_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 1353 #define ADC_SQR3_SQ17_3 (0x08U << ADC_SQR3_SQ17_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 1354 #define ADC_SQR3_SQ17_4 (0x10U << ADC_SQR3_SQ17_Pos) /*!< 0x01000000 */
<> 148:21d94c44109e 1355
<> 148:21d94c44109e 1356 #define ADC_SQR3_SQ18_Pos (25U)
<> 148:21d94c44109e 1357 #define ADC_SQR3_SQ18_Msk (0x1FU << ADC_SQR3_SQ18_Pos) /*!< 0x3E000000 */
<> 148:21d94c44109e 1358 #define ADC_SQR3_SQ18 ADC_SQR3_SQ18_Msk /*!< ADC group regular sequencer rank 18 */
<> 148:21d94c44109e 1359 #define ADC_SQR3_SQ18_0 (0x01U << ADC_SQR3_SQ18_Pos) /*!< 0x02000000 */
<> 148:21d94c44109e 1360 #define ADC_SQR3_SQ18_1 (0x02U << ADC_SQR3_SQ18_Pos) /*!< 0x04000000 */
<> 148:21d94c44109e 1361 #define ADC_SQR3_SQ18_2 (0x04U << ADC_SQR3_SQ18_Pos) /*!< 0x08000000 */
<> 148:21d94c44109e 1362 #define ADC_SQR3_SQ18_3 (0x08U << ADC_SQR3_SQ18_Pos) /*!< 0x10000000 */
<> 148:21d94c44109e 1363 #define ADC_SQR3_SQ18_4 (0x10U << ADC_SQR3_SQ18_Pos) /*!< 0x20000000 */
<> 148:21d94c44109e 1364
<> 148:21d94c44109e 1365 /******************* Bit definition for ADC_SQR4 register *******************/
<> 148:21d94c44109e 1366 #define ADC_SQR4_SQ7_Pos (0U)
<> 148:21d94c44109e 1367 #define ADC_SQR4_SQ7_Msk (0x1FU << ADC_SQR4_SQ7_Pos) /*!< 0x0000001F */
<> 148:21d94c44109e 1368 #define ADC_SQR4_SQ7 ADC_SQR4_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
<> 148:21d94c44109e 1369 #define ADC_SQR4_SQ7_0 (0x01U << ADC_SQR4_SQ7_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 1370 #define ADC_SQR4_SQ7_1 (0x02U << ADC_SQR4_SQ7_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 1371 #define ADC_SQR4_SQ7_2 (0x04U << ADC_SQR4_SQ7_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 1372 #define ADC_SQR4_SQ7_3 (0x08U << ADC_SQR4_SQ7_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 1373 #define ADC_SQR4_SQ7_4 (0x10U << ADC_SQR4_SQ7_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 1374
<> 148:21d94c44109e 1375 #define ADC_SQR4_SQ8_Pos (5U)
<> 148:21d94c44109e 1376 #define ADC_SQR4_SQ8_Msk (0x1FU << ADC_SQR4_SQ8_Pos) /*!< 0x000003E0 */
<> 148:21d94c44109e 1377 #define ADC_SQR4_SQ8 ADC_SQR4_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
<> 148:21d94c44109e 1378 #define ADC_SQR4_SQ8_0 (0x01U << ADC_SQR4_SQ8_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 1379 #define ADC_SQR4_SQ8_1 (0x02U << ADC_SQR4_SQ8_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 1380 #define ADC_SQR4_SQ8_2 (0x04U << ADC_SQR4_SQ8_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 1381 #define ADC_SQR4_SQ8_3 (0x08U << ADC_SQR4_SQ8_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 1382 #define ADC_SQR4_SQ8_4 (0x10U << ADC_SQR4_SQ8_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 1383
<> 148:21d94c44109e 1384 #define ADC_SQR4_SQ9_Pos (10U)
<> 148:21d94c44109e 1385 #define ADC_SQR4_SQ9_Msk (0x1FU << ADC_SQR4_SQ9_Pos) /*!< 0x00007C00 */
<> 148:21d94c44109e 1386 #define ADC_SQR4_SQ9 ADC_SQR4_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
<> 148:21d94c44109e 1387 #define ADC_SQR4_SQ9_0 (0x01U << ADC_SQR4_SQ9_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 1388 #define ADC_SQR4_SQ9_1 (0x02U << ADC_SQR4_SQ9_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 1389 #define ADC_SQR4_SQ9_2 (0x04U << ADC_SQR4_SQ9_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 1390 #define ADC_SQR4_SQ9_3 (0x08U << ADC_SQR4_SQ9_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 1391 #define ADC_SQR4_SQ9_4 (0x10U << ADC_SQR4_SQ9_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 1392
<> 148:21d94c44109e 1393 #define ADC_SQR4_SQ10_Pos (15U)
<> 148:21d94c44109e 1394 #define ADC_SQR4_SQ10_Msk (0x1FU << ADC_SQR4_SQ10_Pos) /*!< 0x000F8000 */
<> 148:21d94c44109e 1395 #define ADC_SQR4_SQ10 ADC_SQR4_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
<> 148:21d94c44109e 1396 #define ADC_SQR4_SQ10_0 (0x01U << ADC_SQR4_SQ10_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 1397 #define ADC_SQR4_SQ10_1 (0x02U << ADC_SQR4_SQ10_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 1398 #define ADC_SQR4_SQ10_2 (0x04U << ADC_SQR4_SQ10_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 1399 #define ADC_SQR4_SQ10_3 (0x08U << ADC_SQR4_SQ10_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 1400 #define ADC_SQR4_SQ10_4 (0x10U << ADC_SQR4_SQ10_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 1401
<> 148:21d94c44109e 1402 #define ADC_SQR4_SQ11_Pos (20U)
<> 148:21d94c44109e 1403 #define ADC_SQR4_SQ11_Msk (0x1FU << ADC_SQR4_SQ11_Pos) /*!< 0x01F00000 */
<> 148:21d94c44109e 1404 #define ADC_SQR4_SQ11 ADC_SQR4_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
<> 148:21d94c44109e 1405 #define ADC_SQR4_SQ11_0 (0x01U << ADC_SQR4_SQ11_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 1406 #define ADC_SQR4_SQ11_1 (0x02U << ADC_SQR4_SQ11_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 1407 #define ADC_SQR4_SQ11_2 (0x04U << ADC_SQR4_SQ11_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 1408 #define ADC_SQR4_SQ11_3 (0x08U << ADC_SQR4_SQ11_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 1409 #define ADC_SQR4_SQ11_4 (0x10U << ADC_SQR4_SQ11_Pos) /*!< 0x01000000 */
<> 148:21d94c44109e 1410
<> 148:21d94c44109e 1411 #define ADC_SQR4_SQ12_Pos (25U)
<> 148:21d94c44109e 1412 #define ADC_SQR4_SQ12_Msk (0x1FU << ADC_SQR4_SQ12_Pos) /*!< 0x3E000000 */
<> 148:21d94c44109e 1413 #define ADC_SQR4_SQ12 ADC_SQR4_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
<> 148:21d94c44109e 1414 #define ADC_SQR4_SQ12_0 (0x01U << ADC_SQR4_SQ12_Pos) /*!< 0x02000000 */
<> 148:21d94c44109e 1415 #define ADC_SQR4_SQ12_1 (0x02U << ADC_SQR4_SQ12_Pos) /*!< 0x04000000 */
<> 148:21d94c44109e 1416 #define ADC_SQR4_SQ12_2 (0x04U << ADC_SQR4_SQ12_Pos) /*!< 0x08000000 */
<> 148:21d94c44109e 1417 #define ADC_SQR4_SQ12_3 (0x08U << ADC_SQR4_SQ12_Pos) /*!< 0x10000000 */
<> 148:21d94c44109e 1418 #define ADC_SQR4_SQ12_4 (0x10U << ADC_SQR4_SQ12_Pos) /*!< 0x20000000 */
<> 148:21d94c44109e 1419
<> 148:21d94c44109e 1420 /******************* Bit definition for ADC_SQR5 register *******************/
<> 148:21d94c44109e 1421 #define ADC_SQR5_SQ1_Pos (0U)
<> 148:21d94c44109e 1422 #define ADC_SQR5_SQ1_Msk (0x1FU << ADC_SQR5_SQ1_Pos) /*!< 0x0000001F */
<> 148:21d94c44109e 1423 #define ADC_SQR5_SQ1 ADC_SQR5_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
<> 148:21d94c44109e 1424 #define ADC_SQR5_SQ1_0 (0x01U << ADC_SQR5_SQ1_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 1425 #define ADC_SQR5_SQ1_1 (0x02U << ADC_SQR5_SQ1_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 1426 #define ADC_SQR5_SQ1_2 (0x04U << ADC_SQR5_SQ1_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 1427 #define ADC_SQR5_SQ1_3 (0x08U << ADC_SQR5_SQ1_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 1428 #define ADC_SQR5_SQ1_4 (0x10U << ADC_SQR5_SQ1_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 1429
<> 148:21d94c44109e 1430 #define ADC_SQR5_SQ2_Pos (5U)
<> 148:21d94c44109e 1431 #define ADC_SQR5_SQ2_Msk (0x1FU << ADC_SQR5_SQ2_Pos) /*!< 0x000003E0 */
<> 148:21d94c44109e 1432 #define ADC_SQR5_SQ2 ADC_SQR5_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
<> 148:21d94c44109e 1433 #define ADC_SQR5_SQ2_0 (0x01U << ADC_SQR5_SQ2_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 1434 #define ADC_SQR5_SQ2_1 (0x02U << ADC_SQR5_SQ2_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 1435 #define ADC_SQR5_SQ2_2 (0x04U << ADC_SQR5_SQ2_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 1436 #define ADC_SQR5_SQ2_3 (0x08U << ADC_SQR5_SQ2_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 1437 #define ADC_SQR5_SQ2_4 (0x10U << ADC_SQR5_SQ2_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 1438
<> 148:21d94c44109e 1439 #define ADC_SQR5_SQ3_Pos (10U)
<> 148:21d94c44109e 1440 #define ADC_SQR5_SQ3_Msk (0x1FU << ADC_SQR5_SQ3_Pos) /*!< 0x00007C00 */
<> 148:21d94c44109e 1441 #define ADC_SQR5_SQ3 ADC_SQR5_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
<> 148:21d94c44109e 1442 #define ADC_SQR5_SQ3_0 (0x01U << ADC_SQR5_SQ3_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 1443 #define ADC_SQR5_SQ3_1 (0x02U << ADC_SQR5_SQ3_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 1444 #define ADC_SQR5_SQ3_2 (0x04U << ADC_SQR5_SQ3_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 1445 #define ADC_SQR5_SQ3_3 (0x08U << ADC_SQR5_SQ3_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 1446 #define ADC_SQR5_SQ3_4 (0x10U << ADC_SQR5_SQ3_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 1447
<> 148:21d94c44109e 1448 #define ADC_SQR5_SQ4_Pos (15U)
<> 148:21d94c44109e 1449 #define ADC_SQR5_SQ4_Msk (0x1FU << ADC_SQR5_SQ4_Pos) /*!< 0x000F8000 */
<> 148:21d94c44109e 1450 #define ADC_SQR5_SQ4 ADC_SQR5_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
<> 148:21d94c44109e 1451 #define ADC_SQR5_SQ4_0 (0x01U << ADC_SQR5_SQ4_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 1452 #define ADC_SQR5_SQ4_1 (0x02U << ADC_SQR5_SQ4_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 1453 #define ADC_SQR5_SQ4_2 (0x04U << ADC_SQR5_SQ4_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 1454 #define ADC_SQR5_SQ4_3 (0x08U << ADC_SQR5_SQ4_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 1455 #define ADC_SQR5_SQ4_4 (0x10U << ADC_SQR5_SQ4_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 1456
<> 148:21d94c44109e 1457 #define ADC_SQR5_SQ5_Pos (20U)
<> 148:21d94c44109e 1458 #define ADC_SQR5_SQ5_Msk (0x1FU << ADC_SQR5_SQ5_Pos) /*!< 0x01F00000 */
<> 148:21d94c44109e 1459 #define ADC_SQR5_SQ5 ADC_SQR5_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
<> 148:21d94c44109e 1460 #define ADC_SQR5_SQ5_0 (0x01U << ADC_SQR5_SQ5_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 1461 #define ADC_SQR5_SQ5_1 (0x02U << ADC_SQR5_SQ5_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 1462 #define ADC_SQR5_SQ5_2 (0x04U << ADC_SQR5_SQ5_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 1463 #define ADC_SQR5_SQ5_3 (0x08U << ADC_SQR5_SQ5_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 1464 #define ADC_SQR5_SQ5_4 (0x10U << ADC_SQR5_SQ5_Pos) /*!< 0x01000000 */
<> 148:21d94c44109e 1465
<> 148:21d94c44109e 1466 #define ADC_SQR5_SQ6_Pos (25U)
<> 148:21d94c44109e 1467 #define ADC_SQR5_SQ6_Msk (0x1FU << ADC_SQR5_SQ6_Pos) /*!< 0x3E000000 */
<> 148:21d94c44109e 1468 #define ADC_SQR5_SQ6 ADC_SQR5_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
<> 148:21d94c44109e 1469 #define ADC_SQR5_SQ6_0 (0x01U << ADC_SQR5_SQ6_Pos) /*!< 0x02000000 */
<> 148:21d94c44109e 1470 #define ADC_SQR5_SQ6_1 (0x02U << ADC_SQR5_SQ6_Pos) /*!< 0x04000000 */
<> 148:21d94c44109e 1471 #define ADC_SQR5_SQ6_2 (0x04U << ADC_SQR5_SQ6_Pos) /*!< 0x08000000 */
<> 148:21d94c44109e 1472 #define ADC_SQR5_SQ6_3 (0x08U << ADC_SQR5_SQ6_Pos) /*!< 0x10000000 */
<> 148:21d94c44109e 1473 #define ADC_SQR5_SQ6_4 (0x10U << ADC_SQR5_SQ6_Pos) /*!< 0x20000000 */
<> 148:21d94c44109e 1474
<> 148:21d94c44109e 1475
<> 148:21d94c44109e 1476 /******************* Bit definition for ADC_JSQR register *******************/
<> 148:21d94c44109e 1477 #define ADC_JSQR_JSQ1_Pos (0U)
<> 148:21d94c44109e 1478 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
<> 148:21d94c44109e 1479 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
<> 148:21d94c44109e 1480 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 1481 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 1482 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 1483 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 1484 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 1485
<> 148:21d94c44109e 1486 #define ADC_JSQR_JSQ2_Pos (5U)
<> 148:21d94c44109e 1487 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
<> 148:21d94c44109e 1488 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
<> 148:21d94c44109e 1489 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 1490 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 1491 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 1492 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 1493 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 1494
<> 148:21d94c44109e 1495 #define ADC_JSQR_JSQ3_Pos (10U)
<> 148:21d94c44109e 1496 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
<> 148:21d94c44109e 1497 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
<> 148:21d94c44109e 1498 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 1499 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 1500 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 1501 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 1502 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 1503
<> 148:21d94c44109e 1504 #define ADC_JSQR_JSQ4_Pos (15U)
<> 148:21d94c44109e 1505 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
<> 148:21d94c44109e 1506 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
<> 148:21d94c44109e 1507 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 1508 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 1509 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 1510 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 1511 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 1512
<> 148:21d94c44109e 1513 #define ADC_JSQR_JL_Pos (20U)
<> 148:21d94c44109e 1514 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
<> 148:21d94c44109e 1515 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
<> 148:21d94c44109e 1516 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 1517 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 1518
<> 148:21d94c44109e 1519 /******************* Bit definition for ADC_JDR1 register *******************/
<> 148:21d94c44109e 1520 #define ADC_JDR1_JDATA_Pos (0U)
<> 148:21d94c44109e 1521 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 1522 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
<> 148:21d94c44109e 1523
<> 148:21d94c44109e 1524 /******************* Bit definition for ADC_JDR2 register *******************/
<> 148:21d94c44109e 1525 #define ADC_JDR2_JDATA_Pos (0U)
<> 148:21d94c44109e 1526 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 1527 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
<> 148:21d94c44109e 1528
<> 148:21d94c44109e 1529 /******************* Bit definition for ADC_JDR3 register *******************/
<> 148:21d94c44109e 1530 #define ADC_JDR3_JDATA_Pos (0U)
<> 148:21d94c44109e 1531 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 1532 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
<> 148:21d94c44109e 1533
<> 148:21d94c44109e 1534 /******************* Bit definition for ADC_JDR4 register *******************/
<> 148:21d94c44109e 1535 #define ADC_JDR4_JDATA_Pos (0U)
<> 148:21d94c44109e 1536 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 1537 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
<> 148:21d94c44109e 1538
<> 148:21d94c44109e 1539 /******************** Bit definition for ADC_DR register ********************/
<> 148:21d94c44109e 1540 #define ADC_DR_DATA_Pos (0U)
<> 148:21d94c44109e 1541 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 1542 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
<> 148:21d94c44109e 1543
<> 148:21d94c44109e 1544 /******************* Bit definition for ADC_CSR register ********************/
<> 148:21d94c44109e 1545 #define ADC_CSR_AWD1_Pos (0U)
<> 148:21d94c44109e 1546 #define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 1547 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!< ADC multimode master analog watchdog 1 flag */
<> 148:21d94c44109e 1548 #define ADC_CSR_EOCS1_Pos (1U)
<> 148:21d94c44109e 1549 #define ADC_CSR_EOCS1_Msk (0x1U << ADC_CSR_EOCS1_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 1550 #define ADC_CSR_EOCS1 ADC_CSR_EOCS1_Msk /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */
<> 148:21d94c44109e 1551 #define ADC_CSR_JEOS1_Pos (2U)
<> 148:21d94c44109e 1552 #define ADC_CSR_JEOS1_Msk (0x1U << ADC_CSR_JEOS1_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 1553 #define ADC_CSR_JEOS1 ADC_CSR_JEOS1_Msk /*!< ADC multimode master group injected end of sequence conversions flag */
<> 148:21d94c44109e 1554 #define ADC_CSR_JSTRT1_Pos (3U)
<> 148:21d94c44109e 1555 #define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 1556 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!< ADC multimode master group injected conversion start flag */
<> 148:21d94c44109e 1557 #define ADC_CSR_STRT1_Pos (4U)
<> 148:21d94c44109e 1558 #define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 1559 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!< ADC multimode master group regular conversion start flag */
<> 148:21d94c44109e 1560 #define ADC_CSR_OVR1_Pos (5U)
<> 148:21d94c44109e 1561 #define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 1562 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!< ADC multimode master group regular overrun flag */
<> 148:21d94c44109e 1563 #define ADC_CSR_ADONS1_Pos (6U)
<> 148:21d94c44109e 1564 #define ADC_CSR_ADONS1_Msk (0x1U << ADC_CSR_ADONS1_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 1565 #define ADC_CSR_ADONS1 ADC_CSR_ADONS1_Msk /*!< ADC multimode master ready flag */
<> 148:21d94c44109e 1566
<> 148:21d94c44109e 1567 /* Legacy defines */
<> 148:21d94c44109e 1568 #define ADC_CSR_EOC1 (ADC_CSR_EOCS1)
<> 148:21d94c44109e 1569 #define ADC_CSR_JEOC1 (ADC_CSR_JEOS1)
<> 148:21d94c44109e 1570
<> 148:21d94c44109e 1571 /******************* Bit definition for ADC_CCR register ********************/
<> 148:21d94c44109e 1572 #define ADC_CCR_ADCPRE_Pos (16U)
<> 148:21d94c44109e 1573 #define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
<> 148:21d94c44109e 1574 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!< ADC clock source asynchronous prescaler */
<> 148:21d94c44109e 1575 #define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 1576 #define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 1577 #define ADC_CCR_TSVREFE_Pos (23U)
<> 148:21d94c44109e 1578 #define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 1579 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */
<> 148:21d94c44109e 1580
<> 148:21d94c44109e 1581 /******************************************************************************/
<> 148:21d94c44109e 1582 /* */
<> 148:21d94c44109e 1583 /* Analog Comparators (COMP) */
<> 148:21d94c44109e 1584 /* */
<> 148:21d94c44109e 1585 /******************************************************************************/
<> 148:21d94c44109e 1586
<> 148:21d94c44109e 1587 /****************** Bit definition for COMP_CSR register ********************/
<> 148:21d94c44109e 1588 #define COMP_CSR_10KPU (0x00000001U) /*!< Comparator 1 input plus 10K pull-up resistor */
<> 148:21d94c44109e 1589 #define COMP_CSR_400KPU (0x00000002U) /*!< Comparator 1 input plus 400K pull-up resistor */
<> 148:21d94c44109e 1590 #define COMP_CSR_10KPD (0x00000004U) /*!< Comparator 1 input plus 10K pull-down resistor */
<> 148:21d94c44109e 1591 #define COMP_CSR_400KPD (0x00000008U) /*!< Comparator 1 input plus 400K pull-down resistor */
<> 148:21d94c44109e 1592 #define COMP_CSR_CMP1EN_Pos (4U)
<> 148:21d94c44109e 1593 #define COMP_CSR_CMP1EN_Msk (0x1U << COMP_CSR_CMP1EN_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 1594 #define COMP_CSR_CMP1EN COMP_CSR_CMP1EN_Msk /*!< Comparator 1 enable */
<> 148:21d94c44109e 1595 #define COMP_CSR_CMP1OUT_Pos (7U)
<> 148:21d94c44109e 1596 #define COMP_CSR_CMP1OUT_Msk (0x1U << COMP_CSR_CMP1OUT_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 1597 #define COMP_CSR_CMP1OUT COMP_CSR_CMP1OUT_Msk /*!< Comparator 1 output level */
<> 148:21d94c44109e 1598 #define COMP_CSR_SPEED_Pos (12U)
<> 148:21d94c44109e 1599 #define COMP_CSR_SPEED_Msk (0x1U << COMP_CSR_SPEED_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 1600 #define COMP_CSR_SPEED COMP_CSR_SPEED_Msk /*!< Comparator 2 power mode */
<> 148:21d94c44109e 1601 #define COMP_CSR_CMP2OUT_Pos (13U)
<> 148:21d94c44109e 1602 #define COMP_CSR_CMP2OUT_Msk (0x1U << COMP_CSR_CMP2OUT_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 1603 #define COMP_CSR_CMP2OUT COMP_CSR_CMP2OUT_Msk /*!< Comparator 2 output level */
<> 148:21d94c44109e 1604
<> 148:21d94c44109e 1605 #define COMP_CSR_WNDWE_Pos (17U)
<> 148:21d94c44109e 1606 #define COMP_CSR_WNDWE_Msk (0x1U << COMP_CSR_WNDWE_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 1607 #define COMP_CSR_WNDWE COMP_CSR_WNDWE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
<> 148:21d94c44109e 1608
<> 148:21d94c44109e 1609 #define COMP_CSR_INSEL_Pos (18U)
<> 148:21d94c44109e 1610 #define COMP_CSR_INSEL_Msk (0x7U << COMP_CSR_INSEL_Pos) /*!< 0x001C0000 */
<> 148:21d94c44109e 1611 #define COMP_CSR_INSEL COMP_CSR_INSEL_Msk /*!< Comparator 2 input minus selection */
<> 148:21d94c44109e 1612 #define COMP_CSR_INSEL_0 (0x1U << COMP_CSR_INSEL_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 1613 #define COMP_CSR_INSEL_1 (0x2U << COMP_CSR_INSEL_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 1614 #define COMP_CSR_INSEL_2 (0x4U << COMP_CSR_INSEL_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 1615 #define COMP_CSR_OUTSEL_Pos (21U)
<> 148:21d94c44109e 1616 #define COMP_CSR_OUTSEL_Msk (0x7U << COMP_CSR_OUTSEL_Pos) /*!< 0x00E00000 */
<> 148:21d94c44109e 1617 #define COMP_CSR_OUTSEL COMP_CSR_OUTSEL_Msk /*!< Comparator 2 output redirection */
<> 148:21d94c44109e 1618 #define COMP_CSR_OUTSEL_0 (0x1U << COMP_CSR_OUTSEL_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 1619 #define COMP_CSR_OUTSEL_1 (0x2U << COMP_CSR_OUTSEL_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 1620 #define COMP_CSR_OUTSEL_2 (0x4U << COMP_CSR_OUTSEL_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 1621
<> 148:21d94c44109e 1622 /* Bits present in COMP register but not related to comparator */
<> 148:21d94c44109e 1623 /* (or partially related to comparator, in addition to other peripherals) */
<> 148:21d94c44109e 1624 #define COMP_CSR_VREFOUTEN_Pos (16U)
<> 148:21d94c44109e 1625 #define COMP_CSR_VREFOUTEN_Msk (0x1U << COMP_CSR_VREFOUTEN_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 1626 #define COMP_CSR_VREFOUTEN COMP_CSR_VREFOUTEN_Msk /*!< VrefInt output enable on GPIO group 3 */
<> 148:21d94c44109e 1627
<> 148:21d94c44109e 1628 #define COMP_CSR_FCH3_Pos (26U)
<> 148:21d94c44109e 1629 #define COMP_CSR_FCH3_Msk (0x1U << COMP_CSR_FCH3_Pos) /*!< 0x04000000 */
<> 148:21d94c44109e 1630 #define COMP_CSR_FCH3 COMP_CSR_FCH3_Msk /*!< Bit 26 */
<> 148:21d94c44109e 1631 #define COMP_CSR_FCH8_Pos (27U)
<> 148:21d94c44109e 1632 #define COMP_CSR_FCH8_Msk (0x1U << COMP_CSR_FCH8_Pos) /*!< 0x08000000 */
<> 148:21d94c44109e 1633 #define COMP_CSR_FCH8 COMP_CSR_FCH8_Msk /*!< Bit 27 */
<> 148:21d94c44109e 1634 #define COMP_CSR_RCH13_Pos (28U)
<> 148:21d94c44109e 1635 #define COMP_CSR_RCH13_Msk (0x1U << COMP_CSR_RCH13_Pos) /*!< 0x10000000 */
<> 148:21d94c44109e 1636 #define COMP_CSR_RCH13 COMP_CSR_RCH13_Msk /*!< Bit 28 */
<> 148:21d94c44109e 1637
<> 148:21d94c44109e 1638 #define COMP_CSR_CAIE_Pos (29U)
<> 148:21d94c44109e 1639 #define COMP_CSR_CAIE_Msk (0x1U << COMP_CSR_CAIE_Pos) /*!< 0x20000000 */
<> 148:21d94c44109e 1640 #define COMP_CSR_CAIE COMP_CSR_CAIE_Msk /*!< Bit 29 */
<> 148:21d94c44109e 1641 #define COMP_CSR_CAIF_Pos (30U)
<> 148:21d94c44109e 1642 #define COMP_CSR_CAIF_Msk (0x1U << COMP_CSR_CAIF_Pos) /*!< 0x40000000 */
<> 148:21d94c44109e 1643 #define COMP_CSR_CAIF COMP_CSR_CAIF_Msk /*!< Bit 30 */
<> 148:21d94c44109e 1644 #define COMP_CSR_TSUSP_Pos (31U)
<> 148:21d94c44109e 1645 #define COMP_CSR_TSUSP_Msk (0x1U << COMP_CSR_TSUSP_Pos) /*!< 0x80000000 */
<> 148:21d94c44109e 1646 #define COMP_CSR_TSUSP COMP_CSR_TSUSP_Msk /*!< Bit 31 */
<> 148:21d94c44109e 1647
<> 148:21d94c44109e 1648 /******************************************************************************/
<> 148:21d94c44109e 1649 /* */
<> 148:21d94c44109e 1650 /* Operational Amplifier (OPAMP) */
<> 148:21d94c44109e 1651 /* */
<> 148:21d94c44109e 1652 /******************************************************************************/
<> 148:21d94c44109e 1653 /******************* Bit definition for OPAMP_CSR register ******************/
<> 148:21d94c44109e 1654 #define OPAMP_CSR_OPA1PD_Pos (0U)
<> 148:21d94c44109e 1655 #define OPAMP_CSR_OPA1PD_Msk (0x1U << OPAMP_CSR_OPA1PD_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 1656 #define OPAMP_CSR_OPA1PD OPAMP_CSR_OPA1PD_Msk /*!< OPAMP1 disable */
<> 148:21d94c44109e 1657 #define OPAMP_CSR_S3SEL1_Pos (1U)
<> 148:21d94c44109e 1658 #define OPAMP_CSR_S3SEL1_Msk (0x1U << OPAMP_CSR_S3SEL1_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 1659 #define OPAMP_CSR_S3SEL1 OPAMP_CSR_S3SEL1_Msk /*!< Switch 3 for OPAMP1 Enable */
<> 148:21d94c44109e 1660 #define OPAMP_CSR_S4SEL1_Pos (2U)
<> 148:21d94c44109e 1661 #define OPAMP_CSR_S4SEL1_Msk (0x1U << OPAMP_CSR_S4SEL1_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 1662 #define OPAMP_CSR_S4SEL1 OPAMP_CSR_S4SEL1_Msk /*!< Switch 4 for OPAMP1 Enable */
<> 148:21d94c44109e 1663 #define OPAMP_CSR_S5SEL1_Pos (3U)
<> 148:21d94c44109e 1664 #define OPAMP_CSR_S5SEL1_Msk (0x1U << OPAMP_CSR_S5SEL1_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 1665 #define OPAMP_CSR_S5SEL1 OPAMP_CSR_S5SEL1_Msk /*!< Switch 5 for OPAMP1 Enable */
<> 148:21d94c44109e 1666 #define OPAMP_CSR_S6SEL1_Pos (4U)
<> 148:21d94c44109e 1667 #define OPAMP_CSR_S6SEL1_Msk (0x1U << OPAMP_CSR_S6SEL1_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 1668 #define OPAMP_CSR_S6SEL1 OPAMP_CSR_S6SEL1_Msk /*!< Switch 6 for OPAMP1 Enable */
<> 148:21d94c44109e 1669 #define OPAMP_CSR_OPA1CAL_L_Pos (5U)
<> 148:21d94c44109e 1670 #define OPAMP_CSR_OPA1CAL_L_Msk (0x1U << OPAMP_CSR_OPA1CAL_L_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 1671 #define OPAMP_CSR_OPA1CAL_L OPAMP_CSR_OPA1CAL_L_Msk /*!< OPAMP1 Offset calibration for P differential pair */
<> 148:21d94c44109e 1672 #define OPAMP_CSR_OPA1CAL_H_Pos (6U)
<> 148:21d94c44109e 1673 #define OPAMP_CSR_OPA1CAL_H_Msk (0x1U << OPAMP_CSR_OPA1CAL_H_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 1674 #define OPAMP_CSR_OPA1CAL_H OPAMP_CSR_OPA1CAL_H_Msk /*!< OPAMP1 Offset calibration for N differential pair */
<> 148:21d94c44109e 1675 #define OPAMP_CSR_OPA1LPM_Pos (7U)
<> 148:21d94c44109e 1676 #define OPAMP_CSR_OPA1LPM_Msk (0x1U << OPAMP_CSR_OPA1LPM_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 1677 #define OPAMP_CSR_OPA1LPM OPAMP_CSR_OPA1LPM_Msk /*!< OPAMP1 Low power enable */
<> 148:21d94c44109e 1678 #define OPAMP_CSR_OPA2PD_Pos (8U)
<> 148:21d94c44109e 1679 #define OPAMP_CSR_OPA2PD_Msk (0x1U << OPAMP_CSR_OPA2PD_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 1680 #define OPAMP_CSR_OPA2PD OPAMP_CSR_OPA2PD_Msk /*!< OPAMP2 disable */
<> 148:21d94c44109e 1681 #define OPAMP_CSR_S3SEL2_Pos (9U)
<> 148:21d94c44109e 1682 #define OPAMP_CSR_S3SEL2_Msk (0x1U << OPAMP_CSR_S3SEL2_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 1683 #define OPAMP_CSR_S3SEL2 OPAMP_CSR_S3SEL2_Msk /*!< Switch 3 for OPAMP2 Enable */
<> 148:21d94c44109e 1684 #define OPAMP_CSR_S4SEL2_Pos (10U)
<> 148:21d94c44109e 1685 #define OPAMP_CSR_S4SEL2_Msk (0x1U << OPAMP_CSR_S4SEL2_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 1686 #define OPAMP_CSR_S4SEL2 OPAMP_CSR_S4SEL2_Msk /*!< Switch 4 for OPAMP2 Enable */
<> 148:21d94c44109e 1687 #define OPAMP_CSR_S5SEL2_Pos (11U)
<> 148:21d94c44109e 1688 #define OPAMP_CSR_S5SEL2_Msk (0x1U << OPAMP_CSR_S5SEL2_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 1689 #define OPAMP_CSR_S5SEL2 OPAMP_CSR_S5SEL2_Msk /*!< Switch 5 for OPAMP2 Enable */
<> 148:21d94c44109e 1690 #define OPAMP_CSR_S6SEL2_Pos (12U)
<> 148:21d94c44109e 1691 #define OPAMP_CSR_S6SEL2_Msk (0x1U << OPAMP_CSR_S6SEL2_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 1692 #define OPAMP_CSR_S6SEL2 OPAMP_CSR_S6SEL2_Msk /*!< Switch 6 for OPAMP2 Enable */
<> 148:21d94c44109e 1693 #define OPAMP_CSR_OPA2CAL_L_Pos (13U)
<> 148:21d94c44109e 1694 #define OPAMP_CSR_OPA2CAL_L_Msk (0x1U << OPAMP_CSR_OPA2CAL_L_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 1695 #define OPAMP_CSR_OPA2CAL_L OPAMP_CSR_OPA2CAL_L_Msk /*!< OPAMP2 Offset calibration for P differential pair */
<> 148:21d94c44109e 1696 #define OPAMP_CSR_OPA2CAL_H_Pos (14U)
<> 148:21d94c44109e 1697 #define OPAMP_CSR_OPA2CAL_H_Msk (0x1U << OPAMP_CSR_OPA2CAL_H_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 1698 #define OPAMP_CSR_OPA2CAL_H OPAMP_CSR_OPA2CAL_H_Msk /*!< OPAMP2 Offset calibration for N differential pair */
<> 148:21d94c44109e 1699 #define OPAMP_CSR_OPA2LPM_Pos (15U)
<> 148:21d94c44109e 1700 #define OPAMP_CSR_OPA2LPM_Msk (0x1U << OPAMP_CSR_OPA2LPM_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 1701 #define OPAMP_CSR_OPA2LPM OPAMP_CSR_OPA2LPM_Msk /*!< OPAMP2 Low power enable */
<> 148:21d94c44109e 1702 #define OPAMP_CSR_ANAWSEL1_Pos (24U)
<> 148:21d94c44109e 1703 #define OPAMP_CSR_ANAWSEL1_Msk (0x1U << OPAMP_CSR_ANAWSEL1_Pos) /*!< 0x01000000 */
<> 148:21d94c44109e 1704 #define OPAMP_CSR_ANAWSEL1 OPAMP_CSR_ANAWSEL1_Msk /*!< Switch ANA Enable for OPAMP1 */
<> 148:21d94c44109e 1705 #define OPAMP_CSR_ANAWSEL2_Pos (25U)
<> 148:21d94c44109e 1706 #define OPAMP_CSR_ANAWSEL2_Msk (0x1U << OPAMP_CSR_ANAWSEL2_Pos) /*!< 0x02000000 */
<> 148:21d94c44109e 1707 #define OPAMP_CSR_ANAWSEL2 OPAMP_CSR_ANAWSEL2_Msk /*!< Switch ANA Enable for OPAMP2 */
<> 148:21d94c44109e 1708 #define OPAMP_CSR_S7SEL2_Pos (27U)
<> 148:21d94c44109e 1709 #define OPAMP_CSR_S7SEL2_Msk (0x1U << OPAMP_CSR_S7SEL2_Pos) /*!< 0x08000000 */
<> 148:21d94c44109e 1710 #define OPAMP_CSR_S7SEL2 OPAMP_CSR_S7SEL2_Msk /*!< Switch 7 for OPAMP2 Enable */
<> 148:21d94c44109e 1711 #define OPAMP_CSR_AOP_RANGE_Pos (28U)
<> 148:21d94c44109e 1712 #define OPAMP_CSR_AOP_RANGE_Msk (0x1U << OPAMP_CSR_AOP_RANGE_Pos) /*!< 0x10000000 */
<> 148:21d94c44109e 1713 #define OPAMP_CSR_AOP_RANGE OPAMP_CSR_AOP_RANGE_Msk /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
<> 148:21d94c44109e 1714 #define OPAMP_CSR_OPA1CALOUT_Pos (29U)
<> 148:21d94c44109e 1715 #define OPAMP_CSR_OPA1CALOUT_Msk (0x1U << OPAMP_CSR_OPA1CALOUT_Pos) /*!< 0x20000000 */
<> 148:21d94c44109e 1716 #define OPAMP_CSR_OPA1CALOUT OPAMP_CSR_OPA1CALOUT_Msk /*!< OPAMP1 calibration output */
<> 148:21d94c44109e 1717 #define OPAMP_CSR_OPA2CALOUT_Pos (30U)
<> 148:21d94c44109e 1718 #define OPAMP_CSR_OPA2CALOUT_Msk (0x1U << OPAMP_CSR_OPA2CALOUT_Pos) /*!< 0x40000000 */
<> 148:21d94c44109e 1719 #define OPAMP_CSR_OPA2CALOUT OPAMP_CSR_OPA2CALOUT_Msk /*!< OPAMP2 calibration output */
<> 148:21d94c44109e 1720
<> 148:21d94c44109e 1721 /******************* Bit definition for OPAMP_OTR register ******************/
<> 148:21d94c44109e 1722 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos (0U)
<> 148:21d94c44109e 1723 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x0000001F */
<> 148:21d94c44109e 1724 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
<> 148:21d94c44109e 1725 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos (5U)
<> 148:21d94c44109e 1726 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000003E0 */
<> 148:21d94c44109e 1727 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
<> 148:21d94c44109e 1728 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos (10U)
<> 148:21d94c44109e 1729 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x00007C00 */
<> 148:21d94c44109e 1730 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
<> 148:21d94c44109e 1731 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos (15U)
<> 148:21d94c44109e 1732 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000F8000 */
<> 148:21d94c44109e 1733 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
<> 148:21d94c44109e 1734 #define OPAMP_OTR_OT_USER_Pos (31U)
<> 148:21d94c44109e 1735 #define OPAMP_OTR_OT_USER_Msk (0x1U << OPAMP_OTR_OT_USER_Pos) /*!< 0x80000000 */
<> 148:21d94c44109e 1736 #define OPAMP_OTR_OT_USER OPAMP_OTR_OT_USER_Msk /*!< Switch to OPAMP offset user trimmed values */
<> 148:21d94c44109e 1737
<> 148:21d94c44109e 1738 /******************* Bit definition for OPAMP_LPOTR register ****************/
<> 148:21d94c44109e 1739 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos (0U)
<> 148:21d94c44109e 1740 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x0000001F */
<> 148:21d94c44109e 1741 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
<> 148:21d94c44109e 1742 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos (5U)
<> 148:21d94c44109e 1743 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000003E0 */
<> 148:21d94c44109e 1744 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
<> 148:21d94c44109e 1745 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos (10U)
<> 148:21d94c44109e 1746 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x00007C00 */
<> 148:21d94c44109e 1747 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
<> 148:21d94c44109e 1748 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos (15U)
<> 148:21d94c44109e 1749 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000F8000 */
<> 148:21d94c44109e 1750 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
<> 148:21d94c44109e 1751
<> 148:21d94c44109e 1752 /******************************************************************************/
<> 148:21d94c44109e 1753 /* */
<> 148:21d94c44109e 1754 /* CRC calculation unit (CRC) */
<> 148:21d94c44109e 1755 /* */
<> 148:21d94c44109e 1756 /******************************************************************************/
<> 148:21d94c44109e 1757
<> 148:21d94c44109e 1758 /******************* Bit definition for CRC_DR register *********************/
<> 148:21d94c44109e 1759 #define CRC_DR_DR_Pos (0U)
<> 148:21d94c44109e 1760 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 1761 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
<> 148:21d94c44109e 1762
<> 148:21d94c44109e 1763 /******************* Bit definition for CRC_IDR register ********************/
<> 148:21d94c44109e 1764 #define CRC_IDR_IDR_Pos (0U)
<> 148:21d94c44109e 1765 #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
<> 148:21d94c44109e 1766 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
<> 148:21d94c44109e 1767
<> 148:21d94c44109e 1768 /******************** Bit definition for CRC_CR register ********************/
<> 148:21d94c44109e 1769 #define CRC_CR_RESET_Pos (0U)
<> 148:21d94c44109e 1770 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 1771 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
<> 148:21d94c44109e 1772
<> 148:21d94c44109e 1773 /******************************************************************************/
<> 148:21d94c44109e 1774 /* */
<> 148:21d94c44109e 1775 /* Digital to Analog Converter (DAC) */
<> 148:21d94c44109e 1776 /* */
<> 148:21d94c44109e 1777 /******************************************************************************/
<> 148:21d94c44109e 1778
<> 148:21d94c44109e 1779 /******************** Bit definition for DAC_CR register ********************/
<> 148:21d94c44109e 1780 #define DAC_CR_EN1_Pos (0U)
<> 148:21d94c44109e 1781 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 1782 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
<> 148:21d94c44109e 1783 #define DAC_CR_BOFF1_Pos (1U)
<> 148:21d94c44109e 1784 #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 1785 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
<> 148:21d94c44109e 1786 #define DAC_CR_TEN1_Pos (2U)
<> 148:21d94c44109e 1787 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 1788 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
<> 148:21d94c44109e 1789
<> 148:21d94c44109e 1790 #define DAC_CR_TSEL1_Pos (3U)
<> 148:21d94c44109e 1791 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
<> 148:21d94c44109e 1792 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
<> 148:21d94c44109e 1793 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 1794 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 1795 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 1796
<> 148:21d94c44109e 1797 #define DAC_CR_WAVE1_Pos (6U)
<> 148:21d94c44109e 1798 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
<> 148:21d94c44109e 1799 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
<> 148:21d94c44109e 1800 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 1801 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 1802
<> 148:21d94c44109e 1803 #define DAC_CR_MAMP1_Pos (8U)
<> 148:21d94c44109e 1804 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
<> 148:21d94c44109e 1805 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
<> 148:21d94c44109e 1806 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 1807 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 1808 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 1809 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 1810
<> 148:21d94c44109e 1811 #define DAC_CR_DMAEN1_Pos (12U)
<> 148:21d94c44109e 1812 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 1813 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
<> 148:21d94c44109e 1814 #define DAC_CR_DMAUDRIE1_Pos (13U)
<> 148:21d94c44109e 1815 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 1816 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA Interrupt enable */
<> 148:21d94c44109e 1817 #define DAC_CR_EN2_Pos (16U)
<> 148:21d94c44109e 1818 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 1819 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
<> 148:21d94c44109e 1820 #define DAC_CR_BOFF2_Pos (17U)
<> 148:21d94c44109e 1821 #define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 1822 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
<> 148:21d94c44109e 1823 #define DAC_CR_TEN2_Pos (18U)
<> 148:21d94c44109e 1824 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 1825 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
<> 148:21d94c44109e 1826
<> 148:21d94c44109e 1827 #define DAC_CR_TSEL2_Pos (19U)
<> 148:21d94c44109e 1828 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
<> 148:21d94c44109e 1829 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
<> 148:21d94c44109e 1830 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 1831 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 1832 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 1833
<> 148:21d94c44109e 1834 #define DAC_CR_WAVE2_Pos (22U)
<> 148:21d94c44109e 1835 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
<> 148:21d94c44109e 1836 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
<> 148:21d94c44109e 1837 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 1838 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 1839
<> 148:21d94c44109e 1840 #define DAC_CR_MAMP2_Pos (24U)
<> 148:21d94c44109e 1841 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
<> 148:21d94c44109e 1842 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
<> 148:21d94c44109e 1843 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
<> 148:21d94c44109e 1844 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
<> 148:21d94c44109e 1845 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
<> 148:21d94c44109e 1846 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
<> 148:21d94c44109e 1847
<> 148:21d94c44109e 1848 #define DAC_CR_DMAEN2_Pos (28U)
<> 148:21d94c44109e 1849 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
<> 148:21d94c44109e 1850 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
<> 148:21d94c44109e 1851 #define DAC_CR_DMAUDRIE2_Pos (29U)
<> 148:21d94c44109e 1852 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
<> 148:21d94c44109e 1853 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable */
<> 148:21d94c44109e 1854 /***************** Bit definition for DAC_SWTRIGR register ******************/
<> 148:21d94c44109e 1855 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
<> 148:21d94c44109e 1856 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 1857 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
<> 148:21d94c44109e 1858 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
<> 148:21d94c44109e 1859 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 1860 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
<> 148:21d94c44109e 1861
<> 148:21d94c44109e 1862 /***************** Bit definition for DAC_DHR12R1 register ******************/
<> 148:21d94c44109e 1863 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
<> 148:21d94c44109e 1864 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
<> 148:21d94c44109e 1865 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
<> 148:21d94c44109e 1866
<> 148:21d94c44109e 1867 /***************** Bit definition for DAC_DHR12L1 register ******************/
<> 148:21d94c44109e 1868 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
<> 148:21d94c44109e 1869 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
<> 148:21d94c44109e 1870 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
<> 148:21d94c44109e 1871
<> 148:21d94c44109e 1872 /****************** Bit definition for DAC_DHR8R1 register ******************/
<> 148:21d94c44109e 1873 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
<> 148:21d94c44109e 1874 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
<> 148:21d94c44109e 1875 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
<> 148:21d94c44109e 1876
<> 148:21d94c44109e 1877 /***************** Bit definition for DAC_DHR12R2 register ******************/
<> 148:21d94c44109e 1878 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
<> 148:21d94c44109e 1879 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
<> 148:21d94c44109e 1880 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
<> 148:21d94c44109e 1881
<> 148:21d94c44109e 1882 /***************** Bit definition for DAC_DHR12L2 register ******************/
<> 148:21d94c44109e 1883 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
<> 148:21d94c44109e 1884 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
<> 148:21d94c44109e 1885 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
<> 148:21d94c44109e 1886
<> 148:21d94c44109e 1887 /****************** Bit definition for DAC_DHR8R2 register ******************/
<> 148:21d94c44109e 1888 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
<> 148:21d94c44109e 1889 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
<> 148:21d94c44109e 1890 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
<> 148:21d94c44109e 1891
<> 148:21d94c44109e 1892 /***************** Bit definition for DAC_DHR12RD register ******************/
<> 148:21d94c44109e 1893 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
<> 148:21d94c44109e 1894 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
<> 148:21d94c44109e 1895 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
<> 148:21d94c44109e 1896 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
<> 148:21d94c44109e 1897 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
<> 148:21d94c44109e 1898 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
<> 148:21d94c44109e 1899
<> 148:21d94c44109e 1900 /***************** Bit definition for DAC_DHR12LD register ******************/
<> 148:21d94c44109e 1901 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
<> 148:21d94c44109e 1902 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
<> 148:21d94c44109e 1903 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
<> 148:21d94c44109e 1904 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
<> 148:21d94c44109e 1905 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
<> 148:21d94c44109e 1906 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
<> 148:21d94c44109e 1907
<> 148:21d94c44109e 1908 /****************** Bit definition for DAC_DHR8RD register ******************/
<> 148:21d94c44109e 1909 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
<> 148:21d94c44109e 1910 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
<> 148:21d94c44109e 1911 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
<> 148:21d94c44109e 1912 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
<> 148:21d94c44109e 1913 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
<> 148:21d94c44109e 1914 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
<> 148:21d94c44109e 1915
<> 148:21d94c44109e 1916 /******************* Bit definition for DAC_DOR1 register *******************/
<> 148:21d94c44109e 1917 #define DAC_DOR1_DACC1DOR_Pos (0U)
<> 148:21d94c44109e 1918 #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
<> 148:21d94c44109e 1919 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
<> 148:21d94c44109e 1920
<> 148:21d94c44109e 1921 /******************* Bit definition for DAC_DOR2 register *******************/
<> 148:21d94c44109e 1922 #define DAC_DOR2_DACC2DOR_Pos (0U)
<> 148:21d94c44109e 1923 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
<> 148:21d94c44109e 1924 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
<> 148:21d94c44109e 1925
<> 148:21d94c44109e 1926 /******************** Bit definition for DAC_SR register ********************/
<> 148:21d94c44109e 1927 #define DAC_SR_DMAUDR1_Pos (13U)
<> 148:21d94c44109e 1928 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 1929 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
<> 148:21d94c44109e 1930 #define DAC_SR_DMAUDR2_Pos (29U)
<> 148:21d94c44109e 1931 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
<> 148:21d94c44109e 1932 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
<> 148:21d94c44109e 1933
<> 148:21d94c44109e 1934 /******************************************************************************/
<> 148:21d94c44109e 1935 /* */
<> 148:21d94c44109e 1936 /* Debug MCU (DBGMCU) */
<> 148:21d94c44109e 1937 /* */
<> 148:21d94c44109e 1938 /******************************************************************************/
<> 148:21d94c44109e 1939
<> 148:21d94c44109e 1940 /**************** Bit definition for DBGMCU_IDCODE register *****************/
<> 148:21d94c44109e 1941 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
<> 148:21d94c44109e 1942 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
<> 148:21d94c44109e 1943 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
<> 148:21d94c44109e 1944
<> 148:21d94c44109e 1945 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
<> 148:21d94c44109e 1946 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
<> 148:21d94c44109e 1947 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
<> 148:21d94c44109e 1948 #define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 1949 #define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 1950 #define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 1951 #define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 1952 #define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 1953 #define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 1954 #define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 1955 #define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 1956 #define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
<> 148:21d94c44109e 1957 #define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
<> 148:21d94c44109e 1958 #define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
<> 148:21d94c44109e 1959 #define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
<> 148:21d94c44109e 1960 #define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
<> 148:21d94c44109e 1961 #define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
<> 148:21d94c44109e 1962 #define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
<> 148:21d94c44109e 1963 #define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
<> 148:21d94c44109e 1964
<> 148:21d94c44109e 1965 /****************** Bit definition for DBGMCU_CR register *******************/
<> 148:21d94c44109e 1966 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
<> 148:21d94c44109e 1967 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 1968 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
<> 148:21d94c44109e 1969 #define DBGMCU_CR_DBG_STOP_Pos (1U)
<> 148:21d94c44109e 1970 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 1971 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
<> 148:21d94c44109e 1972 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
<> 148:21d94c44109e 1973 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 1974 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
<> 148:21d94c44109e 1975 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
<> 148:21d94c44109e 1976 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 1977 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */
<> 148:21d94c44109e 1978
<> 148:21d94c44109e 1979 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
<> 148:21d94c44109e 1980 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
<> 148:21d94c44109e 1981 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
<> 148:21d94c44109e 1982 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 1983 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 1984
<> 148:21d94c44109e 1985 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
<> 148:21d94c44109e 1986
<> 148:21d94c44109e 1987 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
<> 148:21d94c44109e 1988 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 1989 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
<> 148:21d94c44109e 1990 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
<> 148:21d94c44109e 1991 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 1992 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
<> 148:21d94c44109e 1993 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
<> 148:21d94c44109e 1994 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 1995 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
<> 148:21d94c44109e 1996 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
<> 148:21d94c44109e 1997 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 1998 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */
<> 148:21d94c44109e 1999 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
<> 148:21d94c44109e 2000 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 2001 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
<> 148:21d94c44109e 2002 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
<> 148:21d94c44109e 2003 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 2004 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
<> 148:21d94c44109e 2005 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
<> 148:21d94c44109e 2006 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 2007 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Counter stopped when Core is halted */
<> 148:21d94c44109e 2008 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
<> 148:21d94c44109e 2009 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 2010 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
<> 148:21d94c44109e 2011 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
<> 148:21d94c44109e 2012 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 2013 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
<> 148:21d94c44109e 2014 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
<> 148:21d94c44109e 2015 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 2016 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
<> 148:21d94c44109e 2017 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
<> 148:21d94c44109e 2018 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 2019 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
<> 148:21d94c44109e 2020
<> 148:21d94c44109e 2021 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
<> 148:21d94c44109e 2022
<> 148:21d94c44109e 2023 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (2U)
<> 148:21d94c44109e 2024 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 2025 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /*!< TIM9 counter stopped when core is halted */
<> 148:21d94c44109e 2026 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (3U)
<> 148:21d94c44109e 2027 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 2028 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /*!< TIM10 counter stopped when core is halted */
<> 148:21d94c44109e 2029 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (4U)
<> 148:21d94c44109e 2030 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 2031 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /*!< TIM11 counter stopped when core is halted */
<> 148:21d94c44109e 2032
<> 148:21d94c44109e 2033 /******************************************************************************/
<> 148:21d94c44109e 2034 /* */
<> 148:21d94c44109e 2035 /* DMA Controller (DMA) */
<> 148:21d94c44109e 2036 /* */
<> 148:21d94c44109e 2037 /******************************************************************************/
<> 148:21d94c44109e 2038
<> 148:21d94c44109e 2039 /******************* Bit definition for DMA_ISR register ********************/
<> 148:21d94c44109e 2040 #define DMA_ISR_GIF1_Pos (0U)
<> 148:21d94c44109e 2041 #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 2042 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
<> 148:21d94c44109e 2043 #define DMA_ISR_TCIF1_Pos (1U)
<> 148:21d94c44109e 2044 #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 2045 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
<> 148:21d94c44109e 2046 #define DMA_ISR_HTIF1_Pos (2U)
<> 148:21d94c44109e 2047 #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 2048 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
<> 148:21d94c44109e 2049 #define DMA_ISR_TEIF1_Pos (3U)
<> 148:21d94c44109e 2050 #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 2051 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
<> 148:21d94c44109e 2052 #define DMA_ISR_GIF2_Pos (4U)
<> 148:21d94c44109e 2053 #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 2054 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
<> 148:21d94c44109e 2055 #define DMA_ISR_TCIF2_Pos (5U)
<> 148:21d94c44109e 2056 #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 2057 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
<> 148:21d94c44109e 2058 #define DMA_ISR_HTIF2_Pos (6U)
<> 148:21d94c44109e 2059 #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 2060 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
<> 148:21d94c44109e 2061 #define DMA_ISR_TEIF2_Pos (7U)
<> 148:21d94c44109e 2062 #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 2063 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
<> 148:21d94c44109e 2064 #define DMA_ISR_GIF3_Pos (8U)
<> 148:21d94c44109e 2065 #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 2066 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
<> 148:21d94c44109e 2067 #define DMA_ISR_TCIF3_Pos (9U)
<> 148:21d94c44109e 2068 #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 2069 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
<> 148:21d94c44109e 2070 #define DMA_ISR_HTIF3_Pos (10U)
<> 148:21d94c44109e 2071 #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 2072 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
<> 148:21d94c44109e 2073 #define DMA_ISR_TEIF3_Pos (11U)
<> 148:21d94c44109e 2074 #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 2075 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
<> 148:21d94c44109e 2076 #define DMA_ISR_GIF4_Pos (12U)
<> 148:21d94c44109e 2077 #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 2078 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
<> 148:21d94c44109e 2079 #define DMA_ISR_TCIF4_Pos (13U)
<> 148:21d94c44109e 2080 #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 2081 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
<> 148:21d94c44109e 2082 #define DMA_ISR_HTIF4_Pos (14U)
<> 148:21d94c44109e 2083 #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 2084 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
<> 148:21d94c44109e 2085 #define DMA_ISR_TEIF4_Pos (15U)
<> 148:21d94c44109e 2086 #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 2087 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
<> 148:21d94c44109e 2088 #define DMA_ISR_GIF5_Pos (16U)
<> 148:21d94c44109e 2089 #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 2090 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
<> 148:21d94c44109e 2091 #define DMA_ISR_TCIF5_Pos (17U)
<> 148:21d94c44109e 2092 #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 2093 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
<> 148:21d94c44109e 2094 #define DMA_ISR_HTIF5_Pos (18U)
<> 148:21d94c44109e 2095 #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 2096 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
<> 148:21d94c44109e 2097 #define DMA_ISR_TEIF5_Pos (19U)
<> 148:21d94c44109e 2098 #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 2099 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
<> 148:21d94c44109e 2100 #define DMA_ISR_GIF6_Pos (20U)
<> 148:21d94c44109e 2101 #define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 2102 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
<> 148:21d94c44109e 2103 #define DMA_ISR_TCIF6_Pos (21U)
<> 148:21d94c44109e 2104 #define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 2105 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
<> 148:21d94c44109e 2106 #define DMA_ISR_HTIF6_Pos (22U)
<> 148:21d94c44109e 2107 #define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 2108 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
<> 148:21d94c44109e 2109 #define DMA_ISR_TEIF6_Pos (23U)
<> 148:21d94c44109e 2110 #define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 2111 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
<> 148:21d94c44109e 2112 #define DMA_ISR_GIF7_Pos (24U)
<> 148:21d94c44109e 2113 #define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
<> 148:21d94c44109e 2114 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
<> 148:21d94c44109e 2115 #define DMA_ISR_TCIF7_Pos (25U)
<> 148:21d94c44109e 2116 #define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
<> 148:21d94c44109e 2117 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
<> 148:21d94c44109e 2118 #define DMA_ISR_HTIF7_Pos (26U)
<> 148:21d94c44109e 2119 #define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
<> 148:21d94c44109e 2120 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
<> 148:21d94c44109e 2121 #define DMA_ISR_TEIF7_Pos (27U)
<> 148:21d94c44109e 2122 #define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
<> 148:21d94c44109e 2123 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
<> 148:21d94c44109e 2124
<> 148:21d94c44109e 2125 /******************* Bit definition for DMA_IFCR register *******************/
<> 148:21d94c44109e 2126 #define DMA_IFCR_CGIF1_Pos (0U)
<> 148:21d94c44109e 2127 #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 2128 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
<> 148:21d94c44109e 2129 #define DMA_IFCR_CTCIF1_Pos (1U)
<> 148:21d94c44109e 2130 #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 2131 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
<> 148:21d94c44109e 2132 #define DMA_IFCR_CHTIF1_Pos (2U)
<> 148:21d94c44109e 2133 #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 2134 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
<> 148:21d94c44109e 2135 #define DMA_IFCR_CTEIF1_Pos (3U)
<> 148:21d94c44109e 2136 #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 2137 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
<> 148:21d94c44109e 2138 #define DMA_IFCR_CGIF2_Pos (4U)
<> 148:21d94c44109e 2139 #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 2140 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
<> 148:21d94c44109e 2141 #define DMA_IFCR_CTCIF2_Pos (5U)
<> 148:21d94c44109e 2142 #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 2143 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
<> 148:21d94c44109e 2144 #define DMA_IFCR_CHTIF2_Pos (6U)
<> 148:21d94c44109e 2145 #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 2146 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
<> 148:21d94c44109e 2147 #define DMA_IFCR_CTEIF2_Pos (7U)
<> 148:21d94c44109e 2148 #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 2149 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
<> 148:21d94c44109e 2150 #define DMA_IFCR_CGIF3_Pos (8U)
<> 148:21d94c44109e 2151 #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 2152 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
<> 148:21d94c44109e 2153 #define DMA_IFCR_CTCIF3_Pos (9U)
<> 148:21d94c44109e 2154 #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 2155 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
<> 148:21d94c44109e 2156 #define DMA_IFCR_CHTIF3_Pos (10U)
<> 148:21d94c44109e 2157 #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 2158 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
<> 148:21d94c44109e 2159 #define DMA_IFCR_CTEIF3_Pos (11U)
<> 148:21d94c44109e 2160 #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 2161 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
<> 148:21d94c44109e 2162 #define DMA_IFCR_CGIF4_Pos (12U)
<> 148:21d94c44109e 2163 #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 2164 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
<> 148:21d94c44109e 2165 #define DMA_IFCR_CTCIF4_Pos (13U)
<> 148:21d94c44109e 2166 #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 2167 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
<> 148:21d94c44109e 2168 #define DMA_IFCR_CHTIF4_Pos (14U)
<> 148:21d94c44109e 2169 #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 2170 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
<> 148:21d94c44109e 2171 #define DMA_IFCR_CTEIF4_Pos (15U)
<> 148:21d94c44109e 2172 #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 2173 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
<> 148:21d94c44109e 2174 #define DMA_IFCR_CGIF5_Pos (16U)
<> 148:21d94c44109e 2175 #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 2176 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
<> 148:21d94c44109e 2177 #define DMA_IFCR_CTCIF5_Pos (17U)
<> 148:21d94c44109e 2178 #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 2179 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
<> 148:21d94c44109e 2180 #define DMA_IFCR_CHTIF5_Pos (18U)
<> 148:21d94c44109e 2181 #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 2182 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
<> 148:21d94c44109e 2183 #define DMA_IFCR_CTEIF5_Pos (19U)
<> 148:21d94c44109e 2184 #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 2185 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
<> 148:21d94c44109e 2186 #define DMA_IFCR_CGIF6_Pos (20U)
<> 148:21d94c44109e 2187 #define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 2188 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
<> 148:21d94c44109e 2189 #define DMA_IFCR_CTCIF6_Pos (21U)
<> 148:21d94c44109e 2190 #define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 2191 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
<> 148:21d94c44109e 2192 #define DMA_IFCR_CHTIF6_Pos (22U)
<> 148:21d94c44109e 2193 #define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 2194 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
<> 148:21d94c44109e 2195 #define DMA_IFCR_CTEIF6_Pos (23U)
<> 148:21d94c44109e 2196 #define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 2197 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
<> 148:21d94c44109e 2198 #define DMA_IFCR_CGIF7_Pos (24U)
<> 148:21d94c44109e 2199 #define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
<> 148:21d94c44109e 2200 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
<> 148:21d94c44109e 2201 #define DMA_IFCR_CTCIF7_Pos (25U)
<> 148:21d94c44109e 2202 #define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
<> 148:21d94c44109e 2203 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
<> 148:21d94c44109e 2204 #define DMA_IFCR_CHTIF7_Pos (26U)
<> 148:21d94c44109e 2205 #define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
<> 148:21d94c44109e 2206 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
<> 148:21d94c44109e 2207 #define DMA_IFCR_CTEIF7_Pos (27U)
<> 148:21d94c44109e 2208 #define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
<> 148:21d94c44109e 2209 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
<> 148:21d94c44109e 2210
<> 148:21d94c44109e 2211 /******************* Bit definition for DMA_CCR register *******************/
<> 148:21d94c44109e 2212 #define DMA_CCR_EN_Pos (0U)
<> 148:21d94c44109e 2213 #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 2214 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable*/
<> 148:21d94c44109e 2215 #define DMA_CCR_TCIE_Pos (1U)
<> 148:21d94c44109e 2216 #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 2217 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
<> 148:21d94c44109e 2218 #define DMA_CCR_HTIE_Pos (2U)
<> 148:21d94c44109e 2219 #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 2220 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
<> 148:21d94c44109e 2221 #define DMA_CCR_TEIE_Pos (3U)
<> 148:21d94c44109e 2222 #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 2223 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
<> 148:21d94c44109e 2224 #define DMA_CCR_DIR_Pos (4U)
<> 148:21d94c44109e 2225 #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 2226 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
<> 148:21d94c44109e 2227 #define DMA_CCR_CIRC_Pos (5U)
<> 148:21d94c44109e 2228 #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 2229 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
<> 148:21d94c44109e 2230 #define DMA_CCR_PINC_Pos (6U)
<> 148:21d94c44109e 2231 #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 2232 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
<> 148:21d94c44109e 2233 #define DMA_CCR_MINC_Pos (7U)
<> 148:21d94c44109e 2234 #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 2235 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
<> 148:21d94c44109e 2236
<> 148:21d94c44109e 2237 #define DMA_CCR_PSIZE_Pos (8U)
<> 148:21d94c44109e 2238 #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
<> 148:21d94c44109e 2239 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
<> 148:21d94c44109e 2240 #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 2241 #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 2242
<> 148:21d94c44109e 2243 #define DMA_CCR_MSIZE_Pos (10U)
<> 148:21d94c44109e 2244 #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
<> 148:21d94c44109e 2245 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
<> 148:21d94c44109e 2246 #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 2247 #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 2248
<> 148:21d94c44109e 2249 #define DMA_CCR_PL_Pos (12U)
<> 148:21d94c44109e 2250 #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
<> 148:21d94c44109e 2251 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */
<> 148:21d94c44109e 2252 #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 2253 #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 2254
<> 148:21d94c44109e 2255 #define DMA_CCR_MEM2MEM_Pos (14U)
<> 148:21d94c44109e 2256 #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 2257 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
<> 148:21d94c44109e 2258
<> 148:21d94c44109e 2259 /****************** Bit definition generic for DMA_CNDTR register *******************/
<> 148:21d94c44109e 2260 #define DMA_CNDTR_NDT_Pos (0U)
<> 148:21d94c44109e 2261 #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 2262 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
<> 148:21d94c44109e 2263
<> 148:21d94c44109e 2264 /****************** Bit definition for DMA_CNDTR1 register ******************/
<> 148:21d94c44109e 2265 #define DMA_CNDTR1_NDT_Pos (0U)
<> 148:21d94c44109e 2266 #define DMA_CNDTR1_NDT_Msk (0xFFFFU << DMA_CNDTR1_NDT_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 2267 #define DMA_CNDTR1_NDT DMA_CNDTR1_NDT_Msk /*!< Number of data to Transfer */
<> 148:21d94c44109e 2268
<> 148:21d94c44109e 2269 /****************** Bit definition for DMA_CNDTR2 register ******************/
<> 148:21d94c44109e 2270 #define DMA_CNDTR2_NDT_Pos (0U)
<> 148:21d94c44109e 2271 #define DMA_CNDTR2_NDT_Msk (0xFFFFU << DMA_CNDTR2_NDT_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 2272 #define DMA_CNDTR2_NDT DMA_CNDTR2_NDT_Msk /*!< Number of data to Transfer */
<> 148:21d94c44109e 2273
<> 148:21d94c44109e 2274 /****************** Bit definition for DMA_CNDTR3 register ******************/
<> 148:21d94c44109e 2275 #define DMA_CNDTR3_NDT_Pos (0U)
<> 148:21d94c44109e 2276 #define DMA_CNDTR3_NDT_Msk (0xFFFFU << DMA_CNDTR3_NDT_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 2277 #define DMA_CNDTR3_NDT DMA_CNDTR3_NDT_Msk /*!< Number of data to Transfer */
<> 148:21d94c44109e 2278
<> 148:21d94c44109e 2279 /****************** Bit definition for DMA_CNDTR4 register ******************/
<> 148:21d94c44109e 2280 #define DMA_CNDTR4_NDT_Pos (0U)
<> 148:21d94c44109e 2281 #define DMA_CNDTR4_NDT_Msk (0xFFFFU << DMA_CNDTR4_NDT_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 2282 #define DMA_CNDTR4_NDT DMA_CNDTR4_NDT_Msk /*!< Number of data to Transfer */
<> 148:21d94c44109e 2283
<> 148:21d94c44109e 2284 /****************** Bit definition for DMA_CNDTR5 register ******************/
<> 148:21d94c44109e 2285 #define DMA_CNDTR5_NDT_Pos (0U)
<> 148:21d94c44109e 2286 #define DMA_CNDTR5_NDT_Msk (0xFFFFU << DMA_CNDTR5_NDT_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 2287 #define DMA_CNDTR5_NDT DMA_CNDTR5_NDT_Msk /*!< Number of data to Transfer */
<> 148:21d94c44109e 2288
<> 148:21d94c44109e 2289 /****************** Bit definition for DMA_CNDTR6 register ******************/
<> 148:21d94c44109e 2290 #define DMA_CNDTR6_NDT_Pos (0U)
<> 148:21d94c44109e 2291 #define DMA_CNDTR6_NDT_Msk (0xFFFFU << DMA_CNDTR6_NDT_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 2292 #define DMA_CNDTR6_NDT DMA_CNDTR6_NDT_Msk /*!< Number of data to Transfer */
<> 148:21d94c44109e 2293
<> 148:21d94c44109e 2294 /****************** Bit definition for DMA_CNDTR7 register ******************/
<> 148:21d94c44109e 2295 #define DMA_CNDTR7_NDT_Pos (0U)
<> 148:21d94c44109e 2296 #define DMA_CNDTR7_NDT_Msk (0xFFFFU << DMA_CNDTR7_NDT_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 2297 #define DMA_CNDTR7_NDT DMA_CNDTR7_NDT_Msk /*!< Number of data to Transfer */
<> 148:21d94c44109e 2298
<> 148:21d94c44109e 2299 /****************** Bit definition generic for DMA_CPAR register ********************/
<> 148:21d94c44109e 2300 #define DMA_CPAR_PA_Pos (0U)
<> 148:21d94c44109e 2301 #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 2302 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
<> 148:21d94c44109e 2303
<> 148:21d94c44109e 2304 /****************** Bit definition for DMA_CPAR1 register *******************/
<> 148:21d94c44109e 2305 #define DMA_CPAR1_PA_Pos (0U)
<> 148:21d94c44109e 2306 #define DMA_CPAR1_PA_Msk (0xFFFFFFFFU << DMA_CPAR1_PA_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 2307 #define DMA_CPAR1_PA DMA_CPAR1_PA_Msk /*!< Peripheral Address */
<> 148:21d94c44109e 2308
<> 148:21d94c44109e 2309 /****************** Bit definition for DMA_CPAR2 register *******************/
<> 148:21d94c44109e 2310 #define DMA_CPAR2_PA_Pos (0U)
<> 148:21d94c44109e 2311 #define DMA_CPAR2_PA_Msk (0xFFFFFFFFU << DMA_CPAR2_PA_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 2312 #define DMA_CPAR2_PA DMA_CPAR2_PA_Msk /*!< Peripheral Address */
<> 148:21d94c44109e 2313
<> 148:21d94c44109e 2314 /****************** Bit definition for DMA_CPAR3 register *******************/
<> 148:21d94c44109e 2315 #define DMA_CPAR3_PA_Pos (0U)
<> 148:21d94c44109e 2316 #define DMA_CPAR3_PA_Msk (0xFFFFFFFFU << DMA_CPAR3_PA_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 2317 #define DMA_CPAR3_PA DMA_CPAR3_PA_Msk /*!< Peripheral Address */
<> 148:21d94c44109e 2318
<> 148:21d94c44109e 2319
<> 148:21d94c44109e 2320 /****************** Bit definition for DMA_CPAR4 register *******************/
<> 148:21d94c44109e 2321 #define DMA_CPAR4_PA_Pos (0U)
<> 148:21d94c44109e 2322 #define DMA_CPAR4_PA_Msk (0xFFFFFFFFU << DMA_CPAR4_PA_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 2323 #define DMA_CPAR4_PA DMA_CPAR4_PA_Msk /*!< Peripheral Address */
<> 148:21d94c44109e 2324
<> 148:21d94c44109e 2325 /****************** Bit definition for DMA_CPAR5 register *******************/
<> 148:21d94c44109e 2326 #define DMA_CPAR5_PA_Pos (0U)
<> 148:21d94c44109e 2327 #define DMA_CPAR5_PA_Msk (0xFFFFFFFFU << DMA_CPAR5_PA_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 2328 #define DMA_CPAR5_PA DMA_CPAR5_PA_Msk /*!< Peripheral Address */
<> 148:21d94c44109e 2329
<> 148:21d94c44109e 2330 /****************** Bit definition for DMA_CPAR6 register *******************/
<> 148:21d94c44109e 2331 #define DMA_CPAR6_PA_Pos (0U)
<> 148:21d94c44109e 2332 #define DMA_CPAR6_PA_Msk (0xFFFFFFFFU << DMA_CPAR6_PA_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 2333 #define DMA_CPAR6_PA DMA_CPAR6_PA_Msk /*!< Peripheral Address */
<> 148:21d94c44109e 2334
<> 148:21d94c44109e 2335
<> 148:21d94c44109e 2336 /****************** Bit definition for DMA_CPAR7 register *******************/
<> 148:21d94c44109e 2337 #define DMA_CPAR7_PA_Pos (0U)
<> 148:21d94c44109e 2338 #define DMA_CPAR7_PA_Msk (0xFFFFFFFFU << DMA_CPAR7_PA_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 2339 #define DMA_CPAR7_PA DMA_CPAR7_PA_Msk /*!< Peripheral Address */
<> 148:21d94c44109e 2340
<> 148:21d94c44109e 2341 /****************** Bit definition generic for DMA_CMAR register ********************/
<> 148:21d94c44109e 2342 #define DMA_CMAR_MA_Pos (0U)
<> 148:21d94c44109e 2343 #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 2344 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
<> 148:21d94c44109e 2345
<> 148:21d94c44109e 2346 /****************** Bit definition for DMA_CMAR1 register *******************/
<> 148:21d94c44109e 2347 #define DMA_CMAR1_MA_Pos (0U)
<> 148:21d94c44109e 2348 #define DMA_CMAR1_MA_Msk (0xFFFFFFFFU << DMA_CMAR1_MA_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 2349 #define DMA_CMAR1_MA DMA_CMAR1_MA_Msk /*!< Memory Address */
<> 148:21d94c44109e 2350
<> 148:21d94c44109e 2351 /****************** Bit definition for DMA_CMAR2 register *******************/
<> 148:21d94c44109e 2352 #define DMA_CMAR2_MA_Pos (0U)
<> 148:21d94c44109e 2353 #define DMA_CMAR2_MA_Msk (0xFFFFFFFFU << DMA_CMAR2_MA_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 2354 #define DMA_CMAR2_MA DMA_CMAR2_MA_Msk /*!< Memory Address */
<> 148:21d94c44109e 2355
<> 148:21d94c44109e 2356 /****************** Bit definition for DMA_CMAR3 register *******************/
<> 148:21d94c44109e 2357 #define DMA_CMAR3_MA_Pos (0U)
<> 148:21d94c44109e 2358 #define DMA_CMAR3_MA_Msk (0xFFFFFFFFU << DMA_CMAR3_MA_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 2359 #define DMA_CMAR3_MA DMA_CMAR3_MA_Msk /*!< Memory Address */
<> 148:21d94c44109e 2360
<> 148:21d94c44109e 2361
<> 148:21d94c44109e 2362 /****************** Bit definition for DMA_CMAR4 register *******************/
<> 148:21d94c44109e 2363 #define DMA_CMAR4_MA_Pos (0U)
<> 148:21d94c44109e 2364 #define DMA_CMAR4_MA_Msk (0xFFFFFFFFU << DMA_CMAR4_MA_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 2365 #define DMA_CMAR4_MA DMA_CMAR4_MA_Msk /*!< Memory Address */
<> 148:21d94c44109e 2366
<> 148:21d94c44109e 2367 /****************** Bit definition for DMA_CMAR5 register *******************/
<> 148:21d94c44109e 2368 #define DMA_CMAR5_MA_Pos (0U)
<> 148:21d94c44109e 2369 #define DMA_CMAR5_MA_Msk (0xFFFFFFFFU << DMA_CMAR5_MA_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 2370 #define DMA_CMAR5_MA DMA_CMAR5_MA_Msk /*!< Memory Address */
<> 148:21d94c44109e 2371
<> 148:21d94c44109e 2372 /****************** Bit definition for DMA_CMAR6 register *******************/
<> 148:21d94c44109e 2373 #define DMA_CMAR6_MA_Pos (0U)
<> 148:21d94c44109e 2374 #define DMA_CMAR6_MA_Msk (0xFFFFFFFFU << DMA_CMAR6_MA_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 2375 #define DMA_CMAR6_MA DMA_CMAR6_MA_Msk /*!< Memory Address */
<> 148:21d94c44109e 2376
<> 148:21d94c44109e 2377 /****************** Bit definition for DMA_CMAR7 register *******************/
<> 148:21d94c44109e 2378 #define DMA_CMAR7_MA_Pos (0U)
<> 148:21d94c44109e 2379 #define DMA_CMAR7_MA_Msk (0xFFFFFFFFU << DMA_CMAR7_MA_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 2380 #define DMA_CMAR7_MA DMA_CMAR7_MA_Msk /*!< Memory Address */
<> 148:21d94c44109e 2381
<> 148:21d94c44109e 2382 /******************************************************************************/
<> 148:21d94c44109e 2383 /* */
<> 148:21d94c44109e 2384 /* External Interrupt/Event Controller (EXTI) */
<> 148:21d94c44109e 2385 /* */
<> 148:21d94c44109e 2386 /******************************************************************************/
<> 148:21d94c44109e 2387
<> 148:21d94c44109e 2388 /******************* Bit definition for EXTI_IMR register *******************/
<> 148:21d94c44109e 2389 #define EXTI_IMR_MR0_Pos (0U)
<> 148:21d94c44109e 2390 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 2391 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
<> 148:21d94c44109e 2392 #define EXTI_IMR_MR1_Pos (1U)
<> 148:21d94c44109e 2393 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 2394 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
<> 148:21d94c44109e 2395 #define EXTI_IMR_MR2_Pos (2U)
<> 148:21d94c44109e 2396 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 2397 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
<> 148:21d94c44109e 2398 #define EXTI_IMR_MR3_Pos (3U)
<> 148:21d94c44109e 2399 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 2400 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
<> 148:21d94c44109e 2401 #define EXTI_IMR_MR4_Pos (4U)
<> 148:21d94c44109e 2402 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 2403 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
<> 148:21d94c44109e 2404 #define EXTI_IMR_MR5_Pos (5U)
<> 148:21d94c44109e 2405 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 2406 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
<> 148:21d94c44109e 2407 #define EXTI_IMR_MR6_Pos (6U)
<> 148:21d94c44109e 2408 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 2409 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
<> 148:21d94c44109e 2410 #define EXTI_IMR_MR7_Pos (7U)
<> 148:21d94c44109e 2411 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 2412 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
<> 148:21d94c44109e 2413 #define EXTI_IMR_MR8_Pos (8U)
<> 148:21d94c44109e 2414 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 2415 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
<> 148:21d94c44109e 2416 #define EXTI_IMR_MR9_Pos (9U)
<> 148:21d94c44109e 2417 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 2418 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
<> 148:21d94c44109e 2419 #define EXTI_IMR_MR10_Pos (10U)
<> 148:21d94c44109e 2420 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 2421 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
<> 148:21d94c44109e 2422 #define EXTI_IMR_MR11_Pos (11U)
<> 148:21d94c44109e 2423 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 2424 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
<> 148:21d94c44109e 2425 #define EXTI_IMR_MR12_Pos (12U)
<> 148:21d94c44109e 2426 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 2427 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
<> 148:21d94c44109e 2428 #define EXTI_IMR_MR13_Pos (13U)
<> 148:21d94c44109e 2429 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 2430 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
<> 148:21d94c44109e 2431 #define EXTI_IMR_MR14_Pos (14U)
<> 148:21d94c44109e 2432 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 2433 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
<> 148:21d94c44109e 2434 #define EXTI_IMR_MR15_Pos (15U)
<> 148:21d94c44109e 2435 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 2436 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
<> 148:21d94c44109e 2437 #define EXTI_IMR_MR16_Pos (16U)
<> 148:21d94c44109e 2438 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 2439 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
<> 148:21d94c44109e 2440 #define EXTI_IMR_MR17_Pos (17U)
<> 148:21d94c44109e 2441 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 2442 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
<> 148:21d94c44109e 2443 #define EXTI_IMR_MR18_Pos (18U)
<> 148:21d94c44109e 2444 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 2445 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
<> 148:21d94c44109e 2446 #define EXTI_IMR_MR19_Pos (19U)
<> 148:21d94c44109e 2447 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 2448 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
<> 148:21d94c44109e 2449 #define EXTI_IMR_MR20_Pos (20U)
<> 148:21d94c44109e 2450 #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 2451 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
<> 148:21d94c44109e 2452 #define EXTI_IMR_MR21_Pos (21U)
<> 148:21d94c44109e 2453 #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 2454 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
<> 148:21d94c44109e 2455 #define EXTI_IMR_MR22_Pos (22U)
<> 148:21d94c44109e 2456 #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 2457 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
<> 148:21d94c44109e 2458 #define EXTI_IMR_MR23_Pos (23U)
<> 148:21d94c44109e 2459 #define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 2460 #define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */
<> 148:21d94c44109e 2461
<> 148:21d94c44109e 2462 /* References Defines */
<> 148:21d94c44109e 2463 #define EXTI_IMR_IM0 EXTI_IMR_MR0
<> 148:21d94c44109e 2464 #define EXTI_IMR_IM1 EXTI_IMR_MR1
<> 148:21d94c44109e 2465 #define EXTI_IMR_IM2 EXTI_IMR_MR2
<> 148:21d94c44109e 2466 #define EXTI_IMR_IM3 EXTI_IMR_MR3
<> 148:21d94c44109e 2467 #define EXTI_IMR_IM4 EXTI_IMR_MR4
<> 148:21d94c44109e 2468 #define EXTI_IMR_IM5 EXTI_IMR_MR5
<> 148:21d94c44109e 2469 #define EXTI_IMR_IM6 EXTI_IMR_MR6
<> 148:21d94c44109e 2470 #define EXTI_IMR_IM7 EXTI_IMR_MR7
<> 148:21d94c44109e 2471 #define EXTI_IMR_IM8 EXTI_IMR_MR8
<> 148:21d94c44109e 2472 #define EXTI_IMR_IM9 EXTI_IMR_MR9
<> 148:21d94c44109e 2473 #define EXTI_IMR_IM10 EXTI_IMR_MR10
<> 148:21d94c44109e 2474 #define EXTI_IMR_IM11 EXTI_IMR_MR11
<> 148:21d94c44109e 2475 #define EXTI_IMR_IM12 EXTI_IMR_MR12
<> 148:21d94c44109e 2476 #define EXTI_IMR_IM13 EXTI_IMR_MR13
<> 148:21d94c44109e 2477 #define EXTI_IMR_IM14 EXTI_IMR_MR14
<> 148:21d94c44109e 2478 #define EXTI_IMR_IM15 EXTI_IMR_MR15
<> 148:21d94c44109e 2479 #define EXTI_IMR_IM16 EXTI_IMR_MR16
<> 148:21d94c44109e 2480 #define EXTI_IMR_IM17 EXTI_IMR_MR17
<> 148:21d94c44109e 2481 #define EXTI_IMR_IM18 EXTI_IMR_MR18
<> 148:21d94c44109e 2482 #define EXTI_IMR_IM19 EXTI_IMR_MR19
<> 148:21d94c44109e 2483 #define EXTI_IMR_IM20 EXTI_IMR_MR20
<> 148:21d94c44109e 2484 #define EXTI_IMR_IM21 EXTI_IMR_MR21
<> 148:21d94c44109e 2485 #define EXTI_IMR_IM22 EXTI_IMR_MR22
<> 148:21d94c44109e 2486 /* Category 3, 4 & 5 */
<> 148:21d94c44109e 2487 #define EXTI_IMR_IM23 EXTI_IMR_MR23
<> 148:21d94c44109e 2488 #define EXTI_IMR_IM_Pos (0U)
<> 148:21d94c44109e 2489 #define EXTI_IMR_IM_Msk (0xFFFFFFU << EXTI_IMR_IM_Pos) /*!< 0x00FFFFFF */
<> 148:21d94c44109e 2490 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
<> 148:21d94c44109e 2491
<> 148:21d94c44109e 2492 /******************* Bit definition for EXTI_EMR register *******************/
<> 148:21d94c44109e 2493 #define EXTI_EMR_MR0_Pos (0U)
<> 148:21d94c44109e 2494 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 2495 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
<> 148:21d94c44109e 2496 #define EXTI_EMR_MR1_Pos (1U)
<> 148:21d94c44109e 2497 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 2498 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
<> 148:21d94c44109e 2499 #define EXTI_EMR_MR2_Pos (2U)
<> 148:21d94c44109e 2500 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 2501 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
<> 148:21d94c44109e 2502 #define EXTI_EMR_MR3_Pos (3U)
<> 148:21d94c44109e 2503 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 2504 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
<> 148:21d94c44109e 2505 #define EXTI_EMR_MR4_Pos (4U)
<> 148:21d94c44109e 2506 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 2507 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
<> 148:21d94c44109e 2508 #define EXTI_EMR_MR5_Pos (5U)
<> 148:21d94c44109e 2509 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 2510 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
<> 148:21d94c44109e 2511 #define EXTI_EMR_MR6_Pos (6U)
<> 148:21d94c44109e 2512 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 2513 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
<> 148:21d94c44109e 2514 #define EXTI_EMR_MR7_Pos (7U)
<> 148:21d94c44109e 2515 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 2516 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
<> 148:21d94c44109e 2517 #define EXTI_EMR_MR8_Pos (8U)
<> 148:21d94c44109e 2518 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 2519 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
<> 148:21d94c44109e 2520 #define EXTI_EMR_MR9_Pos (9U)
<> 148:21d94c44109e 2521 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 2522 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
<> 148:21d94c44109e 2523 #define EXTI_EMR_MR10_Pos (10U)
<> 148:21d94c44109e 2524 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 2525 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
<> 148:21d94c44109e 2526 #define EXTI_EMR_MR11_Pos (11U)
<> 148:21d94c44109e 2527 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 2528 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
<> 148:21d94c44109e 2529 #define EXTI_EMR_MR12_Pos (12U)
<> 148:21d94c44109e 2530 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 2531 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
<> 148:21d94c44109e 2532 #define EXTI_EMR_MR13_Pos (13U)
<> 148:21d94c44109e 2533 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 2534 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
<> 148:21d94c44109e 2535 #define EXTI_EMR_MR14_Pos (14U)
<> 148:21d94c44109e 2536 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 2537 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
<> 148:21d94c44109e 2538 #define EXTI_EMR_MR15_Pos (15U)
<> 148:21d94c44109e 2539 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 2540 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
<> 148:21d94c44109e 2541 #define EXTI_EMR_MR16_Pos (16U)
<> 148:21d94c44109e 2542 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 2543 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
<> 148:21d94c44109e 2544 #define EXTI_EMR_MR17_Pos (17U)
<> 148:21d94c44109e 2545 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 2546 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
<> 148:21d94c44109e 2547 #define EXTI_EMR_MR18_Pos (18U)
<> 148:21d94c44109e 2548 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 2549 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
<> 148:21d94c44109e 2550 #define EXTI_EMR_MR19_Pos (19U)
<> 148:21d94c44109e 2551 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 2552 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
<> 148:21d94c44109e 2553 #define EXTI_EMR_MR20_Pos (20U)
<> 148:21d94c44109e 2554 #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 2555 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
<> 148:21d94c44109e 2556 #define EXTI_EMR_MR21_Pos (21U)
<> 148:21d94c44109e 2557 #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 2558 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
<> 148:21d94c44109e 2559 #define EXTI_EMR_MR22_Pos (22U)
<> 148:21d94c44109e 2560 #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 2561 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
<> 148:21d94c44109e 2562 #define EXTI_EMR_MR23_Pos (23U)
<> 148:21d94c44109e 2563 #define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 2564 #define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */
<> 148:21d94c44109e 2565
<> 148:21d94c44109e 2566 /* References Defines */
<> 148:21d94c44109e 2567 #define EXTI_EMR_EM0 EXTI_EMR_MR0
<> 148:21d94c44109e 2568 #define EXTI_EMR_EM1 EXTI_EMR_MR1
<> 148:21d94c44109e 2569 #define EXTI_EMR_EM2 EXTI_EMR_MR2
<> 148:21d94c44109e 2570 #define EXTI_EMR_EM3 EXTI_EMR_MR3
<> 148:21d94c44109e 2571 #define EXTI_EMR_EM4 EXTI_EMR_MR4
<> 148:21d94c44109e 2572 #define EXTI_EMR_EM5 EXTI_EMR_MR5
<> 148:21d94c44109e 2573 #define EXTI_EMR_EM6 EXTI_EMR_MR6
<> 148:21d94c44109e 2574 #define EXTI_EMR_EM7 EXTI_EMR_MR7
<> 148:21d94c44109e 2575 #define EXTI_EMR_EM8 EXTI_EMR_MR8
<> 148:21d94c44109e 2576 #define EXTI_EMR_EM9 EXTI_EMR_MR9
<> 148:21d94c44109e 2577 #define EXTI_EMR_EM10 EXTI_EMR_MR10
<> 148:21d94c44109e 2578 #define EXTI_EMR_EM11 EXTI_EMR_MR11
<> 148:21d94c44109e 2579 #define EXTI_EMR_EM12 EXTI_EMR_MR12
<> 148:21d94c44109e 2580 #define EXTI_EMR_EM13 EXTI_EMR_MR13
<> 148:21d94c44109e 2581 #define EXTI_EMR_EM14 EXTI_EMR_MR14
<> 148:21d94c44109e 2582 #define EXTI_EMR_EM15 EXTI_EMR_MR15
<> 148:21d94c44109e 2583 #define EXTI_EMR_EM16 EXTI_EMR_MR16
<> 148:21d94c44109e 2584 #define EXTI_EMR_EM17 EXTI_EMR_MR17
<> 148:21d94c44109e 2585 #define EXTI_EMR_EM18 EXTI_EMR_MR18
<> 148:21d94c44109e 2586 #define EXTI_EMR_EM19 EXTI_EMR_MR19
<> 148:21d94c44109e 2587 #define EXTI_EMR_EM20 EXTI_EMR_MR20
<> 148:21d94c44109e 2588 #define EXTI_EMR_EM21 EXTI_EMR_MR21
<> 148:21d94c44109e 2589 #define EXTI_EMR_EM22 EXTI_EMR_MR22
<> 148:21d94c44109e 2590 #define EXTI_EMR_EM23 EXTI_EMR_MR23
<> 148:21d94c44109e 2591
<> 148:21d94c44109e 2592 /****************** Bit definition for EXTI_RTSR register *******************/
<> 148:21d94c44109e 2593 #define EXTI_RTSR_TR0_Pos (0U)
<> 148:21d94c44109e 2594 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 2595 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
<> 148:21d94c44109e 2596 #define EXTI_RTSR_TR1_Pos (1U)
<> 148:21d94c44109e 2597 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 2598 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
<> 148:21d94c44109e 2599 #define EXTI_RTSR_TR2_Pos (2U)
<> 148:21d94c44109e 2600 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 2601 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
<> 148:21d94c44109e 2602 #define EXTI_RTSR_TR3_Pos (3U)
<> 148:21d94c44109e 2603 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 2604 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
<> 148:21d94c44109e 2605 #define EXTI_RTSR_TR4_Pos (4U)
<> 148:21d94c44109e 2606 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 2607 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
<> 148:21d94c44109e 2608 #define EXTI_RTSR_TR5_Pos (5U)
<> 148:21d94c44109e 2609 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 2610 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
<> 148:21d94c44109e 2611 #define EXTI_RTSR_TR6_Pos (6U)
<> 148:21d94c44109e 2612 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 2613 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
<> 148:21d94c44109e 2614 #define EXTI_RTSR_TR7_Pos (7U)
<> 148:21d94c44109e 2615 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 2616 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
<> 148:21d94c44109e 2617 #define EXTI_RTSR_TR8_Pos (8U)
<> 148:21d94c44109e 2618 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 2619 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
<> 148:21d94c44109e 2620 #define EXTI_RTSR_TR9_Pos (9U)
<> 148:21d94c44109e 2621 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 2622 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
<> 148:21d94c44109e 2623 #define EXTI_RTSR_TR10_Pos (10U)
<> 148:21d94c44109e 2624 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 2625 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
<> 148:21d94c44109e 2626 #define EXTI_RTSR_TR11_Pos (11U)
<> 148:21d94c44109e 2627 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 2628 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
<> 148:21d94c44109e 2629 #define EXTI_RTSR_TR12_Pos (12U)
<> 148:21d94c44109e 2630 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 2631 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
<> 148:21d94c44109e 2632 #define EXTI_RTSR_TR13_Pos (13U)
<> 148:21d94c44109e 2633 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 2634 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
<> 148:21d94c44109e 2635 #define EXTI_RTSR_TR14_Pos (14U)
<> 148:21d94c44109e 2636 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 2637 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
<> 148:21d94c44109e 2638 #define EXTI_RTSR_TR15_Pos (15U)
<> 148:21d94c44109e 2639 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 2640 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
<> 148:21d94c44109e 2641 #define EXTI_RTSR_TR16_Pos (16U)
<> 148:21d94c44109e 2642 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 2643 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
<> 148:21d94c44109e 2644 #define EXTI_RTSR_TR17_Pos (17U)
<> 148:21d94c44109e 2645 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 2646 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
<> 148:21d94c44109e 2647 #define EXTI_RTSR_TR18_Pos (18U)
<> 148:21d94c44109e 2648 #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 2649 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
<> 148:21d94c44109e 2650 #define EXTI_RTSR_TR19_Pos (19U)
<> 148:21d94c44109e 2651 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 2652 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
<> 148:21d94c44109e 2653 #define EXTI_RTSR_TR20_Pos (20U)
<> 148:21d94c44109e 2654 #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 2655 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
<> 148:21d94c44109e 2656 #define EXTI_RTSR_TR21_Pos (21U)
<> 148:21d94c44109e 2657 #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 2658 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
<> 148:21d94c44109e 2659 #define EXTI_RTSR_TR22_Pos (22U)
<> 148:21d94c44109e 2660 #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 2661 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
<> 148:21d94c44109e 2662 #define EXTI_RTSR_TR23_Pos (23U)
<> 148:21d94c44109e 2663 #define EXTI_RTSR_TR23_Msk (0x1U << EXTI_RTSR_TR23_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 2664 #define EXTI_RTSR_TR23 EXTI_RTSR_TR23_Msk /*!< Rising trigger event configuration bit of line 23 */
<> 148:21d94c44109e 2665
<> 148:21d94c44109e 2666 /* References Defines */
<> 148:21d94c44109e 2667 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0
<> 148:21d94c44109e 2668 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1
<> 148:21d94c44109e 2669 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2
<> 148:21d94c44109e 2670 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3
<> 148:21d94c44109e 2671 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4
<> 148:21d94c44109e 2672 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5
<> 148:21d94c44109e 2673 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6
<> 148:21d94c44109e 2674 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7
<> 148:21d94c44109e 2675 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8
<> 148:21d94c44109e 2676 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9
<> 148:21d94c44109e 2677 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10
<> 148:21d94c44109e 2678 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11
<> 148:21d94c44109e 2679 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12
<> 148:21d94c44109e 2680 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13
<> 148:21d94c44109e 2681 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14
<> 148:21d94c44109e 2682 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15
<> 148:21d94c44109e 2683 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16
<> 148:21d94c44109e 2684 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17
<> 148:21d94c44109e 2685 #define EXTI_RTSR_RT18 EXTI_RTSR_TR18
<> 148:21d94c44109e 2686 #define EXTI_RTSR_RT19 EXTI_RTSR_TR19
<> 148:21d94c44109e 2687 #define EXTI_RTSR_RT20 EXTI_RTSR_TR20
<> 148:21d94c44109e 2688 #define EXTI_RTSR_RT21 EXTI_RTSR_TR21
<> 148:21d94c44109e 2689 #define EXTI_RTSR_RT22 EXTI_RTSR_TR22
<> 148:21d94c44109e 2690 #define EXTI_RTSR_RT23 EXTI_RTSR_TR23
<> 148:21d94c44109e 2691
<> 148:21d94c44109e 2692 /****************** Bit definition for EXTI_FTSR register *******************/
<> 148:21d94c44109e 2693 #define EXTI_FTSR_TR0_Pos (0U)
<> 148:21d94c44109e 2694 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 2695 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
<> 148:21d94c44109e 2696 #define EXTI_FTSR_TR1_Pos (1U)
<> 148:21d94c44109e 2697 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 2698 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
<> 148:21d94c44109e 2699 #define EXTI_FTSR_TR2_Pos (2U)
<> 148:21d94c44109e 2700 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 2701 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
<> 148:21d94c44109e 2702 #define EXTI_FTSR_TR3_Pos (3U)
<> 148:21d94c44109e 2703 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 2704 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
<> 148:21d94c44109e 2705 #define EXTI_FTSR_TR4_Pos (4U)
<> 148:21d94c44109e 2706 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 2707 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
<> 148:21d94c44109e 2708 #define EXTI_FTSR_TR5_Pos (5U)
<> 148:21d94c44109e 2709 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 2710 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
<> 148:21d94c44109e 2711 #define EXTI_FTSR_TR6_Pos (6U)
<> 148:21d94c44109e 2712 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 2713 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
<> 148:21d94c44109e 2714 #define EXTI_FTSR_TR7_Pos (7U)
<> 148:21d94c44109e 2715 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 2716 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
<> 148:21d94c44109e 2717 #define EXTI_FTSR_TR8_Pos (8U)
<> 148:21d94c44109e 2718 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 2719 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
<> 148:21d94c44109e 2720 #define EXTI_FTSR_TR9_Pos (9U)
<> 148:21d94c44109e 2721 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 2722 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
<> 148:21d94c44109e 2723 #define EXTI_FTSR_TR10_Pos (10U)
<> 148:21d94c44109e 2724 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 2725 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
<> 148:21d94c44109e 2726 #define EXTI_FTSR_TR11_Pos (11U)
<> 148:21d94c44109e 2727 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 2728 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
<> 148:21d94c44109e 2729 #define EXTI_FTSR_TR12_Pos (12U)
<> 148:21d94c44109e 2730 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 2731 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
<> 148:21d94c44109e 2732 #define EXTI_FTSR_TR13_Pos (13U)
<> 148:21d94c44109e 2733 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 2734 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
<> 148:21d94c44109e 2735 #define EXTI_FTSR_TR14_Pos (14U)
<> 148:21d94c44109e 2736 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 2737 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
<> 148:21d94c44109e 2738 #define EXTI_FTSR_TR15_Pos (15U)
<> 148:21d94c44109e 2739 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 2740 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
<> 148:21d94c44109e 2741 #define EXTI_FTSR_TR16_Pos (16U)
<> 148:21d94c44109e 2742 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 2743 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
<> 148:21d94c44109e 2744 #define EXTI_FTSR_TR17_Pos (17U)
<> 148:21d94c44109e 2745 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 2746 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
<> 148:21d94c44109e 2747 #define EXTI_FTSR_TR18_Pos (18U)
<> 148:21d94c44109e 2748 #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 2749 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
<> 148:21d94c44109e 2750 #define EXTI_FTSR_TR19_Pos (19U)
<> 148:21d94c44109e 2751 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 2752 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
<> 148:21d94c44109e 2753 #define EXTI_FTSR_TR20_Pos (20U)
<> 148:21d94c44109e 2754 #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 2755 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
<> 148:21d94c44109e 2756 #define EXTI_FTSR_TR21_Pos (21U)
<> 148:21d94c44109e 2757 #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 2758 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
<> 148:21d94c44109e 2759 #define EXTI_FTSR_TR22_Pos (22U)
<> 148:21d94c44109e 2760 #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 2761 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
<> 148:21d94c44109e 2762 #define EXTI_FTSR_TR23_Pos (23U)
<> 148:21d94c44109e 2763 #define EXTI_FTSR_TR23_Msk (0x1U << EXTI_FTSR_TR23_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 2764 #define EXTI_FTSR_TR23 EXTI_FTSR_TR23_Msk /*!< Falling trigger event configuration bit of line 23 */
<> 148:21d94c44109e 2765
<> 148:21d94c44109e 2766 /* References Defines */
<> 148:21d94c44109e 2767 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0
<> 148:21d94c44109e 2768 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1
<> 148:21d94c44109e 2769 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2
<> 148:21d94c44109e 2770 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3
<> 148:21d94c44109e 2771 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4
<> 148:21d94c44109e 2772 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5
<> 148:21d94c44109e 2773 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6
<> 148:21d94c44109e 2774 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7
<> 148:21d94c44109e 2775 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8
<> 148:21d94c44109e 2776 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9
<> 148:21d94c44109e 2777 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10
<> 148:21d94c44109e 2778 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11
<> 148:21d94c44109e 2779 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12
<> 148:21d94c44109e 2780 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13
<> 148:21d94c44109e 2781 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14
<> 148:21d94c44109e 2782 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15
<> 148:21d94c44109e 2783 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16
<> 148:21d94c44109e 2784 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17
<> 148:21d94c44109e 2785 #define EXTI_FTSR_FT18 EXTI_FTSR_TR18
<> 148:21d94c44109e 2786 #define EXTI_FTSR_FT19 EXTI_FTSR_TR19
<> 148:21d94c44109e 2787 #define EXTI_FTSR_FT20 EXTI_FTSR_TR20
<> 148:21d94c44109e 2788 #define EXTI_FTSR_FT21 EXTI_FTSR_TR21
<> 148:21d94c44109e 2789 #define EXTI_FTSR_FT22 EXTI_FTSR_TR22
<> 148:21d94c44109e 2790 #define EXTI_FTSR_FT23 EXTI_FTSR_TR23
<> 148:21d94c44109e 2791
<> 148:21d94c44109e 2792 /****************** Bit definition for EXTI_SWIER register ******************/
<> 148:21d94c44109e 2793 #define EXTI_SWIER_SWIER0_Pos (0U)
<> 148:21d94c44109e 2794 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 2795 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
<> 148:21d94c44109e 2796 #define EXTI_SWIER_SWIER1_Pos (1U)
<> 148:21d94c44109e 2797 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 2798 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
<> 148:21d94c44109e 2799 #define EXTI_SWIER_SWIER2_Pos (2U)
<> 148:21d94c44109e 2800 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 2801 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
<> 148:21d94c44109e 2802 #define EXTI_SWIER_SWIER3_Pos (3U)
<> 148:21d94c44109e 2803 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 2804 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
<> 148:21d94c44109e 2805 #define EXTI_SWIER_SWIER4_Pos (4U)
<> 148:21d94c44109e 2806 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 2807 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
<> 148:21d94c44109e 2808 #define EXTI_SWIER_SWIER5_Pos (5U)
<> 148:21d94c44109e 2809 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 2810 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
<> 148:21d94c44109e 2811 #define EXTI_SWIER_SWIER6_Pos (6U)
<> 148:21d94c44109e 2812 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 2813 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
<> 148:21d94c44109e 2814 #define EXTI_SWIER_SWIER7_Pos (7U)
<> 148:21d94c44109e 2815 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 2816 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
<> 148:21d94c44109e 2817 #define EXTI_SWIER_SWIER8_Pos (8U)
<> 148:21d94c44109e 2818 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 2819 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
<> 148:21d94c44109e 2820 #define EXTI_SWIER_SWIER9_Pos (9U)
<> 148:21d94c44109e 2821 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 2822 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
<> 148:21d94c44109e 2823 #define EXTI_SWIER_SWIER10_Pos (10U)
<> 148:21d94c44109e 2824 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 2825 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
<> 148:21d94c44109e 2826 #define EXTI_SWIER_SWIER11_Pos (11U)
<> 148:21d94c44109e 2827 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 2828 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
<> 148:21d94c44109e 2829 #define EXTI_SWIER_SWIER12_Pos (12U)
<> 148:21d94c44109e 2830 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 2831 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
<> 148:21d94c44109e 2832 #define EXTI_SWIER_SWIER13_Pos (13U)
<> 148:21d94c44109e 2833 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 2834 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
<> 148:21d94c44109e 2835 #define EXTI_SWIER_SWIER14_Pos (14U)
<> 148:21d94c44109e 2836 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 2837 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
<> 148:21d94c44109e 2838 #define EXTI_SWIER_SWIER15_Pos (15U)
<> 148:21d94c44109e 2839 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 2840 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
<> 148:21d94c44109e 2841 #define EXTI_SWIER_SWIER16_Pos (16U)
<> 148:21d94c44109e 2842 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 2843 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
<> 148:21d94c44109e 2844 #define EXTI_SWIER_SWIER17_Pos (17U)
<> 148:21d94c44109e 2845 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 2846 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
<> 148:21d94c44109e 2847 #define EXTI_SWIER_SWIER18_Pos (18U)
<> 148:21d94c44109e 2848 #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 2849 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
<> 148:21d94c44109e 2850 #define EXTI_SWIER_SWIER19_Pos (19U)
<> 148:21d94c44109e 2851 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 2852 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
<> 148:21d94c44109e 2853 #define EXTI_SWIER_SWIER20_Pos (20U)
<> 148:21d94c44109e 2854 #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 2855 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
<> 148:21d94c44109e 2856 #define EXTI_SWIER_SWIER21_Pos (21U)
<> 148:21d94c44109e 2857 #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 2858 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
<> 148:21d94c44109e 2859 #define EXTI_SWIER_SWIER22_Pos (22U)
<> 148:21d94c44109e 2860 #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 2861 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
<> 148:21d94c44109e 2862 #define EXTI_SWIER_SWIER23_Pos (23U)
<> 148:21d94c44109e 2863 #define EXTI_SWIER_SWIER23_Msk (0x1U << EXTI_SWIER_SWIER23_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 2864 #define EXTI_SWIER_SWIER23 EXTI_SWIER_SWIER23_Msk /*!< Software Interrupt on line 23 */
<> 148:21d94c44109e 2865
<> 148:21d94c44109e 2866 /* References Defines */
<> 148:21d94c44109e 2867 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
<> 148:21d94c44109e 2868 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
<> 148:21d94c44109e 2869 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
<> 148:21d94c44109e 2870 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
<> 148:21d94c44109e 2871 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
<> 148:21d94c44109e 2872 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
<> 148:21d94c44109e 2873 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
<> 148:21d94c44109e 2874 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
<> 148:21d94c44109e 2875 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
<> 148:21d94c44109e 2876 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
<> 148:21d94c44109e 2877 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
<> 148:21d94c44109e 2878 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
<> 148:21d94c44109e 2879 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
<> 148:21d94c44109e 2880 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
<> 148:21d94c44109e 2881 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
<> 148:21d94c44109e 2882 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
<> 148:21d94c44109e 2883 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
<> 148:21d94c44109e 2884 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
<> 148:21d94c44109e 2885 #define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
<> 148:21d94c44109e 2886 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
<> 148:21d94c44109e 2887 #define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
<> 148:21d94c44109e 2888 #define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
<> 148:21d94c44109e 2889 #define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
<> 148:21d94c44109e 2890 #define EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
<> 148:21d94c44109e 2891
<> 148:21d94c44109e 2892 /******************* Bit definition for EXTI_PR register ********************/
<> 148:21d94c44109e 2893 #define EXTI_PR_PR0_Pos (0U)
<> 148:21d94c44109e 2894 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 2895 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
<> 148:21d94c44109e 2896 #define EXTI_PR_PR1_Pos (1U)
<> 148:21d94c44109e 2897 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 2898 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
<> 148:21d94c44109e 2899 #define EXTI_PR_PR2_Pos (2U)
<> 148:21d94c44109e 2900 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 2901 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
<> 148:21d94c44109e 2902 #define EXTI_PR_PR3_Pos (3U)
<> 148:21d94c44109e 2903 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 2904 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
<> 148:21d94c44109e 2905 #define EXTI_PR_PR4_Pos (4U)
<> 148:21d94c44109e 2906 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 2907 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
<> 148:21d94c44109e 2908 #define EXTI_PR_PR5_Pos (5U)
<> 148:21d94c44109e 2909 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 2910 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
<> 148:21d94c44109e 2911 #define EXTI_PR_PR6_Pos (6U)
<> 148:21d94c44109e 2912 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 2913 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
<> 148:21d94c44109e 2914 #define EXTI_PR_PR7_Pos (7U)
<> 148:21d94c44109e 2915 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 2916 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
<> 148:21d94c44109e 2917 #define EXTI_PR_PR8_Pos (8U)
<> 148:21d94c44109e 2918 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 2919 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
<> 148:21d94c44109e 2920 #define EXTI_PR_PR9_Pos (9U)
<> 148:21d94c44109e 2921 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 2922 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
<> 148:21d94c44109e 2923 #define EXTI_PR_PR10_Pos (10U)
<> 148:21d94c44109e 2924 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 2925 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
<> 148:21d94c44109e 2926 #define EXTI_PR_PR11_Pos (11U)
<> 148:21d94c44109e 2927 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 2928 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
<> 148:21d94c44109e 2929 #define EXTI_PR_PR12_Pos (12U)
<> 148:21d94c44109e 2930 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 2931 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
<> 148:21d94c44109e 2932 #define EXTI_PR_PR13_Pos (13U)
<> 148:21d94c44109e 2933 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 2934 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
<> 148:21d94c44109e 2935 #define EXTI_PR_PR14_Pos (14U)
<> 148:21d94c44109e 2936 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 2937 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
<> 148:21d94c44109e 2938 #define EXTI_PR_PR15_Pos (15U)
<> 148:21d94c44109e 2939 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 2940 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
<> 148:21d94c44109e 2941 #define EXTI_PR_PR16_Pos (16U)
<> 148:21d94c44109e 2942 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 2943 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
<> 148:21d94c44109e 2944 #define EXTI_PR_PR17_Pos (17U)
<> 148:21d94c44109e 2945 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 2946 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
<> 148:21d94c44109e 2947 #define EXTI_PR_PR18_Pos (18U)
<> 148:21d94c44109e 2948 #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 2949 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
<> 148:21d94c44109e 2950 #define EXTI_PR_PR19_Pos (19U)
<> 148:21d94c44109e 2951 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 2952 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
<> 148:21d94c44109e 2953 #define EXTI_PR_PR20_Pos (20U)
<> 148:21d94c44109e 2954 #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 2955 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
<> 148:21d94c44109e 2956 #define EXTI_PR_PR21_Pos (21U)
<> 148:21d94c44109e 2957 #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 2958 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
<> 148:21d94c44109e 2959 #define EXTI_PR_PR22_Pos (22U)
<> 148:21d94c44109e 2960 #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 2961 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
<> 148:21d94c44109e 2962 #define EXTI_PR_PR23_Pos (23U)
<> 148:21d94c44109e 2963 #define EXTI_PR_PR23_Msk (0x1U << EXTI_PR_PR23_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 2964 #define EXTI_PR_PR23 EXTI_PR_PR23_Msk /*!< Pending bit for line 23 */
<> 148:21d94c44109e 2965
<> 148:21d94c44109e 2966 /* References Defines */
<> 148:21d94c44109e 2967 #define EXTI_PR_PIF0 EXTI_PR_PR0
<> 148:21d94c44109e 2968 #define EXTI_PR_PIF1 EXTI_PR_PR1
<> 148:21d94c44109e 2969 #define EXTI_PR_PIF2 EXTI_PR_PR2
<> 148:21d94c44109e 2970 #define EXTI_PR_PIF3 EXTI_PR_PR3
<> 148:21d94c44109e 2971 #define EXTI_PR_PIF4 EXTI_PR_PR4
<> 148:21d94c44109e 2972 #define EXTI_PR_PIF5 EXTI_PR_PR5
<> 148:21d94c44109e 2973 #define EXTI_PR_PIF6 EXTI_PR_PR6
<> 148:21d94c44109e 2974 #define EXTI_PR_PIF7 EXTI_PR_PR7
<> 148:21d94c44109e 2975 #define EXTI_PR_PIF8 EXTI_PR_PR8
<> 148:21d94c44109e 2976 #define EXTI_PR_PIF9 EXTI_PR_PR9
<> 148:21d94c44109e 2977 #define EXTI_PR_PIF10 EXTI_PR_PR10
<> 148:21d94c44109e 2978 #define EXTI_PR_PIF11 EXTI_PR_PR11
<> 148:21d94c44109e 2979 #define EXTI_PR_PIF12 EXTI_PR_PR12
<> 148:21d94c44109e 2980 #define EXTI_PR_PIF13 EXTI_PR_PR13
<> 148:21d94c44109e 2981 #define EXTI_PR_PIF14 EXTI_PR_PR14
<> 148:21d94c44109e 2982 #define EXTI_PR_PIF15 EXTI_PR_PR15
<> 148:21d94c44109e 2983 #define EXTI_PR_PIF16 EXTI_PR_PR16
<> 148:21d94c44109e 2984 #define EXTI_PR_PIF17 EXTI_PR_PR17
<> 148:21d94c44109e 2985 #define EXTI_PR_PIF18 EXTI_PR_PR18
<> 148:21d94c44109e 2986 #define EXTI_PR_PIF19 EXTI_PR_PR19
<> 148:21d94c44109e 2987 #define EXTI_PR_PIF20 EXTI_PR_PR20
<> 148:21d94c44109e 2988 #define EXTI_PR_PIF21 EXTI_PR_PR21
<> 148:21d94c44109e 2989 #define EXTI_PR_PIF22 EXTI_PR_PR22
<> 148:21d94c44109e 2990 #define EXTI_PR_PIF23 EXTI_PR_PR23
<> 148:21d94c44109e 2991
<> 148:21d94c44109e 2992 /******************************************************************************/
<> 148:21d94c44109e 2993 /* */
<> 148:21d94c44109e 2994 /* FLASH, DATA EEPROM and Option Bytes Registers */
<> 148:21d94c44109e 2995 /* (FLASH, DATA_EEPROM, OB) */
<> 148:21d94c44109e 2996 /* */
<> 148:21d94c44109e 2997 /******************************************************************************/
<> 148:21d94c44109e 2998
<> 148:21d94c44109e 2999 /******************* Bit definition for FLASH_ACR register ******************/
<> 148:21d94c44109e 3000 #define FLASH_ACR_LATENCY_Pos (0U)
<> 148:21d94c44109e 3001 #define FLASH_ACR_LATENCY_Msk (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 3002 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */
<> 148:21d94c44109e 3003 #define FLASH_ACR_PRFTEN_Pos (1U)
<> 148:21d94c44109e 3004 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 3005 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */
<> 148:21d94c44109e 3006 #define FLASH_ACR_ACC64_Pos (2U)
<> 148:21d94c44109e 3007 #define FLASH_ACR_ACC64_Msk (0x1U << FLASH_ACR_ACC64_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 3008 #define FLASH_ACR_ACC64 FLASH_ACR_ACC64_Msk /*!< Access 64 bits */
<> 148:21d94c44109e 3009 #define FLASH_ACR_SLEEP_PD_Pos (3U)
<> 148:21d94c44109e 3010 #define FLASH_ACR_SLEEP_PD_Msk (0x1U << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 3011 #define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */
<> 148:21d94c44109e 3012 #define FLASH_ACR_RUN_PD_Pos (4U)
<> 148:21d94c44109e 3013 #define FLASH_ACR_RUN_PD_Msk (0x1U << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 3014 #define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */
<> 148:21d94c44109e 3015
<> 148:21d94c44109e 3016 /******************* Bit definition for FLASH_PECR register ******************/
<> 148:21d94c44109e 3017 #define FLASH_PECR_PELOCK_Pos (0U)
<> 148:21d94c44109e 3018 #define FLASH_PECR_PELOCK_Msk (0x1U << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 3019 #define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */
<> 148:21d94c44109e 3020 #define FLASH_PECR_PRGLOCK_Pos (1U)
<> 148:21d94c44109e 3021 #define FLASH_PECR_PRGLOCK_Msk (0x1U << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 3022 #define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */
<> 148:21d94c44109e 3023 #define FLASH_PECR_OPTLOCK_Pos (2U)
<> 148:21d94c44109e 3024 #define FLASH_PECR_OPTLOCK_Msk (0x1U << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 3025 #define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */
<> 148:21d94c44109e 3026 #define FLASH_PECR_PROG_Pos (3U)
<> 148:21d94c44109e 3027 #define FLASH_PECR_PROG_Msk (0x1U << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 3028 #define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */
<> 148:21d94c44109e 3029 #define FLASH_PECR_DATA_Pos (4U)
<> 148:21d94c44109e 3030 #define FLASH_PECR_DATA_Msk (0x1U << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 3031 #define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */
<> 148:21d94c44109e 3032 #define FLASH_PECR_FTDW_Pos (8U)
<> 148:21d94c44109e 3033 #define FLASH_PECR_FTDW_Msk (0x1U << FLASH_PECR_FTDW_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 3034 #define FLASH_PECR_FTDW FLASH_PECR_FTDW_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */
<> 148:21d94c44109e 3035 #define FLASH_PECR_ERASE_Pos (9U)
<> 148:21d94c44109e 3036 #define FLASH_PECR_ERASE_Msk (0x1U << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 3037 #define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */
<> 148:21d94c44109e 3038 #define FLASH_PECR_FPRG_Pos (10U)
<> 148:21d94c44109e 3039 #define FLASH_PECR_FPRG_Msk (0x1U << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 3040 #define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */
<> 148:21d94c44109e 3041 #define FLASH_PECR_EOPIE_Pos (16U)
<> 148:21d94c44109e 3042 #define FLASH_PECR_EOPIE_Msk (0x1U << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 3043 #define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */
<> 148:21d94c44109e 3044 #define FLASH_PECR_ERRIE_Pos (17U)
<> 148:21d94c44109e 3045 #define FLASH_PECR_ERRIE_Msk (0x1U << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 3046 #define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */
<> 148:21d94c44109e 3047 #define FLASH_PECR_OBL_LAUNCH_Pos (18U)
<> 148:21d94c44109e 3048 #define FLASH_PECR_OBL_LAUNCH_Msk (0x1U << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 3049 #define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */
<> 148:21d94c44109e 3050
<> 148:21d94c44109e 3051 /****************** Bit definition for FLASH_PDKEYR register ******************/
<> 148:21d94c44109e 3052 #define FLASH_PDKEYR_PDKEYR_Pos (0U)
<> 148:21d94c44109e 3053 #define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFU << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 3054 #define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */
<> 148:21d94c44109e 3055
<> 148:21d94c44109e 3056 /****************** Bit definition for FLASH_PEKEYR register ******************/
<> 148:21d94c44109e 3057 #define FLASH_PEKEYR_PEKEYR_Pos (0U)
<> 148:21d94c44109e 3058 #define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFU << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 3059 #define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */
<> 148:21d94c44109e 3060
<> 148:21d94c44109e 3061 /****************** Bit definition for FLASH_PRGKEYR register ******************/
<> 148:21d94c44109e 3062 #define FLASH_PRGKEYR_PRGKEYR_Pos (0U)
<> 148:21d94c44109e 3063 #define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFU << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 3064 #define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */
<> 148:21d94c44109e 3065
<> 148:21d94c44109e 3066 /****************** Bit definition for FLASH_OPTKEYR register ******************/
<> 148:21d94c44109e 3067 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
<> 148:21d94c44109e 3068 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 3069 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */
<> 148:21d94c44109e 3070
<> 148:21d94c44109e 3071 /****************** Bit definition for FLASH_SR register *******************/
<> 148:21d94c44109e 3072 #define FLASH_SR_BSY_Pos (0U)
<> 148:21d94c44109e 3073 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 3074 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
<> 148:21d94c44109e 3075 #define FLASH_SR_EOP_Pos (1U)
<> 148:21d94c44109e 3076 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 3077 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/
<> 148:21d94c44109e 3078 #define FLASH_SR_ENDHV_Pos (2U)
<> 148:21d94c44109e 3079 #define FLASH_SR_ENDHV_Msk (0x1U << FLASH_SR_ENDHV_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 3080 #define FLASH_SR_ENDHV FLASH_SR_ENDHV_Msk /*!< End of high voltage */
<> 148:21d94c44109e 3081 #define FLASH_SR_READY_Pos (3U)
<> 148:21d94c44109e 3082 #define FLASH_SR_READY_Msk (0x1U << FLASH_SR_READY_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 3083 #define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */
<> 148:21d94c44109e 3084
<> 148:21d94c44109e 3085 #define FLASH_SR_WRPERR_Pos (8U)
<> 148:21d94c44109e 3086 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 3087 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protected error */
<> 148:21d94c44109e 3088 #define FLASH_SR_PGAERR_Pos (9U)
<> 148:21d94c44109e 3089 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 3090 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */
<> 148:21d94c44109e 3091 #define FLASH_SR_SIZERR_Pos (10U)
<> 148:21d94c44109e 3092 #define FLASH_SR_SIZERR_Msk (0x1U << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 3093 #define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */
<> 148:21d94c44109e 3094 #define FLASH_SR_OPTVERR_Pos (11U)
<> 148:21d94c44109e 3095 #define FLASH_SR_OPTVERR_Msk (0x1U << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 3096 #define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option validity error */
<> 148:21d94c44109e 3097 #define FLASH_SR_OPTVERRUSR_Pos (12U)
<> 148:21d94c44109e 3098 #define FLASH_SR_OPTVERRUSR_Msk (0x1U << FLASH_SR_OPTVERRUSR_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 3099 #define FLASH_SR_OPTVERRUSR FLASH_SR_OPTVERRUSR_Msk /*!< Option User validity error */
<> 148:21d94c44109e 3100 #define FLASH_SR_RDERR_Pos (13U)
<> 148:21d94c44109e 3101 #define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 3102 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */
<> 148:21d94c44109e 3103
<> 148:21d94c44109e 3104 /****************** Bit definition for FLASH_OBR register *******************/
<> 148:21d94c44109e 3105 #define FLASH_OBR_RDPRT_Pos (0U)
<> 148:21d94c44109e 3106 #define FLASH_OBR_RDPRT_Msk (0xFFU << FLASH_OBR_RDPRT_Pos) /*!< 0x000000FF */
<> 148:21d94c44109e 3107 #define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read Protection */
<> 148:21d94c44109e 3108 #define FLASH_OBR_SPRMOD_Pos (8U)
<> 148:21d94c44109e 3109 #define FLASH_OBR_SPRMOD_Msk (0x1U << FLASH_OBR_SPRMOD_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 3110 #define FLASH_OBR_SPRMOD FLASH_OBR_SPRMOD_Msk /*!< Selection of protection mode of WPRi bits */
<> 148:21d94c44109e 3111 #define FLASH_OBR_BOR_LEV_Pos (16U)
<> 148:21d94c44109e 3112 #define FLASH_OBR_BOR_LEV_Msk (0xFU << FLASH_OBR_BOR_LEV_Pos) /*!< 0x000F0000 */
<> 148:21d94c44109e 3113 #define FLASH_OBR_BOR_LEV FLASH_OBR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
<> 148:21d94c44109e 3114 #define FLASH_OBR_USER_Pos (20U)
<> 148:21d94c44109e 3115 #define FLASH_OBR_USER_Msk (0x7U << FLASH_OBR_USER_Pos) /*!< 0x00700000 */
<> 148:21d94c44109e 3116 #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */
<> 148:21d94c44109e 3117 #define FLASH_OBR_IWDG_SW_Pos (20U)
<> 148:21d94c44109e 3118 #define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 3119 #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG_SW */
<> 148:21d94c44109e 3120 #define FLASH_OBR_nRST_STOP_Pos (21U)
<> 148:21d94c44109e 3121 #define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 3122 #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */
<> 148:21d94c44109e 3123 #define FLASH_OBR_nRST_STDBY_Pos (22U)
<> 148:21d94c44109e 3124 #define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 3125 #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */
<> 148:21d94c44109e 3126
<> 148:21d94c44109e 3127 /****************** Bit definition for FLASH_WRPR register ******************/
<> 148:21d94c44109e 3128 #define FLASH_WRPR1_WRP_Pos (0U)
<> 148:21d94c44109e 3129 #define FLASH_WRPR1_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR1_WRP_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 3130 #define FLASH_WRPR1_WRP FLASH_WRPR1_WRP_Msk /*!< Write Protect sectors 0 to 31 */
<> 148:21d94c44109e 3131 #define FLASH_WRPR2_WRP_Pos (0U)
<> 148:21d94c44109e 3132 #define FLASH_WRPR2_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR2_WRP_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 3133 #define FLASH_WRPR2_WRP FLASH_WRPR2_WRP_Msk /*!< Write Protect sectors 32 to 63 */
<> 148:21d94c44109e 3134
<> 148:21d94c44109e 3135 /******************************************************************************/
<> 148:21d94c44109e 3136 /* */
<> 148:21d94c44109e 3137 /* General Purpose I/O */
<> 148:21d94c44109e 3138 /* */
<> 148:21d94c44109e 3139 /******************************************************************************/
<> 148:21d94c44109e 3140 /****************** Bits definition for GPIO_MODER register *****************/
<> 148:21d94c44109e 3141 #define GPIO_MODER_MODER0_Pos (0U)
<> 148:21d94c44109e 3142 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
<> 148:21d94c44109e 3143 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
<> 148:21d94c44109e 3144 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 3145 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 3146
<> 148:21d94c44109e 3147 #define GPIO_MODER_MODER1_Pos (2U)
<> 148:21d94c44109e 3148 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
<> 148:21d94c44109e 3149 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
<> 148:21d94c44109e 3150 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 3151 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 3152
<> 148:21d94c44109e 3153 #define GPIO_MODER_MODER2_Pos (4U)
<> 148:21d94c44109e 3154 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
<> 148:21d94c44109e 3155 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
<> 148:21d94c44109e 3156 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 3157 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 3158
<> 148:21d94c44109e 3159 #define GPIO_MODER_MODER3_Pos (6U)
<> 148:21d94c44109e 3160 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
<> 148:21d94c44109e 3161 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
<> 148:21d94c44109e 3162 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 3163 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 3164
<> 148:21d94c44109e 3165 #define GPIO_MODER_MODER4_Pos (8U)
<> 148:21d94c44109e 3166 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
<> 148:21d94c44109e 3167 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
<> 148:21d94c44109e 3168 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 3169 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 3170
<> 148:21d94c44109e 3171 #define GPIO_MODER_MODER5_Pos (10U)
<> 148:21d94c44109e 3172 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
<> 148:21d94c44109e 3173 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
<> 148:21d94c44109e 3174 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 3175 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 3176
<> 148:21d94c44109e 3177 #define GPIO_MODER_MODER6_Pos (12U)
<> 148:21d94c44109e 3178 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
<> 148:21d94c44109e 3179 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
<> 148:21d94c44109e 3180 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 3181 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 3182
<> 148:21d94c44109e 3183 #define GPIO_MODER_MODER7_Pos (14U)
<> 148:21d94c44109e 3184 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
<> 148:21d94c44109e 3185 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
<> 148:21d94c44109e 3186 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 3187 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 3188
<> 148:21d94c44109e 3189 #define GPIO_MODER_MODER8_Pos (16U)
<> 148:21d94c44109e 3190 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
<> 148:21d94c44109e 3191 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
<> 148:21d94c44109e 3192 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 3193 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 3194
<> 148:21d94c44109e 3195 #define GPIO_MODER_MODER9_Pos (18U)
<> 148:21d94c44109e 3196 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
<> 148:21d94c44109e 3197 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
<> 148:21d94c44109e 3198 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 3199 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 3200
<> 148:21d94c44109e 3201 #define GPIO_MODER_MODER10_Pos (20U)
<> 148:21d94c44109e 3202 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
<> 148:21d94c44109e 3203 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
<> 148:21d94c44109e 3204 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 3205 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 3206
<> 148:21d94c44109e 3207 #define GPIO_MODER_MODER11_Pos (22U)
<> 148:21d94c44109e 3208 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
<> 148:21d94c44109e 3209 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
<> 148:21d94c44109e 3210 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 3211 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 3212
<> 148:21d94c44109e 3213 #define GPIO_MODER_MODER12_Pos (24U)
<> 148:21d94c44109e 3214 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
<> 148:21d94c44109e 3215 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
<> 148:21d94c44109e 3216 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
<> 148:21d94c44109e 3217 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
<> 148:21d94c44109e 3218
<> 148:21d94c44109e 3219 #define GPIO_MODER_MODER13_Pos (26U)
<> 148:21d94c44109e 3220 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
<> 148:21d94c44109e 3221 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
<> 148:21d94c44109e 3222 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
<> 148:21d94c44109e 3223 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
<> 148:21d94c44109e 3224
<> 148:21d94c44109e 3225 #define GPIO_MODER_MODER14_Pos (28U)
<> 148:21d94c44109e 3226 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
<> 148:21d94c44109e 3227 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
<> 148:21d94c44109e 3228 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
<> 148:21d94c44109e 3229 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
<> 148:21d94c44109e 3230
<> 148:21d94c44109e 3231 #define GPIO_MODER_MODER15_Pos (30U)
<> 148:21d94c44109e 3232 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
<> 148:21d94c44109e 3233 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
<> 148:21d94c44109e 3234 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
<> 148:21d94c44109e 3235 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
<> 148:21d94c44109e 3236
<> 148:21d94c44109e 3237 /****************** Bits definition for GPIO_OTYPER register ****************/
<> 148:21d94c44109e 3238 #define GPIO_OTYPER_OT_0 (0x00000001U)
<> 148:21d94c44109e 3239 #define GPIO_OTYPER_OT_1 (0x00000002U)
<> 148:21d94c44109e 3240 #define GPIO_OTYPER_OT_2 (0x00000004U)
<> 148:21d94c44109e 3241 #define GPIO_OTYPER_OT_3 (0x00000008U)
<> 148:21d94c44109e 3242 #define GPIO_OTYPER_OT_4 (0x00000010U)
<> 148:21d94c44109e 3243 #define GPIO_OTYPER_OT_5 (0x00000020U)
<> 148:21d94c44109e 3244 #define GPIO_OTYPER_OT_6 (0x00000040U)
<> 148:21d94c44109e 3245 #define GPIO_OTYPER_OT_7 (0x00000080U)
<> 148:21d94c44109e 3246 #define GPIO_OTYPER_OT_8 (0x00000100U)
<> 148:21d94c44109e 3247 #define GPIO_OTYPER_OT_9 (0x00000200U)
<> 148:21d94c44109e 3248 #define GPIO_OTYPER_OT_10 (0x00000400U)
<> 148:21d94c44109e 3249 #define GPIO_OTYPER_OT_11 (0x00000800U)
<> 148:21d94c44109e 3250 #define GPIO_OTYPER_OT_12 (0x00001000U)
<> 148:21d94c44109e 3251 #define GPIO_OTYPER_OT_13 (0x00002000U)
<> 148:21d94c44109e 3252 #define GPIO_OTYPER_OT_14 (0x00004000U)
<> 148:21d94c44109e 3253 #define GPIO_OTYPER_OT_15 (0x00008000U)
<> 148:21d94c44109e 3254
<> 148:21d94c44109e 3255 /****************** Bits definition for GPIO_OSPEEDR register ***************/
<> 148:21d94c44109e 3256 #define GPIO_OSPEEDER_OSPEEDR0_Pos (0U)
<> 148:21d94c44109e 3257 #define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
<> 148:21d94c44109e 3258 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk
<> 148:21d94c44109e 3259 #define GPIO_OSPEEDER_OSPEEDR0_0 (0x1U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 3260 #define GPIO_OSPEEDER_OSPEEDR0_1 (0x2U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 3261
<> 148:21d94c44109e 3262 #define GPIO_OSPEEDER_OSPEEDR1_Pos (2U)
<> 148:21d94c44109e 3263 #define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
<> 148:21d94c44109e 3264 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk
<> 148:21d94c44109e 3265 #define GPIO_OSPEEDER_OSPEEDR1_0 (0x1U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 3266 #define GPIO_OSPEEDER_OSPEEDR1_1 (0x2U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 3267
<> 148:21d94c44109e 3268 #define GPIO_OSPEEDER_OSPEEDR2_Pos (4U)
<> 148:21d94c44109e 3269 #define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
<> 148:21d94c44109e 3270 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk
<> 148:21d94c44109e 3271 #define GPIO_OSPEEDER_OSPEEDR2_0 (0x1U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 3272 #define GPIO_OSPEEDER_OSPEEDR2_1 (0x2U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 3273
<> 148:21d94c44109e 3274 #define GPIO_OSPEEDER_OSPEEDR3_Pos (6U)
<> 148:21d94c44109e 3275 #define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
<> 148:21d94c44109e 3276 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk
<> 148:21d94c44109e 3277 #define GPIO_OSPEEDER_OSPEEDR3_0 (0x1U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 3278 #define GPIO_OSPEEDER_OSPEEDR3_1 (0x2U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 3279
<> 148:21d94c44109e 3280 #define GPIO_OSPEEDER_OSPEEDR4_Pos (8U)
<> 148:21d94c44109e 3281 #define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
<> 148:21d94c44109e 3282 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk
<> 148:21d94c44109e 3283 #define GPIO_OSPEEDER_OSPEEDR4_0 (0x1U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 3284 #define GPIO_OSPEEDER_OSPEEDR4_1 (0x2U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 3285
<> 148:21d94c44109e 3286 #define GPIO_OSPEEDER_OSPEEDR5_Pos (10U)
<> 148:21d94c44109e 3287 #define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
<> 148:21d94c44109e 3288 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk
<> 148:21d94c44109e 3289 #define GPIO_OSPEEDER_OSPEEDR5_0 (0x1U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 3290 #define GPIO_OSPEEDER_OSPEEDR5_1 (0x2U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 3291
<> 148:21d94c44109e 3292 #define GPIO_OSPEEDER_OSPEEDR6_Pos (12U)
<> 148:21d94c44109e 3293 #define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
<> 148:21d94c44109e 3294 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk
<> 148:21d94c44109e 3295 #define GPIO_OSPEEDER_OSPEEDR6_0 (0x1U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 3296 #define GPIO_OSPEEDER_OSPEEDR6_1 (0x2U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 3297
<> 148:21d94c44109e 3298 #define GPIO_OSPEEDER_OSPEEDR7_Pos (14U)
<> 148:21d94c44109e 3299 #define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
<> 148:21d94c44109e 3300 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk
<> 148:21d94c44109e 3301 #define GPIO_OSPEEDER_OSPEEDR7_0 (0x1U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 3302 #define GPIO_OSPEEDER_OSPEEDR7_1 (0x2U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 3303
<> 148:21d94c44109e 3304 #define GPIO_OSPEEDER_OSPEEDR8_Pos (16U)
<> 148:21d94c44109e 3305 #define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
<> 148:21d94c44109e 3306 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk
<> 148:21d94c44109e 3307 #define GPIO_OSPEEDER_OSPEEDR8_0 (0x1U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 3308 #define GPIO_OSPEEDER_OSPEEDR8_1 (0x2U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 3309
<> 148:21d94c44109e 3310 #define GPIO_OSPEEDER_OSPEEDR9_Pos (18U)
<> 148:21d94c44109e 3311 #define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
<> 148:21d94c44109e 3312 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk
<> 148:21d94c44109e 3313 #define GPIO_OSPEEDER_OSPEEDR9_0 (0x1U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 3314 #define GPIO_OSPEEDER_OSPEEDR9_1 (0x2U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 3315
<> 148:21d94c44109e 3316 #define GPIO_OSPEEDER_OSPEEDR10_Pos (20U)
<> 148:21d94c44109e 3317 #define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
<> 148:21d94c44109e 3318 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk
<> 148:21d94c44109e 3319 #define GPIO_OSPEEDER_OSPEEDR10_0 (0x1U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 3320 #define GPIO_OSPEEDER_OSPEEDR10_1 (0x2U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 3321
<> 148:21d94c44109e 3322 #define GPIO_OSPEEDER_OSPEEDR11_Pos (22U)
<> 148:21d94c44109e 3323 #define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
<> 148:21d94c44109e 3324 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk
<> 148:21d94c44109e 3325 #define GPIO_OSPEEDER_OSPEEDR11_0 (0x1U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 3326 #define GPIO_OSPEEDER_OSPEEDR11_1 (0x2U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 3327
<> 148:21d94c44109e 3328 #define GPIO_OSPEEDER_OSPEEDR12_Pos (24U)
<> 148:21d94c44109e 3329 #define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
<> 148:21d94c44109e 3330 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk
<> 148:21d94c44109e 3331 #define GPIO_OSPEEDER_OSPEEDR12_0 (0x1U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
<> 148:21d94c44109e 3332 #define GPIO_OSPEEDER_OSPEEDR12_1 (0x2U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
<> 148:21d94c44109e 3333
<> 148:21d94c44109e 3334 #define GPIO_OSPEEDER_OSPEEDR13_Pos (26U)
<> 148:21d94c44109e 3335 #define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
<> 148:21d94c44109e 3336 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk
<> 148:21d94c44109e 3337 #define GPIO_OSPEEDER_OSPEEDR13_0 (0x1U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
<> 148:21d94c44109e 3338 #define GPIO_OSPEEDER_OSPEEDR13_1 (0x2U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
<> 148:21d94c44109e 3339
<> 148:21d94c44109e 3340 #define GPIO_OSPEEDER_OSPEEDR14_Pos (28U)
<> 148:21d94c44109e 3341 #define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
<> 148:21d94c44109e 3342 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk
<> 148:21d94c44109e 3343 #define GPIO_OSPEEDER_OSPEEDR14_0 (0x1U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
<> 148:21d94c44109e 3344 #define GPIO_OSPEEDER_OSPEEDR14_1 (0x2U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
<> 148:21d94c44109e 3345
<> 148:21d94c44109e 3346 #define GPIO_OSPEEDER_OSPEEDR15_Pos (30U)
<> 148:21d94c44109e 3347 #define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
<> 148:21d94c44109e 3348 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk
<> 148:21d94c44109e 3349 #define GPIO_OSPEEDER_OSPEEDR15_0 (0x1U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
<> 148:21d94c44109e 3350 #define GPIO_OSPEEDER_OSPEEDR15_1 (0x2U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
<> 148:21d94c44109e 3351
<> 148:21d94c44109e 3352 /****************** Bits definition for GPIO_PUPDR register *****************/
<> 148:21d94c44109e 3353 #define GPIO_PUPDR_PUPDR0_Pos (0U)
<> 148:21d94c44109e 3354 #define GPIO_PUPDR_PUPDR0_Msk (0x3U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */
<> 148:21d94c44109e 3355 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk
<> 148:21d94c44109e 3356 #define GPIO_PUPDR_PUPDR0_0 (0x1U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 3357 #define GPIO_PUPDR_PUPDR0_1 (0x2U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 3358
<> 148:21d94c44109e 3359 #define GPIO_PUPDR_PUPDR1_Pos (2U)
<> 148:21d94c44109e 3360 #define GPIO_PUPDR_PUPDR1_Msk (0x3U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */
<> 148:21d94c44109e 3361 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk
<> 148:21d94c44109e 3362 #define GPIO_PUPDR_PUPDR1_0 (0x1U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 3363 #define GPIO_PUPDR_PUPDR1_1 (0x2U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 3364
<> 148:21d94c44109e 3365 #define GPIO_PUPDR_PUPDR2_Pos (4U)
<> 148:21d94c44109e 3366 #define GPIO_PUPDR_PUPDR2_Msk (0x3U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */
<> 148:21d94c44109e 3367 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk
<> 148:21d94c44109e 3368 #define GPIO_PUPDR_PUPDR2_0 (0x1U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 3369 #define GPIO_PUPDR_PUPDR2_1 (0x2U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 3370
<> 148:21d94c44109e 3371 #define GPIO_PUPDR_PUPDR3_Pos (6U)
<> 148:21d94c44109e 3372 #define GPIO_PUPDR_PUPDR3_Msk (0x3U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */
<> 148:21d94c44109e 3373 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk
<> 148:21d94c44109e 3374 #define GPIO_PUPDR_PUPDR3_0 (0x1U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 3375 #define GPIO_PUPDR_PUPDR3_1 (0x2U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 3376
<> 148:21d94c44109e 3377 #define GPIO_PUPDR_PUPDR4_Pos (8U)
<> 148:21d94c44109e 3378 #define GPIO_PUPDR_PUPDR4_Msk (0x3U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */
<> 148:21d94c44109e 3379 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk
<> 148:21d94c44109e 3380 #define GPIO_PUPDR_PUPDR4_0 (0x1U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 3381 #define GPIO_PUPDR_PUPDR4_1 (0x2U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 3382
<> 148:21d94c44109e 3383 #define GPIO_PUPDR_PUPDR5_Pos (10U)
<> 148:21d94c44109e 3384 #define GPIO_PUPDR_PUPDR5_Msk (0x3U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */
<> 148:21d94c44109e 3385 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk
<> 148:21d94c44109e 3386 #define GPIO_PUPDR_PUPDR5_0 (0x1U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 3387 #define GPIO_PUPDR_PUPDR5_1 (0x2U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 3388
<> 148:21d94c44109e 3389 #define GPIO_PUPDR_PUPDR6_Pos (12U)
<> 148:21d94c44109e 3390 #define GPIO_PUPDR_PUPDR6_Msk (0x3U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */
<> 148:21d94c44109e 3391 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk
<> 148:21d94c44109e 3392 #define GPIO_PUPDR_PUPDR6_0 (0x1U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 3393 #define GPIO_PUPDR_PUPDR6_1 (0x2U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 3394
<> 148:21d94c44109e 3395 #define GPIO_PUPDR_PUPDR7_Pos (14U)
<> 148:21d94c44109e 3396 #define GPIO_PUPDR_PUPDR7_Msk (0x3U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */
<> 148:21d94c44109e 3397 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk
<> 148:21d94c44109e 3398 #define GPIO_PUPDR_PUPDR7_0 (0x1U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 3399 #define GPIO_PUPDR_PUPDR7_1 (0x2U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 3400
<> 148:21d94c44109e 3401 #define GPIO_PUPDR_PUPDR8_Pos (16U)
<> 148:21d94c44109e 3402 #define GPIO_PUPDR_PUPDR8_Msk (0x3U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */
<> 148:21d94c44109e 3403 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk
<> 148:21d94c44109e 3404 #define GPIO_PUPDR_PUPDR8_0 (0x1U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 3405 #define GPIO_PUPDR_PUPDR8_1 (0x2U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 3406
<> 148:21d94c44109e 3407 #define GPIO_PUPDR_PUPDR9_Pos (18U)
<> 148:21d94c44109e 3408 #define GPIO_PUPDR_PUPDR9_Msk (0x3U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */
<> 148:21d94c44109e 3409 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk
<> 148:21d94c44109e 3410 #define GPIO_PUPDR_PUPDR9_0 (0x1U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 3411 #define GPIO_PUPDR_PUPDR9_1 (0x2U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 3412
<> 148:21d94c44109e 3413 #define GPIO_PUPDR_PUPDR10_Pos (20U)
<> 148:21d94c44109e 3414 #define GPIO_PUPDR_PUPDR10_Msk (0x3U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */
<> 148:21d94c44109e 3415 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk
<> 148:21d94c44109e 3416 #define GPIO_PUPDR_PUPDR10_0 (0x1U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 3417 #define GPIO_PUPDR_PUPDR10_1 (0x2U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 3418
<> 148:21d94c44109e 3419 #define GPIO_PUPDR_PUPDR11_Pos (22U)
<> 148:21d94c44109e 3420 #define GPIO_PUPDR_PUPDR11_Msk (0x3U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */
<> 148:21d94c44109e 3421 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk
<> 148:21d94c44109e 3422 #define GPIO_PUPDR_PUPDR11_0 (0x1U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 3423 #define GPIO_PUPDR_PUPDR11_1 (0x2U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 3424
<> 148:21d94c44109e 3425 #define GPIO_PUPDR_PUPDR12_Pos (24U)
<> 148:21d94c44109e 3426 #define GPIO_PUPDR_PUPDR12_Msk (0x3U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */
<> 148:21d94c44109e 3427 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk
<> 148:21d94c44109e 3428 #define GPIO_PUPDR_PUPDR12_0 (0x1U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */
<> 148:21d94c44109e 3429 #define GPIO_PUPDR_PUPDR12_1 (0x2U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */
<> 148:21d94c44109e 3430
<> 148:21d94c44109e 3431 #define GPIO_PUPDR_PUPDR13_Pos (26U)
<> 148:21d94c44109e 3432 #define GPIO_PUPDR_PUPDR13_Msk (0x3U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */
<> 148:21d94c44109e 3433 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk
<> 148:21d94c44109e 3434 #define GPIO_PUPDR_PUPDR13_0 (0x1U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */
<> 148:21d94c44109e 3435 #define GPIO_PUPDR_PUPDR13_1 (0x2U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */
<> 148:21d94c44109e 3436
<> 148:21d94c44109e 3437 #define GPIO_PUPDR_PUPDR14_Pos (28U)
<> 148:21d94c44109e 3438 #define GPIO_PUPDR_PUPDR14_Msk (0x3U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */
<> 148:21d94c44109e 3439 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk
<> 148:21d94c44109e 3440 #define GPIO_PUPDR_PUPDR14_0 (0x1U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */
<> 148:21d94c44109e 3441 #define GPIO_PUPDR_PUPDR14_1 (0x2U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */
<> 148:21d94c44109e 3442 #define GPIO_PUPDR_PUPDR15_Pos (30U)
<> 148:21d94c44109e 3443 #define GPIO_PUPDR_PUPDR15_Msk (0x3U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */
<> 148:21d94c44109e 3444 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk
<> 148:21d94c44109e 3445 #define GPIO_PUPDR_PUPDR15_0 (0x1U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */
<> 148:21d94c44109e 3446 #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */
<> 148:21d94c44109e 3447
<> 148:21d94c44109e 3448 /****************** Bits definition for GPIO_IDR register *******************/
<> 148:21d94c44109e 3449 #define GPIO_IDR_IDR_0 (0x00000001U)
<> 148:21d94c44109e 3450 #define GPIO_IDR_IDR_1 (0x00000002U)
<> 148:21d94c44109e 3451 #define GPIO_IDR_IDR_2 (0x00000004U)
<> 148:21d94c44109e 3452 #define GPIO_IDR_IDR_3 (0x00000008U)
<> 148:21d94c44109e 3453 #define GPIO_IDR_IDR_4 (0x00000010U)
<> 148:21d94c44109e 3454 #define GPIO_IDR_IDR_5 (0x00000020U)
<> 148:21d94c44109e 3455 #define GPIO_IDR_IDR_6 (0x00000040U)
<> 148:21d94c44109e 3456 #define GPIO_IDR_IDR_7 (0x00000080U)
<> 148:21d94c44109e 3457 #define GPIO_IDR_IDR_8 (0x00000100U)
<> 148:21d94c44109e 3458 #define GPIO_IDR_IDR_9 (0x00000200U)
<> 148:21d94c44109e 3459 #define GPIO_IDR_IDR_10 (0x00000400U)
<> 148:21d94c44109e 3460 #define GPIO_IDR_IDR_11 (0x00000800U)
<> 148:21d94c44109e 3461 #define GPIO_IDR_IDR_12 (0x00001000U)
<> 148:21d94c44109e 3462 #define GPIO_IDR_IDR_13 (0x00002000U)
<> 148:21d94c44109e 3463 #define GPIO_IDR_IDR_14 (0x00004000U)
<> 148:21d94c44109e 3464 #define GPIO_IDR_IDR_15 (0x00008000U)
<> 148:21d94c44109e 3465
<> 148:21d94c44109e 3466 /****************** Bits definition for GPIO_ODR register *******************/
<> 148:21d94c44109e 3467 #define GPIO_ODR_ODR_0 (0x00000001U)
<> 148:21d94c44109e 3468 #define GPIO_ODR_ODR_1 (0x00000002U)
<> 148:21d94c44109e 3469 #define GPIO_ODR_ODR_2 (0x00000004U)
<> 148:21d94c44109e 3470 #define GPIO_ODR_ODR_3 (0x00000008U)
<> 148:21d94c44109e 3471 #define GPIO_ODR_ODR_4 (0x00000010U)
<> 148:21d94c44109e 3472 #define GPIO_ODR_ODR_5 (0x00000020U)
<> 148:21d94c44109e 3473 #define GPIO_ODR_ODR_6 (0x00000040U)
<> 148:21d94c44109e 3474 #define GPIO_ODR_ODR_7 (0x00000080U)
<> 148:21d94c44109e 3475 #define GPIO_ODR_ODR_8 (0x00000100U)
<> 148:21d94c44109e 3476 #define GPIO_ODR_ODR_9 (0x00000200U)
<> 148:21d94c44109e 3477 #define GPIO_ODR_ODR_10 (0x00000400U)
<> 148:21d94c44109e 3478 #define GPIO_ODR_ODR_11 (0x00000800U)
<> 148:21d94c44109e 3479 #define GPIO_ODR_ODR_12 (0x00001000U)
<> 148:21d94c44109e 3480 #define GPIO_ODR_ODR_13 (0x00002000U)
<> 148:21d94c44109e 3481 #define GPIO_ODR_ODR_14 (0x00004000U)
<> 148:21d94c44109e 3482 #define GPIO_ODR_ODR_15 (0x00008000U)
<> 148:21d94c44109e 3483
<> 148:21d94c44109e 3484 /****************** Bits definition for GPIO_BSRR register ******************/
<> 148:21d94c44109e 3485 #define GPIO_BSRR_BS_0 (0x00000001U)
<> 148:21d94c44109e 3486 #define GPIO_BSRR_BS_1 (0x00000002U)
<> 148:21d94c44109e 3487 #define GPIO_BSRR_BS_2 (0x00000004U)
<> 148:21d94c44109e 3488 #define GPIO_BSRR_BS_3 (0x00000008U)
<> 148:21d94c44109e 3489 #define GPIO_BSRR_BS_4 (0x00000010U)
<> 148:21d94c44109e 3490 #define GPIO_BSRR_BS_5 (0x00000020U)
<> 148:21d94c44109e 3491 #define GPIO_BSRR_BS_6 (0x00000040U)
<> 148:21d94c44109e 3492 #define GPIO_BSRR_BS_7 (0x00000080U)
<> 148:21d94c44109e 3493 #define GPIO_BSRR_BS_8 (0x00000100U)
<> 148:21d94c44109e 3494 #define GPIO_BSRR_BS_9 (0x00000200U)
<> 148:21d94c44109e 3495 #define GPIO_BSRR_BS_10 (0x00000400U)
<> 148:21d94c44109e 3496 #define GPIO_BSRR_BS_11 (0x00000800U)
<> 148:21d94c44109e 3497 #define GPIO_BSRR_BS_12 (0x00001000U)
<> 148:21d94c44109e 3498 #define GPIO_BSRR_BS_13 (0x00002000U)
<> 148:21d94c44109e 3499 #define GPIO_BSRR_BS_14 (0x00004000U)
<> 148:21d94c44109e 3500 #define GPIO_BSRR_BS_15 (0x00008000U)
<> 148:21d94c44109e 3501 #define GPIO_BSRR_BR_0 (0x00010000U)
<> 148:21d94c44109e 3502 #define GPIO_BSRR_BR_1 (0x00020000U)
<> 148:21d94c44109e 3503 #define GPIO_BSRR_BR_2 (0x00040000U)
<> 148:21d94c44109e 3504 #define GPIO_BSRR_BR_3 (0x00080000U)
<> 148:21d94c44109e 3505 #define GPIO_BSRR_BR_4 (0x00100000U)
<> 148:21d94c44109e 3506 #define GPIO_BSRR_BR_5 (0x00200000U)
<> 148:21d94c44109e 3507 #define GPIO_BSRR_BR_6 (0x00400000U)
<> 148:21d94c44109e 3508 #define GPIO_BSRR_BR_7 (0x00800000U)
<> 148:21d94c44109e 3509 #define GPIO_BSRR_BR_8 (0x01000000U)
<> 148:21d94c44109e 3510 #define GPIO_BSRR_BR_9 (0x02000000U)
<> 148:21d94c44109e 3511 #define GPIO_BSRR_BR_10 (0x04000000U)
<> 148:21d94c44109e 3512 #define GPIO_BSRR_BR_11 (0x08000000U)
<> 148:21d94c44109e 3513 #define GPIO_BSRR_BR_12 (0x10000000U)
<> 148:21d94c44109e 3514 #define GPIO_BSRR_BR_13 (0x20000000U)
<> 148:21d94c44109e 3515 #define GPIO_BSRR_BR_14 (0x40000000U)
<> 148:21d94c44109e 3516 #define GPIO_BSRR_BR_15 (0x80000000U)
<> 148:21d94c44109e 3517
<> 148:21d94c44109e 3518 /****************** Bit definition for GPIO_LCKR register ********************/
<> 148:21d94c44109e 3519 #define GPIO_LCKR_LCK0_Pos (0U)
<> 148:21d94c44109e 3520 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 3521 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
<> 148:21d94c44109e 3522 #define GPIO_LCKR_LCK1_Pos (1U)
<> 148:21d94c44109e 3523 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 3524 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
<> 148:21d94c44109e 3525 #define GPIO_LCKR_LCK2_Pos (2U)
<> 148:21d94c44109e 3526 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 3527 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
<> 148:21d94c44109e 3528 #define GPIO_LCKR_LCK3_Pos (3U)
<> 148:21d94c44109e 3529 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 3530 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
<> 148:21d94c44109e 3531 #define GPIO_LCKR_LCK4_Pos (4U)
<> 148:21d94c44109e 3532 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 3533 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
<> 148:21d94c44109e 3534 #define GPIO_LCKR_LCK5_Pos (5U)
<> 148:21d94c44109e 3535 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 3536 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
<> 148:21d94c44109e 3537 #define GPIO_LCKR_LCK6_Pos (6U)
<> 148:21d94c44109e 3538 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 3539 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
<> 148:21d94c44109e 3540 #define GPIO_LCKR_LCK7_Pos (7U)
<> 148:21d94c44109e 3541 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 3542 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
<> 148:21d94c44109e 3543 #define GPIO_LCKR_LCK8_Pos (8U)
<> 148:21d94c44109e 3544 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 3545 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
<> 148:21d94c44109e 3546 #define GPIO_LCKR_LCK9_Pos (9U)
<> 148:21d94c44109e 3547 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 3548 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
<> 148:21d94c44109e 3549 #define GPIO_LCKR_LCK10_Pos (10U)
<> 148:21d94c44109e 3550 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 3551 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
<> 148:21d94c44109e 3552 #define GPIO_LCKR_LCK11_Pos (11U)
<> 148:21d94c44109e 3553 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 3554 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
<> 148:21d94c44109e 3555 #define GPIO_LCKR_LCK12_Pos (12U)
<> 148:21d94c44109e 3556 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 3557 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
<> 148:21d94c44109e 3558 #define GPIO_LCKR_LCK13_Pos (13U)
<> 148:21d94c44109e 3559 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 3560 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
<> 148:21d94c44109e 3561 #define GPIO_LCKR_LCK14_Pos (14U)
<> 148:21d94c44109e 3562 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 3563 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
<> 148:21d94c44109e 3564 #define GPIO_LCKR_LCK15_Pos (15U)
<> 148:21d94c44109e 3565 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 3566 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
<> 148:21d94c44109e 3567 #define GPIO_LCKR_LCKK_Pos (16U)
<> 148:21d94c44109e 3568 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 3569 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
<> 148:21d94c44109e 3570
<> 148:21d94c44109e 3571 /****************** Bit definition for GPIO_AFRL register ********************/
<> 148:21d94c44109e 3572 #define GPIO_AFRL_AFRL0_Pos (0U)
<> 148:21d94c44109e 3573 #define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */
<> 148:21d94c44109e 3574 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk
<> 148:21d94c44109e 3575 #define GPIO_AFRL_AFRL1_Pos (4U)
<> 148:21d94c44109e 3576 #define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */
<> 148:21d94c44109e 3577 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk
<> 148:21d94c44109e 3578 #define GPIO_AFRL_AFRL2_Pos (8U)
<> 148:21d94c44109e 3579 #define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */
<> 148:21d94c44109e 3580 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk
<> 148:21d94c44109e 3581 #define GPIO_AFRL_AFRL3_Pos (12U)
<> 148:21d94c44109e 3582 #define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */
<> 148:21d94c44109e 3583 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk
<> 148:21d94c44109e 3584 #define GPIO_AFRL_AFRL4_Pos (16U)
<> 148:21d94c44109e 3585 #define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */
<> 148:21d94c44109e 3586 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk
<> 148:21d94c44109e 3587 #define GPIO_AFRL_AFRL5_Pos (20U)
<> 148:21d94c44109e 3588 #define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */
<> 148:21d94c44109e 3589 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk
<> 148:21d94c44109e 3590 #define GPIO_AFRL_AFRL6_Pos (24U)
<> 148:21d94c44109e 3591 #define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */
<> 148:21d94c44109e 3592 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk
<> 148:21d94c44109e 3593 #define GPIO_AFRL_AFRL7_Pos (28U)
<> 148:21d94c44109e 3594 #define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */
<> 148:21d94c44109e 3595 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk
<> 148:21d94c44109e 3596
<> 148:21d94c44109e 3597 /****************** Bit definition for GPIO_AFRH register ********************/
<> 148:21d94c44109e 3598 #define GPIO_AFRH_AFRH0_Pos (0U)
<> 148:21d94c44109e 3599 #define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */
<> 148:21d94c44109e 3600 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk
<> 148:21d94c44109e 3601 #define GPIO_AFRH_AFRH1_Pos (4U)
<> 148:21d94c44109e 3602 #define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */
<> 148:21d94c44109e 3603 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk
<> 148:21d94c44109e 3604 #define GPIO_AFRH_AFRH2_Pos (8U)
<> 148:21d94c44109e 3605 #define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */
<> 148:21d94c44109e 3606 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk
<> 148:21d94c44109e 3607 #define GPIO_AFRH_AFRH3_Pos (12U)
<> 148:21d94c44109e 3608 #define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */
<> 148:21d94c44109e 3609 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk
<> 148:21d94c44109e 3610 #define GPIO_AFRH_AFRH4_Pos (16U)
<> 148:21d94c44109e 3611 #define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */
<> 148:21d94c44109e 3612 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk
<> 148:21d94c44109e 3613 #define GPIO_AFRH_AFRH5_Pos (20U)
<> 148:21d94c44109e 3614 #define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */
<> 148:21d94c44109e 3615 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk
<> 148:21d94c44109e 3616 #define GPIO_AFRH_AFRH6_Pos (24U)
<> 148:21d94c44109e 3617 #define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */
<> 148:21d94c44109e 3618 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk
<> 148:21d94c44109e 3619 #define GPIO_AFRH_AFRH7_Pos (28U)
<> 148:21d94c44109e 3620 #define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */
<> 148:21d94c44109e 3621 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk
<> 148:21d94c44109e 3622
<> 148:21d94c44109e 3623 /****************** Bit definition for GPIO_BRR register *********************/
<> 148:21d94c44109e 3624 #define GPIO_BRR_BR_0 (0x00000001U)
<> 148:21d94c44109e 3625 #define GPIO_BRR_BR_1 (0x00000002U)
<> 148:21d94c44109e 3626 #define GPIO_BRR_BR_2 (0x00000004U)
<> 148:21d94c44109e 3627 #define GPIO_BRR_BR_3 (0x00000008U)
<> 148:21d94c44109e 3628 #define GPIO_BRR_BR_4 (0x00000010U)
<> 148:21d94c44109e 3629 #define GPIO_BRR_BR_5 (0x00000020U)
<> 148:21d94c44109e 3630 #define GPIO_BRR_BR_6 (0x00000040U)
<> 148:21d94c44109e 3631 #define GPIO_BRR_BR_7 (0x00000080U)
<> 148:21d94c44109e 3632 #define GPIO_BRR_BR_8 (0x00000100U)
<> 148:21d94c44109e 3633 #define GPIO_BRR_BR_9 (0x00000200U)
<> 148:21d94c44109e 3634 #define GPIO_BRR_BR_10 (0x00000400U)
<> 148:21d94c44109e 3635 #define GPIO_BRR_BR_11 (0x00000800U)
<> 148:21d94c44109e 3636 #define GPIO_BRR_BR_12 (0x00001000U)
<> 148:21d94c44109e 3637 #define GPIO_BRR_BR_13 (0x00002000U)
<> 148:21d94c44109e 3638 #define GPIO_BRR_BR_14 (0x00004000U)
<> 148:21d94c44109e 3639 #define GPIO_BRR_BR_15 (0x00008000U)
<> 148:21d94c44109e 3640
<> 148:21d94c44109e 3641 /******************************************************************************/
<> 148:21d94c44109e 3642 /* */
<> 148:21d94c44109e 3643 /* Inter-integrated Circuit Interface (I2C) */
<> 148:21d94c44109e 3644 /* */
<> 148:21d94c44109e 3645 /******************************************************************************/
<> 148:21d94c44109e 3646
<> 148:21d94c44109e 3647 /******************* Bit definition for I2C_CR1 register ********************/
<> 148:21d94c44109e 3648 #define I2C_CR1_PE_Pos (0U)
<> 148:21d94c44109e 3649 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 3650 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */
<> 148:21d94c44109e 3651 #define I2C_CR1_SMBUS_Pos (1U)
<> 148:21d94c44109e 3652 #define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 3653 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */
<> 148:21d94c44109e 3654 #define I2C_CR1_SMBTYPE_Pos (3U)
<> 148:21d94c44109e 3655 #define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 3656 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */
<> 148:21d94c44109e 3657 #define I2C_CR1_ENARP_Pos (4U)
<> 148:21d94c44109e 3658 #define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 3659 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */
<> 148:21d94c44109e 3660 #define I2C_CR1_ENPEC_Pos (5U)
<> 148:21d94c44109e 3661 #define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 3662 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */
<> 148:21d94c44109e 3663 #define I2C_CR1_ENGC_Pos (6U)
<> 148:21d94c44109e 3664 #define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 3665 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */
<> 148:21d94c44109e 3666 #define I2C_CR1_NOSTRETCH_Pos (7U)
<> 148:21d94c44109e 3667 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 3668 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */
<> 148:21d94c44109e 3669 #define I2C_CR1_START_Pos (8U)
<> 148:21d94c44109e 3670 #define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 3671 #define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */
<> 148:21d94c44109e 3672 #define I2C_CR1_STOP_Pos (9U)
<> 148:21d94c44109e 3673 #define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 3674 #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */
<> 148:21d94c44109e 3675 #define I2C_CR1_ACK_Pos (10U)
<> 148:21d94c44109e 3676 #define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 3677 #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */
<> 148:21d94c44109e 3678 #define I2C_CR1_POS_Pos (11U)
<> 148:21d94c44109e 3679 #define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 3680 #define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */
<> 148:21d94c44109e 3681 #define I2C_CR1_PEC_Pos (12U)
<> 148:21d94c44109e 3682 #define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 3683 #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */
<> 148:21d94c44109e 3684 #define I2C_CR1_ALERT_Pos (13U)
<> 148:21d94c44109e 3685 #define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 3686 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */
<> 148:21d94c44109e 3687 #define I2C_CR1_SWRST_Pos (15U)
<> 148:21d94c44109e 3688 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 3689 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */
<> 148:21d94c44109e 3690
<> 148:21d94c44109e 3691 /******************* Bit definition for I2C_CR2 register ********************/
<> 148:21d94c44109e 3692 #define I2C_CR2_FREQ_Pos (0U)
<> 148:21d94c44109e 3693 #define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
<> 148:21d94c44109e 3694 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
<> 148:21d94c44109e 3695 #define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 3696 #define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 3697 #define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 3698 #define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 3699 #define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 3700 #define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 3701
<> 148:21d94c44109e 3702 #define I2C_CR2_ITERREN_Pos (8U)
<> 148:21d94c44109e 3703 #define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 3704 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */
<> 148:21d94c44109e 3705 #define I2C_CR2_ITEVTEN_Pos (9U)
<> 148:21d94c44109e 3706 #define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 3707 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */
<> 148:21d94c44109e 3708 #define I2C_CR2_ITBUFEN_Pos (10U)
<> 148:21d94c44109e 3709 #define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 3710 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */
<> 148:21d94c44109e 3711 #define I2C_CR2_DMAEN_Pos (11U)
<> 148:21d94c44109e 3712 #define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 3713 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */
<> 148:21d94c44109e 3714 #define I2C_CR2_LAST_Pos (12U)
<> 148:21d94c44109e 3715 #define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 3716 #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
<> 148:21d94c44109e 3717
<> 148:21d94c44109e 3718 /******************* Bit definition for I2C_OAR1 register *******************/
<> 148:21d94c44109e 3719 #define I2C_OAR1_ADD1_7 (0x000000FEU) /*!< Interface Address */
<> 148:21d94c44109e 3720 #define I2C_OAR1_ADD8_9 (0x00000300U) /*!< Interface Address */
<> 148:21d94c44109e 3721
<> 148:21d94c44109e 3722 #define I2C_OAR1_ADD0_Pos (0U)
<> 148:21d94c44109e 3723 #define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 3724 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */
<> 148:21d94c44109e 3725 #define I2C_OAR1_ADD1_Pos (1U)
<> 148:21d94c44109e 3726 #define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 3727 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */
<> 148:21d94c44109e 3728 #define I2C_OAR1_ADD2_Pos (2U)
<> 148:21d94c44109e 3729 #define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 3730 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */
<> 148:21d94c44109e 3731 #define I2C_OAR1_ADD3_Pos (3U)
<> 148:21d94c44109e 3732 #define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 3733 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */
<> 148:21d94c44109e 3734 #define I2C_OAR1_ADD4_Pos (4U)
<> 148:21d94c44109e 3735 #define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 3736 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */
<> 148:21d94c44109e 3737 #define I2C_OAR1_ADD5_Pos (5U)
<> 148:21d94c44109e 3738 #define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 3739 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */
<> 148:21d94c44109e 3740 #define I2C_OAR1_ADD6_Pos (6U)
<> 148:21d94c44109e 3741 #define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 3742 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */
<> 148:21d94c44109e 3743 #define I2C_OAR1_ADD7_Pos (7U)
<> 148:21d94c44109e 3744 #define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 3745 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */
<> 148:21d94c44109e 3746 #define I2C_OAR1_ADD8_Pos (8U)
<> 148:21d94c44109e 3747 #define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 3748 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */
<> 148:21d94c44109e 3749 #define I2C_OAR1_ADD9_Pos (9U)
<> 148:21d94c44109e 3750 #define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 3751 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */
<> 148:21d94c44109e 3752
<> 148:21d94c44109e 3753 #define I2C_OAR1_ADDMODE_Pos (15U)
<> 148:21d94c44109e 3754 #define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 3755 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */
<> 148:21d94c44109e 3756
<> 148:21d94c44109e 3757 /******************* Bit definition for I2C_OAR2 register *******************/
<> 148:21d94c44109e 3758 #define I2C_OAR2_ENDUAL_Pos (0U)
<> 148:21d94c44109e 3759 #define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 3760 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */
<> 148:21d94c44109e 3761 #define I2C_OAR2_ADD2_Pos (1U)
<> 148:21d94c44109e 3762 #define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
<> 148:21d94c44109e 3763 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
<> 148:21d94c44109e 3764
<> 148:21d94c44109e 3765 /******************** Bit definition for I2C_DR register ********************/
<> 148:21d94c44109e 3766 #define I2C_DR_DR_Pos (0U)
<> 148:21d94c44109e 3767 #define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
<> 148:21d94c44109e 3768 #define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */
<> 148:21d94c44109e 3769
<> 148:21d94c44109e 3770 /******************* Bit definition for I2C_SR1 register ********************/
<> 148:21d94c44109e 3771 #define I2C_SR1_SB_Pos (0U)
<> 148:21d94c44109e 3772 #define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 3773 #define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */
<> 148:21d94c44109e 3774 #define I2C_SR1_ADDR_Pos (1U)
<> 148:21d94c44109e 3775 #define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 3776 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */
<> 148:21d94c44109e 3777 #define I2C_SR1_BTF_Pos (2U)
<> 148:21d94c44109e 3778 #define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 3779 #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */
<> 148:21d94c44109e 3780 #define I2C_SR1_ADD10_Pos (3U)
<> 148:21d94c44109e 3781 #define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 3782 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */
<> 148:21d94c44109e 3783 #define I2C_SR1_STOPF_Pos (4U)
<> 148:21d94c44109e 3784 #define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 3785 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */
<> 148:21d94c44109e 3786 #define I2C_SR1_RXNE_Pos (6U)
<> 148:21d94c44109e 3787 #define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 3788 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */
<> 148:21d94c44109e 3789 #define I2C_SR1_TXE_Pos (7U)
<> 148:21d94c44109e 3790 #define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 3791 #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */
<> 148:21d94c44109e 3792 #define I2C_SR1_BERR_Pos (8U)
<> 148:21d94c44109e 3793 #define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 3794 #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */
<> 148:21d94c44109e 3795 #define I2C_SR1_ARLO_Pos (9U)
<> 148:21d94c44109e 3796 #define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 3797 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */
<> 148:21d94c44109e 3798 #define I2C_SR1_AF_Pos (10U)
<> 148:21d94c44109e 3799 #define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 3800 #define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */
<> 148:21d94c44109e 3801 #define I2C_SR1_OVR_Pos (11U)
<> 148:21d94c44109e 3802 #define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 3803 #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */
<> 148:21d94c44109e 3804 #define I2C_SR1_PECERR_Pos (12U)
<> 148:21d94c44109e 3805 #define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 3806 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */
<> 148:21d94c44109e 3807 #define I2C_SR1_TIMEOUT_Pos (14U)
<> 148:21d94c44109e 3808 #define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 3809 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */
<> 148:21d94c44109e 3810 #define I2C_SR1_SMBALERT_Pos (15U)
<> 148:21d94c44109e 3811 #define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 3812 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */
<> 148:21d94c44109e 3813
<> 148:21d94c44109e 3814 /******************* Bit definition for I2C_SR2 register ********************/
<> 148:21d94c44109e 3815 #define I2C_SR2_MSL_Pos (0U)
<> 148:21d94c44109e 3816 #define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 3817 #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */
<> 148:21d94c44109e 3818 #define I2C_SR2_BUSY_Pos (1U)
<> 148:21d94c44109e 3819 #define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 3820 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */
<> 148:21d94c44109e 3821 #define I2C_SR2_TRA_Pos (2U)
<> 148:21d94c44109e 3822 #define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 3823 #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */
<> 148:21d94c44109e 3824 #define I2C_SR2_GENCALL_Pos (4U)
<> 148:21d94c44109e 3825 #define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 3826 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */
<> 148:21d94c44109e 3827 #define I2C_SR2_SMBDEFAULT_Pos (5U)
<> 148:21d94c44109e 3828 #define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 3829 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */
<> 148:21d94c44109e 3830 #define I2C_SR2_SMBHOST_Pos (6U)
<> 148:21d94c44109e 3831 #define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 3832 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */
<> 148:21d94c44109e 3833 #define I2C_SR2_DUALF_Pos (7U)
<> 148:21d94c44109e 3834 #define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 3835 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */
<> 148:21d94c44109e 3836 #define I2C_SR2_PEC_Pos (8U)
<> 148:21d94c44109e 3837 #define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
<> 148:21d94c44109e 3838 #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */
<> 148:21d94c44109e 3839
<> 148:21d94c44109e 3840 /******************* Bit definition for I2C_CCR register ********************/
<> 148:21d94c44109e 3841 #define I2C_CCR_CCR_Pos (0U)
<> 148:21d94c44109e 3842 #define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
<> 148:21d94c44109e 3843 #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */
<> 148:21d94c44109e 3844 #define I2C_CCR_DUTY_Pos (14U)
<> 148:21d94c44109e 3845 #define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 3846 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */
<> 148:21d94c44109e 3847 #define I2C_CCR_FS_Pos (15U)
<> 148:21d94c44109e 3848 #define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 3849 #define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */
<> 148:21d94c44109e 3850
<> 148:21d94c44109e 3851 /****************** Bit definition for I2C_TRISE register *******************/
<> 148:21d94c44109e 3852 #define I2C_TRISE_TRISE_Pos (0U)
<> 148:21d94c44109e 3853 #define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
<> 148:21d94c44109e 3854 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
<> 148:21d94c44109e 3855
<> 148:21d94c44109e 3856 /******************************************************************************/
<> 148:21d94c44109e 3857 /* */
<> 148:21d94c44109e 3858 /* Independent WATCHDOG (IWDG) */
<> 148:21d94c44109e 3859 /* */
<> 148:21d94c44109e 3860 /******************************************************************************/
<> 148:21d94c44109e 3861
<> 148:21d94c44109e 3862 /******************* Bit definition for IWDG_KR register ********************/
<> 148:21d94c44109e 3863 #define IWDG_KR_KEY_Pos (0U)
<> 148:21d94c44109e 3864 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 3865 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
<> 148:21d94c44109e 3866
<> 148:21d94c44109e 3867 /******************* Bit definition for IWDG_PR register ********************/
<> 148:21d94c44109e 3868 #define IWDG_PR_PR_Pos (0U)
<> 148:21d94c44109e 3869 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
<> 148:21d94c44109e 3870 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
<> 148:21d94c44109e 3871 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 3872 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 3873 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 3874
<> 148:21d94c44109e 3875 /******************* Bit definition for IWDG_RLR register *******************/
<> 148:21d94c44109e 3876 #define IWDG_RLR_RL_Pos (0U)
<> 148:21d94c44109e 3877 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
<> 148:21d94c44109e 3878 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
<> 148:21d94c44109e 3879
<> 148:21d94c44109e 3880 /******************* Bit definition for IWDG_SR register ********************/
<> 148:21d94c44109e 3881 #define IWDG_SR_PVU_Pos (0U)
<> 148:21d94c44109e 3882 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 3883 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
<> 148:21d94c44109e 3884 #define IWDG_SR_RVU_Pos (1U)
<> 148:21d94c44109e 3885 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 3886 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
<> 148:21d94c44109e 3887
<> 148:21d94c44109e 3888 /******************************************************************************/
<> 148:21d94c44109e 3889 /* */
<> 148:21d94c44109e 3890 /* Power Control (PWR) */
<> 148:21d94c44109e 3891 /* */
<> 148:21d94c44109e 3892 /******************************************************************************/
<> 148:21d94c44109e 3893
<> 148:21d94c44109e 3894 #define PWR_PVD_SUPPORT /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
<> 148:21d94c44109e 3895
<> 148:21d94c44109e 3896 /******************** Bit definition for PWR_CR register ********************/
<> 148:21d94c44109e 3897 #define PWR_CR_LPSDSR_Pos (0U)
<> 148:21d94c44109e 3898 #define PWR_CR_LPSDSR_Msk (0x1U << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 3899 #define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */
<> 148:21d94c44109e 3900 #define PWR_CR_PDDS_Pos (1U)
<> 148:21d94c44109e 3901 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 3902 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
<> 148:21d94c44109e 3903 #define PWR_CR_CWUF_Pos (2U)
<> 148:21d94c44109e 3904 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 3905 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
<> 148:21d94c44109e 3906 #define PWR_CR_CSBF_Pos (3U)
<> 148:21d94c44109e 3907 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 3908 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
<> 148:21d94c44109e 3909 #define PWR_CR_PVDE_Pos (4U)
<> 148:21d94c44109e 3910 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 3911 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
<> 148:21d94c44109e 3912
<> 148:21d94c44109e 3913 #define PWR_CR_PLS_Pos (5U)
<> 148:21d94c44109e 3914 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
<> 148:21d94c44109e 3915 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
<> 148:21d94c44109e 3916 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 3917 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 3918 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 3919
<> 148:21d94c44109e 3920 /*!< PVD level configuration */
<> 148:21d94c44109e 3921 #define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
<> 148:21d94c44109e 3922 #define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */
<> 148:21d94c44109e 3923 #define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */
<> 148:21d94c44109e 3924 #define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */
<> 148:21d94c44109e 3925 #define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */
<> 148:21d94c44109e 3926 #define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */
<> 148:21d94c44109e 3927 #define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */
<> 148:21d94c44109e 3928 #define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */
<> 148:21d94c44109e 3929
<> 148:21d94c44109e 3930 #define PWR_CR_DBP_Pos (8U)
<> 148:21d94c44109e 3931 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 3932 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
<> 148:21d94c44109e 3933 #define PWR_CR_ULP_Pos (9U)
<> 148:21d94c44109e 3934 #define PWR_CR_ULP_Msk (0x1U << PWR_CR_ULP_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 3935 #define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */
<> 148:21d94c44109e 3936 #define PWR_CR_FWU_Pos (10U)
<> 148:21d94c44109e 3937 #define PWR_CR_FWU_Msk (0x1U << PWR_CR_FWU_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 3938 #define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */
<> 148:21d94c44109e 3939
<> 148:21d94c44109e 3940 #define PWR_CR_VOS_Pos (11U)
<> 148:21d94c44109e 3941 #define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x00001800 */
<> 148:21d94c44109e 3942 #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */
<> 148:21d94c44109e 3943 #define PWR_CR_VOS_0 (0x1U << PWR_CR_VOS_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 3944 #define PWR_CR_VOS_1 (0x2U << PWR_CR_VOS_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 3945 #define PWR_CR_LPRUN_Pos (14U)
<> 148:21d94c44109e 3946 #define PWR_CR_LPRUN_Msk (0x1U << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 3947 #define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */
<> 148:21d94c44109e 3948
<> 148:21d94c44109e 3949 /******************* Bit definition for PWR_CSR register ********************/
<> 148:21d94c44109e 3950 #define PWR_CSR_WUF_Pos (0U)
<> 148:21d94c44109e 3951 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 3952 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
<> 148:21d94c44109e 3953 #define PWR_CSR_SBF_Pos (1U)
<> 148:21d94c44109e 3954 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 3955 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
<> 148:21d94c44109e 3956 #define PWR_CSR_PVDO_Pos (2U)
<> 148:21d94c44109e 3957 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 3958 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
<> 148:21d94c44109e 3959 #define PWR_CSR_VREFINTRDYF_Pos (3U)
<> 148:21d94c44109e 3960 #define PWR_CSR_VREFINTRDYF_Msk (0x1U << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 3961 #define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */
<> 148:21d94c44109e 3962 #define PWR_CSR_VOSF_Pos (4U)
<> 148:21d94c44109e 3963 #define PWR_CSR_VOSF_Msk (0x1U << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 3964 #define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */
<> 148:21d94c44109e 3965 #define PWR_CSR_REGLPF_Pos (5U)
<> 148:21d94c44109e 3966 #define PWR_CSR_REGLPF_Msk (0x1U << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 3967 #define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */
<> 148:21d94c44109e 3968
<> 148:21d94c44109e 3969 #define PWR_CSR_EWUP1_Pos (8U)
<> 148:21d94c44109e 3970 #define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 3971 #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
<> 148:21d94c44109e 3972 #define PWR_CSR_EWUP2_Pos (9U)
<> 148:21d94c44109e 3973 #define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 3974 #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
<> 148:21d94c44109e 3975 #define PWR_CSR_EWUP3_Pos (10U)
<> 148:21d94c44109e 3976 #define PWR_CSR_EWUP3_Msk (0x1U << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 3977 #define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */
<> 148:21d94c44109e 3978
<> 148:21d94c44109e 3979 /******************************************************************************/
<> 148:21d94c44109e 3980 /* */
<> 148:21d94c44109e 3981 /* Reset and Clock Control (RCC) */
<> 148:21d94c44109e 3982 /* */
<> 148:21d94c44109e 3983 /******************************************************************************/
<> 148:21d94c44109e 3984 /*
<> 148:21d94c44109e 3985 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
<> 148:21d94c44109e 3986 */
<> 148:21d94c44109e 3987 #define RCC_LSECSS_SUPPORT /*!< LSE CSS feature support */
<> 148:21d94c44109e 3988
<> 148:21d94c44109e 3989 /******************** Bit definition for RCC_CR register ********************/
<> 148:21d94c44109e 3990 #define RCC_CR_HSION_Pos (0U)
<> 148:21d94c44109e 3991 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 3992 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
<> 148:21d94c44109e 3993 #define RCC_CR_HSIRDY_Pos (1U)
<> 148:21d94c44109e 3994 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 3995 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
<> 148:21d94c44109e 3996
<> 148:21d94c44109e 3997 #define RCC_CR_MSION_Pos (8U)
<> 148:21d94c44109e 3998 #define RCC_CR_MSION_Msk (0x1U << RCC_CR_MSION_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 3999 #define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */
<> 148:21d94c44109e 4000 #define RCC_CR_MSIRDY_Pos (9U)
<> 148:21d94c44109e 4001 #define RCC_CR_MSIRDY_Msk (0x1U << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 4002 #define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */
<> 148:21d94c44109e 4003
<> 148:21d94c44109e 4004 #define RCC_CR_HSEON_Pos (16U)
<> 148:21d94c44109e 4005 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 4006 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
<> 148:21d94c44109e 4007 #define RCC_CR_HSERDY_Pos (17U)
<> 148:21d94c44109e 4008 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 4009 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
<> 148:21d94c44109e 4010 #define RCC_CR_HSEBYP_Pos (18U)
<> 148:21d94c44109e 4011 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 4012 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
<> 148:21d94c44109e 4013
<> 148:21d94c44109e 4014 #define RCC_CR_PLLON_Pos (24U)
<> 148:21d94c44109e 4015 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
<> 148:21d94c44109e 4016 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
<> 148:21d94c44109e 4017 #define RCC_CR_PLLRDY_Pos (25U)
<> 148:21d94c44109e 4018 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
<> 148:21d94c44109e 4019 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
<> 148:21d94c44109e 4020 #define RCC_CR_CSSON_Pos (28U)
<> 148:21d94c44109e 4021 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x10000000 */
<> 148:21d94c44109e 4022 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */
<> 148:21d94c44109e 4023
<> 148:21d94c44109e 4024 #define RCC_CR_RTCPRE_Pos (29U)
<> 148:21d94c44109e 4025 #define RCC_CR_RTCPRE_Msk (0x3U << RCC_CR_RTCPRE_Pos) /*!< 0x60000000 */
<> 148:21d94c44109e 4026 #define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC Prescaler */
<> 148:21d94c44109e 4027 #define RCC_CR_RTCPRE_0 (0x20000000U) /*!< Bit0 */
<> 148:21d94c44109e 4028 #define RCC_CR_RTCPRE_1 (0x40000000U) /*!< Bit1 */
<> 148:21d94c44109e 4029
<> 148:21d94c44109e 4030 /******************** Bit definition for RCC_ICSCR register *****************/
<> 148:21d94c44109e 4031 #define RCC_ICSCR_HSICAL_Pos (0U)
<> 148:21d94c44109e 4032 #define RCC_ICSCR_HSICAL_Msk (0xFFU << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */
<> 148:21d94c44109e 4033 #define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
<> 148:21d94c44109e 4034 #define RCC_ICSCR_HSITRIM_Pos (8U)
<> 148:21d94c44109e 4035 #define RCC_ICSCR_HSITRIM_Msk (0x1FU << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */
<> 148:21d94c44109e 4036 #define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
<> 148:21d94c44109e 4037
<> 148:21d94c44109e 4038 #define RCC_ICSCR_MSIRANGE_Pos (13U)
<> 148:21d94c44109e 4039 #define RCC_ICSCR_MSIRANGE_Msk (0x7U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */
<> 148:21d94c44109e 4040 #define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */
<> 148:21d94c44109e 4041 #define RCC_ICSCR_MSIRANGE_0 (0x0U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */
<> 148:21d94c44109e 4042 #define RCC_ICSCR_MSIRANGE_1 (0x1U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 4043 #define RCC_ICSCR_MSIRANGE_2 (0x2U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 4044 #define RCC_ICSCR_MSIRANGE_3 (0x3U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */
<> 148:21d94c44109e 4045 #define RCC_ICSCR_MSIRANGE_4 (0x4U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 4046 #define RCC_ICSCR_MSIRANGE_5 (0x5U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */
<> 148:21d94c44109e 4047 #define RCC_ICSCR_MSIRANGE_6 (0x6U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */
<> 148:21d94c44109e 4048 #define RCC_ICSCR_MSICAL_Pos (16U)
<> 148:21d94c44109e 4049 #define RCC_ICSCR_MSICAL_Msk (0xFFU << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */
<> 148:21d94c44109e 4050 #define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */
<> 148:21d94c44109e 4051 #define RCC_ICSCR_MSITRIM_Pos (24U)
<> 148:21d94c44109e 4052 #define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */
<> 148:21d94c44109e 4053 #define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */
<> 148:21d94c44109e 4054
<> 148:21d94c44109e 4055 /******************** Bit definition for RCC_CFGR register ******************/
<> 148:21d94c44109e 4056 #define RCC_CFGR_SW_Pos (0U)
<> 148:21d94c44109e 4057 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
<> 148:21d94c44109e 4058 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
<> 148:21d94c44109e 4059 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 4060 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 4061
<> 148:21d94c44109e 4062 /*!< SW configuration */
<> 148:21d94c44109e 4063 #define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */
<> 148:21d94c44109e 4064 #define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */
<> 148:21d94c44109e 4065 #define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */
<> 148:21d94c44109e 4066 #define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */
<> 148:21d94c44109e 4067
<> 148:21d94c44109e 4068 #define RCC_CFGR_SWS_Pos (2U)
<> 148:21d94c44109e 4069 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
<> 148:21d94c44109e 4070 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
<> 148:21d94c44109e 4071 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 4072 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 4073
<> 148:21d94c44109e 4074 /*!< SWS configuration */
<> 148:21d94c44109e 4075 #define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
<> 148:21d94c44109e 4076 #define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */
<> 148:21d94c44109e 4077 #define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
<> 148:21d94c44109e 4078 #define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
<> 148:21d94c44109e 4079
<> 148:21d94c44109e 4080 #define RCC_CFGR_HPRE_Pos (4U)
<> 148:21d94c44109e 4081 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
<> 148:21d94c44109e 4082 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
<> 148:21d94c44109e 4083 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 4084 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 4085 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 4086 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 4087
<> 148:21d94c44109e 4088 /*!< HPRE configuration */
<> 148:21d94c44109e 4089 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
<> 148:21d94c44109e 4090 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
<> 148:21d94c44109e 4091 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
<> 148:21d94c44109e 4092 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
<> 148:21d94c44109e 4093 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
<> 148:21d94c44109e 4094 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
<> 148:21d94c44109e 4095 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
<> 148:21d94c44109e 4096 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
<> 148:21d94c44109e 4097 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
<> 148:21d94c44109e 4098
<> 148:21d94c44109e 4099 #define RCC_CFGR_PPRE1_Pos (8U)
<> 148:21d94c44109e 4100 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
<> 148:21d94c44109e 4101 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
<> 148:21d94c44109e 4102 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 4103 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 4104 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 4105
<> 148:21d94c44109e 4106 /*!< PPRE1 configuration */
<> 148:21d94c44109e 4107 #define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
<> 148:21d94c44109e 4108 #define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
<> 148:21d94c44109e 4109 #define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
<> 148:21d94c44109e 4110 #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
<> 148:21d94c44109e 4111 #define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
<> 148:21d94c44109e 4112
<> 148:21d94c44109e 4113 #define RCC_CFGR_PPRE2_Pos (11U)
<> 148:21d94c44109e 4114 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
<> 148:21d94c44109e 4115 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
<> 148:21d94c44109e 4116 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 4117 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 4118 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 4119
<> 148:21d94c44109e 4120 /*!< PPRE2 configuration */
<> 148:21d94c44109e 4121 #define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
<> 148:21d94c44109e 4122 #define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
<> 148:21d94c44109e 4123 #define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
<> 148:21d94c44109e 4124 #define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
<> 148:21d94c44109e 4125 #define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
<> 148:21d94c44109e 4126
<> 148:21d94c44109e 4127 /*!< PLL entry clock source*/
<> 148:21d94c44109e 4128 #define RCC_CFGR_PLLSRC_Pos (16U)
<> 148:21d94c44109e 4129 #define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 4130 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
<> 148:21d94c44109e 4131
<> 148:21d94c44109e 4132 #define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */
<> 148:21d94c44109e 4133 #define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */
<> 148:21d94c44109e 4134
<> 148:21d94c44109e 4135
<> 148:21d94c44109e 4136 /*!< PLLMUL configuration */
<> 148:21d94c44109e 4137 #define RCC_CFGR_PLLMUL_Pos (18U)
<> 148:21d94c44109e 4138 #define RCC_CFGR_PLLMUL_Msk (0xFU << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
<> 148:21d94c44109e 4139 #define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
<> 148:21d94c44109e 4140 #define RCC_CFGR_PLLMUL_0 (0x1U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 4141 #define RCC_CFGR_PLLMUL_1 (0x2U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 4142 #define RCC_CFGR_PLLMUL_2 (0x4U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 4143 #define RCC_CFGR_PLLMUL_3 (0x8U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 4144
<> 148:21d94c44109e 4145 /*!< PLLMUL configuration */
<> 148:21d94c44109e 4146 #define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */
<> 148:21d94c44109e 4147 #define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */
<> 148:21d94c44109e 4148 #define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */
<> 148:21d94c44109e 4149 #define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */
<> 148:21d94c44109e 4150 #define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */
<> 148:21d94c44109e 4151 #define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */
<> 148:21d94c44109e 4152 #define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */
<> 148:21d94c44109e 4153 #define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */
<> 148:21d94c44109e 4154 #define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */
<> 148:21d94c44109e 4155
<> 148:21d94c44109e 4156 /*!< PLLDIV configuration */
<> 148:21d94c44109e 4157 #define RCC_CFGR_PLLDIV_Pos (22U)
<> 148:21d94c44109e 4158 #define RCC_CFGR_PLLDIV_Msk (0x3U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */
<> 148:21d94c44109e 4159 #define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */
<> 148:21d94c44109e 4160 #define RCC_CFGR_PLLDIV_0 (0x1U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 4161 #define RCC_CFGR_PLLDIV_1 (0x2U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 4162
<> 148:21d94c44109e 4163
<> 148:21d94c44109e 4164 /*!< PLLDIV configuration */
<> 148:21d94c44109e 4165 #define RCC_CFGR_PLLDIV1 (0x00000000U) /*!< PLL clock output = CKVCO / 1 */
<> 148:21d94c44109e 4166 #define RCC_CFGR_PLLDIV2_Pos (22U)
<> 148:21d94c44109e 4167 #define RCC_CFGR_PLLDIV2_Msk (0x1U << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 4168 #define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */
<> 148:21d94c44109e 4169 #define RCC_CFGR_PLLDIV3_Pos (23U)
<> 148:21d94c44109e 4170 #define RCC_CFGR_PLLDIV3_Msk (0x1U << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 4171 #define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */
<> 148:21d94c44109e 4172 #define RCC_CFGR_PLLDIV4_Pos (22U)
<> 148:21d94c44109e 4173 #define RCC_CFGR_PLLDIV4_Msk (0x3U << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */
<> 148:21d94c44109e 4174 #define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */
<> 148:21d94c44109e 4175
<> 148:21d94c44109e 4176
<> 148:21d94c44109e 4177 #define RCC_CFGR_MCOSEL_Pos (24U)
<> 148:21d94c44109e 4178 #define RCC_CFGR_MCOSEL_Msk (0x7U << RCC_CFGR_MCOSEL_Pos) /*!< 0x07000000 */
<> 148:21d94c44109e 4179 #define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */
<> 148:21d94c44109e 4180 #define RCC_CFGR_MCOSEL_0 (0x1U << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
<> 148:21d94c44109e 4181 #define RCC_CFGR_MCOSEL_1 (0x2U << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
<> 148:21d94c44109e 4182 #define RCC_CFGR_MCOSEL_2 (0x4U << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
<> 148:21d94c44109e 4183
<> 148:21d94c44109e 4184 /*!< MCO configuration */
<> 148:21d94c44109e 4185 #define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */
<> 148:21d94c44109e 4186 #define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U)
<> 148:21d94c44109e 4187 #define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1U << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
<> 148:21d94c44109e 4188 #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected */
<> 148:21d94c44109e 4189 #define RCC_CFGR_MCOSEL_HSI_Pos (25U)
<> 148:21d94c44109e 4190 #define RCC_CFGR_MCOSEL_HSI_Msk (0x1U << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
<> 148:21d94c44109e 4191 #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */
<> 148:21d94c44109e 4192 #define RCC_CFGR_MCOSEL_MSI_Pos (24U)
<> 148:21d94c44109e 4193 #define RCC_CFGR_MCOSEL_MSI_Msk (0x3U << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
<> 148:21d94c44109e 4194 #define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */
<> 148:21d94c44109e 4195 #define RCC_CFGR_MCOSEL_HSE_Pos (26U)
<> 148:21d94c44109e 4196 #define RCC_CFGR_MCOSEL_HSE_Msk (0x1U << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
<> 148:21d94c44109e 4197 #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */
<> 148:21d94c44109e 4198 #define RCC_CFGR_MCOSEL_PLL_Pos (24U)
<> 148:21d94c44109e 4199 #define RCC_CFGR_MCOSEL_PLL_Msk (0x5U << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
<> 148:21d94c44109e 4200 #define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */
<> 148:21d94c44109e 4201 #define RCC_CFGR_MCOSEL_LSI_Pos (25U)
<> 148:21d94c44109e 4202 #define RCC_CFGR_MCOSEL_LSI_Msk (0x3U << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
<> 148:21d94c44109e 4203 #define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */
<> 148:21d94c44109e 4204 #define RCC_CFGR_MCOSEL_LSE_Pos (24U)
<> 148:21d94c44109e 4205 #define RCC_CFGR_MCOSEL_LSE_Msk (0x7U << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
<> 148:21d94c44109e 4206 #define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */
<> 148:21d94c44109e 4207
<> 148:21d94c44109e 4208 #define RCC_CFGR_MCOPRE_Pos (28U)
<> 148:21d94c44109e 4209 #define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
<> 148:21d94c44109e 4210 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
<> 148:21d94c44109e 4211 #define RCC_CFGR_MCOPRE_0 (0x1U << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
<> 148:21d94c44109e 4212 #define RCC_CFGR_MCOPRE_1 (0x2U << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
<> 148:21d94c44109e 4213 #define RCC_CFGR_MCOPRE_2 (0x4U << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
<> 148:21d94c44109e 4214
<> 148:21d94c44109e 4215 /*!< MCO Prescaler configuration */
<> 148:21d94c44109e 4216 #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
<> 148:21d94c44109e 4217 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
<> 148:21d94c44109e 4218 #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
<> 148:21d94c44109e 4219 #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
<> 148:21d94c44109e 4220 #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
<> 148:21d94c44109e 4221
<> 148:21d94c44109e 4222 /* Legacy aliases */
<> 148:21d94c44109e 4223 #define RCC_CFGR_MCO_DIV1 RCC_CFGR_MCOPRE_DIV1
<> 148:21d94c44109e 4224 #define RCC_CFGR_MCO_DIV2 RCC_CFGR_MCOPRE_DIV2
<> 148:21d94c44109e 4225 #define RCC_CFGR_MCO_DIV4 RCC_CFGR_MCOPRE_DIV4
<> 148:21d94c44109e 4226 #define RCC_CFGR_MCO_DIV8 RCC_CFGR_MCOPRE_DIV8
<> 148:21d94c44109e 4227 #define RCC_CFGR_MCO_DIV16 RCC_CFGR_MCOPRE_DIV16
<> 148:21d94c44109e 4228 #define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK
<> 148:21d94c44109e 4229 #define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK
<> 148:21d94c44109e 4230 #define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI
<> 148:21d94c44109e 4231 #define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI
<> 148:21d94c44109e 4232 #define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE
<> 148:21d94c44109e 4233 #define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
<> 148:21d94c44109e 4234 #define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI
<> 148:21d94c44109e 4235 #define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE
<> 148:21d94c44109e 4236
<> 148:21d94c44109e 4237 /*!<****************** Bit definition for RCC_CIR register ********************/
<> 148:21d94c44109e 4238 #define RCC_CIR_LSIRDYF_Pos (0U)
<> 148:21d94c44109e 4239 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 4240 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
<> 148:21d94c44109e 4241 #define RCC_CIR_LSERDYF_Pos (1U)
<> 148:21d94c44109e 4242 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 4243 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
<> 148:21d94c44109e 4244 #define RCC_CIR_HSIRDYF_Pos (2U)
<> 148:21d94c44109e 4245 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 4246 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
<> 148:21d94c44109e 4247 #define RCC_CIR_HSERDYF_Pos (3U)
<> 148:21d94c44109e 4248 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 4249 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
<> 148:21d94c44109e 4250 #define RCC_CIR_PLLRDYF_Pos (4U)
<> 148:21d94c44109e 4251 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 4252 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
<> 148:21d94c44109e 4253 #define RCC_CIR_MSIRDYF_Pos (5U)
<> 148:21d94c44109e 4254 #define RCC_CIR_MSIRDYF_Msk (0x1U << RCC_CIR_MSIRDYF_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 4255 #define RCC_CIR_MSIRDYF RCC_CIR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */
<> 148:21d94c44109e 4256 #define RCC_CIR_LSECSSF_Pos (6U)
<> 148:21d94c44109e 4257 #define RCC_CIR_LSECSSF_Msk (0x1U << RCC_CIR_LSECSSF_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 4258 #define RCC_CIR_LSECSSF RCC_CIR_LSECSSF_Msk /*!< LSE CSS Interrupt flag */
<> 148:21d94c44109e 4259 #define RCC_CIR_CSSF_Pos (7U)
<> 148:21d94c44109e 4260 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 4261 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
<> 148:21d94c44109e 4262
<> 148:21d94c44109e 4263 #define RCC_CIR_LSIRDYIE_Pos (8U)
<> 148:21d94c44109e 4264 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 4265 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
<> 148:21d94c44109e 4266 #define RCC_CIR_LSERDYIE_Pos (9U)
<> 148:21d94c44109e 4267 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 4268 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
<> 148:21d94c44109e 4269 #define RCC_CIR_HSIRDYIE_Pos (10U)
<> 148:21d94c44109e 4270 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 4271 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
<> 148:21d94c44109e 4272 #define RCC_CIR_HSERDYIE_Pos (11U)
<> 148:21d94c44109e 4273 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 4274 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
<> 148:21d94c44109e 4275 #define RCC_CIR_PLLRDYIE_Pos (12U)
<> 148:21d94c44109e 4276 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 4277 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
<> 148:21d94c44109e 4278 #define RCC_CIR_MSIRDYIE_Pos (13U)
<> 148:21d94c44109e 4279 #define RCC_CIR_MSIRDYIE_Msk (0x1U << RCC_CIR_MSIRDYIE_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 4280 #define RCC_CIR_MSIRDYIE RCC_CIR_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */
<> 148:21d94c44109e 4281 #define RCC_CIR_LSECSSIE_Pos (14U)
<> 148:21d94c44109e 4282 #define RCC_CIR_LSECSSIE_Msk (0x1U << RCC_CIR_LSECSSIE_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 4283 #define RCC_CIR_LSECSSIE RCC_CIR_LSECSSIE_Msk /*!< LSE CSS Interrupt Enable */
<> 148:21d94c44109e 4284
<> 148:21d94c44109e 4285 #define RCC_CIR_LSIRDYC_Pos (16U)
<> 148:21d94c44109e 4286 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 4287 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
<> 148:21d94c44109e 4288 #define RCC_CIR_LSERDYC_Pos (17U)
<> 148:21d94c44109e 4289 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 4290 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
<> 148:21d94c44109e 4291 #define RCC_CIR_HSIRDYC_Pos (18U)
<> 148:21d94c44109e 4292 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 4293 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
<> 148:21d94c44109e 4294 #define RCC_CIR_HSERDYC_Pos (19U)
<> 148:21d94c44109e 4295 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 4296 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
<> 148:21d94c44109e 4297 #define RCC_CIR_PLLRDYC_Pos (20U)
<> 148:21d94c44109e 4298 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 4299 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
<> 148:21d94c44109e 4300 #define RCC_CIR_MSIRDYC_Pos (21U)
<> 148:21d94c44109e 4301 #define RCC_CIR_MSIRDYC_Msk (0x1U << RCC_CIR_MSIRDYC_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 4302 #define RCC_CIR_MSIRDYC RCC_CIR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */
<> 148:21d94c44109e 4303 #define RCC_CIR_LSECSSC_Pos (22U)
<> 148:21d94c44109e 4304 #define RCC_CIR_LSECSSC_Msk (0x1U << RCC_CIR_LSECSSC_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 4305 #define RCC_CIR_LSECSSC RCC_CIR_LSECSSC_Msk /*!< LSE CSS Interrupt Clear */
<> 148:21d94c44109e 4306 #define RCC_CIR_CSSC_Pos (23U)
<> 148:21d94c44109e 4307 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 4308 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
<> 148:21d94c44109e 4309
<> 148:21d94c44109e 4310 /***************** Bit definition for RCC_AHBRSTR register ******************/
<> 148:21d94c44109e 4311 #define RCC_AHBRSTR_GPIOARST_Pos (0U)
<> 148:21d94c44109e 4312 #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 4313 #define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIO port A reset */
<> 148:21d94c44109e 4314 #define RCC_AHBRSTR_GPIOBRST_Pos (1U)
<> 148:21d94c44109e 4315 #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 4316 #define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIO port B reset */
<> 148:21d94c44109e 4317 #define RCC_AHBRSTR_GPIOCRST_Pos (2U)
<> 148:21d94c44109e 4318 #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 4319 #define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIO port C reset */
<> 148:21d94c44109e 4320 #define RCC_AHBRSTR_GPIODRST_Pos (3U)
<> 148:21d94c44109e 4321 #define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 4322 #define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIO port D reset */
<> 148:21d94c44109e 4323 #define RCC_AHBRSTR_GPIOERST_Pos (4U)
<> 148:21d94c44109e 4324 #define RCC_AHBRSTR_GPIOERST_Msk (0x1U << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 4325 #define RCC_AHBRSTR_GPIOERST RCC_AHBRSTR_GPIOERST_Msk /*!< GPIO port E reset */
<> 148:21d94c44109e 4326 #define RCC_AHBRSTR_GPIOHRST_Pos (5U)
<> 148:21d94c44109e 4327 #define RCC_AHBRSTR_GPIOHRST_Msk (0x1U << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 4328 #define RCC_AHBRSTR_GPIOHRST RCC_AHBRSTR_GPIOHRST_Msk /*!< GPIO port H reset */
<> 148:21d94c44109e 4329 #define RCC_AHBRSTR_CRCRST_Pos (12U)
<> 148:21d94c44109e 4330 #define RCC_AHBRSTR_CRCRST_Msk (0x1U << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 4331 #define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */
<> 148:21d94c44109e 4332 #define RCC_AHBRSTR_FLITFRST_Pos (15U)
<> 148:21d94c44109e 4333 #define RCC_AHBRSTR_FLITFRST_Msk (0x1U << RCC_AHBRSTR_FLITFRST_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 4334 #define RCC_AHBRSTR_FLITFRST RCC_AHBRSTR_FLITFRST_Msk /*!< FLITF reset */
<> 148:21d94c44109e 4335 #define RCC_AHBRSTR_DMA1RST_Pos (24U)
<> 148:21d94c44109e 4336 #define RCC_AHBRSTR_DMA1RST_Msk (0x1U << RCC_AHBRSTR_DMA1RST_Pos) /*!< 0x01000000 */
<> 148:21d94c44109e 4337 #define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMA1RST_Msk /*!< DMA1 reset */
<> 148:21d94c44109e 4338 #define RCC_AHBRSTR_DMA2RST_Pos (25U)
<> 148:21d94c44109e 4339 #define RCC_AHBRSTR_DMA2RST_Msk (0x1U << RCC_AHBRSTR_DMA2RST_Pos) /*!< 0x02000000 */
<> 148:21d94c44109e 4340 #define RCC_AHBRSTR_DMA2RST RCC_AHBRSTR_DMA2RST_Msk /*!< DMA2 reset */
<> 148:21d94c44109e 4341
<> 148:21d94c44109e 4342 /***************** Bit definition for RCC_APB2RSTR register *****************/
<> 148:21d94c44109e 4343 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
<> 148:21d94c44109e 4344 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 4345 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< System Configuration SYSCFG reset */
<> 148:21d94c44109e 4346 #define RCC_APB2RSTR_TIM9RST_Pos (2U)
<> 148:21d94c44109e 4347 #define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 4348 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk /*!< TIM9 reset */
<> 148:21d94c44109e 4349 #define RCC_APB2RSTR_TIM10RST_Pos (3U)
<> 148:21d94c44109e 4350 #define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 4351 #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk /*!< TIM10 reset */
<> 148:21d94c44109e 4352 #define RCC_APB2RSTR_TIM11RST_Pos (4U)
<> 148:21d94c44109e 4353 #define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 4354 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk /*!< TIM11 reset */
<> 148:21d94c44109e 4355 #define RCC_APB2RSTR_ADC1RST_Pos (9U)
<> 148:21d94c44109e 4356 #define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 4357 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC1 reset */
<> 148:21d94c44109e 4358 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
<> 148:21d94c44109e 4359 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 4360 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */
<> 148:21d94c44109e 4361 #define RCC_APB2RSTR_USART1RST_Pos (14U)
<> 148:21d94c44109e 4362 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 4363 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
<> 148:21d94c44109e 4364
<> 148:21d94c44109e 4365 /***************** Bit definition for RCC_APB1RSTR register *****************/
<> 148:21d94c44109e 4366 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
<> 148:21d94c44109e 4367 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 4368 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
<> 148:21d94c44109e 4369 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
<> 148:21d94c44109e 4370 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 4371 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
<> 148:21d94c44109e 4372 #define RCC_APB1RSTR_TIM4RST_Pos (2U)
<> 148:21d94c44109e 4373 #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 4374 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */
<> 148:21d94c44109e 4375 #define RCC_APB1RSTR_TIM5RST_Pos (3U)
<> 148:21d94c44109e 4376 #define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 4377 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk /*!< Timer 5 reset */
<> 148:21d94c44109e 4378 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
<> 148:21d94c44109e 4379 #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 4380 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */
<> 148:21d94c44109e 4381 #define RCC_APB1RSTR_TIM7RST_Pos (5U)
<> 148:21d94c44109e 4382 #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 4383 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */
<> 148:21d94c44109e 4384 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
<> 148:21d94c44109e 4385 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 4386 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
<> 148:21d94c44109e 4387 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
<> 148:21d94c44109e 4388 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 4389 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */
<> 148:21d94c44109e 4390 #define RCC_APB1RSTR_SPI3RST_Pos (15U)
<> 148:21d94c44109e 4391 #define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 4392 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk /*!< SPI 3 reset */
<> 148:21d94c44109e 4393 #define RCC_APB1RSTR_USART2RST_Pos (17U)
<> 148:21d94c44109e 4394 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 4395 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
<> 148:21d94c44109e 4396 #define RCC_APB1RSTR_USART3RST_Pos (18U)
<> 148:21d94c44109e 4397 #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 4398 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */
<> 148:21d94c44109e 4399 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
<> 148:21d94c44109e 4400 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 4401 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
<> 148:21d94c44109e 4402 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
<> 148:21d94c44109e 4403 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 4404 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
<> 148:21d94c44109e 4405 #define RCC_APB1RSTR_USBRST_Pos (23U)
<> 148:21d94c44109e 4406 #define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 4407 #define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB reset */
<> 148:21d94c44109e 4408 #define RCC_APB1RSTR_PWRRST_Pos (28U)
<> 148:21d94c44109e 4409 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
<> 148:21d94c44109e 4410 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */
<> 148:21d94c44109e 4411 #define RCC_APB1RSTR_DACRST_Pos (29U)
<> 148:21d94c44109e 4412 #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
<> 148:21d94c44109e 4413 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC interface reset */
<> 148:21d94c44109e 4414 #define RCC_APB1RSTR_COMPRST_Pos (31U)
<> 148:21d94c44109e 4415 #define RCC_APB1RSTR_COMPRST_Msk (0x1U << RCC_APB1RSTR_COMPRST_Pos) /*!< 0x80000000 */
<> 148:21d94c44109e 4416 #define RCC_APB1RSTR_COMPRST RCC_APB1RSTR_COMPRST_Msk /*!< Comparator interface reset */
<> 148:21d94c44109e 4417
<> 148:21d94c44109e 4418 /****************** Bit definition for RCC_AHBENR register ******************/
<> 148:21d94c44109e 4419 #define RCC_AHBENR_GPIOAEN_Pos (0U)
<> 148:21d94c44109e 4420 #define RCC_AHBENR_GPIOAEN_Msk (0x1U << RCC_AHBENR_GPIOAEN_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 4421 #define RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk /*!< GPIO port A clock enable */
<> 148:21d94c44109e 4422 #define RCC_AHBENR_GPIOBEN_Pos (1U)
<> 148:21d94c44109e 4423 #define RCC_AHBENR_GPIOBEN_Msk (0x1U << RCC_AHBENR_GPIOBEN_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 4424 #define RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk /*!< GPIO port B clock enable */
<> 148:21d94c44109e 4425 #define RCC_AHBENR_GPIOCEN_Pos (2U)
<> 148:21d94c44109e 4426 #define RCC_AHBENR_GPIOCEN_Msk (0x1U << RCC_AHBENR_GPIOCEN_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 4427 #define RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk /*!< GPIO port C clock enable */
<> 148:21d94c44109e 4428 #define RCC_AHBENR_GPIODEN_Pos (3U)
<> 148:21d94c44109e 4429 #define RCC_AHBENR_GPIODEN_Msk (0x1U << RCC_AHBENR_GPIODEN_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 4430 #define RCC_AHBENR_GPIODEN RCC_AHBENR_GPIODEN_Msk /*!< GPIO port D clock enable */
<> 148:21d94c44109e 4431 #define RCC_AHBENR_GPIOEEN_Pos (4U)
<> 148:21d94c44109e 4432 #define RCC_AHBENR_GPIOEEN_Msk (0x1U << RCC_AHBENR_GPIOEEN_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 4433 #define RCC_AHBENR_GPIOEEN RCC_AHBENR_GPIOEEN_Msk /*!< GPIO port E clock enable */
<> 148:21d94c44109e 4434 #define RCC_AHBENR_GPIOHEN_Pos (5U)
<> 148:21d94c44109e 4435 #define RCC_AHBENR_GPIOHEN_Msk (0x1U << RCC_AHBENR_GPIOHEN_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 4436 #define RCC_AHBENR_GPIOHEN RCC_AHBENR_GPIOHEN_Msk /*!< GPIO port H clock enable */
<> 148:21d94c44109e 4437 #define RCC_AHBENR_CRCEN_Pos (12U)
<> 148:21d94c44109e 4438 #define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 4439 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
<> 148:21d94c44109e 4440 #define RCC_AHBENR_FLITFEN_Pos (15U)
<> 148:21d94c44109e 4441 #define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 4442 #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable (has effect only when
<> 148:21d94c44109e 4443 the Flash memory is in power down mode) */
<> 148:21d94c44109e 4444 #define RCC_AHBENR_DMA1EN_Pos (24U)
<> 148:21d94c44109e 4445 #define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x01000000 */
<> 148:21d94c44109e 4446 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */
<> 148:21d94c44109e 4447 #define RCC_AHBENR_DMA2EN_Pos (25U)
<> 148:21d94c44109e 4448 #define RCC_AHBENR_DMA2EN_Msk (0x1U << RCC_AHBENR_DMA2EN_Pos) /*!< 0x02000000 */
<> 148:21d94c44109e 4449 #define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enable */
<> 148:21d94c44109e 4450
<> 148:21d94c44109e 4451 /****************** Bit definition for RCC_APB2ENR register *****************/
<> 148:21d94c44109e 4452 #define RCC_APB2ENR_SYSCFGEN_Pos (0U)
<> 148:21d94c44109e 4453 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 4454 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< System Configuration SYSCFG clock enable */
<> 148:21d94c44109e 4455 #define RCC_APB2ENR_TIM9EN_Pos (2U)
<> 148:21d94c44109e 4456 #define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 4457 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk /*!< TIM9 interface clock enable */
<> 148:21d94c44109e 4458 #define RCC_APB2ENR_TIM10EN_Pos (3U)
<> 148:21d94c44109e 4459 #define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 4460 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk /*!< TIM10 interface clock enable */
<> 148:21d94c44109e 4461 #define RCC_APB2ENR_TIM11EN_Pos (4U)
<> 148:21d94c44109e 4462 #define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 4463 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk /*!< TIM11 Timer clock enable */
<> 148:21d94c44109e 4464 #define RCC_APB2ENR_ADC1EN_Pos (9U)
<> 148:21d94c44109e 4465 #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 4466 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC1 clock enable */
<> 148:21d94c44109e 4467 #define RCC_APB2ENR_SPI1EN_Pos (12U)
<> 148:21d94c44109e 4468 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 4469 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */
<> 148:21d94c44109e 4470 #define RCC_APB2ENR_USART1EN_Pos (14U)
<> 148:21d94c44109e 4471 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 4472 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
<> 148:21d94c44109e 4473
<> 148:21d94c44109e 4474 /***************** Bit definition for RCC_APB1ENR register ******************/
<> 148:21d94c44109e 4475 #define RCC_APB1ENR_TIM2EN_Pos (0U)
<> 148:21d94c44109e 4476 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 4477 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/
<> 148:21d94c44109e 4478 #define RCC_APB1ENR_TIM3EN_Pos (1U)
<> 148:21d94c44109e 4479 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 4480 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
<> 148:21d94c44109e 4481 #define RCC_APB1ENR_TIM4EN_Pos (2U)
<> 148:21d94c44109e 4482 #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 4483 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */
<> 148:21d94c44109e 4484 #define RCC_APB1ENR_TIM5EN_Pos (3U)
<> 148:21d94c44109e 4485 #define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 4486 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk /*!< Timer 5 clock enable */
<> 148:21d94c44109e 4487 #define RCC_APB1ENR_TIM6EN_Pos (4U)
<> 148:21d94c44109e 4488 #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 4489 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */
<> 148:21d94c44109e 4490 #define RCC_APB1ENR_TIM7EN_Pos (5U)
<> 148:21d94c44109e 4491 #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 4492 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */
<> 148:21d94c44109e 4493 #define RCC_APB1ENR_WWDGEN_Pos (11U)
<> 148:21d94c44109e 4494 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 4495 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
<> 148:21d94c44109e 4496 #define RCC_APB1ENR_SPI2EN_Pos (14U)
<> 148:21d94c44109e 4497 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 4498 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */
<> 148:21d94c44109e 4499 #define RCC_APB1ENR_SPI3EN_Pos (15U)
<> 148:21d94c44109e 4500 #define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 4501 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI 3 clock enable */
<> 148:21d94c44109e 4502 #define RCC_APB1ENR_USART2EN_Pos (17U)
<> 148:21d94c44109e 4503 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 4504 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */
<> 148:21d94c44109e 4505 #define RCC_APB1ENR_USART3EN_Pos (18U)
<> 148:21d94c44109e 4506 #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 4507 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */
<> 148:21d94c44109e 4508 #define RCC_APB1ENR_I2C1EN_Pos (21U)
<> 148:21d94c44109e 4509 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 4510 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */
<> 148:21d94c44109e 4511 #define RCC_APB1ENR_I2C2EN_Pos (22U)
<> 148:21d94c44109e 4512 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 4513 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */
<> 148:21d94c44109e 4514 #define RCC_APB1ENR_USBEN_Pos (23U)
<> 148:21d94c44109e 4515 #define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 4516 #define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB clock enable */
<> 148:21d94c44109e 4517 #define RCC_APB1ENR_PWREN_Pos (28U)
<> 148:21d94c44109e 4518 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
<> 148:21d94c44109e 4519 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */
<> 148:21d94c44109e 4520 #define RCC_APB1ENR_DACEN_Pos (29U)
<> 148:21d94c44109e 4521 #define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
<> 148:21d94c44109e 4522 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC interface clock enable */
<> 148:21d94c44109e 4523 #define RCC_APB1ENR_COMPEN_Pos (31U)
<> 148:21d94c44109e 4524 #define RCC_APB1ENR_COMPEN_Msk (0x1U << RCC_APB1ENR_COMPEN_Pos) /*!< 0x80000000 */
<> 148:21d94c44109e 4525 #define RCC_APB1ENR_COMPEN RCC_APB1ENR_COMPEN_Msk /*!< Comparator interface clock enable */
<> 148:21d94c44109e 4526
<> 148:21d94c44109e 4527 /****************** Bit definition for RCC_AHBLPENR register ****************/
<> 148:21d94c44109e 4528 #define RCC_AHBLPENR_GPIOALPEN_Pos (0U)
<> 148:21d94c44109e 4529 #define RCC_AHBLPENR_GPIOALPEN_Msk (0x1U << RCC_AHBLPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 4530 #define RCC_AHBLPENR_GPIOALPEN RCC_AHBLPENR_GPIOALPEN_Msk /*!< GPIO port A clock enabled in sleep mode */
<> 148:21d94c44109e 4531 #define RCC_AHBLPENR_GPIOBLPEN_Pos (1U)
<> 148:21d94c44109e 4532 #define RCC_AHBLPENR_GPIOBLPEN_Msk (0x1U << RCC_AHBLPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 4533 #define RCC_AHBLPENR_GPIOBLPEN RCC_AHBLPENR_GPIOBLPEN_Msk /*!< GPIO port B clock enabled in sleep mode */
<> 148:21d94c44109e 4534 #define RCC_AHBLPENR_GPIOCLPEN_Pos (2U)
<> 148:21d94c44109e 4535 #define RCC_AHBLPENR_GPIOCLPEN_Msk (0x1U << RCC_AHBLPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 4536 #define RCC_AHBLPENR_GPIOCLPEN RCC_AHBLPENR_GPIOCLPEN_Msk /*!< GPIO port C clock enabled in sleep mode */
<> 148:21d94c44109e 4537 #define RCC_AHBLPENR_GPIODLPEN_Pos (3U)
<> 148:21d94c44109e 4538 #define RCC_AHBLPENR_GPIODLPEN_Msk (0x1U << RCC_AHBLPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 4539 #define RCC_AHBLPENR_GPIODLPEN RCC_AHBLPENR_GPIODLPEN_Msk /*!< GPIO port D clock enabled in sleep mode */
<> 148:21d94c44109e 4540 #define RCC_AHBLPENR_GPIOELPEN_Pos (4U)
<> 148:21d94c44109e 4541 #define RCC_AHBLPENR_GPIOELPEN_Msk (0x1U << RCC_AHBLPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 4542 #define RCC_AHBLPENR_GPIOELPEN RCC_AHBLPENR_GPIOELPEN_Msk /*!< GPIO port E clock enabled in sleep mode */
<> 148:21d94c44109e 4543 #define RCC_AHBLPENR_GPIOHLPEN_Pos (5U)
<> 148:21d94c44109e 4544 #define RCC_AHBLPENR_GPIOHLPEN_Msk (0x1U << RCC_AHBLPENR_GPIOHLPEN_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 4545 #define RCC_AHBLPENR_GPIOHLPEN RCC_AHBLPENR_GPIOHLPEN_Msk /*!< GPIO port H clock enabled in sleep mode */
<> 148:21d94c44109e 4546 #define RCC_AHBLPENR_CRCLPEN_Pos (12U)
<> 148:21d94c44109e 4547 #define RCC_AHBLPENR_CRCLPEN_Msk (0x1U << RCC_AHBLPENR_CRCLPEN_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 4548 #define RCC_AHBLPENR_CRCLPEN RCC_AHBLPENR_CRCLPEN_Msk /*!< CRC clock enabled in sleep mode */
<> 148:21d94c44109e 4549 #define RCC_AHBLPENR_FLITFLPEN_Pos (15U)
<> 148:21d94c44109e 4550 #define RCC_AHBLPENR_FLITFLPEN_Msk (0x1U << RCC_AHBLPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 4551 #define RCC_AHBLPENR_FLITFLPEN RCC_AHBLPENR_FLITFLPEN_Msk /*!< Flash Interface clock enabled in sleep mode
<> 148:21d94c44109e 4552 (has effect only when the Flash memory is
<> 148:21d94c44109e 4553 in power down mode) */
<> 148:21d94c44109e 4554 #define RCC_AHBLPENR_SRAMLPEN_Pos (16U)
<> 148:21d94c44109e 4555 #define RCC_AHBLPENR_SRAMLPEN_Msk (0x1U << RCC_AHBLPENR_SRAMLPEN_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 4556 #define RCC_AHBLPENR_SRAMLPEN RCC_AHBLPENR_SRAMLPEN_Msk /*!< SRAM clock enabled in sleep mode */
<> 148:21d94c44109e 4557 #define RCC_AHBLPENR_DMA1LPEN_Pos (24U)
<> 148:21d94c44109e 4558 #define RCC_AHBLPENR_DMA1LPEN_Msk (0x1U << RCC_AHBLPENR_DMA1LPEN_Pos) /*!< 0x01000000 */
<> 148:21d94c44109e 4559 #define RCC_AHBLPENR_DMA1LPEN RCC_AHBLPENR_DMA1LPEN_Msk /*!< DMA1 clock enabled in sleep mode */
<> 148:21d94c44109e 4560 #define RCC_AHBLPENR_DMA2LPEN_Pos (25U)
<> 148:21d94c44109e 4561 #define RCC_AHBLPENR_DMA2LPEN_Msk (0x1U << RCC_AHBLPENR_DMA2LPEN_Pos) /*!< 0x02000000 */
<> 148:21d94c44109e 4562 #define RCC_AHBLPENR_DMA2LPEN RCC_AHBLPENR_DMA2LPEN_Msk /*!< DMA2 clock enabled in sleep mode */
<> 148:21d94c44109e 4563
<> 148:21d94c44109e 4564 /****************** Bit definition for RCC_APB2LPENR register ***************/
<> 148:21d94c44109e 4565 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (0U)
<> 148:21d94c44109e 4566 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 4567 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk /*!< System Configuration SYSCFG clock enabled in sleep mode */
<> 148:21d94c44109e 4568 #define RCC_APB2LPENR_TIM9LPEN_Pos (2U)
<> 148:21d94c44109e 4569 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 4570 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk /*!< TIM9 interface clock enabled in sleep mode */
<> 148:21d94c44109e 4571 #define RCC_APB2LPENR_TIM10LPEN_Pos (3U)
<> 148:21d94c44109e 4572 #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 4573 #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk /*!< TIM10 interface clock enabled in sleep mode */
<> 148:21d94c44109e 4574 #define RCC_APB2LPENR_TIM11LPEN_Pos (4U)
<> 148:21d94c44109e 4575 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 4576 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk /*!< TIM11 Timer clock enabled in sleep mode */
<> 148:21d94c44109e 4577 #define RCC_APB2LPENR_ADC1LPEN_Pos (9U)
<> 148:21d94c44109e 4578 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 4579 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk /*!< ADC1 clock enabled in sleep mode */
<> 148:21d94c44109e 4580 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
<> 148:21d94c44109e 4581 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 4582 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk /*!< SPI1 clock enabled in sleep mode */
<> 148:21d94c44109e 4583 #define RCC_APB2LPENR_USART1LPEN_Pos (14U)
<> 148:21d94c44109e 4584 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 4585 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk /*!< USART1 clock enabled in sleep mode */
<> 148:21d94c44109e 4586
<> 148:21d94c44109e 4587 /***************** Bit definition for RCC_APB1LPENR register ****************/
<> 148:21d94c44109e 4588 #define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
<> 148:21d94c44109e 4589 #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 4590 #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk /*!< Timer 2 clock enabled in sleep mode */
<> 148:21d94c44109e 4591 #define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
<> 148:21d94c44109e 4592 #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 4593 #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk /*!< Timer 3 clock enabled in sleep mode */
<> 148:21d94c44109e 4594 #define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
<> 148:21d94c44109e 4595 #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 4596 #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk /*!< Timer 4 clock enabled in sleep mode */
<> 148:21d94c44109e 4597 #define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
<> 148:21d94c44109e 4598 #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 4599 #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk /*!< Timer 5 clock enabled in sleep mode */
<> 148:21d94c44109e 4600 #define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
<> 148:21d94c44109e 4601 #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 4602 #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk /*!< Timer 6 clock enabled in sleep mode */
<> 148:21d94c44109e 4603 #define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
<> 148:21d94c44109e 4604 #define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 4605 #define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk /*!< Timer 7 clock enabled in sleep mode */
<> 148:21d94c44109e 4606 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
<> 148:21d94c44109e 4607 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 4608 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk /*!< Window Watchdog clock enabled in sleep mode */
<> 148:21d94c44109e 4609 #define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
<> 148:21d94c44109e 4610 #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 4611 #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk /*!< SPI 2 clock enabled in sleep mode */
<> 148:21d94c44109e 4612 #define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
<> 148:21d94c44109e 4613 #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 4614 #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk /*!< SPI 3 clock enabled in sleep mode */
<> 148:21d94c44109e 4615 #define RCC_APB1LPENR_USART2LPEN_Pos (17U)
<> 148:21d94c44109e 4616 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 4617 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk /*!< USART 2 clock enabled in sleep mode */
<> 148:21d94c44109e 4618 #define RCC_APB1LPENR_USART3LPEN_Pos (18U)
<> 148:21d94c44109e 4619 #define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 4620 #define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk /*!< USART 3 clock enabled in sleep mode */
<> 148:21d94c44109e 4621 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
<> 148:21d94c44109e 4622 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 4623 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk /*!< I2C 1 clock enabled in sleep mode */
<> 148:21d94c44109e 4624 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
<> 148:21d94c44109e 4625 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 4626 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk /*!< I2C 2 clock enabled in sleep mode */
<> 148:21d94c44109e 4627 #define RCC_APB1LPENR_USBLPEN_Pos (23U)
<> 148:21d94c44109e 4628 #define RCC_APB1LPENR_USBLPEN_Msk (0x1U << RCC_APB1LPENR_USBLPEN_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 4629 #define RCC_APB1LPENR_USBLPEN RCC_APB1LPENR_USBLPEN_Msk /*!< USB clock enabled in sleep mode */
<> 148:21d94c44109e 4630 #define RCC_APB1LPENR_PWRLPEN_Pos (28U)
<> 148:21d94c44109e 4631 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
<> 148:21d94c44109e 4632 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk /*!< Power interface clock enabled in sleep mode */
<> 148:21d94c44109e 4633 #define RCC_APB1LPENR_DACLPEN_Pos (29U)
<> 148:21d94c44109e 4634 #define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
<> 148:21d94c44109e 4635 #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk /*!< DAC interface clock enabled in sleep mode */
<> 148:21d94c44109e 4636 #define RCC_APB1LPENR_COMPLPEN_Pos (31U)
<> 148:21d94c44109e 4637 #define RCC_APB1LPENR_COMPLPEN_Msk (0x1U << RCC_APB1LPENR_COMPLPEN_Pos) /*!< 0x80000000 */
<> 148:21d94c44109e 4638 #define RCC_APB1LPENR_COMPLPEN RCC_APB1LPENR_COMPLPEN_Msk /*!< Comparator interface clock enabled in sleep mode*/
<> 148:21d94c44109e 4639
<> 148:21d94c44109e 4640 /******************* Bit definition for RCC_CSR register ********************/
<> 148:21d94c44109e 4641 #define RCC_CSR_LSION_Pos (0U)
<> 148:21d94c44109e 4642 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 4643 #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
<> 148:21d94c44109e 4644 #define RCC_CSR_LSIRDY_Pos (1U)
<> 148:21d94c44109e 4645 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 4646 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
<> 148:21d94c44109e 4647
<> 148:21d94c44109e 4648 #define RCC_CSR_LSEON_Pos (8U)
<> 148:21d94c44109e 4649 #define RCC_CSR_LSEON_Msk (0x1U << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 4650 #define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */
<> 148:21d94c44109e 4651 #define RCC_CSR_LSERDY_Pos (9U)
<> 148:21d94c44109e 4652 #define RCC_CSR_LSERDY_Msk (0x1U << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 4653 #define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
<> 148:21d94c44109e 4654 #define RCC_CSR_LSEBYP_Pos (10U)
<> 148:21d94c44109e 4655 #define RCC_CSR_LSEBYP_Msk (0x1U << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 4656 #define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
<> 148:21d94c44109e 4657
<> 148:21d94c44109e 4658 #define RCC_CSR_LSECSSON_Pos (11U)
<> 148:21d94c44109e 4659 #define RCC_CSR_LSECSSON_Msk (0x1U << RCC_CSR_LSECSSON_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 4660 #define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */
<> 148:21d94c44109e 4661 #define RCC_CSR_LSECSSD_Pos (12U)
<> 148:21d94c44109e 4662 #define RCC_CSR_LSECSSD_Msk (0x1U << RCC_CSR_LSECSSD_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 4663 #define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */
<> 148:21d94c44109e 4664
<> 148:21d94c44109e 4665 #define RCC_CSR_RTCSEL_Pos (16U)
<> 148:21d94c44109e 4666 #define RCC_CSR_RTCSEL_Msk (0x3U << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */
<> 148:21d94c44109e 4667 #define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
<> 148:21d94c44109e 4668 #define RCC_CSR_RTCSEL_0 (0x1U << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 4669 #define RCC_CSR_RTCSEL_1 (0x2U << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 4670
<> 148:21d94c44109e 4671 /*!< RTC congiguration */
<> 148:21d94c44109e 4672 #define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
<> 148:21d94c44109e 4673 #define RCC_CSR_RTCSEL_LSE_Pos (16U)
<> 148:21d94c44109e 4674 #define RCC_CSR_RTCSEL_LSE_Msk (0x1U << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 4675 #define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */
<> 148:21d94c44109e 4676 #define RCC_CSR_RTCSEL_LSI_Pos (17U)
<> 148:21d94c44109e 4677 #define RCC_CSR_RTCSEL_LSI_Msk (0x1U << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 4678 #define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */
<> 148:21d94c44109e 4679 #define RCC_CSR_RTCSEL_HSE_Pos (16U)
<> 148:21d94c44109e 4680 #define RCC_CSR_RTCSEL_HSE_Msk (0x3U << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */
<> 148:21d94c44109e 4681 #define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
<> 148:21d94c44109e 4682
<> 148:21d94c44109e 4683 #define RCC_CSR_RTCEN_Pos (22U)
<> 148:21d94c44109e 4684 #define RCC_CSR_RTCEN_Msk (0x1U << RCC_CSR_RTCEN_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 4685 #define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */
<> 148:21d94c44109e 4686 #define RCC_CSR_RTCRST_Pos (23U)
<> 148:21d94c44109e 4687 #define RCC_CSR_RTCRST_Msk (0x1U << RCC_CSR_RTCRST_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 4688 #define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC reset */
<> 148:21d94c44109e 4689
<> 148:21d94c44109e 4690 #define RCC_CSR_RMVF_Pos (24U)
<> 148:21d94c44109e 4691 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
<> 148:21d94c44109e 4692 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
<> 148:21d94c44109e 4693 #define RCC_CSR_OBLRSTF_Pos (25U)
<> 148:21d94c44109e 4694 #define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
<> 148:21d94c44109e 4695 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< Option Bytes Loader reset flag */
<> 148:21d94c44109e 4696 #define RCC_CSR_PINRSTF_Pos (26U)
<> 148:21d94c44109e 4697 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
<> 148:21d94c44109e 4698 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
<> 148:21d94c44109e 4699 #define RCC_CSR_PORRSTF_Pos (27U)
<> 148:21d94c44109e 4700 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
<> 148:21d94c44109e 4701 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
<> 148:21d94c44109e 4702 #define RCC_CSR_SFTRSTF_Pos (28U)
<> 148:21d94c44109e 4703 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
<> 148:21d94c44109e 4704 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
<> 148:21d94c44109e 4705 #define RCC_CSR_IWDGRSTF_Pos (29U)
<> 148:21d94c44109e 4706 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
<> 148:21d94c44109e 4707 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
<> 148:21d94c44109e 4708 #define RCC_CSR_WWDGRSTF_Pos (30U)
<> 148:21d94c44109e 4709 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
<> 148:21d94c44109e 4710 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
<> 148:21d94c44109e 4711 #define RCC_CSR_LPWRRSTF_Pos (31U)
<> 148:21d94c44109e 4712 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
<> 148:21d94c44109e 4713 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
<> 148:21d94c44109e 4714
<> 148:21d94c44109e 4715 /******************************************************************************/
<> 148:21d94c44109e 4716 /* */
<> 148:21d94c44109e 4717 /* Real-Time Clock (RTC) */
<> 148:21d94c44109e 4718 /* */
<> 148:21d94c44109e 4719 /******************************************************************************/
<> 148:21d94c44109e 4720 /*
<> 148:21d94c44109e 4721 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
<> 148:21d94c44109e 4722 */
<> 148:21d94c44109e 4723 #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
<> 148:21d94c44109e 4724 #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
<> 148:21d94c44109e 4725 #define RTC_TAMPER3_SUPPORT /*!< TAMPER 3 feature support */
<> 148:21d94c44109e 4726 #define RTC_BACKUP_SUPPORT /*!< BACKUP register feature support */
<> 148:21d94c44109e 4727 #define RTC_WAKEUP_SUPPORT /*!< WAKEUP feature support */
<> 148:21d94c44109e 4728 #define RTC_SMOOTHCALIB_SUPPORT /*!< Smooth digital calibration feature support */
<> 148:21d94c44109e 4729 #define RTC_SUBSECOND_SUPPORT /*!< Sub-second feature support */
<> 148:21d94c44109e 4730
<> 148:21d94c44109e 4731 /******************** Bits definition for RTC_TR register *******************/
<> 148:21d94c44109e 4732 #define RTC_TR_PM_Pos (22U)
<> 148:21d94c44109e 4733 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 4734 #define RTC_TR_PM RTC_TR_PM_Msk
<> 148:21d94c44109e 4735 #define RTC_TR_HT_Pos (20U)
<> 148:21d94c44109e 4736 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
<> 148:21d94c44109e 4737 #define RTC_TR_HT RTC_TR_HT_Msk
<> 148:21d94c44109e 4738 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 4739 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 4740 #define RTC_TR_HU_Pos (16U)
<> 148:21d94c44109e 4741 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
<> 148:21d94c44109e 4742 #define RTC_TR_HU RTC_TR_HU_Msk
<> 148:21d94c44109e 4743 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 4744 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 4745 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 4746 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 4747 #define RTC_TR_MNT_Pos (12U)
<> 148:21d94c44109e 4748 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
<> 148:21d94c44109e 4749 #define RTC_TR_MNT RTC_TR_MNT_Msk
<> 148:21d94c44109e 4750 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 4751 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 4752 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 4753 #define RTC_TR_MNU_Pos (8U)
<> 148:21d94c44109e 4754 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
<> 148:21d94c44109e 4755 #define RTC_TR_MNU RTC_TR_MNU_Msk
<> 148:21d94c44109e 4756 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 4757 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 4758 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 4759 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 4760 #define RTC_TR_ST_Pos (4U)
<> 148:21d94c44109e 4761 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
<> 148:21d94c44109e 4762 #define RTC_TR_ST RTC_TR_ST_Msk
<> 148:21d94c44109e 4763 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 4764 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 4765 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 4766 #define RTC_TR_SU_Pos (0U)
<> 148:21d94c44109e 4767 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
<> 148:21d94c44109e 4768 #define RTC_TR_SU RTC_TR_SU_Msk
<> 148:21d94c44109e 4769 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 4770 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 4771 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 4772 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 4773
<> 148:21d94c44109e 4774 /******************** Bits definition for RTC_DR register *******************/
<> 148:21d94c44109e 4775 #define RTC_DR_YT_Pos (20U)
<> 148:21d94c44109e 4776 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
<> 148:21d94c44109e 4777 #define RTC_DR_YT RTC_DR_YT_Msk
<> 148:21d94c44109e 4778 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 4779 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 4780 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 4781 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 4782 #define RTC_DR_YU_Pos (16U)
<> 148:21d94c44109e 4783 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
<> 148:21d94c44109e 4784 #define RTC_DR_YU RTC_DR_YU_Msk
<> 148:21d94c44109e 4785 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 4786 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 4787 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 4788 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 4789 #define RTC_DR_WDU_Pos (13U)
<> 148:21d94c44109e 4790 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
<> 148:21d94c44109e 4791 #define RTC_DR_WDU RTC_DR_WDU_Msk
<> 148:21d94c44109e 4792 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 4793 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 4794 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 4795 #define RTC_DR_MT_Pos (12U)
<> 148:21d94c44109e 4796 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 4797 #define RTC_DR_MT RTC_DR_MT_Msk
<> 148:21d94c44109e 4798 #define RTC_DR_MU_Pos (8U)
<> 148:21d94c44109e 4799 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
<> 148:21d94c44109e 4800 #define RTC_DR_MU RTC_DR_MU_Msk
<> 148:21d94c44109e 4801 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 4802 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 4803 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 4804 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 4805 #define RTC_DR_DT_Pos (4U)
<> 148:21d94c44109e 4806 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
<> 148:21d94c44109e 4807 #define RTC_DR_DT RTC_DR_DT_Msk
<> 148:21d94c44109e 4808 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 4809 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 4810 #define RTC_DR_DU_Pos (0U)
<> 148:21d94c44109e 4811 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
<> 148:21d94c44109e 4812 #define RTC_DR_DU RTC_DR_DU_Msk
<> 148:21d94c44109e 4813 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 4814 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 4815 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 4816 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 4817
<> 148:21d94c44109e 4818 /******************** Bits definition for RTC_CR register *******************/
<> 148:21d94c44109e 4819 #define RTC_CR_COE_Pos (23U)
<> 148:21d94c44109e 4820 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 4821 #define RTC_CR_COE RTC_CR_COE_Msk
<> 148:21d94c44109e 4822 #define RTC_CR_OSEL_Pos (21U)
<> 148:21d94c44109e 4823 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
<> 148:21d94c44109e 4824 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
<> 148:21d94c44109e 4825 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 4826 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 4827 #define RTC_CR_POL_Pos (20U)
<> 148:21d94c44109e 4828 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 4829 #define RTC_CR_POL RTC_CR_POL_Msk
<> 148:21d94c44109e 4830 #define RTC_CR_COSEL_Pos (19U)
<> 148:21d94c44109e 4831 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 4832 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
<> 148:21d94c44109e 4833 #define RTC_CR_BCK_Pos (18U)
<> 148:21d94c44109e 4834 #define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 4835 #define RTC_CR_BCK RTC_CR_BCK_Msk
<> 148:21d94c44109e 4836 #define RTC_CR_SUB1H_Pos (17U)
<> 148:21d94c44109e 4837 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 4838 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
<> 148:21d94c44109e 4839 #define RTC_CR_ADD1H_Pos (16U)
<> 148:21d94c44109e 4840 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 4841 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
<> 148:21d94c44109e 4842 #define RTC_CR_TSIE_Pos (15U)
<> 148:21d94c44109e 4843 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 4844 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
<> 148:21d94c44109e 4845 #define RTC_CR_WUTIE_Pos (14U)
<> 148:21d94c44109e 4846 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 4847 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
<> 148:21d94c44109e 4848 #define RTC_CR_ALRBIE_Pos (13U)
<> 148:21d94c44109e 4849 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 4850 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
<> 148:21d94c44109e 4851 #define RTC_CR_ALRAIE_Pos (12U)
<> 148:21d94c44109e 4852 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 4853 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
<> 148:21d94c44109e 4854 #define RTC_CR_TSE_Pos (11U)
<> 148:21d94c44109e 4855 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 4856 #define RTC_CR_TSE RTC_CR_TSE_Msk
<> 148:21d94c44109e 4857 #define RTC_CR_WUTE_Pos (10U)
<> 148:21d94c44109e 4858 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 4859 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
<> 148:21d94c44109e 4860 #define RTC_CR_ALRBE_Pos (9U)
<> 148:21d94c44109e 4861 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 4862 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
<> 148:21d94c44109e 4863 #define RTC_CR_ALRAE_Pos (8U)
<> 148:21d94c44109e 4864 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 4865 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
<> 148:21d94c44109e 4866 #define RTC_CR_DCE_Pos (7U)
<> 148:21d94c44109e 4867 #define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 4868 #define RTC_CR_DCE RTC_CR_DCE_Msk
<> 148:21d94c44109e 4869 #define RTC_CR_FMT_Pos (6U)
<> 148:21d94c44109e 4870 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 4871 #define RTC_CR_FMT RTC_CR_FMT_Msk
<> 148:21d94c44109e 4872 #define RTC_CR_BYPSHAD_Pos (5U)
<> 148:21d94c44109e 4873 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 4874 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
<> 148:21d94c44109e 4875 #define RTC_CR_REFCKON_Pos (4U)
<> 148:21d94c44109e 4876 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 4877 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
<> 148:21d94c44109e 4878 #define RTC_CR_TSEDGE_Pos (3U)
<> 148:21d94c44109e 4879 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 4880 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
<> 148:21d94c44109e 4881 #define RTC_CR_WUCKSEL_Pos (0U)
<> 148:21d94c44109e 4882 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
<> 148:21d94c44109e 4883 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
<> 148:21d94c44109e 4884 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 4885 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 4886 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 4887
<> 148:21d94c44109e 4888 /******************** Bits definition for RTC_ISR register ******************/
<> 148:21d94c44109e 4889 #define RTC_ISR_RECALPF_Pos (16U)
<> 148:21d94c44109e 4890 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 4891 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
<> 148:21d94c44109e 4892 #define RTC_ISR_TAMP3F_Pos (15U)
<> 148:21d94c44109e 4893 #define RTC_ISR_TAMP3F_Msk (0x1U << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 4894 #define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
<> 148:21d94c44109e 4895 #define RTC_ISR_TAMP2F_Pos (14U)
<> 148:21d94c44109e 4896 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 4897 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
<> 148:21d94c44109e 4898 #define RTC_ISR_TAMP1F_Pos (13U)
<> 148:21d94c44109e 4899 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 4900 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
<> 148:21d94c44109e 4901 #define RTC_ISR_TSOVF_Pos (12U)
<> 148:21d94c44109e 4902 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 4903 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
<> 148:21d94c44109e 4904 #define RTC_ISR_TSF_Pos (11U)
<> 148:21d94c44109e 4905 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 4906 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
<> 148:21d94c44109e 4907 #define RTC_ISR_WUTF_Pos (10U)
<> 148:21d94c44109e 4908 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 4909 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
<> 148:21d94c44109e 4910 #define RTC_ISR_ALRBF_Pos (9U)
<> 148:21d94c44109e 4911 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 4912 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
<> 148:21d94c44109e 4913 #define RTC_ISR_ALRAF_Pos (8U)
<> 148:21d94c44109e 4914 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 4915 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
<> 148:21d94c44109e 4916 #define RTC_ISR_INIT_Pos (7U)
<> 148:21d94c44109e 4917 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 4918 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
<> 148:21d94c44109e 4919 #define RTC_ISR_INITF_Pos (6U)
<> 148:21d94c44109e 4920 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 4921 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
<> 148:21d94c44109e 4922 #define RTC_ISR_RSF_Pos (5U)
<> 148:21d94c44109e 4923 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 4924 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
<> 148:21d94c44109e 4925 #define RTC_ISR_INITS_Pos (4U)
<> 148:21d94c44109e 4926 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 4927 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
<> 148:21d94c44109e 4928 #define RTC_ISR_SHPF_Pos (3U)
<> 148:21d94c44109e 4929 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 4930 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
<> 148:21d94c44109e 4931 #define RTC_ISR_WUTWF_Pos (2U)
<> 148:21d94c44109e 4932 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 4933 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
<> 148:21d94c44109e 4934 #define RTC_ISR_ALRBWF_Pos (1U)
<> 148:21d94c44109e 4935 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 4936 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
<> 148:21d94c44109e 4937 #define RTC_ISR_ALRAWF_Pos (0U)
<> 148:21d94c44109e 4938 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 4939 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
<> 148:21d94c44109e 4940
<> 148:21d94c44109e 4941 /******************** Bits definition for RTC_PRER register *****************/
<> 148:21d94c44109e 4942 #define RTC_PRER_PREDIV_A_Pos (16U)
<> 148:21d94c44109e 4943 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
<> 148:21d94c44109e 4944 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
<> 148:21d94c44109e 4945 #define RTC_PRER_PREDIV_S_Pos (0U)
<> 148:21d94c44109e 4946 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
<> 148:21d94c44109e 4947 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
<> 148:21d94c44109e 4948
<> 148:21d94c44109e 4949 /******************** Bits definition for RTC_WUTR register *****************/
<> 148:21d94c44109e 4950 #define RTC_WUTR_WUT_Pos (0U)
<> 148:21d94c44109e 4951 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 4952 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
<> 148:21d94c44109e 4953
<> 148:21d94c44109e 4954 /******************** Bits definition for RTC_CALIBR register ***************/
<> 148:21d94c44109e 4955 #define RTC_CALIBR_DCS_Pos (7U)
<> 148:21d94c44109e 4956 #define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 4957 #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
<> 148:21d94c44109e 4958 #define RTC_CALIBR_DC_Pos (0U)
<> 148:21d94c44109e 4959 #define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
<> 148:21d94c44109e 4960 #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
<> 148:21d94c44109e 4961
<> 148:21d94c44109e 4962 /******************** Bits definition for RTC_ALRMAR register ***************/
<> 148:21d94c44109e 4963 #define RTC_ALRMAR_MSK4_Pos (31U)
<> 148:21d94c44109e 4964 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
<> 148:21d94c44109e 4965 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
<> 148:21d94c44109e 4966 #define RTC_ALRMAR_WDSEL_Pos (30U)
<> 148:21d94c44109e 4967 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
<> 148:21d94c44109e 4968 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
<> 148:21d94c44109e 4969 #define RTC_ALRMAR_DT_Pos (28U)
<> 148:21d94c44109e 4970 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
<> 148:21d94c44109e 4971 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
<> 148:21d94c44109e 4972 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
<> 148:21d94c44109e 4973 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
<> 148:21d94c44109e 4974 #define RTC_ALRMAR_DU_Pos (24U)
<> 148:21d94c44109e 4975 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
<> 148:21d94c44109e 4976 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
<> 148:21d94c44109e 4977 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
<> 148:21d94c44109e 4978 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
<> 148:21d94c44109e 4979 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
<> 148:21d94c44109e 4980 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
<> 148:21d94c44109e 4981 #define RTC_ALRMAR_MSK3_Pos (23U)
<> 148:21d94c44109e 4982 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 4983 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
<> 148:21d94c44109e 4984 #define RTC_ALRMAR_PM_Pos (22U)
<> 148:21d94c44109e 4985 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 4986 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
<> 148:21d94c44109e 4987 #define RTC_ALRMAR_HT_Pos (20U)
<> 148:21d94c44109e 4988 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
<> 148:21d94c44109e 4989 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
<> 148:21d94c44109e 4990 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 4991 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 4992 #define RTC_ALRMAR_HU_Pos (16U)
<> 148:21d94c44109e 4993 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
<> 148:21d94c44109e 4994 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
<> 148:21d94c44109e 4995 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 4996 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 4997 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 4998 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 4999 #define RTC_ALRMAR_MSK2_Pos (15U)
<> 148:21d94c44109e 5000 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 5001 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
<> 148:21d94c44109e 5002 #define RTC_ALRMAR_MNT_Pos (12U)
<> 148:21d94c44109e 5003 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
<> 148:21d94c44109e 5004 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
<> 148:21d94c44109e 5005 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 5006 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 5007 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 5008 #define RTC_ALRMAR_MNU_Pos (8U)
<> 148:21d94c44109e 5009 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
<> 148:21d94c44109e 5010 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
<> 148:21d94c44109e 5011 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 5012 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 5013 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 5014 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 5015 #define RTC_ALRMAR_MSK1_Pos (7U)
<> 148:21d94c44109e 5016 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 5017 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
<> 148:21d94c44109e 5018 #define RTC_ALRMAR_ST_Pos (4U)
<> 148:21d94c44109e 5019 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
<> 148:21d94c44109e 5020 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
<> 148:21d94c44109e 5021 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 5022 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 5023 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 5024 #define RTC_ALRMAR_SU_Pos (0U)
<> 148:21d94c44109e 5025 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
<> 148:21d94c44109e 5026 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
<> 148:21d94c44109e 5027 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 5028 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 5029 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 5030 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 5031
<> 148:21d94c44109e 5032 /******************** Bits definition for RTC_ALRMBR register ***************/
<> 148:21d94c44109e 5033 #define RTC_ALRMBR_MSK4_Pos (31U)
<> 148:21d94c44109e 5034 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
<> 148:21d94c44109e 5035 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
<> 148:21d94c44109e 5036 #define RTC_ALRMBR_WDSEL_Pos (30U)
<> 148:21d94c44109e 5037 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
<> 148:21d94c44109e 5038 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
<> 148:21d94c44109e 5039 #define RTC_ALRMBR_DT_Pos (28U)
<> 148:21d94c44109e 5040 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
<> 148:21d94c44109e 5041 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
<> 148:21d94c44109e 5042 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
<> 148:21d94c44109e 5043 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
<> 148:21d94c44109e 5044 #define RTC_ALRMBR_DU_Pos (24U)
<> 148:21d94c44109e 5045 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
<> 148:21d94c44109e 5046 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
<> 148:21d94c44109e 5047 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
<> 148:21d94c44109e 5048 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
<> 148:21d94c44109e 5049 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
<> 148:21d94c44109e 5050 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
<> 148:21d94c44109e 5051 #define RTC_ALRMBR_MSK3_Pos (23U)
<> 148:21d94c44109e 5052 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 5053 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
<> 148:21d94c44109e 5054 #define RTC_ALRMBR_PM_Pos (22U)
<> 148:21d94c44109e 5055 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 5056 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
<> 148:21d94c44109e 5057 #define RTC_ALRMBR_HT_Pos (20U)
<> 148:21d94c44109e 5058 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
<> 148:21d94c44109e 5059 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
<> 148:21d94c44109e 5060 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 5061 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 5062 #define RTC_ALRMBR_HU_Pos (16U)
<> 148:21d94c44109e 5063 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
<> 148:21d94c44109e 5064 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
<> 148:21d94c44109e 5065 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 5066 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 5067 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 5068 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 5069 #define RTC_ALRMBR_MSK2_Pos (15U)
<> 148:21d94c44109e 5070 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 5071 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
<> 148:21d94c44109e 5072 #define RTC_ALRMBR_MNT_Pos (12U)
<> 148:21d94c44109e 5073 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
<> 148:21d94c44109e 5074 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
<> 148:21d94c44109e 5075 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 5076 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 5077 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 5078 #define RTC_ALRMBR_MNU_Pos (8U)
<> 148:21d94c44109e 5079 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
<> 148:21d94c44109e 5080 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
<> 148:21d94c44109e 5081 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 5082 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 5083 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 5084 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 5085 #define RTC_ALRMBR_MSK1_Pos (7U)
<> 148:21d94c44109e 5086 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 5087 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
<> 148:21d94c44109e 5088 #define RTC_ALRMBR_ST_Pos (4U)
<> 148:21d94c44109e 5089 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
<> 148:21d94c44109e 5090 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
<> 148:21d94c44109e 5091 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 5092 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 5093 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 5094 #define RTC_ALRMBR_SU_Pos (0U)
<> 148:21d94c44109e 5095 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
<> 148:21d94c44109e 5096 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
<> 148:21d94c44109e 5097 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 5098 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 5099 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 5100 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 5101
<> 148:21d94c44109e 5102 /******************** Bits definition for RTC_WPR register ******************/
<> 148:21d94c44109e 5103 #define RTC_WPR_KEY_Pos (0U)
<> 148:21d94c44109e 5104 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
<> 148:21d94c44109e 5105 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
<> 148:21d94c44109e 5106
<> 148:21d94c44109e 5107 /******************** Bits definition for RTC_SSR register ******************/
<> 148:21d94c44109e 5108 #define RTC_SSR_SS_Pos (0U)
<> 148:21d94c44109e 5109 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 5110 #define RTC_SSR_SS RTC_SSR_SS_Msk
<> 148:21d94c44109e 5111
<> 148:21d94c44109e 5112 /******************** Bits definition for RTC_SHIFTR register ***************/
<> 148:21d94c44109e 5113 #define RTC_SHIFTR_SUBFS_Pos (0U)
<> 148:21d94c44109e 5114 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
<> 148:21d94c44109e 5115 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
<> 148:21d94c44109e 5116 #define RTC_SHIFTR_ADD1S_Pos (31U)
<> 148:21d94c44109e 5117 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
<> 148:21d94c44109e 5118 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
<> 148:21d94c44109e 5119
<> 148:21d94c44109e 5120 /******************** Bits definition for RTC_TSTR register *****************/
<> 148:21d94c44109e 5121 #define RTC_TSTR_PM_Pos (22U)
<> 148:21d94c44109e 5122 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 5123 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
<> 148:21d94c44109e 5124 #define RTC_TSTR_HT_Pos (20U)
<> 148:21d94c44109e 5125 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
<> 148:21d94c44109e 5126 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
<> 148:21d94c44109e 5127 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 5128 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 5129 #define RTC_TSTR_HU_Pos (16U)
<> 148:21d94c44109e 5130 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
<> 148:21d94c44109e 5131 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
<> 148:21d94c44109e 5132 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 5133 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 5134 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 5135 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 5136 #define RTC_TSTR_MNT_Pos (12U)
<> 148:21d94c44109e 5137 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
<> 148:21d94c44109e 5138 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
<> 148:21d94c44109e 5139 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 5140 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 5141 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 5142 #define RTC_TSTR_MNU_Pos (8U)
<> 148:21d94c44109e 5143 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
<> 148:21d94c44109e 5144 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
<> 148:21d94c44109e 5145 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 5146 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 5147 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 5148 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 5149 #define RTC_TSTR_ST_Pos (4U)
<> 148:21d94c44109e 5150 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
<> 148:21d94c44109e 5151 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
<> 148:21d94c44109e 5152 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 5153 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 5154 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 5155 #define RTC_TSTR_SU_Pos (0U)
<> 148:21d94c44109e 5156 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
<> 148:21d94c44109e 5157 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
<> 148:21d94c44109e 5158 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 5159 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 5160 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 5161 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 5162
<> 148:21d94c44109e 5163 /******************** Bits definition for RTC_TSDR register *****************/
<> 148:21d94c44109e 5164 #define RTC_TSDR_WDU_Pos (13U)
<> 148:21d94c44109e 5165 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
<> 148:21d94c44109e 5166 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
<> 148:21d94c44109e 5167 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 5168 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 5169 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 5170 #define RTC_TSDR_MT_Pos (12U)
<> 148:21d94c44109e 5171 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 5172 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
<> 148:21d94c44109e 5173 #define RTC_TSDR_MU_Pos (8U)
<> 148:21d94c44109e 5174 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
<> 148:21d94c44109e 5175 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
<> 148:21d94c44109e 5176 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 5177 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 5178 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 5179 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 5180 #define RTC_TSDR_DT_Pos (4U)
<> 148:21d94c44109e 5181 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
<> 148:21d94c44109e 5182 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
<> 148:21d94c44109e 5183 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 5184 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 5185 #define RTC_TSDR_DU_Pos (0U)
<> 148:21d94c44109e 5186 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
<> 148:21d94c44109e 5187 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
<> 148:21d94c44109e 5188 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 5189 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 5190 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 5191 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 5192
<> 148:21d94c44109e 5193 /******************** Bits definition for RTC_TSSSR register ****************/
<> 148:21d94c44109e 5194 #define RTC_TSSSR_SS_Pos (0U)
<> 148:21d94c44109e 5195 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 5196 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
<> 148:21d94c44109e 5197
<> 148:21d94c44109e 5198 /******************** Bits definition for RTC_CAL register *****************/
<> 148:21d94c44109e 5199 #define RTC_CALR_CALP_Pos (15U)
<> 148:21d94c44109e 5200 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 5201 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
<> 148:21d94c44109e 5202 #define RTC_CALR_CALW8_Pos (14U)
<> 148:21d94c44109e 5203 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 5204 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
<> 148:21d94c44109e 5205 #define RTC_CALR_CALW16_Pos (13U)
<> 148:21d94c44109e 5206 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 5207 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
<> 148:21d94c44109e 5208 #define RTC_CALR_CALM_Pos (0U)
<> 148:21d94c44109e 5209 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
<> 148:21d94c44109e 5210 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
<> 148:21d94c44109e 5211 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 5212 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 5213 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 5214 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 5215 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 5216 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 5217 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 5218 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 5219 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 5220
<> 148:21d94c44109e 5221 /******************** Bits definition for RTC_TAFCR register ****************/
<> 148:21d94c44109e 5222 #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
<> 148:21d94c44109e 5223 #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 5224 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
<> 148:21d94c44109e 5225 #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
<> 148:21d94c44109e 5226 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 5227 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
<> 148:21d94c44109e 5228 #define RTC_TAFCR_TAMPPRCH_Pos (13U)
<> 148:21d94c44109e 5229 #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
<> 148:21d94c44109e 5230 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
<> 148:21d94c44109e 5231 #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 5232 #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 5233 #define RTC_TAFCR_TAMPFLT_Pos (11U)
<> 148:21d94c44109e 5234 #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
<> 148:21d94c44109e 5235 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
<> 148:21d94c44109e 5236 #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 5237 #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 5238 #define RTC_TAFCR_TAMPFREQ_Pos (8U)
<> 148:21d94c44109e 5239 #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
<> 148:21d94c44109e 5240 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
<> 148:21d94c44109e 5241 #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 5242 #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 5243 #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 5244 #define RTC_TAFCR_TAMPTS_Pos (7U)
<> 148:21d94c44109e 5245 #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 5246 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
<> 148:21d94c44109e 5247 #define RTC_TAFCR_TAMP3TRG_Pos (6U)
<> 148:21d94c44109e 5248 #define RTC_TAFCR_TAMP3TRG_Msk (0x1U << RTC_TAFCR_TAMP3TRG_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 5249 #define RTC_TAFCR_TAMP3TRG RTC_TAFCR_TAMP3TRG_Msk
<> 148:21d94c44109e 5250 #define RTC_TAFCR_TAMP3E_Pos (5U)
<> 148:21d94c44109e 5251 #define RTC_TAFCR_TAMP3E_Msk (0x1U << RTC_TAFCR_TAMP3E_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 5252 #define RTC_TAFCR_TAMP3E RTC_TAFCR_TAMP3E_Msk
<> 148:21d94c44109e 5253 #define RTC_TAFCR_TAMP2TRG_Pos (4U)
<> 148:21d94c44109e 5254 #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 5255 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
<> 148:21d94c44109e 5256 #define RTC_TAFCR_TAMP2E_Pos (3U)
<> 148:21d94c44109e 5257 #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 5258 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
<> 148:21d94c44109e 5259 #define RTC_TAFCR_TAMPIE_Pos (2U)
<> 148:21d94c44109e 5260 #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 5261 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
<> 148:21d94c44109e 5262 #define RTC_TAFCR_TAMP1TRG_Pos (1U)
<> 148:21d94c44109e 5263 #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 5264 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
<> 148:21d94c44109e 5265 #define RTC_TAFCR_TAMP1E_Pos (0U)
<> 148:21d94c44109e 5266 #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 5267 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
<> 148:21d94c44109e 5268
<> 148:21d94c44109e 5269 /******************** Bits definition for RTC_ALRMASSR register *************/
<> 148:21d94c44109e 5270 #define RTC_ALRMASSR_MASKSS_Pos (24U)
<> 148:21d94c44109e 5271 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
<> 148:21d94c44109e 5272 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
<> 148:21d94c44109e 5273 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
<> 148:21d94c44109e 5274 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
<> 148:21d94c44109e 5275 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
<> 148:21d94c44109e 5276 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
<> 148:21d94c44109e 5277 #define RTC_ALRMASSR_SS_Pos (0U)
<> 148:21d94c44109e 5278 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
<> 148:21d94c44109e 5279 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
<> 148:21d94c44109e 5280
<> 148:21d94c44109e 5281 /******************** Bits definition for RTC_ALRMBSSR register *************/
<> 148:21d94c44109e 5282 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
<> 148:21d94c44109e 5283 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
<> 148:21d94c44109e 5284 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
<> 148:21d94c44109e 5285 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
<> 148:21d94c44109e 5286 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
<> 148:21d94c44109e 5287 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
<> 148:21d94c44109e 5288 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
<> 148:21d94c44109e 5289 #define RTC_ALRMBSSR_SS_Pos (0U)
<> 148:21d94c44109e 5290 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
<> 148:21d94c44109e 5291 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
<> 148:21d94c44109e 5292
<> 148:21d94c44109e 5293 /******************** Bits definition for RTC_BKP0R register ****************/
<> 148:21d94c44109e 5294 #define RTC_BKP0R_Pos (0U)
<> 148:21d94c44109e 5295 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 5296 #define RTC_BKP0R RTC_BKP0R_Msk
<> 148:21d94c44109e 5297
<> 148:21d94c44109e 5298 /******************** Bits definition for RTC_BKP1R register ****************/
<> 148:21d94c44109e 5299 #define RTC_BKP1R_Pos (0U)
<> 148:21d94c44109e 5300 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 5301 #define RTC_BKP1R RTC_BKP1R_Msk
<> 148:21d94c44109e 5302
<> 148:21d94c44109e 5303 /******************** Bits definition for RTC_BKP2R register ****************/
<> 148:21d94c44109e 5304 #define RTC_BKP2R_Pos (0U)
<> 148:21d94c44109e 5305 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 5306 #define RTC_BKP2R RTC_BKP2R_Msk
<> 148:21d94c44109e 5307
<> 148:21d94c44109e 5308 /******************** Bits definition for RTC_BKP3R register ****************/
<> 148:21d94c44109e 5309 #define RTC_BKP3R_Pos (0U)
<> 148:21d94c44109e 5310 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 5311 #define RTC_BKP3R RTC_BKP3R_Msk
<> 148:21d94c44109e 5312
<> 148:21d94c44109e 5313 /******************** Bits definition for RTC_BKP4R register ****************/
<> 148:21d94c44109e 5314 #define RTC_BKP4R_Pos (0U)
<> 148:21d94c44109e 5315 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 5316 #define RTC_BKP4R RTC_BKP4R_Msk
<> 148:21d94c44109e 5317
<> 148:21d94c44109e 5318 /******************** Bits definition for RTC_BKP5R register ****************/
<> 148:21d94c44109e 5319 #define RTC_BKP5R_Pos (0U)
<> 148:21d94c44109e 5320 #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 5321 #define RTC_BKP5R RTC_BKP5R_Msk
<> 148:21d94c44109e 5322
<> 148:21d94c44109e 5323 /******************** Bits definition for RTC_BKP6R register ****************/
<> 148:21d94c44109e 5324 #define RTC_BKP6R_Pos (0U)
<> 148:21d94c44109e 5325 #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 5326 #define RTC_BKP6R RTC_BKP6R_Msk
<> 148:21d94c44109e 5327
<> 148:21d94c44109e 5328 /******************** Bits definition for RTC_BKP7R register ****************/
<> 148:21d94c44109e 5329 #define RTC_BKP7R_Pos (0U)
<> 148:21d94c44109e 5330 #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 5331 #define RTC_BKP7R RTC_BKP7R_Msk
<> 148:21d94c44109e 5332
<> 148:21d94c44109e 5333 /******************** Bits definition for RTC_BKP8R register ****************/
<> 148:21d94c44109e 5334 #define RTC_BKP8R_Pos (0U)
<> 148:21d94c44109e 5335 #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 5336 #define RTC_BKP8R RTC_BKP8R_Msk
<> 148:21d94c44109e 5337
<> 148:21d94c44109e 5338 /******************** Bits definition for RTC_BKP9R register ****************/
<> 148:21d94c44109e 5339 #define RTC_BKP9R_Pos (0U)
<> 148:21d94c44109e 5340 #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 5341 #define RTC_BKP9R RTC_BKP9R_Msk
<> 148:21d94c44109e 5342
<> 148:21d94c44109e 5343 /******************** Bits definition for RTC_BKP10R register ***************/
<> 148:21d94c44109e 5344 #define RTC_BKP10R_Pos (0U)
<> 148:21d94c44109e 5345 #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 5346 #define RTC_BKP10R RTC_BKP10R_Msk
<> 148:21d94c44109e 5347
<> 148:21d94c44109e 5348 /******************** Bits definition for RTC_BKP11R register ***************/
<> 148:21d94c44109e 5349 #define RTC_BKP11R_Pos (0U)
<> 148:21d94c44109e 5350 #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 5351 #define RTC_BKP11R RTC_BKP11R_Msk
<> 148:21d94c44109e 5352
<> 148:21d94c44109e 5353 /******************** Bits definition for RTC_BKP12R register ***************/
<> 148:21d94c44109e 5354 #define RTC_BKP12R_Pos (0U)
<> 148:21d94c44109e 5355 #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 5356 #define RTC_BKP12R RTC_BKP12R_Msk
<> 148:21d94c44109e 5357
<> 148:21d94c44109e 5358 /******************** Bits definition for RTC_BKP13R register ***************/
<> 148:21d94c44109e 5359 #define RTC_BKP13R_Pos (0U)
<> 148:21d94c44109e 5360 #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 5361 #define RTC_BKP13R RTC_BKP13R_Msk
<> 148:21d94c44109e 5362
<> 148:21d94c44109e 5363 /******************** Bits definition for RTC_BKP14R register ***************/
<> 148:21d94c44109e 5364 #define RTC_BKP14R_Pos (0U)
<> 148:21d94c44109e 5365 #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 5366 #define RTC_BKP14R RTC_BKP14R_Msk
<> 148:21d94c44109e 5367
<> 148:21d94c44109e 5368 /******************** Bits definition for RTC_BKP15R register ***************/
<> 148:21d94c44109e 5369 #define RTC_BKP15R_Pos (0U)
<> 148:21d94c44109e 5370 #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 5371 #define RTC_BKP15R RTC_BKP15R_Msk
<> 148:21d94c44109e 5372
<> 148:21d94c44109e 5373 /******************** Bits definition for RTC_BKP16R register ***************/
<> 148:21d94c44109e 5374 #define RTC_BKP16R_Pos (0U)
<> 148:21d94c44109e 5375 #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 5376 #define RTC_BKP16R RTC_BKP16R_Msk
<> 148:21d94c44109e 5377
<> 148:21d94c44109e 5378 /******************** Bits definition for RTC_BKP17R register ***************/
<> 148:21d94c44109e 5379 #define RTC_BKP17R_Pos (0U)
<> 148:21d94c44109e 5380 #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 5381 #define RTC_BKP17R RTC_BKP17R_Msk
<> 148:21d94c44109e 5382
<> 148:21d94c44109e 5383 /******************** Bits definition for RTC_BKP18R register ***************/
<> 148:21d94c44109e 5384 #define RTC_BKP18R_Pos (0U)
<> 148:21d94c44109e 5385 #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 5386 #define RTC_BKP18R RTC_BKP18R_Msk
<> 148:21d94c44109e 5387
<> 148:21d94c44109e 5388 /******************** Bits definition for RTC_BKP19R register ***************/
<> 148:21d94c44109e 5389 #define RTC_BKP19R_Pos (0U)
<> 148:21d94c44109e 5390 #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 5391 #define RTC_BKP19R RTC_BKP19R_Msk
<> 148:21d94c44109e 5392
<> 148:21d94c44109e 5393 /******************** Bits definition for RTC_BKP20R register ***************/
<> 148:21d94c44109e 5394 #define RTC_BKP20R_Pos (0U)
<> 148:21d94c44109e 5395 #define RTC_BKP20R_Msk (0xFFFFFFFFU << RTC_BKP20R_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 5396 #define RTC_BKP20R RTC_BKP20R_Msk
<> 148:21d94c44109e 5397
<> 148:21d94c44109e 5398 /******************** Bits definition for RTC_BKP21R register ***************/
<> 148:21d94c44109e 5399 #define RTC_BKP21R_Pos (0U)
<> 148:21d94c44109e 5400 #define RTC_BKP21R_Msk (0xFFFFFFFFU << RTC_BKP21R_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 5401 #define RTC_BKP21R RTC_BKP21R_Msk
<> 148:21d94c44109e 5402
<> 148:21d94c44109e 5403 /******************** Bits definition for RTC_BKP22R register ***************/
<> 148:21d94c44109e 5404 #define RTC_BKP22R_Pos (0U)
<> 148:21d94c44109e 5405 #define RTC_BKP22R_Msk (0xFFFFFFFFU << RTC_BKP22R_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 5406 #define RTC_BKP22R RTC_BKP22R_Msk
<> 148:21d94c44109e 5407
<> 148:21d94c44109e 5408 /******************** Bits definition for RTC_BKP23R register ***************/
<> 148:21d94c44109e 5409 #define RTC_BKP23R_Pos (0U)
<> 148:21d94c44109e 5410 #define RTC_BKP23R_Msk (0xFFFFFFFFU << RTC_BKP23R_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 5411 #define RTC_BKP23R RTC_BKP23R_Msk
<> 148:21d94c44109e 5412
<> 148:21d94c44109e 5413 /******************** Bits definition for RTC_BKP24R register ***************/
<> 148:21d94c44109e 5414 #define RTC_BKP24R_Pos (0U)
<> 148:21d94c44109e 5415 #define RTC_BKP24R_Msk (0xFFFFFFFFU << RTC_BKP24R_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 5416 #define RTC_BKP24R RTC_BKP24R_Msk
<> 148:21d94c44109e 5417
<> 148:21d94c44109e 5418 /******************** Bits definition for RTC_BKP25R register ***************/
<> 148:21d94c44109e 5419 #define RTC_BKP25R_Pos (0U)
<> 148:21d94c44109e 5420 #define RTC_BKP25R_Msk (0xFFFFFFFFU << RTC_BKP25R_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 5421 #define RTC_BKP25R RTC_BKP25R_Msk
<> 148:21d94c44109e 5422
<> 148:21d94c44109e 5423 /******************** Bits definition for RTC_BKP26R register ***************/
<> 148:21d94c44109e 5424 #define RTC_BKP26R_Pos (0U)
<> 148:21d94c44109e 5425 #define RTC_BKP26R_Msk (0xFFFFFFFFU << RTC_BKP26R_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 5426 #define RTC_BKP26R RTC_BKP26R_Msk
<> 148:21d94c44109e 5427
<> 148:21d94c44109e 5428 /******************** Bits definition for RTC_BKP27R register ***************/
<> 148:21d94c44109e 5429 #define RTC_BKP27R_Pos (0U)
<> 148:21d94c44109e 5430 #define RTC_BKP27R_Msk (0xFFFFFFFFU << RTC_BKP27R_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 5431 #define RTC_BKP27R RTC_BKP27R_Msk
<> 148:21d94c44109e 5432
<> 148:21d94c44109e 5433 /******************** Bits definition for RTC_BKP28R register ***************/
<> 148:21d94c44109e 5434 #define RTC_BKP28R_Pos (0U)
<> 148:21d94c44109e 5435 #define RTC_BKP28R_Msk (0xFFFFFFFFU << RTC_BKP28R_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 5436 #define RTC_BKP28R RTC_BKP28R_Msk
<> 148:21d94c44109e 5437
<> 148:21d94c44109e 5438 /******************** Bits definition for RTC_BKP29R register ***************/
<> 148:21d94c44109e 5439 #define RTC_BKP29R_Pos (0U)
<> 148:21d94c44109e 5440 #define RTC_BKP29R_Msk (0xFFFFFFFFU << RTC_BKP29R_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 5441 #define RTC_BKP29R RTC_BKP29R_Msk
<> 148:21d94c44109e 5442
<> 148:21d94c44109e 5443 /******************** Bits definition for RTC_BKP30R register ***************/
<> 148:21d94c44109e 5444 #define RTC_BKP30R_Pos (0U)
<> 148:21d94c44109e 5445 #define RTC_BKP30R_Msk (0xFFFFFFFFU << RTC_BKP30R_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 5446 #define RTC_BKP30R RTC_BKP30R_Msk
<> 148:21d94c44109e 5447
<> 148:21d94c44109e 5448 /******************** Bits definition for RTC_BKP31R register ***************/
<> 148:21d94c44109e 5449 #define RTC_BKP31R_Pos (0U)
<> 148:21d94c44109e 5450 #define RTC_BKP31R_Msk (0xFFFFFFFFU << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 5451 #define RTC_BKP31R RTC_BKP31R_Msk
<> 148:21d94c44109e 5452
<> 148:21d94c44109e 5453 /******************** Number of backup registers ******************************/
<> 148:21d94c44109e 5454 #define RTC_BKP_NUMBER 32
<> 148:21d94c44109e 5455
<> 148:21d94c44109e 5456 /******************************************************************************/
<> 148:21d94c44109e 5457 /* */
<> 148:21d94c44109e 5458 /* Serial Peripheral Interface (SPI) */
<> 148:21d94c44109e 5459 /* */
<> 148:21d94c44109e 5460 /******************************************************************************/
<> 148:21d94c44109e 5461
<> 148:21d94c44109e 5462 /*
<> 148:21d94c44109e 5463 * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
<> 148:21d94c44109e 5464 */
<> 148:21d94c44109e 5465 #define SPI_I2S_SUPPORT
<> 148:21d94c44109e 5466
<> 148:21d94c44109e 5467 /******************* Bit definition for SPI_CR1 register ********************/
<> 148:21d94c44109e 5468 #define SPI_CR1_CPHA_Pos (0U)
<> 148:21d94c44109e 5469 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 5470 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
<> 148:21d94c44109e 5471 #define SPI_CR1_CPOL_Pos (1U)
<> 148:21d94c44109e 5472 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 5473 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
<> 148:21d94c44109e 5474 #define SPI_CR1_MSTR_Pos (2U)
<> 148:21d94c44109e 5475 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 5476 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
<> 148:21d94c44109e 5477
<> 148:21d94c44109e 5478 #define SPI_CR1_BR_Pos (3U)
<> 148:21d94c44109e 5479 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
<> 148:21d94c44109e 5480 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
<> 148:21d94c44109e 5481 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 5482 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 5483 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 5484
<> 148:21d94c44109e 5485 #define SPI_CR1_SPE_Pos (6U)
<> 148:21d94c44109e 5486 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 5487 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
<> 148:21d94c44109e 5488 #define SPI_CR1_LSBFIRST_Pos (7U)
<> 148:21d94c44109e 5489 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 5490 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
<> 148:21d94c44109e 5491 #define SPI_CR1_SSI_Pos (8U)
<> 148:21d94c44109e 5492 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 5493 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
<> 148:21d94c44109e 5494 #define SPI_CR1_SSM_Pos (9U)
<> 148:21d94c44109e 5495 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 5496 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
<> 148:21d94c44109e 5497 #define SPI_CR1_RXONLY_Pos (10U)
<> 148:21d94c44109e 5498 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 5499 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
<> 148:21d94c44109e 5500 #define SPI_CR1_DFF_Pos (11U)
<> 148:21d94c44109e 5501 #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 5502 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
<> 148:21d94c44109e 5503 #define SPI_CR1_CRCNEXT_Pos (12U)
<> 148:21d94c44109e 5504 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 5505 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
<> 148:21d94c44109e 5506 #define SPI_CR1_CRCEN_Pos (13U)
<> 148:21d94c44109e 5507 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 5508 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
<> 148:21d94c44109e 5509 #define SPI_CR1_BIDIOE_Pos (14U)
<> 148:21d94c44109e 5510 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 5511 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
<> 148:21d94c44109e 5512 #define SPI_CR1_BIDIMODE_Pos (15U)
<> 148:21d94c44109e 5513 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 5514 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
<> 148:21d94c44109e 5515
<> 148:21d94c44109e 5516 /******************* Bit definition for SPI_CR2 register ********************/
<> 148:21d94c44109e 5517 #define SPI_CR2_RXDMAEN_Pos (0U)
<> 148:21d94c44109e 5518 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 5519 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
<> 148:21d94c44109e 5520 #define SPI_CR2_TXDMAEN_Pos (1U)
<> 148:21d94c44109e 5521 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 5522 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
<> 148:21d94c44109e 5523 #define SPI_CR2_SSOE_Pos (2U)
<> 148:21d94c44109e 5524 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 5525 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
<> 148:21d94c44109e 5526 #define SPI_CR2_FRF_Pos (4U)
<> 148:21d94c44109e 5527 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 5528 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame format */
<> 148:21d94c44109e 5529 #define SPI_CR2_ERRIE_Pos (5U)
<> 148:21d94c44109e 5530 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 5531 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
<> 148:21d94c44109e 5532 #define SPI_CR2_RXNEIE_Pos (6U)
<> 148:21d94c44109e 5533 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 5534 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
<> 148:21d94c44109e 5535 #define SPI_CR2_TXEIE_Pos (7U)
<> 148:21d94c44109e 5536 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 5537 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
<> 148:21d94c44109e 5538
<> 148:21d94c44109e 5539 /******************** Bit definition for SPI_SR register ********************/
<> 148:21d94c44109e 5540 #define SPI_SR_RXNE_Pos (0U)
<> 148:21d94c44109e 5541 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 5542 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
<> 148:21d94c44109e 5543 #define SPI_SR_TXE_Pos (1U)
<> 148:21d94c44109e 5544 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 5545 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
<> 148:21d94c44109e 5546 #define SPI_SR_CHSIDE_Pos (2U)
<> 148:21d94c44109e 5547 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 5548 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
<> 148:21d94c44109e 5549 #define SPI_SR_UDR_Pos (3U)
<> 148:21d94c44109e 5550 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 5551 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
<> 148:21d94c44109e 5552 #define SPI_SR_CRCERR_Pos (4U)
<> 148:21d94c44109e 5553 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 5554 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
<> 148:21d94c44109e 5555 #define SPI_SR_MODF_Pos (5U)
<> 148:21d94c44109e 5556 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 5557 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
<> 148:21d94c44109e 5558 #define SPI_SR_OVR_Pos (6U)
<> 148:21d94c44109e 5559 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 5560 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
<> 148:21d94c44109e 5561 #define SPI_SR_BSY_Pos (7U)
<> 148:21d94c44109e 5562 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 5563 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
<> 148:21d94c44109e 5564 #define SPI_SR_FRE_Pos (8U)
<> 148:21d94c44109e 5565 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 5566 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
<> 148:21d94c44109e 5567
<> 148:21d94c44109e 5568 /******************** Bit definition for SPI_DR register ********************/
<> 148:21d94c44109e 5569 #define SPI_DR_DR_Pos (0U)
<> 148:21d94c44109e 5570 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 5571 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
<> 148:21d94c44109e 5572
<> 148:21d94c44109e 5573 /******************* Bit definition for SPI_CRCPR register ******************/
<> 148:21d94c44109e 5574 #define SPI_CRCPR_CRCPOLY_Pos (0U)
<> 148:21d94c44109e 5575 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 5576 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
<> 148:21d94c44109e 5577
<> 148:21d94c44109e 5578 /****************** Bit definition for SPI_RXCRCR register ******************/
<> 148:21d94c44109e 5579 #define SPI_RXCRCR_RXCRC_Pos (0U)
<> 148:21d94c44109e 5580 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 5581 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
<> 148:21d94c44109e 5582
<> 148:21d94c44109e 5583 /****************** Bit definition for SPI_TXCRCR register ******************/
<> 148:21d94c44109e 5584 #define SPI_TXCRCR_TXCRC_Pos (0U)
<> 148:21d94c44109e 5585 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 5586 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
<> 148:21d94c44109e 5587
<> 148:21d94c44109e 5588 /****************** Bit definition for SPI_I2SCFGR register *****************/
<> 148:21d94c44109e 5589 #define SPI_I2SCFGR_CHLEN_Pos (0U)
<> 148:21d94c44109e 5590 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 5591 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
<> 148:21d94c44109e 5592
<> 148:21d94c44109e 5593 #define SPI_I2SCFGR_DATLEN_Pos (1U)
<> 148:21d94c44109e 5594 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
<> 148:21d94c44109e 5595 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
<> 148:21d94c44109e 5596 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 5597 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 5598
<> 148:21d94c44109e 5599 #define SPI_I2SCFGR_CKPOL_Pos (3U)
<> 148:21d94c44109e 5600 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 5601 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
<> 148:21d94c44109e 5602
<> 148:21d94c44109e 5603 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
<> 148:21d94c44109e 5604 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
<> 148:21d94c44109e 5605 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
<> 148:21d94c44109e 5606 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 5607 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 5608
<> 148:21d94c44109e 5609 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
<> 148:21d94c44109e 5610 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 5611 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
<> 148:21d94c44109e 5612
<> 148:21d94c44109e 5613 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
<> 148:21d94c44109e 5614 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
<> 148:21d94c44109e 5615 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
<> 148:21d94c44109e 5616 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 5617 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 5618
<> 148:21d94c44109e 5619 #define SPI_I2SCFGR_I2SE_Pos (10U)
<> 148:21d94c44109e 5620 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 5621 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
<> 148:21d94c44109e 5622 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
<> 148:21d94c44109e 5623 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 5624 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
<> 148:21d94c44109e 5625
<> 148:21d94c44109e 5626 /****************** Bit definition for SPI_I2SPR register *******************/
<> 148:21d94c44109e 5627 #define SPI_I2SPR_I2SDIV_Pos (0U)
<> 148:21d94c44109e 5628 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
<> 148:21d94c44109e 5629 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
<> 148:21d94c44109e 5630 #define SPI_I2SPR_ODD_Pos (8U)
<> 148:21d94c44109e 5631 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 5632 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
<> 148:21d94c44109e 5633 #define SPI_I2SPR_MCKOE_Pos (9U)
<> 148:21d94c44109e 5634 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 5635 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
<> 148:21d94c44109e 5636
<> 148:21d94c44109e 5637 /******************************************************************************/
<> 148:21d94c44109e 5638 /* */
<> 148:21d94c44109e 5639 /* System Configuration (SYSCFG) */
<> 148:21d94c44109e 5640 /* */
<> 148:21d94c44109e 5641 /******************************************************************************/
<> 148:21d94c44109e 5642 /***************** Bit definition for SYSCFG_MEMRMP register ****************/
<> 148:21d94c44109e 5643 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
<> 148:21d94c44109e 5644 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */
<> 148:21d94c44109e 5645 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
<> 148:21d94c44109e 5646 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 5647 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 5648 #define SYSCFG_MEMRMP_BOOT_MODE_Pos (8U)
<> 148:21d94c44109e 5649 #define SYSCFG_MEMRMP_BOOT_MODE_Msk (0x3U << SYSCFG_MEMRMP_BOOT_MODE_Pos) /*!< 0x00000300 */
<> 148:21d94c44109e 5650 #define SYSCFG_MEMRMP_BOOT_MODE SYSCFG_MEMRMP_BOOT_MODE_Msk /*!< Boot mode Config */
<> 148:21d94c44109e 5651 #define SYSCFG_MEMRMP_BOOT_MODE_0 (0x1U << SYSCFG_MEMRMP_BOOT_MODE_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 5652 #define SYSCFG_MEMRMP_BOOT_MODE_1 (0x2U << SYSCFG_MEMRMP_BOOT_MODE_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 5653
<> 148:21d94c44109e 5654 /***************** Bit definition for SYSCFG_PMC register *******************/
<> 148:21d94c44109e 5655 #define SYSCFG_PMC_USB_PU_Pos (0U)
<> 148:21d94c44109e 5656 #define SYSCFG_PMC_USB_PU_Msk (0x1U << SYSCFG_PMC_USB_PU_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 5657 #define SYSCFG_PMC_USB_PU SYSCFG_PMC_USB_PU_Msk /*!< SYSCFG PMC */
<> 148:21d94c44109e 5658
<> 148:21d94c44109e 5659 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
<> 148:21d94c44109e 5660 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
<> 148:21d94c44109e 5661 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
<> 148:21d94c44109e 5662 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
<> 148:21d94c44109e 5663 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
<> 148:21d94c44109e 5664 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
<> 148:21d94c44109e 5665 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
<> 148:21d94c44109e 5666 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
<> 148:21d94c44109e 5667 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
<> 148:21d94c44109e 5668 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
<> 148:21d94c44109e 5669 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
<> 148:21d94c44109e 5670 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
<> 148:21d94c44109e 5671 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
<> 148:21d94c44109e 5672
<> 148:21d94c44109e 5673 /**
<> 148:21d94c44109e 5674 * @brief EXTI0 configuration
<> 148:21d94c44109e 5675 */
<> 148:21d94c44109e 5676 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */
<> 148:21d94c44109e 5677 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */
<> 148:21d94c44109e 5678 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */
<> 148:21d94c44109e 5679 #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */
<> 148:21d94c44109e 5680 #define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!< PE[0] pin */
<> 148:21d94c44109e 5681 #define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */
<> 148:21d94c44109e 5682 #define SYSCFG_EXTICR1_EXTI0_PF (0x00000006U) /*!< PF[0] pin */
<> 148:21d94c44109e 5683 #define SYSCFG_EXTICR1_EXTI0_PG (0x00000007U) /*!< PG[0] pin */
<> 148:21d94c44109e 5684
<> 148:21d94c44109e 5685 /**
<> 148:21d94c44109e 5686 * @brief EXTI1 configuration
<> 148:21d94c44109e 5687 */
<> 148:21d94c44109e 5688 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */
<> 148:21d94c44109e 5689 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */
<> 148:21d94c44109e 5690 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */
<> 148:21d94c44109e 5691 #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */
<> 148:21d94c44109e 5692 #define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!< PE[1] pin */
<> 148:21d94c44109e 5693 #define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */
<> 148:21d94c44109e 5694 #define SYSCFG_EXTICR1_EXTI1_PF (0x00000060U) /*!< PF[1] pin */
<> 148:21d94c44109e 5695 #define SYSCFG_EXTICR1_EXTI1_PG (0x00000070U) /*!< PG[1] pin */
<> 148:21d94c44109e 5696
<> 148:21d94c44109e 5697 /**
<> 148:21d94c44109e 5698 * @brief EXTI2 configuration
<> 148:21d94c44109e 5699 */
<> 148:21d94c44109e 5700 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */
<> 148:21d94c44109e 5701 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */
<> 148:21d94c44109e 5702 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */
<> 148:21d94c44109e 5703 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
<> 148:21d94c44109e 5704 #define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!< PE[2] pin */
<> 148:21d94c44109e 5705 #define SYSCFG_EXTICR1_EXTI2_PH (0x00000500U) /*!< PH[2] pin */
<> 148:21d94c44109e 5706 #define SYSCFG_EXTICR1_EXTI2_PF (0x00000600U) /*!< PF[2] pin */
<> 148:21d94c44109e 5707 #define SYSCFG_EXTICR1_EXTI2_PG (0x00000700U) /*!< PG[2] pin */
<> 148:21d94c44109e 5708
<> 148:21d94c44109e 5709 /**
<> 148:21d94c44109e 5710 * @brief EXTI3 configuration
<> 148:21d94c44109e 5711 */
<> 148:21d94c44109e 5712 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */
<> 148:21d94c44109e 5713 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */
<> 148:21d94c44109e 5714 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
<> 148:21d94c44109e 5715 #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
<> 148:21d94c44109e 5716 #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
<> 148:21d94c44109e 5717 #define SYSCFG_EXTICR1_EXTI3_PF (0x00003000U) /*!< PF[3] pin */
<> 148:21d94c44109e 5718 #define SYSCFG_EXTICR1_EXTI3_PG (0x00004000U) /*!< PG[3] pin */
<> 148:21d94c44109e 5719
<> 148:21d94c44109e 5720 /***************** Bit definition for SYSCFG_EXTICR2 register *****************/
<> 148:21d94c44109e 5721 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
<> 148:21d94c44109e 5722 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
<> 148:21d94c44109e 5723 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
<> 148:21d94c44109e 5724 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
<> 148:21d94c44109e 5725 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
<> 148:21d94c44109e 5726 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
<> 148:21d94c44109e 5727 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
<> 148:21d94c44109e 5728 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
<> 148:21d94c44109e 5729 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
<> 148:21d94c44109e 5730 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
<> 148:21d94c44109e 5731 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
<> 148:21d94c44109e 5732 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
<> 148:21d94c44109e 5733
<> 148:21d94c44109e 5734 /**
<> 148:21d94c44109e 5735 * @brief EXTI4 configuration
<> 148:21d94c44109e 5736 */
<> 148:21d94c44109e 5737 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */
<> 148:21d94c44109e 5738 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */
<> 148:21d94c44109e 5739 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
<> 148:21d94c44109e 5740 #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */
<> 148:21d94c44109e 5741 #define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!< PE[4] pin */
<> 148:21d94c44109e 5742 #define SYSCFG_EXTICR2_EXTI4_PF (0x00000006U) /*!< PF[4] pin */
<> 148:21d94c44109e 5743 #define SYSCFG_EXTICR2_EXTI4_PG (0x00000007U) /*!< PG[4] pin */
<> 148:21d94c44109e 5744
<> 148:21d94c44109e 5745 /**
<> 148:21d94c44109e 5746 * @brief EXTI5 configuration
<> 148:21d94c44109e 5747 */
<> 148:21d94c44109e 5748 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */
<> 148:21d94c44109e 5749 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */
<> 148:21d94c44109e 5750 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
<> 148:21d94c44109e 5751 #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */
<> 148:21d94c44109e 5752 #define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!< PE[5] pin */
<> 148:21d94c44109e 5753 #define SYSCFG_EXTICR2_EXTI5_PF (0x00000060U) /*!< PF[5] pin */
<> 148:21d94c44109e 5754 #define SYSCFG_EXTICR2_EXTI5_PG (0x00000070U) /*!< PG[5] pin */
<> 148:21d94c44109e 5755
<> 148:21d94c44109e 5756 /**
<> 148:21d94c44109e 5757 * @brief EXTI6 configuration
<> 148:21d94c44109e 5758 */
<> 148:21d94c44109e 5759 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */
<> 148:21d94c44109e 5760 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */
<> 148:21d94c44109e 5761 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
<> 148:21d94c44109e 5762 #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */
<> 148:21d94c44109e 5763 #define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!< PE[6] pin */
<> 148:21d94c44109e 5764 #define SYSCFG_EXTICR2_EXTI6_PF (0x00000600U) /*!< PF[6] pin */
<> 148:21d94c44109e 5765 #define SYSCFG_EXTICR2_EXTI6_PG (0x00000700U) /*!< PG[6] pin */
<> 148:21d94c44109e 5766
<> 148:21d94c44109e 5767 /**
<> 148:21d94c44109e 5768 * @brief EXTI7 configuration
<> 148:21d94c44109e 5769 */
<> 148:21d94c44109e 5770 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */
<> 148:21d94c44109e 5771 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */
<> 148:21d94c44109e 5772 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
<> 148:21d94c44109e 5773 #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */
<> 148:21d94c44109e 5774 #define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!< PE[7] pin */
<> 148:21d94c44109e 5775 #define SYSCFG_EXTICR2_EXTI7_PF (0x00006000U) /*!< PF[7] pin */
<> 148:21d94c44109e 5776 #define SYSCFG_EXTICR2_EXTI7_PG (0x00007000U) /*!< PG[7] pin */
<> 148:21d94c44109e 5777
<> 148:21d94c44109e 5778 /***************** Bit definition for SYSCFG_EXTICR3 register *****************/
<> 148:21d94c44109e 5779 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
<> 148:21d94c44109e 5780 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
<> 148:21d94c44109e 5781 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
<> 148:21d94c44109e 5782 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
<> 148:21d94c44109e 5783 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
<> 148:21d94c44109e 5784 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
<> 148:21d94c44109e 5785 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
<> 148:21d94c44109e 5786 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
<> 148:21d94c44109e 5787 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
<> 148:21d94c44109e 5788 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
<> 148:21d94c44109e 5789 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
<> 148:21d94c44109e 5790 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
<> 148:21d94c44109e 5791
<> 148:21d94c44109e 5792 /**
<> 148:21d94c44109e 5793 * @brief EXTI8 configuration
<> 148:21d94c44109e 5794 */
<> 148:21d94c44109e 5795 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */
<> 148:21d94c44109e 5796 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */
<> 148:21d94c44109e 5797 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
<> 148:21d94c44109e 5798 #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */
<> 148:21d94c44109e 5799 #define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!< PE[8] pin */
<> 148:21d94c44109e 5800 #define SYSCFG_EXTICR3_EXTI8_PF (0x00000006U) /*!< PF[8] pin */
<> 148:21d94c44109e 5801 #define SYSCFG_EXTICR3_EXTI8_PG (0x00000007U) /*!< PG[8] pin */
<> 148:21d94c44109e 5802
<> 148:21d94c44109e 5803 /**
<> 148:21d94c44109e 5804 * @brief EXTI9 configuration
<> 148:21d94c44109e 5805 */
<> 148:21d94c44109e 5806 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */
<> 148:21d94c44109e 5807 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */
<> 148:21d94c44109e 5808 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
<> 148:21d94c44109e 5809 #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */
<> 148:21d94c44109e 5810 #define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!< PE[9] pin */
<> 148:21d94c44109e 5811 #define SYSCFG_EXTICR3_EXTI9_PF (0x00000060U) /*!< PF[9] pin */
<> 148:21d94c44109e 5812 #define SYSCFG_EXTICR3_EXTI9_PG (0x00000070U) /*!< PG[9] pin */
<> 148:21d94c44109e 5813
<> 148:21d94c44109e 5814 /**
<> 148:21d94c44109e 5815 * @brief EXTI10 configuration
<> 148:21d94c44109e 5816 */
<> 148:21d94c44109e 5817 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */
<> 148:21d94c44109e 5818 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */
<> 148:21d94c44109e 5819 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
<> 148:21d94c44109e 5820 #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */
<> 148:21d94c44109e 5821 #define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!< PE[10] pin */
<> 148:21d94c44109e 5822 #define SYSCFG_EXTICR3_EXTI10_PF (0x00000600U) /*!< PF[10] pin */
<> 148:21d94c44109e 5823 #define SYSCFG_EXTICR3_EXTI10_PG (0x00000700U) /*!< PG[10] pin */
<> 148:21d94c44109e 5824
<> 148:21d94c44109e 5825 /**
<> 148:21d94c44109e 5826 * @brief EXTI11 configuration
<> 148:21d94c44109e 5827 */
<> 148:21d94c44109e 5828 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */
<> 148:21d94c44109e 5829 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */
<> 148:21d94c44109e 5830 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
<> 148:21d94c44109e 5831 #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */
<> 148:21d94c44109e 5832 #define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!< PE[11] pin */
<> 148:21d94c44109e 5833 #define SYSCFG_EXTICR3_EXTI11_PF (0x00006000U) /*!< PF[11] pin */
<> 148:21d94c44109e 5834 #define SYSCFG_EXTICR3_EXTI11_PG (0x00007000U) /*!< PG[11] pin */
<> 148:21d94c44109e 5835
<> 148:21d94c44109e 5836 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/
<> 148:21d94c44109e 5837 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
<> 148:21d94c44109e 5838 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
<> 148:21d94c44109e 5839 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
<> 148:21d94c44109e 5840 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
<> 148:21d94c44109e 5841 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
<> 148:21d94c44109e 5842 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
<> 148:21d94c44109e 5843 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
<> 148:21d94c44109e 5844 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
<> 148:21d94c44109e 5845 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
<> 148:21d94c44109e 5846 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
<> 148:21d94c44109e 5847 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
<> 148:21d94c44109e 5848 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
<> 148:21d94c44109e 5849
<> 148:21d94c44109e 5850 /**
<> 148:21d94c44109e 5851 * @brief EXTI12 configuration
<> 148:21d94c44109e 5852 */
<> 148:21d94c44109e 5853 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */
<> 148:21d94c44109e 5854 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */
<> 148:21d94c44109e 5855 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
<> 148:21d94c44109e 5856 #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */
<> 148:21d94c44109e 5857 #define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!< PE[12] pin */
<> 148:21d94c44109e 5858 #define SYSCFG_EXTICR4_EXTI12_PF (0x00000006U) /*!< PF[12] pin */
<> 148:21d94c44109e 5859 #define SYSCFG_EXTICR4_EXTI12_PG (0x00000007U) /*!< PG[12] pin */
<> 148:21d94c44109e 5860
<> 148:21d94c44109e 5861 /**
<> 148:21d94c44109e 5862 * @brief EXTI13 configuration
<> 148:21d94c44109e 5863 */
<> 148:21d94c44109e 5864 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */
<> 148:21d94c44109e 5865 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */
<> 148:21d94c44109e 5866 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
<> 148:21d94c44109e 5867 #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */
<> 148:21d94c44109e 5868 #define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!< PE[13] pin */
<> 148:21d94c44109e 5869 #define SYSCFG_EXTICR4_EXTI13_PF (0x00000060U) /*!< PF[13] pin */
<> 148:21d94c44109e 5870 #define SYSCFG_EXTICR4_EXTI13_PG (0x00000070U) /*!< PG[13] pin */
<> 148:21d94c44109e 5871
<> 148:21d94c44109e 5872 /**
<> 148:21d94c44109e 5873 * @brief EXTI14 configuration
<> 148:21d94c44109e 5874 */
<> 148:21d94c44109e 5875 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */
<> 148:21d94c44109e 5876 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */
<> 148:21d94c44109e 5877 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
<> 148:21d94c44109e 5878 #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */
<> 148:21d94c44109e 5879 #define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!< PE[14] pin */
<> 148:21d94c44109e 5880 #define SYSCFG_EXTICR4_EXTI14_PF (0x00000600U) /*!< PF[14] pin */
<> 148:21d94c44109e 5881 #define SYSCFG_EXTICR4_EXTI14_PG (0x00000700U) /*!< PG[14] pin */
<> 148:21d94c44109e 5882
<> 148:21d94c44109e 5883 /**
<> 148:21d94c44109e 5884 * @brief EXTI15 configuration
<> 148:21d94c44109e 5885 */
<> 148:21d94c44109e 5886 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */
<> 148:21d94c44109e 5887 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */
<> 148:21d94c44109e 5888 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
<> 148:21d94c44109e 5889 #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */
<> 148:21d94c44109e 5890 #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
<> 148:21d94c44109e 5891 #define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */
<> 148:21d94c44109e 5892 #define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */
<> 148:21d94c44109e 5893
<> 148:21d94c44109e 5894 /******************************************************************************/
<> 148:21d94c44109e 5895 /* */
<> 148:21d94c44109e 5896 /* Routing Interface (RI) */
<> 148:21d94c44109e 5897 /* */
<> 148:21d94c44109e 5898 /******************************************************************************/
<> 148:21d94c44109e 5899
<> 148:21d94c44109e 5900 /******************** Bit definition for RI_ICR register ********************/
<> 148:21d94c44109e 5901 #define RI_ICR_IC1OS_Pos (0U)
<> 148:21d94c44109e 5902 #define RI_ICR_IC1OS_Msk (0xFU << RI_ICR_IC1OS_Pos) /*!< 0x0000000F */
<> 148:21d94c44109e 5903 #define RI_ICR_IC1OS RI_ICR_IC1OS_Msk /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
<> 148:21d94c44109e 5904 #define RI_ICR_IC1OS_0 (0x1U << RI_ICR_IC1OS_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 5905 #define RI_ICR_IC1OS_1 (0x2U << RI_ICR_IC1OS_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 5906 #define RI_ICR_IC1OS_2 (0x4U << RI_ICR_IC1OS_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 5907 #define RI_ICR_IC1OS_3 (0x8U << RI_ICR_IC1OS_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 5908
<> 148:21d94c44109e 5909 #define RI_ICR_IC2OS_Pos (4U)
<> 148:21d94c44109e 5910 #define RI_ICR_IC2OS_Msk (0xFU << RI_ICR_IC2OS_Pos) /*!< 0x000000F0 */
<> 148:21d94c44109e 5911 #define RI_ICR_IC2OS RI_ICR_IC2OS_Msk /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
<> 148:21d94c44109e 5912 #define RI_ICR_IC2OS_0 (0x1U << RI_ICR_IC2OS_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 5913 #define RI_ICR_IC2OS_1 (0x2U << RI_ICR_IC2OS_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 5914 #define RI_ICR_IC2OS_2 (0x4U << RI_ICR_IC2OS_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 5915 #define RI_ICR_IC2OS_3 (0x8U << RI_ICR_IC2OS_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 5916
<> 148:21d94c44109e 5917 #define RI_ICR_IC3OS_Pos (8U)
<> 148:21d94c44109e 5918 #define RI_ICR_IC3OS_Msk (0xFU << RI_ICR_IC3OS_Pos) /*!< 0x00000F00 */
<> 148:21d94c44109e 5919 #define RI_ICR_IC3OS RI_ICR_IC3OS_Msk /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
<> 148:21d94c44109e 5920 #define RI_ICR_IC3OS_0 (0x1U << RI_ICR_IC3OS_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 5921 #define RI_ICR_IC3OS_1 (0x2U << RI_ICR_IC3OS_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 5922 #define RI_ICR_IC3OS_2 (0x4U << RI_ICR_IC3OS_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 5923 #define RI_ICR_IC3OS_3 (0x8U << RI_ICR_IC3OS_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 5924
<> 148:21d94c44109e 5925 #define RI_ICR_IC4OS_Pos (12U)
<> 148:21d94c44109e 5926 #define RI_ICR_IC4OS_Msk (0xFU << RI_ICR_IC4OS_Pos) /*!< 0x0000F000 */
<> 148:21d94c44109e 5927 #define RI_ICR_IC4OS RI_ICR_IC4OS_Msk /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
<> 148:21d94c44109e 5928 #define RI_ICR_IC4OS_0 (0x1U << RI_ICR_IC4OS_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 5929 #define RI_ICR_IC4OS_1 (0x2U << RI_ICR_IC4OS_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 5930 #define RI_ICR_IC4OS_2 (0x4U << RI_ICR_IC4OS_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 5931 #define RI_ICR_IC4OS_3 (0x8U << RI_ICR_IC4OS_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 5932
<> 148:21d94c44109e 5933 #define RI_ICR_TIM_Pos (16U)
<> 148:21d94c44109e 5934 #define RI_ICR_TIM_Msk (0x3U << RI_ICR_TIM_Pos) /*!< 0x00030000 */
<> 148:21d94c44109e 5935 #define RI_ICR_TIM RI_ICR_TIM_Msk /*!< TIM[3:0] bits (Timers select bits) */
<> 148:21d94c44109e 5936 #define RI_ICR_TIM_0 (0x1U << RI_ICR_TIM_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 5937 #define RI_ICR_TIM_1 (0x2U << RI_ICR_TIM_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 5938
<> 148:21d94c44109e 5939 #define RI_ICR_IC1_Pos (18U)
<> 148:21d94c44109e 5940 #define RI_ICR_IC1_Msk (0x1U << RI_ICR_IC1_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 5941 #define RI_ICR_IC1 RI_ICR_IC1_Msk /*!< Input capture 1 */
<> 148:21d94c44109e 5942 #define RI_ICR_IC2_Pos (19U)
<> 148:21d94c44109e 5943 #define RI_ICR_IC2_Msk (0x1U << RI_ICR_IC2_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 5944 #define RI_ICR_IC2 RI_ICR_IC2_Msk /*!< Input capture 2 */
<> 148:21d94c44109e 5945 #define RI_ICR_IC3_Pos (20U)
<> 148:21d94c44109e 5946 #define RI_ICR_IC3_Msk (0x1U << RI_ICR_IC3_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 5947 #define RI_ICR_IC3 RI_ICR_IC3_Msk /*!< Input capture 3 */
<> 148:21d94c44109e 5948 #define RI_ICR_IC4_Pos (21U)
<> 148:21d94c44109e 5949 #define RI_ICR_IC4_Msk (0x1U << RI_ICR_IC4_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 5950 #define RI_ICR_IC4 RI_ICR_IC4_Msk /*!< Input capture 4 */
<> 148:21d94c44109e 5951
<> 148:21d94c44109e 5952 /******************** Bit definition for RI_ASCR1 register ********************/
<> 148:21d94c44109e 5953 #define RI_ASCR1_CH_Pos (0U)
<> 148:21d94c44109e 5954 #define RI_ASCR1_CH_Msk (0x7BFDFFFFU << RI_ASCR1_CH_Pos) /*!< 0x7BFDFFFF */
<> 148:21d94c44109e 5955 #define RI_ASCR1_CH RI_ASCR1_CH_Msk /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
<> 148:21d94c44109e 5956 #define RI_ASCR1_CH_0 (0x00000001U) /*!< Bit 0 */
<> 148:21d94c44109e 5957 #define RI_ASCR1_CH_1 (0x00000002U) /*!< Bit 1 */
<> 148:21d94c44109e 5958 #define RI_ASCR1_CH_2 (0x00000004U) /*!< Bit 2 */
<> 148:21d94c44109e 5959 #define RI_ASCR1_CH_3 (0x00000008U) /*!< Bit 3 */
<> 148:21d94c44109e 5960 #define RI_ASCR1_CH_4 (0x00000010U) /*!< Bit 4 */
<> 148:21d94c44109e 5961 #define RI_ASCR1_CH_5 (0x00000020U) /*!< Bit 5 */
<> 148:21d94c44109e 5962 #define RI_ASCR1_CH_6 (0x00000040U) /*!< Bit 6 */
<> 148:21d94c44109e 5963 #define RI_ASCR1_CH_7 (0x00000080U) /*!< Bit 7 */
<> 148:21d94c44109e 5964 #define RI_ASCR1_CH_8 (0x00000100U) /*!< Bit 8 */
<> 148:21d94c44109e 5965 #define RI_ASCR1_CH_9 (0x00000200U) /*!< Bit 9 */
<> 148:21d94c44109e 5966 #define RI_ASCR1_CH_10 (0x00000400U) /*!< Bit 10 */
<> 148:21d94c44109e 5967 #define RI_ASCR1_CH_11 (0x00000800U) /*!< Bit 11 */
<> 148:21d94c44109e 5968 #define RI_ASCR1_CH_12 (0x00001000U) /*!< Bit 12 */
<> 148:21d94c44109e 5969 #define RI_ASCR1_CH_13 (0x00002000U) /*!< Bit 13 */
<> 148:21d94c44109e 5970 #define RI_ASCR1_CH_14 (0x00004000U) /*!< Bit 14 */
<> 148:21d94c44109e 5971 #define RI_ASCR1_CH_15 (0x00008000U) /*!< Bit 15 */
<> 148:21d94c44109e 5972 #define RI_ASCR1_CH_31 (0x00010000U) /*!< Bit 16 */
<> 148:21d94c44109e 5973 #define RI_ASCR1_CH_18 (0x00040000U) /*!< Bit 18 */
<> 148:21d94c44109e 5974 #define RI_ASCR1_CH_19 (0x00080000U) /*!< Bit 19 */
<> 148:21d94c44109e 5975 #define RI_ASCR1_CH_20 (0x00100000U) /*!< Bit 20 */
<> 148:21d94c44109e 5976 #define RI_ASCR1_CH_21 (0x00200000U) /*!< Bit 21 */
<> 148:21d94c44109e 5977 #define RI_ASCR1_CH_22 (0x00400000U) /*!< Bit 22 */
<> 148:21d94c44109e 5978 #define RI_ASCR1_CH_23 (0x00800000U) /*!< Bit 23 */
<> 148:21d94c44109e 5979 #define RI_ASCR1_CH_24 (0x01000000U) /*!< Bit 24 */
<> 148:21d94c44109e 5980 #define RI_ASCR1_CH_25 (0x02000000U) /*!< Bit 25 */
<> 148:21d94c44109e 5981 #define RI_ASCR1_VCOMP_Pos (26U)
<> 148:21d94c44109e 5982 #define RI_ASCR1_VCOMP_Msk (0x1U << RI_ASCR1_VCOMP_Pos) /*!< 0x04000000 */
<> 148:21d94c44109e 5983 #define RI_ASCR1_VCOMP RI_ASCR1_VCOMP_Msk /*!< ADC analog switch selection for internal node to COMP1 */
<> 148:21d94c44109e 5984 #define RI_ASCR1_CH_27 (0x08000000U) /*!< Bit 27 */
<> 148:21d94c44109e 5985 #define RI_ASCR1_CH_28 (0x10000000U) /*!< Bit 28 */
<> 148:21d94c44109e 5986 #define RI_ASCR1_CH_29 (0x20000000U) /*!< Bit 29 */
<> 148:21d94c44109e 5987 #define RI_ASCR1_CH_30 (0x40000000U) /*!< Bit 30 */
<> 148:21d94c44109e 5988 #define RI_ASCR1_SCM_Pos (31U)
<> 148:21d94c44109e 5989 #define RI_ASCR1_SCM_Msk (0x1U << RI_ASCR1_SCM_Pos) /*!< 0x80000000 */
<> 148:21d94c44109e 5990 #define RI_ASCR1_SCM RI_ASCR1_SCM_Msk /*!< I/O Switch control mode */
<> 148:21d94c44109e 5991
<> 148:21d94c44109e 5992 /******************** Bit definition for RI_ASCR2 register ********************/
<> 148:21d94c44109e 5993 #define RI_ASCR2_GR10_1 (0x00000001U) /*!< GR10-1 selection bit */
<> 148:21d94c44109e 5994 #define RI_ASCR2_GR10_2 (0x00000002U) /*!< GR10-2 selection bit */
<> 148:21d94c44109e 5995 #define RI_ASCR2_GR10_3 (0x00000004U) /*!< GR10-3 selection bit */
<> 148:21d94c44109e 5996 #define RI_ASCR2_GR10_4 (0x00000008U) /*!< GR10-4 selection bit */
<> 148:21d94c44109e 5997 #define RI_ASCR2_GR6_Pos (4U)
<> 148:21d94c44109e 5998 #define RI_ASCR2_GR6_Msk (0x1800003U << RI_ASCR2_GR6_Pos) /*!< 0x18000030 */
<> 148:21d94c44109e 5999 #define RI_ASCR2_GR6 RI_ASCR2_GR6_Msk /*!< GR6 selection bits */
<> 148:21d94c44109e 6000 #define RI_ASCR2_GR6_1 (0x0000001U << RI_ASCR2_GR6_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 6001 #define RI_ASCR2_GR6_2 (0x0000002U << RI_ASCR2_GR6_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 6002 #define RI_ASCR2_GR6_3 (0x0800000U << RI_ASCR2_GR6_Pos) /*!< 0x08000000 */
<> 148:21d94c44109e 6003 #define RI_ASCR2_GR6_4 (0x1000000U << RI_ASCR2_GR6_Pos) /*!< 0x10000000 */
<> 148:21d94c44109e 6004 #define RI_ASCR2_GR5_1 (0x00000040U) /*!< GR5-1 selection bit */
<> 148:21d94c44109e 6005 #define RI_ASCR2_GR5_2 (0x00000080U) /*!< GR5-2 selection bit */
<> 148:21d94c44109e 6006 #define RI_ASCR2_GR5_3 (0x00000100U) /*!< GR5-3 selection bit */
<> 148:21d94c44109e 6007 #define RI_ASCR2_GR4_1 (0x00000200U) /*!< GR4-1 selection bit */
<> 148:21d94c44109e 6008 #define RI_ASCR2_GR4_2 (0x00000400U) /*!< GR4-2 selection bit */
<> 148:21d94c44109e 6009 #define RI_ASCR2_GR4_3 (0x00000800U) /*!< GR4-3 selection bit */
<> 148:21d94c44109e 6010 #define RI_ASCR2_GR4_4 (0x00008000U) /*!< GR4-4 selection bit */
<> 148:21d94c44109e 6011 #define RI_ASCR2_CH0b_Pos (16U)
<> 148:21d94c44109e 6012 #define RI_ASCR2_CH0b_Msk (0x1U << RI_ASCR2_CH0b_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 6013 #define RI_ASCR2_CH0b RI_ASCR2_CH0b_Msk /*!< CH0b selection bit */
<> 148:21d94c44109e 6014
<> 148:21d94c44109e 6015 /******************** Bit definition for RI_HYSCR1 register ********************/
<> 148:21d94c44109e 6016 #define RI_HYSCR1_PA_Pos (0U)
<> 148:21d94c44109e 6017 #define RI_HYSCR1_PA_Msk (0xFFFFU << RI_HYSCR1_PA_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 6018 #define RI_HYSCR1_PA RI_HYSCR1_PA_Msk /*!< PA[15:0] Port A Hysteresis selection */
<> 148:21d94c44109e 6019 #define RI_HYSCR1_PA_0 (0x0001U << RI_HYSCR1_PA_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 6020 #define RI_HYSCR1_PA_1 (0x0002U << RI_HYSCR1_PA_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 6021 #define RI_HYSCR1_PA_2 (0x0004U << RI_HYSCR1_PA_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 6022 #define RI_HYSCR1_PA_3 (0x0008U << RI_HYSCR1_PA_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 6023 #define RI_HYSCR1_PA_4 (0x0010U << RI_HYSCR1_PA_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 6024 #define RI_HYSCR1_PA_5 (0x0020U << RI_HYSCR1_PA_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 6025 #define RI_HYSCR1_PA_6 (0x0040U << RI_HYSCR1_PA_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 6026 #define RI_HYSCR1_PA_7 (0x0080U << RI_HYSCR1_PA_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 6027 #define RI_HYSCR1_PA_8 (0x0100U << RI_HYSCR1_PA_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 6028 #define RI_HYSCR1_PA_9 (0x0200U << RI_HYSCR1_PA_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 6029 #define RI_HYSCR1_PA_10 (0x0400U << RI_HYSCR1_PA_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 6030 #define RI_HYSCR1_PA_11 (0x0800U << RI_HYSCR1_PA_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 6031 #define RI_HYSCR1_PA_12 (0x1000U << RI_HYSCR1_PA_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 6032 #define RI_HYSCR1_PA_13 (0x2000U << RI_HYSCR1_PA_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 6033 #define RI_HYSCR1_PA_14 (0x4000U << RI_HYSCR1_PA_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 6034 #define RI_HYSCR1_PA_15 (0x8000U << RI_HYSCR1_PA_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 6035
<> 148:21d94c44109e 6036 #define RI_HYSCR1_PB_Pos (16U)
<> 148:21d94c44109e 6037 #define RI_HYSCR1_PB_Msk (0xFFFFU << RI_HYSCR1_PB_Pos) /*!< 0xFFFF0000 */
<> 148:21d94c44109e 6038 #define RI_HYSCR1_PB RI_HYSCR1_PB_Msk /*!< PB[15:0] Port B Hysteresis selection */
<> 148:21d94c44109e 6039 #define RI_HYSCR1_PB_0 (0x0001U << RI_HYSCR1_PB_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 6040 #define RI_HYSCR1_PB_1 (0x0002U << RI_HYSCR1_PB_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 6041 #define RI_HYSCR1_PB_2 (0x0004U << RI_HYSCR1_PB_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 6042 #define RI_HYSCR1_PB_3 (0x0008U << RI_HYSCR1_PB_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 6043 #define RI_HYSCR1_PB_4 (0x0010U << RI_HYSCR1_PB_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 6044 #define RI_HYSCR1_PB_5 (0x0020U << RI_HYSCR1_PB_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 6045 #define RI_HYSCR1_PB_6 (0x0040U << RI_HYSCR1_PB_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 6046 #define RI_HYSCR1_PB_7 (0x0080U << RI_HYSCR1_PB_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 6047 #define RI_HYSCR1_PB_8 (0x0100U << RI_HYSCR1_PB_Pos) /*!< 0x01000000 */
<> 148:21d94c44109e 6048 #define RI_HYSCR1_PB_9 (0x0200U << RI_HYSCR1_PB_Pos) /*!< 0x02000000 */
<> 148:21d94c44109e 6049 #define RI_HYSCR1_PB_10 (0x0400U << RI_HYSCR1_PB_Pos) /*!< 0x04000000 */
<> 148:21d94c44109e 6050 #define RI_HYSCR1_PB_11 (0x0800U << RI_HYSCR1_PB_Pos) /*!< 0x08000000 */
<> 148:21d94c44109e 6051 #define RI_HYSCR1_PB_12 (0x1000U << RI_HYSCR1_PB_Pos) /*!< 0x10000000 */
<> 148:21d94c44109e 6052 #define RI_HYSCR1_PB_13 (0x2000U << RI_HYSCR1_PB_Pos) /*!< 0x20000000 */
<> 148:21d94c44109e 6053 #define RI_HYSCR1_PB_14 (0x4000U << RI_HYSCR1_PB_Pos) /*!< 0x40000000 */
<> 148:21d94c44109e 6054 #define RI_HYSCR1_PB_15 (0x8000U << RI_HYSCR1_PB_Pos) /*!< 0x80000000 */
<> 148:21d94c44109e 6055
<> 148:21d94c44109e 6056 /******************** Bit definition for RI_HYSCR2 register ********************/
<> 148:21d94c44109e 6057 #define RI_HYSCR2_PC_Pos (0U)
<> 148:21d94c44109e 6058 #define RI_HYSCR2_PC_Msk (0xFFFFU << RI_HYSCR2_PC_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 6059 #define RI_HYSCR2_PC RI_HYSCR2_PC_Msk /*!< PC[15:0] Port C Hysteresis selection */
<> 148:21d94c44109e 6060 #define RI_HYSCR2_PC_0 (0x0001U << RI_HYSCR2_PC_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 6061 #define RI_HYSCR2_PC_1 (0x0002U << RI_HYSCR2_PC_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 6062 #define RI_HYSCR2_PC_2 (0x0004U << RI_HYSCR2_PC_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 6063 #define RI_HYSCR2_PC_3 (0x0008U << RI_HYSCR2_PC_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 6064 #define RI_HYSCR2_PC_4 (0x0010U << RI_HYSCR2_PC_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 6065 #define RI_HYSCR2_PC_5 (0x0020U << RI_HYSCR2_PC_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 6066 #define RI_HYSCR2_PC_6 (0x0040U << RI_HYSCR2_PC_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 6067 #define RI_HYSCR2_PC_7 (0x0080U << RI_HYSCR2_PC_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 6068 #define RI_HYSCR2_PC_8 (0x0100U << RI_HYSCR2_PC_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 6069 #define RI_HYSCR2_PC_9 (0x0200U << RI_HYSCR2_PC_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 6070 #define RI_HYSCR2_PC_10 (0x0400U << RI_HYSCR2_PC_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 6071 #define RI_HYSCR2_PC_11 (0x0800U << RI_HYSCR2_PC_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 6072 #define RI_HYSCR2_PC_12 (0x1000U << RI_HYSCR2_PC_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 6073 #define RI_HYSCR2_PC_13 (0x2000U << RI_HYSCR2_PC_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 6074 #define RI_HYSCR2_PC_14 (0x4000U << RI_HYSCR2_PC_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 6075 #define RI_HYSCR2_PC_15 (0x8000U << RI_HYSCR2_PC_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 6076
<> 148:21d94c44109e 6077 #define RI_HYSCR2_PD_Pos (16U)
<> 148:21d94c44109e 6078 #define RI_HYSCR2_PD_Msk (0xFFFFU << RI_HYSCR2_PD_Pos) /*!< 0xFFFF0000 */
<> 148:21d94c44109e 6079 #define RI_HYSCR2_PD RI_HYSCR2_PD_Msk /*!< PD[15:0] Port D Hysteresis selection */
<> 148:21d94c44109e 6080 #define RI_HYSCR2_PD_0 (0x0001U << RI_HYSCR2_PD_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 6081 #define RI_HYSCR2_PD_1 (0x0002U << RI_HYSCR2_PD_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 6082 #define RI_HYSCR2_PD_2 (0x0004U << RI_HYSCR2_PD_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 6083 #define RI_HYSCR2_PD_3 (0x0008U << RI_HYSCR2_PD_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 6084 #define RI_HYSCR2_PD_4 (0x0010U << RI_HYSCR2_PD_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 6085 #define RI_HYSCR2_PD_5 (0x0020U << RI_HYSCR2_PD_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 6086 #define RI_HYSCR2_PD_6 (0x0040U << RI_HYSCR2_PD_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 6087 #define RI_HYSCR2_PD_7 (0x0080U << RI_HYSCR2_PD_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 6088 #define RI_HYSCR2_PD_8 (0x0100U << RI_HYSCR2_PD_Pos) /*!< 0x01000000 */
<> 148:21d94c44109e 6089 #define RI_HYSCR2_PD_9 (0x0200U << RI_HYSCR2_PD_Pos) /*!< 0x02000000 */
<> 148:21d94c44109e 6090 #define RI_HYSCR2_PD_10 (0x0400U << RI_HYSCR2_PD_Pos) /*!< 0x04000000 */
<> 148:21d94c44109e 6091 #define RI_HYSCR2_PD_11 (0x0800U << RI_HYSCR2_PD_Pos) /*!< 0x08000000 */
<> 148:21d94c44109e 6092 #define RI_HYSCR2_PD_12 (0x1000U << RI_HYSCR2_PD_Pos) /*!< 0x10000000 */
<> 148:21d94c44109e 6093 #define RI_HYSCR2_PD_13 (0x2000U << RI_HYSCR2_PD_Pos) /*!< 0x20000000 */
<> 148:21d94c44109e 6094 #define RI_HYSCR2_PD_14 (0x4000U << RI_HYSCR2_PD_Pos) /*!< 0x40000000 */
<> 148:21d94c44109e 6095 #define RI_HYSCR2_PD_15 (0x8000U << RI_HYSCR2_PD_Pos) /*!< 0x80000000 */
<> 148:21d94c44109e 6096
<> 148:21d94c44109e 6097 /******************** Bit definition for RI_HYSCR3 register ********************/
<> 148:21d94c44109e 6098 #define RI_HYSCR3_PE_Pos (0U)
<> 148:21d94c44109e 6099 #define RI_HYSCR3_PE_Msk (0xFFFFU << RI_HYSCR3_PE_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 6100 #define RI_HYSCR3_PE RI_HYSCR3_PE_Msk /*!< PE[15:0] Port E Hysteresis selection */
<> 148:21d94c44109e 6101 #define RI_HYSCR3_PE_0 (0x0001U << RI_HYSCR3_PE_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 6102 #define RI_HYSCR3_PE_1 (0x0002U << RI_HYSCR3_PE_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 6103 #define RI_HYSCR3_PE_2 (0x0004U << RI_HYSCR3_PE_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 6104 #define RI_HYSCR3_PE_3 (0x0008U << RI_HYSCR3_PE_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 6105 #define RI_HYSCR3_PE_4 (0x0010U << RI_HYSCR3_PE_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 6106 #define RI_HYSCR3_PE_5 (0x0020U << RI_HYSCR3_PE_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 6107 #define RI_HYSCR3_PE_6 (0x0040U << RI_HYSCR3_PE_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 6108 #define RI_HYSCR3_PE_7 (0x0080U << RI_HYSCR3_PE_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 6109 #define RI_HYSCR3_PE_8 (0x0100U << RI_HYSCR3_PE_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 6110 #define RI_HYSCR3_PE_9 (0x0200U << RI_HYSCR3_PE_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 6111 #define RI_HYSCR3_PE_10 (0x0400U << RI_HYSCR3_PE_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 6112 #define RI_HYSCR3_PE_11 (0x0800U << RI_HYSCR3_PE_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 6113 #define RI_HYSCR3_PE_12 (0x1000U << RI_HYSCR3_PE_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 6114 #define RI_HYSCR3_PE_13 (0x2000U << RI_HYSCR3_PE_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 6115 #define RI_HYSCR3_PE_14 (0x4000U << RI_HYSCR3_PE_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 6116 #define RI_HYSCR3_PE_15 (0x8000U << RI_HYSCR3_PE_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 6117
<> 148:21d94c44109e 6118 /******************** Bit definition for RI_ASMR1 register ********************/
<> 148:21d94c44109e 6119 #define RI_ASMR1_PA_Pos (0U)
<> 148:21d94c44109e 6120 #define RI_ASMR1_PA_Msk (0xFFFFU << RI_ASMR1_PA_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 6121 #define RI_ASMR1_PA RI_ASMR1_PA_Msk /*!< PA[15:0] Port A selection*/
<> 148:21d94c44109e 6122 #define RI_ASMR1_PA_0 (0x0001U << RI_ASMR1_PA_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 6123 #define RI_ASMR1_PA_1 (0x0002U << RI_ASMR1_PA_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 6124 #define RI_ASMR1_PA_2 (0x0004U << RI_ASMR1_PA_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 6125 #define RI_ASMR1_PA_3 (0x0008U << RI_ASMR1_PA_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 6126 #define RI_ASMR1_PA_4 (0x0010U << RI_ASMR1_PA_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 6127 #define RI_ASMR1_PA_5 (0x0020U << RI_ASMR1_PA_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 6128 #define RI_ASMR1_PA_6 (0x0040U << RI_ASMR1_PA_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 6129 #define RI_ASMR1_PA_7 (0x0080U << RI_ASMR1_PA_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 6130 #define RI_ASMR1_PA_8 (0x0100U << RI_ASMR1_PA_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 6131 #define RI_ASMR1_PA_9 (0x0200U << RI_ASMR1_PA_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 6132 #define RI_ASMR1_PA_10 (0x0400U << RI_ASMR1_PA_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 6133 #define RI_ASMR1_PA_11 (0x0800U << RI_ASMR1_PA_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 6134 #define RI_ASMR1_PA_12 (0x1000U << RI_ASMR1_PA_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 6135 #define RI_ASMR1_PA_13 (0x2000U << RI_ASMR1_PA_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 6136 #define RI_ASMR1_PA_14 (0x4000U << RI_ASMR1_PA_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 6137 #define RI_ASMR1_PA_15 (0x8000U << RI_ASMR1_PA_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 6138
<> 148:21d94c44109e 6139 /******************** Bit definition for RI_CMR1 register ********************/
<> 148:21d94c44109e 6140 #define RI_CMR1_PA_Pos (0U)
<> 148:21d94c44109e 6141 #define RI_CMR1_PA_Msk (0xFFFFU << RI_CMR1_PA_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 6142 #define RI_CMR1_PA RI_CMR1_PA_Msk /*!< PA[15:0] Port A selection*/
<> 148:21d94c44109e 6143 #define RI_CMR1_PA_0 (0x0001U << RI_CMR1_PA_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 6144 #define RI_CMR1_PA_1 (0x0002U << RI_CMR1_PA_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 6145 #define RI_CMR1_PA_2 (0x0004U << RI_CMR1_PA_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 6146 #define RI_CMR1_PA_3 (0x0008U << RI_CMR1_PA_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 6147 #define RI_CMR1_PA_4 (0x0010U << RI_CMR1_PA_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 6148 #define RI_CMR1_PA_5 (0x0020U << RI_CMR1_PA_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 6149 #define RI_CMR1_PA_6 (0x0040U << RI_CMR1_PA_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 6150 #define RI_CMR1_PA_7 (0x0080U << RI_CMR1_PA_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 6151 #define RI_CMR1_PA_8 (0x0100U << RI_CMR1_PA_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 6152 #define RI_CMR1_PA_9 (0x0200U << RI_CMR1_PA_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 6153 #define RI_CMR1_PA_10 (0x0400U << RI_CMR1_PA_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 6154 #define RI_CMR1_PA_11 (0x0800U << RI_CMR1_PA_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 6155 #define RI_CMR1_PA_12 (0x1000U << RI_CMR1_PA_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 6156 #define RI_CMR1_PA_13 (0x2000U << RI_CMR1_PA_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 6157 #define RI_CMR1_PA_14 (0x4000U << RI_CMR1_PA_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 6158 #define RI_CMR1_PA_15 (0x8000U << RI_CMR1_PA_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 6159
<> 148:21d94c44109e 6160 /******************** Bit definition for RI_CICR1 register ********************/
<> 148:21d94c44109e 6161 #define RI_CICR1_PA_Pos (0U)
<> 148:21d94c44109e 6162 #define RI_CICR1_PA_Msk (0xFFFFU << RI_CICR1_PA_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 6163 #define RI_CICR1_PA RI_CICR1_PA_Msk /*!< PA[15:0] Port A selection*/
<> 148:21d94c44109e 6164 #define RI_CICR1_PA_0 (0x0001U << RI_CICR1_PA_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 6165 #define RI_CICR1_PA_1 (0x0002U << RI_CICR1_PA_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 6166 #define RI_CICR1_PA_2 (0x0004U << RI_CICR1_PA_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 6167 #define RI_CICR1_PA_3 (0x0008U << RI_CICR1_PA_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 6168 #define RI_CICR1_PA_4 (0x0010U << RI_CICR1_PA_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 6169 #define RI_CICR1_PA_5 (0x0020U << RI_CICR1_PA_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 6170 #define RI_CICR1_PA_6 (0x0040U << RI_CICR1_PA_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 6171 #define RI_CICR1_PA_7 (0x0080U << RI_CICR1_PA_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 6172 #define RI_CICR1_PA_8 (0x0100U << RI_CICR1_PA_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 6173 #define RI_CICR1_PA_9 (0x0200U << RI_CICR1_PA_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 6174 #define RI_CICR1_PA_10 (0x0400U << RI_CICR1_PA_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 6175 #define RI_CICR1_PA_11 (0x0800U << RI_CICR1_PA_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 6176 #define RI_CICR1_PA_12 (0x1000U << RI_CICR1_PA_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 6177 #define RI_CICR1_PA_13 (0x2000U << RI_CICR1_PA_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 6178 #define RI_CICR1_PA_14 (0x4000U << RI_CICR1_PA_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 6179 #define RI_CICR1_PA_15 (0x8000U << RI_CICR1_PA_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 6180
<> 148:21d94c44109e 6181 /******************** Bit definition for RI_ASMR2 register ********************/
<> 148:21d94c44109e 6182 #define RI_ASMR2_PB_Pos (0U)
<> 148:21d94c44109e 6183 #define RI_ASMR2_PB_Msk (0xFFFFU << RI_ASMR2_PB_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 6184 #define RI_ASMR2_PB RI_ASMR2_PB_Msk /*!< PB[15:0] Port B selection */
<> 148:21d94c44109e 6185 #define RI_ASMR2_PB_0 (0x0001U << RI_ASMR2_PB_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 6186 #define RI_ASMR2_PB_1 (0x0002U << RI_ASMR2_PB_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 6187 #define RI_ASMR2_PB_2 (0x0004U << RI_ASMR2_PB_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 6188 #define RI_ASMR2_PB_3 (0x0008U << RI_ASMR2_PB_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 6189 #define RI_ASMR2_PB_4 (0x0010U << RI_ASMR2_PB_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 6190 #define RI_ASMR2_PB_5 (0x0020U << RI_ASMR2_PB_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 6191 #define RI_ASMR2_PB_6 (0x0040U << RI_ASMR2_PB_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 6192 #define RI_ASMR2_PB_7 (0x0080U << RI_ASMR2_PB_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 6193 #define RI_ASMR2_PB_8 (0x0100U << RI_ASMR2_PB_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 6194 #define RI_ASMR2_PB_9 (0x0200U << RI_ASMR2_PB_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 6195 #define RI_ASMR2_PB_10 (0x0400U << RI_ASMR2_PB_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 6196 #define RI_ASMR2_PB_11 (0x0800U << RI_ASMR2_PB_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 6197 #define RI_ASMR2_PB_12 (0x1000U << RI_ASMR2_PB_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 6198 #define RI_ASMR2_PB_13 (0x2000U << RI_ASMR2_PB_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 6199 #define RI_ASMR2_PB_14 (0x4000U << RI_ASMR2_PB_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 6200 #define RI_ASMR2_PB_15 (0x8000U << RI_ASMR2_PB_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 6201
<> 148:21d94c44109e 6202 /******************** Bit definition for RI_CMR2 register ********************/
<> 148:21d94c44109e 6203 #define RI_CMR2_PB_Pos (0U)
<> 148:21d94c44109e 6204 #define RI_CMR2_PB_Msk (0xFFFFU << RI_CMR2_PB_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 6205 #define RI_CMR2_PB RI_CMR2_PB_Msk /*!< PB[15:0] Port B selection */
<> 148:21d94c44109e 6206 #define RI_CMR2_PB_0 (0x0001U << RI_CMR2_PB_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 6207 #define RI_CMR2_PB_1 (0x0002U << RI_CMR2_PB_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 6208 #define RI_CMR2_PB_2 (0x0004U << RI_CMR2_PB_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 6209 #define RI_CMR2_PB_3 (0x0008U << RI_CMR2_PB_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 6210 #define RI_CMR2_PB_4 (0x0010U << RI_CMR2_PB_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 6211 #define RI_CMR2_PB_5 (0x0020U << RI_CMR2_PB_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 6212 #define RI_CMR2_PB_6 (0x0040U << RI_CMR2_PB_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 6213 #define RI_CMR2_PB_7 (0x0080U << RI_CMR2_PB_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 6214 #define RI_CMR2_PB_8 (0x0100U << RI_CMR2_PB_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 6215 #define RI_CMR2_PB_9 (0x0200U << RI_CMR2_PB_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 6216 #define RI_CMR2_PB_10 (0x0400U << RI_CMR2_PB_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 6217 #define RI_CMR2_PB_11 (0x0800U << RI_CMR2_PB_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 6218 #define RI_CMR2_PB_12 (0x1000U << RI_CMR2_PB_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 6219 #define RI_CMR2_PB_13 (0x2000U << RI_CMR2_PB_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 6220 #define RI_CMR2_PB_14 (0x4000U << RI_CMR2_PB_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 6221 #define RI_CMR2_PB_15 (0x8000U << RI_CMR2_PB_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 6222
<> 148:21d94c44109e 6223 /******************** Bit definition for RI_CICR2 register ********************/
<> 148:21d94c44109e 6224 #define RI_CICR2_PB_Pos (0U)
<> 148:21d94c44109e 6225 #define RI_CICR2_PB_Msk (0xFFFFU << RI_CICR2_PB_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 6226 #define RI_CICR2_PB RI_CICR2_PB_Msk /*!< PB[15:0] Port B selection */
<> 148:21d94c44109e 6227 #define RI_CICR2_PB_0 (0x0001U << RI_CICR2_PB_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 6228 #define RI_CICR2_PB_1 (0x0002U << RI_CICR2_PB_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 6229 #define RI_CICR2_PB_2 (0x0004U << RI_CICR2_PB_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 6230 #define RI_CICR2_PB_3 (0x0008U << RI_CICR2_PB_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 6231 #define RI_CICR2_PB_4 (0x0010U << RI_CICR2_PB_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 6232 #define RI_CICR2_PB_5 (0x0020U << RI_CICR2_PB_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 6233 #define RI_CICR2_PB_6 (0x0040U << RI_CICR2_PB_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 6234 #define RI_CICR2_PB_7 (0x0080U << RI_CICR2_PB_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 6235 #define RI_CICR2_PB_8 (0x0100U << RI_CICR2_PB_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 6236 #define RI_CICR2_PB_9 (0x0200U << RI_CICR2_PB_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 6237 #define RI_CICR2_PB_10 (0x0400U << RI_CICR2_PB_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 6238 #define RI_CICR2_PB_11 (0x0800U << RI_CICR2_PB_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 6239 #define RI_CICR2_PB_12 (0x1000U << RI_CICR2_PB_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 6240 #define RI_CICR2_PB_13 (0x2000U << RI_CICR2_PB_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 6241 #define RI_CICR2_PB_14 (0x4000U << RI_CICR2_PB_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 6242 #define RI_CICR2_PB_15 (0x8000U << RI_CICR2_PB_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 6243
<> 148:21d94c44109e 6244 /******************** Bit definition for RI_ASMR3 register ********************/
<> 148:21d94c44109e 6245 #define RI_ASMR3_PC_Pos (0U)
<> 148:21d94c44109e 6246 #define RI_ASMR3_PC_Msk (0xFFFFU << RI_ASMR3_PC_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 6247 #define RI_ASMR3_PC RI_ASMR3_PC_Msk /*!< PC[15:0] Port C selection */
<> 148:21d94c44109e 6248 #define RI_ASMR3_PC_0 (0x0001U << RI_ASMR3_PC_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 6249 #define RI_ASMR3_PC_1 (0x0002U << RI_ASMR3_PC_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 6250 #define RI_ASMR3_PC_2 (0x0004U << RI_ASMR3_PC_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 6251 #define RI_ASMR3_PC_3 (0x0008U << RI_ASMR3_PC_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 6252 #define RI_ASMR3_PC_4 (0x0010U << RI_ASMR3_PC_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 6253 #define RI_ASMR3_PC_5 (0x0020U << RI_ASMR3_PC_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 6254 #define RI_ASMR3_PC_6 (0x0040U << RI_ASMR3_PC_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 6255 #define RI_ASMR3_PC_7 (0x0080U << RI_ASMR3_PC_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 6256 #define RI_ASMR3_PC_8 (0x0100U << RI_ASMR3_PC_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 6257 #define RI_ASMR3_PC_9 (0x0200U << RI_ASMR3_PC_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 6258 #define RI_ASMR3_PC_10 (0x0400U << RI_ASMR3_PC_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 6259 #define RI_ASMR3_PC_11 (0x0800U << RI_ASMR3_PC_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 6260 #define RI_ASMR3_PC_12 (0x1000U << RI_ASMR3_PC_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 6261 #define RI_ASMR3_PC_13 (0x2000U << RI_ASMR3_PC_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 6262 #define RI_ASMR3_PC_14 (0x4000U << RI_ASMR3_PC_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 6263 #define RI_ASMR3_PC_15 (0x8000U << RI_ASMR3_PC_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 6264
<> 148:21d94c44109e 6265 /******************** Bit definition for RI_CMR3 register ********************/
<> 148:21d94c44109e 6266 #define RI_CMR3_PC_Pos (0U)
<> 148:21d94c44109e 6267 #define RI_CMR3_PC_Msk (0xFFFFU << RI_CMR3_PC_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 6268 #define RI_CMR3_PC RI_CMR3_PC_Msk /*!< PC[15:0] Port C selection */
<> 148:21d94c44109e 6269 #define RI_CMR3_PC_0 (0x0001U << RI_CMR3_PC_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 6270 #define RI_CMR3_PC_1 (0x0002U << RI_CMR3_PC_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 6271 #define RI_CMR3_PC_2 (0x0004U << RI_CMR3_PC_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 6272 #define RI_CMR3_PC_3 (0x0008U << RI_CMR3_PC_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 6273 #define RI_CMR3_PC_4 (0x0010U << RI_CMR3_PC_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 6274 #define RI_CMR3_PC_5 (0x0020U << RI_CMR3_PC_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 6275 #define RI_CMR3_PC_6 (0x0040U << RI_CMR3_PC_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 6276 #define RI_CMR3_PC_7 (0x0080U << RI_CMR3_PC_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 6277 #define RI_CMR3_PC_8 (0x0100U << RI_CMR3_PC_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 6278 #define RI_CMR3_PC_9 (0x0200U << RI_CMR3_PC_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 6279 #define RI_CMR3_PC_10 (0x0400U << RI_CMR3_PC_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 6280 #define RI_CMR3_PC_11 (0x0800U << RI_CMR3_PC_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 6281 #define RI_CMR3_PC_12 (0x1000U << RI_CMR3_PC_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 6282 #define RI_CMR3_PC_13 (0x2000U << RI_CMR3_PC_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 6283 #define RI_CMR3_PC_14 (0x4000U << RI_CMR3_PC_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 6284 #define RI_CMR3_PC_15 (0x8000U << RI_CMR3_PC_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 6285
<> 148:21d94c44109e 6286 /******************** Bit definition for RI_CICR3 register ********************/
<> 148:21d94c44109e 6287 #define RI_CICR3_PC_Pos (0U)
<> 148:21d94c44109e 6288 #define RI_CICR3_PC_Msk (0xFFFFU << RI_CICR3_PC_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 6289 #define RI_CICR3_PC RI_CICR3_PC_Msk /*!< PC[15:0] Port C selection */
<> 148:21d94c44109e 6290 #define RI_CICR3_PC_0 (0x0001U << RI_CICR3_PC_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 6291 #define RI_CICR3_PC_1 (0x0002U << RI_CICR3_PC_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 6292 #define RI_CICR3_PC_2 (0x0004U << RI_CICR3_PC_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 6293 #define RI_CICR3_PC_3 (0x0008U << RI_CICR3_PC_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 6294 #define RI_CICR3_PC_4 (0x0010U << RI_CICR3_PC_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 6295 #define RI_CICR3_PC_5 (0x0020U << RI_CICR3_PC_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 6296 #define RI_CICR3_PC_6 (0x0040U << RI_CICR3_PC_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 6297 #define RI_CICR3_PC_7 (0x0080U << RI_CICR3_PC_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 6298 #define RI_CICR3_PC_8 (0x0100U << RI_CICR3_PC_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 6299 #define RI_CICR3_PC_9 (0x0200U << RI_CICR3_PC_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 6300 #define RI_CICR3_PC_10 (0x0400U << RI_CICR3_PC_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 6301 #define RI_CICR3_PC_11 (0x0800U << RI_CICR3_PC_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 6302 #define RI_CICR3_PC_12 (0x1000U << RI_CICR3_PC_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 6303 #define RI_CICR3_PC_13 (0x2000U << RI_CICR3_PC_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 6304 #define RI_CICR3_PC_14 (0x4000U << RI_CICR3_PC_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 6305 #define RI_CICR3_PC_15 (0x8000U << RI_CICR3_PC_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 6306
<> 148:21d94c44109e 6307 /******************************************************************************/
<> 148:21d94c44109e 6308 /* */
<> 148:21d94c44109e 6309 /* Timers (TIM) */
<> 148:21d94c44109e 6310 /* */
<> 148:21d94c44109e 6311 /******************************************************************************/
<> 148:21d94c44109e 6312
<> 148:21d94c44109e 6313 /******************* Bit definition for TIM_CR1 register ********************/
<> 148:21d94c44109e 6314 #define TIM_CR1_CEN_Pos (0U)
<> 148:21d94c44109e 6315 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 6316 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
<> 148:21d94c44109e 6317 #define TIM_CR1_UDIS_Pos (1U)
<> 148:21d94c44109e 6318 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 6319 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
<> 148:21d94c44109e 6320 #define TIM_CR1_URS_Pos (2U)
<> 148:21d94c44109e 6321 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 6322 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
<> 148:21d94c44109e 6323 #define TIM_CR1_OPM_Pos (3U)
<> 148:21d94c44109e 6324 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 6325 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
<> 148:21d94c44109e 6326 #define TIM_CR1_DIR_Pos (4U)
<> 148:21d94c44109e 6327 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 6328 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
<> 148:21d94c44109e 6329
<> 148:21d94c44109e 6330 #define TIM_CR1_CMS_Pos (5U)
<> 148:21d94c44109e 6331 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
<> 148:21d94c44109e 6332 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
<> 148:21d94c44109e 6333 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 6334 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 6335
<> 148:21d94c44109e 6336 #define TIM_CR1_ARPE_Pos (7U)
<> 148:21d94c44109e 6337 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 6338 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
<> 148:21d94c44109e 6339
<> 148:21d94c44109e 6340 #define TIM_CR1_CKD_Pos (8U)
<> 148:21d94c44109e 6341 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
<> 148:21d94c44109e 6342 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
<> 148:21d94c44109e 6343 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 6344 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 6345
<> 148:21d94c44109e 6346 /******************* Bit definition for TIM_CR2 register ********************/
<> 148:21d94c44109e 6347 #define TIM_CR2_CCDS_Pos (3U)
<> 148:21d94c44109e 6348 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 6349 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
<> 148:21d94c44109e 6350
<> 148:21d94c44109e 6351 #define TIM_CR2_MMS_Pos (4U)
<> 148:21d94c44109e 6352 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
<> 148:21d94c44109e 6353 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
<> 148:21d94c44109e 6354 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 6355 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 6356 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 6357
<> 148:21d94c44109e 6358 #define TIM_CR2_TI1S_Pos (7U)
<> 148:21d94c44109e 6359 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 6360 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
<> 148:21d94c44109e 6361
<> 148:21d94c44109e 6362 /******************* Bit definition for TIM_SMCR register *******************/
<> 148:21d94c44109e 6363 #define TIM_SMCR_SMS_Pos (0U)
<> 148:21d94c44109e 6364 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
<> 148:21d94c44109e 6365 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
<> 148:21d94c44109e 6366 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 6367 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 6368 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 6369
<> 148:21d94c44109e 6370 #define TIM_SMCR_OCCS_Pos (3U)
<> 148:21d94c44109e 6371 #define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 6372 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
<> 148:21d94c44109e 6373
<> 148:21d94c44109e 6374 #define TIM_SMCR_TS_Pos (4U)
<> 148:21d94c44109e 6375 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
<> 148:21d94c44109e 6376 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
<> 148:21d94c44109e 6377 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 6378 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 6379 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 6380
<> 148:21d94c44109e 6381 #define TIM_SMCR_MSM_Pos (7U)
<> 148:21d94c44109e 6382 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 6383 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
<> 148:21d94c44109e 6384
<> 148:21d94c44109e 6385 #define TIM_SMCR_ETF_Pos (8U)
<> 148:21d94c44109e 6386 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
<> 148:21d94c44109e 6387 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
<> 148:21d94c44109e 6388 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 6389 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 6390 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 6391 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 6392
<> 148:21d94c44109e 6393 #define TIM_SMCR_ETPS_Pos (12U)
<> 148:21d94c44109e 6394 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
<> 148:21d94c44109e 6395 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
<> 148:21d94c44109e 6396 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 6397 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 6398
<> 148:21d94c44109e 6399 #define TIM_SMCR_ECE_Pos (14U)
<> 148:21d94c44109e 6400 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 6401 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
<> 148:21d94c44109e 6402 #define TIM_SMCR_ETP_Pos (15U)
<> 148:21d94c44109e 6403 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 6404 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
<> 148:21d94c44109e 6405
<> 148:21d94c44109e 6406 /******************* Bit definition for TIM_DIER register *******************/
<> 148:21d94c44109e 6407 #define TIM_DIER_UIE_Pos (0U)
<> 148:21d94c44109e 6408 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 6409 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
<> 148:21d94c44109e 6410 #define TIM_DIER_CC1IE_Pos (1U)
<> 148:21d94c44109e 6411 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 6412 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
<> 148:21d94c44109e 6413 #define TIM_DIER_CC2IE_Pos (2U)
<> 148:21d94c44109e 6414 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 6415 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
<> 148:21d94c44109e 6416 #define TIM_DIER_CC3IE_Pos (3U)
<> 148:21d94c44109e 6417 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 6418 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
<> 148:21d94c44109e 6419 #define TIM_DIER_CC4IE_Pos (4U)
<> 148:21d94c44109e 6420 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 6421 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
<> 148:21d94c44109e 6422 #define TIM_DIER_TIE_Pos (6U)
<> 148:21d94c44109e 6423 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 6424 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
<> 148:21d94c44109e 6425 #define TIM_DIER_UDE_Pos (8U)
<> 148:21d94c44109e 6426 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 6427 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
<> 148:21d94c44109e 6428 #define TIM_DIER_CC1DE_Pos (9U)
<> 148:21d94c44109e 6429 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 6430 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
<> 148:21d94c44109e 6431 #define TIM_DIER_CC2DE_Pos (10U)
<> 148:21d94c44109e 6432 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 6433 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
<> 148:21d94c44109e 6434 #define TIM_DIER_CC3DE_Pos (11U)
<> 148:21d94c44109e 6435 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 6436 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
<> 148:21d94c44109e 6437 #define TIM_DIER_CC4DE_Pos (12U)
<> 148:21d94c44109e 6438 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 6439 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
<> 148:21d94c44109e 6440 #define TIM_DIER_COMDE ((uint16_t)0x2000U) /*!<COM DMA request enable */
<> 148:21d94c44109e 6441 #define TIM_DIER_TDE_Pos (14U)
<> 148:21d94c44109e 6442 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 6443 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
<> 148:21d94c44109e 6444
<> 148:21d94c44109e 6445 /******************** Bit definition for TIM_SR register ********************/
<> 148:21d94c44109e 6446 #define TIM_SR_UIF_Pos (0U)
<> 148:21d94c44109e 6447 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 6448 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
<> 148:21d94c44109e 6449 #define TIM_SR_CC1IF_Pos (1U)
<> 148:21d94c44109e 6450 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 6451 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
<> 148:21d94c44109e 6452 #define TIM_SR_CC2IF_Pos (2U)
<> 148:21d94c44109e 6453 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 6454 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
<> 148:21d94c44109e 6455 #define TIM_SR_CC3IF_Pos (3U)
<> 148:21d94c44109e 6456 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 6457 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
<> 148:21d94c44109e 6458 #define TIM_SR_CC4IF_Pos (4U)
<> 148:21d94c44109e 6459 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 6460 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
<> 148:21d94c44109e 6461 #define TIM_SR_TIF_Pos (6U)
<> 148:21d94c44109e 6462 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 6463 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
<> 148:21d94c44109e 6464 #define TIM_SR_CC1OF_Pos (9U)
<> 148:21d94c44109e 6465 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 6466 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
<> 148:21d94c44109e 6467 #define TIM_SR_CC2OF_Pos (10U)
<> 148:21d94c44109e 6468 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 6469 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
<> 148:21d94c44109e 6470 #define TIM_SR_CC3OF_Pos (11U)
<> 148:21d94c44109e 6471 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 6472 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
<> 148:21d94c44109e 6473 #define TIM_SR_CC4OF_Pos (12U)
<> 148:21d94c44109e 6474 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 6475 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
<> 148:21d94c44109e 6476
<> 148:21d94c44109e 6477 /******************* Bit definition for TIM_EGR register ********************/
<> 148:21d94c44109e 6478 #define TIM_EGR_UG_Pos (0U)
<> 148:21d94c44109e 6479 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 6480 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
<> 148:21d94c44109e 6481 #define TIM_EGR_CC1G_Pos (1U)
<> 148:21d94c44109e 6482 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 6483 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
<> 148:21d94c44109e 6484 #define TIM_EGR_CC2G_Pos (2U)
<> 148:21d94c44109e 6485 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 6486 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
<> 148:21d94c44109e 6487 #define TIM_EGR_CC3G_Pos (3U)
<> 148:21d94c44109e 6488 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 6489 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
<> 148:21d94c44109e 6490 #define TIM_EGR_CC4G_Pos (4U)
<> 148:21d94c44109e 6491 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 6492 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
<> 148:21d94c44109e 6493 #define TIM_EGR_TG_Pos (6U)
<> 148:21d94c44109e 6494 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 6495 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
<> 148:21d94c44109e 6496
<> 148:21d94c44109e 6497 /****************** Bit definition for TIM_CCMR1 register *******************/
<> 148:21d94c44109e 6498 #define TIM_CCMR1_CC1S_Pos (0U)
<> 148:21d94c44109e 6499 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
<> 148:21d94c44109e 6500 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
<> 148:21d94c44109e 6501 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 6502 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 6503
<> 148:21d94c44109e 6504 #define TIM_CCMR1_OC1FE_Pos (2U)
<> 148:21d94c44109e 6505 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 6506 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
<> 148:21d94c44109e 6507 #define TIM_CCMR1_OC1PE_Pos (3U)
<> 148:21d94c44109e 6508 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 6509 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
<> 148:21d94c44109e 6510
<> 148:21d94c44109e 6511 #define TIM_CCMR1_OC1M_Pos (4U)
<> 148:21d94c44109e 6512 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
<> 148:21d94c44109e 6513 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
<> 148:21d94c44109e 6514 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 6515 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 6516 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 6517
<> 148:21d94c44109e 6518 #define TIM_CCMR1_OC1CE_Pos (7U)
<> 148:21d94c44109e 6519 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 6520 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
<> 148:21d94c44109e 6521
<> 148:21d94c44109e 6522 #define TIM_CCMR1_CC2S_Pos (8U)
<> 148:21d94c44109e 6523 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
<> 148:21d94c44109e 6524 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
<> 148:21d94c44109e 6525 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 6526 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 6527
<> 148:21d94c44109e 6528 #define TIM_CCMR1_OC2FE_Pos (10U)
<> 148:21d94c44109e 6529 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 6530 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
<> 148:21d94c44109e 6531 #define TIM_CCMR1_OC2PE_Pos (11U)
<> 148:21d94c44109e 6532 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 6533 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
<> 148:21d94c44109e 6534
<> 148:21d94c44109e 6535 #define TIM_CCMR1_OC2M_Pos (12U)
<> 148:21d94c44109e 6536 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
<> 148:21d94c44109e 6537 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
<> 148:21d94c44109e 6538 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 6539 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 6540 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 6541
<> 148:21d94c44109e 6542 #define TIM_CCMR1_OC2CE_Pos (15U)
<> 148:21d94c44109e 6543 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 6544 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
<> 148:21d94c44109e 6545
<> 148:21d94c44109e 6546 /*----------------------------------------------------------------------------*/
<> 148:21d94c44109e 6547
<> 148:21d94c44109e 6548 #define TIM_CCMR1_IC1PSC_Pos (2U)
<> 148:21d94c44109e 6549 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
<> 148:21d94c44109e 6550 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
<> 148:21d94c44109e 6551 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 6552 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 6553
<> 148:21d94c44109e 6554 #define TIM_CCMR1_IC1F_Pos (4U)
<> 148:21d94c44109e 6555 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
<> 148:21d94c44109e 6556 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
<> 148:21d94c44109e 6557 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 6558 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 6559 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 6560 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 6561
<> 148:21d94c44109e 6562 #define TIM_CCMR1_IC2PSC_Pos (10U)
<> 148:21d94c44109e 6563 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
<> 148:21d94c44109e 6564 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
<> 148:21d94c44109e 6565 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 6566 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 6567
<> 148:21d94c44109e 6568 #define TIM_CCMR1_IC2F_Pos (12U)
<> 148:21d94c44109e 6569 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
<> 148:21d94c44109e 6570 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
<> 148:21d94c44109e 6571 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 6572 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 6573 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 6574 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 6575
<> 148:21d94c44109e 6576 /****************** Bit definition for TIM_CCMR2 register *******************/
<> 148:21d94c44109e 6577 #define TIM_CCMR2_CC3S_Pos (0U)
<> 148:21d94c44109e 6578 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
<> 148:21d94c44109e 6579 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
<> 148:21d94c44109e 6580 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 6581 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 6582
<> 148:21d94c44109e 6583 #define TIM_CCMR2_OC3FE_Pos (2U)
<> 148:21d94c44109e 6584 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 6585 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
<> 148:21d94c44109e 6586 #define TIM_CCMR2_OC3PE_Pos (3U)
<> 148:21d94c44109e 6587 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 6588 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
<> 148:21d94c44109e 6589
<> 148:21d94c44109e 6590 #define TIM_CCMR2_OC3M_Pos (4U)
<> 148:21d94c44109e 6591 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
<> 148:21d94c44109e 6592 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
<> 148:21d94c44109e 6593 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 6594 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 6595 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 6596
<> 148:21d94c44109e 6597 #define TIM_CCMR2_OC3CE_Pos (7U)
<> 148:21d94c44109e 6598 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 6599 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
<> 148:21d94c44109e 6600
<> 148:21d94c44109e 6601 #define TIM_CCMR2_CC4S_Pos (8U)
<> 148:21d94c44109e 6602 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
<> 148:21d94c44109e 6603 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
<> 148:21d94c44109e 6604 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 6605 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 6606
<> 148:21d94c44109e 6607 #define TIM_CCMR2_OC4FE_Pos (10U)
<> 148:21d94c44109e 6608 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 6609 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
<> 148:21d94c44109e 6610 #define TIM_CCMR2_OC4PE_Pos (11U)
<> 148:21d94c44109e 6611 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 6612 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
<> 148:21d94c44109e 6613
<> 148:21d94c44109e 6614 #define TIM_CCMR2_OC4M_Pos (12U)
<> 148:21d94c44109e 6615 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
<> 148:21d94c44109e 6616 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
<> 148:21d94c44109e 6617 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 6618 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 6619 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 6620
<> 148:21d94c44109e 6621 #define TIM_CCMR2_OC4CE_Pos (15U)
<> 148:21d94c44109e 6622 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 6623 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
<> 148:21d94c44109e 6624
<> 148:21d94c44109e 6625 /*----------------------------------------------------------------------------*/
<> 148:21d94c44109e 6626
<> 148:21d94c44109e 6627 #define TIM_CCMR2_IC3PSC_Pos (2U)
<> 148:21d94c44109e 6628 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
<> 148:21d94c44109e 6629 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
<> 148:21d94c44109e 6630 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 6631 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 6632
<> 148:21d94c44109e 6633 #define TIM_CCMR2_IC3F_Pos (4U)
<> 148:21d94c44109e 6634 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
<> 148:21d94c44109e 6635 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
<> 148:21d94c44109e 6636 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 6637 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 6638 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 6639 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 6640
<> 148:21d94c44109e 6641 #define TIM_CCMR2_IC4PSC_Pos (10U)
<> 148:21d94c44109e 6642 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
<> 148:21d94c44109e 6643 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
<> 148:21d94c44109e 6644 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 6645 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 6646
<> 148:21d94c44109e 6647 #define TIM_CCMR2_IC4F_Pos (12U)
<> 148:21d94c44109e 6648 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
<> 148:21d94c44109e 6649 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
<> 148:21d94c44109e 6650 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 6651 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 6652 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 6653 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 6654
<> 148:21d94c44109e 6655 /******************* Bit definition for TIM_CCER register *******************/
<> 148:21d94c44109e 6656 #define TIM_CCER_CC1E_Pos (0U)
<> 148:21d94c44109e 6657 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 6658 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
<> 148:21d94c44109e 6659 #define TIM_CCER_CC1P_Pos (1U)
<> 148:21d94c44109e 6660 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 6661 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
<> 148:21d94c44109e 6662 #define TIM_CCER_CC1NP_Pos (3U)
<> 148:21d94c44109e 6663 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 6664 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
<> 148:21d94c44109e 6665 #define TIM_CCER_CC2E_Pos (4U)
<> 148:21d94c44109e 6666 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 6667 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
<> 148:21d94c44109e 6668 #define TIM_CCER_CC2P_Pos (5U)
<> 148:21d94c44109e 6669 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 6670 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
<> 148:21d94c44109e 6671 #define TIM_CCER_CC2NP_Pos (7U)
<> 148:21d94c44109e 6672 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 6673 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
<> 148:21d94c44109e 6674 #define TIM_CCER_CC3E_Pos (8U)
<> 148:21d94c44109e 6675 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 6676 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
<> 148:21d94c44109e 6677 #define TIM_CCER_CC3P_Pos (9U)
<> 148:21d94c44109e 6678 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 6679 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
<> 148:21d94c44109e 6680 #define TIM_CCER_CC3NP_Pos (11U)
<> 148:21d94c44109e 6681 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 6682 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
<> 148:21d94c44109e 6683 #define TIM_CCER_CC4E_Pos (12U)
<> 148:21d94c44109e 6684 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 6685 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
<> 148:21d94c44109e 6686 #define TIM_CCER_CC4P_Pos (13U)
<> 148:21d94c44109e 6687 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 6688 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
<> 148:21d94c44109e 6689 #define TIM_CCER_CC4NP_Pos (15U)
<> 148:21d94c44109e 6690 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 6691 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
<> 148:21d94c44109e 6692
<> 148:21d94c44109e 6693 /******************* Bit definition for TIM_CNT register ********************/
<> 148:21d94c44109e 6694 #define TIM_CNT_CNT_Pos (0U)
<> 148:21d94c44109e 6695 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 6696 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
<> 148:21d94c44109e 6697
<> 148:21d94c44109e 6698 /******************* Bit definition for TIM_PSC register ********************/
<> 148:21d94c44109e 6699 #define TIM_PSC_PSC_Pos (0U)
<> 148:21d94c44109e 6700 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 6701 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
<> 148:21d94c44109e 6702
<> 148:21d94c44109e 6703 /******************* Bit definition for TIM_ARR register ********************/
<> 148:21d94c44109e 6704 #define TIM_ARR_ARR_Pos (0U)
<> 148:21d94c44109e 6705 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 6706 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
<> 148:21d94c44109e 6707
<> 148:21d94c44109e 6708 /******************* Bit definition for TIM_CCR1 register *******************/
<> 148:21d94c44109e 6709 #define TIM_CCR1_CCR1_Pos (0U)
<> 148:21d94c44109e 6710 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 6711 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
<> 148:21d94c44109e 6712
<> 148:21d94c44109e 6713 /******************* Bit definition for TIM_CCR2 register *******************/
<> 148:21d94c44109e 6714 #define TIM_CCR2_CCR2_Pos (0U)
<> 148:21d94c44109e 6715 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 6716 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
<> 148:21d94c44109e 6717
<> 148:21d94c44109e 6718 /******************* Bit definition for TIM_CCR3 register *******************/
<> 148:21d94c44109e 6719 #define TIM_CCR3_CCR3_Pos (0U)
<> 148:21d94c44109e 6720 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 6721 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
<> 148:21d94c44109e 6722
<> 148:21d94c44109e 6723 /******************* Bit definition for TIM_CCR4 register *******************/
<> 148:21d94c44109e 6724 #define TIM_CCR4_CCR4_Pos (0U)
<> 148:21d94c44109e 6725 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 6726 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
<> 148:21d94c44109e 6727
<> 148:21d94c44109e 6728 /******************* Bit definition for TIM_DCR register ********************/
<> 148:21d94c44109e 6729 #define TIM_DCR_DBA_Pos (0U)
<> 148:21d94c44109e 6730 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
<> 148:21d94c44109e 6731 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
<> 148:21d94c44109e 6732 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 6733 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 6734 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 6735 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 6736 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 6737
<> 148:21d94c44109e 6738 #define TIM_DCR_DBL_Pos (8U)
<> 148:21d94c44109e 6739 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
<> 148:21d94c44109e 6740 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
<> 148:21d94c44109e 6741 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 6742 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 6743 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 6744 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 6745 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 6746
<> 148:21d94c44109e 6747 /******************* Bit definition for TIM_DMAR register *******************/
<> 148:21d94c44109e 6748 #define TIM_DMAR_DMAB_Pos (0U)
<> 148:21d94c44109e 6749 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
<> 148:21d94c44109e 6750 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
<> 148:21d94c44109e 6751
<> 148:21d94c44109e 6752 /******************* Bit definition for TIM_OR register *********************/
<> 148:21d94c44109e 6753 #define TIM_OR_TI1RMP_Pos (0U)
<> 148:21d94c44109e 6754 #define TIM_OR_TI1RMP_Msk (0x3U << TIM_OR_TI1RMP_Pos) /*!< 0x00000003 */
<> 148:21d94c44109e 6755 #define TIM_OR_TI1RMP TIM_OR_TI1RMP_Msk /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
<> 148:21d94c44109e 6756 #define TIM_OR_TI1RMP_0 (0x1U << TIM_OR_TI1RMP_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 6757 #define TIM_OR_TI1RMP_1 (0x2U << TIM_OR_TI1RMP_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 6758
<> 148:21d94c44109e 6759 #define TIM_OR_ETR_RMP_Pos (2U)
<> 148:21d94c44109e 6760 #define TIM_OR_ETR_RMP_Msk (0x1U << TIM_OR_ETR_RMP_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 6761 #define TIM_OR_ETR_RMP TIM_OR_ETR_RMP_Msk /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
<> 148:21d94c44109e 6762 #define TIM_OR_TI1_RMP_RI_Pos (3U)
<> 148:21d94c44109e 6763 #define TIM_OR_TI1_RMP_RI_Msk (0x1U << TIM_OR_TI1_RMP_RI_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 6764 #define TIM_OR_TI1_RMP_RI TIM_OR_TI1_RMP_RI_Msk /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
<> 148:21d94c44109e 6765
<> 148:21d94c44109e 6766 /*----------------------------------------------------------------------------*/
<> 148:21d94c44109e 6767 #define TIM9_OR_ITR1_RMP_Pos (2U)
<> 148:21d94c44109e 6768 #define TIM9_OR_ITR1_RMP_Msk (0x1U << TIM9_OR_ITR1_RMP_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 6769 #define TIM9_OR_ITR1_RMP TIM9_OR_ITR1_RMP_Msk /*!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) */
<> 148:21d94c44109e 6770
<> 148:21d94c44109e 6771 /*----------------------------------------------------------------------------*/
<> 148:21d94c44109e 6772 #define TIM2_OR_ITR1_RMP_Pos (0U)
<> 148:21d94c44109e 6773 #define TIM2_OR_ITR1_RMP_Msk (0x1U << TIM2_OR_ITR1_RMP_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 6774 #define TIM2_OR_ITR1_RMP TIM2_OR_ITR1_RMP_Msk /*!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) */
<> 148:21d94c44109e 6775
<> 148:21d94c44109e 6776 /*----------------------------------------------------------------------------*/
<> 148:21d94c44109e 6777 #define TIM3_OR_ITR2_RMP_Pos (0U)
<> 148:21d94c44109e 6778 #define TIM3_OR_ITR2_RMP_Msk (0x1U << TIM3_OR_ITR2_RMP_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 6779 #define TIM3_OR_ITR2_RMP TIM3_OR_ITR2_RMP_Msk /*!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) */
<> 148:21d94c44109e 6780
<> 148:21d94c44109e 6781 /*----------------------------------------------------------------------------*/
<> 148:21d94c44109e 6782
<> 148:21d94c44109e 6783 /******************************************************************************/
<> 148:21d94c44109e 6784 /* */
<> 148:21d94c44109e 6785 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
<> 148:21d94c44109e 6786 /* */
<> 148:21d94c44109e 6787 /******************************************************************************/
<> 148:21d94c44109e 6788
<> 148:21d94c44109e 6789 /******************* Bit definition for USART_SR register *******************/
<> 148:21d94c44109e 6790 #define USART_SR_PE_Pos (0U)
<> 148:21d94c44109e 6791 #define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 6792 #define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */
<> 148:21d94c44109e 6793 #define USART_SR_FE_Pos (1U)
<> 148:21d94c44109e 6794 #define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 6795 #define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */
<> 148:21d94c44109e 6796 #define USART_SR_NE_Pos (2U)
<> 148:21d94c44109e 6797 #define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 6798 #define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */
<> 148:21d94c44109e 6799 #define USART_SR_ORE_Pos (3U)
<> 148:21d94c44109e 6800 #define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 6801 #define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */
<> 148:21d94c44109e 6802 #define USART_SR_IDLE_Pos (4U)
<> 148:21d94c44109e 6803 #define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 6804 #define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */
<> 148:21d94c44109e 6805 #define USART_SR_RXNE_Pos (5U)
<> 148:21d94c44109e 6806 #define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 6807 #define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */
<> 148:21d94c44109e 6808 #define USART_SR_TC_Pos (6U)
<> 148:21d94c44109e 6809 #define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 6810 #define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */
<> 148:21d94c44109e 6811 #define USART_SR_TXE_Pos (7U)
<> 148:21d94c44109e 6812 #define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 6813 #define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */
<> 148:21d94c44109e 6814 #define USART_SR_LBD_Pos (8U)
<> 148:21d94c44109e 6815 #define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 6816 #define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */
<> 148:21d94c44109e 6817 #define USART_SR_CTS_Pos (9U)
<> 148:21d94c44109e 6818 #define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 6819 #define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */
<> 148:21d94c44109e 6820
<> 148:21d94c44109e 6821 /******************* Bit definition for USART_DR register *******************/
<> 148:21d94c44109e 6822 #define USART_DR_DR_Pos (0U)
<> 148:21d94c44109e 6823 #define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
<> 148:21d94c44109e 6824 #define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
<> 148:21d94c44109e 6825
<> 148:21d94c44109e 6826 /****************** Bit definition for USART_BRR register *******************/
<> 148:21d94c44109e 6827 #define USART_BRR_DIV_FRACTION_Pos (0U)
<> 148:21d94c44109e 6828 #define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
<> 148:21d94c44109e 6829 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
<> 148:21d94c44109e 6830 #define USART_BRR_DIV_MANTISSA_Pos (4U)
<> 148:21d94c44109e 6831 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
<> 148:21d94c44109e 6832 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
<> 148:21d94c44109e 6833
<> 148:21d94c44109e 6834 /****************** Bit definition for USART_CR1 register *******************/
<> 148:21d94c44109e 6835 #define USART_CR1_SBK_Pos (0U)
<> 148:21d94c44109e 6836 #define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 6837 #define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */
<> 148:21d94c44109e 6838 #define USART_CR1_RWU_Pos (1U)
<> 148:21d94c44109e 6839 #define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 6840 #define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */
<> 148:21d94c44109e 6841 #define USART_CR1_RE_Pos (2U)
<> 148:21d94c44109e 6842 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 6843 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
<> 148:21d94c44109e 6844 #define USART_CR1_TE_Pos (3U)
<> 148:21d94c44109e 6845 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 6846 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
<> 148:21d94c44109e 6847 #define USART_CR1_IDLEIE_Pos (4U)
<> 148:21d94c44109e 6848 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 6849 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
<> 148:21d94c44109e 6850 #define USART_CR1_RXNEIE_Pos (5U)
<> 148:21d94c44109e 6851 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 6852 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
<> 148:21d94c44109e 6853 #define USART_CR1_TCIE_Pos (6U)
<> 148:21d94c44109e 6854 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 6855 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
<> 148:21d94c44109e 6856 #define USART_CR1_TXEIE_Pos (7U)
<> 148:21d94c44109e 6857 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 6858 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */
<> 148:21d94c44109e 6859 #define USART_CR1_PEIE_Pos (8U)
<> 148:21d94c44109e 6860 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 6861 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
<> 148:21d94c44109e 6862 #define USART_CR1_PS_Pos (9U)
<> 148:21d94c44109e 6863 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 6864 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
<> 148:21d94c44109e 6865 #define USART_CR1_PCE_Pos (10U)
<> 148:21d94c44109e 6866 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 6867 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
<> 148:21d94c44109e 6868 #define USART_CR1_WAKE_Pos (11U)
<> 148:21d94c44109e 6869 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 6870 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */
<> 148:21d94c44109e 6871 #define USART_CR1_M_Pos (12U)
<> 148:21d94c44109e 6872 #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 6873 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
<> 148:21d94c44109e 6874 #define USART_CR1_UE_Pos (13U)
<> 148:21d94c44109e 6875 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 6876 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
<> 148:21d94c44109e 6877 #define USART_CR1_OVER8_Pos (15U)
<> 148:21d94c44109e 6878 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 6879 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit mode */
<> 148:21d94c44109e 6880
<> 148:21d94c44109e 6881 /****************** Bit definition for USART_CR2 register *******************/
<> 148:21d94c44109e 6882 #define USART_CR2_ADD_Pos (0U)
<> 148:21d94c44109e 6883 #define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
<> 148:21d94c44109e 6884 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
<> 148:21d94c44109e 6885 #define USART_CR2_LBDL_Pos (5U)
<> 148:21d94c44109e 6886 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 6887 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
<> 148:21d94c44109e 6888 #define USART_CR2_LBDIE_Pos (6U)
<> 148:21d94c44109e 6889 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 6890 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
<> 148:21d94c44109e 6891 #define USART_CR2_LBCL_Pos (8U)
<> 148:21d94c44109e 6892 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 6893 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
<> 148:21d94c44109e 6894 #define USART_CR2_CPHA_Pos (9U)
<> 148:21d94c44109e 6895 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 6896 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
<> 148:21d94c44109e 6897 #define USART_CR2_CPOL_Pos (10U)
<> 148:21d94c44109e 6898 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 6899 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
<> 148:21d94c44109e 6900 #define USART_CR2_CLKEN_Pos (11U)
<> 148:21d94c44109e 6901 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 6902 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
<> 148:21d94c44109e 6903
<> 148:21d94c44109e 6904 #define USART_CR2_STOP_Pos (12U)
<> 148:21d94c44109e 6905 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
<> 148:21d94c44109e 6906 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
<> 148:21d94c44109e 6907 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 6908 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 6909
<> 148:21d94c44109e 6910 #define USART_CR2_LINEN_Pos (14U)
<> 148:21d94c44109e 6911 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 6912 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
<> 148:21d94c44109e 6913
<> 148:21d94c44109e 6914 /****************** Bit definition for USART_CR3 register *******************/
<> 148:21d94c44109e 6915 #define USART_CR3_EIE_Pos (0U)
<> 148:21d94c44109e 6916 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 6917 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
<> 148:21d94c44109e 6918 #define USART_CR3_IREN_Pos (1U)
<> 148:21d94c44109e 6919 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 6920 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
<> 148:21d94c44109e 6921 #define USART_CR3_IRLP_Pos (2U)
<> 148:21d94c44109e 6922 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 6923 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
<> 148:21d94c44109e 6924 #define USART_CR3_HDSEL_Pos (3U)
<> 148:21d94c44109e 6925 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 6926 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
<> 148:21d94c44109e 6927 #define USART_CR3_NACK_Pos (4U)
<> 148:21d94c44109e 6928 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 6929 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */
<> 148:21d94c44109e 6930 #define USART_CR3_SCEN_Pos (5U)
<> 148:21d94c44109e 6931 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 6932 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */
<> 148:21d94c44109e 6933 #define USART_CR3_DMAR_Pos (6U)
<> 148:21d94c44109e 6934 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 6935 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
<> 148:21d94c44109e 6936 #define USART_CR3_DMAT_Pos (7U)
<> 148:21d94c44109e 6937 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 6938 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
<> 148:21d94c44109e 6939 #define USART_CR3_RTSE_Pos (8U)
<> 148:21d94c44109e 6940 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 6941 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
<> 148:21d94c44109e 6942 #define USART_CR3_CTSE_Pos (9U)
<> 148:21d94c44109e 6943 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 6944 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
<> 148:21d94c44109e 6945 #define USART_CR3_CTSIE_Pos (10U)
<> 148:21d94c44109e 6946 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 6947 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
<> 148:21d94c44109e 6948 #define USART_CR3_ONEBIT_Pos (11U)
<> 148:21d94c44109e 6949 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 6950 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
<> 148:21d94c44109e 6951
<> 148:21d94c44109e 6952 /****************** Bit definition for USART_GTPR register ******************/
<> 148:21d94c44109e 6953 #define USART_GTPR_PSC_Pos (0U)
<> 148:21d94c44109e 6954 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
<> 148:21d94c44109e 6955 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
<> 148:21d94c44109e 6956 #define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 6957 #define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 6958 #define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 6959 #define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 6960 #define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 6961 #define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 6962 #define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 6963 #define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 6964
<> 148:21d94c44109e 6965 #define USART_GTPR_GT_Pos (8U)
<> 148:21d94c44109e 6966 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
<> 148:21d94c44109e 6967 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */
<> 148:21d94c44109e 6968
<> 148:21d94c44109e 6969 /******************************************************************************/
<> 148:21d94c44109e 6970 /* */
<> 148:21d94c44109e 6971 /* Universal Serial Bus (USB) */
<> 148:21d94c44109e 6972 /* */
<> 148:21d94c44109e 6973 /******************************************************************************/
<> 148:21d94c44109e 6974
<> 148:21d94c44109e 6975 /*!<Endpoint-specific registers */
<> 148:21d94c44109e 6976
<> 148:21d94c44109e 6977 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
<> 148:21d94c44109e 6978 #define USB_EP1R (USB_BASE + 0x00000004U) /*!< endpoint 1 register address */
<> 148:21d94c44109e 6979 #define USB_EP2R (USB_BASE + 0x00000008U) /*!< endpoint 2 register address */
<> 148:21d94c44109e 6980 #define USB_EP3R (USB_BASE + 0x0000000CU) /*!< endpoint 3 register address */
<> 148:21d94c44109e 6981 #define USB_EP4R (USB_BASE + 0x00000010U) /*!< endpoint 4 register address */
<> 148:21d94c44109e 6982 #define USB_EP5R (USB_BASE + 0x00000014U) /*!< endpoint 5 register address */
<> 148:21d94c44109e 6983 #define USB_EP6R (USB_BASE + 0x00000018U) /*!< endpoint 6 register address */
<> 148:21d94c44109e 6984 #define USB_EP7R (USB_BASE + 0x0000001CU) /*!< endpoint 7 register address */
<> 148:21d94c44109e 6985
<> 148:21d94c44109e 6986 /* bit positions */
<> 148:21d94c44109e 6987 #define USB_EP_CTR_RX_Pos (15U)
<> 148:21d94c44109e 6988 #define USB_EP_CTR_RX_Msk (0x1U << USB_EP_CTR_RX_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 6989 #define USB_EP_CTR_RX USB_EP_CTR_RX_Msk /*!< EndPoint Correct TRansfer RX */
<> 148:21d94c44109e 6990 #define USB_EP_DTOG_RX_Pos (14U)
<> 148:21d94c44109e 6991 #define USB_EP_DTOG_RX_Msk (0x1U << USB_EP_DTOG_RX_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 6992 #define USB_EP_DTOG_RX USB_EP_DTOG_RX_Msk /*!< EndPoint Data TOGGLE RX */
<> 148:21d94c44109e 6993 #define USB_EPRX_STAT_Pos (12U)
<> 148:21d94c44109e 6994 #define USB_EPRX_STAT_Msk (0x3U << USB_EPRX_STAT_Pos) /*!< 0x00003000 */
<> 148:21d94c44109e 6995 #define USB_EPRX_STAT USB_EPRX_STAT_Msk /*!< EndPoint RX STATus bit field */
<> 148:21d94c44109e 6996 #define USB_EP_SETUP_Pos (11U)
<> 148:21d94c44109e 6997 #define USB_EP_SETUP_Msk (0x1U << USB_EP_SETUP_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 6998 #define USB_EP_SETUP USB_EP_SETUP_Msk /*!< EndPoint SETUP */
<> 148:21d94c44109e 6999 #define USB_EP_T_FIELD_Pos (9U)
<> 148:21d94c44109e 7000 #define USB_EP_T_FIELD_Msk (0x3U << USB_EP_T_FIELD_Pos) /*!< 0x00000600 */
<> 148:21d94c44109e 7001 #define USB_EP_T_FIELD USB_EP_T_FIELD_Msk /*!< EndPoint TYPE */
<> 148:21d94c44109e 7002 #define USB_EP_KIND_Pos (8U)
<> 148:21d94c44109e 7003 #define USB_EP_KIND_Msk (0x1U << USB_EP_KIND_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 7004 #define USB_EP_KIND USB_EP_KIND_Msk /*!< EndPoint KIND */
<> 148:21d94c44109e 7005 #define USB_EP_CTR_TX_Pos (7U)
<> 148:21d94c44109e 7006 #define USB_EP_CTR_TX_Msk (0x1U << USB_EP_CTR_TX_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 7007 #define USB_EP_CTR_TX USB_EP_CTR_TX_Msk /*!< EndPoint Correct TRansfer TX */
<> 148:21d94c44109e 7008 #define USB_EP_DTOG_TX_Pos (6U)
<> 148:21d94c44109e 7009 #define USB_EP_DTOG_TX_Msk (0x1U << USB_EP_DTOG_TX_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 7010 #define USB_EP_DTOG_TX USB_EP_DTOG_TX_Msk /*!< EndPoint Data TOGGLE TX */
<> 148:21d94c44109e 7011 #define USB_EPTX_STAT_Pos (4U)
<> 148:21d94c44109e 7012 #define USB_EPTX_STAT_Msk (0x3U << USB_EPTX_STAT_Pos) /*!< 0x00000030 */
<> 148:21d94c44109e 7013 #define USB_EPTX_STAT USB_EPTX_STAT_Msk /*!< EndPoint TX STATus bit field */
<> 148:21d94c44109e 7014 #define USB_EPADDR_FIELD_Pos (0U)
<> 148:21d94c44109e 7015 #define USB_EPADDR_FIELD_Msk (0xFU << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */
<> 148:21d94c44109e 7016 #define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /*!< EndPoint ADDRess FIELD */
<> 148:21d94c44109e 7017
<> 148:21d94c44109e 7018 /* EndPoint REGister MASK (no toggle fields) */
<> 148:21d94c44109e 7019 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
<> 148:21d94c44109e 7020 /*!< EP_TYPE[1:0] EndPoint TYPE */
<> 148:21d94c44109e 7021 #define USB_EP_TYPE_MASK_Pos (9U)
<> 148:21d94c44109e 7022 #define USB_EP_TYPE_MASK_Msk (0x3U << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */
<> 148:21d94c44109e 7023 #define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */
<> 148:21d94c44109e 7024 #define USB_EP_BULK (0x00000000U) /*!< EndPoint BULK */
<> 148:21d94c44109e 7025 #define USB_EP_CONTROL (0x00000200U) /*!< EndPoint CONTROL */
<> 148:21d94c44109e 7026 #define USB_EP_ISOCHRONOUS (0x00000400U) /*!< EndPoint ISOCHRONOUS */
<> 148:21d94c44109e 7027 #define USB_EP_INTERRUPT (0x00000600U) /*!< EndPoint INTERRUPT */
<> 148:21d94c44109e 7028 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
<> 148:21d94c44109e 7029
<> 148:21d94c44109e 7030 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
<> 148:21d94c44109e 7031 /*!< STAT_TX[1:0] STATus for TX transfer */
<> 148:21d94c44109e 7032 #define USB_EP_TX_DIS (0x00000000U) /*!< EndPoint TX DISabled */
<> 148:21d94c44109e 7033 #define USB_EP_TX_STALL (0x00000010U) /*!< EndPoint TX STALLed */
<> 148:21d94c44109e 7034 #define USB_EP_TX_NAK (0x00000020U) /*!< EndPoint TX NAKed */
<> 148:21d94c44109e 7035 #define USB_EP_TX_VALID (0x00000030U) /*!< EndPoint TX VALID */
<> 148:21d94c44109e 7036 #define USB_EPTX_DTOG1 (0x00000010U) /*!< EndPoint TX Data TOGgle bit1 */
<> 148:21d94c44109e 7037 #define USB_EPTX_DTOG2 (0x00000020U) /*!< EndPoint TX Data TOGgle bit2 */
<> 148:21d94c44109e 7038 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
<> 148:21d94c44109e 7039 /*!< STAT_RX[1:0] STATus for RX transfer */
<> 148:21d94c44109e 7040 #define USB_EP_RX_DIS (0x00000000U) /*!< EndPoint RX DISabled */
<> 148:21d94c44109e 7041 #define USB_EP_RX_STALL (0x00001000U) /*!< EndPoint RX STALLed */
<> 148:21d94c44109e 7042 #define USB_EP_RX_NAK (0x00002000U) /*!< EndPoint RX NAKed */
<> 148:21d94c44109e 7043 #define USB_EP_RX_VALID (0x00003000U) /*!< EndPoint RX VALID */
<> 148:21d94c44109e 7044 #define USB_EPRX_DTOG1 (0x00001000U) /*!< EndPoint RX Data TOGgle bit1 */
<> 148:21d94c44109e 7045 #define USB_EPRX_DTOG2 (0x00002000U) /*!< EndPoint RX Data TOGgle bit1 */
<> 148:21d94c44109e 7046 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
<> 148:21d94c44109e 7047
<> 148:21d94c44109e 7048 /******************* Bit definition for USB_EP0R register *******************/
<> 148:21d94c44109e 7049 #define USB_EP0R_EA_Pos (0U)
<> 148:21d94c44109e 7050 #define USB_EP0R_EA_Msk (0xFU << USB_EP0R_EA_Pos) /*!< 0x0000000F */
<> 148:21d94c44109e 7051 #define USB_EP0R_EA USB_EP0R_EA_Msk /*!<Endpoint Address */
<> 148:21d94c44109e 7052
<> 148:21d94c44109e 7053 #define USB_EP0R_STAT_TX_Pos (4U)
<> 148:21d94c44109e 7054 #define USB_EP0R_STAT_TX_Msk (0x3U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */
<> 148:21d94c44109e 7055 #define USB_EP0R_STAT_TX USB_EP0R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
<> 148:21d94c44109e 7056 #define USB_EP0R_STAT_TX_0 (0x1U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 7057 #define USB_EP0R_STAT_TX_1 (0x2U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 7058
<> 148:21d94c44109e 7059 #define USB_EP0R_DTOG_TX_Pos (6U)
<> 148:21d94c44109e 7060 #define USB_EP0R_DTOG_TX_Msk (0x1U << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 7061 #define USB_EP0R_DTOG_TX USB_EP0R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */
<> 148:21d94c44109e 7062 #define USB_EP0R_CTR_TX_Pos (7U)
<> 148:21d94c44109e 7063 #define USB_EP0R_CTR_TX_Msk (0x1U << USB_EP0R_CTR_TX_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 7064 #define USB_EP0R_CTR_TX USB_EP0R_CTR_TX_Msk /*!<Correct Transfer for transmission */
<> 148:21d94c44109e 7065 #define USB_EP0R_EP_KIND_Pos (8U)
<> 148:21d94c44109e 7066 #define USB_EP0R_EP_KIND_Msk (0x1U << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 7067 #define USB_EP0R_EP_KIND USB_EP0R_EP_KIND_Msk /*!<Endpoint Kind */
<> 148:21d94c44109e 7068
<> 148:21d94c44109e 7069 #define USB_EP0R_EP_TYPE_Pos (9U)
<> 148:21d94c44109e 7070 #define USB_EP0R_EP_TYPE_Msk (0x3U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */
<> 148:21d94c44109e 7071 #define USB_EP0R_EP_TYPE USB_EP0R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */
<> 148:21d94c44109e 7072 #define USB_EP0R_EP_TYPE_0 (0x1U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 7073 #define USB_EP0R_EP_TYPE_1 (0x2U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 7074
<> 148:21d94c44109e 7075 #define USB_EP0R_SETUP_Pos (11U)
<> 148:21d94c44109e 7076 #define USB_EP0R_SETUP_Msk (0x1U << USB_EP0R_SETUP_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 7077 #define USB_EP0R_SETUP USB_EP0R_SETUP_Msk /*!<Setup transaction completed */
<> 148:21d94c44109e 7078
<> 148:21d94c44109e 7079 #define USB_EP0R_STAT_RX_Pos (12U)
<> 148:21d94c44109e 7080 #define USB_EP0R_STAT_RX_Msk (0x3U << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */
<> 148:21d94c44109e 7081 #define USB_EP0R_STAT_RX USB_EP0R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
<> 148:21d94c44109e 7082 #define USB_EP0R_STAT_RX_0 (0x1U << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 7083 #define USB_EP0R_STAT_RX_1 (0x2U << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 7084
<> 148:21d94c44109e 7085 #define USB_EP0R_DTOG_RX_Pos (14U)
<> 148:21d94c44109e 7086 #define USB_EP0R_DTOG_RX_Msk (0x1U << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 7087 #define USB_EP0R_DTOG_RX USB_EP0R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */
<> 148:21d94c44109e 7088 #define USB_EP0R_CTR_RX_Pos (15U)
<> 148:21d94c44109e 7089 #define USB_EP0R_CTR_RX_Msk (0x1U << USB_EP0R_CTR_RX_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 7090 #define USB_EP0R_CTR_RX USB_EP0R_CTR_RX_Msk /*!<Correct Transfer for reception */
<> 148:21d94c44109e 7091
<> 148:21d94c44109e 7092 /******************* Bit definition for USB_EP1R register *******************/
<> 148:21d94c44109e 7093 #define USB_EP1R_EA_Pos (0U)
<> 148:21d94c44109e 7094 #define USB_EP1R_EA_Msk (0xFU << USB_EP1R_EA_Pos) /*!< 0x0000000F */
<> 148:21d94c44109e 7095 #define USB_EP1R_EA USB_EP1R_EA_Msk /*!<Endpoint Address */
<> 148:21d94c44109e 7096
<> 148:21d94c44109e 7097 #define USB_EP1R_STAT_TX_Pos (4U)
<> 148:21d94c44109e 7098 #define USB_EP1R_STAT_TX_Msk (0x3U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */
<> 148:21d94c44109e 7099 #define USB_EP1R_STAT_TX USB_EP1R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
<> 148:21d94c44109e 7100 #define USB_EP1R_STAT_TX_0 (0x1U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 7101 #define USB_EP1R_STAT_TX_1 (0x2U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 7102
<> 148:21d94c44109e 7103 #define USB_EP1R_DTOG_TX_Pos (6U)
<> 148:21d94c44109e 7104 #define USB_EP1R_DTOG_TX_Msk (0x1U << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 7105 #define USB_EP1R_DTOG_TX USB_EP1R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */
<> 148:21d94c44109e 7106 #define USB_EP1R_CTR_TX_Pos (7U)
<> 148:21d94c44109e 7107 #define USB_EP1R_CTR_TX_Msk (0x1U << USB_EP1R_CTR_TX_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 7108 #define USB_EP1R_CTR_TX USB_EP1R_CTR_TX_Msk /*!<Correct Transfer for transmission */
<> 148:21d94c44109e 7109 #define USB_EP1R_EP_KIND_Pos (8U)
<> 148:21d94c44109e 7110 #define USB_EP1R_EP_KIND_Msk (0x1U << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 7111 #define USB_EP1R_EP_KIND USB_EP1R_EP_KIND_Msk /*!<Endpoint Kind */
<> 148:21d94c44109e 7112
<> 148:21d94c44109e 7113 #define USB_EP1R_EP_TYPE_Pos (9U)
<> 148:21d94c44109e 7114 #define USB_EP1R_EP_TYPE_Msk (0x3U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */
<> 148:21d94c44109e 7115 #define USB_EP1R_EP_TYPE USB_EP1R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */
<> 148:21d94c44109e 7116 #define USB_EP1R_EP_TYPE_0 (0x1U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 7117 #define USB_EP1R_EP_TYPE_1 (0x2U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 7118
<> 148:21d94c44109e 7119 #define USB_EP1R_SETUP_Pos (11U)
<> 148:21d94c44109e 7120 #define USB_EP1R_SETUP_Msk (0x1U << USB_EP1R_SETUP_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 7121 #define USB_EP1R_SETUP USB_EP1R_SETUP_Msk /*!<Setup transaction completed */
<> 148:21d94c44109e 7122
<> 148:21d94c44109e 7123 #define USB_EP1R_STAT_RX_Pos (12U)
<> 148:21d94c44109e 7124 #define USB_EP1R_STAT_RX_Msk (0x3U << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */
<> 148:21d94c44109e 7125 #define USB_EP1R_STAT_RX USB_EP1R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
<> 148:21d94c44109e 7126 #define USB_EP1R_STAT_RX_0 (0x1U << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 7127 #define USB_EP1R_STAT_RX_1 (0x2U << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 7128
<> 148:21d94c44109e 7129 #define USB_EP1R_DTOG_RX_Pos (14U)
<> 148:21d94c44109e 7130 #define USB_EP1R_DTOG_RX_Msk (0x1U << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 7131 #define USB_EP1R_DTOG_RX USB_EP1R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */
<> 148:21d94c44109e 7132 #define USB_EP1R_CTR_RX_Pos (15U)
<> 148:21d94c44109e 7133 #define USB_EP1R_CTR_RX_Msk (0x1U << USB_EP1R_CTR_RX_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 7134 #define USB_EP1R_CTR_RX USB_EP1R_CTR_RX_Msk /*!<Correct Transfer for reception */
<> 148:21d94c44109e 7135
<> 148:21d94c44109e 7136 /******************* Bit definition for USB_EP2R register *******************/
<> 148:21d94c44109e 7137 #define USB_EP2R_EA_Pos (0U)
<> 148:21d94c44109e 7138 #define USB_EP2R_EA_Msk (0xFU << USB_EP2R_EA_Pos) /*!< 0x0000000F */
<> 148:21d94c44109e 7139 #define USB_EP2R_EA USB_EP2R_EA_Msk /*!<Endpoint Address */
<> 148:21d94c44109e 7140
<> 148:21d94c44109e 7141 #define USB_EP2R_STAT_TX_Pos (4U)
<> 148:21d94c44109e 7142 #define USB_EP2R_STAT_TX_Msk (0x3U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */
<> 148:21d94c44109e 7143 #define USB_EP2R_STAT_TX USB_EP2R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
<> 148:21d94c44109e 7144 #define USB_EP2R_STAT_TX_0 (0x1U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 7145 #define USB_EP2R_STAT_TX_1 (0x2U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 7146
<> 148:21d94c44109e 7147 #define USB_EP2R_DTOG_TX_Pos (6U)
<> 148:21d94c44109e 7148 #define USB_EP2R_DTOG_TX_Msk (0x1U << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 7149 #define USB_EP2R_DTOG_TX USB_EP2R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */
<> 148:21d94c44109e 7150 #define USB_EP2R_CTR_TX_Pos (7U)
<> 148:21d94c44109e 7151 #define USB_EP2R_CTR_TX_Msk (0x1U << USB_EP2R_CTR_TX_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 7152 #define USB_EP2R_CTR_TX USB_EP2R_CTR_TX_Msk /*!<Correct Transfer for transmission */
<> 148:21d94c44109e 7153 #define USB_EP2R_EP_KIND_Pos (8U)
<> 148:21d94c44109e 7154 #define USB_EP2R_EP_KIND_Msk (0x1U << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 7155 #define USB_EP2R_EP_KIND USB_EP2R_EP_KIND_Msk /*!<Endpoint Kind */
<> 148:21d94c44109e 7156
<> 148:21d94c44109e 7157 #define USB_EP2R_EP_TYPE_Pos (9U)
<> 148:21d94c44109e 7158 #define USB_EP2R_EP_TYPE_Msk (0x3U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */
<> 148:21d94c44109e 7159 #define USB_EP2R_EP_TYPE USB_EP2R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */
<> 148:21d94c44109e 7160 #define USB_EP2R_EP_TYPE_0 (0x1U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 7161 #define USB_EP2R_EP_TYPE_1 (0x2U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 7162
<> 148:21d94c44109e 7163 #define USB_EP2R_SETUP_Pos (11U)
<> 148:21d94c44109e 7164 #define USB_EP2R_SETUP_Msk (0x1U << USB_EP2R_SETUP_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 7165 #define USB_EP2R_SETUP USB_EP2R_SETUP_Msk /*!<Setup transaction completed */
<> 148:21d94c44109e 7166
<> 148:21d94c44109e 7167 #define USB_EP2R_STAT_RX_Pos (12U)
<> 148:21d94c44109e 7168 #define USB_EP2R_STAT_RX_Msk (0x3U << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */
<> 148:21d94c44109e 7169 #define USB_EP2R_STAT_RX USB_EP2R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
<> 148:21d94c44109e 7170 #define USB_EP2R_STAT_RX_0 (0x1U << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 7171 #define USB_EP2R_STAT_RX_1 (0x2U << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 7172
<> 148:21d94c44109e 7173 #define USB_EP2R_DTOG_RX_Pos (14U)
<> 148:21d94c44109e 7174 #define USB_EP2R_DTOG_RX_Msk (0x1U << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 7175 #define USB_EP2R_DTOG_RX USB_EP2R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */
<> 148:21d94c44109e 7176 #define USB_EP2R_CTR_RX_Pos (15U)
<> 148:21d94c44109e 7177 #define USB_EP2R_CTR_RX_Msk (0x1U << USB_EP2R_CTR_RX_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 7178 #define USB_EP2R_CTR_RX USB_EP2R_CTR_RX_Msk /*!<Correct Transfer for reception */
<> 148:21d94c44109e 7179
<> 148:21d94c44109e 7180 /******************* Bit definition for USB_EP3R register *******************/
<> 148:21d94c44109e 7181 #define USB_EP3R_EA_Pos (0U)
<> 148:21d94c44109e 7182 #define USB_EP3R_EA_Msk (0xFU << USB_EP3R_EA_Pos) /*!< 0x0000000F */
<> 148:21d94c44109e 7183 #define USB_EP3R_EA USB_EP3R_EA_Msk /*!<Endpoint Address */
<> 148:21d94c44109e 7184
<> 148:21d94c44109e 7185 #define USB_EP3R_STAT_TX_Pos (4U)
<> 148:21d94c44109e 7186 #define USB_EP3R_STAT_TX_Msk (0x3U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */
<> 148:21d94c44109e 7187 #define USB_EP3R_STAT_TX USB_EP3R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
<> 148:21d94c44109e 7188 #define USB_EP3R_STAT_TX_0 (0x1U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 7189 #define USB_EP3R_STAT_TX_1 (0x2U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 7190
<> 148:21d94c44109e 7191 #define USB_EP3R_DTOG_TX_Pos (6U)
<> 148:21d94c44109e 7192 #define USB_EP3R_DTOG_TX_Msk (0x1U << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 7193 #define USB_EP3R_DTOG_TX USB_EP3R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */
<> 148:21d94c44109e 7194 #define USB_EP3R_CTR_TX_Pos (7U)
<> 148:21d94c44109e 7195 #define USB_EP3R_CTR_TX_Msk (0x1U << USB_EP3R_CTR_TX_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 7196 #define USB_EP3R_CTR_TX USB_EP3R_CTR_TX_Msk /*!<Correct Transfer for transmission */
<> 148:21d94c44109e 7197 #define USB_EP3R_EP_KIND_Pos (8U)
<> 148:21d94c44109e 7198 #define USB_EP3R_EP_KIND_Msk (0x1U << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 7199 #define USB_EP3R_EP_KIND USB_EP3R_EP_KIND_Msk /*!<Endpoint Kind */
<> 148:21d94c44109e 7200
<> 148:21d94c44109e 7201 #define USB_EP3R_EP_TYPE_Pos (9U)
<> 148:21d94c44109e 7202 #define USB_EP3R_EP_TYPE_Msk (0x3U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */
<> 148:21d94c44109e 7203 #define USB_EP3R_EP_TYPE USB_EP3R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */
<> 148:21d94c44109e 7204 #define USB_EP3R_EP_TYPE_0 (0x1U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 7205 #define USB_EP3R_EP_TYPE_1 (0x2U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 7206
<> 148:21d94c44109e 7207 #define USB_EP3R_SETUP_Pos (11U)
<> 148:21d94c44109e 7208 #define USB_EP3R_SETUP_Msk (0x1U << USB_EP3R_SETUP_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 7209 #define USB_EP3R_SETUP USB_EP3R_SETUP_Msk /*!<Setup transaction completed */
<> 148:21d94c44109e 7210
<> 148:21d94c44109e 7211 #define USB_EP3R_STAT_RX_Pos (12U)
<> 148:21d94c44109e 7212 #define USB_EP3R_STAT_RX_Msk (0x3U << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */
<> 148:21d94c44109e 7213 #define USB_EP3R_STAT_RX USB_EP3R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
<> 148:21d94c44109e 7214 #define USB_EP3R_STAT_RX_0 (0x1U << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 7215 #define USB_EP3R_STAT_RX_1 (0x2U << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 7216
<> 148:21d94c44109e 7217 #define USB_EP3R_DTOG_RX_Pos (14U)
<> 148:21d94c44109e 7218 #define USB_EP3R_DTOG_RX_Msk (0x1U << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 7219 #define USB_EP3R_DTOG_RX USB_EP3R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */
<> 148:21d94c44109e 7220 #define USB_EP3R_CTR_RX_Pos (15U)
<> 148:21d94c44109e 7221 #define USB_EP3R_CTR_RX_Msk (0x1U << USB_EP3R_CTR_RX_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 7222 #define USB_EP3R_CTR_RX USB_EP3R_CTR_RX_Msk /*!<Correct Transfer for reception */
<> 148:21d94c44109e 7223
<> 148:21d94c44109e 7224 /******************* Bit definition for USB_EP4R register *******************/
<> 148:21d94c44109e 7225 #define USB_EP4R_EA_Pos (0U)
<> 148:21d94c44109e 7226 #define USB_EP4R_EA_Msk (0xFU << USB_EP4R_EA_Pos) /*!< 0x0000000F */
<> 148:21d94c44109e 7227 #define USB_EP4R_EA USB_EP4R_EA_Msk /*!<Endpoint Address */
<> 148:21d94c44109e 7228
<> 148:21d94c44109e 7229 #define USB_EP4R_STAT_TX_Pos (4U)
<> 148:21d94c44109e 7230 #define USB_EP4R_STAT_TX_Msk (0x3U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */
<> 148:21d94c44109e 7231 #define USB_EP4R_STAT_TX USB_EP4R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
<> 148:21d94c44109e 7232 #define USB_EP4R_STAT_TX_0 (0x1U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 7233 #define USB_EP4R_STAT_TX_1 (0x2U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 7234
<> 148:21d94c44109e 7235 #define USB_EP4R_DTOG_TX_Pos (6U)
<> 148:21d94c44109e 7236 #define USB_EP4R_DTOG_TX_Msk (0x1U << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 7237 #define USB_EP4R_DTOG_TX USB_EP4R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */
<> 148:21d94c44109e 7238 #define USB_EP4R_CTR_TX_Pos (7U)
<> 148:21d94c44109e 7239 #define USB_EP4R_CTR_TX_Msk (0x1U << USB_EP4R_CTR_TX_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 7240 #define USB_EP4R_CTR_TX USB_EP4R_CTR_TX_Msk /*!<Correct Transfer for transmission */
<> 148:21d94c44109e 7241 #define USB_EP4R_EP_KIND_Pos (8U)
<> 148:21d94c44109e 7242 #define USB_EP4R_EP_KIND_Msk (0x1U << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 7243 #define USB_EP4R_EP_KIND USB_EP4R_EP_KIND_Msk /*!<Endpoint Kind */
<> 148:21d94c44109e 7244
<> 148:21d94c44109e 7245 #define USB_EP4R_EP_TYPE_Pos (9U)
<> 148:21d94c44109e 7246 #define USB_EP4R_EP_TYPE_Msk (0x3U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */
<> 148:21d94c44109e 7247 #define USB_EP4R_EP_TYPE USB_EP4R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */
<> 148:21d94c44109e 7248 #define USB_EP4R_EP_TYPE_0 (0x1U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 7249 #define USB_EP4R_EP_TYPE_1 (0x2U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 7250
<> 148:21d94c44109e 7251 #define USB_EP4R_SETUP_Pos (11U)
<> 148:21d94c44109e 7252 #define USB_EP4R_SETUP_Msk (0x1U << USB_EP4R_SETUP_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 7253 #define USB_EP4R_SETUP USB_EP4R_SETUP_Msk /*!<Setup transaction completed */
<> 148:21d94c44109e 7254
<> 148:21d94c44109e 7255 #define USB_EP4R_STAT_RX_Pos (12U)
<> 148:21d94c44109e 7256 #define USB_EP4R_STAT_RX_Msk (0x3U << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */
<> 148:21d94c44109e 7257 #define USB_EP4R_STAT_RX USB_EP4R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
<> 148:21d94c44109e 7258 #define USB_EP4R_STAT_RX_0 (0x1U << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 7259 #define USB_EP4R_STAT_RX_1 (0x2U << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 7260
<> 148:21d94c44109e 7261 #define USB_EP4R_DTOG_RX_Pos (14U)
<> 148:21d94c44109e 7262 #define USB_EP4R_DTOG_RX_Msk (0x1U << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 7263 #define USB_EP4R_DTOG_RX USB_EP4R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */
<> 148:21d94c44109e 7264 #define USB_EP4R_CTR_RX_Pos (15U)
<> 148:21d94c44109e 7265 #define USB_EP4R_CTR_RX_Msk (0x1U << USB_EP4R_CTR_RX_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 7266 #define USB_EP4R_CTR_RX USB_EP4R_CTR_RX_Msk /*!<Correct Transfer for reception */
<> 148:21d94c44109e 7267
<> 148:21d94c44109e 7268 /******************* Bit definition for USB_EP5R register *******************/
<> 148:21d94c44109e 7269 #define USB_EP5R_EA_Pos (0U)
<> 148:21d94c44109e 7270 #define USB_EP5R_EA_Msk (0xFU << USB_EP5R_EA_Pos) /*!< 0x0000000F */
<> 148:21d94c44109e 7271 #define USB_EP5R_EA USB_EP5R_EA_Msk /*!<Endpoint Address */
<> 148:21d94c44109e 7272
<> 148:21d94c44109e 7273 #define USB_EP5R_STAT_TX_Pos (4U)
<> 148:21d94c44109e 7274 #define USB_EP5R_STAT_TX_Msk (0x3U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */
<> 148:21d94c44109e 7275 #define USB_EP5R_STAT_TX USB_EP5R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
<> 148:21d94c44109e 7276 #define USB_EP5R_STAT_TX_0 (0x1U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 7277 #define USB_EP5R_STAT_TX_1 (0x2U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 7278
<> 148:21d94c44109e 7279 #define USB_EP5R_DTOG_TX_Pos (6U)
<> 148:21d94c44109e 7280 #define USB_EP5R_DTOG_TX_Msk (0x1U << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 7281 #define USB_EP5R_DTOG_TX USB_EP5R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */
<> 148:21d94c44109e 7282 #define USB_EP5R_CTR_TX_Pos (7U)
<> 148:21d94c44109e 7283 #define USB_EP5R_CTR_TX_Msk (0x1U << USB_EP5R_CTR_TX_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 7284 #define USB_EP5R_CTR_TX USB_EP5R_CTR_TX_Msk /*!<Correct Transfer for transmission */
<> 148:21d94c44109e 7285 #define USB_EP5R_EP_KIND_Pos (8U)
<> 148:21d94c44109e 7286 #define USB_EP5R_EP_KIND_Msk (0x1U << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 7287 #define USB_EP5R_EP_KIND USB_EP5R_EP_KIND_Msk /*!<Endpoint Kind */
<> 148:21d94c44109e 7288
<> 148:21d94c44109e 7289 #define USB_EP5R_EP_TYPE_Pos (9U)
<> 148:21d94c44109e 7290 #define USB_EP5R_EP_TYPE_Msk (0x3U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */
<> 148:21d94c44109e 7291 #define USB_EP5R_EP_TYPE USB_EP5R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */
<> 148:21d94c44109e 7292 #define USB_EP5R_EP_TYPE_0 (0x1U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 7293 #define USB_EP5R_EP_TYPE_1 (0x2U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 7294
<> 148:21d94c44109e 7295 #define USB_EP5R_SETUP_Pos (11U)
<> 148:21d94c44109e 7296 #define USB_EP5R_SETUP_Msk (0x1U << USB_EP5R_SETUP_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 7297 #define USB_EP5R_SETUP USB_EP5R_SETUP_Msk /*!<Setup transaction completed */
<> 148:21d94c44109e 7298
<> 148:21d94c44109e 7299 #define USB_EP5R_STAT_RX_Pos (12U)
<> 148:21d94c44109e 7300 #define USB_EP5R_STAT_RX_Msk (0x3U << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */
<> 148:21d94c44109e 7301 #define USB_EP5R_STAT_RX USB_EP5R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
<> 148:21d94c44109e 7302 #define USB_EP5R_STAT_RX_0 (0x1U << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 7303 #define USB_EP5R_STAT_RX_1 (0x2U << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 7304
<> 148:21d94c44109e 7305 #define USB_EP5R_DTOG_RX_Pos (14U)
<> 148:21d94c44109e 7306 #define USB_EP5R_DTOG_RX_Msk (0x1U << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 7307 #define USB_EP5R_DTOG_RX USB_EP5R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */
<> 148:21d94c44109e 7308 #define USB_EP5R_CTR_RX_Pos (15U)
<> 148:21d94c44109e 7309 #define USB_EP5R_CTR_RX_Msk (0x1U << USB_EP5R_CTR_RX_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 7310 #define USB_EP5R_CTR_RX USB_EP5R_CTR_RX_Msk /*!<Correct Transfer for reception */
<> 148:21d94c44109e 7311
<> 148:21d94c44109e 7312 /******************* Bit definition for USB_EP6R register *******************/
<> 148:21d94c44109e 7313 #define USB_EP6R_EA_Pos (0U)
<> 148:21d94c44109e 7314 #define USB_EP6R_EA_Msk (0xFU << USB_EP6R_EA_Pos) /*!< 0x0000000F */
<> 148:21d94c44109e 7315 #define USB_EP6R_EA USB_EP6R_EA_Msk /*!<Endpoint Address */
<> 148:21d94c44109e 7316
<> 148:21d94c44109e 7317 #define USB_EP6R_STAT_TX_Pos (4U)
<> 148:21d94c44109e 7318 #define USB_EP6R_STAT_TX_Msk (0x3U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */
<> 148:21d94c44109e 7319 #define USB_EP6R_STAT_TX USB_EP6R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
<> 148:21d94c44109e 7320 #define USB_EP6R_STAT_TX_0 (0x1U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 7321 #define USB_EP6R_STAT_TX_1 (0x2U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 7322
<> 148:21d94c44109e 7323 #define USB_EP6R_DTOG_TX_Pos (6U)
<> 148:21d94c44109e 7324 #define USB_EP6R_DTOG_TX_Msk (0x1U << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 7325 #define USB_EP6R_DTOG_TX USB_EP6R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */
<> 148:21d94c44109e 7326 #define USB_EP6R_CTR_TX_Pos (7U)
<> 148:21d94c44109e 7327 #define USB_EP6R_CTR_TX_Msk (0x1U << USB_EP6R_CTR_TX_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 7328 #define USB_EP6R_CTR_TX USB_EP6R_CTR_TX_Msk /*!<Correct Transfer for transmission */
<> 148:21d94c44109e 7329 #define USB_EP6R_EP_KIND_Pos (8U)
<> 148:21d94c44109e 7330 #define USB_EP6R_EP_KIND_Msk (0x1U << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 7331 #define USB_EP6R_EP_KIND USB_EP6R_EP_KIND_Msk /*!<Endpoint Kind */
<> 148:21d94c44109e 7332
<> 148:21d94c44109e 7333 #define USB_EP6R_EP_TYPE_Pos (9U)
<> 148:21d94c44109e 7334 #define USB_EP6R_EP_TYPE_Msk (0x3U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */
<> 148:21d94c44109e 7335 #define USB_EP6R_EP_TYPE USB_EP6R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */
<> 148:21d94c44109e 7336 #define USB_EP6R_EP_TYPE_0 (0x1U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 7337 #define USB_EP6R_EP_TYPE_1 (0x2U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 7338
<> 148:21d94c44109e 7339 #define USB_EP6R_SETUP_Pos (11U)
<> 148:21d94c44109e 7340 #define USB_EP6R_SETUP_Msk (0x1U << USB_EP6R_SETUP_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 7341 #define USB_EP6R_SETUP USB_EP6R_SETUP_Msk /*!<Setup transaction completed */
<> 148:21d94c44109e 7342
<> 148:21d94c44109e 7343 #define USB_EP6R_STAT_RX_Pos (12U)
<> 148:21d94c44109e 7344 #define USB_EP6R_STAT_RX_Msk (0x3U << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */
<> 148:21d94c44109e 7345 #define USB_EP6R_STAT_RX USB_EP6R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
<> 148:21d94c44109e 7346 #define USB_EP6R_STAT_RX_0 (0x1U << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 7347 #define USB_EP6R_STAT_RX_1 (0x2U << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 7348
<> 148:21d94c44109e 7349 #define USB_EP6R_DTOG_RX_Pos (14U)
<> 148:21d94c44109e 7350 #define USB_EP6R_DTOG_RX_Msk (0x1U << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 7351 #define USB_EP6R_DTOG_RX USB_EP6R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */
<> 148:21d94c44109e 7352 #define USB_EP6R_CTR_RX_Pos (15U)
<> 148:21d94c44109e 7353 #define USB_EP6R_CTR_RX_Msk (0x1U << USB_EP6R_CTR_RX_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 7354 #define USB_EP6R_CTR_RX USB_EP6R_CTR_RX_Msk /*!<Correct Transfer for reception */
<> 148:21d94c44109e 7355
<> 148:21d94c44109e 7356 /******************* Bit definition for USB_EP7R register *******************/
<> 148:21d94c44109e 7357 #define USB_EP7R_EA_Pos (0U)
<> 148:21d94c44109e 7358 #define USB_EP7R_EA_Msk (0xFU << USB_EP7R_EA_Pos) /*!< 0x0000000F */
<> 148:21d94c44109e 7359 #define USB_EP7R_EA USB_EP7R_EA_Msk /*!<Endpoint Address */
<> 148:21d94c44109e 7360
<> 148:21d94c44109e 7361 #define USB_EP7R_STAT_TX_Pos (4U)
<> 148:21d94c44109e 7362 #define USB_EP7R_STAT_TX_Msk (0x3U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */
<> 148:21d94c44109e 7363 #define USB_EP7R_STAT_TX USB_EP7R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
<> 148:21d94c44109e 7364 #define USB_EP7R_STAT_TX_0 (0x1U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 7365 #define USB_EP7R_STAT_TX_1 (0x2U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 7366
<> 148:21d94c44109e 7367 #define USB_EP7R_DTOG_TX_Pos (6U)
<> 148:21d94c44109e 7368 #define USB_EP7R_DTOG_TX_Msk (0x1U << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 7369 #define USB_EP7R_DTOG_TX USB_EP7R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */
<> 148:21d94c44109e 7370 #define USB_EP7R_CTR_TX_Pos (7U)
<> 148:21d94c44109e 7371 #define USB_EP7R_CTR_TX_Msk (0x1U << USB_EP7R_CTR_TX_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 7372 #define USB_EP7R_CTR_TX USB_EP7R_CTR_TX_Msk /*!<Correct Transfer for transmission */
<> 148:21d94c44109e 7373 #define USB_EP7R_EP_KIND_Pos (8U)
<> 148:21d94c44109e 7374 #define USB_EP7R_EP_KIND_Msk (0x1U << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 7375 #define USB_EP7R_EP_KIND USB_EP7R_EP_KIND_Msk /*!<Endpoint Kind */
<> 148:21d94c44109e 7376
<> 148:21d94c44109e 7377 #define USB_EP7R_EP_TYPE_Pos (9U)
<> 148:21d94c44109e 7378 #define USB_EP7R_EP_TYPE_Msk (0x3U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */
<> 148:21d94c44109e 7379 #define USB_EP7R_EP_TYPE USB_EP7R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */
<> 148:21d94c44109e 7380 #define USB_EP7R_EP_TYPE_0 (0x1U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 7381 #define USB_EP7R_EP_TYPE_1 (0x2U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 7382
<> 148:21d94c44109e 7383 #define USB_EP7R_SETUP_Pos (11U)
<> 148:21d94c44109e 7384 #define USB_EP7R_SETUP_Msk (0x1U << USB_EP7R_SETUP_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 7385 #define USB_EP7R_SETUP USB_EP7R_SETUP_Msk /*!<Setup transaction completed */
<> 148:21d94c44109e 7386
<> 148:21d94c44109e 7387 #define USB_EP7R_STAT_RX_Pos (12U)
<> 148:21d94c44109e 7388 #define USB_EP7R_STAT_RX_Msk (0x3U << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */
<> 148:21d94c44109e 7389 #define USB_EP7R_STAT_RX USB_EP7R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
<> 148:21d94c44109e 7390 #define USB_EP7R_STAT_RX_0 (0x1U << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 7391 #define USB_EP7R_STAT_RX_1 (0x2U << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 7392
<> 148:21d94c44109e 7393 #define USB_EP7R_DTOG_RX_Pos (14U)
<> 148:21d94c44109e 7394 #define USB_EP7R_DTOG_RX_Msk (0x1U << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 7395 #define USB_EP7R_DTOG_RX USB_EP7R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */
<> 148:21d94c44109e 7396 #define USB_EP7R_CTR_RX_Pos (15U)
<> 148:21d94c44109e 7397 #define USB_EP7R_CTR_RX_Msk (0x1U << USB_EP7R_CTR_RX_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 7398 #define USB_EP7R_CTR_RX USB_EP7R_CTR_RX_Msk /*!<Correct Transfer for reception */
<> 148:21d94c44109e 7399
<> 148:21d94c44109e 7400 /*!<Common registers */
<> 148:21d94c44109e 7401
<> 148:21d94c44109e 7402 #define USB_CNTR (USB_BASE + 0x00000040U) /*!< Control register */
<> 148:21d94c44109e 7403 #define USB_ISTR (USB_BASE + 0x00000044U) /*!< Interrupt status register */
<> 148:21d94c44109e 7404 #define USB_FNR (USB_BASE + 0x00000048U) /*!< Frame number register */
<> 148:21d94c44109e 7405 #define USB_DADDR (USB_BASE + 0x0000004CU) /*!< Device address register */
<> 148:21d94c44109e 7406 #define USB_BTABLE (USB_BASE + 0x00000050U) /*!< Buffer Table address register */
<> 148:21d94c44109e 7407
<> 148:21d94c44109e 7408
<> 148:21d94c44109e 7409
<> 148:21d94c44109e 7410 /******************* Bit definition for USB_CNTR register *******************/
<> 148:21d94c44109e 7411 #define USB_CNTR_FRES_Pos (0U)
<> 148:21d94c44109e 7412 #define USB_CNTR_FRES_Msk (0x1U << USB_CNTR_FRES_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 7413 #define USB_CNTR_FRES USB_CNTR_FRES_Msk /*!<Force USB Reset */
<> 148:21d94c44109e 7414 #define USB_CNTR_PDWN_Pos (1U)
<> 148:21d94c44109e 7415 #define USB_CNTR_PDWN_Msk (0x1U << USB_CNTR_PDWN_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 7416 #define USB_CNTR_PDWN USB_CNTR_PDWN_Msk /*!<Power down */
<> 148:21d94c44109e 7417 #define USB_CNTR_LPMODE_Pos (2U)
<> 148:21d94c44109e 7418 #define USB_CNTR_LPMODE_Msk (0x1U << USB_CNTR_LPMODE_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 7419 #define USB_CNTR_LPMODE USB_CNTR_LPMODE_Msk /*!<Low-power mode */
<> 148:21d94c44109e 7420 #define USB_CNTR_FSUSP_Pos (3U)
<> 148:21d94c44109e 7421 #define USB_CNTR_FSUSP_Msk (0x1U << USB_CNTR_FSUSP_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 7422 #define USB_CNTR_FSUSP USB_CNTR_FSUSP_Msk /*!<Force suspend */
<> 148:21d94c44109e 7423 #define USB_CNTR_RESUME_Pos (4U)
<> 148:21d94c44109e 7424 #define USB_CNTR_RESUME_Msk (0x1U << USB_CNTR_RESUME_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 7425 #define USB_CNTR_RESUME USB_CNTR_RESUME_Msk /*!<Resume request */
<> 148:21d94c44109e 7426 #define USB_CNTR_ESOFM_Pos (8U)
<> 148:21d94c44109e 7427 #define USB_CNTR_ESOFM_Msk (0x1U << USB_CNTR_ESOFM_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 7428 #define USB_CNTR_ESOFM USB_CNTR_ESOFM_Msk /*!<Expected Start Of Frame Interrupt Mask */
<> 148:21d94c44109e 7429 #define USB_CNTR_SOFM_Pos (9U)
<> 148:21d94c44109e 7430 #define USB_CNTR_SOFM_Msk (0x1U << USB_CNTR_SOFM_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 7431 #define USB_CNTR_SOFM USB_CNTR_SOFM_Msk /*!<Start Of Frame Interrupt Mask */
<> 148:21d94c44109e 7432 #define USB_CNTR_RESETM_Pos (10U)
<> 148:21d94c44109e 7433 #define USB_CNTR_RESETM_Msk (0x1U << USB_CNTR_RESETM_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 7434 #define USB_CNTR_RESETM USB_CNTR_RESETM_Msk /*!<RESET Interrupt Mask */
<> 148:21d94c44109e 7435 #define USB_CNTR_SUSPM_Pos (11U)
<> 148:21d94c44109e 7436 #define USB_CNTR_SUSPM_Msk (0x1U << USB_CNTR_SUSPM_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 7437 #define USB_CNTR_SUSPM USB_CNTR_SUSPM_Msk /*!<Suspend mode Interrupt Mask */
<> 148:21d94c44109e 7438 #define USB_CNTR_WKUPM_Pos (12U)
<> 148:21d94c44109e 7439 #define USB_CNTR_WKUPM_Msk (0x1U << USB_CNTR_WKUPM_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 7440 #define USB_CNTR_WKUPM USB_CNTR_WKUPM_Msk /*!<Wakeup Interrupt Mask */
<> 148:21d94c44109e 7441 #define USB_CNTR_ERRM_Pos (13U)
<> 148:21d94c44109e 7442 #define USB_CNTR_ERRM_Msk (0x1U << USB_CNTR_ERRM_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 7443 #define USB_CNTR_ERRM USB_CNTR_ERRM_Msk /*!<Error Interrupt Mask */
<> 148:21d94c44109e 7444 #define USB_CNTR_PMAOVRM_Pos (14U)
<> 148:21d94c44109e 7445 #define USB_CNTR_PMAOVRM_Msk (0x1U << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 7446 #define USB_CNTR_PMAOVRM USB_CNTR_PMAOVRM_Msk /*!<Packet Memory Area Over / Underrun Interrupt Mask */
<> 148:21d94c44109e 7447 #define USB_CNTR_CTRM_Pos (15U)
<> 148:21d94c44109e 7448 #define USB_CNTR_CTRM_Msk (0x1U << USB_CNTR_CTRM_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 7449 #define USB_CNTR_CTRM USB_CNTR_CTRM_Msk /*!<Correct Transfer Interrupt Mask */
<> 148:21d94c44109e 7450
<> 148:21d94c44109e 7451 /******************* Bit definition for USB_ISTR register *******************/
<> 148:21d94c44109e 7452 #define USB_ISTR_EP_ID_Pos (0U)
<> 148:21d94c44109e 7453 #define USB_ISTR_EP_ID_Msk (0xFU << USB_ISTR_EP_ID_Pos) /*!< 0x0000000F */
<> 148:21d94c44109e 7454 #define USB_ISTR_EP_ID USB_ISTR_EP_ID_Msk /*!<Endpoint Identifier */
<> 148:21d94c44109e 7455 #define USB_ISTR_DIR_Pos (4U)
<> 148:21d94c44109e 7456 #define USB_ISTR_DIR_Msk (0x1U << USB_ISTR_DIR_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 7457 #define USB_ISTR_DIR USB_ISTR_DIR_Msk /*!<Direction of transaction */
<> 148:21d94c44109e 7458 #define USB_ISTR_ESOF_Pos (8U)
<> 148:21d94c44109e 7459 #define USB_ISTR_ESOF_Msk (0x1U << USB_ISTR_ESOF_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 7460 #define USB_ISTR_ESOF USB_ISTR_ESOF_Msk /*!<Expected Start Of Frame */
<> 148:21d94c44109e 7461 #define USB_ISTR_SOF_Pos (9U)
<> 148:21d94c44109e 7462 #define USB_ISTR_SOF_Msk (0x1U << USB_ISTR_SOF_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 7463 #define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!<Start Of Frame */
<> 148:21d94c44109e 7464 #define USB_ISTR_RESET_Pos (10U)
<> 148:21d94c44109e 7465 #define USB_ISTR_RESET_Msk (0x1U << USB_ISTR_RESET_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 7466 #define USB_ISTR_RESET USB_ISTR_RESET_Msk /*!<USB RESET request */
<> 148:21d94c44109e 7467 #define USB_ISTR_SUSP_Pos (11U)
<> 148:21d94c44109e 7468 #define USB_ISTR_SUSP_Msk (0x1U << USB_ISTR_SUSP_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 7469 #define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!<Suspend mode request */
<> 148:21d94c44109e 7470 #define USB_ISTR_WKUP_Pos (12U)
<> 148:21d94c44109e 7471 #define USB_ISTR_WKUP_Msk (0x1U << USB_ISTR_WKUP_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 7472 #define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!<Wake up */
<> 148:21d94c44109e 7473 #define USB_ISTR_ERR_Pos (13U)
<> 148:21d94c44109e 7474 #define USB_ISTR_ERR_Msk (0x1U << USB_ISTR_ERR_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 7475 #define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!<Error */
<> 148:21d94c44109e 7476 #define USB_ISTR_PMAOVR_Pos (14U)
<> 148:21d94c44109e 7477 #define USB_ISTR_PMAOVR_Msk (0x1U << USB_ISTR_PMAOVR_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 7478 #define USB_ISTR_PMAOVR USB_ISTR_PMAOVR_Msk /*!<Packet Memory Area Over / Underrun */
<> 148:21d94c44109e 7479 #define USB_ISTR_CTR_Pos (15U)
<> 148:21d94c44109e 7480 #define USB_ISTR_CTR_Msk (0x1U << USB_ISTR_CTR_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 7481 #define USB_ISTR_CTR USB_ISTR_CTR_Msk /*!<Correct Transfer */
<> 148:21d94c44109e 7482
<> 148:21d94c44109e 7483 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
<> 148:21d94c44109e 7484 #define USB_CLR_PMAOVRM (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
<> 148:21d94c44109e 7485 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
<> 148:21d94c44109e 7486 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
<> 148:21d94c44109e 7487 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
<> 148:21d94c44109e 7488 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
<> 148:21d94c44109e 7489 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
<> 148:21d94c44109e 7490 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
<> 148:21d94c44109e 7491
<> 148:21d94c44109e 7492
<> 148:21d94c44109e 7493 /******************* Bit definition for USB_FNR register ********************/
<> 148:21d94c44109e 7494 #define USB_FNR_FN_Pos (0U)
<> 148:21d94c44109e 7495 #define USB_FNR_FN_Msk (0x7FFU << USB_FNR_FN_Pos) /*!< 0x000007FF */
<> 148:21d94c44109e 7496 #define USB_FNR_FN USB_FNR_FN_Msk /*!<Frame Number */
<> 148:21d94c44109e 7497 #define USB_FNR_LSOF_Pos (11U)
<> 148:21d94c44109e 7498 #define USB_FNR_LSOF_Msk (0x3U << USB_FNR_LSOF_Pos) /*!< 0x00001800 */
<> 148:21d94c44109e 7499 #define USB_FNR_LSOF USB_FNR_LSOF_Msk /*!<Lost SOF */
<> 148:21d94c44109e 7500 #define USB_FNR_LCK_Pos (13U)
<> 148:21d94c44109e 7501 #define USB_FNR_LCK_Msk (0x1U << USB_FNR_LCK_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 7502 #define USB_FNR_LCK USB_FNR_LCK_Msk /*!<Locked */
<> 148:21d94c44109e 7503 #define USB_FNR_RXDM_Pos (14U)
<> 148:21d94c44109e 7504 #define USB_FNR_RXDM_Msk (0x1U << USB_FNR_RXDM_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 7505 #define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!<Receive Data - Line Status */
<> 148:21d94c44109e 7506 #define USB_FNR_RXDP_Pos (15U)
<> 148:21d94c44109e 7507 #define USB_FNR_RXDP_Msk (0x1U << USB_FNR_RXDP_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 7508 #define USB_FNR_RXDP USB_FNR_RXDP_Msk /*!<Receive Data + Line Status */
<> 148:21d94c44109e 7509
<> 148:21d94c44109e 7510 /****************** Bit definition for USB_DADDR register *******************/
<> 148:21d94c44109e 7511 #define USB_DADDR_ADD_Pos (0U)
<> 148:21d94c44109e 7512 #define USB_DADDR_ADD_Msk (0x7FU << USB_DADDR_ADD_Pos) /*!< 0x0000007F */
<> 148:21d94c44109e 7513 #define USB_DADDR_ADD USB_DADDR_ADD_Msk /*!<ADD[6:0] bits (Device Address) */
<> 148:21d94c44109e 7514 #define USB_DADDR_ADD0_Pos (0U)
<> 148:21d94c44109e 7515 #define USB_DADDR_ADD0_Msk (0x1U << USB_DADDR_ADD0_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 7516 #define USB_DADDR_ADD0 USB_DADDR_ADD0_Msk /*!<Bit 0 */
<> 148:21d94c44109e 7517 #define USB_DADDR_ADD1_Pos (1U)
<> 148:21d94c44109e 7518 #define USB_DADDR_ADD1_Msk (0x1U << USB_DADDR_ADD1_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 7519 #define USB_DADDR_ADD1 USB_DADDR_ADD1_Msk /*!<Bit 1 */
<> 148:21d94c44109e 7520 #define USB_DADDR_ADD2_Pos (2U)
<> 148:21d94c44109e 7521 #define USB_DADDR_ADD2_Msk (0x1U << USB_DADDR_ADD2_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 7522 #define USB_DADDR_ADD2 USB_DADDR_ADD2_Msk /*!<Bit 2 */
<> 148:21d94c44109e 7523 #define USB_DADDR_ADD3_Pos (3U)
<> 148:21d94c44109e 7524 #define USB_DADDR_ADD3_Msk (0x1U << USB_DADDR_ADD3_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 7525 #define USB_DADDR_ADD3 USB_DADDR_ADD3_Msk /*!<Bit 3 */
<> 148:21d94c44109e 7526 #define USB_DADDR_ADD4_Pos (4U)
<> 148:21d94c44109e 7527 #define USB_DADDR_ADD4_Msk (0x1U << USB_DADDR_ADD4_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 7528 #define USB_DADDR_ADD4 USB_DADDR_ADD4_Msk /*!<Bit 4 */
<> 148:21d94c44109e 7529 #define USB_DADDR_ADD5_Pos (5U)
<> 148:21d94c44109e 7530 #define USB_DADDR_ADD5_Msk (0x1U << USB_DADDR_ADD5_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 7531 #define USB_DADDR_ADD5 USB_DADDR_ADD5_Msk /*!<Bit 5 */
<> 148:21d94c44109e 7532 #define USB_DADDR_ADD6_Pos (6U)
<> 148:21d94c44109e 7533 #define USB_DADDR_ADD6_Msk (0x1U << USB_DADDR_ADD6_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 7534 #define USB_DADDR_ADD6 USB_DADDR_ADD6_Msk /*!<Bit 6 */
<> 148:21d94c44109e 7535
<> 148:21d94c44109e 7536 #define USB_DADDR_EF_Pos (7U)
<> 148:21d94c44109e 7537 #define USB_DADDR_EF_Msk (0x1U << USB_DADDR_EF_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 7538 #define USB_DADDR_EF USB_DADDR_EF_Msk /*!<Enable Function */
<> 148:21d94c44109e 7539
<> 148:21d94c44109e 7540 /****************** Bit definition for USB_BTABLE register ******************/
<> 148:21d94c44109e 7541 #define USB_BTABLE_BTABLE_Pos (3U)
<> 148:21d94c44109e 7542 #define USB_BTABLE_BTABLE_Msk (0x1FFFU << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
<> 148:21d94c44109e 7543 #define USB_BTABLE_BTABLE USB_BTABLE_BTABLE_Msk /*!<Buffer Table */
<> 148:21d94c44109e 7544
<> 148:21d94c44109e 7545 /*!< Buffer descriptor table */
<> 148:21d94c44109e 7546 /***************** Bit definition for USB_ADDR0_TX register *****************/
<> 148:21d94c44109e 7547 #define USB_ADDR0_TX_ADDR0_TX_Pos (1U)
<> 148:21d94c44109e 7548 #define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFU << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
<> 148:21d94c44109e 7549 #define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */
<> 148:21d94c44109e 7550
<> 148:21d94c44109e 7551 /***************** Bit definition for USB_ADDR1_TX register *****************/
<> 148:21d94c44109e 7552 #define USB_ADDR1_TX_ADDR1_TX_Pos (1U)
<> 148:21d94c44109e 7553 #define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFU << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
<> 148:21d94c44109e 7554 #define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */
<> 148:21d94c44109e 7555
<> 148:21d94c44109e 7556 /***************** Bit definition for USB_ADDR2_TX register *****************/
<> 148:21d94c44109e 7557 #define USB_ADDR2_TX_ADDR2_TX_Pos (1U)
<> 148:21d94c44109e 7558 #define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFU << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
<> 148:21d94c44109e 7559 #define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */
<> 148:21d94c44109e 7560
<> 148:21d94c44109e 7561 /***************** Bit definition for USB_ADDR3_TX register *****************/
<> 148:21d94c44109e 7562 #define USB_ADDR3_TX_ADDR3_TX_Pos (1U)
<> 148:21d94c44109e 7563 #define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFU << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
<> 148:21d94c44109e 7564 #define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */
<> 148:21d94c44109e 7565
<> 148:21d94c44109e 7566 /***************** Bit definition for USB_ADDR4_TX register *****************/
<> 148:21d94c44109e 7567 #define USB_ADDR4_TX_ADDR4_TX_Pos (1U)
<> 148:21d94c44109e 7568 #define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFU << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
<> 148:21d94c44109e 7569 #define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */
<> 148:21d94c44109e 7570
<> 148:21d94c44109e 7571 /***************** Bit definition for USB_ADDR5_TX register *****************/
<> 148:21d94c44109e 7572 #define USB_ADDR5_TX_ADDR5_TX_Pos (1U)
<> 148:21d94c44109e 7573 #define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFU << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
<> 148:21d94c44109e 7574 #define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */
<> 148:21d94c44109e 7575
<> 148:21d94c44109e 7576 /***************** Bit definition for USB_ADDR6_TX register *****************/
<> 148:21d94c44109e 7577 #define USB_ADDR6_TX_ADDR6_TX_Pos (1U)
<> 148:21d94c44109e 7578 #define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFU << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
<> 148:21d94c44109e 7579 #define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */
<> 148:21d94c44109e 7580
<> 148:21d94c44109e 7581 /***************** Bit definition for USB_ADDR7_TX register *****************/
<> 148:21d94c44109e 7582 #define USB_ADDR7_TX_ADDR7_TX_Pos (1U)
<> 148:21d94c44109e 7583 #define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFU << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
<> 148:21d94c44109e 7584 #define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */
<> 148:21d94c44109e 7585
<> 148:21d94c44109e 7586 /*----------------------------------------------------------------------------*/
<> 148:21d94c44109e 7587
<> 148:21d94c44109e 7588 /***************** Bit definition for USB_COUNT0_TX register ****************/
<> 148:21d94c44109e 7589 #define USB_COUNT0_TX_COUNT0_TX_Pos (0U)
<> 148:21d94c44109e 7590 #define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFU << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
<> 148:21d94c44109e 7591 #define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */
<> 148:21d94c44109e 7592
<> 148:21d94c44109e 7593 /***************** Bit definition for USB_COUNT1_TX register ****************/
<> 148:21d94c44109e 7594 #define USB_COUNT1_TX_COUNT1_TX_Pos (0U)
<> 148:21d94c44109e 7595 #define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFU << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
<> 148:21d94c44109e 7596 #define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */
<> 148:21d94c44109e 7597
<> 148:21d94c44109e 7598 /***************** Bit definition for USB_COUNT2_TX register ****************/
<> 148:21d94c44109e 7599 #define USB_COUNT2_TX_COUNT2_TX_Pos (0U)
<> 148:21d94c44109e 7600 #define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFU << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
<> 148:21d94c44109e 7601 #define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */
<> 148:21d94c44109e 7602
<> 148:21d94c44109e 7603 /***************** Bit definition for USB_COUNT3_TX register ****************/
<> 148:21d94c44109e 7604 #define USB_COUNT3_TX_COUNT3_TX_Pos (0U)
<> 148:21d94c44109e 7605 #define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFU << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
<> 148:21d94c44109e 7606 #define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */
<> 148:21d94c44109e 7607
<> 148:21d94c44109e 7608 /***************** Bit definition for USB_COUNT4_TX register ****************/
<> 148:21d94c44109e 7609 #define USB_COUNT4_TX_COUNT4_TX_Pos (0U)
<> 148:21d94c44109e 7610 #define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFU << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
<> 148:21d94c44109e 7611 #define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */
<> 148:21d94c44109e 7612
<> 148:21d94c44109e 7613 /***************** Bit definition for USB_COUNT5_TX register ****************/
<> 148:21d94c44109e 7614 #define USB_COUNT5_TX_COUNT5_TX_Pos (0U)
<> 148:21d94c44109e 7615 #define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFU << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
<> 148:21d94c44109e 7616 #define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */
<> 148:21d94c44109e 7617
<> 148:21d94c44109e 7618 /***************** Bit definition for USB_COUNT6_TX register ****************/
<> 148:21d94c44109e 7619 #define USB_COUNT6_TX_COUNT6_TX_Pos (0U)
<> 148:21d94c44109e 7620 #define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFU << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
<> 148:21d94c44109e 7621 #define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */
<> 148:21d94c44109e 7622
<> 148:21d94c44109e 7623 /***************** Bit definition for USB_COUNT7_TX register ****************/
<> 148:21d94c44109e 7624 #define USB_COUNT7_TX_COUNT7_TX_Pos (0U)
<> 148:21d94c44109e 7625 #define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFU << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
<> 148:21d94c44109e 7626 #define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */
<> 148:21d94c44109e 7627
<> 148:21d94c44109e 7628 /*----------------------------------------------------------------------------*/
<> 148:21d94c44109e 7629
<> 148:21d94c44109e 7630 /**************** Bit definition for USB_COUNT0_TX_0 register ***************/
<> 148:21d94c44109e 7631 #define USB_COUNT0_TX_0_COUNT0_TX_0 (0x000003FFU) /*!< Transmission Byte Count 0 (low) */
<> 148:21d94c44109e 7632
<> 148:21d94c44109e 7633 /**************** Bit definition for USB_COUNT0_TX_1 register ***************/
<> 148:21d94c44109e 7634 #define USB_COUNT0_TX_1_COUNT0_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 0 (high) */
<> 148:21d94c44109e 7635
<> 148:21d94c44109e 7636 /**************** Bit definition for USB_COUNT1_TX_0 register ***************/
<> 148:21d94c44109e 7637 #define USB_COUNT1_TX_0_COUNT1_TX_0 (0x000003FFU) /*!< Transmission Byte Count 1 (low) */
<> 148:21d94c44109e 7638
<> 148:21d94c44109e 7639 /**************** Bit definition for USB_COUNT1_TX_1 register ***************/
<> 148:21d94c44109e 7640 #define USB_COUNT1_TX_1_COUNT1_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 1 (high) */
<> 148:21d94c44109e 7641
<> 148:21d94c44109e 7642 /**************** Bit definition for USB_COUNT2_TX_0 register ***************/
<> 148:21d94c44109e 7643 #define USB_COUNT2_TX_0_COUNT2_TX_0 (0x000003FFU) /*!< Transmission Byte Count 2 (low) */
<> 148:21d94c44109e 7644
<> 148:21d94c44109e 7645 /**************** Bit definition for USB_COUNT2_TX_1 register ***************/
<> 148:21d94c44109e 7646 #define USB_COUNT2_TX_1_COUNT2_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 2 (high) */
<> 148:21d94c44109e 7647
<> 148:21d94c44109e 7648 /**************** Bit definition for USB_COUNT3_TX_0 register ***************/
<> 148:21d94c44109e 7649 #define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x00000000U03FF) /*!< Transmission Byte Count 3 (low) */
<> 148:21d94c44109e 7650
<> 148:21d94c44109e 7651 /**************** Bit definition for USB_COUNT3_TX_1 register ***************/
<> 148:21d94c44109e 7652 #define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x000003FFU0000) /*!< Transmission Byte Count 3 (high) */
<> 148:21d94c44109e 7653
<> 148:21d94c44109e 7654 /**************** Bit definition for USB_COUNT4_TX_0 register ***************/
<> 148:21d94c44109e 7655 #define USB_COUNT4_TX_0_COUNT4_TX_0 (0x000003FFU) /*!< Transmission Byte Count 4 (low) */
<> 148:21d94c44109e 7656
<> 148:21d94c44109e 7657 /**************** Bit definition for USB_COUNT4_TX_1 register ***************/
<> 148:21d94c44109e 7658 #define USB_COUNT4_TX_1_COUNT4_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 4 (high) */
<> 148:21d94c44109e 7659
<> 148:21d94c44109e 7660 /**************** Bit definition for USB_COUNT5_TX_0 register ***************/
<> 148:21d94c44109e 7661 #define USB_COUNT5_TX_0_COUNT5_TX_0 (0x000003FFU) /*!< Transmission Byte Count 5 (low) */
<> 148:21d94c44109e 7662
<> 148:21d94c44109e 7663 /**************** Bit definition for USB_COUNT5_TX_1 register ***************/
<> 148:21d94c44109e 7664 #define USB_COUNT5_TX_1_COUNT5_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 5 (high) */
<> 148:21d94c44109e 7665
<> 148:21d94c44109e 7666 /**************** Bit definition for USB_COUNT6_TX_0 register ***************/
<> 148:21d94c44109e 7667 #define USB_COUNT6_TX_0_COUNT6_TX_0 (0x000003FFU) /*!< Transmission Byte Count 6 (low) */
<> 148:21d94c44109e 7668
<> 148:21d94c44109e 7669 /**************** Bit definition for USB_COUNT6_TX_1 register ***************/
<> 148:21d94c44109e 7670 #define USB_COUNT6_TX_1_COUNT6_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 6 (high) */
<> 148:21d94c44109e 7671
<> 148:21d94c44109e 7672 /**************** Bit definition for USB_COUNT7_TX_0 register ***************/
<> 148:21d94c44109e 7673 #define USB_COUNT7_TX_0_COUNT7_TX_0 (0x000003FFU) /*!< Transmission Byte Count 7 (low) */
<> 148:21d94c44109e 7674
<> 148:21d94c44109e 7675 /**************** Bit definition for USB_COUNT7_TX_1 register ***************/
<> 148:21d94c44109e 7676 #define USB_COUNT7_TX_1_COUNT7_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 7 (high) */
<> 148:21d94c44109e 7677
<> 148:21d94c44109e 7678 /*----------------------------------------------------------------------------*/
<> 148:21d94c44109e 7679
<> 148:21d94c44109e 7680 /***************** Bit definition for USB_ADDR0_RX register *****************/
<> 148:21d94c44109e 7681 #define USB_ADDR0_RX_ADDR0_RX_Pos (1U)
<> 148:21d94c44109e 7682 #define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFU << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
<> 148:21d94c44109e 7683 #define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */
<> 148:21d94c44109e 7684
<> 148:21d94c44109e 7685 /***************** Bit definition for USB_ADDR1_RX register *****************/
<> 148:21d94c44109e 7686 #define USB_ADDR1_RX_ADDR1_RX_Pos (1U)
<> 148:21d94c44109e 7687 #define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFU << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
<> 148:21d94c44109e 7688 #define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */
<> 148:21d94c44109e 7689
<> 148:21d94c44109e 7690 /***************** Bit definition for USB_ADDR2_RX register *****************/
<> 148:21d94c44109e 7691 #define USB_ADDR2_RX_ADDR2_RX_Pos (1U)
<> 148:21d94c44109e 7692 #define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFU << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
<> 148:21d94c44109e 7693 #define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */
<> 148:21d94c44109e 7694
<> 148:21d94c44109e 7695 /***************** Bit definition for USB_ADDR3_RX register *****************/
<> 148:21d94c44109e 7696 #define USB_ADDR3_RX_ADDR3_RX_Pos (1U)
<> 148:21d94c44109e 7697 #define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFU << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
<> 148:21d94c44109e 7698 #define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */
<> 148:21d94c44109e 7699
<> 148:21d94c44109e 7700 /***************** Bit definition for USB_ADDR4_RX register *****************/
<> 148:21d94c44109e 7701 #define USB_ADDR4_RX_ADDR4_RX_Pos (1U)
<> 148:21d94c44109e 7702 #define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFU << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
<> 148:21d94c44109e 7703 #define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */
<> 148:21d94c44109e 7704
<> 148:21d94c44109e 7705 /***************** Bit definition for USB_ADDR5_RX register *****************/
<> 148:21d94c44109e 7706 #define USB_ADDR5_RX_ADDR5_RX_Pos (1U)
<> 148:21d94c44109e 7707 #define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFU << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
<> 148:21d94c44109e 7708 #define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */
<> 148:21d94c44109e 7709
<> 148:21d94c44109e 7710 /***************** Bit definition for USB_ADDR6_RX register *****************/
<> 148:21d94c44109e 7711 #define USB_ADDR6_RX_ADDR6_RX_Pos (1U)
<> 148:21d94c44109e 7712 #define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFU << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
<> 148:21d94c44109e 7713 #define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */
<> 148:21d94c44109e 7714
<> 148:21d94c44109e 7715 /***************** Bit definition for USB_ADDR7_RX register *****************/
<> 148:21d94c44109e 7716 #define USB_ADDR7_RX_ADDR7_RX_Pos (1U)
<> 148:21d94c44109e 7717 #define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFU << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
<> 148:21d94c44109e 7718 #define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */
<> 148:21d94c44109e 7719
<> 148:21d94c44109e 7720 /*----------------------------------------------------------------------------*/
<> 148:21d94c44109e 7721
<> 148:21d94c44109e 7722 /***************** Bit definition for USB_COUNT0_RX register ****************/
<> 148:21d94c44109e 7723 #define USB_COUNT0_RX_COUNT0_RX_Pos (0U)
<> 148:21d94c44109e 7724 #define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFU << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
<> 148:21d94c44109e 7725 #define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */
<> 148:21d94c44109e 7726
<> 148:21d94c44109e 7727 #define USB_COUNT0_RX_NUM_BLOCK_Pos (10U)
<> 148:21d94c44109e 7728 #define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
<> 148:21d94c44109e 7729 #define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
<> 148:21d94c44109e 7730 #define USB_COUNT0_RX_NUM_BLOCK_0 (0x01U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 7731 #define USB_COUNT0_RX_NUM_BLOCK_1 (0x02U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 7732 #define USB_COUNT0_RX_NUM_BLOCK_2 (0x04U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 7733 #define USB_COUNT0_RX_NUM_BLOCK_3 (0x08U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 7734 #define USB_COUNT0_RX_NUM_BLOCK_4 (0x10U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 7735
<> 148:21d94c44109e 7736 #define USB_COUNT0_RX_BLSIZE_Pos (15U)
<> 148:21d94c44109e 7737 #define USB_COUNT0_RX_BLSIZE_Msk (0x1U << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 7738 #define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */
<> 148:21d94c44109e 7739
<> 148:21d94c44109e 7740 /***************** Bit definition for USB_COUNT1_RX register ****************/
<> 148:21d94c44109e 7741 #define USB_COUNT1_RX_COUNT1_RX_Pos (0U)
<> 148:21d94c44109e 7742 #define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFU << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
<> 148:21d94c44109e 7743 #define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */
<> 148:21d94c44109e 7744
<> 148:21d94c44109e 7745 #define USB_COUNT1_RX_NUM_BLOCK_Pos (10U)
<> 148:21d94c44109e 7746 #define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
<> 148:21d94c44109e 7747 #define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
<> 148:21d94c44109e 7748 #define USB_COUNT1_RX_NUM_BLOCK_0 (0x01U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 7749 #define USB_COUNT1_RX_NUM_BLOCK_1 (0x02U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 7750 #define USB_COUNT1_RX_NUM_BLOCK_2 (0x04U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 7751 #define USB_COUNT1_RX_NUM_BLOCK_3 (0x08U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 7752 #define USB_COUNT1_RX_NUM_BLOCK_4 (0x10U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 7753
<> 148:21d94c44109e 7754 #define USB_COUNT1_RX_BLSIZE_Pos (15U)
<> 148:21d94c44109e 7755 #define USB_COUNT1_RX_BLSIZE_Msk (0x1U << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 7756 #define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */
<> 148:21d94c44109e 7757
<> 148:21d94c44109e 7758 /***************** Bit definition for USB_COUNT2_RX register ****************/
<> 148:21d94c44109e 7759 #define USB_COUNT2_RX_COUNT2_RX_Pos (0U)
<> 148:21d94c44109e 7760 #define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFU << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
<> 148:21d94c44109e 7761 #define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */
<> 148:21d94c44109e 7762
<> 148:21d94c44109e 7763 #define USB_COUNT2_RX_NUM_BLOCK_Pos (10U)
<> 148:21d94c44109e 7764 #define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
<> 148:21d94c44109e 7765 #define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
<> 148:21d94c44109e 7766 #define USB_COUNT2_RX_NUM_BLOCK_0 (0x01U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 7767 #define USB_COUNT2_RX_NUM_BLOCK_1 (0x02U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 7768 #define USB_COUNT2_RX_NUM_BLOCK_2 (0x04U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 7769 #define USB_COUNT2_RX_NUM_BLOCK_3 (0x08U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 7770 #define USB_COUNT2_RX_NUM_BLOCK_4 (0x10U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 7771
<> 148:21d94c44109e 7772 #define USB_COUNT2_RX_BLSIZE_Pos (15U)
<> 148:21d94c44109e 7773 #define USB_COUNT2_RX_BLSIZE_Msk (0x1U << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 7774 #define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */
<> 148:21d94c44109e 7775
<> 148:21d94c44109e 7776 /***************** Bit definition for USB_COUNT3_RX register ****************/
<> 148:21d94c44109e 7777 #define USB_COUNT3_RX_COUNT3_RX_Pos (0U)
<> 148:21d94c44109e 7778 #define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFU << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
<> 148:21d94c44109e 7779 #define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */
<> 148:21d94c44109e 7780
<> 148:21d94c44109e 7781 #define USB_COUNT3_RX_NUM_BLOCK_Pos (10U)
<> 148:21d94c44109e 7782 #define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
<> 148:21d94c44109e 7783 #define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
<> 148:21d94c44109e 7784 #define USB_COUNT3_RX_NUM_BLOCK_0 (0x01U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 7785 #define USB_COUNT3_RX_NUM_BLOCK_1 (0x02U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 7786 #define USB_COUNT3_RX_NUM_BLOCK_2 (0x04U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 7787 #define USB_COUNT3_RX_NUM_BLOCK_3 (0x08U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 7788 #define USB_COUNT3_RX_NUM_BLOCK_4 (0x10U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 7789
<> 148:21d94c44109e 7790 #define USB_COUNT3_RX_BLSIZE_Pos (15U)
<> 148:21d94c44109e 7791 #define USB_COUNT3_RX_BLSIZE_Msk (0x1U << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 7792 #define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */
<> 148:21d94c44109e 7793
<> 148:21d94c44109e 7794 /***************** Bit definition for USB_COUNT4_RX register ****************/
<> 148:21d94c44109e 7795 #define USB_COUNT4_RX_COUNT4_RX_Pos (0U)
<> 148:21d94c44109e 7796 #define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFU << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
<> 148:21d94c44109e 7797 #define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */
<> 148:21d94c44109e 7798
<> 148:21d94c44109e 7799 #define USB_COUNT4_RX_NUM_BLOCK_Pos (10U)
<> 148:21d94c44109e 7800 #define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
<> 148:21d94c44109e 7801 #define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
<> 148:21d94c44109e 7802 #define USB_COUNT4_RX_NUM_BLOCK_0 (0x01U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 7803 #define USB_COUNT4_RX_NUM_BLOCK_1 (0x02U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 7804 #define USB_COUNT4_RX_NUM_BLOCK_2 (0x04U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 7805 #define USB_COUNT4_RX_NUM_BLOCK_3 (0x08U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 7806 #define USB_COUNT4_RX_NUM_BLOCK_4 (0x10U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 7807
<> 148:21d94c44109e 7808 #define USB_COUNT4_RX_BLSIZE_Pos (15U)
<> 148:21d94c44109e 7809 #define USB_COUNT4_RX_BLSIZE_Msk (0x1U << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 7810 #define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */
<> 148:21d94c44109e 7811
<> 148:21d94c44109e 7812 /***************** Bit definition for USB_COUNT5_RX register ****************/
<> 148:21d94c44109e 7813 #define USB_COUNT5_RX_COUNT5_RX_Pos (0U)
<> 148:21d94c44109e 7814 #define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFU << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
<> 148:21d94c44109e 7815 #define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */
<> 148:21d94c44109e 7816
<> 148:21d94c44109e 7817 #define USB_COUNT5_RX_NUM_BLOCK_Pos (10U)
<> 148:21d94c44109e 7818 #define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
<> 148:21d94c44109e 7819 #define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
<> 148:21d94c44109e 7820 #define USB_COUNT5_RX_NUM_BLOCK_0 (0x01U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 7821 #define USB_COUNT5_RX_NUM_BLOCK_1 (0x02U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 7822 #define USB_COUNT5_RX_NUM_BLOCK_2 (0x04U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 7823 #define USB_COUNT5_RX_NUM_BLOCK_3 (0x08U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 7824 #define USB_COUNT5_RX_NUM_BLOCK_4 (0x10U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 7825
<> 148:21d94c44109e 7826 #define USB_COUNT5_RX_BLSIZE_Pos (15U)
<> 148:21d94c44109e 7827 #define USB_COUNT5_RX_BLSIZE_Msk (0x1U << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 7828 #define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */
<> 148:21d94c44109e 7829
<> 148:21d94c44109e 7830 /***************** Bit definition for USB_COUNT6_RX register ****************/
<> 148:21d94c44109e 7831 #define USB_COUNT6_RX_COUNT6_RX_Pos (0U)
<> 148:21d94c44109e 7832 #define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFU << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
<> 148:21d94c44109e 7833 #define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */
<> 148:21d94c44109e 7834
<> 148:21d94c44109e 7835 #define USB_COUNT6_RX_NUM_BLOCK_Pos (10U)
<> 148:21d94c44109e 7836 #define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
<> 148:21d94c44109e 7837 #define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
<> 148:21d94c44109e 7838 #define USB_COUNT6_RX_NUM_BLOCK_0 (0x01U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 7839 #define USB_COUNT6_RX_NUM_BLOCK_1 (0x02U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 7840 #define USB_COUNT6_RX_NUM_BLOCK_2 (0x04U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 7841 #define USB_COUNT6_RX_NUM_BLOCK_3 (0x08U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 7842 #define USB_COUNT6_RX_NUM_BLOCK_4 (0x10U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 7843
<> 148:21d94c44109e 7844 #define USB_COUNT6_RX_BLSIZE_Pos (15U)
<> 148:21d94c44109e 7845 #define USB_COUNT6_RX_BLSIZE_Msk (0x1U << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 7846 #define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */
<> 148:21d94c44109e 7847
<> 148:21d94c44109e 7848 /***************** Bit definition for USB_COUNT7_RX register ****************/
<> 148:21d94c44109e 7849 #define USB_COUNT7_RX_COUNT7_RX_Pos (0U)
<> 148:21d94c44109e 7850 #define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFU << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
<> 148:21d94c44109e 7851 #define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */
<> 148:21d94c44109e 7852
<> 148:21d94c44109e 7853 #define USB_COUNT7_RX_NUM_BLOCK_Pos (10U)
<> 148:21d94c44109e 7854 #define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
<> 148:21d94c44109e 7855 #define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
<> 148:21d94c44109e 7856 #define USB_COUNT7_RX_NUM_BLOCK_0 (0x01U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 7857 #define USB_COUNT7_RX_NUM_BLOCK_1 (0x02U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 7858 #define USB_COUNT7_RX_NUM_BLOCK_2 (0x04U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 7859 #define USB_COUNT7_RX_NUM_BLOCK_3 (0x08U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 7860 #define USB_COUNT7_RX_NUM_BLOCK_4 (0x10U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 7861
<> 148:21d94c44109e 7862 #define USB_COUNT7_RX_BLSIZE_Pos (15U)
<> 148:21d94c44109e 7863 #define USB_COUNT7_RX_BLSIZE_Msk (0x1U << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 7864 #define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */
<> 148:21d94c44109e 7865
<> 148:21d94c44109e 7866 /*----------------------------------------------------------------------------*/
<> 148:21d94c44109e 7867
<> 148:21d94c44109e 7868 /**************** Bit definition for USB_COUNT0_RX_0 register ***************/
<> 148:21d94c44109e 7869 #define USB_COUNT0_RX_0_COUNT0_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
<> 148:21d94c44109e 7870
<> 148:21d94c44109e 7871 #define USB_COUNT0_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
<> 148:21d94c44109e 7872 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
<> 148:21d94c44109e 7873 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
<> 148:21d94c44109e 7874 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
<> 148:21d94c44109e 7875 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
<> 148:21d94c44109e 7876 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
<> 148:21d94c44109e 7877
<> 148:21d94c44109e 7878 #define USB_COUNT0_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
<> 148:21d94c44109e 7879
<> 148:21d94c44109e 7880 /**************** Bit definition for USB_COUNT0_RX_1 register ***************/
<> 148:21d94c44109e 7881 #define USB_COUNT0_RX_1_COUNT0_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
<> 148:21d94c44109e 7882
<> 148:21d94c44109e 7883 #define USB_COUNT0_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
<> 148:21d94c44109e 7884 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 1 */
<> 148:21d94c44109e 7885 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
<> 148:21d94c44109e 7886 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
<> 148:21d94c44109e 7887 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
<> 148:21d94c44109e 7888 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
<> 148:21d94c44109e 7889
<> 148:21d94c44109e 7890 #define USB_COUNT0_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
<> 148:21d94c44109e 7891
<> 148:21d94c44109e 7892 /**************** Bit definition for USB_COUNT1_RX_0 register ***************/
<> 148:21d94c44109e 7893 #define USB_COUNT1_RX_0_COUNT1_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
<> 148:21d94c44109e 7894
<> 148:21d94c44109e 7895 #define USB_COUNT1_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
<> 148:21d94c44109e 7896 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
<> 148:21d94c44109e 7897 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
<> 148:21d94c44109e 7898 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
<> 148:21d94c44109e 7899 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
<> 148:21d94c44109e 7900 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
<> 148:21d94c44109e 7901
<> 148:21d94c44109e 7902 #define USB_COUNT1_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
<> 148:21d94c44109e 7903
<> 148:21d94c44109e 7904 /**************** Bit definition for USB_COUNT1_RX_1 register ***************/
<> 148:21d94c44109e 7905 #define USB_COUNT1_RX_1_COUNT1_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
<> 148:21d94c44109e 7906
<> 148:21d94c44109e 7907 #define USB_COUNT1_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
<> 148:21d94c44109e 7908 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
<> 148:21d94c44109e 7909 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
<> 148:21d94c44109e 7910 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
<> 148:21d94c44109e 7911 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
<> 148:21d94c44109e 7912 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
<> 148:21d94c44109e 7913
<> 148:21d94c44109e 7914 #define USB_COUNT1_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
<> 148:21d94c44109e 7915
<> 148:21d94c44109e 7916 /**************** Bit definition for USB_COUNT2_RX_0 register ***************/
<> 148:21d94c44109e 7917 #define USB_COUNT2_RX_0_COUNT2_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
<> 148:21d94c44109e 7918
<> 148:21d94c44109e 7919 #define USB_COUNT2_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
<> 148:21d94c44109e 7920 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
<> 148:21d94c44109e 7921 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
<> 148:21d94c44109e 7922 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
<> 148:21d94c44109e 7923 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
<> 148:21d94c44109e 7924 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
<> 148:21d94c44109e 7925
<> 148:21d94c44109e 7926 #define USB_COUNT2_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
<> 148:21d94c44109e 7927
<> 148:21d94c44109e 7928 /**************** Bit definition for USB_COUNT2_RX_1 register ***************/
<> 148:21d94c44109e 7929 #define USB_COUNT2_RX_1_COUNT2_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
<> 148:21d94c44109e 7930
<> 148:21d94c44109e 7931 #define USB_COUNT2_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
<> 148:21d94c44109e 7932 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
<> 148:21d94c44109e 7933 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
<> 148:21d94c44109e 7934 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
<> 148:21d94c44109e 7935 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
<> 148:21d94c44109e 7936 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
<> 148:21d94c44109e 7937
<> 148:21d94c44109e 7938 #define USB_COUNT2_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
<> 148:21d94c44109e 7939
<> 148:21d94c44109e 7940 /**************** Bit definition for USB_COUNT3_RX_0 register ***************/
<> 148:21d94c44109e 7941 #define USB_COUNT3_RX_0_COUNT3_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
<> 148:21d94c44109e 7942
<> 148:21d94c44109e 7943 #define USB_COUNT3_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
<> 148:21d94c44109e 7944 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
<> 148:21d94c44109e 7945 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
<> 148:21d94c44109e 7946 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
<> 148:21d94c44109e 7947 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
<> 148:21d94c44109e 7948 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
<> 148:21d94c44109e 7949
<> 148:21d94c44109e 7950 #define USB_COUNT3_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
<> 148:21d94c44109e 7951
<> 148:21d94c44109e 7952 /**************** Bit definition for USB_COUNT3_RX_1 register ***************/
<> 148:21d94c44109e 7953 #define USB_COUNT3_RX_1_COUNT3_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
<> 148:21d94c44109e 7954
<> 148:21d94c44109e 7955 #define USB_COUNT3_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
<> 148:21d94c44109e 7956 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
<> 148:21d94c44109e 7957 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
<> 148:21d94c44109e 7958 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
<> 148:21d94c44109e 7959 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
<> 148:21d94c44109e 7960 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
<> 148:21d94c44109e 7961
<> 148:21d94c44109e 7962 #define USB_COUNT3_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
<> 148:21d94c44109e 7963
<> 148:21d94c44109e 7964 /**************** Bit definition for USB_COUNT4_RX_0 register ***************/
<> 148:21d94c44109e 7965 #define USB_COUNT4_RX_0_COUNT4_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
<> 148:21d94c44109e 7966
<> 148:21d94c44109e 7967 #define USB_COUNT4_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
<> 148:21d94c44109e 7968 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
<> 148:21d94c44109e 7969 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
<> 148:21d94c44109e 7970 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
<> 148:21d94c44109e 7971 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
<> 148:21d94c44109e 7972 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
<> 148:21d94c44109e 7973
<> 148:21d94c44109e 7974 #define USB_COUNT4_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
<> 148:21d94c44109e 7975
<> 148:21d94c44109e 7976 /**************** Bit definition for USB_COUNT4_RX_1 register ***************/
<> 148:21d94c44109e 7977 #define USB_COUNT4_RX_1_COUNT4_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
<> 148:21d94c44109e 7978
<> 148:21d94c44109e 7979 #define USB_COUNT4_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
<> 148:21d94c44109e 7980 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
<> 148:21d94c44109e 7981 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
<> 148:21d94c44109e 7982 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
<> 148:21d94c44109e 7983 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
<> 148:21d94c44109e 7984 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
<> 148:21d94c44109e 7985
<> 148:21d94c44109e 7986 #define USB_COUNT4_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
<> 148:21d94c44109e 7987
<> 148:21d94c44109e 7988 /**************** Bit definition for USB_COUNT5_RX_0 register ***************/
<> 148:21d94c44109e 7989 #define USB_COUNT5_RX_0_COUNT5_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
<> 148:21d94c44109e 7990
<> 148:21d94c44109e 7991 #define USB_COUNT5_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
<> 148:21d94c44109e 7992 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
<> 148:21d94c44109e 7993 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
<> 148:21d94c44109e 7994 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
<> 148:21d94c44109e 7995 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
<> 148:21d94c44109e 7996 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
<> 148:21d94c44109e 7997
<> 148:21d94c44109e 7998 #define USB_COUNT5_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
<> 148:21d94c44109e 7999
<> 148:21d94c44109e 8000 /**************** Bit definition for USB_COUNT5_RX_1 register ***************/
<> 148:21d94c44109e 8001 #define USB_COUNT5_RX_1_COUNT5_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
<> 148:21d94c44109e 8002
<> 148:21d94c44109e 8003 #define USB_COUNT5_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
<> 148:21d94c44109e 8004 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
<> 148:21d94c44109e 8005 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
<> 148:21d94c44109e 8006 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
<> 148:21d94c44109e 8007 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
<> 148:21d94c44109e 8008 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
<> 148:21d94c44109e 8009
<> 148:21d94c44109e 8010 #define USB_COUNT5_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
<> 148:21d94c44109e 8011
<> 148:21d94c44109e 8012 /*************** Bit definition for USB_COUNT6_RX_0 register ***************/
<> 148:21d94c44109e 8013 #define USB_COUNT6_RX_0_COUNT6_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
<> 148:21d94c44109e 8014
<> 148:21d94c44109e 8015 #define USB_COUNT6_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
<> 148:21d94c44109e 8016 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
<> 148:21d94c44109e 8017 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
<> 148:21d94c44109e 8018 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
<> 148:21d94c44109e 8019 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
<> 148:21d94c44109e 8020 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
<> 148:21d94c44109e 8021
<> 148:21d94c44109e 8022 #define USB_COUNT6_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
<> 148:21d94c44109e 8023
<> 148:21d94c44109e 8024 /**************** Bit definition for USB_COUNT6_RX_1 register ***************/
<> 148:21d94c44109e 8025 #define USB_COUNT6_RX_1_COUNT6_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
<> 148:21d94c44109e 8026
<> 148:21d94c44109e 8027 #define USB_COUNT6_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
<> 148:21d94c44109e 8028 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
<> 148:21d94c44109e 8029 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
<> 148:21d94c44109e 8030 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
<> 148:21d94c44109e 8031 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
<> 148:21d94c44109e 8032 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
<> 148:21d94c44109e 8033
<> 148:21d94c44109e 8034 #define USB_COUNT6_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
<> 148:21d94c44109e 8035
<> 148:21d94c44109e 8036 /*************** Bit definition for USB_COUNT7_RX_0 register ****************/
<> 148:21d94c44109e 8037 #define USB_COUNT7_RX_0_COUNT7_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
<> 148:21d94c44109e 8038
<> 148:21d94c44109e 8039 #define USB_COUNT7_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
<> 148:21d94c44109e 8040 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
<> 148:21d94c44109e 8041 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
<> 148:21d94c44109e 8042 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
<> 148:21d94c44109e 8043 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
<> 148:21d94c44109e 8044 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
<> 148:21d94c44109e 8045
<> 148:21d94c44109e 8046 #define USB_COUNT7_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
<> 148:21d94c44109e 8047
<> 148:21d94c44109e 8048 /*************** Bit definition for USB_COUNT7_RX_1 register ****************/
<> 148:21d94c44109e 8049 #define USB_COUNT7_RX_1_COUNT7_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
<> 148:21d94c44109e 8050
<> 148:21d94c44109e 8051 #define USB_COUNT7_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
<> 148:21d94c44109e 8052 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
<> 148:21d94c44109e 8053 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
<> 148:21d94c44109e 8054 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
<> 148:21d94c44109e 8055 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
<> 148:21d94c44109e 8056 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
<> 148:21d94c44109e 8057
<> 148:21d94c44109e 8058 #define USB_COUNT7_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
<> 148:21d94c44109e 8059
<> 148:21d94c44109e 8060 /******************************************************************************/
<> 148:21d94c44109e 8061 /* */
<> 148:21d94c44109e 8062 /* Window WATCHDOG (WWDG) */
<> 148:21d94c44109e 8063 /* */
<> 148:21d94c44109e 8064 /******************************************************************************/
<> 148:21d94c44109e 8065
<> 148:21d94c44109e 8066 /******************* Bit definition for WWDG_CR register ********************/
<> 148:21d94c44109e 8067 #define WWDG_CR_T_Pos (0U)
<> 148:21d94c44109e 8068 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
<> 148:21d94c44109e 8069 #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
<> 148:21d94c44109e 8070 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 8071 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 8072 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 8073 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 8074 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 8075 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 8076 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 8077
<> 148:21d94c44109e 8078 /* Legacy defines */
<> 148:21d94c44109e 8079 #define WWDG_CR_T0 WWDG_CR_T_0
<> 148:21d94c44109e 8080 #define WWDG_CR_T1 WWDG_CR_T_1
<> 148:21d94c44109e 8081 #define WWDG_CR_T2 WWDG_CR_T_2
<> 148:21d94c44109e 8082 #define WWDG_CR_T3 WWDG_CR_T_3
<> 148:21d94c44109e 8083 #define WWDG_CR_T4 WWDG_CR_T_4
<> 148:21d94c44109e 8084 #define WWDG_CR_T5 WWDG_CR_T_5
<> 148:21d94c44109e 8085 #define WWDG_CR_T6 WWDG_CR_T_6
<> 148:21d94c44109e 8086
<> 148:21d94c44109e 8087 #define WWDG_CR_WDGA_Pos (7U)
<> 148:21d94c44109e 8088 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 8089 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
<> 148:21d94c44109e 8090
<> 148:21d94c44109e 8091 /******************* Bit definition for WWDG_CFR register *******************/
<> 148:21d94c44109e 8092 #define WWDG_CFR_W_Pos (0U)
<> 148:21d94c44109e 8093 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
<> 148:21d94c44109e 8094 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
<> 148:21d94c44109e 8095 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 8096 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 8097 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 8098 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 8099 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 8100 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 8101 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 8102
<> 148:21d94c44109e 8103 /* Legacy defines */
<> 148:21d94c44109e 8104 #define WWDG_CFR_W0 WWDG_CFR_W_0
<> 148:21d94c44109e 8105 #define WWDG_CFR_W1 WWDG_CFR_W_1
<> 148:21d94c44109e 8106 #define WWDG_CFR_W2 WWDG_CFR_W_2
<> 148:21d94c44109e 8107 #define WWDG_CFR_W3 WWDG_CFR_W_3
<> 148:21d94c44109e 8108 #define WWDG_CFR_W4 WWDG_CFR_W_4
<> 148:21d94c44109e 8109 #define WWDG_CFR_W5 WWDG_CFR_W_5
<> 148:21d94c44109e 8110 #define WWDG_CFR_W6 WWDG_CFR_W_6
<> 148:21d94c44109e 8111
<> 148:21d94c44109e 8112 #define WWDG_CFR_WDGTB_Pos (7U)
<> 148:21d94c44109e 8113 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
<> 148:21d94c44109e 8114 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
<> 148:21d94c44109e 8115 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 8116 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 8117
<> 148:21d94c44109e 8118 /* Legacy defines */
<> 148:21d94c44109e 8119 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
<> 148:21d94c44109e 8120 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
<> 148:21d94c44109e 8121
<> 148:21d94c44109e 8122 #define WWDG_CFR_EWI_Pos (9U)
<> 148:21d94c44109e 8123 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 8124 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
<> 148:21d94c44109e 8125
<> 148:21d94c44109e 8126 /******************* Bit definition for WWDG_SR register ********************/
<> 148:21d94c44109e 8127 #define WWDG_SR_EWIF_Pos (0U)
<> 148:21d94c44109e 8128 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 8129 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
<> 148:21d94c44109e 8130
<> 148:21d94c44109e 8131 /******************************************************************************/
<> 148:21d94c44109e 8132 /* */
<> 148:21d94c44109e 8133 /* SystemTick (SysTick) */
<> 148:21d94c44109e 8134 /* */
<> 148:21d94c44109e 8135 /******************************************************************************/
<> 148:21d94c44109e 8136
<> 148:21d94c44109e 8137 /***************** Bit definition for SysTick_CTRL register *****************/
<> 148:21d94c44109e 8138 #define SysTick_CTRL_ENABLE (0x00000001U) /*!< Counter enable */
<> 148:21d94c44109e 8139 #define SysTick_CTRL_TICKINT (0x00000002U) /*!< Counting down to 0 pends the SysTick handler */
<> 148:21d94c44109e 8140 #define SysTick_CTRL_CLKSOURCE (0x00000004U) /*!< Clock source */
<> 148:21d94c44109e 8141 #define SysTick_CTRL_COUNTFLAG (0x00010000U) /*!< Count Flag */
<> 148:21d94c44109e 8142
<> 148:21d94c44109e 8143 /***************** Bit definition for SysTick_LOAD register *****************/
<> 148:21d94c44109e 8144 #define SysTick_LOAD_RELOAD (0x00FFFFFFU) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
<> 148:21d94c44109e 8145
<> 148:21d94c44109e 8146 /***************** Bit definition for SysTick_VAL register ******************/
<> 148:21d94c44109e 8147 #define SysTick_VAL_CURRENT (0x00FFFFFFU) /*!< Current value at the time the register is accessed */
<> 148:21d94c44109e 8148
<> 148:21d94c44109e 8149 /***************** Bit definition for SysTick_CALIB register ****************/
<> 148:21d94c44109e 8150 #define SysTick_CALIB_TENMS (0x00FFFFFFU) /*!< Reload value to use for 10ms timing */
<> 148:21d94c44109e 8151 #define SysTick_CALIB_SKEW (0x40000000U) /*!< Calibration value is not exactly 10 ms */
<> 148:21d94c44109e 8152 #define SysTick_CALIB_NOREF (0x80000000U) /*!< The reference clock is not provided */
<> 148:21d94c44109e 8153
<> 148:21d94c44109e 8154 /******************************************************************************/
<> 148:21d94c44109e 8155 /* */
<> 148:21d94c44109e 8156 /* Nested Vectored Interrupt Controller (NVIC) */
<> 148:21d94c44109e 8157 /* */
<> 148:21d94c44109e 8158 /******************************************************************************/
<> 148:21d94c44109e 8159
<> 148:21d94c44109e 8160 /****************** Bit definition for NVIC_ISER register *******************/
<> 148:21d94c44109e 8161 #define NVIC_ISER_SETENA_Pos (0U)
<> 148:21d94c44109e 8162 #define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 8163 #define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */
<> 148:21d94c44109e 8164 #define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 8165 #define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 8166 #define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 8167 #define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 8168 #define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 8169 #define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 8170 #define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 8171 #define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 8172 #define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 8173 #define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 8174 #define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 8175 #define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 8176 #define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 8177 #define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 8178 #define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 8179 #define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 8180 #define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 8181 #define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 8182 #define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 8183 #define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 8184 #define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 8185 #define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 8186 #define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 8187 #define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 8188 #define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */
<> 148:21d94c44109e 8189 #define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */
<> 148:21d94c44109e 8190 #define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */
<> 148:21d94c44109e 8191 #define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */
<> 148:21d94c44109e 8192 #define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */
<> 148:21d94c44109e 8193 #define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */
<> 148:21d94c44109e 8194 #define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */
<> 148:21d94c44109e 8195 #define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */
<> 148:21d94c44109e 8196
<> 148:21d94c44109e 8197 /****************** Bit definition for NVIC_ICER register *******************/
<> 148:21d94c44109e 8198 #define NVIC_ICER_CLRENA_Pos (0U)
<> 148:21d94c44109e 8199 #define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 8200 #define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */
<> 148:21d94c44109e 8201 #define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 8202 #define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 8203 #define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 8204 #define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 8205 #define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 8206 #define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 8207 #define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 8208 #define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 8209 #define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 8210 #define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 8211 #define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 8212 #define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 8213 #define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 8214 #define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 8215 #define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 8216 #define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 8217 #define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 8218 #define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 8219 #define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 8220 #define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 8221 #define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 8222 #define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 8223 #define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 8224 #define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 8225 #define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */
<> 148:21d94c44109e 8226 #define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */
<> 148:21d94c44109e 8227 #define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */
<> 148:21d94c44109e 8228 #define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */
<> 148:21d94c44109e 8229 #define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */
<> 148:21d94c44109e 8230 #define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */
<> 148:21d94c44109e 8231 #define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */
<> 148:21d94c44109e 8232 #define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */
<> 148:21d94c44109e 8233
<> 148:21d94c44109e 8234 /****************** Bit definition for NVIC_ISPR register *******************/
<> 148:21d94c44109e 8235 #define NVIC_ISPR_SETPEND_Pos (0U)
<> 148:21d94c44109e 8236 #define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 8237 #define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */
<> 148:21d94c44109e 8238 #define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 8239 #define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 8240 #define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 8241 #define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 8242 #define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 8243 #define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 8244 #define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 8245 #define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 8246 #define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 8247 #define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 8248 #define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 8249 #define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 8250 #define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 8251 #define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 8252 #define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 8253 #define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 8254 #define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 8255 #define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 8256 #define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 8257 #define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 8258 #define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 8259 #define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 8260 #define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 8261 #define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 8262 #define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */
<> 148:21d94c44109e 8263 #define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */
<> 148:21d94c44109e 8264 #define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */
<> 148:21d94c44109e 8265 #define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */
<> 148:21d94c44109e 8266 #define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */
<> 148:21d94c44109e 8267 #define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */
<> 148:21d94c44109e 8268 #define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */
<> 148:21d94c44109e 8269 #define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */
<> 148:21d94c44109e 8270
<> 148:21d94c44109e 8271 /****************** Bit definition for NVIC_ICPR register *******************/
<> 148:21d94c44109e 8272 #define NVIC_ICPR_CLRPEND_Pos (0U)
<> 148:21d94c44109e 8273 #define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 8274 #define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */
<> 148:21d94c44109e 8275 #define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 8276 #define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 8277 #define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 8278 #define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 8279 #define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 8280 #define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 8281 #define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 8282 #define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 8283 #define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 8284 #define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 8285 #define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 8286 #define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 8287 #define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 8288 #define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 8289 #define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 8290 #define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 8291 #define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 8292 #define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 8293 #define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 8294 #define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 8295 #define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 8296 #define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 8297 #define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 8298 #define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 8299 #define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */
<> 148:21d94c44109e 8300 #define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */
<> 148:21d94c44109e 8301 #define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */
<> 148:21d94c44109e 8302 #define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */
<> 148:21d94c44109e 8303 #define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */
<> 148:21d94c44109e 8304 #define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */
<> 148:21d94c44109e 8305 #define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */
<> 148:21d94c44109e 8306 #define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */
<> 148:21d94c44109e 8307
<> 148:21d94c44109e 8308 /****************** Bit definition for NVIC_IABR register *******************/
<> 148:21d94c44109e 8309 #define NVIC_IABR_ACTIVE_Pos (0U)
<> 148:21d94c44109e 8310 #define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 8311 #define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */
<> 148:21d94c44109e 8312 #define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 8313 #define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 8314 #define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */
<> 148:21d94c44109e 8315 #define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 8316 #define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 8317 #define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */
<> 148:21d94c44109e 8318 #define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */
<> 148:21d94c44109e 8319 #define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 8320 #define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 8321 #define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 8322 #define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 8323 #define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 8324 #define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 8325 #define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */
<> 148:21d94c44109e 8326 #define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */
<> 148:21d94c44109e 8327 #define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 8328 #define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 8329 #define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 8330 #define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 8331 #define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 8332 #define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */
<> 148:21d94c44109e 8333 #define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */
<> 148:21d94c44109e 8334 #define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */
<> 148:21d94c44109e 8335 #define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */
<> 148:21d94c44109e 8336 #define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */
<> 148:21d94c44109e 8337 #define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */
<> 148:21d94c44109e 8338 #define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */
<> 148:21d94c44109e 8339 #define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */
<> 148:21d94c44109e 8340 #define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */
<> 148:21d94c44109e 8341 #define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */
<> 148:21d94c44109e 8342 #define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */
<> 148:21d94c44109e 8343 #define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */
<> 148:21d94c44109e 8344
<> 148:21d94c44109e 8345 /****************** Bit definition for NVIC_PRI0 register *******************/
<> 148:21d94c44109e 8346 #define NVIC_IPR0_PRI_0 (0x000000FFU) /*!< Priority of interrupt 0 */
<> 148:21d94c44109e 8347 #define NVIC_IPR0_PRI_1 (0x0000FF00U) /*!< Priority of interrupt 1 */
<> 148:21d94c44109e 8348 #define NVIC_IPR0_PRI_2 (0x00FF0000U) /*!< Priority of interrupt 2 */
<> 148:21d94c44109e 8349 #define NVIC_IPR0_PRI_3 (0xFF000000U) /*!< Priority of interrupt 3 */
<> 148:21d94c44109e 8350
<> 148:21d94c44109e 8351 /****************** Bit definition for NVIC_PRI1 register *******************/
<> 148:21d94c44109e 8352 #define NVIC_IPR1_PRI_4 (0x000000FFU) /*!< Priority of interrupt 4 */
<> 148:21d94c44109e 8353 #define NVIC_IPR1_PRI_5 (0x0000FF00U) /*!< Priority of interrupt 5 */
<> 148:21d94c44109e 8354 #define NVIC_IPR1_PRI_6 (0x00FF0000U) /*!< Priority of interrupt 6 */
<> 148:21d94c44109e 8355 #define NVIC_IPR1_PRI_7 (0xFF000000U) /*!< Priority of interrupt 7 */
<> 148:21d94c44109e 8356
<> 148:21d94c44109e 8357 /****************** Bit definition for NVIC_PRI2 register *******************/
<> 148:21d94c44109e 8358 #define NVIC_IPR2_PRI_8 (0x000000FFU) /*!< Priority of interrupt 8 */
<> 148:21d94c44109e 8359 #define NVIC_IPR2_PRI_9 (0x0000FF00U) /*!< Priority of interrupt 9 */
<> 148:21d94c44109e 8360 #define NVIC_IPR2_PRI_10 (0x00FF0000U) /*!< Priority of interrupt 10 */
<> 148:21d94c44109e 8361 #define NVIC_IPR2_PRI_11 (0xFF000000U) /*!< Priority of interrupt 11 */
<> 148:21d94c44109e 8362
<> 148:21d94c44109e 8363 /****************** Bit definition for NVIC_PRI3 register *******************/
<> 148:21d94c44109e 8364 #define NVIC_IPR3_PRI_12 (0x000000FFU) /*!< Priority of interrupt 12 */
<> 148:21d94c44109e 8365 #define NVIC_IPR3_PRI_13 (0x0000FF00U) /*!< Priority of interrupt 13 */
<> 148:21d94c44109e 8366 #define NVIC_IPR3_PRI_14 (0x00FF0000U) /*!< Priority of interrupt 14 */
<> 148:21d94c44109e 8367 #define NVIC_IPR3_PRI_15 (0xFF000000U) /*!< Priority of interrupt 15 */
<> 148:21d94c44109e 8368
<> 148:21d94c44109e 8369 /****************** Bit definition for NVIC_PRI4 register *******************/
<> 148:21d94c44109e 8370 #define NVIC_IPR4_PRI_16 (0x000000FFU) /*!< Priority of interrupt 16 */
<> 148:21d94c44109e 8371 #define NVIC_IPR4_PRI_17 (0x0000FF00U) /*!< Priority of interrupt 17 */
<> 148:21d94c44109e 8372 #define NVIC_IPR4_PRI_18 (0x00FF0000U) /*!< Priority of interrupt 18 */
<> 148:21d94c44109e 8373 #define NVIC_IPR4_PRI_19 (0xFF000000U) /*!< Priority of interrupt 19 */
<> 148:21d94c44109e 8374
<> 148:21d94c44109e 8375 /****************** Bit definition for NVIC_PRI5 register *******************/
<> 148:21d94c44109e 8376 #define NVIC_IPR5_PRI_20 (0x000000FFU) /*!< Priority of interrupt 20 */
<> 148:21d94c44109e 8377 #define NVIC_IPR5_PRI_21 (0x0000FF00U) /*!< Priority of interrupt 21 */
<> 148:21d94c44109e 8378 #define NVIC_IPR5_PRI_22 (0x00FF0000U) /*!< Priority of interrupt 22 */
<> 148:21d94c44109e 8379 #define NVIC_IPR5_PRI_23 (0xFF000000U) /*!< Priority of interrupt 23 */
<> 148:21d94c44109e 8380
<> 148:21d94c44109e 8381 /****************** Bit definition for NVIC_PRI6 register *******************/
<> 148:21d94c44109e 8382 #define NVIC_IPR6_PRI_24 (0x000000FFU) /*!< Priority of interrupt 24 */
<> 148:21d94c44109e 8383 #define NVIC_IPR6_PRI_25 (0x0000FF00U) /*!< Priority of interrupt 25 */
<> 148:21d94c44109e 8384 #define NVIC_IPR6_PRI_26 (0x00FF0000U) /*!< Priority of interrupt 26 */
<> 148:21d94c44109e 8385 #define NVIC_IPR6_PRI_27 (0xFF000000U) /*!< Priority of interrupt 27 */
<> 148:21d94c44109e 8386
<> 148:21d94c44109e 8387 /****************** Bit definition for NVIC_PRI7 register *******************/
<> 148:21d94c44109e 8388 #define NVIC_IPR7_PRI_28 (0x000000FFU) /*!< Priority of interrupt 28 */
<> 148:21d94c44109e 8389 #define NVIC_IPR7_PRI_29 (0x0000FF00U) /*!< Priority of interrupt 29 */
<> 148:21d94c44109e 8390 #define NVIC_IPR7_PRI_30 (0x00FF0000U) /*!< Priority of interrupt 30 */
<> 148:21d94c44109e 8391 #define NVIC_IPR7_PRI_31 (0xFF000000U) /*!< Priority of interrupt 31 */
<> 148:21d94c44109e 8392
<> 148:21d94c44109e 8393 /****************** Bit definition for SCB_CPUID register *******************/
<> 148:21d94c44109e 8394 #define SCB_CPUID_REVISION (0x0000000FU) /*!< Implementation defined revision number */
<> 148:21d94c44109e 8395 #define SCB_CPUID_PARTNO (0x0000FFF0U) /*!< Number of processor within serie */
<> 148:21d94c44109e 8396 #define SCB_CPUID_Constant (0x000F0000U) /*!< Reads as 0x0F */
<> 148:21d94c44109e 8397 #define SCB_CPUID_VARIANT (0x00F00000U) /*!< Implementation defined variant number */
<> 148:21d94c44109e 8398 #define SCB_CPUID_IMPLEMENTER (0xFF000000U) /*!< Implementer code. ARM is 0x41 */
<> 148:21d94c44109e 8399
<> 148:21d94c44109e 8400 /******************* Bit definition for SCB_ICSR register *******************/
<> 148:21d94c44109e 8401 #define SCB_ICSR_VECTACTIVE (0x000001FFU) /*!< Active ISR number field */
<> 148:21d94c44109e 8402 #define SCB_ICSR_RETTOBASE (0x00000800U) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
<> 148:21d94c44109e 8403 #define SCB_ICSR_VECTPENDING (0x003FF000U) /*!< Pending ISR number field */
<> 148:21d94c44109e 8404 #define SCB_ICSR_ISRPENDING (0x00400000U) /*!< Interrupt pending flag */
<> 148:21d94c44109e 8405 #define SCB_ICSR_ISRPREEMPT (0x00800000U) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
<> 148:21d94c44109e 8406 #define SCB_ICSR_PENDSTCLR (0x02000000U) /*!< Clear pending SysTick bit */
<> 148:21d94c44109e 8407 #define SCB_ICSR_PENDSTSET (0x04000000U) /*!< Set pending SysTick bit */
<> 148:21d94c44109e 8408 #define SCB_ICSR_PENDSVCLR (0x08000000U) /*!< Clear pending pendSV bit */
<> 148:21d94c44109e 8409 #define SCB_ICSR_PENDSVSET (0x10000000U) /*!< Set pending pendSV bit */
<> 148:21d94c44109e 8410 #define SCB_ICSR_NMIPENDSET (0x80000000U) /*!< Set pending NMI bit */
<> 148:21d94c44109e 8411
<> 148:21d94c44109e 8412 /******************* Bit definition for SCB_VTOR register *******************/
<> 148:21d94c44109e 8413 #define SCB_VTOR_TBLOFF (0x1FFFFF80U) /*!< Vector table base offset field */
<> 148:21d94c44109e 8414 #define SCB_VTOR_TBLBASE (0x20000000U) /*!< Table base in code(0) or RAM(1) */
<> 148:21d94c44109e 8415
<> 148:21d94c44109e 8416 /*!<***************** Bit definition for SCB_AIRCR register *******************/
<> 148:21d94c44109e 8417 #define SCB_AIRCR_VECTRESET (0x00000001U) /*!< System Reset bit */
<> 148:21d94c44109e 8418 #define SCB_AIRCR_VECTCLRACTIVE (0x00000002U) /*!< Clear active vector bit */
<> 148:21d94c44109e 8419 #define SCB_AIRCR_SYSRESETREQ (0x00000004U) /*!< Requests chip control logic to generate a reset */
<> 148:21d94c44109e 8420
<> 148:21d94c44109e 8421 #define SCB_AIRCR_PRIGROUP (0x00000700U) /*!< PRIGROUP[2:0] bits (Priority group) */
<> 148:21d94c44109e 8422 #define SCB_AIRCR_PRIGROUP_0 (0x00000100U) /*!< Bit 0 */
<> 148:21d94c44109e 8423 #define SCB_AIRCR_PRIGROUP_1 (0x00000200U) /*!< Bit 1 */
<> 148:21d94c44109e 8424 #define SCB_AIRCR_PRIGROUP_2 (0x00000400U) /*!< Bit 2 */
<> 148:21d94c44109e 8425
<> 148:21d94c44109e 8426 /* prority group configuration */
<> 148:21d94c44109e 8427 #define SCB_AIRCR_PRIGROUP0 (0x00000000U) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
<> 148:21d94c44109e 8428 #define SCB_AIRCR_PRIGROUP1 (0x00000100U) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
<> 148:21d94c44109e 8429 #define SCB_AIRCR_PRIGROUP2 (0x00000200U) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
<> 148:21d94c44109e 8430 #define SCB_AIRCR_PRIGROUP3 (0x00000300U) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
<> 148:21d94c44109e 8431 #define SCB_AIRCR_PRIGROUP4 (0x00000400U) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
<> 148:21d94c44109e 8432 #define SCB_AIRCR_PRIGROUP5 (0x00000500U) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
<> 148:21d94c44109e 8433 #define SCB_AIRCR_PRIGROUP6 (0x00000600U) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
<> 148:21d94c44109e 8434 #define SCB_AIRCR_PRIGROUP7 (0x00000700U) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
<> 148:21d94c44109e 8435
<> 148:21d94c44109e 8436 #define SCB_AIRCR_ENDIANESS (0x00008000U) /*!< Data endianness bit */
<> 148:21d94c44109e 8437 #define SCB_AIRCR_VECTKEY (0xFFFF0000U) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
<> 148:21d94c44109e 8438
<> 148:21d94c44109e 8439 /******************* Bit definition for SCB_SCR register ********************/
<> 148:21d94c44109e 8440 #define SCB_SCR_SLEEPONEXIT (0x00000002U) /*!< Sleep on exit bit */
<> 148:21d94c44109e 8441 #define SCB_SCR_SLEEPDEEP (0x00000004U) /*!< Sleep deep bit */
<> 148:21d94c44109e 8442 #define SCB_SCR_SEVONPEND (0x00000010U) /*!< Wake up from WFE */
<> 148:21d94c44109e 8443
<> 148:21d94c44109e 8444 /******************** Bit definition for SCB_CCR register *******************/
<> 148:21d94c44109e 8445 #define SCB_CCR_NONBASETHRDENA (0x00000001U) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
<> 148:21d94c44109e 8446 #define SCB_CCR_USERSETMPEND (0x00000002U) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
<> 148:21d94c44109e 8447 #define SCB_CCR_UNALIGN_TRP (0x00000008U) /*!< Trap for unaligned access */
<> 148:21d94c44109e 8448 #define SCB_CCR_DIV_0_TRP (0x00000010U) /*!< Trap on Divide by 0 */
<> 148:21d94c44109e 8449 #define SCB_CCR_BFHFNMIGN (0x00000100U) /*!< Handlers running at priority -1 and -2 */
<> 148:21d94c44109e 8450 #define SCB_CCR_STKALIGN (0x00000200U) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
<> 148:21d94c44109e 8451
<> 148:21d94c44109e 8452 /******************* Bit definition for SCB_SHPR register ********************/
<> 148:21d94c44109e 8453 #define SCB_SHPR_PRI_N_Pos (0U)
<> 148:21d94c44109e 8454 #define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */
<> 148:21d94c44109e 8455 #define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
<> 148:21d94c44109e 8456 #define SCB_SHPR_PRI_N1_Pos (8U)
<> 148:21d94c44109e 8457 #define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */
<> 148:21d94c44109e 8458 #define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
<> 148:21d94c44109e 8459 #define SCB_SHPR_PRI_N2_Pos (16U)
<> 148:21d94c44109e 8460 #define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */
<> 148:21d94c44109e 8461 #define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
<> 148:21d94c44109e 8462 #define SCB_SHPR_PRI_N3_Pos (24U)
<> 148:21d94c44109e 8463 #define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */
<> 148:21d94c44109e 8464 #define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
<> 148:21d94c44109e 8465
<> 148:21d94c44109e 8466 /****************** Bit definition for SCB_SHCSR register *******************/
<> 148:21d94c44109e 8467 #define SCB_SHCSR_MEMFAULTACT (0x00000001U) /*!< MemManage is active */
<> 148:21d94c44109e 8468 #define SCB_SHCSR_BUSFAULTACT (0x00000002U) /*!< BusFault is active */
<> 148:21d94c44109e 8469 #define SCB_SHCSR_USGFAULTACT (0x00000008U) /*!< UsageFault is active */
<> 148:21d94c44109e 8470 #define SCB_SHCSR_SVCALLACT (0x00000080U) /*!< SVCall is active */
<> 148:21d94c44109e 8471 #define SCB_SHCSR_MONITORACT (0x00000100U) /*!< Monitor is active */
<> 148:21d94c44109e 8472 #define SCB_SHCSR_PENDSVACT (0x00000400U) /*!< PendSV is active */
<> 148:21d94c44109e 8473 #define SCB_SHCSR_SYSTICKACT (0x00000800U) /*!< SysTick is active */
<> 148:21d94c44109e 8474 #define SCB_SHCSR_USGFAULTPENDED (0x00001000U) /*!< Usage Fault is pended */
<> 148:21d94c44109e 8475 #define SCB_SHCSR_MEMFAULTPENDED (0x00002000U) /*!< MemManage is pended */
<> 148:21d94c44109e 8476 #define SCB_SHCSR_BUSFAULTPENDED (0x00004000U) /*!< Bus Fault is pended */
<> 148:21d94c44109e 8477 #define SCB_SHCSR_SVCALLPENDED (0x00008000U) /*!< SVCall is pended */
<> 148:21d94c44109e 8478 #define SCB_SHCSR_MEMFAULTENA (0x00010000U) /*!< MemManage enable */
<> 148:21d94c44109e 8479 #define SCB_SHCSR_BUSFAULTENA (0x00020000U) /*!< Bus Fault enable */
<> 148:21d94c44109e 8480 #define SCB_SHCSR_USGFAULTENA (0x00040000U) /*!< UsageFault enable */
<> 148:21d94c44109e 8481
<> 148:21d94c44109e 8482 /******************* Bit definition for SCB_CFSR register *******************/
<> 148:21d94c44109e 8483 /*!< MFSR */
<> 148:21d94c44109e 8484 #define SCB_CFSR_IACCVIOL_Pos (0U)
<> 148:21d94c44109e 8485 #define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */
<> 148:21d94c44109e 8486 #define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
<> 148:21d94c44109e 8487 #define SCB_CFSR_DACCVIOL_Pos (1U)
<> 148:21d94c44109e 8488 #define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */
<> 148:21d94c44109e 8489 #define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
<> 148:21d94c44109e 8490 #define SCB_CFSR_MUNSTKERR_Pos (3U)
<> 148:21d94c44109e 8491 #define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */
<> 148:21d94c44109e 8492 #define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
<> 148:21d94c44109e 8493 #define SCB_CFSR_MSTKERR_Pos (4U)
<> 148:21d94c44109e 8494 #define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */
<> 148:21d94c44109e 8495 #define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
<> 148:21d94c44109e 8496 #define SCB_CFSR_MMARVALID_Pos (7U)
<> 148:21d94c44109e 8497 #define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */
<> 148:21d94c44109e 8498 #define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
<> 148:21d94c44109e 8499 /*!< BFSR */
<> 148:21d94c44109e 8500 #define SCB_CFSR_IBUSERR_Pos (8U)
<> 148:21d94c44109e 8501 #define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */
<> 148:21d94c44109e 8502 #define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
<> 148:21d94c44109e 8503 #define SCB_CFSR_PRECISERR_Pos (9U)
<> 148:21d94c44109e 8504 #define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */
<> 148:21d94c44109e 8505 #define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
<> 148:21d94c44109e 8506 #define SCB_CFSR_IMPRECISERR_Pos (10U)
<> 148:21d94c44109e 8507 #define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */
<> 148:21d94c44109e 8508 #define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
<> 148:21d94c44109e 8509 #define SCB_CFSR_UNSTKERR_Pos (11U)
<> 148:21d94c44109e 8510 #define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */
<> 148:21d94c44109e 8511 #define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
<> 148:21d94c44109e 8512 #define SCB_CFSR_STKERR_Pos (12U)
<> 148:21d94c44109e 8513 #define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */
<> 148:21d94c44109e 8514 #define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
<> 148:21d94c44109e 8515 #define SCB_CFSR_BFARVALID_Pos (15U)
<> 148:21d94c44109e 8516 #define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */
<> 148:21d94c44109e 8517 #define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
<> 148:21d94c44109e 8518 /*!< UFSR */
<> 148:21d94c44109e 8519 #define SCB_CFSR_UNDEFINSTR_Pos (16U)
<> 148:21d94c44109e 8520 #define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */
<> 148:21d94c44109e 8521 #define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to excecute an undefined instruction */
<> 148:21d94c44109e 8522 #define SCB_CFSR_INVSTATE_Pos (17U)
<> 148:21d94c44109e 8523 #define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */
<> 148:21d94c44109e 8524 #define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
<> 148:21d94c44109e 8525 #define SCB_CFSR_INVPC_Pos (18U)
<> 148:21d94c44109e 8526 #define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */
<> 148:21d94c44109e 8527 #define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
<> 148:21d94c44109e 8528 #define SCB_CFSR_NOCP_Pos (19U)
<> 148:21d94c44109e 8529 #define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */
<> 148:21d94c44109e 8530 #define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
<> 148:21d94c44109e 8531 #define SCB_CFSR_UNALIGNED_Pos (24U)
<> 148:21d94c44109e 8532 #define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */
<> 148:21d94c44109e 8533 #define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
<> 148:21d94c44109e 8534 #define SCB_CFSR_DIVBYZERO_Pos (25U)
<> 148:21d94c44109e 8535 #define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */
<> 148:21d94c44109e 8536 #define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
<> 148:21d94c44109e 8537
<> 148:21d94c44109e 8538 /******************* Bit definition for SCB_HFSR register *******************/
<> 148:21d94c44109e 8539 #define SCB_HFSR_VECTTBL (0x00000002U) /*!< Fault occures because of vector table read on exception processing */
<> 148:21d94c44109e 8540 #define SCB_HFSR_FORCED (0x40000000U) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
<> 148:21d94c44109e 8541 #define SCB_HFSR_DEBUGEVT (0x80000000U) /*!< Fault related to debug */
<> 148:21d94c44109e 8542
<> 148:21d94c44109e 8543 /******************* Bit definition for SCB_DFSR register *******************/
<> 148:21d94c44109e 8544 #define SCB_DFSR_HALTED (0x00000001U) /*!< Halt request flag */
<> 148:21d94c44109e 8545 #define SCB_DFSR_BKPT (0x00000002U) /*!< BKPT flag */
<> 148:21d94c44109e 8546 #define SCB_DFSR_DWTTRAP (0x00000004U) /*!< Data Watchpoint and Trace (DWT) flag */
<> 148:21d94c44109e 8547 #define SCB_DFSR_VCATCH (0x00000008U) /*!< Vector catch flag */
<> 148:21d94c44109e 8548 #define SCB_DFSR_EXTERNAL (0x00000010U) /*!< External debug request flag */
<> 148:21d94c44109e 8549
<> 148:21d94c44109e 8550 /******************* Bit definition for SCB_MMFAR register ******************/
<> 148:21d94c44109e 8551 #define SCB_MMFAR_ADDRESS_Pos (0U)
<> 148:21d94c44109e 8552 #define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 8553 #define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */
<> 148:21d94c44109e 8554
<> 148:21d94c44109e 8555 /******************* Bit definition for SCB_BFAR register *******************/
<> 148:21d94c44109e 8556 #define SCB_BFAR_ADDRESS_Pos (0U)
<> 148:21d94c44109e 8557 #define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 8558 #define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */
<> 148:21d94c44109e 8559
<> 148:21d94c44109e 8560 /******************* Bit definition for SCB_afsr register *******************/
<> 148:21d94c44109e 8561 #define SCB_AFSR_IMPDEF_Pos (0U)
<> 148:21d94c44109e 8562 #define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */
<> 148:21d94c44109e 8563 #define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */
<> 148:21d94c44109e 8564 /**
<> 148:21d94c44109e 8565 * @}
<> 148:21d94c44109e 8566 */
<> 148:21d94c44109e 8567
<> 148:21d94c44109e 8568 /**
<> 148:21d94c44109e 8569 * @}
<> 148:21d94c44109e 8570 */
<> 148:21d94c44109e 8571 /** @addtogroup Exported_macro
<> 148:21d94c44109e 8572 * @{
<> 148:21d94c44109e 8573 */
<> 148:21d94c44109e 8574
<> 148:21d94c44109e 8575 /****************************** ADC Instances *********************************/
<> 148:21d94c44109e 8576 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
<> 148:21d94c44109e 8577
<> 148:21d94c44109e 8578 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
<> 148:21d94c44109e 8579
<> 148:21d94c44109e 8580 /******************************** COMP Instances ******************************/
<> 148:21d94c44109e 8581 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
<> 148:21d94c44109e 8582 ((INSTANCE) == COMP2))
<> 148:21d94c44109e 8583
<> 148:21d94c44109e 8584 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
<> 148:21d94c44109e 8585
<> 148:21d94c44109e 8586 /****************************** CRC Instances *********************************/
<> 148:21d94c44109e 8587 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
<> 148:21d94c44109e 8588
<> 148:21d94c44109e 8589 /****************************** DAC Instances *********************************/
<> 148:21d94c44109e 8590 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
<> 148:21d94c44109e 8591
<> 148:21d94c44109e 8592 /****************************** DMA Instances *********************************/
<> 148:21d94c44109e 8593 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
<> 148:21d94c44109e 8594 ((INSTANCE) == DMA1_Channel2) || \
<> 148:21d94c44109e 8595 ((INSTANCE) == DMA1_Channel3) || \
<> 148:21d94c44109e 8596 ((INSTANCE) == DMA1_Channel4) || \
<> 148:21d94c44109e 8597 ((INSTANCE) == DMA1_Channel5) || \
<> 148:21d94c44109e 8598 ((INSTANCE) == DMA1_Channel6) || \
<> 148:21d94c44109e 8599 ((INSTANCE) == DMA1_Channel7) || \
<> 148:21d94c44109e 8600 ((INSTANCE) == DMA2_Channel1) || \
<> 148:21d94c44109e 8601 ((INSTANCE) == DMA2_Channel2) || \
<> 148:21d94c44109e 8602 ((INSTANCE) == DMA2_Channel3) || \
<> 148:21d94c44109e 8603 ((INSTANCE) == DMA2_Channel4) || \
<> 148:21d94c44109e 8604 ((INSTANCE) == DMA2_Channel5))
<> 148:21d94c44109e 8605
<> 148:21d94c44109e 8606 /******************************* GPIO Instances *******************************/
<> 148:21d94c44109e 8607 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
<> 148:21d94c44109e 8608 ((INSTANCE) == GPIOB) || \
<> 148:21d94c44109e 8609 ((INSTANCE) == GPIOC) || \
<> 148:21d94c44109e 8610 ((INSTANCE) == GPIOD) || \
<> 148:21d94c44109e 8611 ((INSTANCE) == GPIOE) || \
<> 148:21d94c44109e 8612 ((INSTANCE) == GPIOH))
<> 148:21d94c44109e 8613
<> 148:21d94c44109e 8614 /**************************** GPIO Alternate Function Instances ***************/
<> 148:21d94c44109e 8615 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
<> 148:21d94c44109e 8616
<> 148:21d94c44109e 8617 /**************************** GPIO Lock Instances *****************************/
<> 148:21d94c44109e 8618 /* On L1, all GPIO Bank support the Lock mechanism */
<> 148:21d94c44109e 8619 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
<> 148:21d94c44109e 8620
<> 148:21d94c44109e 8621 /******************************** I2C Instances *******************************/
<> 148:21d94c44109e 8622 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
<> 148:21d94c44109e 8623 ((INSTANCE) == I2C2))
<> 148:21d94c44109e 8624
<> 148:21d94c44109e 8625 /****************************** SMBUS Instances *******************************/
<> 148:21d94c44109e 8626 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
<> 148:21d94c44109e 8627
<> 148:21d94c44109e 8628 /******************************** I2S Instances *******************************/
<> 148:21d94c44109e 8629 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
<> 148:21d94c44109e 8630 ((INSTANCE) == SPI3))
<> 148:21d94c44109e 8631 /****************************** IWDG Instances ********************************/
<> 148:21d94c44109e 8632 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
<> 148:21d94c44109e 8633
<> 148:21d94c44109e 8634 /****************************** OPAMP Instances *******************************/
<> 148:21d94c44109e 8635 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
<> 148:21d94c44109e 8636 ((INSTANCE) == OPAMP2))
<> 148:21d94c44109e 8637
<> 148:21d94c44109e 8638 #define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
<> 148:21d94c44109e 8639
<> 148:21d94c44109e 8640 /****************************** RTC Instances *********************************/
<> 148:21d94c44109e 8641 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
<> 148:21d94c44109e 8642
<> 148:21d94c44109e 8643 /******************************** SPI Instances *******************************/
<> 148:21d94c44109e 8644 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
<> 148:21d94c44109e 8645 ((INSTANCE) == SPI2) || \
<> 148:21d94c44109e 8646 ((INSTANCE) == SPI3))
<> 148:21d94c44109e 8647
<> 148:21d94c44109e 8648 /****************************** TIM Instances *********************************/
<> 148:21d94c44109e 8649 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 148:21d94c44109e 8650 ((INSTANCE) == TIM3) || \
<> 148:21d94c44109e 8651 ((INSTANCE) == TIM4) || \
<> 148:21d94c44109e 8652 ((INSTANCE) == TIM5) || \
<> 148:21d94c44109e 8653 ((INSTANCE) == TIM6) || \
<> 148:21d94c44109e 8654 ((INSTANCE) == TIM7) || \
<> 148:21d94c44109e 8655 ((INSTANCE) == TIM9) || \
<> 148:21d94c44109e 8656 ((INSTANCE) == TIM10) || \
<> 148:21d94c44109e 8657 ((INSTANCE) == TIM11))
<> 148:21d94c44109e 8658
<> 148:21d94c44109e 8659 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 148:21d94c44109e 8660 ((INSTANCE) == TIM3) || \
<> 148:21d94c44109e 8661 ((INSTANCE) == TIM4) || \
<> 148:21d94c44109e 8662 ((INSTANCE) == TIM5) || \
<> 148:21d94c44109e 8663 ((INSTANCE) == TIM9) || \
<> 148:21d94c44109e 8664 ((INSTANCE) == TIM10) || \
<> 148:21d94c44109e 8665 ((INSTANCE) == TIM11))
<> 148:21d94c44109e 8666
<> 148:21d94c44109e 8667 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 148:21d94c44109e 8668 ((INSTANCE) == TIM3) || \
<> 148:21d94c44109e 8669 ((INSTANCE) == TIM4) || \
<> 148:21d94c44109e 8670 ((INSTANCE) == TIM5) || \
<> 148:21d94c44109e 8671 ((INSTANCE) == TIM9))
<> 148:21d94c44109e 8672
<> 148:21d94c44109e 8673 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 148:21d94c44109e 8674 ((INSTANCE) == TIM3) || \
<> 148:21d94c44109e 8675 ((INSTANCE) == TIM4) || \
<> 148:21d94c44109e 8676 ((INSTANCE) == TIM5))
<> 148:21d94c44109e 8677
<> 148:21d94c44109e 8678 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 148:21d94c44109e 8679 ((INSTANCE) == TIM3) || \
<> 148:21d94c44109e 8680 ((INSTANCE) == TIM4) || \
<> 148:21d94c44109e 8681 ((INSTANCE) == TIM5))
<> 148:21d94c44109e 8682
<> 148:21d94c44109e 8683 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 148:21d94c44109e 8684 ((INSTANCE) == TIM3) || \
<> 148:21d94c44109e 8685 ((INSTANCE) == TIM4) || \
<> 148:21d94c44109e 8686 ((INSTANCE) == TIM5) || \
<> 148:21d94c44109e 8687 ((INSTANCE) == TIM9))
<> 148:21d94c44109e 8688
<> 148:21d94c44109e 8689 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 148:21d94c44109e 8690 ((INSTANCE) == TIM3) || \
<> 148:21d94c44109e 8691 ((INSTANCE) == TIM4) || \
<> 148:21d94c44109e 8692 ((INSTANCE) == TIM5) || \
<> 148:21d94c44109e 8693 ((INSTANCE) == TIM9) || \
<> 148:21d94c44109e 8694 ((INSTANCE) == TIM10) || \
<> 148:21d94c44109e 8695 ((INSTANCE) == TIM11))
<> 148:21d94c44109e 8696
<> 148:21d94c44109e 8697 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 148:21d94c44109e 8698 ((INSTANCE) == TIM3) || \
<> 148:21d94c44109e 8699 ((INSTANCE) == TIM4) || \
<> 148:21d94c44109e 8700 ((INSTANCE) == TIM5) || \
<> 148:21d94c44109e 8701 ((INSTANCE) == TIM9))
<> 148:21d94c44109e 8702
<> 148:21d94c44109e 8703 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 148:21d94c44109e 8704 ((INSTANCE) == TIM3) || \
<> 148:21d94c44109e 8705 ((INSTANCE) == TIM4) || \
<> 148:21d94c44109e 8706 ((INSTANCE) == TIM5) || \
<> 148:21d94c44109e 8707 ((INSTANCE) == TIM9))
<> 148:21d94c44109e 8708
<> 148:21d94c44109e 8709 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 148:21d94c44109e 8710 ((INSTANCE) == TIM3) || \
<> 148:21d94c44109e 8711 ((INSTANCE) == TIM4))
<> 148:21d94c44109e 8712
<> 148:21d94c44109e 8713 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 148:21d94c44109e 8714 ((INSTANCE) == TIM3) || \
<> 148:21d94c44109e 8715 ((INSTANCE) == TIM4) || \
<> 148:21d94c44109e 8716 ((INSTANCE) == TIM5))
<> 148:21d94c44109e 8717
<> 148:21d94c44109e 8718 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 148:21d94c44109e 8719 ((INSTANCE) == TIM3) || \
<> 148:21d94c44109e 8720 ((INSTANCE) == TIM4) || \
<> 148:21d94c44109e 8721 ((INSTANCE) == TIM5))
<> 148:21d94c44109e 8722
<> 148:21d94c44109e 8723
<> 148:21d94c44109e 8724 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 148:21d94c44109e 8725 ((INSTANCE) == TIM3) || \
<> 148:21d94c44109e 8726 ((INSTANCE) == TIM4) || \
<> 148:21d94c44109e 8727 ((INSTANCE) == TIM5) || \
<> 148:21d94c44109e 8728 ((INSTANCE) == TIM6) || \
<> 148:21d94c44109e 8729 ((INSTANCE) == TIM7) || \
<> 148:21d94c44109e 8730 ((INSTANCE) == TIM9))
<> 148:21d94c44109e 8731
<> 148:21d94c44109e 8732 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 148:21d94c44109e 8733 ((INSTANCE) == TIM3) || \
<> 148:21d94c44109e 8734 ((INSTANCE) == TIM4) || \
<> 148:21d94c44109e 8735 ((INSTANCE) == TIM5) || \
<> 148:21d94c44109e 8736 ((INSTANCE) == TIM9))
<> 148:21d94c44109e 8737
<> 148:21d94c44109e 8738 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5)
<> 148:21d94c44109e 8739
<> 148:21d94c44109e 8740 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 148:21d94c44109e 8741 ((INSTANCE) == TIM3) || \
<> 148:21d94c44109e 8742 ((INSTANCE) == TIM4) || \
<> 148:21d94c44109e 8743 ((INSTANCE) == TIM5))
<> 148:21d94c44109e 8744
<> 148:21d94c44109e 8745 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
<> 148:21d94c44109e 8746 ((((INSTANCE) == TIM2) && \
<> 148:21d94c44109e 8747 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 148:21d94c44109e 8748 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 148:21d94c44109e 8749 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 148:21d94c44109e 8750 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 148:21d94c44109e 8751 || \
<> 148:21d94c44109e 8752 (((INSTANCE) == TIM3) && \
<> 148:21d94c44109e 8753 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 148:21d94c44109e 8754 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 148:21d94c44109e 8755 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 148:21d94c44109e 8756 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 148:21d94c44109e 8757 || \
<> 148:21d94c44109e 8758 (((INSTANCE) == TIM4) && \
<> 148:21d94c44109e 8759 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 148:21d94c44109e 8760 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 148:21d94c44109e 8761 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 148:21d94c44109e 8762 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 148:21d94c44109e 8763 || \
<> 148:21d94c44109e 8764 (((INSTANCE) == TIM5) && \
<> 148:21d94c44109e 8765 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 148:21d94c44109e 8766 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 148:21d94c44109e 8767 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 148:21d94c44109e 8768 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 148:21d94c44109e 8769 || \
<> 148:21d94c44109e 8770 (((INSTANCE) == TIM9) && \
<> 148:21d94c44109e 8771 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 148:21d94c44109e 8772 ((CHANNEL) == TIM_CHANNEL_2))) \
<> 148:21d94c44109e 8773 || \
<> 148:21d94c44109e 8774 (((INSTANCE) == TIM10) && \
<> 148:21d94c44109e 8775 (((CHANNEL) == TIM_CHANNEL_1))) \
<> 148:21d94c44109e 8776 || \
<> 148:21d94c44109e 8777 (((INSTANCE) == TIM11) && \
<> 148:21d94c44109e 8778 (((CHANNEL) == TIM_CHANNEL_1))))
<> 148:21d94c44109e 8779
<> 148:21d94c44109e 8780 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 148:21d94c44109e 8781 ((INSTANCE) == TIM3) || \
<> 148:21d94c44109e 8782 ((INSTANCE) == TIM4) || \
<> 148:21d94c44109e 8783 ((INSTANCE) == TIM5) || \
<> 148:21d94c44109e 8784 ((INSTANCE) == TIM9) || \
<> 148:21d94c44109e 8785 ((INSTANCE) == TIM10) || \
<> 148:21d94c44109e 8786 ((INSTANCE) == TIM11))
<> 148:21d94c44109e 8787
<> 148:21d94c44109e 8788 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 148:21d94c44109e 8789 ((INSTANCE) == TIM3) || \
<> 148:21d94c44109e 8790 ((INSTANCE) == TIM4) || \
<> 148:21d94c44109e 8791 ((INSTANCE) == TIM5) || \
<> 148:21d94c44109e 8792 ((INSTANCE) == TIM6) || \
<> 148:21d94c44109e 8793 ((INSTANCE) == TIM7))
<> 148:21d94c44109e 8794
<> 148:21d94c44109e 8795 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 148:21d94c44109e 8796 ((INSTANCE) == TIM3) || \
<> 148:21d94c44109e 8797 ((INSTANCE) == TIM4) || \
<> 148:21d94c44109e 8798 ((INSTANCE) == TIM5))
<> 148:21d94c44109e 8799
<> 148:21d94c44109e 8800 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 148:21d94c44109e 8801 ((INSTANCE) == TIM3) || \
<> 148:21d94c44109e 8802 ((INSTANCE) == TIM4) || \
<> 148:21d94c44109e 8803 ((INSTANCE) == TIM5) || \
<> 148:21d94c44109e 8804 ((INSTANCE) == TIM9))
<> 148:21d94c44109e 8805
<> 148:21d94c44109e 8806 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 148:21d94c44109e 8807 ((INSTANCE) == TIM3) || \
<> 148:21d94c44109e 8808 ((INSTANCE) == TIM4) || \
<> 148:21d94c44109e 8809 ((INSTANCE) == TIM5) || \
<> 148:21d94c44109e 8810 ((INSTANCE) == TIM9))
<> 148:21d94c44109e 8811
<> 148:21d94c44109e 8812 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 148:21d94c44109e 8813 ((INSTANCE) == TIM3) || \
<> 148:21d94c44109e 8814 ((INSTANCE) == TIM9) || \
<> 148:21d94c44109e 8815 ((INSTANCE) == TIM10) || \
<> 148:21d94c44109e 8816 ((INSTANCE) == TIM11))
<> 148:21d94c44109e 8817
<> 148:21d94c44109e 8818 /******************** USART Instances : Synchronous mode **********************/
<> 148:21d94c44109e 8819 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 148:21d94c44109e 8820 ((INSTANCE) == USART2) || \
<> 148:21d94c44109e 8821 ((INSTANCE) == USART3))
<> 148:21d94c44109e 8822
<> 148:21d94c44109e 8823 /******************** UART Instances : Asynchronous mode **********************/
<> 148:21d94c44109e 8824 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 148:21d94c44109e 8825 ((INSTANCE) == USART2) || \
<> 148:21d94c44109e 8826 ((INSTANCE) == USART3))
<> 148:21d94c44109e 8827
<> 148:21d94c44109e 8828 /******************** UART Instances : Half-Duplex mode **********************/
<> 148:21d94c44109e 8829 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 148:21d94c44109e 8830 ((INSTANCE) == USART2) || \
<> 148:21d94c44109e 8831 ((INSTANCE) == USART3))
<> 148:21d94c44109e 8832
<> 148:21d94c44109e 8833 /******************** UART Instances : LIN mode **********************/
<> 148:21d94c44109e 8834 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 148:21d94c44109e 8835 ((INSTANCE) == USART2) || \
<> 148:21d94c44109e 8836 ((INSTANCE) == USART3))
<> 148:21d94c44109e 8837
<> 148:21d94c44109e 8838 /****************** UART Instances : Hardware Flow control ********************/
<> 148:21d94c44109e 8839 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 148:21d94c44109e 8840 ((INSTANCE) == USART2) || \
<> 148:21d94c44109e 8841 ((INSTANCE) == USART3))
<> 148:21d94c44109e 8842
<> 148:21d94c44109e 8843 /********************* UART Instances : Smard card mode ***********************/
<> 148:21d94c44109e 8844 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 148:21d94c44109e 8845 ((INSTANCE) == USART2) || \
<> 148:21d94c44109e 8846 ((INSTANCE) == USART3))
<> 148:21d94c44109e 8847
<> 148:21d94c44109e 8848 /*********************** UART Instances : IRDA mode ***************************/
<> 148:21d94c44109e 8849 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 148:21d94c44109e 8850 ((INSTANCE) == USART2) || \
<> 148:21d94c44109e 8851 ((INSTANCE) == USART3))
<> 148:21d94c44109e 8852
<> 148:21d94c44109e 8853 /***************** UART Instances : Multi-Processor mode **********************/
<> 148:21d94c44109e 8854 #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 148:21d94c44109e 8855 ((INSTANCE) == USART2) || \
<> 148:21d94c44109e 8856 ((INSTANCE) == USART3))
<> 148:21d94c44109e 8857
<> 148:21d94c44109e 8858 /****************************** WWDG Instances ********************************/
<> 148:21d94c44109e 8859 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
<> 148:21d94c44109e 8860
<> 148:21d94c44109e 8861 /****************************** USB Instances ********************************/
<> 148:21d94c44109e 8862 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
<> 148:21d94c44109e 8863
<> 148:21d94c44109e 8864 /**
<> 148:21d94c44109e 8865 * @}
<> 148:21d94c44109e 8866 */
<> 148:21d94c44109e 8867
<> 148:21d94c44109e 8868 /******************************************************************************/
<> 148:21d94c44109e 8869 /* For a painless codes migration between the STM32L1xx device product */
<> 148:21d94c44109e 8870 /* lines, the aliases defined below are put in place to overcome the */
<> 148:21d94c44109e 8871 /* differences in the interrupt handlers and IRQn definitions. */
<> 148:21d94c44109e 8872 /* No need to update developed interrupt code when moving across */
<> 148:21d94c44109e 8873 /* product lines within the same STM32L1 Family */
<> 148:21d94c44109e 8874 /******************************************************************************/
<> 148:21d94c44109e 8875
<> 148:21d94c44109e 8876 /* Aliases for __IRQn */
<> 148:21d94c44109e 8877
<> 148:21d94c44109e 8878 /* Aliases for __IRQHandler */
<> 148:21d94c44109e 8879
<> 148:21d94c44109e 8880 /**
<> 148:21d94c44109e 8881 * @}
<> 148:21d94c44109e 8882 */
<> 148:21d94c44109e 8883
<> 148:21d94c44109e 8884 /**
<> 148:21d94c44109e 8885 * @}
<> 148:21d94c44109e 8886 */
<> 148:21d94c44109e 8887
<> 148:21d94c44109e 8888 #ifdef __cplusplus
<> 148:21d94c44109e 8889 }
<> 148:21d94c44109e 8890 #endif /* __cplusplus */
<> 148:21d94c44109e 8891
<> 148:21d94c44109e 8892 #endif /* __STM32L151xC_H */
<> 148:21d94c44109e 8893
<> 148:21d94c44109e 8894
<> 148:21d94c44109e 8895
<> 148:21d94c44109e 8896 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/