mbed-dev - mbed library sources. Supersedes mbed-src.

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mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c.c@148:21d94c44109e, 2016-09-30 (annotated)

Committer:: <>
Date:: Fri Sep 30 18:07:01 2016 +0100
Revision:: 148:21d94c44109e
Parent:: 144:ef7eb2e8f9f7

This updates the lib to the mbed lib v127

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f4xx_hal_i2c.c
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @version V1.5.0
<>	144:ef7eb2e8f9f7	6	* @date 06-May-2016
<>	144:ef7eb2e8f9f7	7	* @brief I2C HAL module driver.
<>	144:ef7eb2e8f9f7	8	* This file provides firmware functions to manage the following
<>	144:ef7eb2e8f9f7	9	* functionalities of the Inter Integrated Circuit (I2C) peripheral:
<>	144:ef7eb2e8f9f7	10	* + Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	11	* + IO operation functions
<>	144:ef7eb2e8f9f7	12	* + Peripheral Control functions
<>	144:ef7eb2e8f9f7	13	* + Peripheral State functions
<>	144:ef7eb2e8f9f7	14	*
<>	144:ef7eb2e8f9f7	15	@verbatim
<>	144:ef7eb2e8f9f7	16	==============================================================================
<>	144:ef7eb2e8f9f7	17	##### How to use this driver #####
<>	144:ef7eb2e8f9f7	18	==============================================================================
<>	144:ef7eb2e8f9f7	19	[..]
<>	144:ef7eb2e8f9f7	20	The I2C HAL driver can be used as follows:
<>	144:ef7eb2e8f9f7	21
<>	144:ef7eb2e8f9f7	22	(#) Declare a I2C_HandleTypeDef handle structure, for example:
<>	144:ef7eb2e8f9f7	23	I2C_HandleTypeDef hi2c;
<>	144:ef7eb2e8f9f7	24
<>	144:ef7eb2e8f9f7	25	(#)Initialize the I2C low level resources by implement the HAL_I2C_MspInit() API:
<>	144:ef7eb2e8f9f7	26	(##) Enable the I2Cx interface clock
<>	144:ef7eb2e8f9f7	27	(##) I2C pins configuration
<>	144:ef7eb2e8f9f7	28	(+++) Enable the clock for the I2C GPIOs
<>	144:ef7eb2e8f9f7	29	(+++) Configure I2C pins as alternate function open-drain
<>	144:ef7eb2e8f9f7	30	(##) NVIC configuration if you need to use interrupt process
<>	144:ef7eb2e8f9f7	31	(+++) Configure the I2Cx interrupt priority
<>	144:ef7eb2e8f9f7	32	(+++) Enable the NVIC I2C IRQ Channel
<>	144:ef7eb2e8f9f7	33	(##) DMA Configuration if you need to use DMA process
<>	144:ef7eb2e8f9f7	34	(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
<>	144:ef7eb2e8f9f7	35	(+++) Enable the DMAx interface clock using
<>	144:ef7eb2e8f9f7	36	(+++) Configure the DMA handle parameters
<>	144:ef7eb2e8f9f7	37	(+++) Configure the DMA Tx or Rx Stream
<>	144:ef7eb2e8f9f7	38	(+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
<>	144:ef7eb2e8f9f7	39	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
<>	144:ef7eb2e8f9f7	40	the DMA Tx or Rx Stream
<>	144:ef7eb2e8f9f7	41
<>	144:ef7eb2e8f9f7	42	(#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1,
<>	144:ef7eb2e8f9f7	43	Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure.
<>	144:ef7eb2e8f9f7	44
<>	144:ef7eb2e8f9f7	45	(#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
<>	144:ef7eb2e8f9f7	46	(GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
<>	144:ef7eb2e8f9f7	47
<>	144:ef7eb2e8f9f7	48	(#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
<>	144:ef7eb2e8f9f7	49
<>	144:ef7eb2e8f9f7	50	(#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
<>	144:ef7eb2e8f9f7	51
<>	144:ef7eb2e8f9f7	52	* Polling mode IO operation *
<>	144:ef7eb2e8f9f7	53	=================================
<>	144:ef7eb2e8f9f7	54	[..]
<>	144:ef7eb2e8f9f7	55	(+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
<>	144:ef7eb2e8f9f7	56	(+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
<>	144:ef7eb2e8f9f7	57	(+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
<>	144:ef7eb2e8f9f7	58	(+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
<>	144:ef7eb2e8f9f7	59
<>	144:ef7eb2e8f9f7	60	* Polling mode IO MEM operation *
<>	144:ef7eb2e8f9f7	61	=====================================
<>	144:ef7eb2e8f9f7	62	[..]
<>	144:ef7eb2e8f9f7	63	(+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
<>	144:ef7eb2e8f9f7	64	(+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
<>	144:ef7eb2e8f9f7	65
<>	144:ef7eb2e8f9f7	66
<>	144:ef7eb2e8f9f7	67	* Interrupt mode IO operation *
<>	144:ef7eb2e8f9f7	68	===================================
<>	144:ef7eb2e8f9f7	69	[..]
<>	144:ef7eb2e8f9f7	70	(+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT()
<>	144:ef7eb2e8f9f7	71	(+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	72	add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
<>	144:ef7eb2e8f9f7	73	(+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT()
<>	144:ef7eb2e8f9f7	74	(+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	75	add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
<>	144:ef7eb2e8f9f7	76	(+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT()
<>	144:ef7eb2e8f9f7	77	(+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	78	add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
<>	144:ef7eb2e8f9f7	79	(+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT()
<>	144:ef7eb2e8f9f7	80	(+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	81	add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
<>	144:ef7eb2e8f9f7	82	(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
<>	144:ef7eb2e8f9f7	83	add his own code by customization of function pointer HAL_I2C_ErrorCallback
<>	144:ef7eb2e8f9f7	84
<>	144:ef7eb2e8f9f7	85	* Interrupt mode IO sequential operation *
<>	144:ef7eb2e8f9f7	86	==============================================
<>	144:ef7eb2e8f9f7	87	[..]
<>	144:ef7eb2e8f9f7	88	(+@) These interfaces allow to manage a sequential transfer with a repeated start condition
<>	144:ef7eb2e8f9f7	89	when a direction change during transfer
<>	144:ef7eb2e8f9f7	90	(+) A specific option manage the different steps of a sequential transfer
<>	144:ef7eb2e8f9f7	91	(+) Differents steps option I2C_XferOptions_definition are listed below :
<>	144:ef7eb2e8f9f7	92	(++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
<>	144:ef7eb2e8f9f7	93	(++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a start condition with data to transfer without a final stop condition
<>	144:ef7eb2e8f9f7	94	(++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a restart condition with new data to transfer if the direction change or
<>	144:ef7eb2e8f9f7	95	manage only the new data to transfer if no direction change and without a final stop condition in both cases
<>	144:ef7eb2e8f9f7	96	(++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a restart condition with new data to transfer if the direction change or
<>	144:ef7eb2e8f9f7	97	manage only the new data to transfer if no direction change and with a final stop condition in both cases
<>	144:ef7eb2e8f9f7	98
<>	144:ef7eb2e8f9f7	99	(+) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
<>	144:ef7eb2e8f9f7	100	(++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	101	add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
<>	144:ef7eb2e8f9f7	102	(+) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
<>	144:ef7eb2e8f9f7	103	(++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	104	add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
<>	144:ef7eb2e8f9f7	105	(+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
<>	144:ef7eb2e8f9f7	106	(++) The associated previous transfer callback is called at the end of abort process
<>	144:ef7eb2e8f9f7	107	(++) mean HAL_I2C_MasterTxCpltCallback() in case of previous state was master transmit
<>	144:ef7eb2e8f9f7	108	(++) mean HAL_I2c_MasterRxCpltCallback() in case of previous state was master receive
<>	144:ef7eb2e8f9f7	109	(+) Enable/disable the Address listen mode in slave I2C mode
<>	144:ef7eb2e8f9f7	110	using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
<>	144:ef7eb2e8f9f7	111	(++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
<>	144:ef7eb2e8f9f7	112	add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
<>	144:ef7eb2e8f9f7	113	(++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	114	add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
<>	144:ef7eb2e8f9f7	115	(+) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
<>	144:ef7eb2e8f9f7	116	(++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	117	add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
<>	144:ef7eb2e8f9f7	118	(+) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
<>	144:ef7eb2e8f9f7	119	(++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	120	add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
<>	144:ef7eb2e8f9f7	121
<>	144:ef7eb2e8f9f7	122
<>	144:ef7eb2e8f9f7	123	* Interrupt mode IO MEM operation *
<>	144:ef7eb2e8f9f7	124	=======================================
<>	144:ef7eb2e8f9f7	125	[..]
<>	144:ef7eb2e8f9f7	126	(+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using
<>	144:ef7eb2e8f9f7	127	HAL_I2C_Mem_Write_IT()
<>	144:ef7eb2e8f9f7	128	(+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	129	add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
<>	144:ef7eb2e8f9f7	130	(+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using
<>	144:ef7eb2e8f9f7	131	HAL_I2C_Mem_Read_IT()
<>	144:ef7eb2e8f9f7	132	(+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	133	add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
<>	144:ef7eb2e8f9f7	134	(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
<>	144:ef7eb2e8f9f7	135	add his own code by customization of function pointer HAL_I2C_ErrorCallback
<>	144:ef7eb2e8f9f7	136
<>	144:ef7eb2e8f9f7	137	* DMA mode IO operation *
<>	144:ef7eb2e8f9f7	138	==============================
<>	144:ef7eb2e8f9f7	139	[..]
<>	144:ef7eb2e8f9f7	140	(+) Transmit in master mode an amount of data in non blocking mode (DMA) using
<>	144:ef7eb2e8f9f7	141	HAL_I2C_Master_Transmit_DMA()
<>	144:ef7eb2e8f9f7	142	(+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	143	add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
<>	144:ef7eb2e8f9f7	144	(+) Receive in master mode an amount of data in non blocking mode (DMA) using
<>	144:ef7eb2e8f9f7	145	HAL_I2C_Master_Receive_DMA()
<>	144:ef7eb2e8f9f7	146	(+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	147	add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
<>	144:ef7eb2e8f9f7	148	(+) Transmit in slave mode an amount of data in non blocking mode (DMA) using
<>	144:ef7eb2e8f9f7	149	HAL_I2C_Slave_Transmit_DMA()
<>	144:ef7eb2e8f9f7	150	(+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	151	add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
<>	144:ef7eb2e8f9f7	152	(+) Receive in slave mode an amount of data in non blocking mode (DMA) using
<>	144:ef7eb2e8f9f7	153	HAL_I2C_Slave_Receive_DMA()
<>	144:ef7eb2e8f9f7	154	(+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	155	add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
<>	144:ef7eb2e8f9f7	156	(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
<>	144:ef7eb2e8f9f7	157	add his own code by customization of function pointer HAL_I2C_ErrorCallback
<>	144:ef7eb2e8f9f7	158
<>	144:ef7eb2e8f9f7	159	* DMA mode IO MEM operation *
<>	144:ef7eb2e8f9f7	160	=================================
<>	144:ef7eb2e8f9f7	161	[..]
<>	144:ef7eb2e8f9f7	162	(+) Write an amount of data in no-blocking mode with DMA to a specific memory address using
<>	144:ef7eb2e8f9f7	163	HAL_I2C_Mem_Write_DMA()
<>	144:ef7eb2e8f9f7	164	(+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	165	add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
<>	144:ef7eb2e8f9f7	166	(+) Read an amount of data in no-blocking mode with DMA from a specific memory address using
<>	144:ef7eb2e8f9f7	167	HAL_I2C_Mem_Read_DMA()
<>	144:ef7eb2e8f9f7	168	(+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	169	add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
<>	144:ef7eb2e8f9f7	170	(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
<>	144:ef7eb2e8f9f7	171	add his own code by customization of function pointer HAL_I2C_ErrorCallback
<>	144:ef7eb2e8f9f7	172
<>	144:ef7eb2e8f9f7	173
<>	144:ef7eb2e8f9f7	174	* I2C HAL driver macros list *
<>	144:ef7eb2e8f9f7	175	==================================
<>	144:ef7eb2e8f9f7	176	[..]
<>	144:ef7eb2e8f9f7	177	Below the list of most used macros in I2C HAL driver.
<>	144:ef7eb2e8f9f7	178
<>	144:ef7eb2e8f9f7	179	(+) __HAL_I2C_ENABLE: Enable the I2C peripheral
<>	144:ef7eb2e8f9f7	180	(+) __HAL_I2C_DISABLE: Disable the I2C peripheral
<>	144:ef7eb2e8f9f7	181	(+) __HAL_I2C_GET_FLAG: Checks whether the specified I2C flag is set or not
<>	144:ef7eb2e8f9f7	182	(+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
<>	144:ef7eb2e8f9f7	183	(+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
<>	144:ef7eb2e8f9f7	184	(+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
<>	144:ef7eb2e8f9f7	185
<>	144:ef7eb2e8f9f7	186	[..]
<>	144:ef7eb2e8f9f7	187	(@) You can refer to the I2C HAL driver header file for more useful macros
<>	144:ef7eb2e8f9f7	188
<>	144:ef7eb2e8f9f7	189
<>	144:ef7eb2e8f9f7	190	@endverbatim
<>	144:ef7eb2e8f9f7	191	******************************************************************************
<>	144:ef7eb2e8f9f7	192	* @attention
<>	144:ef7eb2e8f9f7	193	*
<>	144:ef7eb2e8f9f7	194	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	195	*
<>	144:ef7eb2e8f9f7	196	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	197	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	198	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	199	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	200	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	201	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	202	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	203	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	204	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	205	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	206	*
<>	144:ef7eb2e8f9f7	207	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	208	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	209	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	210	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	211	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	212	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	213	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	214	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	215	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	216	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	217	*
<>	144:ef7eb2e8f9f7	218	******************************************************************************
<>	144:ef7eb2e8f9f7	219	*/
<>	144:ef7eb2e8f9f7	220
<>	144:ef7eb2e8f9f7	221	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	222	#include "stm32f4xx_hal.h"
<>	144:ef7eb2e8f9f7	223
<>	144:ef7eb2e8f9f7	224	/** @addtogroup STM32F4xx_HAL_Driver
<>	144:ef7eb2e8f9f7	225	* @{
<>	144:ef7eb2e8f9f7	226	*/
<>	144:ef7eb2e8f9f7	227
<>	144:ef7eb2e8f9f7	228	/** @defgroup I2C I2C
<>	144:ef7eb2e8f9f7	229	* @brief I2C HAL module driver
<>	144:ef7eb2e8f9f7	230	* @{
<>	144:ef7eb2e8f9f7	231	*/
<>	144:ef7eb2e8f9f7	232
<>	144:ef7eb2e8f9f7	233	#ifdef HAL_I2C_MODULE_ENABLED
<>	144:ef7eb2e8f9f7	234
<>	144:ef7eb2e8f9f7	235	/* Private typedef -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	236	/* Private define ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	237	/** @addtogroup I2C_Private_Constants
<>	144:ef7eb2e8f9f7	238	* @{
<>	144:ef7eb2e8f9f7	239	*/
<>	144:ef7eb2e8f9f7	240	#define I2C_TIMEOUT_FLAG ((uint32_t)35U) /!< Timeout 35 ms /
<>	144:ef7eb2e8f9f7	241	#define I2C_TIMEOUT_ADDR_SLAVE ((uint32_t)10000U) /!< Timeout 10 s /
<>	144:ef7eb2e8f9f7	242	#define I2C_TIMEOUT_BUSY_FLAG ((uint32_t)25U) /!< Timeout 25 ms /
<>	144:ef7eb2e8f9f7	243	#define I2C_NO_OPTION_FRAME ((uint32_t)0xFFFF0000U) /!< XferOptions default value /
<>	144:ef7eb2e8f9f7	244
<>	144:ef7eb2e8f9f7	245	/* Private define for @ref PreviousState usage */
<>	144:ef7eb2e8f9f7	246	#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX \| HAL_I2C_STATE_BUSY_RX) & (~(uint32_t)HAL_I2C_STATE_READY))) /!< Mask State define, keep only RX and TX bits /
<>	144:ef7eb2e8f9f7	247	#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /!< Default Value /
<>	144:ef7eb2e8f9f7	248	#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) \| HAL_I2C_MODE_MASTER)) /!< Master Busy TX, combinaison of State LSB and Mode enum /
<>	144:ef7eb2e8f9f7	249	#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) \| HAL_I2C_MODE_MASTER)) /!< Master Busy RX, combinaison of State LSB and Mode enum /
<>	144:ef7eb2e8f9f7	250	#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) \| HAL_I2C_MODE_SLAVE)) /!< Slave Busy TX, combinaison of State LSB and Mode enum /
<>	144:ef7eb2e8f9f7	251	#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) \| HAL_I2C_MODE_SLAVE)) /!< Slave Busy RX, combinaison of State LSB and Mode enum /
<>	144:ef7eb2e8f9f7	252
<>	144:ef7eb2e8f9f7	253	/**
<>	144:ef7eb2e8f9f7	254	* @}
<>	144:ef7eb2e8f9f7	255	*/
<>	144:ef7eb2e8f9f7	256
<>	144:ef7eb2e8f9f7	257	/* Private macro -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	258	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	259	/* Private function prototypes -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	260	/** @addtogroup I2C_Private_Functions
<>	144:ef7eb2e8f9f7	261	* @{
<>	144:ef7eb2e8f9f7	262	*/
<>	144:ef7eb2e8f9f7	263	/* Private functions to handle DMA transfer */
<>	144:ef7eb2e8f9f7	264	static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	265	static void I2C_DMAError(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	266	static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	267
<>	144:ef7eb2e8f9f7	268	static void I2C_ITError(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	269
<>	144:ef7eb2e8f9f7	270	static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	271	static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	272	static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	273	static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	274	static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	275	static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	276	static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	277	static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	278	static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	279	static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	280	static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	281
<>	144:ef7eb2e8f9f7	282	/* Private functions for I2C transfer IRQ handler */
<>	144:ef7eb2e8f9f7	283	static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	284	static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	285	static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	286	static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	287	static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	288	static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	289	static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	290
<>	144:ef7eb2e8f9f7	291	static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	292	static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	293	static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	294	static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	295	static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	296	static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	297	static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	298	/**
<>	144:ef7eb2e8f9f7	299	* @}
<>	144:ef7eb2e8f9f7	300	*/
<>	144:ef7eb2e8f9f7	301
<>	144:ef7eb2e8f9f7	302	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	303	/** @defgroup I2C_Exported_Functions I2C Exported Functions
<>	144:ef7eb2e8f9f7	304	* @{
<>	144:ef7eb2e8f9f7	305	*/
<>	144:ef7eb2e8f9f7	306
<>	144:ef7eb2e8f9f7	307	/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	308	* @brief Initialization and Configuration functions
<>	144:ef7eb2e8f9f7	309	*
<>	144:ef7eb2e8f9f7	310	@verbatim
<>	144:ef7eb2e8f9f7	311	===============================================================================
<>	144:ef7eb2e8f9f7	312	##### Initialization and de-initialization functions #####
<>	144:ef7eb2e8f9f7	313	===============================================================================
<>	144:ef7eb2e8f9f7	314	[..] This subsection provides a set of functions allowing to initialize and
<>	144:ef7eb2e8f9f7	315	de-initialize the I2Cx peripheral:
<>	144:ef7eb2e8f9f7	316
<>	144:ef7eb2e8f9f7	317	(+) User must Implement HAL_I2C_MspInit() function in which he configures
<>	144:ef7eb2e8f9f7	318	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC).
<>	144:ef7eb2e8f9f7	319
<>	144:ef7eb2e8f9f7	320	(+) Call the function HAL_I2C_Init() to configure the selected device with
<>	144:ef7eb2e8f9f7	321	the selected configuration:
<>	144:ef7eb2e8f9f7	322	(++) Communication Speed
<>	144:ef7eb2e8f9f7	323	(++) Duty cycle
<>	144:ef7eb2e8f9f7	324	(++) Addressing mode
<>	144:ef7eb2e8f9f7	325	(++) Own Address 1
<>	144:ef7eb2e8f9f7	326	(++) Dual Addressing mode
<>	144:ef7eb2e8f9f7	327	(++) Own Address 2
<>	144:ef7eb2e8f9f7	328	(++) General call mode
<>	144:ef7eb2e8f9f7	329	(++) Nostretch mode
<>	144:ef7eb2e8f9f7	330
<>	144:ef7eb2e8f9f7	331	(+) Call the function HAL_I2C_DeInit() to restore the default configuration
<>	144:ef7eb2e8f9f7	332	of the selected I2Cx peripheral.
<>	144:ef7eb2e8f9f7	333
<>	144:ef7eb2e8f9f7	334	@endverbatim
<>	144:ef7eb2e8f9f7	335	* @{
<>	144:ef7eb2e8f9f7	336	*/
<>	144:ef7eb2e8f9f7	337
<>	144:ef7eb2e8f9f7	338	/**
<>	144:ef7eb2e8f9f7	339	* @brief Initializes the I2C according to the specified parameters
<>	144:ef7eb2e8f9f7	340	* in the I2C_InitTypeDef and create the associated handle.
<>	144:ef7eb2e8f9f7	341	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	342	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	343	* @retval HAL status
<>	144:ef7eb2e8f9f7	344	*/
<>	144:ef7eb2e8f9f7	345	HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	346	{
<>	144:ef7eb2e8f9f7	347	uint32_t freqrange = 0U;
<>	144:ef7eb2e8f9f7	348	uint32_t pclk1 = 0U;
<>	144:ef7eb2e8f9f7	349
<>	144:ef7eb2e8f9f7	350	/* Check the I2C handle allocation */
<>	144:ef7eb2e8f9f7	351	if(hi2c == NULL)
<>	144:ef7eb2e8f9f7	352	{
<>	144:ef7eb2e8f9f7	353	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	354	}
<>	144:ef7eb2e8f9f7	355
<>	144:ef7eb2e8f9f7	356	/* Check the parameters */
<>	144:ef7eb2e8f9f7	357	assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
<>	144:ef7eb2e8f9f7	358	assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed));
<>	144:ef7eb2e8f9f7	359	assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle));
<>	144:ef7eb2e8f9f7	360	assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
<>	144:ef7eb2e8f9f7	361	assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
<>	144:ef7eb2e8f9f7	362	assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
<>	144:ef7eb2e8f9f7	363	assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
<>	144:ef7eb2e8f9f7	364	assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
<>	144:ef7eb2e8f9f7	365	assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
<>	144:ef7eb2e8f9f7	366
<>	144:ef7eb2e8f9f7	367	if(hi2c->State == HAL_I2C_STATE_RESET)
<>	144:ef7eb2e8f9f7	368	{
<>	144:ef7eb2e8f9f7	369	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	370	hi2c->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	371	/* Init the low level hardware : GPIO, CLOCK, NVIC */
<>	144:ef7eb2e8f9f7	372	HAL_I2C_MspInit(hi2c);
<>	144:ef7eb2e8f9f7	373	}
<>	144:ef7eb2e8f9f7	374
<>	144:ef7eb2e8f9f7	375	hi2c->State = HAL_I2C_STATE_BUSY;
<>	144:ef7eb2e8f9f7	376
<>	144:ef7eb2e8f9f7	377	/* Disable the selected I2C peripheral */
<>	144:ef7eb2e8f9f7	378	__HAL_I2C_DISABLE(hi2c);
<>	144:ef7eb2e8f9f7	379
<>	144:ef7eb2e8f9f7	380	/* Get PCLK1 frequency */
<>	144:ef7eb2e8f9f7	381	pclk1 = HAL_RCC_GetPCLK1Freq();
<>	144:ef7eb2e8f9f7	382
<>	144:ef7eb2e8f9f7	383	/* Calculate frequency range */
<>	144:ef7eb2e8f9f7	384	freqrange = I2C_FREQRANGE(pclk1);
<>	144:ef7eb2e8f9f7	385
<>	144:ef7eb2e8f9f7	386	/---------------------------- I2Cx CR2 Configuration ----------------------/
<>	144:ef7eb2e8f9f7	387	/* Configure I2Cx: Frequency range */
<>	144:ef7eb2e8f9f7	388	hi2c->Instance->CR2 = freqrange;
<>	144:ef7eb2e8f9f7	389
<>	144:ef7eb2e8f9f7	390	/---------------------------- I2Cx TRISE Configuration --------------------/
<>	144:ef7eb2e8f9f7	391	/* Configure I2Cx: Rise Time */
<>	144:ef7eb2e8f9f7	392	hi2c->Instance->TRISE = I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed);
<>	144:ef7eb2e8f9f7	393
<>	144:ef7eb2e8f9f7	394	/---------------------------- I2Cx CCR Configuration ----------------------/
<>	144:ef7eb2e8f9f7	395	/* Configure I2Cx: Speed */
<>	144:ef7eb2e8f9f7	396	hi2c->Instance->CCR = I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle);
<>	144:ef7eb2e8f9f7	397
<>	144:ef7eb2e8f9f7	398	/---------------------------- I2Cx CR1 Configuration ----------------------/
<>	144:ef7eb2e8f9f7	399	/* Configure I2Cx: Generalcall and NoStretch mode */
<>	144:ef7eb2e8f9f7	400	hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode \| hi2c->Init.NoStretchMode);
<>	144:ef7eb2e8f9f7	401
<>	144:ef7eb2e8f9f7	402	/---------------------------- I2Cx OAR1 Configuration ---------------------/
<>	144:ef7eb2e8f9f7	403	/* Configure I2Cx: Own Address1 and addressing mode */
<>	144:ef7eb2e8f9f7	404	hi2c->Instance->OAR1 = (hi2c->Init.AddressingMode \| hi2c->Init.OwnAddress1);
<>	144:ef7eb2e8f9f7	405
<>	144:ef7eb2e8f9f7	406	/---------------------------- I2Cx OAR2 Configuration ---------------------/
<>	144:ef7eb2e8f9f7	407	/* Configure I2Cx: Dual mode and Own Address2 */
<>	144:ef7eb2e8f9f7	408	hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode \| hi2c->Init.OwnAddress2);
<>	144:ef7eb2e8f9f7	409
<>	144:ef7eb2e8f9f7	410	/* Enable the selected I2C peripheral */
<>	144:ef7eb2e8f9f7	411	__HAL_I2C_ENABLE(hi2c);
<>	144:ef7eb2e8f9f7	412
<>	144:ef7eb2e8f9f7	413	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	414	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	415	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	416	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	417
<>	144:ef7eb2e8f9f7	418	return HAL_OK;
<>	144:ef7eb2e8f9f7	419	}
<>	144:ef7eb2e8f9f7	420
<>	144:ef7eb2e8f9f7	421	/**
<>	144:ef7eb2e8f9f7	422	* @brief DeInitializes the I2C peripheral.
<>	144:ef7eb2e8f9f7	423	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	424	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	425	* @retval HAL status
<>	144:ef7eb2e8f9f7	426	*/
<>	144:ef7eb2e8f9f7	427	HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	428	{
<>	144:ef7eb2e8f9f7	429	/* Check the I2C handle allocation */
<>	144:ef7eb2e8f9f7	430	if(hi2c == NULL)
<>	144:ef7eb2e8f9f7	431	{
<>	144:ef7eb2e8f9f7	432	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	433	}
<>	144:ef7eb2e8f9f7	434
<>	144:ef7eb2e8f9f7	435	/* Check the parameters */
<>	144:ef7eb2e8f9f7	436	assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
<>	144:ef7eb2e8f9f7	437
<>	144:ef7eb2e8f9f7	438	hi2c->State = HAL_I2C_STATE_BUSY;
<>	144:ef7eb2e8f9f7	439
<>	144:ef7eb2e8f9f7	440	/* Disable the I2C Peripheral Clock */
<>	144:ef7eb2e8f9f7	441	__HAL_I2C_DISABLE(hi2c);
<>	144:ef7eb2e8f9f7	442
<>	144:ef7eb2e8f9f7	443	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<>	144:ef7eb2e8f9f7	444	HAL_I2C_MspDeInit(hi2c);
<>	144:ef7eb2e8f9f7	445
<>	144:ef7eb2e8f9f7	446	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	447	hi2c->State = HAL_I2C_STATE_RESET;
<>	144:ef7eb2e8f9f7	448	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	449	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	450
<>	144:ef7eb2e8f9f7	451	/* Release Lock */
<>	144:ef7eb2e8f9f7	452	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	453
<>	144:ef7eb2e8f9f7	454	return HAL_OK;
<>	144:ef7eb2e8f9f7	455	}
<>	144:ef7eb2e8f9f7	456
<>	144:ef7eb2e8f9f7	457	/**
<>	144:ef7eb2e8f9f7	458	* @brief I2C MSP Init.
<>	144:ef7eb2e8f9f7	459	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	460	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	461	* @retval None
<>	144:ef7eb2e8f9f7	462	*/
<>	144:ef7eb2e8f9f7	463	__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	464	{
<>	144:ef7eb2e8f9f7	465	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	466	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	467	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	468	the HAL_I2C_MspInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	469	*/
<>	144:ef7eb2e8f9f7	470	}
<>	144:ef7eb2e8f9f7	471
<>	144:ef7eb2e8f9f7	472	/**
<>	144:ef7eb2e8f9f7	473	* @brief I2C MSP DeInit
<>	144:ef7eb2e8f9f7	474	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	475	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	476	* @retval None
<>	144:ef7eb2e8f9f7	477	*/
<>	144:ef7eb2e8f9f7	478	__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	479	{
<>	144:ef7eb2e8f9f7	480	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	481	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	482	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	483	the HAL_I2C_MspDeInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	484	*/
<>	144:ef7eb2e8f9f7	485	}
<>	144:ef7eb2e8f9f7	486
<>	144:ef7eb2e8f9f7	487	/**
<>	144:ef7eb2e8f9f7	488	* @}
<>	144:ef7eb2e8f9f7	489	*/
<>	144:ef7eb2e8f9f7	490
<>	144:ef7eb2e8f9f7	491	/** @defgroup I2C_Exported_Functions_Group2 IO operation functions
<>	144:ef7eb2e8f9f7	492	* @brief Data transfers functions
<>	144:ef7eb2e8f9f7	493	*
<>	144:ef7eb2e8f9f7	494	@verbatim
<>	144:ef7eb2e8f9f7	495	===============================================================================
<>	144:ef7eb2e8f9f7	496	##### IO operation functions #####
<>	144:ef7eb2e8f9f7	497	===============================================================================
<>	144:ef7eb2e8f9f7	498	[..]
<>	144:ef7eb2e8f9f7	499	This subsection provides a set of functions allowing to manage the I2C data
<>	144:ef7eb2e8f9f7	500	transfers.
<>	144:ef7eb2e8f9f7	501
<>	144:ef7eb2e8f9f7	502	(#) There are two modes of transfer:
<>	144:ef7eb2e8f9f7	503	(++) Blocking mode : The communication is performed in the polling mode.
<>	144:ef7eb2e8f9f7	504	The status of all data processing is returned by the same function
<>	144:ef7eb2e8f9f7	505	after finishing transfer.
<>	144:ef7eb2e8f9f7	506	(++) No-Blocking mode : The communication is performed using Interrupts
<>	144:ef7eb2e8f9f7	507	or DMA. These functions return the status of the transfer startup.
<>	144:ef7eb2e8f9f7	508	The end of the data processing will be indicated through the
<>	144:ef7eb2e8f9f7	509	dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
<>	144:ef7eb2e8f9f7	510	using DMA mode.
<>	144:ef7eb2e8f9f7	511
<>	144:ef7eb2e8f9f7	512	(#) Blocking mode functions are :
<>	144:ef7eb2e8f9f7	513	(++) HAL_I2C_Master_Transmit()
<>	144:ef7eb2e8f9f7	514	(++) HAL_I2C_Master_Receive()
<>	144:ef7eb2e8f9f7	515	(++) HAL_I2C_Slave_Transmit()
<>	144:ef7eb2e8f9f7	516	(++) HAL_I2C_Slave_Receive()
<>	144:ef7eb2e8f9f7	517	(++) HAL_I2C_Mem_Write()
<>	144:ef7eb2e8f9f7	518	(++) HAL_I2C_Mem_Read()
<>	144:ef7eb2e8f9f7	519	(++) HAL_I2C_IsDeviceReady()
<>	144:ef7eb2e8f9f7	520
<>	144:ef7eb2e8f9f7	521	(#) No-Blocking mode functions with Interrupt are :
<>	144:ef7eb2e8f9f7	522	(++) HAL_I2C_Master_Transmit_IT()
<>	144:ef7eb2e8f9f7	523	(++) HAL_I2C_Master_Receive_IT()
<>	144:ef7eb2e8f9f7	524	(++) HAL_I2C_Slave_Transmit_IT()
<>	144:ef7eb2e8f9f7	525	(++) HAL_I2C_Slave_Receive_IT()
<>	144:ef7eb2e8f9f7	526	(++) HAL_I2C_Master_Sequential_Transmit_IT()
<>	144:ef7eb2e8f9f7	527	(++) HAL_I2C_Master_Sequential_Receive_IT()
<>	144:ef7eb2e8f9f7	528	(++) HAL_I2C_Slave_Sequential_Transmit_IT()
<>	144:ef7eb2e8f9f7	529	(++) HAL_I2C_Slave_Sequential_Receive_IT()
<>	144:ef7eb2e8f9f7	530	(++) HAL_I2C_Mem_Write_IT()
<>	144:ef7eb2e8f9f7	531	(++) HAL_I2C_Mem_Read_IT()
<>	144:ef7eb2e8f9f7	532
<>	144:ef7eb2e8f9f7	533	(#) No-Blocking mode functions with DMA are :
<>	144:ef7eb2e8f9f7	534	(++) HAL_I2C_Master_Transmit_DMA()
<>	144:ef7eb2e8f9f7	535	(++) HAL_I2C_Master_Receive_DMA()
<>	144:ef7eb2e8f9f7	536	(++) HAL_I2C_Slave_Transmit_DMA()
<>	144:ef7eb2e8f9f7	537	(++) HAL_I2C_Slave_Receive_DMA()
<>	144:ef7eb2e8f9f7	538	(++) HAL_I2C_Mem_Write_DMA()
<>	144:ef7eb2e8f9f7	539	(++) HAL_I2C_Mem_Read_DMA()
<>	144:ef7eb2e8f9f7	540
<>	144:ef7eb2e8f9f7	541	(#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
<>	144:ef7eb2e8f9f7	542	(++) HAL_I2C_MemTxCpltCallback()
<>	144:ef7eb2e8f9f7	543	(++) HAL_I2C_MemRxCpltCallback()
<>	144:ef7eb2e8f9f7	544	(++) HAL_I2C_MasterTxCpltCallback()
<>	144:ef7eb2e8f9f7	545	(++) HAL_I2C_MasterRxCpltCallback()
<>	144:ef7eb2e8f9f7	546	(++) HAL_I2C_SlaveTxCpltCallback()
<>	144:ef7eb2e8f9f7	547	(++) HAL_I2C_SlaveRxCpltCallback()
<>	144:ef7eb2e8f9f7	548	(++) HAL_I2C_ErrorCallback()
<>	144:ef7eb2e8f9f7	549	(++) HAL_I2C_AbortCpltCallback()
<>	144:ef7eb2e8f9f7	550
<>	144:ef7eb2e8f9f7	551	@endverbatim
<>	144:ef7eb2e8f9f7	552	* @{
<>	144:ef7eb2e8f9f7	553	*/
<>	144:ef7eb2e8f9f7	554
<>	144:ef7eb2e8f9f7	555	/**
<>	144:ef7eb2e8f9f7	556	* @brief Transmits in master mode an amount of data in blocking mode.
<>	144:ef7eb2e8f9f7	557	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	558	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	559	* @param DevAddress Target device address: The device 7 bits address value
<>	144:ef7eb2e8f9f7	560	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	561	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	562	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	563	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	564	* @retval HAL status
<>	144:ef7eb2e8f9f7	565	*/
<>	144:ef7eb2e8f9f7	566	HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	567	{
<>	144:ef7eb2e8f9f7	568	uint32_t tickstart = 0x00U;
<>	144:ef7eb2e8f9f7	569
<>	144:ef7eb2e8f9f7	570	/* Init tickstart for timeout management*/
<>	144:ef7eb2e8f9f7	571	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	572
<>	144:ef7eb2e8f9f7	573	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	574	{
<>	144:ef7eb2e8f9f7	575	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	576	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	577	{
<>	144:ef7eb2e8f9f7	578	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	579	}
<>	144:ef7eb2e8f9f7	580
<>	144:ef7eb2e8f9f7	581	/* Process Locked */
<>	144:ef7eb2e8f9f7	582	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	583
<>	144:ef7eb2e8f9f7	584	/* Disable Pos */
<>	144:ef7eb2e8f9f7	585	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	586
<>	144:ef7eb2e8f9f7	587	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	588	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	144:ef7eb2e8f9f7	589	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	590	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	591
<>	144:ef7eb2e8f9f7	592	/* Send Slave Address */
<>	144:ef7eb2e8f9f7	593	if(I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	594	{
<>	144:ef7eb2e8f9f7	595	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	596	{
<>	144:ef7eb2e8f9f7	597	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	598	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	599	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	600	}
<>	144:ef7eb2e8f9f7	601	else
<>	144:ef7eb2e8f9f7	602	{
<>	144:ef7eb2e8f9f7	603	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	604	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	605	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	606	}
<>	144:ef7eb2e8f9f7	607	}
<>	144:ef7eb2e8f9f7	608
<>	144:ef7eb2e8f9f7	609	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	610	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	611
<>	144:ef7eb2e8f9f7	612	while(Size > 0U)
<>	144:ef7eb2e8f9f7	613	{
<>	144:ef7eb2e8f9f7	614	/* Wait until TXE flag is set */
<>	144:ef7eb2e8f9f7	615	if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	616	{
<>	144:ef7eb2e8f9f7	617	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	618	{
<>	144:ef7eb2e8f9f7	619	/* Generate Stop */
<>	144:ef7eb2e8f9f7	620	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	621	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	622	}
<>	144:ef7eb2e8f9f7	623	else
<>	144:ef7eb2e8f9f7	624	{
<>	144:ef7eb2e8f9f7	625	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	626	}
<>	144:ef7eb2e8f9f7	627	}
<>	144:ef7eb2e8f9f7	628
<>	144:ef7eb2e8f9f7	629	/* Write data to DR */
<>	144:ef7eb2e8f9f7	630	hi2c->Instance->DR = (*pData++);
<>	144:ef7eb2e8f9f7	631	Size--;
<>	144:ef7eb2e8f9f7	632
<>	144:ef7eb2e8f9f7	633	if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U))
<>	144:ef7eb2e8f9f7	634	{
<>	144:ef7eb2e8f9f7	635	/* Write data to DR */
<>	144:ef7eb2e8f9f7	636	hi2c->Instance->DR = (*pData++);
<>	144:ef7eb2e8f9f7	637	Size--;
<>	144:ef7eb2e8f9f7	638	}
<>	144:ef7eb2e8f9f7	639
<>	144:ef7eb2e8f9f7	640	/* Wait until BTF flag is set */
<>	144:ef7eb2e8f9f7	641	if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	642	{
<>	144:ef7eb2e8f9f7	643	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	644	{
<>	144:ef7eb2e8f9f7	645	/* Generate Stop */
<>	144:ef7eb2e8f9f7	646	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	647	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	648	}
<>	144:ef7eb2e8f9f7	649	else
<>	144:ef7eb2e8f9f7	650	{
<>	144:ef7eb2e8f9f7	651	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	652	}
<>	144:ef7eb2e8f9f7	653	}
<>	144:ef7eb2e8f9f7	654	}
<>	144:ef7eb2e8f9f7	655
<>	144:ef7eb2e8f9f7	656	/* Generate Stop */
<>	144:ef7eb2e8f9f7	657	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	658
<>	144:ef7eb2e8f9f7	659	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	660	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	661
<>	144:ef7eb2e8f9f7	662	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	663	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	664
<>	144:ef7eb2e8f9f7	665	return HAL_OK;
<>	144:ef7eb2e8f9f7	666	}
<>	144:ef7eb2e8f9f7	667	else
<>	144:ef7eb2e8f9f7	668	{
<>	144:ef7eb2e8f9f7	669	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	670	}
<>	144:ef7eb2e8f9f7	671	}
<>	144:ef7eb2e8f9f7	672
<>	144:ef7eb2e8f9f7	673	/**
<>	144:ef7eb2e8f9f7	674	* @brief Receives in master mode an amount of data in blocking mode.
<>	144:ef7eb2e8f9f7	675	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	676	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	677	* @param DevAddress Target device address: The device 7 bits address value
<>	144:ef7eb2e8f9f7	678	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	679	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	680	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	681	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	682	* @retval HAL status
<>	144:ef7eb2e8f9f7	683	*/
<>	144:ef7eb2e8f9f7	684	HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	685	{
<>	144:ef7eb2e8f9f7	686	uint32_t tickstart = 0x00U;
<>	144:ef7eb2e8f9f7	687
<>	144:ef7eb2e8f9f7	688	/* Init tickstart for timeout management*/
<>	144:ef7eb2e8f9f7	689	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	690
<>	144:ef7eb2e8f9f7	691	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	692	{
<>	144:ef7eb2e8f9f7	693	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	694	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	695	{
<>	144:ef7eb2e8f9f7	696	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	697	}
<>	144:ef7eb2e8f9f7	698
<>	144:ef7eb2e8f9f7	699	/* Process Locked */
<>	144:ef7eb2e8f9f7	700	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	701
<>	144:ef7eb2e8f9f7	702	/* Disable Pos */
<>	144:ef7eb2e8f9f7	703	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	704
<>	144:ef7eb2e8f9f7	705	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	706	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	144:ef7eb2e8f9f7	707	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	708	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	709
<>	144:ef7eb2e8f9f7	710	/* Send Slave Address */
<>	144:ef7eb2e8f9f7	711	if(I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	712	{
<>	144:ef7eb2e8f9f7	713	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	714	{
<>	144:ef7eb2e8f9f7	715	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	716	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	717	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	718	}
<>	144:ef7eb2e8f9f7	719	else
<>	144:ef7eb2e8f9f7	720	{
<>	144:ef7eb2e8f9f7	721	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	722	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	723	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	724	}
<>	144:ef7eb2e8f9f7	725	}
<>	144:ef7eb2e8f9f7	726
<>	144:ef7eb2e8f9f7	727	if(Size == 0U)
<>	144:ef7eb2e8f9f7	728	{
<>	144:ef7eb2e8f9f7	729	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	730	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	731
<>	144:ef7eb2e8f9f7	732	/* Generate Stop */
<>	144:ef7eb2e8f9f7	733	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	734	}
<>	144:ef7eb2e8f9f7	735	else if(Size == 1U)
<>	144:ef7eb2e8f9f7	736	{
<>	144:ef7eb2e8f9f7	737	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	738	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	739
<>	144:ef7eb2e8f9f7	740	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	741	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	742
<>	144:ef7eb2e8f9f7	743	/* Generate Stop */
<>	144:ef7eb2e8f9f7	744	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	745	}
<>	144:ef7eb2e8f9f7	746	else if(Size == 2U)
<>	144:ef7eb2e8f9f7	747	{
<>	144:ef7eb2e8f9f7	748	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	749	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	750
<>	144:ef7eb2e8f9f7	751	/* Enable Pos */
<>	144:ef7eb2e8f9f7	752	hi2c->Instance->CR1 \|= I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	753
<>	144:ef7eb2e8f9f7	754	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	755	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	756	}
<>	144:ef7eb2e8f9f7	757	else
<>	144:ef7eb2e8f9f7	758	{
<>	144:ef7eb2e8f9f7	759	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	760	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	761
<>	144:ef7eb2e8f9f7	762	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	763	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	764	}
<>	144:ef7eb2e8f9f7	765
<>	144:ef7eb2e8f9f7	766	while(Size > 0U)
<>	144:ef7eb2e8f9f7	767	{
<>	144:ef7eb2e8f9f7	768	if(Size <= 3U)
<>	144:ef7eb2e8f9f7	769	{
<>	144:ef7eb2e8f9f7	770	/* One byte */
<>	144:ef7eb2e8f9f7	771	if(Size == 1U)
<>	144:ef7eb2e8f9f7	772	{
<>	144:ef7eb2e8f9f7	773	/* Wait until RXNE flag is set */
<>	144:ef7eb2e8f9f7	774	if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	775	{
<>	144:ef7eb2e8f9f7	776	if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
<>	144:ef7eb2e8f9f7	777	{
<>	144:ef7eb2e8f9f7	778	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	779	}
<>	144:ef7eb2e8f9f7	780	else
<>	144:ef7eb2e8f9f7	781	{
<>	144:ef7eb2e8f9f7	782	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	783	}
<>	144:ef7eb2e8f9f7	784	}
<>	144:ef7eb2e8f9f7	785
<>	144:ef7eb2e8f9f7	786	/* Read data from DR */
<>	144:ef7eb2e8f9f7	787	(*pData++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	788	Size--;
<>	144:ef7eb2e8f9f7	789	}
<>	144:ef7eb2e8f9f7	790	/* Two bytes */
<>	144:ef7eb2e8f9f7	791	else if(Size == 2U)
<>	144:ef7eb2e8f9f7	792	{
<>	144:ef7eb2e8f9f7	793	/* Wait until BTF flag is set */
<>	144:ef7eb2e8f9f7	794	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	795	{
<>	144:ef7eb2e8f9f7	796	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	797	}
<>	144:ef7eb2e8f9f7	798
<>	144:ef7eb2e8f9f7	799	/* Generate Stop */
<>	144:ef7eb2e8f9f7	800	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	801
<>	144:ef7eb2e8f9f7	802	/* Read data from DR */
<>	144:ef7eb2e8f9f7	803	(*pData++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	804	Size--;
<>	144:ef7eb2e8f9f7	805
<>	144:ef7eb2e8f9f7	806	/* Read data from DR */
<>	144:ef7eb2e8f9f7	807	(*pData++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	808	Size--;
<>	144:ef7eb2e8f9f7	809	}
<>	144:ef7eb2e8f9f7	810	/* 3 Last bytes */
<>	144:ef7eb2e8f9f7	811	else
<>	144:ef7eb2e8f9f7	812	{
<>	144:ef7eb2e8f9f7	813	/* Wait until BTF flag is set */
<>	144:ef7eb2e8f9f7	814	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	815	{
<>	144:ef7eb2e8f9f7	816	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	817	}
<>	144:ef7eb2e8f9f7	818
<>	144:ef7eb2e8f9f7	819	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	820	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	821
<>	144:ef7eb2e8f9f7	822	/* Read data from DR */
<>	144:ef7eb2e8f9f7	823	(*pData++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	824	Size--;
<>	144:ef7eb2e8f9f7	825
<>	144:ef7eb2e8f9f7	826	/* Wait until BTF flag is set */
<>	144:ef7eb2e8f9f7	827	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	828	{
<>	144:ef7eb2e8f9f7	829	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	830	}
<>	144:ef7eb2e8f9f7	831
<>	144:ef7eb2e8f9f7	832	/* Generate Stop */
<>	144:ef7eb2e8f9f7	833	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	834
<>	144:ef7eb2e8f9f7	835	/* Read data from DR */
<>	144:ef7eb2e8f9f7	836	(*pData++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	837	Size--;
<>	144:ef7eb2e8f9f7	838
<>	144:ef7eb2e8f9f7	839	/* Read data from DR */
<>	144:ef7eb2e8f9f7	840	(*pData++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	841	Size--;
<>	144:ef7eb2e8f9f7	842	}
<>	144:ef7eb2e8f9f7	843	}
<>	144:ef7eb2e8f9f7	844	else
<>	144:ef7eb2e8f9f7	845	{
<>	144:ef7eb2e8f9f7	846	/* Wait until RXNE flag is set */
<>	144:ef7eb2e8f9f7	847	if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	848	{
<>	144:ef7eb2e8f9f7	849	if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
<>	144:ef7eb2e8f9f7	850	{
<>	144:ef7eb2e8f9f7	851	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	852	}
<>	144:ef7eb2e8f9f7	853	else
<>	144:ef7eb2e8f9f7	854	{
<>	144:ef7eb2e8f9f7	855	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	856	}
<>	144:ef7eb2e8f9f7	857	}
<>	144:ef7eb2e8f9f7	858
<>	144:ef7eb2e8f9f7	859	/* Read data from DR */
<>	144:ef7eb2e8f9f7	860	(*pData++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	861	Size--;
<>	144:ef7eb2e8f9f7	862
<>	144:ef7eb2e8f9f7	863	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
<>	144:ef7eb2e8f9f7	864	{
<>	144:ef7eb2e8f9f7	865	/* Read data from DR */
<>	144:ef7eb2e8f9f7	866	(*pData++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	867	Size--;
<>	144:ef7eb2e8f9f7	868	}
<>	144:ef7eb2e8f9f7	869	}
<>	144:ef7eb2e8f9f7	870	}
<>	144:ef7eb2e8f9f7	871
<>	144:ef7eb2e8f9f7	872	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	873	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	874
<>	144:ef7eb2e8f9f7	875	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	876	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	877
<>	144:ef7eb2e8f9f7	878	return HAL_OK;
<>	144:ef7eb2e8f9f7	879	}
<>	144:ef7eb2e8f9f7	880	else
<>	144:ef7eb2e8f9f7	881	{
<>	144:ef7eb2e8f9f7	882	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	883	}
<>	144:ef7eb2e8f9f7	884	}
<>	144:ef7eb2e8f9f7	885
<>	144:ef7eb2e8f9f7	886	/**
<>	144:ef7eb2e8f9f7	887	* @brief Transmits in slave mode an amount of data in blocking mode.
<>	144:ef7eb2e8f9f7	888	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	889	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	890	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	891	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	892	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	893	* @retval HAL status
<>	144:ef7eb2e8f9f7	894	*/
<>	144:ef7eb2e8f9f7	895	HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	896	{
<>	144:ef7eb2e8f9f7	897	uint32_t tickstart = 0x00U;
<>	144:ef7eb2e8f9f7	898
<>	144:ef7eb2e8f9f7	899	/* Init tickstart for timeout management*/
<>	144:ef7eb2e8f9f7	900	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	901
<>	144:ef7eb2e8f9f7	902	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	903	{
<>	144:ef7eb2e8f9f7	904	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	905	{
<>	144:ef7eb2e8f9f7	906	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	907	}
<>	144:ef7eb2e8f9f7	908
<>	144:ef7eb2e8f9f7	909	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	910	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	911	{
<>	144:ef7eb2e8f9f7	912	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	913	}
<>	144:ef7eb2e8f9f7	914
<>	144:ef7eb2e8f9f7	915	/* Process Locked */
<>	144:ef7eb2e8f9f7	916	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	917
<>	144:ef7eb2e8f9f7	918	/* Disable Pos */
<>	144:ef7eb2e8f9f7	919	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	920
<>	144:ef7eb2e8f9f7	921	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	922	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	144:ef7eb2e8f9f7	923	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	924	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	925
<>	144:ef7eb2e8f9f7	926	/* Enable Address Acknowledge */
<>	144:ef7eb2e8f9f7	927	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	928
<>	144:ef7eb2e8f9f7	929	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	930	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	931	{
<>	144:ef7eb2e8f9f7	932	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	933	}
<>	144:ef7eb2e8f9f7	934
<>	144:ef7eb2e8f9f7	935	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	936	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	937
<>	144:ef7eb2e8f9f7	938	/* If 10bit addressing mode is selected */
<>	144:ef7eb2e8f9f7	939	if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
<>	144:ef7eb2e8f9f7	940	{
<>	144:ef7eb2e8f9f7	941	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	942	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	943	{
<>	144:ef7eb2e8f9f7	944	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	945	}
<>	144:ef7eb2e8f9f7	946
<>	144:ef7eb2e8f9f7	947	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	948	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	949	}
<>	144:ef7eb2e8f9f7	950
<>	144:ef7eb2e8f9f7	951	while(Size > 0U)
<>	144:ef7eb2e8f9f7	952	{
<>	144:ef7eb2e8f9f7	953	/* Wait until TXE flag is set */
<>	144:ef7eb2e8f9f7	954	if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	955	{
<>	144:ef7eb2e8f9f7	956	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	957	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	958	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	959	{
<>	144:ef7eb2e8f9f7	960	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	961	}
<>	144:ef7eb2e8f9f7	962	else
<>	144:ef7eb2e8f9f7	963	{
<>	144:ef7eb2e8f9f7	964	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	965	}
<>	144:ef7eb2e8f9f7	966	}
<>	144:ef7eb2e8f9f7	967
<>	144:ef7eb2e8f9f7	968	/* Write data to DR */
<>	144:ef7eb2e8f9f7	969	hi2c->Instance->DR = (*pData++);
<>	144:ef7eb2e8f9f7	970	Size--;
<>	144:ef7eb2e8f9f7	971
<>	144:ef7eb2e8f9f7	972	if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U))
<>	144:ef7eb2e8f9f7	973	{
<>	144:ef7eb2e8f9f7	974	/* Write data to DR */
<>	144:ef7eb2e8f9f7	975	hi2c->Instance->DR = (*pData++);
<>	144:ef7eb2e8f9f7	976	Size--;
<>	144:ef7eb2e8f9f7	977	}
<>	144:ef7eb2e8f9f7	978	}
<>	144:ef7eb2e8f9f7	979
<>	144:ef7eb2e8f9f7	980	/* Wait until AF flag is set */
<>	144:ef7eb2e8f9f7	981	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	982	{
<>	144:ef7eb2e8f9f7	983	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	984	}
<>	144:ef7eb2e8f9f7	985
<>	144:ef7eb2e8f9f7	986	/* Clear AF flag */
<>	144:ef7eb2e8f9f7	987	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	988
<>	144:ef7eb2e8f9f7	989	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	990	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	991
<>	144:ef7eb2e8f9f7	992	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	993	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	994
<>	144:ef7eb2e8f9f7	995	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	996	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	997
<>	144:ef7eb2e8f9f7	998	return HAL_OK;
<>	144:ef7eb2e8f9f7	999	}
<>	144:ef7eb2e8f9f7	1000	else
<>	144:ef7eb2e8f9f7	1001	{
<>	144:ef7eb2e8f9f7	1002	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1003	}
<>	144:ef7eb2e8f9f7	1004	}
<>	144:ef7eb2e8f9f7	1005
<>	144:ef7eb2e8f9f7	1006	/**
<>	144:ef7eb2e8f9f7	1007	* @brief Receive in slave mode an amount of data in blocking mode
<>	144:ef7eb2e8f9f7	1008	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1009	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	1010	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1011	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1012	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	1013	* @retval HAL status
<>	144:ef7eb2e8f9f7	1014	*/
<>	144:ef7eb2e8f9f7	1015	HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	1016	{
<>	144:ef7eb2e8f9f7	1017	uint32_t tickstart = 0x00U;
<>	144:ef7eb2e8f9f7	1018
<>	144:ef7eb2e8f9f7	1019	/* Init tickstart for timeout management*/
<>	144:ef7eb2e8f9f7	1020	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1021
<>	144:ef7eb2e8f9f7	1022	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1023	{
<>	144:ef7eb2e8f9f7	1024	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	1025	{
<>	144:ef7eb2e8f9f7	1026	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1027	}
<>	144:ef7eb2e8f9f7	1028
<>	144:ef7eb2e8f9f7	1029	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	1030	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1031	{
<>	144:ef7eb2e8f9f7	1032	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1033	}
<>	144:ef7eb2e8f9f7	1034
<>	144:ef7eb2e8f9f7	1035	/* Process Locked */
<>	144:ef7eb2e8f9f7	1036	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1037
<>	144:ef7eb2e8f9f7	1038	/* Disable Pos */
<>	144:ef7eb2e8f9f7	1039	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	1040
<>	144:ef7eb2e8f9f7	1041	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	1042	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	144:ef7eb2e8f9f7	1043	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1044	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	1045
<>	144:ef7eb2e8f9f7	1046	/* Enable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1047	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1048
<>	144:ef7eb2e8f9f7	1049	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	1050	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1051	{
<>	144:ef7eb2e8f9f7	1052	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1053	}
<>	144:ef7eb2e8f9f7	1054
<>	144:ef7eb2e8f9f7	1055	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	1056	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	1057
<>	144:ef7eb2e8f9f7	1058	while(Size > 0U)
<>	144:ef7eb2e8f9f7	1059	{
<>	144:ef7eb2e8f9f7	1060	/* Wait until RXNE flag is set */
<>	144:ef7eb2e8f9f7	1061	if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1062	{
<>	144:ef7eb2e8f9f7	1063	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1064	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1065	if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
<>	144:ef7eb2e8f9f7	1066	{
<>	144:ef7eb2e8f9f7	1067	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1068	}
<>	144:ef7eb2e8f9f7	1069	else
<>	144:ef7eb2e8f9f7	1070	{
<>	144:ef7eb2e8f9f7	1071	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1072	}
<>	144:ef7eb2e8f9f7	1073	}
<>	144:ef7eb2e8f9f7	1074
<>	144:ef7eb2e8f9f7	1075	/* Read data from DR */
<>	144:ef7eb2e8f9f7	1076	(*pData++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	1077	Size--;
<>	144:ef7eb2e8f9f7	1078
<>	144:ef7eb2e8f9f7	1079	if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U))
<>	144:ef7eb2e8f9f7	1080	{
<>	144:ef7eb2e8f9f7	1081	/* Read data from DR */
<>	144:ef7eb2e8f9f7	1082	(*pData++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	1083	Size--;
<>	144:ef7eb2e8f9f7	1084	}
<>	144:ef7eb2e8f9f7	1085	}
<>	144:ef7eb2e8f9f7	1086
<>	144:ef7eb2e8f9f7	1087	/* Wait until STOP flag is set */
<>	144:ef7eb2e8f9f7	1088	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1089	{
<>	144:ef7eb2e8f9f7	1090	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1091	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1092
<>	144:ef7eb2e8f9f7	1093	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	1094	{
<>	144:ef7eb2e8f9f7	1095	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1096	}
<>	144:ef7eb2e8f9f7	1097	else
<>	144:ef7eb2e8f9f7	1098	{
<>	144:ef7eb2e8f9f7	1099	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1100	}
<>	144:ef7eb2e8f9f7	1101	}
<>	144:ef7eb2e8f9f7	1102
<>	144:ef7eb2e8f9f7	1103	/* Clear STOP flag */
<>	144:ef7eb2e8f9f7	1104	__HAL_I2C_CLEAR_STOPFLAG(hi2c);
<>	144:ef7eb2e8f9f7	1105
<>	144:ef7eb2e8f9f7	1106	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1107	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1108
<>	144:ef7eb2e8f9f7	1109	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1110	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	1111
<>	144:ef7eb2e8f9f7	1112	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1113	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1114
<>	144:ef7eb2e8f9f7	1115	return HAL_OK;
<>	144:ef7eb2e8f9f7	1116	}
<>	144:ef7eb2e8f9f7	1117	else
<>	144:ef7eb2e8f9f7	1118	{
<>	144:ef7eb2e8f9f7	1119	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1120	}
<>	144:ef7eb2e8f9f7	1121	}
<>	144:ef7eb2e8f9f7	1122
<>	144:ef7eb2e8f9f7	1123	/**
<>	144:ef7eb2e8f9f7	1124	* @brief Transmit in master mode an amount of data in no-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1125	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1126	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	1127	* @param DevAddress Target device address: The device 7 bits address value
<>	144:ef7eb2e8f9f7	1128	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	1129	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1130	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1131	* @retval HAL status
<>	144:ef7eb2e8f9f7	1132	*/
<>	144:ef7eb2e8f9f7	1133	HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1134	{
<>	144:ef7eb2e8f9f7	1135	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	1136
<>	144:ef7eb2e8f9f7	1137	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1138	{
<>	144:ef7eb2e8f9f7	1139	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	1140	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	1141	do
<>	144:ef7eb2e8f9f7	1142	{
<>	144:ef7eb2e8f9f7	1143	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	1144	{
<>	144:ef7eb2e8f9f7	1145	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	1146	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1147
<>	144:ef7eb2e8f9f7	1148	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1149	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1150
<>	144:ef7eb2e8f9f7	1151	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1152	}
<>	144:ef7eb2e8f9f7	1153	}
<>	144:ef7eb2e8f9f7	1154	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	1155
<>	144:ef7eb2e8f9f7	1156	/* Process Locked */
<>	144:ef7eb2e8f9f7	1157	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1158
<>	144:ef7eb2e8f9f7	1159	/* Disable Pos */
<>	144:ef7eb2e8f9f7	1160	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	1161
<>	144:ef7eb2e8f9f7	1162	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	1163	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	144:ef7eb2e8f9f7	1164	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1165
<>	144:ef7eb2e8f9f7	1166	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1167	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	1168	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1169	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	1170	hi2c->Devaddress = DevAddress;
<>	144:ef7eb2e8f9f7	1171
<>	144:ef7eb2e8f9f7	1172	/* Generate Start */
<>	144:ef7eb2e8f9f7	1173	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	1174
<>	144:ef7eb2e8f9f7	1175	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1176	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1177
<>	144:ef7eb2e8f9f7	1178	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1179	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1180	process unlock */
<>	144:ef7eb2e8f9f7	1181	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	1182	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	1183
<>	144:ef7eb2e8f9f7	1184	return HAL_OK;
<>	144:ef7eb2e8f9f7	1185	}
<>	144:ef7eb2e8f9f7	1186	else
<>	144:ef7eb2e8f9f7	1187	{
<>	144:ef7eb2e8f9f7	1188	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1189	}
<>	144:ef7eb2e8f9f7	1190	}
<>	144:ef7eb2e8f9f7	1191
<>	144:ef7eb2e8f9f7	1192	/**
<>	144:ef7eb2e8f9f7	1193	* @brief Receive in master mode an amount of data in no-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1194	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1195	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	1196	* @param DevAddress Target device address: The device 7 bits address value
<>	144:ef7eb2e8f9f7	1197	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	1198	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1199	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1200	* @retval HAL status
<>	144:ef7eb2e8f9f7	1201	*/
<>	144:ef7eb2e8f9f7	1202	HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1203	{
<>	144:ef7eb2e8f9f7	1204	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	1205
<>	144:ef7eb2e8f9f7	1206	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1207	{
<>	144:ef7eb2e8f9f7	1208	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	1209	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	1210	do
<>	144:ef7eb2e8f9f7	1211	{
<>	144:ef7eb2e8f9f7	1212	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	1213	{
<>	144:ef7eb2e8f9f7	1214	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	1215	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1216
<>	144:ef7eb2e8f9f7	1217	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1218	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1219
<>	144:ef7eb2e8f9f7	1220	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1221	}
<>	144:ef7eb2e8f9f7	1222	}
<>	144:ef7eb2e8f9f7	1223	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	1224
<>	144:ef7eb2e8f9f7	1225	/* Process Locked */
<>	144:ef7eb2e8f9f7	1226	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1227
<>	144:ef7eb2e8f9f7	1228	/* Disable Pos */
<>	144:ef7eb2e8f9f7	1229	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	1230
<>	144:ef7eb2e8f9f7	1231	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	1232	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	144:ef7eb2e8f9f7	1233	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1234	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1235	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	1236	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1237	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	1238	hi2c->Devaddress = DevAddress;
<>	144:ef7eb2e8f9f7	1239
<>	144:ef7eb2e8f9f7	1240	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	1241	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1242
<>	144:ef7eb2e8f9f7	1243	/* Generate Start */
<>	144:ef7eb2e8f9f7	1244	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	1245
<>	144:ef7eb2e8f9f7	1246	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1247	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1248
<>	144:ef7eb2e8f9f7	1249	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1250	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1251	process unlock */
<>	144:ef7eb2e8f9f7	1252
<>	144:ef7eb2e8f9f7	1253	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	1254	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	1255
<>	144:ef7eb2e8f9f7	1256	return HAL_OK;
<>	144:ef7eb2e8f9f7	1257	}
<>	144:ef7eb2e8f9f7	1258	else
<>	144:ef7eb2e8f9f7	1259	{
<>	144:ef7eb2e8f9f7	1260	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1261	}
<>	144:ef7eb2e8f9f7	1262	}
<>	144:ef7eb2e8f9f7	1263
<>	144:ef7eb2e8f9f7	1264	/**
<>	144:ef7eb2e8f9f7	1265	* @brief Sequential transmit in master mode an amount of data in no-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1266	* @note This interface allow to manage repeated start condition when a direction change during transfer
<>	144:ef7eb2e8f9f7	1267	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1268	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	1269	* @param DevAddress Target device address: The device 7 bits address value
<>	144:ef7eb2e8f9f7	1270	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	1271	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1272	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1273	* @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
<>	144:ef7eb2e8f9f7	1274	* @retval HAL status
<>	144:ef7eb2e8f9f7	1275	*/
<>	144:ef7eb2e8f9f7	1276	HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size, uint32_t XferOptions)
<>	144:ef7eb2e8f9f7	1277	{
<>	144:ef7eb2e8f9f7	1278	uint32_t Prev_State = 0x00U;
<>	144:ef7eb2e8f9f7	1279	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	1280
<>	144:ef7eb2e8f9f7	1281	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1282	assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
<>	144:ef7eb2e8f9f7	1283
<>	144:ef7eb2e8f9f7	1284	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1285	{
<>	144:ef7eb2e8f9f7	1286	/* Check Busy Flag only if FIRST call of Master interface */
<>	144:ef7eb2e8f9f7	1287	if((XferOptions == I2C_FIRST_AND_LAST_FRAME) \|\| (XferOptions == I2C_FIRST_FRAME))
<>	144:ef7eb2e8f9f7	1288	{
<>	144:ef7eb2e8f9f7	1289	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	1290	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	1291	do
<>	144:ef7eb2e8f9f7	1292	{
<>	144:ef7eb2e8f9f7	1293	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	1294	{
<>	144:ef7eb2e8f9f7	1295	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	1296	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1297
<>	144:ef7eb2e8f9f7	1298	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1299	__HAL_UNLOCK(hi2c);
<>	148:21d94c44109e	1300
<>	144:ef7eb2e8f9f7	1301	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1302	}
<>	144:ef7eb2e8f9f7	1303	}
<>	144:ef7eb2e8f9f7	1304	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	1305	}
<>	144:ef7eb2e8f9f7	1306
<>	144:ef7eb2e8f9f7	1307	/* Process Locked */
<>	144:ef7eb2e8f9f7	1308	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1309
<>	144:ef7eb2e8f9f7	1310	/* Disable Pos */
<>	144:ef7eb2e8f9f7	1311	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	1312
<>	144:ef7eb2e8f9f7	1313	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	1314	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	144:ef7eb2e8f9f7	1315	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1316
<>	144:ef7eb2e8f9f7	1317	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1318	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	1319	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1320	hi2c->XferOptions = XferOptions;
<>	144:ef7eb2e8f9f7	1321	hi2c->Devaddress = DevAddress;
<>	144:ef7eb2e8f9f7	1322
<>	144:ef7eb2e8f9f7	1323	Prev_State = hi2c->PreviousState;
<>	148:21d94c44109e	1324
<>	144:ef7eb2e8f9f7	1325	/* Generate Start */
<>	144:ef7eb2e8f9f7	1326	if((Prev_State == I2C_STATE_MASTER_BUSY_RX) \|\| (Prev_State == I2C_STATE_NONE))
<>	144:ef7eb2e8f9f7	1327	{
<>	144:ef7eb2e8f9f7	1328	/* Generate Start condition if first transfer */
<>	144:ef7eb2e8f9f7	1329	if((XferOptions == I2C_FIRST_AND_LAST_FRAME) \|\| (XferOptions == I2C_FIRST_FRAME))
<>	144:ef7eb2e8f9f7	1330	{
<>	144:ef7eb2e8f9f7	1331	/* Generate Start */
<>	144:ef7eb2e8f9f7	1332	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	1333	}
<>	144:ef7eb2e8f9f7	1334	else if(Prev_State == I2C_STATE_MASTER_BUSY_RX)
<>	144:ef7eb2e8f9f7	1335	{
<>	144:ef7eb2e8f9f7	1336	/* Generate ReStart */
<>	144:ef7eb2e8f9f7	1337	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	1338	}
<>	144:ef7eb2e8f9f7	1339	}
<>	144:ef7eb2e8f9f7	1340
<>	144:ef7eb2e8f9f7	1341	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1342	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1343
<>	144:ef7eb2e8f9f7	1344	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1345	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1346	process unlock */
<>	144:ef7eb2e8f9f7	1347
<>	144:ef7eb2e8f9f7	1348	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	1349	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	1350
<>	144:ef7eb2e8f9f7	1351	return HAL_OK;
<>	144:ef7eb2e8f9f7	1352	}
<>	144:ef7eb2e8f9f7	1353	else
<>	144:ef7eb2e8f9f7	1354	{
<>	144:ef7eb2e8f9f7	1355	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1356	}
<>	144:ef7eb2e8f9f7	1357	}
<>	144:ef7eb2e8f9f7	1358
<>	144:ef7eb2e8f9f7	1359	/**
<>	144:ef7eb2e8f9f7	1360	* @brief Sequential receive in master mode an amount of data in no-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1361	* @note This interface allow to manage repeated start condition when a direction change during transfer
<>	144:ef7eb2e8f9f7	1362	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1363	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	1364	* @param DevAddress Target device address: The device 7 bits address value
<>	144:ef7eb2e8f9f7	1365	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	1366	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1367	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1368	* @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
<>	144:ef7eb2e8f9f7	1369	* @retval HAL status
<>	144:ef7eb2e8f9f7	1370	*/
<>	144:ef7eb2e8f9f7	1371	HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size, uint32_t XferOptions)
<>	144:ef7eb2e8f9f7	1372	{
<>	144:ef7eb2e8f9f7	1373	uint32_t Prev_State = 0x00U;
<>	144:ef7eb2e8f9f7	1374	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	1375
<>	144:ef7eb2e8f9f7	1376	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1377	assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
<>	144:ef7eb2e8f9f7	1378
<>	144:ef7eb2e8f9f7	1379	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1380	{
<>	144:ef7eb2e8f9f7	1381	/* Check Busy Flag only if FIRST call of Master interface */
<>	144:ef7eb2e8f9f7	1382	if((XferOptions == I2C_FIRST_AND_LAST_FRAME) \|\| (XferOptions == I2C_FIRST_FRAME))
<>	144:ef7eb2e8f9f7	1383	{
<>	144:ef7eb2e8f9f7	1384	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	1385	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	1386	do
<>	144:ef7eb2e8f9f7	1387	{
<>	144:ef7eb2e8f9f7	1388	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	1389	{
<>	144:ef7eb2e8f9f7	1390	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	1391	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1392
<>	144:ef7eb2e8f9f7	1393	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1394	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1395
<>	144:ef7eb2e8f9f7	1396	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1397	}
<>	144:ef7eb2e8f9f7	1398	}
<>	144:ef7eb2e8f9f7	1399	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	1400	}
<>	144:ef7eb2e8f9f7	1401
<>	144:ef7eb2e8f9f7	1402	/* Process Locked */
<>	144:ef7eb2e8f9f7	1403	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1404
<>	144:ef7eb2e8f9f7	1405	/* Disable Pos */
<>	144:ef7eb2e8f9f7	1406	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	1407
<>	144:ef7eb2e8f9f7	1408	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	1409	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	144:ef7eb2e8f9f7	1410	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1411
<>	144:ef7eb2e8f9f7	1412	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1413	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	1414	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1415	hi2c->XferOptions = XferOptions;
<>	144:ef7eb2e8f9f7	1416	hi2c->Devaddress = DevAddress;
<>	144:ef7eb2e8f9f7	1417
<>	144:ef7eb2e8f9f7	1418	Prev_State = hi2c->PreviousState;
<>	144:ef7eb2e8f9f7	1419
<>	144:ef7eb2e8f9f7	1420	if((Prev_State == I2C_STATE_MASTER_BUSY_TX) \|\| (Prev_State == I2C_STATE_NONE))
<>	144:ef7eb2e8f9f7	1421	{
<>	144:ef7eb2e8f9f7	1422	/* Generate Start condition if first transfer */
<>	144:ef7eb2e8f9f7	1423	if((XferOptions == I2C_FIRST_AND_LAST_FRAME) \|\| (XferOptions == I2C_FIRST_FRAME) \|\| (XferOptions == I2C_NO_OPTION_FRAME))
<>	144:ef7eb2e8f9f7	1424	{
<>	144:ef7eb2e8f9f7	1425	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	1426	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1427
<>	144:ef7eb2e8f9f7	1428	/* Generate Start */
<>	144:ef7eb2e8f9f7	1429	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	1430	}
<>	144:ef7eb2e8f9f7	1431	else if(Prev_State == I2C_STATE_MASTER_BUSY_TX)
<>	144:ef7eb2e8f9f7	1432	{
<>	144:ef7eb2e8f9f7	1433	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	1434	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1435
<>	144:ef7eb2e8f9f7	1436	/* Generate ReStart */
<>	144:ef7eb2e8f9f7	1437	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	1438	}
<>	144:ef7eb2e8f9f7	1439	}
<>	144:ef7eb2e8f9f7	1440
<>	144:ef7eb2e8f9f7	1441	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1442	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1443
<>	144:ef7eb2e8f9f7	1444	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1445	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1446	process unlock */
<>	144:ef7eb2e8f9f7	1447
<>	144:ef7eb2e8f9f7	1448	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	1449	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	1450
<>	144:ef7eb2e8f9f7	1451	return HAL_OK;
<>	144:ef7eb2e8f9f7	1452	}
<>	144:ef7eb2e8f9f7	1453	else
<>	144:ef7eb2e8f9f7	1454	{
<>	144:ef7eb2e8f9f7	1455	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1456	}
<>	144:ef7eb2e8f9f7	1457	}
<>	144:ef7eb2e8f9f7	1458
<>	144:ef7eb2e8f9f7	1459	/**
<>	144:ef7eb2e8f9f7	1460	* @brief Transmit in slave mode an amount of data in no-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1461	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1462	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	1463	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1464	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1465	* @retval HAL status
<>	144:ef7eb2e8f9f7	1466	*/
<>	144:ef7eb2e8f9f7	1467	HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1468	{
<>	144:ef7eb2e8f9f7	1469	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	1470
<>	144:ef7eb2e8f9f7	1471	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1472	{
<>	144:ef7eb2e8f9f7	1473	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	1474	{
<>	144:ef7eb2e8f9f7	1475	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1476	}
<>	144:ef7eb2e8f9f7	1477
<>	144:ef7eb2e8f9f7	1478	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	1479	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	1480	do
<>	144:ef7eb2e8f9f7	1481	{
<>	144:ef7eb2e8f9f7	1482	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	1483	{
<>	144:ef7eb2e8f9f7	1484	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	1485	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1486
<>	144:ef7eb2e8f9f7	1487	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1488	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1489
<>	144:ef7eb2e8f9f7	1490	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1491	}
<>	144:ef7eb2e8f9f7	1492	}
<>	144:ef7eb2e8f9f7	1493	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	1494
<>	144:ef7eb2e8f9f7	1495	/* Process Locked */
<>	144:ef7eb2e8f9f7	1496	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1497
<>	144:ef7eb2e8f9f7	1498	/* Disable Pos */
<>	144:ef7eb2e8f9f7	1499	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	1500
<>	144:ef7eb2e8f9f7	1501	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	1502	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	144:ef7eb2e8f9f7	1503	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1504
<>	144:ef7eb2e8f9f7	1505	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1506	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	1507	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1508	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	1509
<>	144:ef7eb2e8f9f7	1510	/* Enable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1511	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1512
<>	144:ef7eb2e8f9f7	1513	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1514	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1515
<>	144:ef7eb2e8f9f7	1516	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1517	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1518	process unlock */
<>	144:ef7eb2e8f9f7	1519
<>	144:ef7eb2e8f9f7	1520	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	1521	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	1522
<>	144:ef7eb2e8f9f7	1523	return HAL_OK;
<>	144:ef7eb2e8f9f7	1524	}
<>	144:ef7eb2e8f9f7	1525	else
<>	144:ef7eb2e8f9f7	1526	{
<>	144:ef7eb2e8f9f7	1527	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1528	}
<>	144:ef7eb2e8f9f7	1529	}
<>	144:ef7eb2e8f9f7	1530
<>	144:ef7eb2e8f9f7	1531	/**
<>	144:ef7eb2e8f9f7	1532	* @brief Receive in slave mode an amount of data in no-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1533	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1534	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	1535	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1536	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1537	* @retval HAL status
<>	144:ef7eb2e8f9f7	1538	*/
<>	144:ef7eb2e8f9f7	1539	HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1540	{
<>	144:ef7eb2e8f9f7	1541	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	1542
<>	144:ef7eb2e8f9f7	1543	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1544	{
<>	144:ef7eb2e8f9f7	1545	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	1546	{
<>	144:ef7eb2e8f9f7	1547	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1548	}
<>	144:ef7eb2e8f9f7	1549
<>	144:ef7eb2e8f9f7	1550	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	1551	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	1552	do
<>	144:ef7eb2e8f9f7	1553	{
<>	144:ef7eb2e8f9f7	1554	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	1555	{
<>	144:ef7eb2e8f9f7	1556	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	1557	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1558
<>	144:ef7eb2e8f9f7	1559	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1560	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1561
<>	144:ef7eb2e8f9f7	1562	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1563	}
<>	144:ef7eb2e8f9f7	1564	}
<>	144:ef7eb2e8f9f7	1565	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	1566
<>	144:ef7eb2e8f9f7	1567	/* Process Locked */
<>	144:ef7eb2e8f9f7	1568	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1569
<>	144:ef7eb2e8f9f7	1570	/* Disable Pos */
<>	144:ef7eb2e8f9f7	1571	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	1572
<>	144:ef7eb2e8f9f7	1573	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	1574	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	144:ef7eb2e8f9f7	1575	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1576
<>	144:ef7eb2e8f9f7	1577	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1578	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	1579	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1580	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	1581
<>	144:ef7eb2e8f9f7	1582	/* Enable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1583	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1584
<>	144:ef7eb2e8f9f7	1585	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1586	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1587
<>	144:ef7eb2e8f9f7	1588	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1589	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1590	process unlock */
<>	144:ef7eb2e8f9f7	1591
<>	144:ef7eb2e8f9f7	1592	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	1593	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	1594
<>	144:ef7eb2e8f9f7	1595	return HAL_OK;
<>	144:ef7eb2e8f9f7	1596	}
<>	144:ef7eb2e8f9f7	1597	else
<>	144:ef7eb2e8f9f7	1598	{
<>	144:ef7eb2e8f9f7	1599	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1600	}
<>	144:ef7eb2e8f9f7	1601	}
<>	144:ef7eb2e8f9f7	1602
<>	144:ef7eb2e8f9f7	1603	/**
<>	144:ef7eb2e8f9f7	1604	* @brief Sequential transmit in slave mode an amount of data in no-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1605	* @note This interface allow to manage repeated start condition when a direction change during transfer
<>	144:ef7eb2e8f9f7	1606	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1607	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	1608	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1609	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1610	* @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
<>	144:ef7eb2e8f9f7	1611	* @retval HAL status
<>	144:ef7eb2e8f9f7	1612	*/
<>	144:ef7eb2e8f9f7	1613	HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size, uint32_t XferOptions)
<>	144:ef7eb2e8f9f7	1614	{
<>	144:ef7eb2e8f9f7	1615	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1616	assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
<>	144:ef7eb2e8f9f7	1617
<>	144:ef7eb2e8f9f7	1618	if(hi2c->State == HAL_I2C_STATE_LISTEN)
<>	144:ef7eb2e8f9f7	1619	{
<>	144:ef7eb2e8f9f7	1620	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	1621	{
<>	144:ef7eb2e8f9f7	1622	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1623	}
<>	144:ef7eb2e8f9f7	1624
<>	144:ef7eb2e8f9f7	1625	/* Process Locked */
<>	144:ef7eb2e8f9f7	1626	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1627
<>	144:ef7eb2e8f9f7	1628	/* Disable Pos */
<>	144:ef7eb2e8f9f7	1629	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	1630
<>	144:ef7eb2e8f9f7	1631	hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
<>	144:ef7eb2e8f9f7	1632	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	144:ef7eb2e8f9f7	1633	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1634
<>	144:ef7eb2e8f9f7	1635	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1636	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	1637	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1638	hi2c->XferOptions = XferOptions;
<>	144:ef7eb2e8f9f7	1639
<>	144:ef7eb2e8f9f7	1640	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	1641	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	1642
<>	144:ef7eb2e8f9f7	1643	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1644	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1645
<>	144:ef7eb2e8f9f7	1646	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1647	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1648	process unlock */
<>	144:ef7eb2e8f9f7	1649
<>	144:ef7eb2e8f9f7	1650	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	1651	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	1652
<>	144:ef7eb2e8f9f7	1653	return HAL_OK;
<>	144:ef7eb2e8f9f7	1654	}
<>	144:ef7eb2e8f9f7	1655	else
<>	144:ef7eb2e8f9f7	1656	{
<>	144:ef7eb2e8f9f7	1657	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1658	}
<>	144:ef7eb2e8f9f7	1659	}
<>	144:ef7eb2e8f9f7	1660
<>	144:ef7eb2e8f9f7	1661	/**
<>	144:ef7eb2e8f9f7	1662	* @brief Sequential receive in slave mode an amount of data in no-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1663	* @note This interface allow to manage repeated start condition when a direction change during transfer
<>	144:ef7eb2e8f9f7	1664	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1665	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	1666	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1667	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1668	* @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
<>	144:ef7eb2e8f9f7	1669	* @retval HAL status
<>	144:ef7eb2e8f9f7	1670	*/
<>	144:ef7eb2e8f9f7	1671	HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size, uint32_t XferOptions)
<>	144:ef7eb2e8f9f7	1672	{
<>	144:ef7eb2e8f9f7	1673	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1674	assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
<>	144:ef7eb2e8f9f7	1675
<>	144:ef7eb2e8f9f7	1676	if(hi2c->State == HAL_I2C_STATE_LISTEN)
<>	144:ef7eb2e8f9f7	1677	{
<>	144:ef7eb2e8f9f7	1678	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	1679	{
<>	144:ef7eb2e8f9f7	1680	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1681	}
<>	144:ef7eb2e8f9f7	1682
<>	144:ef7eb2e8f9f7	1683	/* Process Locked */
<>	144:ef7eb2e8f9f7	1684	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1685
<>	144:ef7eb2e8f9f7	1686	/* Disable Pos */
<>	144:ef7eb2e8f9f7	1687	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	1688
<>	144:ef7eb2e8f9f7	1689	hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
<>	144:ef7eb2e8f9f7	1690	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	144:ef7eb2e8f9f7	1691	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1692
<>	144:ef7eb2e8f9f7	1693	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1694	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	1695	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1696	hi2c->XferOptions = XferOptions;
<>	144:ef7eb2e8f9f7	1697
<>	144:ef7eb2e8f9f7	1698	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	1699	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	1700
<>	144:ef7eb2e8f9f7	1701	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1702	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1703
<>	144:ef7eb2e8f9f7	1704	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1705	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1706	process unlock */
<>	144:ef7eb2e8f9f7	1707
<>	144:ef7eb2e8f9f7	1708	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	1709	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	1710
<>	144:ef7eb2e8f9f7	1711	return HAL_OK;
<>	144:ef7eb2e8f9f7	1712	}
<>	144:ef7eb2e8f9f7	1713	else
<>	144:ef7eb2e8f9f7	1714	{
<>	144:ef7eb2e8f9f7	1715	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1716	}
<>	144:ef7eb2e8f9f7	1717	}
<>	144:ef7eb2e8f9f7	1718
<>	144:ef7eb2e8f9f7	1719	/**
<>	144:ef7eb2e8f9f7	1720	* @brief Enable the Address listen mode with Interrupt.
<>	144:ef7eb2e8f9f7	1721	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1722	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1723	* @retval HAL status
<>	144:ef7eb2e8f9f7	1724	*/
<>	144:ef7eb2e8f9f7	1725	HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	1726	{
<>	144:ef7eb2e8f9f7	1727	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1728	{
<>	144:ef7eb2e8f9f7	1729	hi2c->State = HAL_I2C_STATE_LISTEN;
<>	144:ef7eb2e8f9f7	1730
<>	144:ef7eb2e8f9f7	1731	/* Enable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1732	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1733
<>	144:ef7eb2e8f9f7	1734	/* Enable EVT and ERR interrupt */
<>	144:ef7eb2e8f9f7	1735	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	1736
<>	144:ef7eb2e8f9f7	1737	return HAL_OK;
<>	144:ef7eb2e8f9f7	1738	}
<>	144:ef7eb2e8f9f7	1739	else
<>	144:ef7eb2e8f9f7	1740	{
<>	144:ef7eb2e8f9f7	1741	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1742	}
<>	144:ef7eb2e8f9f7	1743	}
<>	144:ef7eb2e8f9f7	1744
<>	144:ef7eb2e8f9f7	1745	/**
<>	144:ef7eb2e8f9f7	1746	* @brief Disable the Address listen mode with Interrupt.
<>	144:ef7eb2e8f9f7	1747	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1748	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1749	* @retval HAL status
<>	144:ef7eb2e8f9f7	1750	*/
<>	144:ef7eb2e8f9f7	1751	HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	1752	{
<>	144:ef7eb2e8f9f7	1753	/* Declaration of tmp to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	1754	uint32_t tmp;
<>	144:ef7eb2e8f9f7	1755
<>	144:ef7eb2e8f9f7	1756	/* Disable Address listen mode only if a transfer is not ongoing */
<>	144:ef7eb2e8f9f7	1757	if(hi2c->State == HAL_I2C_STATE_LISTEN)
<>	144:ef7eb2e8f9f7	1758	{
<>	144:ef7eb2e8f9f7	1759	tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
<>	144:ef7eb2e8f9f7	1760	hi2c->PreviousState = tmp \| (uint32_t)(hi2c->Mode);
<>	144:ef7eb2e8f9f7	1761	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1762	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	1763
<>	144:ef7eb2e8f9f7	1764	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1765	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1766
<>	144:ef7eb2e8f9f7	1767	/* Disable EVT and ERR interrupt */
<>	144:ef7eb2e8f9f7	1768	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	1769
<>	144:ef7eb2e8f9f7	1770	return HAL_OK;
<>	144:ef7eb2e8f9f7	1771	}
<>	144:ef7eb2e8f9f7	1772	else
<>	144:ef7eb2e8f9f7	1773	{
<>	144:ef7eb2e8f9f7	1774	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1775	}
<>	144:ef7eb2e8f9f7	1776	}
<>	144:ef7eb2e8f9f7	1777
<>	144:ef7eb2e8f9f7	1778	/**
<>	144:ef7eb2e8f9f7	1779	* @brief Transmit in master mode an amount of data in no-blocking mode with DMA
<>	144:ef7eb2e8f9f7	1780	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1781	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	1782	* @param DevAddress Target device address: The device 7 bits address value
<>	144:ef7eb2e8f9f7	1783	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	1784	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1785	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1786	* @retval HAL status
<>	144:ef7eb2e8f9f7	1787	*/
<>	144:ef7eb2e8f9f7	1788	HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1789	{
<>	144:ef7eb2e8f9f7	1790	uint32_t tickstart = 0x00U;
<>	144:ef7eb2e8f9f7	1791
<>	144:ef7eb2e8f9f7	1792	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	1793
<>	144:ef7eb2e8f9f7	1794	/* Init tickstart for timeout management*/
<>	144:ef7eb2e8f9f7	1795	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1796
<>	144:ef7eb2e8f9f7	1797	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1798	{
<>	144:ef7eb2e8f9f7	1799	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	1800	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	1801	do
<>	144:ef7eb2e8f9f7	1802	{
<>	144:ef7eb2e8f9f7	1803	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	1804	{
<>	144:ef7eb2e8f9f7	1805	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	1806	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1807
<>	144:ef7eb2e8f9f7	1808	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1809	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1810
<>	144:ef7eb2e8f9f7	1811	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1812	}
<>	144:ef7eb2e8f9f7	1813	}
<>	144:ef7eb2e8f9f7	1814	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	1815
<>	144:ef7eb2e8f9f7	1816	/* Process Locked */
<>	144:ef7eb2e8f9f7	1817	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1818
<>	144:ef7eb2e8f9f7	1819	/* Disable Pos */
<>	144:ef7eb2e8f9f7	1820	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	1821
<>	144:ef7eb2e8f9f7	1822	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	1823	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	144:ef7eb2e8f9f7	1824	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1825
<>	144:ef7eb2e8f9f7	1826	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1827	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	1828	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1829	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	1830
<>	144:ef7eb2e8f9f7	1831	if(hi2c->XferSize > 0U)
<>	144:ef7eb2e8f9f7	1832	{
<>	144:ef7eb2e8f9f7	1833	/* Set the I2C DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	1834	hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
<>	144:ef7eb2e8f9f7	1835
<>	144:ef7eb2e8f9f7	1836	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1837	hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
<>	144:ef7eb2e8f9f7	1838
<>	144:ef7eb2e8f9f7	1839	/* Set the unused DMA callbacks to NULL */
<>	144:ef7eb2e8f9f7	1840	hi2c->hdmatx->XferHalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	1841	hi2c->hdmatx->XferM1CpltCallback = NULL;
<>	144:ef7eb2e8f9f7	1842	hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	1843	hi2c->hdmatx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	1844
<>	144:ef7eb2e8f9f7	1845	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	1846	HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size);
<>	144:ef7eb2e8f9f7	1847
<>	144:ef7eb2e8f9f7	1848	/* Send Slave Address */
<>	144:ef7eb2e8f9f7	1849	if(I2C_MasterRequestWrite(hi2c, DevAddress, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1850	{
<>	144:ef7eb2e8f9f7	1851	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	1852	{
<>	144:ef7eb2e8f9f7	1853	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1854	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1855	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1856	}
<>	144:ef7eb2e8f9f7	1857	else
<>	144:ef7eb2e8f9f7	1858	{
<>	144:ef7eb2e8f9f7	1859	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1860	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1861	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1862	}
<>	144:ef7eb2e8f9f7	1863	}
<>	144:ef7eb2e8f9f7	1864
<>	144:ef7eb2e8f9f7	1865	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	1866	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	1867
<>	144:ef7eb2e8f9f7	1868	/* Enable ERR interrupt */
<>	144:ef7eb2e8f9f7	1869	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	1870
<>	144:ef7eb2e8f9f7	1871	/* Enable DMA Request */
<>	144:ef7eb2e8f9f7	1872	hi2c->Instance->CR2 \|= I2C_CR2_DMAEN;
<>	144:ef7eb2e8f9f7	1873	}
<>	144:ef7eb2e8f9f7	1874	else
<>	144:ef7eb2e8f9f7	1875	{
<>	144:ef7eb2e8f9f7	1876	/* Send Slave Address */
<>	144:ef7eb2e8f9f7	1877	if(I2C_MasterRequestWrite(hi2c, DevAddress, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1878	{
<>	144:ef7eb2e8f9f7	1879	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	1880	{
<>	144:ef7eb2e8f9f7	1881	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1882	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1883	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1884	}
<>	144:ef7eb2e8f9f7	1885	else
<>	144:ef7eb2e8f9f7	1886	{
<>	144:ef7eb2e8f9f7	1887	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1888	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1889	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1890	}
<>	144:ef7eb2e8f9f7	1891	}
<>	144:ef7eb2e8f9f7	1892
<>	144:ef7eb2e8f9f7	1893	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	1894	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	1895
<>	144:ef7eb2e8f9f7	1896	/* Generate Stop */
<>	144:ef7eb2e8f9f7	1897	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	1898
<>	144:ef7eb2e8f9f7	1899	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1900	}
<>	144:ef7eb2e8f9f7	1901
<>	144:ef7eb2e8f9f7	1902	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1903	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1904
<>	144:ef7eb2e8f9f7	1905	return HAL_OK;
<>	144:ef7eb2e8f9f7	1906	}
<>	144:ef7eb2e8f9f7	1907	else
<>	144:ef7eb2e8f9f7	1908	{
<>	144:ef7eb2e8f9f7	1909	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1910	}
<>	144:ef7eb2e8f9f7	1911	}
<>	144:ef7eb2e8f9f7	1912
<>	144:ef7eb2e8f9f7	1913	/**
<>	144:ef7eb2e8f9f7	1914	* @brief Receive in master mode an amount of data in no-blocking mode with DMA
<>	144:ef7eb2e8f9f7	1915	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1916	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	1917	* @param DevAddress Target device address: The device 7 bits address value
<>	144:ef7eb2e8f9f7	1918	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	1919	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1920	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1921	* @retval HAL status
<>	144:ef7eb2e8f9f7	1922	*/
<>	144:ef7eb2e8f9f7	1923	HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1924	{
<>	144:ef7eb2e8f9f7	1925	uint32_t tickstart = 0x00U;
<>	144:ef7eb2e8f9f7	1926
<>	144:ef7eb2e8f9f7	1927	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	1928
<>	144:ef7eb2e8f9f7	1929	/* Init tickstart for timeout management*/
<>	144:ef7eb2e8f9f7	1930	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1931
<>	144:ef7eb2e8f9f7	1932	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1933	{
<>	144:ef7eb2e8f9f7	1934	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	1935	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	1936	do
<>	144:ef7eb2e8f9f7	1937	{
<>	144:ef7eb2e8f9f7	1938	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	1939	{
<>	144:ef7eb2e8f9f7	1940	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	1941	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1942
<>	144:ef7eb2e8f9f7	1943	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1944	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1945
<>	144:ef7eb2e8f9f7	1946	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1947	}
<>	144:ef7eb2e8f9f7	1948	}
<>	144:ef7eb2e8f9f7	1949	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	1950
<>	144:ef7eb2e8f9f7	1951	/* Process Locked */
<>	144:ef7eb2e8f9f7	1952	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1953
<>	144:ef7eb2e8f9f7	1954	/* Disable Pos */
<>	144:ef7eb2e8f9f7	1955	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	1956
<>	144:ef7eb2e8f9f7	1957	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	1958	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	144:ef7eb2e8f9f7	1959	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1960
<>	144:ef7eb2e8f9f7	1961	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1962	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	1963	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1964	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	1965
<>	144:ef7eb2e8f9f7	1966	if(hi2c->XferSize > 0U)
<>	144:ef7eb2e8f9f7	1967	{
<>	144:ef7eb2e8f9f7	1968	/* Set the I2C DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	1969	hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
<>	144:ef7eb2e8f9f7	1970
<>	144:ef7eb2e8f9f7	1971	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1972	hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
<>	144:ef7eb2e8f9f7	1973
<>	144:ef7eb2e8f9f7	1974	/* Set the unused DMA callbacks to NULL */
<>	144:ef7eb2e8f9f7	1975	hi2c->hdmarx->XferHalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	1976	hi2c->hdmarx->XferM1CpltCallback = NULL;
<>	144:ef7eb2e8f9f7	1977	hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	1978	hi2c->hdmarx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	1979
<>	144:ef7eb2e8f9f7	1980	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	1981	HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size);
<>	144:ef7eb2e8f9f7	1982
<>	144:ef7eb2e8f9f7	1983	/* Send Slave Address */
<>	144:ef7eb2e8f9f7	1984	if(I2C_MasterRequestRead(hi2c, DevAddress, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1985	{
<>	144:ef7eb2e8f9f7	1986	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	1987	{
<>	144:ef7eb2e8f9f7	1988	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1989	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1990	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1991	}
<>	144:ef7eb2e8f9f7	1992	else
<>	144:ef7eb2e8f9f7	1993	{
<>	144:ef7eb2e8f9f7	1994	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1995	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1996	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1997	}
<>	144:ef7eb2e8f9f7	1998	}
<>	144:ef7eb2e8f9f7	1999
<>	144:ef7eb2e8f9f7	2000	if(Size == 1U)
<>	144:ef7eb2e8f9f7	2001	{
<>	144:ef7eb2e8f9f7	2002	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	2003	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	2004	}
<>	144:ef7eb2e8f9f7	2005	else
<>	144:ef7eb2e8f9f7	2006	{
<>	144:ef7eb2e8f9f7	2007	/* Enable Last DMA bit */
<>	144:ef7eb2e8f9f7	2008	hi2c->Instance->CR2 \|= I2C_CR2_LAST;
<>	144:ef7eb2e8f9f7	2009	}
<>	144:ef7eb2e8f9f7	2010
<>	144:ef7eb2e8f9f7	2011	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	2012	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	2013
<>	144:ef7eb2e8f9f7	2014	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2015	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2016
<>	144:ef7eb2e8f9f7	2017	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	2018	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	2019	process unlock */
<>	144:ef7eb2e8f9f7	2020	/* Enable ERR interrupt */
<>	144:ef7eb2e8f9f7	2021	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	2022
<>	144:ef7eb2e8f9f7	2023	/* Enable DMA Request */
<>	144:ef7eb2e8f9f7	2024	hi2c->Instance->CR2 \|= I2C_CR2_DMAEN;
<>	144:ef7eb2e8f9f7	2025	}
<>	144:ef7eb2e8f9f7	2026	else
<>	144:ef7eb2e8f9f7	2027	{
<>	144:ef7eb2e8f9f7	2028	/* Send Slave Address */
<>	144:ef7eb2e8f9f7	2029	if(I2C_MasterRequestRead(hi2c, DevAddress, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2030	{
<>	144:ef7eb2e8f9f7	2031	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	2032	{
<>	144:ef7eb2e8f9f7	2033	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2034	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2035	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2036	}
<>	144:ef7eb2e8f9f7	2037	else
<>	144:ef7eb2e8f9f7	2038	{
<>	144:ef7eb2e8f9f7	2039	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2040	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2041	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2042	}
<>	144:ef7eb2e8f9f7	2043	}
<>	144:ef7eb2e8f9f7	2044
<>	144:ef7eb2e8f9f7	2045	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	2046	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	2047
<>	144:ef7eb2e8f9f7	2048	/* Generate Stop */
<>	144:ef7eb2e8f9f7	2049	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	2050
<>	144:ef7eb2e8f9f7	2051	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2052
<>	144:ef7eb2e8f9f7	2053	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2054	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2055	}
<>	144:ef7eb2e8f9f7	2056
<>	144:ef7eb2e8f9f7	2057	return HAL_OK;
<>	144:ef7eb2e8f9f7	2058	}
<>	144:ef7eb2e8f9f7	2059	else
<>	144:ef7eb2e8f9f7	2060	{
<>	144:ef7eb2e8f9f7	2061	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2062	}
<>	144:ef7eb2e8f9f7	2063	}
<>	144:ef7eb2e8f9f7	2064
<>	144:ef7eb2e8f9f7	2065	/**
<>	144:ef7eb2e8f9f7	2066	* @brief Abort a master I2C process communication with Interrupt.
<>	144:ef7eb2e8f9f7	2067	* @note This abort can be called only if state is ready
<>	144:ef7eb2e8f9f7	2068	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2069	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2070	* @param DevAddress Target device address: The device 7 bits address value
<>	144:ef7eb2e8f9f7	2071	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	2072	* @retval HAL status
<>	144:ef7eb2e8f9f7	2073	*/
<>	144:ef7eb2e8f9f7	2074	HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
<>	144:ef7eb2e8f9f7	2075	{
<>	144:ef7eb2e8f9f7	2076	/* Abort Master transfer during Receive or Transmit process */
<>	144:ef7eb2e8f9f7	2077	if(hi2c->Mode == HAL_I2C_MODE_MASTER)
<>	144:ef7eb2e8f9f7	2078	{
<>	144:ef7eb2e8f9f7	2079	/* Process Locked */
<>	144:ef7eb2e8f9f7	2080	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2081
<>	144:ef7eb2e8f9f7	2082	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	2083	hi2c->State = HAL_I2C_STATE_ABORT;
<>	144:ef7eb2e8f9f7	2084
<>	144:ef7eb2e8f9f7	2085	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	2086	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	2087
<>	144:ef7eb2e8f9f7	2088	/* Generate Stop */
<>	144:ef7eb2e8f9f7	2089	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	2090
<>	144:ef7eb2e8f9f7	2091	hi2c->XferCount = 0U;
<>	144:ef7eb2e8f9f7	2092
<>	144:ef7eb2e8f9f7	2093	/* Disable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	2094	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	2095
<>	144:ef7eb2e8f9f7	2096	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2097	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2098
<>	144:ef7eb2e8f9f7	2099	if(hi2c->State == HAL_I2C_STATE_ABORT)
<>	144:ef7eb2e8f9f7	2100	{
<>	144:ef7eb2e8f9f7	2101	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2102
<>	144:ef7eb2e8f9f7	2103	/* Call the Abort Complete callback */
<>	144:ef7eb2e8f9f7	2104	HAL_I2C_AbortCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	2105	}
<>	144:ef7eb2e8f9f7	2106
<>	144:ef7eb2e8f9f7	2107	return HAL_OK;
<>	144:ef7eb2e8f9f7	2108	}
<>	144:ef7eb2e8f9f7	2109	else
<>	144:ef7eb2e8f9f7	2110	{
<>	144:ef7eb2e8f9f7	2111	/* Wrong usage of abort function */
<>	144:ef7eb2e8f9f7	2112	/* This function should be used only in case of abort monitored by master device */
<>	144:ef7eb2e8f9f7	2113	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2114	}
<>	144:ef7eb2e8f9f7	2115	}
<>	144:ef7eb2e8f9f7	2116
<>	144:ef7eb2e8f9f7	2117	/**
<>	144:ef7eb2e8f9f7	2118	* @brief Transmit in slave mode an amount of data in no-blocking mode with DMA
<>	144:ef7eb2e8f9f7	2119	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2120	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	2121	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	2122	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	2123	* @retval HAL status
<>	144:ef7eb2e8f9f7	2124	*/
<>	144:ef7eb2e8f9f7	2125	HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	2126	{
<>	144:ef7eb2e8f9f7	2127	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	2128
<>	144:ef7eb2e8f9f7	2129	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2130	{
<>	144:ef7eb2e8f9f7	2131	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	2132	{
<>	144:ef7eb2e8f9f7	2133	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2134	}
<>	144:ef7eb2e8f9f7	2135
<>	144:ef7eb2e8f9f7	2136	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	2137	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	2138	do
<>	144:ef7eb2e8f9f7	2139	{
<>	144:ef7eb2e8f9f7	2140	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	2141	{
<>	144:ef7eb2e8f9f7	2142	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	2143	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2144
<>	144:ef7eb2e8f9f7	2145	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2146	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2147
<>	144:ef7eb2e8f9f7	2148	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2149	}
<>	144:ef7eb2e8f9f7	2150	}
<>	144:ef7eb2e8f9f7	2151	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	2152
<>	144:ef7eb2e8f9f7	2153	/* Process Locked */
<>	144:ef7eb2e8f9f7	2154	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2155
<>	144:ef7eb2e8f9f7	2156	/* Disable Pos */
<>	144:ef7eb2e8f9f7	2157	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	2158
<>	144:ef7eb2e8f9f7	2159	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	2160	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	144:ef7eb2e8f9f7	2161	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2162
<>	144:ef7eb2e8f9f7	2163	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	2164	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	2165	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	2166	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	2167
<>	144:ef7eb2e8f9f7	2168	/* Set the I2C DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	2169	hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
<>	144:ef7eb2e8f9f7	2170
<>	144:ef7eb2e8f9f7	2171	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	2172	hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
<>	144:ef7eb2e8f9f7	2173
<>	144:ef7eb2e8f9f7	2174	/* Set the unused DMA callbacks to NULL */
<>	144:ef7eb2e8f9f7	2175	hi2c->hdmatx->XferHalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	2176	hi2c->hdmatx->XferM1CpltCallback = NULL;
<>	144:ef7eb2e8f9f7	2177	hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	2178	hi2c->hdmatx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	2179
<>	144:ef7eb2e8f9f7	2180	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	2181	HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size);
<>	144:ef7eb2e8f9f7	2182
<>	144:ef7eb2e8f9f7	2183	/* Enable ERR interrupt */
<>	144:ef7eb2e8f9f7	2184	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	2185
<>	144:ef7eb2e8f9f7	2186	/* Enable DMA Request */
<>	144:ef7eb2e8f9f7	2187	hi2c->Instance->CR2 \|= I2C_CR2_DMAEN;
<>	144:ef7eb2e8f9f7	2188
<>	144:ef7eb2e8f9f7	2189	/* Enable Address Acknowledge */
<>	144:ef7eb2e8f9f7	2190	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	2191
<>	144:ef7eb2e8f9f7	2192	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	2193	count = I2C_TIMEOUT_ADDR_SLAVE * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	2194	do
<>	144:ef7eb2e8f9f7	2195	{
<>	144:ef7eb2e8f9f7	2196	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	2197	{
<>	144:ef7eb2e8f9f7	2198	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	2199	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2200
<>	144:ef7eb2e8f9f7	2201	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2202	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2203
<>	144:ef7eb2e8f9f7	2204	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2205	}
<>	144:ef7eb2e8f9f7	2206	}
<>	144:ef7eb2e8f9f7	2207	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == RESET);
<>	144:ef7eb2e8f9f7	2208
<>	144:ef7eb2e8f9f7	2209	/* If 7bit addressing mode is selected */
<>	144:ef7eb2e8f9f7	2210	if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
<>	144:ef7eb2e8f9f7	2211	{
<>	144:ef7eb2e8f9f7	2212	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	2213	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	2214	}
<>	144:ef7eb2e8f9f7	2215	else
<>	144:ef7eb2e8f9f7	2216	{
<>	144:ef7eb2e8f9f7	2217	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	2218	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	2219
<>	144:ef7eb2e8f9f7	2220	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	2221	count = I2C_TIMEOUT_ADDR_SLAVE * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	2222	do
<>	144:ef7eb2e8f9f7	2223	{
<>	144:ef7eb2e8f9f7	2224	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	2225	{
<>	144:ef7eb2e8f9f7	2226	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	2227	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2228
<>	144:ef7eb2e8f9f7	2229	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2230	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2231
<>	144:ef7eb2e8f9f7	2232	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2233	}
<>	144:ef7eb2e8f9f7	2234	}
<>	144:ef7eb2e8f9f7	2235	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == RESET);
<>	144:ef7eb2e8f9f7	2236
<>	144:ef7eb2e8f9f7	2237	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	2238	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	2239	}
<>	144:ef7eb2e8f9f7	2240
<>	144:ef7eb2e8f9f7	2241	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2242	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2243
<>	144:ef7eb2e8f9f7	2244	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	2245	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	2246	process unlock */
<>	144:ef7eb2e8f9f7	2247	/* Enable ERR interrupt */
<>	144:ef7eb2e8f9f7	2248	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	2249
<>	144:ef7eb2e8f9f7	2250	return HAL_OK;
<>	144:ef7eb2e8f9f7	2251	}
<>	144:ef7eb2e8f9f7	2252	else
<>	144:ef7eb2e8f9f7	2253	{
<>	144:ef7eb2e8f9f7	2254	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2255	}
<>	144:ef7eb2e8f9f7	2256	}
<>	144:ef7eb2e8f9f7	2257
<>	144:ef7eb2e8f9f7	2258	/**
<>	144:ef7eb2e8f9f7	2259	* @brief Receive in slave mode an amount of data in no-blocking mode with DMA
<>	144:ef7eb2e8f9f7	2260	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2261	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	2262	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	2263	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	2264	* @retval HAL status
<>	144:ef7eb2e8f9f7	2265	*/
<>	144:ef7eb2e8f9f7	2266	HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	2267	{
<>	144:ef7eb2e8f9f7	2268	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	2269
<>	144:ef7eb2e8f9f7	2270	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2271	{
<>	144:ef7eb2e8f9f7	2272	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	2273	{
<>	144:ef7eb2e8f9f7	2274	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2275	}
<>	144:ef7eb2e8f9f7	2276
<>	144:ef7eb2e8f9f7	2277	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	2278	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	2279	do
<>	144:ef7eb2e8f9f7	2280	{
<>	144:ef7eb2e8f9f7	2281	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	2282	{
<>	144:ef7eb2e8f9f7	2283	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	2284	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2285
<>	144:ef7eb2e8f9f7	2286	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2287	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2288
<>	144:ef7eb2e8f9f7	2289	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2290	}
<>	144:ef7eb2e8f9f7	2291	}
<>	144:ef7eb2e8f9f7	2292	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	2293
<>	144:ef7eb2e8f9f7	2294	/* Process Locked */
<>	144:ef7eb2e8f9f7	2295	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2296
<>	144:ef7eb2e8f9f7	2297	/* Disable Pos */
<>	144:ef7eb2e8f9f7	2298	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	2299
<>	144:ef7eb2e8f9f7	2300	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	2301	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	144:ef7eb2e8f9f7	2302	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2303
<>	144:ef7eb2e8f9f7	2304	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	2305	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	2306	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	2307	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	2308
<>	144:ef7eb2e8f9f7	2309	/* Set the I2C DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	2310	hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
<>	144:ef7eb2e8f9f7	2311
<>	144:ef7eb2e8f9f7	2312	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	2313	hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
<>	144:ef7eb2e8f9f7	2314
<>	144:ef7eb2e8f9f7	2315	/* Set the unused DMA callbacks to NULL */
<>	144:ef7eb2e8f9f7	2316	hi2c->hdmarx->XferHalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	2317	hi2c->hdmarx->XferM1CpltCallback = NULL;
<>	144:ef7eb2e8f9f7	2318	hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	2319	hi2c->hdmarx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	2320
<>	144:ef7eb2e8f9f7	2321	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	2322	HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size);
<>	144:ef7eb2e8f9f7	2323
<>	144:ef7eb2e8f9f7	2324	/* Enable ERR interrupt */
<>	144:ef7eb2e8f9f7	2325	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	2326
<>	144:ef7eb2e8f9f7	2327	/* Enable DMA Request */
<>	144:ef7eb2e8f9f7	2328	hi2c->Instance->CR2 \|= I2C_CR2_DMAEN;
<>	144:ef7eb2e8f9f7	2329
<>	144:ef7eb2e8f9f7	2330	/* Enable Address Acknowledge */
<>	144:ef7eb2e8f9f7	2331	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	2332
<>	144:ef7eb2e8f9f7	2333	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	2334	count = I2C_TIMEOUT_ADDR_SLAVE * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	2335	do
<>	144:ef7eb2e8f9f7	2336	{
<>	144:ef7eb2e8f9f7	2337	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	2338	{
<>	144:ef7eb2e8f9f7	2339	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	2340	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2341
<>	144:ef7eb2e8f9f7	2342	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2343	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2344
<>	144:ef7eb2e8f9f7	2345	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2346	}
<>	144:ef7eb2e8f9f7	2347	}
<>	144:ef7eb2e8f9f7	2348	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == RESET);
<>	144:ef7eb2e8f9f7	2349
<>	144:ef7eb2e8f9f7	2350	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	2351	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	2352
<>	144:ef7eb2e8f9f7	2353	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2354	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2355
<>	144:ef7eb2e8f9f7	2356	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	2357	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	2358	process unlock */
<>	144:ef7eb2e8f9f7	2359	/* Enable ERR interrupt */
<>	144:ef7eb2e8f9f7	2360	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	2361
<>	144:ef7eb2e8f9f7	2362	return HAL_OK;
<>	144:ef7eb2e8f9f7	2363	}
<>	144:ef7eb2e8f9f7	2364	else
<>	144:ef7eb2e8f9f7	2365	{
<>	144:ef7eb2e8f9f7	2366	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2367	}
<>	144:ef7eb2e8f9f7	2368	}
<>	144:ef7eb2e8f9f7	2369	/**
<>	144:ef7eb2e8f9f7	2370	* @brief Write an amount of data in blocking mode to a specific memory address
<>	144:ef7eb2e8f9f7	2371	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2372	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	2373	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	2374	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	2375	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	2376	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	2377	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	2378	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	2379	* @retval HAL status
<>	144:ef7eb2e8f9f7	2380	*/
<>	144:ef7eb2e8f9f7	2381	HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	2382	{
<>	144:ef7eb2e8f9f7	2383	uint32_t tickstart = 0x00U;
<>	144:ef7eb2e8f9f7	2384
<>	144:ef7eb2e8f9f7	2385	/* Init tickstart for timeout management*/
<>	144:ef7eb2e8f9f7	2386	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	2387
<>	144:ef7eb2e8f9f7	2388	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2389	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<>	144:ef7eb2e8f9f7	2390
<>	144:ef7eb2e8f9f7	2391	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2392	{
<>	144:ef7eb2e8f9f7	2393	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	2394	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2395	{
<>	144:ef7eb2e8f9f7	2396	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2397	}
<>	144:ef7eb2e8f9f7	2398
<>	144:ef7eb2e8f9f7	2399	/* Process Locked */
<>	144:ef7eb2e8f9f7	2400	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2401
<>	144:ef7eb2e8f9f7	2402	/* Disable Pos */
<>	144:ef7eb2e8f9f7	2403	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	2404
<>	144:ef7eb2e8f9f7	2405	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	2406	hi2c->Mode = HAL_I2C_MODE_MEM;
<>	144:ef7eb2e8f9f7	2407	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2408	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	2409
<>	144:ef7eb2e8f9f7	2410	/* Send Slave Address and Memory Address */
<>	144:ef7eb2e8f9f7	2411	if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2412	{
<>	144:ef7eb2e8f9f7	2413	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	2414	{
<>	144:ef7eb2e8f9f7	2415	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2416	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2417	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2418	}
<>	144:ef7eb2e8f9f7	2419	else
<>	144:ef7eb2e8f9f7	2420	{
<>	144:ef7eb2e8f9f7	2421	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2422	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2423	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2424	}
<>	144:ef7eb2e8f9f7	2425	}
<>	144:ef7eb2e8f9f7	2426
<>	144:ef7eb2e8f9f7	2427	while(Size > 0U)
<>	144:ef7eb2e8f9f7	2428	{
<>	144:ef7eb2e8f9f7	2429	/* Wait until TXE flag is set */
<>	144:ef7eb2e8f9f7	2430	if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2431	{
<>	144:ef7eb2e8f9f7	2432	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	2433	{
<>	144:ef7eb2e8f9f7	2434	/* Generate Stop */
<>	144:ef7eb2e8f9f7	2435	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	2436	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2437	}
<>	144:ef7eb2e8f9f7	2438	else
<>	144:ef7eb2e8f9f7	2439	{
<>	144:ef7eb2e8f9f7	2440	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2441	}
<>	144:ef7eb2e8f9f7	2442	}
<>	144:ef7eb2e8f9f7	2443
<>	144:ef7eb2e8f9f7	2444	/* Write data to DR */
<>	144:ef7eb2e8f9f7	2445	hi2c->Instance->DR = (*pData++);
<>	144:ef7eb2e8f9f7	2446	Size--;
<>	144:ef7eb2e8f9f7	2447
<>	144:ef7eb2e8f9f7	2448	if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0))
<>	144:ef7eb2e8f9f7	2449	{
<>	144:ef7eb2e8f9f7	2450	/* Write data to DR */
<>	144:ef7eb2e8f9f7	2451	hi2c->Instance->DR = (*pData++);
<>	144:ef7eb2e8f9f7	2452	Size--;
<>	144:ef7eb2e8f9f7	2453	}
<>	144:ef7eb2e8f9f7	2454	}
<>	144:ef7eb2e8f9f7	2455
<>	144:ef7eb2e8f9f7	2456	/* Wait until BTF flag is set */
<>	144:ef7eb2e8f9f7	2457	if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2458	{
<>	144:ef7eb2e8f9f7	2459	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	2460	{
<>	144:ef7eb2e8f9f7	2461	/* Generate Stop */
<>	144:ef7eb2e8f9f7	2462	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	2463	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2464	}
<>	144:ef7eb2e8f9f7	2465	else
<>	144:ef7eb2e8f9f7	2466	{
<>	144:ef7eb2e8f9f7	2467	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2468	}
<>	144:ef7eb2e8f9f7	2469	}
<>	144:ef7eb2e8f9f7	2470
<>	144:ef7eb2e8f9f7	2471	/* Generate Stop */
<>	144:ef7eb2e8f9f7	2472	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	2473
<>	144:ef7eb2e8f9f7	2474	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2475	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	2476
<>	144:ef7eb2e8f9f7	2477	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2478	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2479
<>	144:ef7eb2e8f9f7	2480	return HAL_OK;
<>	144:ef7eb2e8f9f7	2481	}
<>	144:ef7eb2e8f9f7	2482	else
<>	144:ef7eb2e8f9f7	2483	{
<>	144:ef7eb2e8f9f7	2484	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2485	}
<>	144:ef7eb2e8f9f7	2486	}
<>	144:ef7eb2e8f9f7	2487
<>	144:ef7eb2e8f9f7	2488	/**
<>	144:ef7eb2e8f9f7	2489	* @brief Read an amount of data in blocking mode from a specific memory address
<>	144:ef7eb2e8f9f7	2490	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2491	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	2492	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	2493	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	2494	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	2495	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	2496	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	2497	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	2498	* @retval HAL status
<>	144:ef7eb2e8f9f7	2499	*/
<>	144:ef7eb2e8f9f7	2500	HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	2501	{
<>	144:ef7eb2e8f9f7	2502	uint32_t tickstart = 0x00U;
<>	144:ef7eb2e8f9f7	2503
<>	144:ef7eb2e8f9f7	2504	/* Init tickstart for timeout management*/
<>	144:ef7eb2e8f9f7	2505	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	2506
<>	144:ef7eb2e8f9f7	2507	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2508	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<>	144:ef7eb2e8f9f7	2509
<>	144:ef7eb2e8f9f7	2510	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2511	{
<>	144:ef7eb2e8f9f7	2512	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	2513	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2514	{
<>	144:ef7eb2e8f9f7	2515	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2516	}
<>	144:ef7eb2e8f9f7	2517
<>	144:ef7eb2e8f9f7	2518	/* Process Locked */
<>	144:ef7eb2e8f9f7	2519	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2520
<>	144:ef7eb2e8f9f7	2521	/* Disable Pos */
<>	144:ef7eb2e8f9f7	2522	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	2523
<>	144:ef7eb2e8f9f7	2524	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	2525	hi2c->Mode = HAL_I2C_MODE_MEM;
<>	144:ef7eb2e8f9f7	2526	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2527	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	2528
<>	144:ef7eb2e8f9f7	2529	/* Send Slave Address and Memory Address */
<>	144:ef7eb2e8f9f7	2530	if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2531	{
<>	144:ef7eb2e8f9f7	2532	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	2533	{
<>	144:ef7eb2e8f9f7	2534	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2535	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2536	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2537	}
<>	144:ef7eb2e8f9f7	2538	else
<>	144:ef7eb2e8f9f7	2539	{
<>	144:ef7eb2e8f9f7	2540	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2541	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2542	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2543	}
<>	144:ef7eb2e8f9f7	2544	}
<>	144:ef7eb2e8f9f7	2545
<>	144:ef7eb2e8f9f7	2546	if(Size == 0U)
<>	144:ef7eb2e8f9f7	2547	{
<>	144:ef7eb2e8f9f7	2548	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	2549	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	2550
<>	144:ef7eb2e8f9f7	2551	/* Generate Stop */
<>	144:ef7eb2e8f9f7	2552	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	2553	}
<>	144:ef7eb2e8f9f7	2554	else if(Size == 1U)
<>	144:ef7eb2e8f9f7	2555	{
<>	144:ef7eb2e8f9f7	2556	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	2557	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	2558
<>	144:ef7eb2e8f9f7	2559	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	2560	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	2561
<>	144:ef7eb2e8f9f7	2562	/* Generate Stop */
<>	144:ef7eb2e8f9f7	2563	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	2564	}
<>	144:ef7eb2e8f9f7	2565	else if(Size == 2U)
<>	144:ef7eb2e8f9f7	2566	{
<>	144:ef7eb2e8f9f7	2567	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	2568	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	2569
<>	144:ef7eb2e8f9f7	2570	/* Enable Pos */
<>	144:ef7eb2e8f9f7	2571	hi2c->Instance->CR1 \|= I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	2572
<>	144:ef7eb2e8f9f7	2573	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	2574	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	2575	}
<>	144:ef7eb2e8f9f7	2576	else
<>	144:ef7eb2e8f9f7	2577	{
<>	144:ef7eb2e8f9f7	2578	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	2579	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	2580	}
<>	144:ef7eb2e8f9f7	2581
<>	144:ef7eb2e8f9f7	2582	while(Size > 0U)
<>	144:ef7eb2e8f9f7	2583	{
<>	144:ef7eb2e8f9f7	2584	if(Size <= 3U)
<>	144:ef7eb2e8f9f7	2585	{
<>	144:ef7eb2e8f9f7	2586	/* One byte */
<>	144:ef7eb2e8f9f7	2587	if(Size== 1U)
<>	144:ef7eb2e8f9f7	2588	{
<>	144:ef7eb2e8f9f7	2589	/* Wait until RXNE flag is set */
<>	144:ef7eb2e8f9f7	2590	if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2591	{
<>	144:ef7eb2e8f9f7	2592	if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
<>	144:ef7eb2e8f9f7	2593	{
<>	144:ef7eb2e8f9f7	2594	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2595	}
<>	144:ef7eb2e8f9f7	2596	else
<>	144:ef7eb2e8f9f7	2597	{
<>	144:ef7eb2e8f9f7	2598	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2599	}
<>	144:ef7eb2e8f9f7	2600	}
<>	144:ef7eb2e8f9f7	2601
<>	144:ef7eb2e8f9f7	2602	/* Read data from DR */
<>	144:ef7eb2e8f9f7	2603	(*pData++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	2604	Size--;
<>	144:ef7eb2e8f9f7	2605	}
<>	144:ef7eb2e8f9f7	2606	/* Two bytes */
<>	144:ef7eb2e8f9f7	2607	else if(Size == 2U)
<>	144:ef7eb2e8f9f7	2608	{
<>	144:ef7eb2e8f9f7	2609	/* Wait until BTF flag is set */
<>	144:ef7eb2e8f9f7	2610	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2611	{
<>	144:ef7eb2e8f9f7	2612	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2613	}
<>	144:ef7eb2e8f9f7	2614
<>	144:ef7eb2e8f9f7	2615	/* Generate Stop */
<>	144:ef7eb2e8f9f7	2616	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	2617
<>	144:ef7eb2e8f9f7	2618	/* Read data from DR */
<>	144:ef7eb2e8f9f7	2619	(*pData++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	2620	Size--;
<>	144:ef7eb2e8f9f7	2621
<>	144:ef7eb2e8f9f7	2622	/* Read data from DR */
<>	144:ef7eb2e8f9f7	2623	(*pData++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	2624	Size--;
<>	144:ef7eb2e8f9f7	2625	}
<>	144:ef7eb2e8f9f7	2626	/* 3 Last bytes */
<>	144:ef7eb2e8f9f7	2627	else
<>	144:ef7eb2e8f9f7	2628	{
<>	144:ef7eb2e8f9f7	2629	/* Wait until BTF flag is set */
<>	144:ef7eb2e8f9f7	2630	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2631	{
<>	144:ef7eb2e8f9f7	2632	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2633	}
<>	144:ef7eb2e8f9f7	2634
<>	144:ef7eb2e8f9f7	2635	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	2636	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	2637
<>	144:ef7eb2e8f9f7	2638	/* Read data from DR */
<>	144:ef7eb2e8f9f7	2639	(*pData++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	2640	Size--;
<>	144:ef7eb2e8f9f7	2641
<>	144:ef7eb2e8f9f7	2642	/* Wait until BTF flag is set */
<>	144:ef7eb2e8f9f7	2643	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2644	{
<>	144:ef7eb2e8f9f7	2645	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2646	}
<>	144:ef7eb2e8f9f7	2647
<>	144:ef7eb2e8f9f7	2648	/* Generate Stop */
<>	144:ef7eb2e8f9f7	2649	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	2650
<>	144:ef7eb2e8f9f7	2651	/* Read data from DR */
<>	144:ef7eb2e8f9f7	2652	(*pData++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	2653	Size--;
<>	144:ef7eb2e8f9f7	2654
<>	144:ef7eb2e8f9f7	2655	/* Read data from DR */
<>	144:ef7eb2e8f9f7	2656	(*pData++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	2657	Size--;
<>	144:ef7eb2e8f9f7	2658	}
<>	144:ef7eb2e8f9f7	2659	}
<>	144:ef7eb2e8f9f7	2660	else
<>	144:ef7eb2e8f9f7	2661	{
<>	144:ef7eb2e8f9f7	2662	/* Wait until RXNE flag is set */
<>	144:ef7eb2e8f9f7	2663	if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2664	{
<>	144:ef7eb2e8f9f7	2665	if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
<>	144:ef7eb2e8f9f7	2666	{
<>	144:ef7eb2e8f9f7	2667	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2668	}
<>	144:ef7eb2e8f9f7	2669	else
<>	144:ef7eb2e8f9f7	2670	{
<>	144:ef7eb2e8f9f7	2671	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2672	}
<>	144:ef7eb2e8f9f7	2673	}
<>	144:ef7eb2e8f9f7	2674
<>	144:ef7eb2e8f9f7	2675	/* Read data from DR */
<>	144:ef7eb2e8f9f7	2676	(*pData++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	2677	Size--;
<>	144:ef7eb2e8f9f7	2678
<>	144:ef7eb2e8f9f7	2679	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
<>	144:ef7eb2e8f9f7	2680	{
<>	144:ef7eb2e8f9f7	2681	/* Read data from DR */
<>	144:ef7eb2e8f9f7	2682	(*pData++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	2683	Size--;
<>	144:ef7eb2e8f9f7	2684	}
<>	144:ef7eb2e8f9f7	2685	}
<>	144:ef7eb2e8f9f7	2686	}
<>	144:ef7eb2e8f9f7	2687
<>	144:ef7eb2e8f9f7	2688	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2689	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	2690
<>	144:ef7eb2e8f9f7	2691	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2692	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2693
<>	144:ef7eb2e8f9f7	2694	return HAL_OK;
<>	144:ef7eb2e8f9f7	2695	}
<>	144:ef7eb2e8f9f7	2696	else
<>	144:ef7eb2e8f9f7	2697	{
<>	144:ef7eb2e8f9f7	2698	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2699	}
<>	144:ef7eb2e8f9f7	2700	}
<>	144:ef7eb2e8f9f7	2701
<>	144:ef7eb2e8f9f7	2702	/**
<>	144:ef7eb2e8f9f7	2703	* @brief Write an amount of data in no-blocking mode with Interrupt to a specific memory address
<>	144:ef7eb2e8f9f7	2704	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2705	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	2706	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	2707	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	2708	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	2709	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	2710	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	2711	* @retval HAL status
<>	144:ef7eb2e8f9f7	2712	*/
<>	144:ef7eb2e8f9f7	2713	HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	2714	{
<>	144:ef7eb2e8f9f7	2715	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	2716
<>	144:ef7eb2e8f9f7	2717	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2718	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<>	144:ef7eb2e8f9f7	2719
<>	144:ef7eb2e8f9f7	2720	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2721	{
<>	144:ef7eb2e8f9f7	2722	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	2723	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	2724	do
<>	144:ef7eb2e8f9f7	2725	{
<>	144:ef7eb2e8f9f7	2726	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	2727	{
<>	144:ef7eb2e8f9f7	2728	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	2729	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2730
<>	144:ef7eb2e8f9f7	2731	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2732	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2733
<>	144:ef7eb2e8f9f7	2734	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2735	}
<>	144:ef7eb2e8f9f7	2736	}
<>	144:ef7eb2e8f9f7	2737	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	2738
<>	144:ef7eb2e8f9f7	2739	/* Process Locked */
<>	144:ef7eb2e8f9f7	2740	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2741
<>	144:ef7eb2e8f9f7	2742	/* Disable Pos */
<>	144:ef7eb2e8f9f7	2743	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	2744
<>	144:ef7eb2e8f9f7	2745	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	2746	hi2c->Mode = HAL_I2C_MODE_MEM;
<>	144:ef7eb2e8f9f7	2747	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2748
<>	144:ef7eb2e8f9f7	2749	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	2750	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	2751	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	2752	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	2753	hi2c->Devaddress = DevAddress;
<>	144:ef7eb2e8f9f7	2754	hi2c->Memaddress = MemAddress;
<>	144:ef7eb2e8f9f7	2755	hi2c->MemaddSize = MemAddSize;
<>	144:ef7eb2e8f9f7	2756	hi2c->EventCount = 0U;
<>	144:ef7eb2e8f9f7	2757
<>	144:ef7eb2e8f9f7	2758	/* Generate Start */
<>	144:ef7eb2e8f9f7	2759	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	2760
<>	144:ef7eb2e8f9f7	2761	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2762	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2763
<>	144:ef7eb2e8f9f7	2764	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	2765	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	2766	process unlock */
<>	144:ef7eb2e8f9f7	2767
<>	144:ef7eb2e8f9f7	2768	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	2769	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	2770
<>	144:ef7eb2e8f9f7	2771	return HAL_OK;
<>	144:ef7eb2e8f9f7	2772	}
<>	144:ef7eb2e8f9f7	2773	else
<>	144:ef7eb2e8f9f7	2774	{
<>	144:ef7eb2e8f9f7	2775	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2776	}
<>	144:ef7eb2e8f9f7	2777	}
<>	144:ef7eb2e8f9f7	2778
<>	144:ef7eb2e8f9f7	2779	/**
<>	144:ef7eb2e8f9f7	2780	* @brief Read an amount of data in no-blocking mode with Interrupt from a specific memory address
<>	144:ef7eb2e8f9f7	2781	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2782	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	2783	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	2784	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	2785	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	2786	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	2787	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	2788	* @retval HAL status
<>	144:ef7eb2e8f9f7	2789	*/
<>	144:ef7eb2e8f9f7	2790	HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	2791	{
<>	144:ef7eb2e8f9f7	2792	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	2793
<>	144:ef7eb2e8f9f7	2794	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2795	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<>	144:ef7eb2e8f9f7	2796
<>	144:ef7eb2e8f9f7	2797	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2798	{
<>	144:ef7eb2e8f9f7	2799	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	2800	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	2801	do
<>	144:ef7eb2e8f9f7	2802	{
<>	144:ef7eb2e8f9f7	2803	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	2804	{
<>	144:ef7eb2e8f9f7	2805	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	2806	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2807
<>	144:ef7eb2e8f9f7	2808	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2809	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2810
<>	144:ef7eb2e8f9f7	2811	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2812	}
<>	144:ef7eb2e8f9f7	2813	}
<>	144:ef7eb2e8f9f7	2814	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	2815
<>	144:ef7eb2e8f9f7	2816	/* Process Locked */
<>	144:ef7eb2e8f9f7	2817	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2818
<>	144:ef7eb2e8f9f7	2819	/* Disable Pos */
<>	144:ef7eb2e8f9f7	2820	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	2821
<>	144:ef7eb2e8f9f7	2822	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	2823	hi2c->Mode = HAL_I2C_MODE_MEM;
<>	144:ef7eb2e8f9f7	2824	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2825
<>	144:ef7eb2e8f9f7	2826	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	2827	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	2828	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	2829	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	2830	hi2c->Devaddress = DevAddress;
<>	144:ef7eb2e8f9f7	2831	hi2c->Memaddress = MemAddress;
<>	144:ef7eb2e8f9f7	2832	hi2c->MemaddSize = MemAddSize;
<>	144:ef7eb2e8f9f7	2833	hi2c->EventCount = 0U;
<>	144:ef7eb2e8f9f7	2834
<>	144:ef7eb2e8f9f7	2835	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	2836	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	2837
<>	144:ef7eb2e8f9f7	2838	/* Generate Start */
<>	144:ef7eb2e8f9f7	2839	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	2840
<>	144:ef7eb2e8f9f7	2841	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2842	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2843
<>	144:ef7eb2e8f9f7	2844	if(hi2c->XferSize > 0U)
<>	144:ef7eb2e8f9f7	2845	{
<>	144:ef7eb2e8f9f7	2846	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	2847	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	2848	process unlock */
<>	144:ef7eb2e8f9f7	2849
<>	144:ef7eb2e8f9f7	2850	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	2851	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	2852	}
<>	144:ef7eb2e8f9f7	2853	return HAL_OK;
<>	144:ef7eb2e8f9f7	2854	}
<>	144:ef7eb2e8f9f7	2855	else
<>	144:ef7eb2e8f9f7	2856	{
<>	144:ef7eb2e8f9f7	2857	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2858	}
<>	144:ef7eb2e8f9f7	2859	}
<>	144:ef7eb2e8f9f7	2860
<>	144:ef7eb2e8f9f7	2861	/**
<>	144:ef7eb2e8f9f7	2862	* @brief Write an amount of data in no-blocking mode with DMA to a specific memory address
<>	144:ef7eb2e8f9f7	2863	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2864	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	2865	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	2866	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	2867	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	2868	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	2869	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	2870	* @retval HAL status
<>	144:ef7eb2e8f9f7	2871	*/
<>	144:ef7eb2e8f9f7	2872	HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	2873	{
<>	144:ef7eb2e8f9f7	2874	uint32_t tickstart = 0x00U;
<>	144:ef7eb2e8f9f7	2875
<>	144:ef7eb2e8f9f7	2876	/* Init tickstart for timeout management*/
<>	144:ef7eb2e8f9f7	2877	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	2878
<>	144:ef7eb2e8f9f7	2879	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	2880
<>	144:ef7eb2e8f9f7	2881	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2882	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<>	144:ef7eb2e8f9f7	2883
<>	144:ef7eb2e8f9f7	2884	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2885	{
<>	144:ef7eb2e8f9f7	2886	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	2887	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	2888	do
<>	144:ef7eb2e8f9f7	2889	{
<>	144:ef7eb2e8f9f7	2890	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	2891	{
<>	144:ef7eb2e8f9f7	2892	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	2893	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2894
<>	144:ef7eb2e8f9f7	2895	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2896	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2897
<>	144:ef7eb2e8f9f7	2898	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2899	}
<>	144:ef7eb2e8f9f7	2900	}
<>	144:ef7eb2e8f9f7	2901	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	2902
<>	144:ef7eb2e8f9f7	2903	/* Process Locked */
<>	144:ef7eb2e8f9f7	2904	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2905
<>	144:ef7eb2e8f9f7	2906	/* Disable Pos */
<>	144:ef7eb2e8f9f7	2907	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	2908
<>	144:ef7eb2e8f9f7	2909	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	2910	hi2c->Mode = HAL_I2C_MODE_MEM;
<>	144:ef7eb2e8f9f7	2911	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2912
<>	144:ef7eb2e8f9f7	2913	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	2914	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	2915	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	2916	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	2917
<>	144:ef7eb2e8f9f7	2918	if(hi2c->XferSize > 0U)
<>	144:ef7eb2e8f9f7	2919	{
<>	144:ef7eb2e8f9f7	2920	/* Set the I2C DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	2921	hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
<>	144:ef7eb2e8f9f7	2922
<>	144:ef7eb2e8f9f7	2923	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	2924	hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
<>	144:ef7eb2e8f9f7	2925
<>	144:ef7eb2e8f9f7	2926	/* Set the unused DMA callbacks to NULL */
<>	144:ef7eb2e8f9f7	2927	hi2c->hdmatx->XferHalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	2928	hi2c->hdmatx->XferM1CpltCallback = NULL;
<>	144:ef7eb2e8f9f7	2929	hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	2930	hi2c->hdmatx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	2931
<>	144:ef7eb2e8f9f7	2932	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	2933	HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size);
<>	144:ef7eb2e8f9f7	2934
<>	144:ef7eb2e8f9f7	2935	/* Send Slave Address and Memory Address */
<>	144:ef7eb2e8f9f7	2936	if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2937	{
<>	144:ef7eb2e8f9f7	2938	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	2939	{
<>	144:ef7eb2e8f9f7	2940	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2941	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2942	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2943	}
<>	144:ef7eb2e8f9f7	2944	else
<>	144:ef7eb2e8f9f7	2945	{
<>	144:ef7eb2e8f9f7	2946	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2947	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2948	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2949	}
<>	144:ef7eb2e8f9f7	2950	}
<>	144:ef7eb2e8f9f7	2951
<>	144:ef7eb2e8f9f7	2952	/* Enable ERR interrupt */
<>	144:ef7eb2e8f9f7	2953	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	2954
<>	144:ef7eb2e8f9f7	2955	/* Enable DMA Request */
<>	144:ef7eb2e8f9f7	2956	hi2c->Instance->CR2 \|= I2C_CR2_DMAEN;
<>	144:ef7eb2e8f9f7	2957	}
<>	144:ef7eb2e8f9f7	2958	else
<>	144:ef7eb2e8f9f7	2959	{
<>	144:ef7eb2e8f9f7	2960	/* Send Slave Address and Memory Address */
<>	144:ef7eb2e8f9f7	2961	if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2962	{
<>	144:ef7eb2e8f9f7	2963	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	2964	{
<>	144:ef7eb2e8f9f7	2965	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2966	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2967	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2968	}
<>	144:ef7eb2e8f9f7	2969	else
<>	144:ef7eb2e8f9f7	2970	{
<>	144:ef7eb2e8f9f7	2971	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2972	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2973	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2974	}
<>	144:ef7eb2e8f9f7	2975	}
<>	144:ef7eb2e8f9f7	2976
<>	144:ef7eb2e8f9f7	2977	/* Generate Stop */
<>	144:ef7eb2e8f9f7	2978	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	2979
<>	144:ef7eb2e8f9f7	2980	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2981	}
<>	144:ef7eb2e8f9f7	2982
<>	144:ef7eb2e8f9f7	2983	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2984	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2985
<>	144:ef7eb2e8f9f7	2986	return HAL_OK;
<>	144:ef7eb2e8f9f7	2987	}
<>	144:ef7eb2e8f9f7	2988	else
<>	144:ef7eb2e8f9f7	2989	{
<>	144:ef7eb2e8f9f7	2990	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2991	}
<>	144:ef7eb2e8f9f7	2992	}
<>	144:ef7eb2e8f9f7	2993
<>	144:ef7eb2e8f9f7	2994	/**
<>	144:ef7eb2e8f9f7	2995	* @brief Reads an amount of data in no-blocking mode with DMA from a specific memory address.
<>	144:ef7eb2e8f9f7	2996	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2997	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	2998	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	2999	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	3000	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	3001	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	3002	* @param Size Amount of data to be read
<>	144:ef7eb2e8f9f7	3003	* @retval HAL status
<>	144:ef7eb2e8f9f7	3004	*/
<>	144:ef7eb2e8f9f7	3005	HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	3006	{
<>	144:ef7eb2e8f9f7	3007	uint32_t tickstart = 0x00U;
<>	144:ef7eb2e8f9f7	3008
<>	144:ef7eb2e8f9f7	3009	/* Init tickstart for timeout management*/
<>	144:ef7eb2e8f9f7	3010	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	3011
<>	144:ef7eb2e8f9f7	3012	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	3013
<>	144:ef7eb2e8f9f7	3014	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3015	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<>	144:ef7eb2e8f9f7	3016
<>	144:ef7eb2e8f9f7	3017	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	3018	{
<>	144:ef7eb2e8f9f7	3019	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	3020	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	3021	do
<>	144:ef7eb2e8f9f7	3022	{
<>	144:ef7eb2e8f9f7	3023	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	3024	{
<>	144:ef7eb2e8f9f7	3025	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	3026	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3027
<>	144:ef7eb2e8f9f7	3028	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3029	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3030
<>	144:ef7eb2e8f9f7	3031	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3032	}
<>	144:ef7eb2e8f9f7	3033	}
<>	144:ef7eb2e8f9f7	3034	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	3035
<>	144:ef7eb2e8f9f7	3036	/* Process Locked */
<>	144:ef7eb2e8f9f7	3037	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	3038
<>	144:ef7eb2e8f9f7	3039	/* Disable Pos */
<>	144:ef7eb2e8f9f7	3040	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	3041
<>	144:ef7eb2e8f9f7	3042	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	3043	hi2c->Mode = HAL_I2C_MODE_MEM;
<>	144:ef7eb2e8f9f7	3044	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	3045
<>	144:ef7eb2e8f9f7	3046	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	3047	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	3048	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	3049	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	3050
<>	144:ef7eb2e8f9f7	3051	if(hi2c->XferSize > 0U)
<>	144:ef7eb2e8f9f7	3052	{
<>	144:ef7eb2e8f9f7	3053	/* Set the I2C DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	3054	hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
<>	144:ef7eb2e8f9f7	3055
<>	144:ef7eb2e8f9f7	3056	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3057	hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
<>	144:ef7eb2e8f9f7	3058
<>	144:ef7eb2e8f9f7	3059	/* Set the unused DMA callbacks to NULL */
<>	144:ef7eb2e8f9f7	3060	hi2c->hdmarx->XferHalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	3061	hi2c->hdmarx->XferM1CpltCallback = NULL;
<>	144:ef7eb2e8f9f7	3062	hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	3063	hi2c->hdmarx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	3064
<>	144:ef7eb2e8f9f7	3065	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	3066	HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size);
<>	144:ef7eb2e8f9f7	3067
<>	144:ef7eb2e8f9f7	3068	/* Send Slave Address and Memory Address */
<>	144:ef7eb2e8f9f7	3069	if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3070	{
<>	144:ef7eb2e8f9f7	3071	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	3072	{
<>	144:ef7eb2e8f9f7	3073	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3074	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3075	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	3076	}
<>	144:ef7eb2e8f9f7	3077	else
<>	144:ef7eb2e8f9f7	3078	{
<>	144:ef7eb2e8f9f7	3079	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3080	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3081	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3082	}
<>	144:ef7eb2e8f9f7	3083	}
<>	144:ef7eb2e8f9f7	3084
<>	144:ef7eb2e8f9f7	3085	if(Size == 1U)
<>	144:ef7eb2e8f9f7	3086	{
<>	144:ef7eb2e8f9f7	3087	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	3088	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	3089	}
<>	144:ef7eb2e8f9f7	3090	else
<>	144:ef7eb2e8f9f7	3091	{
<>	144:ef7eb2e8f9f7	3092	/* Enable Last DMA bit */
<>	144:ef7eb2e8f9f7	3093	hi2c->Instance->CR2 \|= I2C_CR2_LAST;
<>	144:ef7eb2e8f9f7	3094	}
<>	144:ef7eb2e8f9f7	3095
<>	144:ef7eb2e8f9f7	3096	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	3097	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	3098
<>	144:ef7eb2e8f9f7	3099	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3100	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3101
<>	144:ef7eb2e8f9f7	3102	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	3103	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	3104	process unlock */
<>	144:ef7eb2e8f9f7	3105	/* Enable ERR interrupt */
<>	144:ef7eb2e8f9f7	3106	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	3107
<>	144:ef7eb2e8f9f7	3108	/* Enable DMA Request */
<>	144:ef7eb2e8f9f7	3109	hi2c->Instance->CR2 \|= I2C_CR2_DMAEN;
<>	144:ef7eb2e8f9f7	3110	}
<>	144:ef7eb2e8f9f7	3111	else
<>	144:ef7eb2e8f9f7	3112	{
<>	144:ef7eb2e8f9f7	3113	/* Send Slave Address and Memory Address */
<>	144:ef7eb2e8f9f7	3114	if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3115	{
<>	144:ef7eb2e8f9f7	3116	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	3117	{
<>	144:ef7eb2e8f9f7	3118	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3119	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3120	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	3121	}
<>	144:ef7eb2e8f9f7	3122	else
<>	144:ef7eb2e8f9f7	3123	{
<>	144:ef7eb2e8f9f7	3124	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3125	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3126	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3127	}
<>	144:ef7eb2e8f9f7	3128	}
<>	144:ef7eb2e8f9f7	3129
<>	144:ef7eb2e8f9f7	3130	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	3131	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	3132
<>	144:ef7eb2e8f9f7	3133	/* Generate Stop */
<>	144:ef7eb2e8f9f7	3134	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	3135
<>	144:ef7eb2e8f9f7	3136	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3137
<>	144:ef7eb2e8f9f7	3138	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3139	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3140	}
<>	144:ef7eb2e8f9f7	3141
<>	144:ef7eb2e8f9f7	3142	return HAL_OK;
<>	144:ef7eb2e8f9f7	3143	}
<>	144:ef7eb2e8f9f7	3144	else
<>	144:ef7eb2e8f9f7	3145	{
<>	144:ef7eb2e8f9f7	3146	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	3147	}
<>	144:ef7eb2e8f9f7	3148	}
<>	144:ef7eb2e8f9f7	3149
<>	144:ef7eb2e8f9f7	3150	/**
<>	144:ef7eb2e8f9f7	3151	* @brief Checks if target device is ready for communication.
<>	144:ef7eb2e8f9f7	3152	* @note This function is used with Memory devices
<>	144:ef7eb2e8f9f7	3153	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3154	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	3155	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	3156	* @param Trials Number of trials
<>	144:ef7eb2e8f9f7	3157	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	3158	* @retval HAL status
<>	144:ef7eb2e8f9f7	3159	*/
<>	144:ef7eb2e8f9f7	3160	HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	3161	{
<>	144:ef7eb2e8f9f7	3162	uint32_t tickstart = 0U, tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, I2C_Trials = 1U;
<>	144:ef7eb2e8f9f7	3163
<>	144:ef7eb2e8f9f7	3164	/* Get tick */
<>	144:ef7eb2e8f9f7	3165	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	3166
<>	144:ef7eb2e8f9f7	3167	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	3168	{
<>	144:ef7eb2e8f9f7	3169	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	3170	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3171	{
<>	144:ef7eb2e8f9f7	3172	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	3173	}
<>	144:ef7eb2e8f9f7	3174
<>	144:ef7eb2e8f9f7	3175	/* Process Locked */
<>	144:ef7eb2e8f9f7	3176	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	3177
<>	144:ef7eb2e8f9f7	3178	/* Disable Pos */
<>	144:ef7eb2e8f9f7	3179	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	3180
<>	144:ef7eb2e8f9f7	3181	hi2c->State = HAL_I2C_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3182	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	3183	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	3184
<>	144:ef7eb2e8f9f7	3185	do
<>	144:ef7eb2e8f9f7	3186	{
<>	144:ef7eb2e8f9f7	3187	/* Generate Start */
<>	144:ef7eb2e8f9f7	3188	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	3189
<>	144:ef7eb2e8f9f7	3190	/* Wait until SB flag is set */
<>	144:ef7eb2e8f9f7	3191	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3192	{
<>	144:ef7eb2e8f9f7	3193	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3194	}
<>	144:ef7eb2e8f9f7	3195
<>	144:ef7eb2e8f9f7	3196	/* Send slave address */
<>	144:ef7eb2e8f9f7	3197	hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
<>	144:ef7eb2e8f9f7	3198
<>	144:ef7eb2e8f9f7	3199	/* Wait until ADDR or AF flag are set */
<>	144:ef7eb2e8f9f7	3200	/* Get tick */
<>	144:ef7eb2e8f9f7	3201	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	3202
<>	144:ef7eb2e8f9f7	3203	tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
<>	144:ef7eb2e8f9f7	3204	tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	3205	tmp3 = hi2c->State;
<>	144:ef7eb2e8f9f7	3206	while((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != HAL_I2C_STATE_TIMEOUT))
<>	144:ef7eb2e8f9f7	3207	{
<>	144:ef7eb2e8f9f7	3208	if((Timeout == 0U)\|\|((HAL_GetTick() - tickstart ) > Timeout))
<>	144:ef7eb2e8f9f7	3209	{
<>	144:ef7eb2e8f9f7	3210	hi2c->State = HAL_I2C_STATE_TIMEOUT;
<>	144:ef7eb2e8f9f7	3211	}
<>	144:ef7eb2e8f9f7	3212	tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
<>	144:ef7eb2e8f9f7	3213	tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	3214	tmp3 = hi2c->State;
<>	144:ef7eb2e8f9f7	3215	}
<>	144:ef7eb2e8f9f7	3216
<>	144:ef7eb2e8f9f7	3217	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3218
<>	144:ef7eb2e8f9f7	3219	/* Check if the ADDR flag has been set */
<>	144:ef7eb2e8f9f7	3220	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
<>	144:ef7eb2e8f9f7	3221	{
<>	144:ef7eb2e8f9f7	3222	/* Generate Stop */
<>	144:ef7eb2e8f9f7	3223	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	3224
<>	144:ef7eb2e8f9f7	3225	/* Clear ADDR Flag */
<>	144:ef7eb2e8f9f7	3226	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	3227
<>	144:ef7eb2e8f9f7	3228	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	3229	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3230	{
<>	144:ef7eb2e8f9f7	3231	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3232	}
<>	144:ef7eb2e8f9f7	3233
<>	144:ef7eb2e8f9f7	3234	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3235
<>	144:ef7eb2e8f9f7	3236	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3237	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3238
<>	144:ef7eb2e8f9f7	3239	return HAL_OK;
<>	144:ef7eb2e8f9f7	3240	}
<>	144:ef7eb2e8f9f7	3241	else
<>	144:ef7eb2e8f9f7	3242	{
<>	144:ef7eb2e8f9f7	3243	/* Generate Stop */
<>	144:ef7eb2e8f9f7	3244	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	3245
<>	144:ef7eb2e8f9f7	3246	/* Clear AF Flag */
<>	144:ef7eb2e8f9f7	3247	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	3248
<>	144:ef7eb2e8f9f7	3249	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	3250	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3251	{
<>	144:ef7eb2e8f9f7	3252	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3253	}
<>	144:ef7eb2e8f9f7	3254	}
<>	144:ef7eb2e8f9f7	3255	}while(I2C_Trials++ < Trials);
<>	144:ef7eb2e8f9f7	3256
<>	144:ef7eb2e8f9f7	3257	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3258
<>	144:ef7eb2e8f9f7	3259	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3260	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3261
<>	144:ef7eb2e8f9f7	3262	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	3263	}
<>	144:ef7eb2e8f9f7	3264	else
<>	144:ef7eb2e8f9f7	3265	{
<>	144:ef7eb2e8f9f7	3266	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	3267	}
<>	144:ef7eb2e8f9f7	3268	}
<>	144:ef7eb2e8f9f7	3269
<>	144:ef7eb2e8f9f7	3270	/**
<>	144:ef7eb2e8f9f7	3271	* @brief This function handles I2C event interrupt request.
<>	144:ef7eb2e8f9f7	3272	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3273	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	3274	* @retval HAL status
<>	144:ef7eb2e8f9f7	3275	*/
<>	144:ef7eb2e8f9f7	3276	void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3277	{
<>	144:ef7eb2e8f9f7	3278	uint32_t sr2itflags = READ_REG(hi2c->Instance->SR2);
<>	144:ef7eb2e8f9f7	3279	uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
<>	144:ef7eb2e8f9f7	3280	uint32_t itsources = READ_REG(hi2c->Instance->CR2);
<>	144:ef7eb2e8f9f7	3281
<>	144:ef7eb2e8f9f7	3282	uint32_t CurrentMode = hi2c->Mode;
<>	144:ef7eb2e8f9f7	3283
<>	144:ef7eb2e8f9f7	3284	/* Master or Memory mode selected */
<>	144:ef7eb2e8f9f7	3285	if((CurrentMode == HAL_I2C_MODE_MASTER) \|\| (CurrentMode == HAL_I2C_MODE_MEM))
<>	144:ef7eb2e8f9f7	3286	{
<>	144:ef7eb2e8f9f7	3287	/* SB Set ----------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3288	if(((sr1itflags & I2C_FLAG_SB) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
<>	144:ef7eb2e8f9f7	3289	{
<>	144:ef7eb2e8f9f7	3290	I2C_Master_SB(hi2c);
<>	144:ef7eb2e8f9f7	3291	}
<>	144:ef7eb2e8f9f7	3292	/* ADD10 Set -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3293	else if(((sr1itflags & I2C_FLAG_ADD10) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
<>	144:ef7eb2e8f9f7	3294	{
<>	144:ef7eb2e8f9f7	3295	I2C_Master_ADD10(hi2c);
<>	144:ef7eb2e8f9f7	3296	}
<>	144:ef7eb2e8f9f7	3297	/* ADDR Set --------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3298	else if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
<>	144:ef7eb2e8f9f7	3299	{
<>	144:ef7eb2e8f9f7	3300	I2C_Master_ADDR(hi2c);
<>	144:ef7eb2e8f9f7	3301	}
<>	144:ef7eb2e8f9f7	3302
<>	144:ef7eb2e8f9f7	3303	/* I2C in mode Transmitter -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	3304	if((sr2itflags & I2C_FLAG_TRA) != RESET)
<>	144:ef7eb2e8f9f7	3305	{
<>	144:ef7eb2e8f9f7	3306	/* TXE set and BTF reset -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	3307	if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
<>	144:ef7eb2e8f9f7	3308	{
<>	144:ef7eb2e8f9f7	3309	I2C_MasterTransmit_TXE(hi2c);
<>	144:ef7eb2e8f9f7	3310	}
<>	144:ef7eb2e8f9f7	3311	/* BTF set -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3312	else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
<>	144:ef7eb2e8f9f7	3313	{
<>	144:ef7eb2e8f9f7	3314	I2C_MasterTransmit_BTF(hi2c);
<>	144:ef7eb2e8f9f7	3315	}
<>	144:ef7eb2e8f9f7	3316	}
<>	144:ef7eb2e8f9f7	3317	/* I2C in mode Receiver --------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3318	else
<>	144:ef7eb2e8f9f7	3319	{
<>	144:ef7eb2e8f9f7	3320	/* RXNE set and BTF reset -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	3321	if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
<>	144:ef7eb2e8f9f7	3322	{
<>	144:ef7eb2e8f9f7	3323	I2C_MasterReceive_RXNE(hi2c);
<>	144:ef7eb2e8f9f7	3324	}
<>	144:ef7eb2e8f9f7	3325	/* BTF set -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3326	else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
<>	144:ef7eb2e8f9f7	3327	{
<>	144:ef7eb2e8f9f7	3328	I2C_MasterReceive_BTF(hi2c);
<>	144:ef7eb2e8f9f7	3329	}
<>	144:ef7eb2e8f9f7	3330	}
<>	144:ef7eb2e8f9f7	3331	}
<>	144:ef7eb2e8f9f7	3332	/* Slave mode selected */
<>	144:ef7eb2e8f9f7	3333	else
<>	144:ef7eb2e8f9f7	3334	{
<>	144:ef7eb2e8f9f7	3335	/* ADDR set --------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3336	if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
<>	144:ef7eb2e8f9f7	3337	{
<>	144:ef7eb2e8f9f7	3338	I2C_Slave_ADDR(hi2c);
<>	144:ef7eb2e8f9f7	3339	}
<>	144:ef7eb2e8f9f7	3340	/* STOPF set --------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3341	else if(((sr1itflags & I2C_FLAG_STOPF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
<>	144:ef7eb2e8f9f7	3342	{
<>	144:ef7eb2e8f9f7	3343	I2C_Slave_STOPF(hi2c);
<>	144:ef7eb2e8f9f7	3344	}
<>	144:ef7eb2e8f9f7	3345	/* I2C in mode Transmitter -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	3346	else if((sr2itflags & I2C_FLAG_TRA) != RESET)
<>	144:ef7eb2e8f9f7	3347	{
<>	144:ef7eb2e8f9f7	3348	/* TXE set and BTF reset -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	3349	if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
<>	144:ef7eb2e8f9f7	3350	{
<>	144:ef7eb2e8f9f7	3351	I2C_SlaveTransmit_TXE(hi2c);
<>	144:ef7eb2e8f9f7	3352	}
<>	144:ef7eb2e8f9f7	3353	/* BTF set -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3354	else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
<>	144:ef7eb2e8f9f7	3355	{
<>	144:ef7eb2e8f9f7	3356	I2C_SlaveTransmit_BTF(hi2c);
<>	144:ef7eb2e8f9f7	3357	}
<>	144:ef7eb2e8f9f7	3358	}
<>	144:ef7eb2e8f9f7	3359	/* I2C in mode Receiver --------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3360	else
<>	144:ef7eb2e8f9f7	3361	{
<>	144:ef7eb2e8f9f7	3362	/* RXNE set and BTF reset ----------------------------------------------*/
<>	144:ef7eb2e8f9f7	3363	if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
<>	144:ef7eb2e8f9f7	3364	{
<>	144:ef7eb2e8f9f7	3365	I2C_SlaveReceive_RXNE(hi2c);
<>	144:ef7eb2e8f9f7	3366	}
<>	144:ef7eb2e8f9f7	3367	/* BTF set -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3368	else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
<>	144:ef7eb2e8f9f7	3369	{
<>	144:ef7eb2e8f9f7	3370	I2C_SlaveReceive_BTF(hi2c);
<>	144:ef7eb2e8f9f7	3371	}
<>	144:ef7eb2e8f9f7	3372	}
<>	144:ef7eb2e8f9f7	3373	}
<>	144:ef7eb2e8f9f7	3374	}
<>	144:ef7eb2e8f9f7	3375
<>	144:ef7eb2e8f9f7	3376	/**
<>	144:ef7eb2e8f9f7	3377	* @brief This function handles I2C error interrupt request.
<>	144:ef7eb2e8f9f7	3378	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3379	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	3380	* @retval HAL status
<>	144:ef7eb2e8f9f7	3381	*/
<>	144:ef7eb2e8f9f7	3382	void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3383	{
<>	144:ef7eb2e8f9f7	3384	uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, tmp4 = 0U;
<>	144:ef7eb2e8f9f7	3385	uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
<>	144:ef7eb2e8f9f7	3386	uint32_t itsources = READ_REG(hi2c->Instance->CR2);
<>	144:ef7eb2e8f9f7	3387
<>	144:ef7eb2e8f9f7	3388	/* I2C Bus error interrupt occurred ----------------------------------------*/
<>	144:ef7eb2e8f9f7	3389	if(((sr1itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
<>	144:ef7eb2e8f9f7	3390	{
<>	144:ef7eb2e8f9f7	3391	hi2c->ErrorCode \|= HAL_I2C_ERROR_BERR;
<>	144:ef7eb2e8f9f7	3392
<>	144:ef7eb2e8f9f7	3393	/* Clear BERR flag */
<>	144:ef7eb2e8f9f7	3394	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
<>	144:ef7eb2e8f9f7	3395	}
<>	144:ef7eb2e8f9f7	3396
<>	144:ef7eb2e8f9f7	3397	/* I2C Arbitration Loss error interrupt occurred ---------------------------*/
<>	144:ef7eb2e8f9f7	3398	if(((sr1itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
<>	144:ef7eb2e8f9f7	3399	{
<>	144:ef7eb2e8f9f7	3400	hi2c->ErrorCode \|= HAL_I2C_ERROR_ARLO;
<>	144:ef7eb2e8f9f7	3401
<>	144:ef7eb2e8f9f7	3402	/* Clear ARLO flag */
<>	144:ef7eb2e8f9f7	3403	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
<>	144:ef7eb2e8f9f7	3404	}
<>	144:ef7eb2e8f9f7	3405
<>	144:ef7eb2e8f9f7	3406	/* I2C Acknowledge failure error interrupt occurred ------------------------*/
<>	144:ef7eb2e8f9f7	3407	if(((sr1itflags & I2C_FLAG_AF) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
<>	144:ef7eb2e8f9f7	3408	{
<>	144:ef7eb2e8f9f7	3409	tmp1 = hi2c->Mode;
<>	144:ef7eb2e8f9f7	3410	tmp2 = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	3411	tmp3 = hi2c->State;
<>	144:ef7eb2e8f9f7	3412	tmp4 = hi2c->PreviousState;
<>	144:ef7eb2e8f9f7	3413	if((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \
<>	144:ef7eb2e8f9f7	3414	((tmp3 == HAL_I2C_STATE_BUSY_TX) \|\| (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) \|\| \
<>	144:ef7eb2e8f9f7	3415	((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX))))
<>	144:ef7eb2e8f9f7	3416	{
<>	144:ef7eb2e8f9f7	3417	I2C_Slave_AF(hi2c);
<>	144:ef7eb2e8f9f7	3418	}
<>	144:ef7eb2e8f9f7	3419	else
<>	144:ef7eb2e8f9f7	3420	{
<>	144:ef7eb2e8f9f7	3421	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	3422
<>	144:ef7eb2e8f9f7	3423	/* Generate Stop */
<>	144:ef7eb2e8f9f7	3424	SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
<>	144:ef7eb2e8f9f7	3425
<>	144:ef7eb2e8f9f7	3426	/* Clear AF flag */
<>	144:ef7eb2e8f9f7	3427	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	3428
<>	144:ef7eb2e8f9f7	3429	}
<>	144:ef7eb2e8f9f7	3430	}
<>	144:ef7eb2e8f9f7	3431
<>	144:ef7eb2e8f9f7	3432	/* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/
<>	144:ef7eb2e8f9f7	3433	if(((sr1itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
<>	144:ef7eb2e8f9f7	3434	{
<>	144:ef7eb2e8f9f7	3435	hi2c->ErrorCode \|= HAL_I2C_ERROR_OVR;
<>	144:ef7eb2e8f9f7	3436	/* Clear OVR flag */
<>	144:ef7eb2e8f9f7	3437	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
<>	144:ef7eb2e8f9f7	3438	}
<>	144:ef7eb2e8f9f7	3439
<>	144:ef7eb2e8f9f7	3440	/* Call the Error Callback in case of Error detected -----------------------*/
<>	144:ef7eb2e8f9f7	3441	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
<>	144:ef7eb2e8f9f7	3442	{
<>	144:ef7eb2e8f9f7	3443	I2C_ITError(hi2c);
<>	144:ef7eb2e8f9f7	3444	}
<>	144:ef7eb2e8f9f7	3445	}
<>	144:ef7eb2e8f9f7	3446
<>	144:ef7eb2e8f9f7	3447	/**
<>	144:ef7eb2e8f9f7	3448	* @brief Master Tx Transfer completed callbacks.
<>	144:ef7eb2e8f9f7	3449	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3450	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	3451	* @retval None
<>	144:ef7eb2e8f9f7	3452	*/
<>	144:ef7eb2e8f9f7	3453	__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3454	{
<>	144:ef7eb2e8f9f7	3455	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3456	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	3457	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3458	the HAL_I2C_MasterTxCpltCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	3459	*/
<>	144:ef7eb2e8f9f7	3460	}
<>	144:ef7eb2e8f9f7	3461
<>	144:ef7eb2e8f9f7	3462	/**
<>	144:ef7eb2e8f9f7	3463	* @brief Master Rx Transfer completed callbacks.
<>	144:ef7eb2e8f9f7	3464	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3465	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	3466	* @retval None
<>	144:ef7eb2e8f9f7	3467	*/
<>	144:ef7eb2e8f9f7	3468	__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3469	{
<>	144:ef7eb2e8f9f7	3470	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3471	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	3472	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3473	the HAL_I2C_MasterRxCpltCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	3474	*/
<>	144:ef7eb2e8f9f7	3475	}
<>	144:ef7eb2e8f9f7	3476
<>	144:ef7eb2e8f9f7	3477	/** @brief Slave Tx Transfer completed callbacks.
<>	144:ef7eb2e8f9f7	3478	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3479	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	3480	* @retval None
<>	144:ef7eb2e8f9f7	3481	*/
<>	144:ef7eb2e8f9f7	3482	__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3483	{
<>	144:ef7eb2e8f9f7	3484	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3485	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	3486	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3487	the HAL_I2C_SlaveTxCpltCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	3488	*/
<>	144:ef7eb2e8f9f7	3489	}
<>	144:ef7eb2e8f9f7	3490
<>	144:ef7eb2e8f9f7	3491	/**
<>	144:ef7eb2e8f9f7	3492	* @brief Slave Rx Transfer completed callbacks.
<>	144:ef7eb2e8f9f7	3493	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3494	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	3495	* @retval None
<>	144:ef7eb2e8f9f7	3496	*/
<>	144:ef7eb2e8f9f7	3497	__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3498	{
<>	144:ef7eb2e8f9f7	3499	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3500	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	3501	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3502	the HAL_I2C_SlaveRxCpltCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	3503	*/
<>	144:ef7eb2e8f9f7	3504	}
<>	144:ef7eb2e8f9f7	3505
<>	144:ef7eb2e8f9f7	3506	/**
<>	144:ef7eb2e8f9f7	3507	* @brief Slave Address Match callback.
<>	144:ef7eb2e8f9f7	3508	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3509	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3510	* @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferOptions_definition
<>	144:ef7eb2e8f9f7	3511	* @param AddrMatchCode Address Match Code
<>	144:ef7eb2e8f9f7	3512	* @retval None
<>	144:ef7eb2e8f9f7	3513	*/
<>	144:ef7eb2e8f9f7	3514	__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
<>	144:ef7eb2e8f9f7	3515	{
<>	144:ef7eb2e8f9f7	3516	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3517	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	3518	UNUSED(TransferDirection);
<>	144:ef7eb2e8f9f7	3519	UNUSED(AddrMatchCode);
<>	144:ef7eb2e8f9f7	3520	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3521	the HAL_I2C_AddrCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	3522	*/
<>	144:ef7eb2e8f9f7	3523	}
<>	144:ef7eb2e8f9f7	3524
<>	144:ef7eb2e8f9f7	3525	/**
<>	144:ef7eb2e8f9f7	3526	* @brief Listen Complete callback.
<>	144:ef7eb2e8f9f7	3527	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3528	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3529	* @retval None
<>	144:ef7eb2e8f9f7	3530	*/
<>	144:ef7eb2e8f9f7	3531	__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3532	{
<>	144:ef7eb2e8f9f7	3533	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3534	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	3535	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3536	the HAL_I2C_ListenCpltCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	3537	*/
<>	144:ef7eb2e8f9f7	3538	}
<>	144:ef7eb2e8f9f7	3539
<>	144:ef7eb2e8f9f7	3540	/**
<>	144:ef7eb2e8f9f7	3541	* @brief Memory Tx Transfer completed callbacks.
<>	144:ef7eb2e8f9f7	3542	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3543	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	3544	* @retval None
<>	144:ef7eb2e8f9f7	3545	*/
<>	144:ef7eb2e8f9f7	3546	__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3547	{
<>	144:ef7eb2e8f9f7	3548	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3549	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	3550	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3551	the HAL_I2C_MemTxCpltCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	3552	*/
<>	144:ef7eb2e8f9f7	3553	}
<>	144:ef7eb2e8f9f7	3554
<>	144:ef7eb2e8f9f7	3555	/**
<>	144:ef7eb2e8f9f7	3556	* @brief Memory Rx Transfer completed callbacks.
<>	144:ef7eb2e8f9f7	3557	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3558	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	3559	* @retval None
<>	144:ef7eb2e8f9f7	3560	*/
<>	144:ef7eb2e8f9f7	3561	__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3562	{
<>	144:ef7eb2e8f9f7	3563	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3564	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	3565	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3566	the HAL_I2C_MemRxCpltCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	3567	*/
<>	144:ef7eb2e8f9f7	3568	}
<>	144:ef7eb2e8f9f7	3569
<>	144:ef7eb2e8f9f7	3570	/**
<>	144:ef7eb2e8f9f7	3571	* @brief I2C error callbacks.
<>	144:ef7eb2e8f9f7	3572	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3573	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	3574	* @retval None
<>	144:ef7eb2e8f9f7	3575	*/
<>	144:ef7eb2e8f9f7	3576	__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3577	{
<>	144:ef7eb2e8f9f7	3578	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3579	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	3580	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3581	the HAL_I2C_ErrorCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	3582	*/
<>	144:ef7eb2e8f9f7	3583	}
<>	144:ef7eb2e8f9f7	3584
<>	144:ef7eb2e8f9f7	3585	/**
<>	144:ef7eb2e8f9f7	3586	* @brief I2C abort callback.
<>	144:ef7eb2e8f9f7	3587	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3588	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3589	* @retval None
<>	144:ef7eb2e8f9f7	3590	*/
<>	144:ef7eb2e8f9f7	3591	__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3592	{
<>	144:ef7eb2e8f9f7	3593	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3594	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	3595
<>	144:ef7eb2e8f9f7	3596	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3597	the HAL_I2C_AbortCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	3598	*/
<>	144:ef7eb2e8f9f7	3599	}
<>	144:ef7eb2e8f9f7	3600
<>	144:ef7eb2e8f9f7	3601	/**
<>	144:ef7eb2e8f9f7	3602	* @}
<>	144:ef7eb2e8f9f7	3603	*/
<>	144:ef7eb2e8f9f7	3604
<>	144:ef7eb2e8f9f7	3605	/** @defgroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions
<>	144:ef7eb2e8f9f7	3606	* @brief Peripheral State and Errors functions
<>	144:ef7eb2e8f9f7	3607	*
<>	144:ef7eb2e8f9f7	3608	@verbatim
<>	144:ef7eb2e8f9f7	3609	===============================================================================
<>	144:ef7eb2e8f9f7	3610	##### Peripheral State, Mode and Errors functions #####
<>	144:ef7eb2e8f9f7	3611	===============================================================================
<>	144:ef7eb2e8f9f7	3612	[..]
<>	144:ef7eb2e8f9f7	3613	This subsection permits to get in run-time the status of the peripheral
<>	144:ef7eb2e8f9f7	3614	and the data flow.
<>	144:ef7eb2e8f9f7	3615
<>	144:ef7eb2e8f9f7	3616	@endverbatim
<>	144:ef7eb2e8f9f7	3617	* @{
<>	144:ef7eb2e8f9f7	3618	*/
<>	144:ef7eb2e8f9f7	3619
<>	144:ef7eb2e8f9f7	3620	/**
<>	144:ef7eb2e8f9f7	3621	* @brief Returns the I2C state.
<>	144:ef7eb2e8f9f7	3622	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3623	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	3624	* @retval HAL state
<>	144:ef7eb2e8f9f7	3625	*/
<>	144:ef7eb2e8f9f7	3626	HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3627	{
<>	144:ef7eb2e8f9f7	3628	return hi2c->State;
<>	144:ef7eb2e8f9f7	3629	}
<>	144:ef7eb2e8f9f7	3630
<>	144:ef7eb2e8f9f7	3631	/**
<>	144:ef7eb2e8f9f7	3632	* @brief Returns the I2C Master, Slave, Memory or no mode.
<>	144:ef7eb2e8f9f7	3633	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3634	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	3635	* @retval HAL mode
<>	144:ef7eb2e8f9f7	3636	*/
<>	144:ef7eb2e8f9f7	3637	HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3638	{
<>	144:ef7eb2e8f9f7	3639	return hi2c->Mode;
<>	144:ef7eb2e8f9f7	3640	}
<>	144:ef7eb2e8f9f7	3641
<>	144:ef7eb2e8f9f7	3642	/**
<>	144:ef7eb2e8f9f7	3643	* @brief Return the I2C error code
<>	144:ef7eb2e8f9f7	3644	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3645	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3646	* @retval I2C Error Code
<>	144:ef7eb2e8f9f7	3647	*/
<>	144:ef7eb2e8f9f7	3648	uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3649	{
<>	144:ef7eb2e8f9f7	3650	return hi2c->ErrorCode;
<>	144:ef7eb2e8f9f7	3651	}
<>	144:ef7eb2e8f9f7	3652
<>	144:ef7eb2e8f9f7	3653	/**
<>	144:ef7eb2e8f9f7	3654	* @}
<>	144:ef7eb2e8f9f7	3655	*/
<>	144:ef7eb2e8f9f7	3656
<>	144:ef7eb2e8f9f7	3657	/**
<>	144:ef7eb2e8f9f7	3658	* @brief Handle TXE flag for Master
<>	144:ef7eb2e8f9f7	3659	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3660	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	3661	* @retval HAL status
<>	144:ef7eb2e8f9f7	3662	*/
<>	144:ef7eb2e8f9f7	3663	static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3664	{
<>	144:ef7eb2e8f9f7	3665	/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	3666	uint32_t CurrentState = hi2c->State;
<>	144:ef7eb2e8f9f7	3667	uint32_t CurrentMode = hi2c->Mode;
<>	144:ef7eb2e8f9f7	3668	uint32_t CurrentXferOptions = hi2c->XferOptions;
<>	144:ef7eb2e8f9f7	3669	uint32_t tmp;
<>	144:ef7eb2e8f9f7	3670
<>	144:ef7eb2e8f9f7	3671	if((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
<>	144:ef7eb2e8f9f7	3672	{
<>	144:ef7eb2e8f9f7	3673	/* Call TxCpltCallback() directly if no stop mode is set */
<>	144:ef7eb2e8f9f7	3674	if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
<>	144:ef7eb2e8f9f7	3675	{
<>	144:ef7eb2e8f9f7	3676	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	3677
<>	144:ef7eb2e8f9f7	3678	tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
<>	144:ef7eb2e8f9f7	3679	hi2c->PreviousState = tmp \| (uint32_t)(hi2c->Mode);
<>	144:ef7eb2e8f9f7	3680	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	3681	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3682
<>	144:ef7eb2e8f9f7	3683	HAL_I2C_MasterTxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3684	}
<>	144:ef7eb2e8f9f7	3685	else /* Generate Stop condition then Call TxCpltCallback() */
<>	144:ef7eb2e8f9f7	3686	{
<>	144:ef7eb2e8f9f7	3687	/* Disable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	3688	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	3689
<>	144:ef7eb2e8f9f7	3690	/* Generate Stop */
<>	144:ef7eb2e8f9f7	3691	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	148:21d94c44109e	3692
<>	144:ef7eb2e8f9f7	3693	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	3694	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3695
<>	144:ef7eb2e8f9f7	3696	if(hi2c->Mode == HAL_I2C_MODE_MEM)
<>	144:ef7eb2e8f9f7	3697	{
<>	144:ef7eb2e8f9f7	3698	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	3699	HAL_I2C_MemTxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3700	}
<>	144:ef7eb2e8f9f7	3701	else
<>	144:ef7eb2e8f9f7	3702	{
<>	144:ef7eb2e8f9f7	3703	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	3704	HAL_I2C_MasterTxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3705	}
<>	144:ef7eb2e8f9f7	3706	}
<>	144:ef7eb2e8f9f7	3707	}
<>	144:ef7eb2e8f9f7	3708	else if((CurrentState == HAL_I2C_STATE_BUSY_TX) \|\| \
<>	144:ef7eb2e8f9f7	3709	((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX)))
<>	144:ef7eb2e8f9f7	3710	{
<>	144:ef7eb2e8f9f7	3711	if(hi2c->XferCount == 0U)
<>	144:ef7eb2e8f9f7	3712	{
<>	144:ef7eb2e8f9f7	3713	/* Disable BUF interrupt */
<>	144:ef7eb2e8f9f7	3714	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
<>	144:ef7eb2e8f9f7	3715	}
<>	144:ef7eb2e8f9f7	3716	else
<>	144:ef7eb2e8f9f7	3717	{
<>	144:ef7eb2e8f9f7	3718	if(hi2c->Mode == HAL_I2C_MODE_MEM)
<>	144:ef7eb2e8f9f7	3719	{
<>	144:ef7eb2e8f9f7	3720	if(hi2c->EventCount == 0)
<>	144:ef7eb2e8f9f7	3721	{
<>	144:ef7eb2e8f9f7	3722	/* If Memory address size is 8Bit */
<>	144:ef7eb2e8f9f7	3723	if(hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT)
<>	144:ef7eb2e8f9f7	3724	{
<>	144:ef7eb2e8f9f7	3725	/* Send Memory Address */
<>	144:ef7eb2e8f9f7	3726	hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
<>	144:ef7eb2e8f9f7	3727
<>	144:ef7eb2e8f9f7	3728	hi2c->EventCount += 2;
<>	144:ef7eb2e8f9f7	3729	}
<>	144:ef7eb2e8f9f7	3730	/* If Memory address size is 16Bit */
<>	144:ef7eb2e8f9f7	3731	else
<>	144:ef7eb2e8f9f7	3732	{
<>	144:ef7eb2e8f9f7	3733	/* Send MSB of Memory Address */
<>	144:ef7eb2e8f9f7	3734	hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress);
<>	144:ef7eb2e8f9f7	3735
<>	144:ef7eb2e8f9f7	3736	hi2c->EventCount++;
<>	144:ef7eb2e8f9f7	3737	}
<>	144:ef7eb2e8f9f7	3738	}
<>	144:ef7eb2e8f9f7	3739	else if(hi2c->EventCount == 1)
<>	144:ef7eb2e8f9f7	3740	{
<>	144:ef7eb2e8f9f7	3741	/* Send LSB of Memory Address */
<>	144:ef7eb2e8f9f7	3742	hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
<>	144:ef7eb2e8f9f7	3743
<>	144:ef7eb2e8f9f7	3744	hi2c->EventCount++;
<>	144:ef7eb2e8f9f7	3745	}
<>	144:ef7eb2e8f9f7	3746	else if(hi2c->EventCount == 2)
<>	144:ef7eb2e8f9f7	3747	{
<>	144:ef7eb2e8f9f7	3748	if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
<>	144:ef7eb2e8f9f7	3749	{
<>	144:ef7eb2e8f9f7	3750	/* Generate Restart */
<>	144:ef7eb2e8f9f7	3751	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	3752	}
<>	144:ef7eb2e8f9f7	3753	else if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
<>	144:ef7eb2e8f9f7	3754	{
<>	144:ef7eb2e8f9f7	3755	/* Write data to DR */
<>	144:ef7eb2e8f9f7	3756	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
<>	144:ef7eb2e8f9f7	3757	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	3758	}
<>	144:ef7eb2e8f9f7	3759	}
<>	144:ef7eb2e8f9f7	3760	}
<>	144:ef7eb2e8f9f7	3761	else
<>	144:ef7eb2e8f9f7	3762	{
<>	144:ef7eb2e8f9f7	3763	/* Write data to DR */
<>	144:ef7eb2e8f9f7	3764	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
<>	144:ef7eb2e8f9f7	3765	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	3766	}
<>	144:ef7eb2e8f9f7	3767	}
<>	144:ef7eb2e8f9f7	3768	}
<>	144:ef7eb2e8f9f7	3769	return HAL_OK;
<>	144:ef7eb2e8f9f7	3770	}
<>	144:ef7eb2e8f9f7	3771
<>	144:ef7eb2e8f9f7	3772	/**
<>	144:ef7eb2e8f9f7	3773	* @brief Handle BTF flag for Master transmitter
<>	144:ef7eb2e8f9f7	3774	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3775	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	3776	* @retval HAL status
<>	144:ef7eb2e8f9f7	3777	*/
<>	144:ef7eb2e8f9f7	3778	static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3779	{
<>	144:ef7eb2e8f9f7	3780	/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	3781	uint32_t tmp;
<>	144:ef7eb2e8f9f7	3782	uint32_t CurrentXferOptions = hi2c->XferOptions;
<>	144:ef7eb2e8f9f7	3783
<>	144:ef7eb2e8f9f7	3784	if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
<>	144:ef7eb2e8f9f7	3785	{
<>	144:ef7eb2e8f9f7	3786	if(hi2c->XferCount != 0U)
<>	144:ef7eb2e8f9f7	3787	{
<>	144:ef7eb2e8f9f7	3788	/* Write data to DR */
<>	144:ef7eb2e8f9f7	3789	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
<>	144:ef7eb2e8f9f7	3790	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	3791	}
<>	144:ef7eb2e8f9f7	3792	else
<>	144:ef7eb2e8f9f7	3793	{
<>	144:ef7eb2e8f9f7	3794	/* Call TxCpltCallback() directly if no stop mode is set */
<>	144:ef7eb2e8f9f7	3795	if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
<>	144:ef7eb2e8f9f7	3796	{
<>	144:ef7eb2e8f9f7	3797	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	3798
<>	144:ef7eb2e8f9f7	3799	tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
<>	144:ef7eb2e8f9f7	3800	hi2c->PreviousState = tmp \| (uint32_t)(hi2c->Mode);
<>	144:ef7eb2e8f9f7	3801	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	3802	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3803
<>	144:ef7eb2e8f9f7	3804	HAL_I2C_MasterTxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3805	}
<>	144:ef7eb2e8f9f7	3806	else /* Generate Stop condition then Call TxCpltCallback() */
<>	144:ef7eb2e8f9f7	3807	{
<>	144:ef7eb2e8f9f7	3808	/* Disable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	3809	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	3810
<>	144:ef7eb2e8f9f7	3811	/* Generate Stop */
<>	144:ef7eb2e8f9f7	3812	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	3813
<>	144:ef7eb2e8f9f7	3814	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	3815	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3816
<>	144:ef7eb2e8f9f7	3817	if(hi2c->Mode == HAL_I2C_MODE_MEM)
<>	144:ef7eb2e8f9f7	3818	{
<>	144:ef7eb2e8f9f7	3819	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	3820
<>	144:ef7eb2e8f9f7	3821	HAL_I2C_MemTxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3822	}
<>	144:ef7eb2e8f9f7	3823	else
<>	144:ef7eb2e8f9f7	3824	{
<>	144:ef7eb2e8f9f7	3825	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	3826
<>	144:ef7eb2e8f9f7	3827	HAL_I2C_MasterTxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3828	}
<>	144:ef7eb2e8f9f7	3829	}
<>	144:ef7eb2e8f9f7	3830	}
<>	144:ef7eb2e8f9f7	3831	}
<>	144:ef7eb2e8f9f7	3832	return HAL_OK;
<>	144:ef7eb2e8f9f7	3833	}
<>	144:ef7eb2e8f9f7	3834
<>	144:ef7eb2e8f9f7	3835	/**
<>	144:ef7eb2e8f9f7	3836	* @brief Handle RXNE flag for Master
<>	144:ef7eb2e8f9f7	3837	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3838	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	3839	* @retval HAL status
<>	144:ef7eb2e8f9f7	3840	*/
<>	144:ef7eb2e8f9f7	3841	static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3842	{
<>	148:21d94c44109e	3843
<>	144:ef7eb2e8f9f7	3844	if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
<>	144:ef7eb2e8f9f7	3845	{
<>	144:ef7eb2e8f9f7	3846	uint32_t tmp = 0U;
<>	144:ef7eb2e8f9f7	3847
<>	144:ef7eb2e8f9f7	3848	tmp = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	3849	if(tmp > 3U)
<>	144:ef7eb2e8f9f7	3850	{
<>	144:ef7eb2e8f9f7	3851	/* Read data from DR */
<>	144:ef7eb2e8f9f7	3852	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	3853	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	3854	}
<>	144:ef7eb2e8f9f7	3855	else if((tmp == 2U) \|\| (tmp == 3U))
<>	144:ef7eb2e8f9f7	3856	{
<>	148:21d94c44109e	3857	/* Disable Acknowledge */
<>	148:21d94c44109e	3858	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	148:21d94c44109e	3859
<>	148:21d94c44109e	3860	/* Enable Pos */
<>	148:21d94c44109e	3861	hi2c->Instance->CR1 \|= I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	3862
<>	144:ef7eb2e8f9f7	3863	/* Disable BUF interrupt */
<>	144:ef7eb2e8f9f7	3864	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
<>	144:ef7eb2e8f9f7	3865	}
<>	144:ef7eb2e8f9f7	3866	else
<>	144:ef7eb2e8f9f7	3867	{
<>	148:21d94c44109e	3868	/* Disable Acknowledge */
<>	148:21d94c44109e	3869	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	148:21d94c44109e	3870
<>	148:21d94c44109e	3871	if(hi2c->XferOptions == I2C_NEXT_FRAME)
<>	144:ef7eb2e8f9f7	3872	{
<>	148:21d94c44109e	3873	/* Enable Pos */
<>	148:21d94c44109e	3874	hi2c->Instance->CR1 \|= I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	3875	}
<>	144:ef7eb2e8f9f7	3876
<>	144:ef7eb2e8f9f7	3877	/* Disable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	3878	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	3879
<>	144:ef7eb2e8f9f7	3880	/* Read data from DR */
<>	144:ef7eb2e8f9f7	3881	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	3882	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	3883
<>	144:ef7eb2e8f9f7	3884	tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
<>	144:ef7eb2e8f9f7	3885	hi2c->PreviousState = tmp \| (uint32_t)(hi2c->Mode);
<>	144:ef7eb2e8f9f7	3886	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3887
<>	144:ef7eb2e8f9f7	3888	if(hi2c->Mode == HAL_I2C_MODE_MEM)
<>	144:ef7eb2e8f9f7	3889	{
<>	144:ef7eb2e8f9f7	3890	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	3891	HAL_I2C_MemRxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3892	}
<>	144:ef7eb2e8f9f7	3893	else
<>	144:ef7eb2e8f9f7	3894	{
<>	144:ef7eb2e8f9f7	3895	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	3896	HAL_I2C_MasterRxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3897	}
<>	144:ef7eb2e8f9f7	3898	}
<>	144:ef7eb2e8f9f7	3899	}
<>	144:ef7eb2e8f9f7	3900	return HAL_OK;
<>	144:ef7eb2e8f9f7	3901	}
<>	144:ef7eb2e8f9f7	3902
<>	144:ef7eb2e8f9f7	3903	/**
<>	144:ef7eb2e8f9f7	3904	* @brief Handle BTF flag for Master receiver
<>	144:ef7eb2e8f9f7	3905	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3906	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	3907	* @retval HAL status
<>	144:ef7eb2e8f9f7	3908	*/
<>	144:ef7eb2e8f9f7	3909	static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3910	{
<>	144:ef7eb2e8f9f7	3911	/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	3912	uint32_t tmp;
<>	144:ef7eb2e8f9f7	3913	uint32_t CurrentXferOptions = hi2c->XferOptions;
<>	144:ef7eb2e8f9f7	3914
<>	144:ef7eb2e8f9f7	3915	if(hi2c->XferCount == 3U)
<>	144:ef7eb2e8f9f7	3916	{
<>	144:ef7eb2e8f9f7	3917	if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) \|\| (CurrentXferOptions == I2C_LAST_FRAME) \|\| (CurrentXferOptions == I2C_NO_OPTION_FRAME))
<>	144:ef7eb2e8f9f7	3918	{
<>	144:ef7eb2e8f9f7	3919	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	3920	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	3921	}
<>	144:ef7eb2e8f9f7	3922
<>	144:ef7eb2e8f9f7	3923	/* Read data from DR */
<>	144:ef7eb2e8f9f7	3924	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	3925	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	3926	}
<>	144:ef7eb2e8f9f7	3927	else if(hi2c->XferCount == 2U)
<>	144:ef7eb2e8f9f7	3928	{
<>	144:ef7eb2e8f9f7	3929	/* Prepare next transfer or stop current transfer */
<>	144:ef7eb2e8f9f7	3930	if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
<>	144:ef7eb2e8f9f7	3931	{
<>	148:21d94c44109e	3932	/* Disable Acknowledge */
<>	148:21d94c44109e	3933	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	148:21d94c44109e	3934
<>	148:21d94c44109e	3935	if((CurrentXferOptions == I2C_NEXT_FRAME) \|\| (CurrentXferOptions == I2C_FIRST_FRAME))
<>	144:ef7eb2e8f9f7	3936	{
<>	148:21d94c44109e	3937	/* Generate Start */
<>	148:21d94c44109e	3938	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	3939	}
<>	144:ef7eb2e8f9f7	3940	tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
<>	144:ef7eb2e8f9f7	3941	hi2c->PreviousState = tmp \| (uint32_t)(hi2c->Mode);
<>	144:ef7eb2e8f9f7	3942	}
<>	144:ef7eb2e8f9f7	3943	else
<>	144:ef7eb2e8f9f7	3944	{
<>	144:ef7eb2e8f9f7	3945	hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
<>	144:ef7eb2e8f9f7	3946
<>	144:ef7eb2e8f9f7	3947	/* Generate Stop */
<>	144:ef7eb2e8f9f7	3948	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	3949	}
<>	144:ef7eb2e8f9f7	3950
<>	144:ef7eb2e8f9f7	3951	/* Read data from DR */
<>	144:ef7eb2e8f9f7	3952	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	3953	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	3954
<>	144:ef7eb2e8f9f7	3955	/* Read data from DR */
<>	144:ef7eb2e8f9f7	3956	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	3957	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	3958
<>	144:ef7eb2e8f9f7	3959	/* Disable EVT and ERR interrupt */
<>	144:ef7eb2e8f9f7	3960	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	3961
<>	144:ef7eb2e8f9f7	3962	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3963
<>	144:ef7eb2e8f9f7	3964	if(hi2c->Mode == HAL_I2C_MODE_MEM)
<>	144:ef7eb2e8f9f7	3965	{
<>	144:ef7eb2e8f9f7	3966	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	3967
<>	144:ef7eb2e8f9f7	3968	HAL_I2C_MemRxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3969	}
<>	144:ef7eb2e8f9f7	3970	else
<>	144:ef7eb2e8f9f7	3971	{
<>	144:ef7eb2e8f9f7	3972	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	3973
<>	144:ef7eb2e8f9f7	3974	HAL_I2C_MasterRxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3975	}
<>	144:ef7eb2e8f9f7	3976	}
<>	144:ef7eb2e8f9f7	3977	else
<>	144:ef7eb2e8f9f7	3978	{
<>	144:ef7eb2e8f9f7	3979	/* Read data from DR */
<>	144:ef7eb2e8f9f7	3980	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	3981	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	3982	}
<>	144:ef7eb2e8f9f7	3983	return HAL_OK;
<>	144:ef7eb2e8f9f7	3984	}
<>	144:ef7eb2e8f9f7	3985
<>	144:ef7eb2e8f9f7	3986	/**
<>	144:ef7eb2e8f9f7	3987	* @brief Handle SB flag for Master
<>	144:ef7eb2e8f9f7	3988	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3989	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	3990	* @retval HAL status
<>	144:ef7eb2e8f9f7	3991	*/
<>	144:ef7eb2e8f9f7	3992
<>	144:ef7eb2e8f9f7	3993	static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3994	{
<>	144:ef7eb2e8f9f7	3995	if(hi2c->Mode == HAL_I2C_MODE_MEM)
<>	144:ef7eb2e8f9f7	3996	{
<>	144:ef7eb2e8f9f7	3997	if(hi2c->EventCount == 0U)
<>	144:ef7eb2e8f9f7	3998	{
<>	144:ef7eb2e8f9f7	3999	/* Send slave address */
<>	144:ef7eb2e8f9f7	4000	hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
<>	144:ef7eb2e8f9f7	4001	}
<>	144:ef7eb2e8f9f7	4002	else
<>	144:ef7eb2e8f9f7	4003	{
<>	144:ef7eb2e8f9f7	4004	hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
<>	144:ef7eb2e8f9f7	4005	}
<>	144:ef7eb2e8f9f7	4006	}
<>	144:ef7eb2e8f9f7	4007	else
<>	144:ef7eb2e8f9f7	4008	{
<>	144:ef7eb2e8f9f7	4009	if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
<>	144:ef7eb2e8f9f7	4010	{
<>	144:ef7eb2e8f9f7	4011	/* Send slave 7 Bits address */
<>	144:ef7eb2e8f9f7	4012	if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
<>	144:ef7eb2e8f9f7	4013	{
<>	144:ef7eb2e8f9f7	4014	hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
<>	144:ef7eb2e8f9f7	4015	}
<>	144:ef7eb2e8f9f7	4016	else
<>	144:ef7eb2e8f9f7	4017	{
<>	144:ef7eb2e8f9f7	4018	hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
<>	144:ef7eb2e8f9f7	4019	}
<>	144:ef7eb2e8f9f7	4020	}
<>	144:ef7eb2e8f9f7	4021	else
<>	144:ef7eb2e8f9f7	4022	{
<>	144:ef7eb2e8f9f7	4023	if(hi2c->EventCount == 0U)
<>	144:ef7eb2e8f9f7	4024	{
<>	144:ef7eb2e8f9f7	4025	/* Send header of slave address */
<>	144:ef7eb2e8f9f7	4026	hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress);
<>	144:ef7eb2e8f9f7	4027	}
<>	144:ef7eb2e8f9f7	4028	else if(hi2c->EventCount == 1U)
<>	144:ef7eb2e8f9f7	4029	{
<>	144:ef7eb2e8f9f7	4030	/* Send header of slave address */
<>	144:ef7eb2e8f9f7	4031	hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress);
<>	144:ef7eb2e8f9f7	4032	}
<>	144:ef7eb2e8f9f7	4033	}
<>	144:ef7eb2e8f9f7	4034	}
<>	144:ef7eb2e8f9f7	4035
<>	144:ef7eb2e8f9f7	4036	return HAL_OK;
<>	144:ef7eb2e8f9f7	4037	}
<>	144:ef7eb2e8f9f7	4038
<>	144:ef7eb2e8f9f7	4039	/**
<>	144:ef7eb2e8f9f7	4040	* @brief Handle ADD10 flag for Master
<>	144:ef7eb2e8f9f7	4041	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4042	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4043	* @retval HAL status
<>	144:ef7eb2e8f9f7	4044	*/
<>	144:ef7eb2e8f9f7	4045	static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4046	{
<>	144:ef7eb2e8f9f7	4047	/* Send slave address */
<>	144:ef7eb2e8f9f7	4048	hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress);
<>	144:ef7eb2e8f9f7	4049
<>	144:ef7eb2e8f9f7	4050	return HAL_OK;
<>	144:ef7eb2e8f9f7	4051	}
<>	144:ef7eb2e8f9f7	4052
<>	144:ef7eb2e8f9f7	4053	/**
<>	144:ef7eb2e8f9f7	4054	* @brief Handle ADDR flag for Master
<>	144:ef7eb2e8f9f7	4055	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4056	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4057	* @retval HAL status
<>	144:ef7eb2e8f9f7	4058	*/
<>	144:ef7eb2e8f9f7	4059	static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4060	{
<>	144:ef7eb2e8f9f7	4061	/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	4062	uint32_t CurrentMode = hi2c->Mode;
<>	144:ef7eb2e8f9f7	4063	uint32_t CurrentXferOptions = hi2c->XferOptions;
<>	144:ef7eb2e8f9f7	4064	uint32_t Prev_State = hi2c->PreviousState;
<>	144:ef7eb2e8f9f7	4065
<>	144:ef7eb2e8f9f7	4066	if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
<>	144:ef7eb2e8f9f7	4067	{
<>	144:ef7eb2e8f9f7	4068	if((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM))
<>	144:ef7eb2e8f9f7	4069	{
<>	144:ef7eb2e8f9f7	4070	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	4071	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4072	}
<>	144:ef7eb2e8f9f7	4073	else if((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT))
<>	144:ef7eb2e8f9f7	4074	{
<>	144:ef7eb2e8f9f7	4075	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	4076	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4077
<>	144:ef7eb2e8f9f7	4078	/* Generate Restart */
<>	144:ef7eb2e8f9f7	4079	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	4080
<>	144:ef7eb2e8f9f7	4081	hi2c->EventCount++;
<>	144:ef7eb2e8f9f7	4082	}
<>	144:ef7eb2e8f9f7	4083	else
<>	144:ef7eb2e8f9f7	4084	{
<>	144:ef7eb2e8f9f7	4085	if(hi2c->XferCount == 0U)
<>	144:ef7eb2e8f9f7	4086	{
<>	144:ef7eb2e8f9f7	4087	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	4088	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4089
<>	144:ef7eb2e8f9f7	4090	/* Generate Stop */
<>	144:ef7eb2e8f9f7	4091	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	4092	}
<>	144:ef7eb2e8f9f7	4093	else if(hi2c->XferCount == 1U)
<>	144:ef7eb2e8f9f7	4094	{
<>	144:ef7eb2e8f9f7	4095	/* Prepare next transfer or stop current transfer */
<>	144:ef7eb2e8f9f7	4096	if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \
<>	144:ef7eb2e8f9f7	4097	&& (Prev_State != I2C_STATE_MASTER_BUSY_RX))
<>	144:ef7eb2e8f9f7	4098	{
<>	144:ef7eb2e8f9f7	4099	if(hi2c->XferOptions != I2C_NEXT_FRAME)
<>	144:ef7eb2e8f9f7	4100	{
<>	144:ef7eb2e8f9f7	4101	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	4102	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4103	}
<>	144:ef7eb2e8f9f7	4104	else
<>	144:ef7eb2e8f9f7	4105	{
<>	144:ef7eb2e8f9f7	4106	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	4107	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4108	}
<>	144:ef7eb2e8f9f7	4109
<>	144:ef7eb2e8f9f7	4110	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	4111	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4112	}
<>	144:ef7eb2e8f9f7	4113	else
<>	144:ef7eb2e8f9f7	4114	{
<>	144:ef7eb2e8f9f7	4115	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	4116	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4117
<>	144:ef7eb2e8f9f7	4118	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	4119	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4120
<>	144:ef7eb2e8f9f7	4121	/* Generate Stop */
<>	144:ef7eb2e8f9f7	4122	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	4123	}
<>	144:ef7eb2e8f9f7	4124	}
<>	144:ef7eb2e8f9f7	4125	else if(hi2c->XferCount == 2U)
<>	144:ef7eb2e8f9f7	4126	{
<>	144:ef7eb2e8f9f7	4127	if(hi2c->XferOptions != I2C_NEXT_FRAME)
<>	144:ef7eb2e8f9f7	4128	{
<>	144:ef7eb2e8f9f7	4129	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	4130	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4131
<>	144:ef7eb2e8f9f7	4132	/* Enable Pos */
<>	144:ef7eb2e8f9f7	4133	hi2c->Instance->CR1 \|= I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	4134	}
<>	144:ef7eb2e8f9f7	4135	else
<>	144:ef7eb2e8f9f7	4136	{
<>	144:ef7eb2e8f9f7	4137	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	4138	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4139	}
<>	144:ef7eb2e8f9f7	4140
<>	144:ef7eb2e8f9f7	4141	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	4142	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4143	}
<>	144:ef7eb2e8f9f7	4144	else
<>	144:ef7eb2e8f9f7	4145	{
<>	144:ef7eb2e8f9f7	4146	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	4147	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4148
<>	144:ef7eb2e8f9f7	4149	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	4150	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4151	}
<>	144:ef7eb2e8f9f7	4152
<>	144:ef7eb2e8f9f7	4153	/* Reset Event counter */
<>	144:ef7eb2e8f9f7	4154	hi2c->EventCount = 0;
<>	144:ef7eb2e8f9f7	4155	}
<>	144:ef7eb2e8f9f7	4156	}
<>	144:ef7eb2e8f9f7	4157	else
<>	144:ef7eb2e8f9f7	4158	{
<>	144:ef7eb2e8f9f7	4159	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	4160	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4161	}
<>	144:ef7eb2e8f9f7	4162
<>	144:ef7eb2e8f9f7	4163	return HAL_OK;
<>	144:ef7eb2e8f9f7	4164	}
<>	144:ef7eb2e8f9f7	4165
<>	144:ef7eb2e8f9f7	4166	/**
<>	144:ef7eb2e8f9f7	4167	* @brief Handle TXE flag for Slave
<>	144:ef7eb2e8f9f7	4168	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4169	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4170	* @retval HAL status
<>	144:ef7eb2e8f9f7	4171	*/
<>	144:ef7eb2e8f9f7	4172	static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4173	{
<>	144:ef7eb2e8f9f7	4174	/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	4175	uint32_t tmp;
<>	144:ef7eb2e8f9f7	4176	uint32_t CurrentState = hi2c->State;
<>	144:ef7eb2e8f9f7	4177
<>	144:ef7eb2e8f9f7	4178	if(hi2c->XferCount != 0U)
<>	144:ef7eb2e8f9f7	4179	{
<>	144:ef7eb2e8f9f7	4180	/* Write data to DR */
<>	144:ef7eb2e8f9f7	4181	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
<>	144:ef7eb2e8f9f7	4182	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	4183
<>	144:ef7eb2e8f9f7	4184	if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
<>	144:ef7eb2e8f9f7	4185	{
<>	144:ef7eb2e8f9f7	4186	/* Last Byte is received, disable Interrupt */
<>	144:ef7eb2e8f9f7	4187	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
<>	144:ef7eb2e8f9f7	4188
<>	144:ef7eb2e8f9f7	4189	/* Set state at HAL_I2C_STATE_LISTEN */
<>	144:ef7eb2e8f9f7	4190	tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
<>	144:ef7eb2e8f9f7	4191	hi2c->PreviousState = tmp \| (uint32_t)(hi2c->Mode);
<>	144:ef7eb2e8f9f7	4192	hi2c->State = HAL_I2C_STATE_LISTEN;
<>	144:ef7eb2e8f9f7	4193
<>	144:ef7eb2e8f9f7	4194	/* Call the Tx complete callback to inform upper layer of the end of receive process */
<>	144:ef7eb2e8f9f7	4195	HAL_I2C_SlaveTxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	4196	}
<>	144:ef7eb2e8f9f7	4197	}
<>	144:ef7eb2e8f9f7	4198	return HAL_OK;
<>	144:ef7eb2e8f9f7	4199	}
<>	144:ef7eb2e8f9f7	4200
<>	144:ef7eb2e8f9f7	4201	/**
<>	144:ef7eb2e8f9f7	4202	* @brief Handle BTF flag for Slave transmitter
<>	144:ef7eb2e8f9f7	4203	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4204	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4205	* @retval HAL status
<>	144:ef7eb2e8f9f7	4206	*/
<>	144:ef7eb2e8f9f7	4207	static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4208	{
<>	144:ef7eb2e8f9f7	4209	if(hi2c->XferCount != 0U)
<>	144:ef7eb2e8f9f7	4210	{
<>	144:ef7eb2e8f9f7	4211	/* Write data to DR */
<>	144:ef7eb2e8f9f7	4212	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
<>	144:ef7eb2e8f9f7	4213	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	4214	}
<>	144:ef7eb2e8f9f7	4215	return HAL_OK;
<>	144:ef7eb2e8f9f7	4216	}
<>	144:ef7eb2e8f9f7	4217
<>	144:ef7eb2e8f9f7	4218	/**
<>	144:ef7eb2e8f9f7	4219	* @brief Handle RXNE flag for Slave
<>	144:ef7eb2e8f9f7	4220	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4221	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4222	* @retval HAL status
<>	144:ef7eb2e8f9f7	4223	*/
<>	144:ef7eb2e8f9f7	4224	static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4225	{
<>	144:ef7eb2e8f9f7	4226	/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	4227	uint32_t tmp;
<>	144:ef7eb2e8f9f7	4228	uint32_t CurrentState = hi2c->State;
<>	144:ef7eb2e8f9f7	4229
<>	144:ef7eb2e8f9f7	4230	if(hi2c->XferCount != 0U)
<>	144:ef7eb2e8f9f7	4231	{
<>	144:ef7eb2e8f9f7	4232	/* Read data from DR */
<>	144:ef7eb2e8f9f7	4233	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	4234	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	4235
<>	144:ef7eb2e8f9f7	4236	if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
<>	144:ef7eb2e8f9f7	4237	{
<>	144:ef7eb2e8f9f7	4238	/* Last Byte is received, disable Interrupt */
<>	144:ef7eb2e8f9f7	4239	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
<>	144:ef7eb2e8f9f7	4240
<>	144:ef7eb2e8f9f7	4241	/* Set state at HAL_I2C_STATE_LISTEN */
<>	144:ef7eb2e8f9f7	4242	tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
<>	144:ef7eb2e8f9f7	4243	hi2c->PreviousState = tmp \| (uint32_t)(hi2c->Mode);
<>	144:ef7eb2e8f9f7	4244	hi2c->State = HAL_I2C_STATE_LISTEN;
<>	144:ef7eb2e8f9f7	4245
<>	144:ef7eb2e8f9f7	4246	/* Call the Rx complete callback to inform upper layer of the end of receive process */
<>	144:ef7eb2e8f9f7	4247	HAL_I2C_SlaveRxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	4248	}
<>	144:ef7eb2e8f9f7	4249	}
<>	144:ef7eb2e8f9f7	4250	return HAL_OK;
<>	144:ef7eb2e8f9f7	4251	}
<>	144:ef7eb2e8f9f7	4252
<>	144:ef7eb2e8f9f7	4253	/**
<>	144:ef7eb2e8f9f7	4254	* @brief Handle BTF flag for Slave receiver
<>	144:ef7eb2e8f9f7	4255	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4256	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4257	* @retval HAL status
<>	144:ef7eb2e8f9f7	4258	*/
<>	144:ef7eb2e8f9f7	4259	static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4260	{
<>	144:ef7eb2e8f9f7	4261	if(hi2c->XferCount != 0U)
<>	144:ef7eb2e8f9f7	4262	{
<>	144:ef7eb2e8f9f7	4263	/* Read data from DR */
<>	144:ef7eb2e8f9f7	4264	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	4265	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	4266	}
<>	144:ef7eb2e8f9f7	4267	return HAL_OK;
<>	144:ef7eb2e8f9f7	4268	}
<>	144:ef7eb2e8f9f7	4269
<>	144:ef7eb2e8f9f7	4270	/**
<>	144:ef7eb2e8f9f7	4271	* @brief Handle ADD flag for Slave
<>	144:ef7eb2e8f9f7	4272	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4273	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4274	* @retval HAL status
<>	144:ef7eb2e8f9f7	4275	*/
<>	144:ef7eb2e8f9f7	4276	static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4277	{
<>	144:ef7eb2e8f9f7	4278	uint8_t TransferDirection = I2C_DIRECTION_RECEIVE;
<>	144:ef7eb2e8f9f7	4279	uint16_t SlaveAddrCode = 0U;
<>	144:ef7eb2e8f9f7	4280
<>	144:ef7eb2e8f9f7	4281	/* Transfer Direction requested by Master */
<>	144:ef7eb2e8f9f7	4282	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA) == RESET)
<>	144:ef7eb2e8f9f7	4283	{
<>	144:ef7eb2e8f9f7	4284	TransferDirection = I2C_DIRECTION_TRANSMIT;
<>	144:ef7eb2e8f9f7	4285	}
<>	144:ef7eb2e8f9f7	4286
<>	144:ef7eb2e8f9f7	4287	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_DUALF) == RESET)
<>	144:ef7eb2e8f9f7	4288	{
<>	144:ef7eb2e8f9f7	4289	SlaveAddrCode = hi2c->Init.OwnAddress1;
<>	144:ef7eb2e8f9f7	4290	}
<>	144:ef7eb2e8f9f7	4291	else
<>	144:ef7eb2e8f9f7	4292	{
<>	144:ef7eb2e8f9f7	4293	SlaveAddrCode = hi2c->Init.OwnAddress2;
<>	144:ef7eb2e8f9f7	4294	}
<>	144:ef7eb2e8f9f7	4295
<>	144:ef7eb2e8f9f7	4296	/* Call Slave Addr callback */
<>	144:ef7eb2e8f9f7	4297	HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
<>	144:ef7eb2e8f9f7	4298
<>	144:ef7eb2e8f9f7	4299	return HAL_OK;
<>	144:ef7eb2e8f9f7	4300	}
<>	144:ef7eb2e8f9f7	4301
<>	144:ef7eb2e8f9f7	4302	/**
<>	144:ef7eb2e8f9f7	4303	* @brief Handle STOPF flag for Slave
<>	144:ef7eb2e8f9f7	4304	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4305	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4306	* @retval HAL status
<>	144:ef7eb2e8f9f7	4307	*/
<>	144:ef7eb2e8f9f7	4308	static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4309	{
<>	144:ef7eb2e8f9f7	4310	/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	4311	uint32_t CurrentState = hi2c->State;
<>	144:ef7eb2e8f9f7	4312
<>	144:ef7eb2e8f9f7	4313	/* Disable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	4314	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	4315
<>	144:ef7eb2e8f9f7	4316	/* Clear STOPF flag */
<>	144:ef7eb2e8f9f7	4317	__HAL_I2C_CLEAR_STOPFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4318
<>	144:ef7eb2e8f9f7	4319	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	4320	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4321
<>	144:ef7eb2e8f9f7	4322	if((CurrentState == HAL_I2C_STATE_LISTEN ) \|\| (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) \|\| \
<>	144:ef7eb2e8f9f7	4323	(CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
<>	144:ef7eb2e8f9f7	4324	{
<>	144:ef7eb2e8f9f7	4325	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	4326	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	4327	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4328	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	4329
<>	144:ef7eb2e8f9f7	4330	/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
<>	144:ef7eb2e8f9f7	4331	HAL_I2C_ListenCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	4332	}
<>	144:ef7eb2e8f9f7	4333	else
<>	144:ef7eb2e8f9f7	4334	{
<>	144:ef7eb2e8f9f7	4335	if((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) \|\| (CurrentState == HAL_I2C_STATE_BUSY_RX))
<>	144:ef7eb2e8f9f7	4336	{
<>	144:ef7eb2e8f9f7	4337	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	4338	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4339	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	4340
<>	144:ef7eb2e8f9f7	4341	HAL_I2C_SlaveRxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	4342	}
<>	144:ef7eb2e8f9f7	4343	}
<>	144:ef7eb2e8f9f7	4344
<>	144:ef7eb2e8f9f7	4345	return HAL_OK;
<>	144:ef7eb2e8f9f7	4346	}
<>	144:ef7eb2e8f9f7	4347
<>	144:ef7eb2e8f9f7	4348	/**
<>	144:ef7eb2e8f9f7	4349	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4350	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4351	* @retval HAL status
<>	144:ef7eb2e8f9f7	4352	*/
<>	144:ef7eb2e8f9f7	4353	static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4354	{
<>	144:ef7eb2e8f9f7	4355	/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	4356	uint32_t CurrentState = hi2c->State;
<>	144:ef7eb2e8f9f7	4357	uint32_t CurrentXferOptions = hi2c->XferOptions;
<>	144:ef7eb2e8f9f7	4358	uint32_t tmp;
<>	144:ef7eb2e8f9f7	4359
<>	144:ef7eb2e8f9f7	4360	if(((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) \|\| (CurrentXferOptions == I2C_LAST_FRAME)) && \
<>	144:ef7eb2e8f9f7	4361	(CurrentState == HAL_I2C_STATE_LISTEN))
<>	144:ef7eb2e8f9f7	4362	{
<>	144:ef7eb2e8f9f7	4363	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	4364
<>	144:ef7eb2e8f9f7	4365	/* Disable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	4366	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	4367
<>	144:ef7eb2e8f9f7	4368	/* Clear AF flag */
<>	144:ef7eb2e8f9f7	4369	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	4370
<>	144:ef7eb2e8f9f7	4371	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	4372	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4373
<>	144:ef7eb2e8f9f7	4374	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	4375	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4376	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	4377
<>	144:ef7eb2e8f9f7	4378	/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
<>	144:ef7eb2e8f9f7	4379	HAL_I2C_ListenCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	4380	}
<>	144:ef7eb2e8f9f7	4381	else if(CurrentState == HAL_I2C_STATE_BUSY_TX)
<>	144:ef7eb2e8f9f7	4382	{
<>	144:ef7eb2e8f9f7	4383	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	4384	tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
<>	144:ef7eb2e8f9f7	4385	hi2c->PreviousState = tmp \| (uint32_t)(hi2c->Mode);
<>	144:ef7eb2e8f9f7	4386	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4387	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	4388
<>	144:ef7eb2e8f9f7	4389	/* Disable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	4390	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	4391
<>	144:ef7eb2e8f9f7	4392	/* Clear AF flag */
<>	144:ef7eb2e8f9f7	4393	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	4394
<>	144:ef7eb2e8f9f7	4395	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	4396	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4397
<>	144:ef7eb2e8f9f7	4398	HAL_I2C_SlaveTxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	4399	}
<>	144:ef7eb2e8f9f7	4400	else
<>	144:ef7eb2e8f9f7	4401	{
<>	144:ef7eb2e8f9f7	4402	/* Clear AF flag only */
<>	144:ef7eb2e8f9f7	4403	/* State Listen, but XferOptions == FIRST or NEXT */
<>	144:ef7eb2e8f9f7	4404	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	4405	}
<>	144:ef7eb2e8f9f7	4406
<>	144:ef7eb2e8f9f7	4407	return HAL_OK;
<>	144:ef7eb2e8f9f7	4408	}
<>	144:ef7eb2e8f9f7	4409
<>	144:ef7eb2e8f9f7	4410	/**
<>	144:ef7eb2e8f9f7	4411	* @brief I2C interrupts error process
<>	144:ef7eb2e8f9f7	4412	* @param hi2c I2C handle.
<>	144:ef7eb2e8f9f7	4413	* @retval None
<>	144:ef7eb2e8f9f7	4414	*/
<>	144:ef7eb2e8f9f7	4415	static void I2C_ITError(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4416	{
<>	144:ef7eb2e8f9f7	4417	/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	4418	uint32_t CurrentState = hi2c->State;
<>	144:ef7eb2e8f9f7	4419
<>	144:ef7eb2e8f9f7	4420	if((CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN) \|\| (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
<>	144:ef7eb2e8f9f7	4421	{
<>	144:ef7eb2e8f9f7	4422	/* keep HAL_I2C_STATE_LISTEN */
<>	144:ef7eb2e8f9f7	4423	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	4424	hi2c->State = HAL_I2C_STATE_LISTEN;
<>	144:ef7eb2e8f9f7	4425	}
<>	144:ef7eb2e8f9f7	4426	else
<>	144:ef7eb2e8f9f7	4427	{
<>	144:ef7eb2e8f9f7	4428	/* If state is an abort treatment on going, don't change state */
<>	144:ef7eb2e8f9f7	4429	/* This change will be do later */
<>	144:ef7eb2e8f9f7	4430	if(hi2c->State != HAL_I2C_STATE_ABORT)
<>	144:ef7eb2e8f9f7	4431	{
<>	144:ef7eb2e8f9f7	4432	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4433	}
<>	144:ef7eb2e8f9f7	4434	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	4435	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	4436	}
<>	144:ef7eb2e8f9f7	4437
<>	144:ef7eb2e8f9f7	4438	/* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */
<>	144:ef7eb2e8f9f7	4439	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	4440
<>	144:ef7eb2e8f9f7	4441	/* Abort DMA transfer */
<>	144:ef7eb2e8f9f7	4442	if((hi2c->Instance->CR1 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
<>	144:ef7eb2e8f9f7	4443	{
<>	144:ef7eb2e8f9f7	4444	hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
<>	144:ef7eb2e8f9f7	4445
<>	144:ef7eb2e8f9f7	4446	if(hi2c->hdmatx != NULL)
<>	144:ef7eb2e8f9f7	4447	{
<>	144:ef7eb2e8f9f7	4448	/* Set the DMA Abort callback :
<>	144:ef7eb2e8f9f7	4449	will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
<>	144:ef7eb2e8f9f7	4450	hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
<>	144:ef7eb2e8f9f7	4451
<>	144:ef7eb2e8f9f7	4452	if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
<>	144:ef7eb2e8f9f7	4453	{
<>	144:ef7eb2e8f9f7	4454	/* Call Directly XferAbortCallback function in case of error */
<>	144:ef7eb2e8f9f7	4455	hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
<>	144:ef7eb2e8f9f7	4456	}
<>	144:ef7eb2e8f9f7	4457	}
<>	144:ef7eb2e8f9f7	4458	else if(hi2c->hdmarx != NULL)
<>	144:ef7eb2e8f9f7	4459	{
<>	144:ef7eb2e8f9f7	4460	/* Set the DMA Abort callback :
<>	144:ef7eb2e8f9f7	4461	will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
<>	144:ef7eb2e8f9f7	4462	hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
<>	144:ef7eb2e8f9f7	4463
<>	144:ef7eb2e8f9f7	4464	if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
<>	144:ef7eb2e8f9f7	4465	{
<>	144:ef7eb2e8f9f7	4466	/* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
<>	144:ef7eb2e8f9f7	4467	hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
<>	144:ef7eb2e8f9f7	4468	}
<>	144:ef7eb2e8f9f7	4469	}
<>	144:ef7eb2e8f9f7	4470	}
<>	144:ef7eb2e8f9f7	4471	else if(hi2c->State == HAL_I2C_STATE_ABORT)
<>	144:ef7eb2e8f9f7	4472	{
<>	144:ef7eb2e8f9f7	4473	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4474
<>	144:ef7eb2e8f9f7	4475	/* Call the corresponding callback to inform upper layer of End of Transfer */
<>	144:ef7eb2e8f9f7	4476	HAL_I2C_AbortCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	4477	}
<>	144:ef7eb2e8f9f7	4478	else
<>	144:ef7eb2e8f9f7	4479	{
<>	144:ef7eb2e8f9f7	4480	/* Call user error callback */
<>	144:ef7eb2e8f9f7	4481	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	4482	}
<>	144:ef7eb2e8f9f7	4483	/* STOP Flag is not set after a NACK reception */
<>	144:ef7eb2e8f9f7	4484	/* So may inform upper layer that listen phase is stopped */
<>	144:ef7eb2e8f9f7	4485	/* during NACK error treatment */
<>	144:ef7eb2e8f9f7	4486	if((hi2c->State == HAL_I2C_STATE_LISTEN) && ((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF))
<>	144:ef7eb2e8f9f7	4487	{
<>	144:ef7eb2e8f9f7	4488	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	4489	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	4490	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4491	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	4492
<>	144:ef7eb2e8f9f7	4493	/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
<>	144:ef7eb2e8f9f7	4494	HAL_I2C_ListenCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	4495	}
<>	144:ef7eb2e8f9f7	4496	}
<>	144:ef7eb2e8f9f7	4497
<>	144:ef7eb2e8f9f7	4498	/**
<>	144:ef7eb2e8f9f7	4499	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4500	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4501	* @param DevAddress Target device address: The device 7 bits address value
<>	144:ef7eb2e8f9f7	4502	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	4503	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	4504	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	4505	* @retval HAL status
<>	144:ef7eb2e8f9f7	4506	*/
<>	144:ef7eb2e8f9f7	4507	static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	4508	{
<>	144:ef7eb2e8f9f7	4509	/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	4510	uint32_t CurrentXferOptions = hi2c->XferOptions;
<>	144:ef7eb2e8f9f7	4511
<>	144:ef7eb2e8f9f7	4512	/* Generate Start condition if first transfer */
<>	144:ef7eb2e8f9f7	4513	if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) \|\| (CurrentXferOptions == I2C_FIRST_FRAME) \|\| (CurrentXferOptions == I2C_NO_OPTION_FRAME))
<>	144:ef7eb2e8f9f7	4514	{
<>	144:ef7eb2e8f9f7	4515	/* Generate Start */
<>	144:ef7eb2e8f9f7	4516	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	4517	}
<>	144:ef7eb2e8f9f7	4518	else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
<>	144:ef7eb2e8f9f7	4519	{
<>	144:ef7eb2e8f9f7	4520	/* Generate ReStart */
<>	144:ef7eb2e8f9f7	4521	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	4522	}
<>	144:ef7eb2e8f9f7	4523
<>	144:ef7eb2e8f9f7	4524	/* Wait until SB flag is set */
<>	144:ef7eb2e8f9f7	4525	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4526	{
<>	144:ef7eb2e8f9f7	4527	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4528	}
<>	144:ef7eb2e8f9f7	4529
<>	144:ef7eb2e8f9f7	4530	if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
<>	144:ef7eb2e8f9f7	4531	{
<>	144:ef7eb2e8f9f7	4532	/* Send slave address */
<>	144:ef7eb2e8f9f7	4533	hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
<>	144:ef7eb2e8f9f7	4534	}
<>	144:ef7eb2e8f9f7	4535	else
<>	144:ef7eb2e8f9f7	4536	{
<>	144:ef7eb2e8f9f7	4537	/* Send header of slave address */
<>	144:ef7eb2e8f9f7	4538	hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
<>	144:ef7eb2e8f9f7	4539
<>	144:ef7eb2e8f9f7	4540	/* Wait until ADD10 flag is set */
<>	144:ef7eb2e8f9f7	4541	if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4542	{
<>	144:ef7eb2e8f9f7	4543	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4544	{
<>	144:ef7eb2e8f9f7	4545	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4546	}
<>	144:ef7eb2e8f9f7	4547	else
<>	144:ef7eb2e8f9f7	4548	{
<>	144:ef7eb2e8f9f7	4549	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4550	}
<>	144:ef7eb2e8f9f7	4551	}
<>	144:ef7eb2e8f9f7	4552
<>	144:ef7eb2e8f9f7	4553	/* Send slave address */
<>	144:ef7eb2e8f9f7	4554	hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
<>	144:ef7eb2e8f9f7	4555	}
<>	144:ef7eb2e8f9f7	4556
<>	144:ef7eb2e8f9f7	4557	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	4558	if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4559	{
<>	144:ef7eb2e8f9f7	4560	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4561	{
<>	144:ef7eb2e8f9f7	4562	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4563	}
<>	144:ef7eb2e8f9f7	4564	else
<>	144:ef7eb2e8f9f7	4565	{
<>	144:ef7eb2e8f9f7	4566	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4567	}
<>	144:ef7eb2e8f9f7	4568	}
<>	144:ef7eb2e8f9f7	4569
<>	144:ef7eb2e8f9f7	4570	return HAL_OK;
<>	144:ef7eb2e8f9f7	4571	}
<>	144:ef7eb2e8f9f7	4572
<>	144:ef7eb2e8f9f7	4573	/**
<>	144:ef7eb2e8f9f7	4574	* @brief Master sends target device address for read request.
<>	144:ef7eb2e8f9f7	4575	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4576	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4577	* @param DevAddress Target device address: The device 7 bits address value
<>	144:ef7eb2e8f9f7	4578	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	4579	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	4580	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	4581	* @retval HAL status
<>	144:ef7eb2e8f9f7	4582	*/
<>	144:ef7eb2e8f9f7	4583	static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	4584	{
<>	144:ef7eb2e8f9f7	4585	/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	4586	uint32_t CurrentXferOptions = hi2c->XferOptions;
<>	144:ef7eb2e8f9f7	4587
<>	144:ef7eb2e8f9f7	4588	/* Generate Start condition if first transfer */
<>	144:ef7eb2e8f9f7	4589	if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) \|\| (CurrentXferOptions == I2C_FIRST_FRAME) \|\| (CurrentXferOptions == I2C_NO_OPTION_FRAME))
<>	144:ef7eb2e8f9f7	4590	{
<>	144:ef7eb2e8f9f7	4591	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	4592	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4593
<>	144:ef7eb2e8f9f7	4594	/* Generate Start */
<>	144:ef7eb2e8f9f7	4595	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	4596	}
<>	144:ef7eb2e8f9f7	4597	else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
<>	144:ef7eb2e8f9f7	4598	{
<>	144:ef7eb2e8f9f7	4599	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	4600	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4601
<>	144:ef7eb2e8f9f7	4602	/* Generate ReStart */
<>	144:ef7eb2e8f9f7	4603	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	4604	}
<>	144:ef7eb2e8f9f7	4605
<>	144:ef7eb2e8f9f7	4606	/* Wait until SB flag is set */
<>	144:ef7eb2e8f9f7	4607	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4608	{
<>	144:ef7eb2e8f9f7	4609	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4610	}
<>	144:ef7eb2e8f9f7	4611
<>	144:ef7eb2e8f9f7	4612	if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
<>	144:ef7eb2e8f9f7	4613	{
<>	144:ef7eb2e8f9f7	4614	/* Send slave address */
<>	144:ef7eb2e8f9f7	4615	hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
<>	144:ef7eb2e8f9f7	4616	}
<>	144:ef7eb2e8f9f7	4617	else
<>	144:ef7eb2e8f9f7	4618	{
<>	144:ef7eb2e8f9f7	4619	/* Send header of slave address */
<>	144:ef7eb2e8f9f7	4620	hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
<>	144:ef7eb2e8f9f7	4621
<>	144:ef7eb2e8f9f7	4622	/* Wait until ADD10 flag is set */
<>	144:ef7eb2e8f9f7	4623	if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4624	{
<>	144:ef7eb2e8f9f7	4625	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4626	{
<>	144:ef7eb2e8f9f7	4627	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4628	}
<>	144:ef7eb2e8f9f7	4629	else
<>	144:ef7eb2e8f9f7	4630	{
<>	144:ef7eb2e8f9f7	4631	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4632	}
<>	144:ef7eb2e8f9f7	4633	}
<>	144:ef7eb2e8f9f7	4634
<>	144:ef7eb2e8f9f7	4635	/* Send slave address */
<>	144:ef7eb2e8f9f7	4636	hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
<>	144:ef7eb2e8f9f7	4637
<>	144:ef7eb2e8f9f7	4638	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	4639	if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4640	{
<>	144:ef7eb2e8f9f7	4641	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4642	{
<>	144:ef7eb2e8f9f7	4643	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4644	}
<>	144:ef7eb2e8f9f7	4645	else
<>	144:ef7eb2e8f9f7	4646	{
<>	144:ef7eb2e8f9f7	4647	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4648	}
<>	144:ef7eb2e8f9f7	4649	}
<>	144:ef7eb2e8f9f7	4650
<>	144:ef7eb2e8f9f7	4651	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	4652	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4653
<>	144:ef7eb2e8f9f7	4654	/* Generate Restart */
<>	144:ef7eb2e8f9f7	4655	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	4656
<>	144:ef7eb2e8f9f7	4657	/* Wait until SB flag is set */
<>	144:ef7eb2e8f9f7	4658	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4659	{
<>	144:ef7eb2e8f9f7	4660	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4661	}
<>	144:ef7eb2e8f9f7	4662
<>	144:ef7eb2e8f9f7	4663	/* Send header of slave address */
<>	144:ef7eb2e8f9f7	4664	hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress);
<>	144:ef7eb2e8f9f7	4665	}
<>	144:ef7eb2e8f9f7	4666
<>	144:ef7eb2e8f9f7	4667	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	4668	if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4669	{
<>	144:ef7eb2e8f9f7	4670	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4671	{
<>	144:ef7eb2e8f9f7	4672	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4673	}
<>	144:ef7eb2e8f9f7	4674	else
<>	144:ef7eb2e8f9f7	4675	{
<>	144:ef7eb2e8f9f7	4676	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4677	}
<>	144:ef7eb2e8f9f7	4678	}
<>	144:ef7eb2e8f9f7	4679
<>	144:ef7eb2e8f9f7	4680	return HAL_OK;
<>	144:ef7eb2e8f9f7	4681	}
<>	144:ef7eb2e8f9f7	4682
<>	144:ef7eb2e8f9f7	4683	/**
<>	144:ef7eb2e8f9f7	4684	* @brief Master sends target device address followed by internal memory address for write request.
<>	144:ef7eb2e8f9f7	4685	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4686	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4687	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	4688	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	4689	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	4690	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	4691	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	4692	* @retval HAL status
<>	144:ef7eb2e8f9f7	4693	*/
<>	144:ef7eb2e8f9f7	4694	static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	4695	{
<>	144:ef7eb2e8f9f7	4696	/* Generate Start */
<>	144:ef7eb2e8f9f7	4697	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	4698
<>	144:ef7eb2e8f9f7	4699	/* Wait until SB flag is set */
<>	144:ef7eb2e8f9f7	4700	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4701	{
<>	144:ef7eb2e8f9f7	4702	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4703	}
<>	144:ef7eb2e8f9f7	4704
<>	144:ef7eb2e8f9f7	4705	/* Send slave address */
<>	144:ef7eb2e8f9f7	4706	hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
<>	144:ef7eb2e8f9f7	4707
<>	144:ef7eb2e8f9f7	4708	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	4709	if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4710	{
<>	144:ef7eb2e8f9f7	4711	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4712	{
<>	144:ef7eb2e8f9f7	4713	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4714	}
<>	144:ef7eb2e8f9f7	4715	else
<>	144:ef7eb2e8f9f7	4716	{
<>	144:ef7eb2e8f9f7	4717	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4718	}
<>	144:ef7eb2e8f9f7	4719	}
<>	144:ef7eb2e8f9f7	4720
<>	144:ef7eb2e8f9f7	4721	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	4722	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4723
<>	144:ef7eb2e8f9f7	4724	/* Wait until TXE flag is set */
<>	144:ef7eb2e8f9f7	4725	if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4726	{
<>	144:ef7eb2e8f9f7	4727	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4728	{
<>	144:ef7eb2e8f9f7	4729	/* Generate Stop */
<>	144:ef7eb2e8f9f7	4730	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	4731	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4732	}
<>	144:ef7eb2e8f9f7	4733	else
<>	144:ef7eb2e8f9f7	4734	{
<>	144:ef7eb2e8f9f7	4735	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4736	}
<>	144:ef7eb2e8f9f7	4737	}
<>	144:ef7eb2e8f9f7	4738
<>	144:ef7eb2e8f9f7	4739	/* If Memory address size is 8Bit */
<>	144:ef7eb2e8f9f7	4740	if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
<>	144:ef7eb2e8f9f7	4741	{
<>	144:ef7eb2e8f9f7	4742	/* Send Memory Address */
<>	144:ef7eb2e8f9f7	4743	hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
<>	144:ef7eb2e8f9f7	4744	}
<>	144:ef7eb2e8f9f7	4745	/* If Memory address size is 16Bit */
<>	144:ef7eb2e8f9f7	4746	else
<>	144:ef7eb2e8f9f7	4747	{
<>	144:ef7eb2e8f9f7	4748	/* Send MSB of Memory Address */
<>	144:ef7eb2e8f9f7	4749	hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
<>	144:ef7eb2e8f9f7	4750
<>	144:ef7eb2e8f9f7	4751	/* Wait until TXE flag is set */
<>	144:ef7eb2e8f9f7	4752	if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4753	{
<>	144:ef7eb2e8f9f7	4754	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4755	{
<>	144:ef7eb2e8f9f7	4756	/* Generate Stop */
<>	144:ef7eb2e8f9f7	4757	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	4758	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4759	}
<>	144:ef7eb2e8f9f7	4760	else
<>	144:ef7eb2e8f9f7	4761	{
<>	144:ef7eb2e8f9f7	4762	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4763	}
<>	144:ef7eb2e8f9f7	4764	}
<>	144:ef7eb2e8f9f7	4765
<>	144:ef7eb2e8f9f7	4766	/* Send LSB of Memory Address */
<>	144:ef7eb2e8f9f7	4767	hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
<>	144:ef7eb2e8f9f7	4768	}
<>	144:ef7eb2e8f9f7	4769
<>	144:ef7eb2e8f9f7	4770	return HAL_OK;
<>	144:ef7eb2e8f9f7	4771	}
<>	144:ef7eb2e8f9f7	4772
<>	144:ef7eb2e8f9f7	4773	/**
<>	144:ef7eb2e8f9f7	4774	* @brief Master sends target device address followed by internal memory address for read request.
<>	144:ef7eb2e8f9f7	4775	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4776	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4777	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	4778	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	4779	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	4780	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	4781	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	4782	* @retval HAL status
<>	144:ef7eb2e8f9f7	4783	*/
<>	144:ef7eb2e8f9f7	4784	static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	4785	{
<>	144:ef7eb2e8f9f7	4786	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	4787	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4788
<>	144:ef7eb2e8f9f7	4789	/* Generate Start */
<>	144:ef7eb2e8f9f7	4790	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	4791
<>	144:ef7eb2e8f9f7	4792	/* Wait until SB flag is set */
<>	144:ef7eb2e8f9f7	4793	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4794	{
<>	144:ef7eb2e8f9f7	4795	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4796	}
<>	144:ef7eb2e8f9f7	4797
<>	144:ef7eb2e8f9f7	4798	/* Send slave address */
<>	144:ef7eb2e8f9f7	4799	hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
<>	144:ef7eb2e8f9f7	4800
<>	144:ef7eb2e8f9f7	4801	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	4802	if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4803	{
<>	144:ef7eb2e8f9f7	4804	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4805	{
<>	144:ef7eb2e8f9f7	4806	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4807	}
<>	144:ef7eb2e8f9f7	4808	else
<>	144:ef7eb2e8f9f7	4809	{
<>	144:ef7eb2e8f9f7	4810	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4811	}
<>	144:ef7eb2e8f9f7	4812	}
<>	144:ef7eb2e8f9f7	4813
<>	144:ef7eb2e8f9f7	4814	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	4815	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4816
<>	144:ef7eb2e8f9f7	4817	/* Wait until TXE flag is set */
<>	144:ef7eb2e8f9f7	4818	if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4819	{
<>	144:ef7eb2e8f9f7	4820	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4821	{
<>	144:ef7eb2e8f9f7	4822	/* Generate Stop */
<>	144:ef7eb2e8f9f7	4823	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	4824	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4825	}
<>	144:ef7eb2e8f9f7	4826	else
<>	144:ef7eb2e8f9f7	4827	{
<>	144:ef7eb2e8f9f7	4828	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4829	}
<>	144:ef7eb2e8f9f7	4830	}
<>	144:ef7eb2e8f9f7	4831
<>	144:ef7eb2e8f9f7	4832	/* If Memory address size is 8Bit */
<>	144:ef7eb2e8f9f7	4833	if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
<>	144:ef7eb2e8f9f7	4834	{
<>	144:ef7eb2e8f9f7	4835	/* Send Memory Address */
<>	144:ef7eb2e8f9f7	4836	hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
<>	144:ef7eb2e8f9f7	4837	}
<>	144:ef7eb2e8f9f7	4838	/* If Memory address size is 16Bit */
<>	144:ef7eb2e8f9f7	4839	else
<>	144:ef7eb2e8f9f7	4840	{
<>	144:ef7eb2e8f9f7	4841	/* Send MSB of Memory Address */
<>	144:ef7eb2e8f9f7	4842	hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
<>	144:ef7eb2e8f9f7	4843
<>	144:ef7eb2e8f9f7	4844	/* Wait until TXE flag is set */
<>	144:ef7eb2e8f9f7	4845	if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4846	{
<>	144:ef7eb2e8f9f7	4847	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4848	{
<>	144:ef7eb2e8f9f7	4849	/* Generate Stop */
<>	144:ef7eb2e8f9f7	4850	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	4851	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4852	}
<>	144:ef7eb2e8f9f7	4853	else
<>	144:ef7eb2e8f9f7	4854	{
<>	144:ef7eb2e8f9f7	4855	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4856	}
<>	144:ef7eb2e8f9f7	4857	}
<>	144:ef7eb2e8f9f7	4858
<>	144:ef7eb2e8f9f7	4859	/* Send LSB of Memory Address */
<>	144:ef7eb2e8f9f7	4860	hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
<>	144:ef7eb2e8f9f7	4861	}
<>	144:ef7eb2e8f9f7	4862
<>	144:ef7eb2e8f9f7	4863	/* Wait until TXE flag is set */
<>	144:ef7eb2e8f9f7	4864	if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4865	{
<>	144:ef7eb2e8f9f7	4866	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4867	{
<>	144:ef7eb2e8f9f7	4868	/* Generate Stop */
<>	144:ef7eb2e8f9f7	4869	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	4870	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4871	}
<>	144:ef7eb2e8f9f7	4872	else
<>	144:ef7eb2e8f9f7	4873	{
<>	144:ef7eb2e8f9f7	4874	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4875	}
<>	144:ef7eb2e8f9f7	4876	}
<>	144:ef7eb2e8f9f7	4877
<>	144:ef7eb2e8f9f7	4878	/* Generate Restart */
<>	144:ef7eb2e8f9f7	4879	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	4880
<>	144:ef7eb2e8f9f7	4881	/* Wait until SB flag is set */
<>	144:ef7eb2e8f9f7	4882	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4883	{
<>	144:ef7eb2e8f9f7	4884	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4885	}
<>	144:ef7eb2e8f9f7	4886
<>	144:ef7eb2e8f9f7	4887	/* Send slave address */
<>	144:ef7eb2e8f9f7	4888	hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
<>	144:ef7eb2e8f9f7	4889
<>	144:ef7eb2e8f9f7	4890	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	4891	if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4892	{
<>	144:ef7eb2e8f9f7	4893	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4894	{
<>	144:ef7eb2e8f9f7	4895	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4896	}
<>	144:ef7eb2e8f9f7	4897	else
<>	144:ef7eb2e8f9f7	4898	{
<>	144:ef7eb2e8f9f7	4899	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4900	}
<>	144:ef7eb2e8f9f7	4901	}
<>	144:ef7eb2e8f9f7	4902
<>	144:ef7eb2e8f9f7	4903	return HAL_OK;
<>	144:ef7eb2e8f9f7	4904	}
<>	144:ef7eb2e8f9f7	4905
<>	144:ef7eb2e8f9f7	4906	/**
<>	144:ef7eb2e8f9f7	4907	* @brief DMA I2C process complete callback.
<>	144:ef7eb2e8f9f7	4908	* @param hdma DMA handle
<>	144:ef7eb2e8f9f7	4909	* @retval None
<>	144:ef7eb2e8f9f7	4910	*/
<>	144:ef7eb2e8f9f7	4911	static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	4912	{
<>	144:ef7eb2e8f9f7	4913	I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
<>	144:ef7eb2e8f9f7	4914
<>	144:ef7eb2e8f9f7	4915	/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	4916	uint32_t CurrentState = hi2c->State;
<>	144:ef7eb2e8f9f7	4917	uint32_t CurrentMode = hi2c->Mode;
<>	144:ef7eb2e8f9f7	4918
<>	144:ef7eb2e8f9f7	4919	if((CurrentState == HAL_I2C_STATE_BUSY_TX) \|\| ((CurrentState == HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE)))
<>	144:ef7eb2e8f9f7	4920	{
<>	144:ef7eb2e8f9f7	4921	/* Disable DMA Request */
<>	144:ef7eb2e8f9f7	4922	hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
<>	144:ef7eb2e8f9f7	4923
<>	144:ef7eb2e8f9f7	4924	hi2c->XferCount = 0U;
<>	144:ef7eb2e8f9f7	4925
<>	144:ef7eb2e8f9f7	4926	/* Enable EVT and ERR interrupt */
<>	144:ef7eb2e8f9f7	4927	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	4928	}
<>	144:ef7eb2e8f9f7	4929	else
<>	144:ef7eb2e8f9f7	4930	{
<>	144:ef7eb2e8f9f7	4931	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	4932	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4933
<>	144:ef7eb2e8f9f7	4934	/* Generate Stop */
<>	144:ef7eb2e8f9f7	4935	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	4936
<>	144:ef7eb2e8f9f7	4937	/* Disable Last DMA */
<>	144:ef7eb2e8f9f7	4938	hi2c->Instance->CR2 &= ~I2C_CR2_LAST;
<>	144:ef7eb2e8f9f7	4939
<>	144:ef7eb2e8f9f7	4940	/* Disable DMA Request */
<>	144:ef7eb2e8f9f7	4941	hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
<>	144:ef7eb2e8f9f7	4942
<>	144:ef7eb2e8f9f7	4943	hi2c->XferCount = 0U;
<>	144:ef7eb2e8f9f7	4944
<>	144:ef7eb2e8f9f7	4945	/* Check if Errors has been detected during transfer */
<>	144:ef7eb2e8f9f7	4946	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
<>	144:ef7eb2e8f9f7	4947	{
<>	144:ef7eb2e8f9f7	4948	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	4949	}
<>	144:ef7eb2e8f9f7	4950	else
<>	144:ef7eb2e8f9f7	4951	{
<>	144:ef7eb2e8f9f7	4952	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4953
<>	144:ef7eb2e8f9f7	4954	if(hi2c->Mode == HAL_I2C_MODE_MEM)
<>	144:ef7eb2e8f9f7	4955	{
<>	144:ef7eb2e8f9f7	4956	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	4957
<>	144:ef7eb2e8f9f7	4958	HAL_I2C_MemRxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	4959	}
<>	144:ef7eb2e8f9f7	4960	else
<>	144:ef7eb2e8f9f7	4961	{
<>	144:ef7eb2e8f9f7	4962	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	4963
<>	144:ef7eb2e8f9f7	4964	HAL_I2C_MasterRxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	4965	}
<>	144:ef7eb2e8f9f7	4966	}
<>	144:ef7eb2e8f9f7	4967	}
<>	144:ef7eb2e8f9f7	4968	}
<>	144:ef7eb2e8f9f7	4969
<>	144:ef7eb2e8f9f7	4970	/**
<>	144:ef7eb2e8f9f7	4971	* @brief DMA I2C communication error callback.
<>	144:ef7eb2e8f9f7	4972	* @param hdma DMA handle
<>	144:ef7eb2e8f9f7	4973	* @retval None
<>	144:ef7eb2e8f9f7	4974	*/
<>	144:ef7eb2e8f9f7	4975	static void I2C_DMAError(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	4976	{
<>	144:ef7eb2e8f9f7	4977	I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
<>	144:ef7eb2e8f9f7	4978
<>	144:ef7eb2e8f9f7	4979	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	4980	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4981
<>	144:ef7eb2e8f9f7	4982	hi2c->XferCount = 0U;
<>	144:ef7eb2e8f9f7	4983
<>	144:ef7eb2e8f9f7	4984	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4985	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	4986
<>	144:ef7eb2e8f9f7	4987	hi2c->ErrorCode \|= HAL_I2C_ERROR_DMA;
<>	144:ef7eb2e8f9f7	4988
<>	144:ef7eb2e8f9f7	4989	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	4990	}
<>	144:ef7eb2e8f9f7	4991
<>	144:ef7eb2e8f9f7	4992	/**
<>	144:ef7eb2e8f9f7	4993	* @brief DMA I2C communication abort callback
<>	144:ef7eb2e8f9f7	4994	* (To be called at end of DMA Abort procedure).
<>	144:ef7eb2e8f9f7	4995	* @param hdma: DMA handle.
<>	144:ef7eb2e8f9f7	4996	* @retval None
<>	144:ef7eb2e8f9f7	4997	*/
<>	144:ef7eb2e8f9f7	4998	static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	4999	{
<>	144:ef7eb2e8f9f7	5000	I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	5001
<>	144:ef7eb2e8f9f7	5002	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	5003	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	5004
<>	144:ef7eb2e8f9f7	5005	hi2c->XferCount = 0U;
<>	144:ef7eb2e8f9f7	5006
<>	144:ef7eb2e8f9f7	5007	/* Reset XferAbortCallback */
<>	144:ef7eb2e8f9f7	5008	hi2c->hdmatx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	5009	hi2c->hdmarx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	5010
<>	144:ef7eb2e8f9f7	5011	/* Check if come from abort from user */
<>	144:ef7eb2e8f9f7	5012	if(hi2c->State == HAL_I2C_STATE_ABORT)
<>	144:ef7eb2e8f9f7	5013	{
<>	144:ef7eb2e8f9f7	5014	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5015	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	5016
<>	144:ef7eb2e8f9f7	5017	/* Call the corresponding callback to inform upper layer of End of Transfer */
<>	144:ef7eb2e8f9f7	5018	HAL_I2C_AbortCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	5019	}
<>	144:ef7eb2e8f9f7	5020	else
<>	144:ef7eb2e8f9f7	5021	{
<>	144:ef7eb2e8f9f7	5022	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5023	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	5024
<>	144:ef7eb2e8f9f7	5025	/* Call the corresponding callback to inform upper layer of End of Transfer */
<>	144:ef7eb2e8f9f7	5026	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	5027	}
<>	144:ef7eb2e8f9f7	5028	}
<>	144:ef7eb2e8f9f7	5029
<>	144:ef7eb2e8f9f7	5030	/**
<>	144:ef7eb2e8f9f7	5031	* @brief This function handles I2C Communication Timeout.
<>	144:ef7eb2e8f9f7	5032	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	5033	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	5034	* @param Flag specifies the I2C flag to check.
<>	144:ef7eb2e8f9f7	5035	* @param Status The new Flag status (SET or RESET).
<>	144:ef7eb2e8f9f7	5036	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	5037	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	5038	* @retval HAL status
<>	144:ef7eb2e8f9f7	5039	*/
<>	144:ef7eb2e8f9f7	5040	static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	5041	{
<>	144:ef7eb2e8f9f7	5042	/* Wait until flag is set */
<>	144:ef7eb2e8f9f7	5043	while((__HAL_I2C_GET_FLAG(hi2c, Flag) ? SET : RESET) == Status)
<>	144:ef7eb2e8f9f7	5044	{
<>	144:ef7eb2e8f9f7	5045	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	5046	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	5047	{
<>	144:ef7eb2e8f9f7	5048	if((Timeout == 0U)\|\|((HAL_GetTick() - Tickstart ) > Timeout))
<>	144:ef7eb2e8f9f7	5049	{
<>	144:ef7eb2e8f9f7	5050	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	5051	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5052
<>	144:ef7eb2e8f9f7	5053	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	5054	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	5055
<>	144:ef7eb2e8f9f7	5056	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5057	}
<>	144:ef7eb2e8f9f7	5058	}
<>	144:ef7eb2e8f9f7	5059	}
<>	144:ef7eb2e8f9f7	5060
<>	144:ef7eb2e8f9f7	5061	return HAL_OK;
<>	144:ef7eb2e8f9f7	5062	}
<>	144:ef7eb2e8f9f7	5063
<>	144:ef7eb2e8f9f7	5064	/**
<>	144:ef7eb2e8f9f7	5065	* @brief This function handles I2C Communication Timeout for Master addressing phase.
<>	144:ef7eb2e8f9f7	5066	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	5067	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	5068	* @param Flag specifies the I2C flag to check.
<>	144:ef7eb2e8f9f7	5069	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	5070	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	5071	* @retval HAL status
<>	144:ef7eb2e8f9f7	5072	*/
<>	144:ef7eb2e8f9f7	5073	static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	5074	{
<>	144:ef7eb2e8f9f7	5075	while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
<>	144:ef7eb2e8f9f7	5076	{
<>	144:ef7eb2e8f9f7	5077	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
<>	144:ef7eb2e8f9f7	5078	{
<>	144:ef7eb2e8f9f7	5079	/* Generate Stop */
<>	144:ef7eb2e8f9f7	5080	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	5081
<>	144:ef7eb2e8f9f7	5082	/* Clear AF Flag */
<>	144:ef7eb2e8f9f7	5083	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	5084
<>	144:ef7eb2e8f9f7	5085	hi2c->ErrorCode = HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	5086	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	5087	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5088
<>	144:ef7eb2e8f9f7	5089	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	5090	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	5091
<>	144:ef7eb2e8f9f7	5092	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5093	}
<>	144:ef7eb2e8f9f7	5094
<>	144:ef7eb2e8f9f7	5095	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	5096	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	5097	{
<>	144:ef7eb2e8f9f7	5098	if((Timeout == 0U)\|\|((HAL_GetTick() - Tickstart ) > Timeout))
<>	144:ef7eb2e8f9f7	5099	{
<>	144:ef7eb2e8f9f7	5100	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	5101	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5102
<>	144:ef7eb2e8f9f7	5103	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	5104	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	5105
<>	144:ef7eb2e8f9f7	5106	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5107	}
<>	144:ef7eb2e8f9f7	5108	}
<>	144:ef7eb2e8f9f7	5109	}
<>	144:ef7eb2e8f9f7	5110	return HAL_OK;
<>	144:ef7eb2e8f9f7	5111	}
<>	144:ef7eb2e8f9f7	5112
<>	144:ef7eb2e8f9f7	5113	/**
<>	144:ef7eb2e8f9f7	5114	* @brief This function handles I2C Communication Timeout for specific usage of TXE flag.
<>	144:ef7eb2e8f9f7	5115	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	5116	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	5117	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	5118	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	5119	* @retval HAL status
<>	144:ef7eb2e8f9f7	5120	*/
<>	144:ef7eb2e8f9f7	5121	static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	5122	{
<>	144:ef7eb2e8f9f7	5123	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
<>	144:ef7eb2e8f9f7	5124	{
<>	144:ef7eb2e8f9f7	5125	/* Check if a NACK is detected */
<>	144:ef7eb2e8f9f7	5126	if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
<>	144:ef7eb2e8f9f7	5127	{
<>	144:ef7eb2e8f9f7	5128	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5129	}
<>	144:ef7eb2e8f9f7	5130
<>	144:ef7eb2e8f9f7	5131	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	5132	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	5133	{
<>	144:ef7eb2e8f9f7	5134	if((Timeout == 0U) \|\| ((HAL_GetTick()-Tickstart) > Timeout))
<>	144:ef7eb2e8f9f7	5135	{
<>	144:ef7eb2e8f9f7	5136	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	5137	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	5138	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5139
<>	144:ef7eb2e8f9f7	5140	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	5141	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	5142
<>	144:ef7eb2e8f9f7	5143	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5144	}
<>	144:ef7eb2e8f9f7	5145	}
<>	144:ef7eb2e8f9f7	5146	}
<>	144:ef7eb2e8f9f7	5147	return HAL_OK;
<>	144:ef7eb2e8f9f7	5148	}
<>	144:ef7eb2e8f9f7	5149
<>	144:ef7eb2e8f9f7	5150	/**
<>	144:ef7eb2e8f9f7	5151	* @brief This function handles I2C Communication Timeout for specific usage of BTF flag.
<>	144:ef7eb2e8f9f7	5152	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	5153	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	5154	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	5155	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	5156	* @retval HAL status
<>	144:ef7eb2e8f9f7	5157	*/
<>	144:ef7eb2e8f9f7	5158	static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	5159	{
<>	144:ef7eb2e8f9f7	5160	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
<>	144:ef7eb2e8f9f7	5161	{
<>	144:ef7eb2e8f9f7	5162	/* Check if a NACK is detected */
<>	144:ef7eb2e8f9f7	5163	if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
<>	144:ef7eb2e8f9f7	5164	{
<>	144:ef7eb2e8f9f7	5165	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5166	}
<>	144:ef7eb2e8f9f7	5167
<>	144:ef7eb2e8f9f7	5168	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	5169	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	5170	{
<>	144:ef7eb2e8f9f7	5171	if((Timeout == 0U) \|\| ((HAL_GetTick()-Tickstart) > Timeout))
<>	144:ef7eb2e8f9f7	5172	{
<>	144:ef7eb2e8f9f7	5173	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	5174	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	5175	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5176
<>	144:ef7eb2e8f9f7	5177	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	5178	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	5179
<>	144:ef7eb2e8f9f7	5180	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5181	}
<>	144:ef7eb2e8f9f7	5182	}
<>	144:ef7eb2e8f9f7	5183	}
<>	144:ef7eb2e8f9f7	5184	return HAL_OK;
<>	144:ef7eb2e8f9f7	5185	}
<>	144:ef7eb2e8f9f7	5186
<>	144:ef7eb2e8f9f7	5187	/**
<>	144:ef7eb2e8f9f7	5188	* @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
<>	144:ef7eb2e8f9f7	5189	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	5190	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	5191	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	5192	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	5193	* @retval HAL status
<>	144:ef7eb2e8f9f7	5194	*/
<>	144:ef7eb2e8f9f7	5195	static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	5196	{
<>	144:ef7eb2e8f9f7	5197	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
<>	144:ef7eb2e8f9f7	5198	{
<>	144:ef7eb2e8f9f7	5199	/* Check if a NACK is detected */
<>	144:ef7eb2e8f9f7	5200	if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
<>	144:ef7eb2e8f9f7	5201	{
<>	144:ef7eb2e8f9f7	5202	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5203	}
<>	144:ef7eb2e8f9f7	5204
<>	144:ef7eb2e8f9f7	5205	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	5206	if((Timeout == 0U) \|\| ((HAL_GetTick()-Tickstart) > Timeout))
<>	144:ef7eb2e8f9f7	5207	{
<>	144:ef7eb2e8f9f7	5208	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	5209	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	5210	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5211
<>	144:ef7eb2e8f9f7	5212	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	5213	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	5214
<>	144:ef7eb2e8f9f7	5215	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5216	}
<>	144:ef7eb2e8f9f7	5217	}
<>	144:ef7eb2e8f9f7	5218	return HAL_OK;
<>	144:ef7eb2e8f9f7	5219	}
<>	144:ef7eb2e8f9f7	5220
<>	144:ef7eb2e8f9f7	5221	/**
<>	144:ef7eb2e8f9f7	5222	* @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
<>	144:ef7eb2e8f9f7	5223	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	5224	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	5225	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	5226	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	5227	* @retval HAL status
<>	144:ef7eb2e8f9f7	5228	*/
<>	144:ef7eb2e8f9f7	5229	static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	5230	{
<>	144:ef7eb2e8f9f7	5231
<>	144:ef7eb2e8f9f7	5232	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
<>	144:ef7eb2e8f9f7	5233	{
<>	144:ef7eb2e8f9f7	5234	/* Check if a STOPF is detected */
<>	144:ef7eb2e8f9f7	5235	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
<>	144:ef7eb2e8f9f7	5236	{
<>	144:ef7eb2e8f9f7	5237	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	5238	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	5239
<>	144:ef7eb2e8f9f7	5240	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	5241	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	5242	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5243
<>	144:ef7eb2e8f9f7	5244	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	5245	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	5246
<>	144:ef7eb2e8f9f7	5247	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5248	}
<>	144:ef7eb2e8f9f7	5249
<>	144:ef7eb2e8f9f7	5250	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	5251	if((Timeout == 0U) \|\| ((HAL_GetTick()-Tickstart) > Timeout))
<>	144:ef7eb2e8f9f7	5252	{
<>	144:ef7eb2e8f9f7	5253	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	5254	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5255
<>	144:ef7eb2e8f9f7	5256	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	5257	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	5258
<>	144:ef7eb2e8f9f7	5259	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5260	}
<>	144:ef7eb2e8f9f7	5261	}
<>	144:ef7eb2e8f9f7	5262	return HAL_OK;
<>	144:ef7eb2e8f9f7	5263	}
<>	144:ef7eb2e8f9f7	5264
<>	144:ef7eb2e8f9f7	5265	/**
<>	144:ef7eb2e8f9f7	5266	* @brief This function handles Acknowledge failed detection during an I2C Communication.
<>	144:ef7eb2e8f9f7	5267	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	5268	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	5269	* @retval HAL status
<>	144:ef7eb2e8f9f7	5270	*/
<>	144:ef7eb2e8f9f7	5271	static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	5272	{
<>	144:ef7eb2e8f9f7	5273	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
<>	144:ef7eb2e8f9f7	5274	{
<>	144:ef7eb2e8f9f7	5275	/* Clear NACKF Flag */
<>	144:ef7eb2e8f9f7	5276	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	5277
<>	144:ef7eb2e8f9f7	5278	hi2c->ErrorCode = HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	5279	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	5280	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5281
<>	144:ef7eb2e8f9f7	5282	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	5283	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	5284
<>	144:ef7eb2e8f9f7	5285	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5286	}
<>	144:ef7eb2e8f9f7	5287	return HAL_OK;
<>	144:ef7eb2e8f9f7	5288	}
<>	144:ef7eb2e8f9f7	5289	/**
<>	144:ef7eb2e8f9f7	5290	* @}
<>	144:ef7eb2e8f9f7	5291	*/
<>	144:ef7eb2e8f9f7	5292
<>	144:ef7eb2e8f9f7	5293	#endif /* HAL_I2C_MODULE_ENABLED */
<>	144:ef7eb2e8f9f7	5294
<>	144:ef7eb2e8f9f7	5295	/**
<>	144:ef7eb2e8f9f7	5296	* @}
<>	144:ef7eb2e8f9f7	5297	*/
<>	144:ef7eb2e8f9f7	5298
<>	144:ef7eb2e8f9f7	5299	/**
<>	144:ef7eb2e8f9f7	5300	* @}
<>	144:ef7eb2e8f9f7	5301	*/
<>	144:ef7eb2e8f9f7	5302
<>	144:ef7eb2e8f9f7	5303	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/