mbed official / USBHost

USBHost library. NOTE: This library is only officially supported on the LPC1768 platform. For more information, please see the handbook page.

Dependencies:   FATFileSystem mbed-rtos

Dependents:   BTstack WallbotWii SD to Flash Data Transfer USBHost-MSD_HelloWorld ... more

Legacy Warning

This is an mbed 2 library. To learn more about mbed OS 5, visit the docs.

Pull requests against this repository are no longer supported. Please raise against mbed OS 5 as documented above.

USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb0/src/userdef/usb0_host_dmacdrv.c@35:f72ccc6892ee, 2016-04-29 (annotated)

Committer:
mbed_official
Date:
Fri Apr 29 01:16:38 2016 +0100
Revision:
35:f72ccc6892ee
Synchronized with git revision fe9720f24b1adc71ab6962506ec51290f6afd270



Full URL: https://github.com/mbedmicro/mbed/commit/fe9720f24b1adc71ab6962506ec51290f6afd270/



[Renesas RZ/A1H] Enable asynchronous communications

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 35:f72ccc6892ee 1 /*******************************************************************************
mbed_official 35:f72ccc6892ee 2 * DISCLAIMER
mbed_official 35:f72ccc6892ee 3 * This software is supplied by Renesas Electronics Corporation and is only
mbed_official 35:f72ccc6892ee 4 * intended for use with Renesas products. No other uses are authorized. This
mbed_official 35:f72ccc6892ee 5 * software is owned by Renesas Electronics Corporation and is protected under
mbed_official 35:f72ccc6892ee 6 * all applicable laws, including copyright laws.
mbed_official 35:f72ccc6892ee 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
mbed_official 35:f72ccc6892ee 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
mbed_official 35:f72ccc6892ee 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
mbed_official 35:f72ccc6892ee 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
mbed_official 35:f72ccc6892ee 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
mbed_official 35:f72ccc6892ee 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
mbed_official 35:f72ccc6892ee 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
mbed_official 35:f72ccc6892ee 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
mbed_official 35:f72ccc6892ee 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
mbed_official 35:f72ccc6892ee 16 * Renesas reserves the right, without notice, to make changes to this software
mbed_official 35:f72ccc6892ee 17 * and to discontinue the availability of this software. By using this software,
mbed_official 35:f72ccc6892ee 18 * you agree to the additional terms and conditions found by accessing the
mbed_official 35:f72ccc6892ee 19 * following link:
mbed_official 35:f72ccc6892ee 20 * http://www.renesas.com/disclaimer
mbed_official 35:f72ccc6892ee 21 * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
mbed_official 35:f72ccc6892ee 22 *******************************************************************************/
mbed_official 35:f72ccc6892ee 23 /*******************************************************************************
mbed_official 35:f72ccc6892ee 24 * File Name : usb0_host_dmacdrv.c
mbed_official 35:f72ccc6892ee 25 * $Rev: 1116 $
mbed_official 35:f72ccc6892ee 26 * $Date:: 2014-07-09 16:29:19 +0900#$
mbed_official 35:f72ccc6892ee 27 * Device(s) : RZ/A1H
mbed_official 35:f72ccc6892ee 28 * Tool-Chain :
mbed_official 35:f72ccc6892ee 29 * OS : None
mbed_official 35:f72ccc6892ee 30 * H/W Platform :
mbed_official 35:f72ccc6892ee 31 * Description : RZ/A1H R7S72100 USB Sample Program
mbed_official 35:f72ccc6892ee 32 * Operation :
mbed_official 35:f72ccc6892ee 33 * Limitations :
mbed_official 35:f72ccc6892ee 34 *******************************************************************************/
mbed_official 35:f72ccc6892ee 35
mbed_official 35:f72ccc6892ee 36
mbed_official 35:f72ccc6892ee 37 /*******************************************************************************
mbed_official 35:f72ccc6892ee 38 Includes <System Includes> , "Project Includes"
mbed_official 35:f72ccc6892ee 39 *******************************************************************************/
mbed_official 35:f72ccc6892ee 40 #include "r_typedefs.h"
mbed_official 35:f72ccc6892ee 41 #include "iodefine.h"
mbed_official 35:f72ccc6892ee 42 #include "rza_io_regrw.h"
mbed_official 35:f72ccc6892ee 43 #include "usb0_host_dmacdrv.h"
mbed_official 35:f72ccc6892ee 44
mbed_official 35:f72ccc6892ee 45
mbed_official 35:f72ccc6892ee 46 /*******************************************************************************
mbed_official 35:f72ccc6892ee 47 Typedef definitions
mbed_official 35:f72ccc6892ee 48 *******************************************************************************/
mbed_official 35:f72ccc6892ee 49
mbed_official 35:f72ccc6892ee 50
mbed_official 35:f72ccc6892ee 51 /*******************************************************************************
mbed_official 35:f72ccc6892ee 52 Macro definitions
mbed_official 35:f72ccc6892ee 53 *******************************************************************************/
mbed_official 35:f72ccc6892ee 54 #define DMAC_INDEFINE (255) /* Macro definition when REQD bit is not used */
mbed_official 35:f72ccc6892ee 55
mbed_official 35:f72ccc6892ee 56 /* ==== Request setting information for on-chip peripheral module ==== */
mbed_official 35:f72ccc6892ee 57 typedef enum dmac_peri_req_reg_type
mbed_official 35:f72ccc6892ee 58 {
mbed_official 35:f72ccc6892ee 59 DMAC_REQ_MID,
mbed_official 35:f72ccc6892ee 60 DMAC_REQ_RID,
mbed_official 35:f72ccc6892ee 61 DMAC_REQ_AM,
mbed_official 35:f72ccc6892ee 62 DMAC_REQ_LVL,
mbed_official 35:f72ccc6892ee 63 DMAC_REQ_REQD
mbed_official 35:f72ccc6892ee 64 } dmac_peri_req_reg_type_t;
mbed_official 35:f72ccc6892ee 65
mbed_official 35:f72ccc6892ee 66
mbed_official 35:f72ccc6892ee 67 /*******************************************************************************
mbed_official 35:f72ccc6892ee 68 Imported global variables and functions (from other files)
mbed_official 35:f72ccc6892ee 69 *******************************************************************************/
mbed_official 35:f72ccc6892ee 70
mbed_official 35:f72ccc6892ee 71
mbed_official 35:f72ccc6892ee 72 /*******************************************************************************
mbed_official 35:f72ccc6892ee 73 Exported global variables and functions (to be accessed by other files)
mbed_official 35:f72ccc6892ee 74 *******************************************************************************/
mbed_official 35:f72ccc6892ee 75
mbed_official 35:f72ccc6892ee 76
mbed_official 35:f72ccc6892ee 77 /*******************************************************************************
mbed_official 35:f72ccc6892ee 78 Private global variables and functions
mbed_official 35:f72ccc6892ee 79 *******************************************************************************/
mbed_official 35:f72ccc6892ee 80 /* ==== Prototype declaration ==== */
mbed_official 35:f72ccc6892ee 81
mbed_official 35:f72ccc6892ee 82 /* ==== Global variable ==== */
mbed_official 35:f72ccc6892ee 83 /* On-chip peripheral module request setting table */
mbed_official 35:f72ccc6892ee 84 static const uint8_t usb0_host_dmac_peri_req_init_table[8][5] =
mbed_official 35:f72ccc6892ee 85 {
mbed_official 35:f72ccc6892ee 86 /* MID,RID, AM,LVL,REQD */
mbed_official 35:f72ccc6892ee 87 { 32, 3, 2, 1, 1}, /* USB_0 channel 0 transmit FIFO empty */
mbed_official 35:f72ccc6892ee 88 { 32, 3, 2, 1, 0}, /* USB_0 channel 0 receive FIFO full */
mbed_official 35:f72ccc6892ee 89 { 33, 3, 2, 1, 1}, /* USB_0 channel 1 transmit FIFO empty */
mbed_official 35:f72ccc6892ee 90 { 33, 3, 2, 1, 0}, /* USB_0 channel 1 receive FIFO full */
mbed_official 35:f72ccc6892ee 91 { 34, 3, 2, 1, 1}, /* USB_1 channel 0 transmit FIFO empty */
mbed_official 35:f72ccc6892ee 92 { 34, 3, 2, 1, 0}, /* USB_1 channel 0 receive FIFO full */
mbed_official 35:f72ccc6892ee 93 { 35, 3, 2, 1, 1}, /* USB_1 channel 1 transmit FIFO empty */
mbed_official 35:f72ccc6892ee 94 { 35, 3, 2, 1, 0}, /* USB_1 channel 1 receive FIFO full */
mbed_official 35:f72ccc6892ee 95 };
mbed_official 35:f72ccc6892ee 96
mbed_official 35:f72ccc6892ee 97
mbed_official 35:f72ccc6892ee 98 /*******************************************************************************
mbed_official 35:f72ccc6892ee 99 * Function Name: usb0_host_DMAC1_PeriReqInit
mbed_official 35:f72ccc6892ee 100 * Description : Sets the register mode for DMA mode and the on-chip peripheral
mbed_official 35:f72ccc6892ee 101 * : module request for transfer request for DMAC channel 1.
mbed_official 35:f72ccc6892ee 102 * : Executes DMAC initial setting using the DMA information
mbed_official 35:f72ccc6892ee 103 * : specified by the argument *trans_info and the enabled/disabled
mbed_official 35:f72ccc6892ee 104 * : continuous transfer specified by the argument continuation.
mbed_official 35:f72ccc6892ee 105 * : Registers DMAC channel 1 interrupt handler function and sets
mbed_official 35:f72ccc6892ee 106 * : the interrupt priority level. Then enables transfer completion
mbed_official 35:f72ccc6892ee 107 * : interrupt.
mbed_official 35:f72ccc6892ee 108 * Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC
mbed_official 35:f72ccc6892ee 109 * : : register
mbed_official 35:f72ccc6892ee 110 * : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
mbed_official 35:f72ccc6892ee 111 * : uint32_t continuation : Set continuous transfer to be valid
mbed_official 35:f72ccc6892ee 112 * : : after DMA transfer has been completed
mbed_official 35:f72ccc6892ee 113 * : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
mbed_official 35:f72ccc6892ee 114 * : DMAC_SAMPLE_SINGLE : Do not execute continuous
mbed_official 35:f72ccc6892ee 115 * : : transfer
mbed_official 35:f72ccc6892ee 116 * : uint32_t request_factor : Factor for on-chip peripheral module
mbed_official 35:f72ccc6892ee 117 * : : request
mbed_official 35:f72ccc6892ee 118 * : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
mbed_official 35:f72ccc6892ee 119 * : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
mbed_official 35:f72ccc6892ee 120 * : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
mbed_official 35:f72ccc6892ee 121 * : :
mbed_official 35:f72ccc6892ee 122 * : uint32_t req_direction : Setting value of CHCFG_n register
mbed_official 35:f72ccc6892ee 123 * : : REQD bit
mbed_official 35:f72ccc6892ee 124 * Return Value : none
mbed_official 35:f72ccc6892ee 125 *******************************************************************************/
mbed_official 35:f72ccc6892ee 126 void usb0_host_DMAC1_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
mbed_official 35:f72ccc6892ee 127 uint32_t request_factor, uint32_t req_direction)
mbed_official 35:f72ccc6892ee 128 {
mbed_official 35:f72ccc6892ee 129 /* ==== Register mode ==== */
mbed_official 35:f72ccc6892ee 130 if (DMAC_MODE_REGISTER == dmamode)
mbed_official 35:f72ccc6892ee 131 {
mbed_official 35:f72ccc6892ee 132 /* ==== Next0 register set ==== */
mbed_official 35:f72ccc6892ee 133 DMAC1.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
mbed_official 35:f72ccc6892ee 134 DMAC1.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
mbed_official 35:f72ccc6892ee 135 DMAC1.N0TB_n = trans_info->count; /* Total transfer byte count */
mbed_official 35:f72ccc6892ee 136
mbed_official 35:f72ccc6892ee 137 /* DAD : Transfer destination address counting direction */
mbed_official 35:f72ccc6892ee 138 /* SAD : Transfer source address counting direction */
mbed_official 35:f72ccc6892ee 139 /* DDS : Transfer destination transfer size */
mbed_official 35:f72ccc6892ee 140 /* SDS : Transfer source transfer size */
mbed_official 35:f72ccc6892ee 141 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:f72ccc6892ee 142 trans_info->daddr_dir,
mbed_official 35:f72ccc6892ee 143 DMAC1_CHCFG_n_DAD_SHIFT,
mbed_official 35:f72ccc6892ee 144 DMAC1_CHCFG_n_DAD);
mbed_official 35:f72ccc6892ee 145 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:f72ccc6892ee 146 trans_info->saddr_dir,
mbed_official 35:f72ccc6892ee 147 DMAC1_CHCFG_n_SAD_SHIFT,
mbed_official 35:f72ccc6892ee 148 DMAC1_CHCFG_n_SAD);
mbed_official 35:f72ccc6892ee 149 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:f72ccc6892ee 150 trans_info->dst_size,
mbed_official 35:f72ccc6892ee 151 DMAC1_CHCFG_n_DDS_SHIFT,
mbed_official 35:f72ccc6892ee 152 DMAC1_CHCFG_n_DDS);
mbed_official 35:f72ccc6892ee 153 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:f72ccc6892ee 154 trans_info->src_size,
mbed_official 35:f72ccc6892ee 155 DMAC1_CHCFG_n_SDS_SHIFT,
mbed_official 35:f72ccc6892ee 156 DMAC1_CHCFG_n_SDS);
mbed_official 35:f72ccc6892ee 157
mbed_official 35:f72ccc6892ee 158 /* DMS : Register mode */
mbed_official 35:f72ccc6892ee 159 /* RSEL : Select Next0 register set */
mbed_official 35:f72ccc6892ee 160 /* SBE : No discharge of buffer data when aborted */
mbed_official 35:f72ccc6892ee 161 /* DEM : No DMA interrupt mask */
mbed_official 35:f72ccc6892ee 162 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:f72ccc6892ee 163 0,
mbed_official 35:f72ccc6892ee 164 DMAC1_CHCFG_n_DMS_SHIFT,
mbed_official 35:f72ccc6892ee 165 DMAC1_CHCFG_n_DMS);
mbed_official 35:f72ccc6892ee 166 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:f72ccc6892ee 167 0,
mbed_official 35:f72ccc6892ee 168 DMAC1_CHCFG_n_RSEL_SHIFT,
mbed_official 35:f72ccc6892ee 169 DMAC1_CHCFG_n_RSEL);
mbed_official 35:f72ccc6892ee 170 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:f72ccc6892ee 171 0,
mbed_official 35:f72ccc6892ee 172 DMAC1_CHCFG_n_SBE_SHIFT,
mbed_official 35:f72ccc6892ee 173 DMAC1_CHCFG_n_SBE);
mbed_official 35:f72ccc6892ee 174 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:f72ccc6892ee 175 0,
mbed_official 35:f72ccc6892ee 176 DMAC1_CHCFG_n_DEM_SHIFT,
mbed_official 35:f72ccc6892ee 177 DMAC1_CHCFG_n_DEM);
mbed_official 35:f72ccc6892ee 178
mbed_official 35:f72ccc6892ee 179 /* ---- Continuous transfer ---- */
mbed_official 35:f72ccc6892ee 180 if (DMAC_SAMPLE_CONTINUATION == continuation)
mbed_official 35:f72ccc6892ee 181 {
mbed_official 35:f72ccc6892ee 182 /* REN : Execute continuous transfer */
mbed_official 35:f72ccc6892ee 183 /* RSW : Change register set when DMA transfer is completed. */
mbed_official 35:f72ccc6892ee 184 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:f72ccc6892ee 185 1,
mbed_official 35:f72ccc6892ee 186 DMAC1_CHCFG_n_REN_SHIFT,
mbed_official 35:f72ccc6892ee 187 DMAC1_CHCFG_n_REN);
mbed_official 35:f72ccc6892ee 188 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:f72ccc6892ee 189 1,
mbed_official 35:f72ccc6892ee 190 DMAC1_CHCFG_n_RSW_SHIFT,
mbed_official 35:f72ccc6892ee 191 DMAC1_CHCFG_n_RSW);
mbed_official 35:f72ccc6892ee 192 }
mbed_official 35:f72ccc6892ee 193 /* ---- Single transfer ---- */
mbed_official 35:f72ccc6892ee 194 else
mbed_official 35:f72ccc6892ee 195 {
mbed_official 35:f72ccc6892ee 196 /* REN : Do not execute continuous transfer */
mbed_official 35:f72ccc6892ee 197 /* RSW : Do not change register set when DMA transfer is completed. */
mbed_official 35:f72ccc6892ee 198 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:f72ccc6892ee 199 0,
mbed_official 35:f72ccc6892ee 200 DMAC1_CHCFG_n_REN_SHIFT,
mbed_official 35:f72ccc6892ee 201 DMAC1_CHCFG_n_REN);
mbed_official 35:f72ccc6892ee 202 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:f72ccc6892ee 203 0,
mbed_official 35:f72ccc6892ee 204 DMAC1_CHCFG_n_RSW_SHIFT,
mbed_official 35:f72ccc6892ee 205 DMAC1_CHCFG_n_RSW);
mbed_official 35:f72ccc6892ee 206 }
mbed_official 35:f72ccc6892ee 207
mbed_official 35:f72ccc6892ee 208 /* TM : Single transfer */
mbed_official 35:f72ccc6892ee 209 /* SEL : Channel setting */
mbed_official 35:f72ccc6892ee 210 /* HIEN, LOEN : On-chip peripheral module request */
mbed_official 35:f72ccc6892ee 211 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:f72ccc6892ee 212 0,
mbed_official 35:f72ccc6892ee 213 DMAC1_CHCFG_n_TM_SHIFT,
mbed_official 35:f72ccc6892ee 214 DMAC1_CHCFG_n_TM);
mbed_official 35:f72ccc6892ee 215 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:f72ccc6892ee 216 1,
mbed_official 35:f72ccc6892ee 217 DMAC1_CHCFG_n_SEL_SHIFT,
mbed_official 35:f72ccc6892ee 218 DMAC1_CHCFG_n_SEL);
mbed_official 35:f72ccc6892ee 219 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:f72ccc6892ee 220 1,
mbed_official 35:f72ccc6892ee 221 DMAC1_CHCFG_n_HIEN_SHIFT,
mbed_official 35:f72ccc6892ee 222 DMAC1_CHCFG_n_HIEN);
mbed_official 35:f72ccc6892ee 223 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:f72ccc6892ee 224 0,
mbed_official 35:f72ccc6892ee 225 DMAC1_CHCFG_n_LOEN_SHIFT,
mbed_official 35:f72ccc6892ee 226 DMAC1_CHCFG_n_LOEN);
mbed_official 35:f72ccc6892ee 227
mbed_official 35:f72ccc6892ee 228 /* ---- Set factor by specified on-chip peripheral module request ---- */
mbed_official 35:f72ccc6892ee 229 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:f72ccc6892ee 230 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
mbed_official 35:f72ccc6892ee 231 DMAC1_CHCFG_n_AM_SHIFT,
mbed_official 35:f72ccc6892ee 232 DMAC1_CHCFG_n_AM);
mbed_official 35:f72ccc6892ee 233 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:f72ccc6892ee 234 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
mbed_official 35:f72ccc6892ee 235 DMAC1_CHCFG_n_LVL_SHIFT,
mbed_official 35:f72ccc6892ee 236 DMAC1_CHCFG_n_LVL);
mbed_official 35:f72ccc6892ee 237 if (usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
mbed_official 35:f72ccc6892ee 238 {
mbed_official 35:f72ccc6892ee 239 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:f72ccc6892ee 240 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
mbed_official 35:f72ccc6892ee 241 DMAC1_CHCFG_n_REQD_SHIFT,
mbed_official 35:f72ccc6892ee 242 DMAC1_CHCFG_n_REQD);
mbed_official 35:f72ccc6892ee 243 }
mbed_official 35:f72ccc6892ee 244 else
mbed_official 35:f72ccc6892ee 245 {
mbed_official 35:f72ccc6892ee 246 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
mbed_official 35:f72ccc6892ee 247 req_direction,
mbed_official 35:f72ccc6892ee 248 DMAC1_CHCFG_n_REQD_SHIFT,
mbed_official 35:f72ccc6892ee 249 DMAC1_CHCFG_n_REQD);
mbed_official 35:f72ccc6892ee 250 }
mbed_official 35:f72ccc6892ee 251 RZA_IO_RegWrite_32(&DMAC01.DMARS,
mbed_official 35:f72ccc6892ee 252 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
mbed_official 35:f72ccc6892ee 253 DMAC01_DMARS_CH1_RID_SHIFT,
mbed_official 35:f72ccc6892ee 254 DMAC01_DMARS_CH1_RID);
mbed_official 35:f72ccc6892ee 255 RZA_IO_RegWrite_32(&DMAC01.DMARS,
mbed_official 35:f72ccc6892ee 256 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
mbed_official 35:f72ccc6892ee 257 DMAC01_DMARS_CH1_MID_SHIFT,
mbed_official 35:f72ccc6892ee 258 DMAC01_DMARS_CH1_MID);
mbed_official 35:f72ccc6892ee 259
mbed_official 35:f72ccc6892ee 260 /* PR : Round robin mode */
mbed_official 35:f72ccc6892ee 261 RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
mbed_official 35:f72ccc6892ee 262 1,
mbed_official 35:f72ccc6892ee 263 DMAC07_DCTRL_0_7_PR_SHIFT,
mbed_official 35:f72ccc6892ee 264 DMAC07_DCTRL_0_7_PR);
mbed_official 35:f72ccc6892ee 265 }
mbed_official 35:f72ccc6892ee 266 }
mbed_official 35:f72ccc6892ee 267
mbed_official 35:f72ccc6892ee 268 /*******************************************************************************
mbed_official 35:f72ccc6892ee 269 * Function Name: usb0_host_DMAC1_Open
mbed_official 35:f72ccc6892ee 270 * Description : Enables DMAC channel 1 transfer.
mbed_official 35:f72ccc6892ee 271 * Arguments : uint32_t req : DMAC request mode
mbed_official 35:f72ccc6892ee 272 * Return Value : 0 : Succeeded in enabling DMA transfer
mbed_official 35:f72ccc6892ee 273 * : -1 : Failed to enable DMA transfer (due to DMA operation)
mbed_official 35:f72ccc6892ee 274 *******************************************************************************/
mbed_official 35:f72ccc6892ee 275 int32_t usb0_host_DMAC1_Open (uint32_t req)
mbed_official 35:f72ccc6892ee 276 {
mbed_official 35:f72ccc6892ee 277 int32_t ret;
mbed_official 35:f72ccc6892ee 278 volatile uint8_t dummy;
mbed_official 35:f72ccc6892ee 279
mbed_official 35:f72ccc6892ee 280 /* Transferable? */
mbed_official 35:f72ccc6892ee 281 if ((0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
mbed_official 35:f72ccc6892ee 282 DMAC1_CHSTAT_n_EN_SHIFT,
mbed_official 35:f72ccc6892ee 283 DMAC1_CHSTAT_n_EN)) &&
mbed_official 35:f72ccc6892ee 284 (0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
mbed_official 35:f72ccc6892ee 285 DMAC1_CHSTAT_n_TACT_SHIFT,
mbed_official 35:f72ccc6892ee 286 DMAC1_CHSTAT_n_TACT)))
mbed_official 35:f72ccc6892ee 287 {
mbed_official 35:f72ccc6892ee 288 /* Clear Channel Status Register */
mbed_official 35:f72ccc6892ee 289 RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
mbed_official 35:f72ccc6892ee 290 1,
mbed_official 35:f72ccc6892ee 291 DMAC1_CHCTRL_n_SWRST_SHIFT,
mbed_official 35:f72ccc6892ee 292 DMAC1_CHCTRL_n_SWRST);
mbed_official 35:f72ccc6892ee 293 dummy = RZA_IO_RegRead_32(&DMAC1.CHCTRL_n,
mbed_official 35:f72ccc6892ee 294 DMAC1_CHCTRL_n_SWRST_SHIFT,
mbed_official 35:f72ccc6892ee 295 DMAC1_CHCTRL_n_SWRST);
mbed_official 35:f72ccc6892ee 296 /* Enable DMA transfer */
mbed_official 35:f72ccc6892ee 297 RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
mbed_official 35:f72ccc6892ee 298 1,
mbed_official 35:f72ccc6892ee 299 DMAC1_CHCTRL_n_SETEN_SHIFT,
mbed_official 35:f72ccc6892ee 300 DMAC1_CHCTRL_n_SETEN);
mbed_official 35:f72ccc6892ee 301
mbed_official 35:f72ccc6892ee 302 /* ---- Request by software ---- */
mbed_official 35:f72ccc6892ee 303 if (DMAC_REQ_MODE_SOFT == req)
mbed_official 35:f72ccc6892ee 304 {
mbed_official 35:f72ccc6892ee 305 /* DMA transfer Request by software */
mbed_official 35:f72ccc6892ee 306 RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
mbed_official 35:f72ccc6892ee 307 1,
mbed_official 35:f72ccc6892ee 308 DMAC1_CHCTRL_n_STG_SHIFT,
mbed_official 35:f72ccc6892ee 309 DMAC1_CHCTRL_n_STG);
mbed_official 35:f72ccc6892ee 310 }
mbed_official 35:f72ccc6892ee 311
mbed_official 35:f72ccc6892ee 312 ret = 0;
mbed_official 35:f72ccc6892ee 313 }
mbed_official 35:f72ccc6892ee 314 else
mbed_official 35:f72ccc6892ee 315 {
mbed_official 35:f72ccc6892ee 316 ret = -1;
mbed_official 35:f72ccc6892ee 317 }
mbed_official 35:f72ccc6892ee 318
mbed_official 35:f72ccc6892ee 319 return ret;
mbed_official 35:f72ccc6892ee 320 }
mbed_official 35:f72ccc6892ee 321
mbed_official 35:f72ccc6892ee 322 /*******************************************************************************
mbed_official 35:f72ccc6892ee 323 * Function Name: usb0_host_DMAC1_Close
mbed_official 35:f72ccc6892ee 324 * Description : Aborts DMAC channel 1 transfer. Returns the remaining transfer
mbed_official 35:f72ccc6892ee 325 * : byte count at the time of DMA transfer abort to the argument
mbed_official 35:f72ccc6892ee 326 * : *remain.
mbed_official 35:f72ccc6892ee 327 * Arguments : uint32_t * remain : Remaining transfer byte count when
mbed_official 35:f72ccc6892ee 328 * : : DMA transfer is aborted
mbed_official 35:f72ccc6892ee 329 * Return Value : none
mbed_official 35:f72ccc6892ee 330 *******************************************************************************/
mbed_official 35:f72ccc6892ee 331 void usb0_host_DMAC1_Close (uint32_t * remain)
mbed_official 35:f72ccc6892ee 332 {
mbed_official 35:f72ccc6892ee 333
mbed_official 35:f72ccc6892ee 334 /* ==== Abort transfer ==== */
mbed_official 35:f72ccc6892ee 335 RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
mbed_official 35:f72ccc6892ee 336 1,
mbed_official 35:f72ccc6892ee 337 DMAC1_CHCTRL_n_CLREN_SHIFT,
mbed_official 35:f72ccc6892ee 338 DMAC1_CHCTRL_n_CLREN);
mbed_official 35:f72ccc6892ee 339
mbed_official 35:f72ccc6892ee 340 while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
mbed_official 35:f72ccc6892ee 341 DMAC1_CHSTAT_n_TACT_SHIFT,
mbed_official 35:f72ccc6892ee 342 DMAC1_CHSTAT_n_TACT))
mbed_official 35:f72ccc6892ee 343 {
mbed_official 35:f72ccc6892ee 344 /* Loop until transfer is aborted */
mbed_official 35:f72ccc6892ee 345 }
mbed_official 35:f72ccc6892ee 346
mbed_official 35:f72ccc6892ee 347 while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
mbed_official 35:f72ccc6892ee 348 DMAC1_CHSTAT_n_EN_SHIFT,
mbed_official 35:f72ccc6892ee 349 DMAC1_CHSTAT_n_EN))
mbed_official 35:f72ccc6892ee 350 {
mbed_official 35:f72ccc6892ee 351 /* Loop until 0 is set in EN before checking the remaining transfer byte count */
mbed_official 35:f72ccc6892ee 352 }
mbed_official 35:f72ccc6892ee 353 /* ==== Obtain remaining transfer byte count ==== */
mbed_official 35:f72ccc6892ee 354 *remain = DMAC1.CRTB_n;
mbed_official 35:f72ccc6892ee 355 }
mbed_official 35:f72ccc6892ee 356
mbed_official 35:f72ccc6892ee 357 /*******************************************************************************
mbed_official 35:f72ccc6892ee 358 * Function Name: usb0_host_DMAC1_Load_Set
mbed_official 35:f72ccc6892ee 359 * Description : Sets the transfer source address, transfer destination
mbed_official 35:f72ccc6892ee 360 * : address, and total transfer byte count respectively
mbed_official 35:f72ccc6892ee 361 * : specified by the argument src_addr, dst_addr, and count to
mbed_official 35:f72ccc6892ee 362 * : DMAC channel 1 as DMA transfer information.
mbed_official 35:f72ccc6892ee 363 * : Sets the register set selected by the CHCFG_n register
mbed_official 35:f72ccc6892ee 364 * : RSEL bit from the Next0 or Next1 register set.
mbed_official 35:f72ccc6892ee 365 * : This function should be called when DMA transfer of DMAC
mbed_official 35:f72ccc6892ee 366 * : channel 1 is aboted.
mbed_official 35:f72ccc6892ee 367 * Arguments : uint32_t src_addr : Transfer source address
mbed_official 35:f72ccc6892ee 368 * : uint32_t dst_addr : Transfer destination address
mbed_official 35:f72ccc6892ee 369 * : uint32_t count : Total transfer byte count
mbed_official 35:f72ccc6892ee 370 * Return Value : none
mbed_official 35:f72ccc6892ee 371 *******************************************************************************/
mbed_official 35:f72ccc6892ee 372 void usb0_host_DMAC1_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
mbed_official 35:f72ccc6892ee 373 {
mbed_official 35:f72ccc6892ee 374 uint8_t reg_set;
mbed_official 35:f72ccc6892ee 375
mbed_official 35:f72ccc6892ee 376 /* Obtain register set in use */
mbed_official 35:f72ccc6892ee 377 reg_set = RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
mbed_official 35:f72ccc6892ee 378 DMAC1_CHSTAT_n_SR_SHIFT,
mbed_official 35:f72ccc6892ee 379 DMAC1_CHSTAT_n_SR);
mbed_official 35:f72ccc6892ee 380
mbed_official 35:f72ccc6892ee 381 /* ==== Load ==== */
mbed_official 35:f72ccc6892ee 382 if (0 == reg_set)
mbed_official 35:f72ccc6892ee 383 {
mbed_official 35:f72ccc6892ee 384 /* ---- Next0 Register Set ---- */
mbed_official 35:f72ccc6892ee 385 DMAC1.N0SA_n = src_addr; /* Start address of transfer source */
mbed_official 35:f72ccc6892ee 386 DMAC1.N0DA_n = dst_addr; /* Start address of transfer destination */
mbed_official 35:f72ccc6892ee 387 DMAC1.N0TB_n = count; /* Total transfer byte count */
mbed_official 35:f72ccc6892ee 388 }
mbed_official 35:f72ccc6892ee 389 else
mbed_official 35:f72ccc6892ee 390 {
mbed_official 35:f72ccc6892ee 391 /* ---- Next1 Register Set ---- */
mbed_official 35:f72ccc6892ee 392 DMAC1.N1SA_n = src_addr; /* Start address of transfer source */
mbed_official 35:f72ccc6892ee 393 DMAC1.N1DA_n = dst_addr; /* Start address of transfer destination */
mbed_official 35:f72ccc6892ee 394 DMAC1.N1TB_n = count; /* Total transfer byte count */
mbed_official 35:f72ccc6892ee 395 }
mbed_official 35:f72ccc6892ee 396 }
mbed_official 35:f72ccc6892ee 397
mbed_official 35:f72ccc6892ee 398 /*******************************************************************************
mbed_official 35:f72ccc6892ee 399 * Function Name: usb0_host_DMAC2_PeriReqInit
mbed_official 35:f72ccc6892ee 400 * Description : Sets the register mode for DMA mode and the on-chip peripheral
mbed_official 35:f72ccc6892ee 401 * : module request for transfer request for DMAC channel 2.
mbed_official 35:f72ccc6892ee 402 * : Executes DMAC initial setting using the DMA information
mbed_official 35:f72ccc6892ee 403 * : specified by the argument *trans_info and the enabled/disabled
mbed_official 35:f72ccc6892ee 404 * : continuous transfer specified by the argument continuation.
mbed_official 35:f72ccc6892ee 405 * : Registers DMAC channel 2 interrupt handler function and sets
mbed_official 35:f72ccc6892ee 406 * : the interrupt priority level. Then enables transfer completion
mbed_official 35:f72ccc6892ee 407 * : interrupt.
mbed_official 35:f72ccc6892ee 408 * Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC
mbed_official 35:f72ccc6892ee 409 * : : register
mbed_official 35:f72ccc6892ee 410 * : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
mbed_official 35:f72ccc6892ee 411 * : uint32_t continuation : Set continuous transfer to be valid
mbed_official 35:f72ccc6892ee 412 * : : after DMA transfer has been completed
mbed_official 35:f72ccc6892ee 413 * : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
mbed_official 35:f72ccc6892ee 414 * : DMAC_SAMPLE_SINGLE : Do not execute continuous
mbed_official 35:f72ccc6892ee 415 * : : transfer
mbed_official 35:f72ccc6892ee 416 * : uint32_t request_factor : Factor for on-chip peripheral module
mbed_official 35:f72ccc6892ee 417 * : : request
mbed_official 35:f72ccc6892ee 418 * : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
mbed_official 35:f72ccc6892ee 419 * : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
mbed_official 35:f72ccc6892ee 420 * : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
mbed_official 35:f72ccc6892ee 421 * : :
mbed_official 35:f72ccc6892ee 422 * : uint32_t req_direction : Setting value of CHCFG_n register
mbed_official 35:f72ccc6892ee 423 * : : REQD bit
mbed_official 35:f72ccc6892ee 424 * Return Value : none
mbed_official 35:f72ccc6892ee 425 *******************************************************************************/
mbed_official 35:f72ccc6892ee 426 void usb0_host_DMAC2_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
mbed_official 35:f72ccc6892ee 427 uint32_t request_factor, uint32_t req_direction)
mbed_official 35:f72ccc6892ee 428 {
mbed_official 35:f72ccc6892ee 429 /* ==== Register mode ==== */
mbed_official 35:f72ccc6892ee 430 if (DMAC_MODE_REGISTER == dmamode)
mbed_official 35:f72ccc6892ee 431 {
mbed_official 35:f72ccc6892ee 432 /* ==== Next0 register set ==== */
mbed_official 35:f72ccc6892ee 433 DMAC2.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
mbed_official 35:f72ccc6892ee 434 DMAC2.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
mbed_official 35:f72ccc6892ee 435 DMAC2.N0TB_n = trans_info->count; /* Total transfer byte count */
mbed_official 35:f72ccc6892ee 436
mbed_official 35:f72ccc6892ee 437 /* DAD : Transfer destination address counting direction */
mbed_official 35:f72ccc6892ee 438 /* SAD : Transfer source address counting direction */
mbed_official 35:f72ccc6892ee 439 /* DDS : Transfer destination transfer size */
mbed_official 35:f72ccc6892ee 440 /* SDS : Transfer source transfer size */
mbed_official 35:f72ccc6892ee 441 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:f72ccc6892ee 442 trans_info->daddr_dir,
mbed_official 35:f72ccc6892ee 443 DMAC2_CHCFG_n_DAD_SHIFT,
mbed_official 35:f72ccc6892ee 444 DMAC2_CHCFG_n_DAD);
mbed_official 35:f72ccc6892ee 445 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:f72ccc6892ee 446 trans_info->saddr_dir,
mbed_official 35:f72ccc6892ee 447 DMAC2_CHCFG_n_SAD_SHIFT,
mbed_official 35:f72ccc6892ee 448 DMAC2_CHCFG_n_SAD);
mbed_official 35:f72ccc6892ee 449 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:f72ccc6892ee 450 trans_info->dst_size,
mbed_official 35:f72ccc6892ee 451 DMAC2_CHCFG_n_DDS_SHIFT,
mbed_official 35:f72ccc6892ee 452 DMAC2_CHCFG_n_DDS);
mbed_official 35:f72ccc6892ee 453 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:f72ccc6892ee 454 trans_info->src_size,
mbed_official 35:f72ccc6892ee 455 DMAC2_CHCFG_n_SDS_SHIFT,
mbed_official 35:f72ccc6892ee 456 DMAC2_CHCFG_n_SDS);
mbed_official 35:f72ccc6892ee 457
mbed_official 35:f72ccc6892ee 458 /* DMS : Register mode */
mbed_official 35:f72ccc6892ee 459 /* RSEL : Select Next0 register set */
mbed_official 35:f72ccc6892ee 460 /* SBE : No discharge of buffer data when aborted */
mbed_official 35:f72ccc6892ee 461 /* DEM : No DMA interrupt mask */
mbed_official 35:f72ccc6892ee 462 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:f72ccc6892ee 463 0,
mbed_official 35:f72ccc6892ee 464 DMAC2_CHCFG_n_DMS_SHIFT,
mbed_official 35:f72ccc6892ee 465 DMAC2_CHCFG_n_DMS);
mbed_official 35:f72ccc6892ee 466 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:f72ccc6892ee 467 0,
mbed_official 35:f72ccc6892ee 468 DMAC2_CHCFG_n_RSEL_SHIFT,
mbed_official 35:f72ccc6892ee 469 DMAC2_CHCFG_n_RSEL);
mbed_official 35:f72ccc6892ee 470 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:f72ccc6892ee 471 0,
mbed_official 35:f72ccc6892ee 472 DMAC2_CHCFG_n_SBE_SHIFT,
mbed_official 35:f72ccc6892ee 473 DMAC2_CHCFG_n_SBE);
mbed_official 35:f72ccc6892ee 474 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:f72ccc6892ee 475 0,
mbed_official 35:f72ccc6892ee 476 DMAC2_CHCFG_n_DEM_SHIFT,
mbed_official 35:f72ccc6892ee 477 DMAC2_CHCFG_n_DEM);
mbed_official 35:f72ccc6892ee 478
mbed_official 35:f72ccc6892ee 479 /* ---- Continuous transfer ---- */
mbed_official 35:f72ccc6892ee 480 if (DMAC_SAMPLE_CONTINUATION == continuation)
mbed_official 35:f72ccc6892ee 481 {
mbed_official 35:f72ccc6892ee 482 /* REN : Execute continuous transfer */
mbed_official 35:f72ccc6892ee 483 /* RSW : Change register set when DMA transfer is completed. */
mbed_official 35:f72ccc6892ee 484 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:f72ccc6892ee 485 1,
mbed_official 35:f72ccc6892ee 486 DMAC2_CHCFG_n_REN_SHIFT,
mbed_official 35:f72ccc6892ee 487 DMAC2_CHCFG_n_REN);
mbed_official 35:f72ccc6892ee 488 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:f72ccc6892ee 489 1,
mbed_official 35:f72ccc6892ee 490 DMAC2_CHCFG_n_RSW_SHIFT,
mbed_official 35:f72ccc6892ee 491 DMAC2_CHCFG_n_RSW);
mbed_official 35:f72ccc6892ee 492 }
mbed_official 35:f72ccc6892ee 493 /* ---- Single transfer ---- */
mbed_official 35:f72ccc6892ee 494 else
mbed_official 35:f72ccc6892ee 495 {
mbed_official 35:f72ccc6892ee 496 /* REN : Do not execute continuous transfer */
mbed_official 35:f72ccc6892ee 497 /* RSW : Do not change register set when DMA transfer is completed. */
mbed_official 35:f72ccc6892ee 498 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:f72ccc6892ee 499 0,
mbed_official 35:f72ccc6892ee 500 DMAC2_CHCFG_n_REN_SHIFT,
mbed_official 35:f72ccc6892ee 501 DMAC2_CHCFG_n_REN);
mbed_official 35:f72ccc6892ee 502 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:f72ccc6892ee 503 0,
mbed_official 35:f72ccc6892ee 504 DMAC2_CHCFG_n_RSW_SHIFT,
mbed_official 35:f72ccc6892ee 505 DMAC2_CHCFG_n_RSW);
mbed_official 35:f72ccc6892ee 506 }
mbed_official 35:f72ccc6892ee 507
mbed_official 35:f72ccc6892ee 508 /* TM : Single transfer */
mbed_official 35:f72ccc6892ee 509 /* SEL : Channel setting */
mbed_official 35:f72ccc6892ee 510 /* HIEN, LOEN : On-chip peripheral module request */
mbed_official 35:f72ccc6892ee 511 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:f72ccc6892ee 512 0,
mbed_official 35:f72ccc6892ee 513 DMAC2_CHCFG_n_TM_SHIFT,
mbed_official 35:f72ccc6892ee 514 DMAC2_CHCFG_n_TM);
mbed_official 35:f72ccc6892ee 515 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:f72ccc6892ee 516 2,
mbed_official 35:f72ccc6892ee 517 DMAC2_CHCFG_n_SEL_SHIFT,
mbed_official 35:f72ccc6892ee 518 DMAC2_CHCFG_n_SEL);
mbed_official 35:f72ccc6892ee 519 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:f72ccc6892ee 520 1,
mbed_official 35:f72ccc6892ee 521 DMAC2_CHCFG_n_HIEN_SHIFT,
mbed_official 35:f72ccc6892ee 522 DMAC2_CHCFG_n_HIEN);
mbed_official 35:f72ccc6892ee 523 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:f72ccc6892ee 524 0,
mbed_official 35:f72ccc6892ee 525 DMAC2_CHCFG_n_LOEN_SHIFT,
mbed_official 35:f72ccc6892ee 526 DMAC2_CHCFG_n_LOEN);
mbed_official 35:f72ccc6892ee 527
mbed_official 35:f72ccc6892ee 528 /* ---- Set factor by specified on-chip peripheral module request ---- */
mbed_official 35:f72ccc6892ee 529 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:f72ccc6892ee 530 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
mbed_official 35:f72ccc6892ee 531 DMAC2_CHCFG_n_AM_SHIFT,
mbed_official 35:f72ccc6892ee 532 DMAC2_CHCFG_n_AM);
mbed_official 35:f72ccc6892ee 533 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:f72ccc6892ee 534 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
mbed_official 35:f72ccc6892ee 535 DMAC2_CHCFG_n_LVL_SHIFT,
mbed_official 35:f72ccc6892ee 536 DMAC2_CHCFG_n_LVL);
mbed_official 35:f72ccc6892ee 537 if (usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
mbed_official 35:f72ccc6892ee 538 {
mbed_official 35:f72ccc6892ee 539 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:f72ccc6892ee 540 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
mbed_official 35:f72ccc6892ee 541 DMAC2_CHCFG_n_REQD_SHIFT,
mbed_official 35:f72ccc6892ee 542 DMAC2_CHCFG_n_REQD);
mbed_official 35:f72ccc6892ee 543 }
mbed_official 35:f72ccc6892ee 544 else
mbed_official 35:f72ccc6892ee 545 {
mbed_official 35:f72ccc6892ee 546 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
mbed_official 35:f72ccc6892ee 547 req_direction,
mbed_official 35:f72ccc6892ee 548 DMAC2_CHCFG_n_REQD_SHIFT,
mbed_official 35:f72ccc6892ee 549 DMAC2_CHCFG_n_REQD);
mbed_official 35:f72ccc6892ee 550 }
mbed_official 35:f72ccc6892ee 551 RZA_IO_RegWrite_32(&DMAC23.DMARS,
mbed_official 35:f72ccc6892ee 552 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
mbed_official 35:f72ccc6892ee 553 DMAC23_DMARS_CH2_RID_SHIFT,
mbed_official 35:f72ccc6892ee 554 DMAC23_DMARS_CH2_RID);
mbed_official 35:f72ccc6892ee 555 RZA_IO_RegWrite_32(&DMAC23.DMARS,
mbed_official 35:f72ccc6892ee 556 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
mbed_official 35:f72ccc6892ee 557 DMAC23_DMARS_CH2_MID_SHIFT,
mbed_official 35:f72ccc6892ee 558 DMAC23_DMARS_CH2_MID);
mbed_official 35:f72ccc6892ee 559
mbed_official 35:f72ccc6892ee 560 /* PR : Round robin mode */
mbed_official 35:f72ccc6892ee 561 RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
mbed_official 35:f72ccc6892ee 562 1,
mbed_official 35:f72ccc6892ee 563 DMAC07_DCTRL_0_7_PR_SHIFT,
mbed_official 35:f72ccc6892ee 564 DMAC07_DCTRL_0_7_PR);
mbed_official 35:f72ccc6892ee 565 }
mbed_official 35:f72ccc6892ee 566 }
mbed_official 35:f72ccc6892ee 567
mbed_official 35:f72ccc6892ee 568 /*******************************************************************************
mbed_official 35:f72ccc6892ee 569 * Function Name: usb0_host_DMAC2_Open
mbed_official 35:f72ccc6892ee 570 * Description : Enables DMAC channel 2 transfer.
mbed_official 35:f72ccc6892ee 571 * Arguments : uint32_t req : DMAC request mode
mbed_official 35:f72ccc6892ee 572 * Return Value : 0 : Succeeded in enabling DMA transfer
mbed_official 35:f72ccc6892ee 573 * : -1 : Failed to enable DMA transfer (due to DMA operation)
mbed_official 35:f72ccc6892ee 574 *******************************************************************************/
mbed_official 35:f72ccc6892ee 575 int32_t usb0_host_DMAC2_Open (uint32_t req)
mbed_official 35:f72ccc6892ee 576 {
mbed_official 35:f72ccc6892ee 577 int32_t ret;
mbed_official 35:f72ccc6892ee 578 volatile uint8_t dummy;
mbed_official 35:f72ccc6892ee 579
mbed_official 35:f72ccc6892ee 580 /* Transferable? */
mbed_official 35:f72ccc6892ee 581 if ((0 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
mbed_official 35:f72ccc6892ee 582 DMAC2_CHSTAT_n_EN_SHIFT,
mbed_official 35:f72ccc6892ee 583 DMAC2_CHSTAT_n_EN)) &&
mbed_official 35:f72ccc6892ee 584 (0 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
mbed_official 35:f72ccc6892ee 585 DMAC2_CHSTAT_n_TACT_SHIFT,
mbed_official 35:f72ccc6892ee 586 DMAC2_CHSTAT_n_TACT)))
mbed_official 35:f72ccc6892ee 587 {
mbed_official 35:f72ccc6892ee 588 /* Clear Channel Status Register */
mbed_official 35:f72ccc6892ee 589 RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
mbed_official 35:f72ccc6892ee 590 1,
mbed_official 35:f72ccc6892ee 591 DMAC2_CHCTRL_n_SWRST_SHIFT,
mbed_official 35:f72ccc6892ee 592 DMAC2_CHCTRL_n_SWRST);
mbed_official 35:f72ccc6892ee 593 dummy = RZA_IO_RegRead_32(&DMAC2.CHCTRL_n,
mbed_official 35:f72ccc6892ee 594 DMAC2_CHCTRL_n_SWRST_SHIFT,
mbed_official 35:f72ccc6892ee 595 DMAC2_CHCTRL_n_SWRST);
mbed_official 35:f72ccc6892ee 596 /* Enable DMA transfer */
mbed_official 35:f72ccc6892ee 597 RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
mbed_official 35:f72ccc6892ee 598 1,
mbed_official 35:f72ccc6892ee 599 DMAC2_CHCTRL_n_SETEN_SHIFT,
mbed_official 35:f72ccc6892ee 600 DMAC2_CHCTRL_n_SETEN);
mbed_official 35:f72ccc6892ee 601
mbed_official 35:f72ccc6892ee 602 /* ---- Request by software ---- */
mbed_official 35:f72ccc6892ee 603 if (DMAC_REQ_MODE_SOFT == req)
mbed_official 35:f72ccc6892ee 604 {
mbed_official 35:f72ccc6892ee 605 /* DMA transfer Request by software */
mbed_official 35:f72ccc6892ee 606 RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
mbed_official 35:f72ccc6892ee 607 1,
mbed_official 35:f72ccc6892ee 608 DMAC2_CHCTRL_n_STG_SHIFT,
mbed_official 35:f72ccc6892ee 609 DMAC2_CHCTRL_n_STG);
mbed_official 35:f72ccc6892ee 610 }
mbed_official 35:f72ccc6892ee 611
mbed_official 35:f72ccc6892ee 612 ret = 0;
mbed_official 35:f72ccc6892ee 613 }
mbed_official 35:f72ccc6892ee 614 else
mbed_official 35:f72ccc6892ee 615 {
mbed_official 35:f72ccc6892ee 616 ret = -1;
mbed_official 35:f72ccc6892ee 617 }
mbed_official 35:f72ccc6892ee 618
mbed_official 35:f72ccc6892ee 619 return ret;
mbed_official 35:f72ccc6892ee 620 }
mbed_official 35:f72ccc6892ee 621
mbed_official 35:f72ccc6892ee 622 /*******************************************************************************
mbed_official 35:f72ccc6892ee 623 * Function Name: usb0_host_DMAC2_Close
mbed_official 35:f72ccc6892ee 624 * Description : Aborts DMAC channel 2 transfer. Returns the remaining transfer
mbed_official 35:f72ccc6892ee 625 * : byte count at the time of DMA transfer abort to the argument
mbed_official 35:f72ccc6892ee 626 * : *remain.
mbed_official 35:f72ccc6892ee 627 * Arguments : uint32_t * remain : Remaining transfer byte count when
mbed_official 35:f72ccc6892ee 628 * : : DMA transfer is aborted
mbed_official 35:f72ccc6892ee 629 * Return Value : none
mbed_official 35:f72ccc6892ee 630 *******************************************************************************/
mbed_official 35:f72ccc6892ee 631 void usb0_host_DMAC2_Close (uint32_t * remain)
mbed_official 35:f72ccc6892ee 632 {
mbed_official 35:f72ccc6892ee 633
mbed_official 35:f72ccc6892ee 634 /* ==== Abort transfer ==== */
mbed_official 35:f72ccc6892ee 635 RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
mbed_official 35:f72ccc6892ee 636 1,
mbed_official 35:f72ccc6892ee 637 DMAC2_CHCTRL_n_CLREN_SHIFT,
mbed_official 35:f72ccc6892ee 638 DMAC2_CHCTRL_n_CLREN);
mbed_official 35:f72ccc6892ee 639
mbed_official 35:f72ccc6892ee 640 while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
mbed_official 35:f72ccc6892ee 641 DMAC2_CHSTAT_n_TACT_SHIFT,
mbed_official 35:f72ccc6892ee 642 DMAC2_CHSTAT_n_TACT))
mbed_official 35:f72ccc6892ee 643 {
mbed_official 35:f72ccc6892ee 644 /* Loop until transfer is aborted */
mbed_official 35:f72ccc6892ee 645 }
mbed_official 35:f72ccc6892ee 646
mbed_official 35:f72ccc6892ee 647 while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
mbed_official 35:f72ccc6892ee 648 DMAC2_CHSTAT_n_EN_SHIFT,
mbed_official 35:f72ccc6892ee 649 DMAC2_CHSTAT_n_EN))
mbed_official 35:f72ccc6892ee 650 {
mbed_official 35:f72ccc6892ee 651 /* Loop until 0 is set in EN before checking the remaining transfer byte count */
mbed_official 35:f72ccc6892ee 652 }
mbed_official 35:f72ccc6892ee 653 /* ==== Obtain remaining transfer byte count ==== */
mbed_official 35:f72ccc6892ee 654 *remain = DMAC2.CRTB_n;
mbed_official 35:f72ccc6892ee 655 }
mbed_official 35:f72ccc6892ee 656
mbed_official 35:f72ccc6892ee 657 /*******************************************************************************
mbed_official 35:f72ccc6892ee 658 * Function Name: usb0_host_DMAC2_Load_Set
mbed_official 35:f72ccc6892ee 659 * Description : Sets the transfer source address, transfer destination
mbed_official 35:f72ccc6892ee 660 * : address, and total transfer byte count respectively
mbed_official 35:f72ccc6892ee 661 * : specified by the argument src_addr, dst_addr, and count to
mbed_official 35:f72ccc6892ee 662 * : DMAC channel 2 as DMA transfer information.
mbed_official 35:f72ccc6892ee 663 * : Sets the register set selected by the CHCFG_n register
mbed_official 35:f72ccc6892ee 664 * : RSEL bit from the Next0 or Next1 register set.
mbed_official 35:f72ccc6892ee 665 * : This function should be called when DMA transfer of DMAC
mbed_official 35:f72ccc6892ee 666 * : channel 2 is aboted.
mbed_official 35:f72ccc6892ee 667 * Arguments : uint32_t src_addr : Transfer source address
mbed_official 35:f72ccc6892ee 668 * : uint32_t dst_addr : Transfer destination address
mbed_official 35:f72ccc6892ee 669 * : uint32_t count : Total transfer byte count
mbed_official 35:f72ccc6892ee 670 * Return Value : none
mbed_official 35:f72ccc6892ee 671 *******************************************************************************/
mbed_official 35:f72ccc6892ee 672 void usb0_host_DMAC2_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
mbed_official 35:f72ccc6892ee 673 {
mbed_official 35:f72ccc6892ee 674 uint8_t reg_set;
mbed_official 35:f72ccc6892ee 675
mbed_official 35:f72ccc6892ee 676 /* Obtain register set in use */
mbed_official 35:f72ccc6892ee 677 reg_set = RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
mbed_official 35:f72ccc6892ee 678 DMAC2_CHSTAT_n_SR_SHIFT,
mbed_official 35:f72ccc6892ee 679 DMAC2_CHSTAT_n_SR);
mbed_official 35:f72ccc6892ee 680
mbed_official 35:f72ccc6892ee 681 /* ==== Load ==== */
mbed_official 35:f72ccc6892ee 682 if (0 == reg_set)
mbed_official 35:f72ccc6892ee 683 {
mbed_official 35:f72ccc6892ee 684 /* ---- Next0 Register Set ---- */
mbed_official 35:f72ccc6892ee 685 DMAC2.N0SA_n = src_addr; /* Start address of transfer source */
mbed_official 35:f72ccc6892ee 686 DMAC2.N0DA_n = dst_addr; /* Start address of transfer destination */
mbed_official 35:f72ccc6892ee 687 DMAC2.N0TB_n = count; /* Total transfer byte count */
mbed_official 35:f72ccc6892ee 688 }
mbed_official 35:f72ccc6892ee 689 else
mbed_official 35:f72ccc6892ee 690 {
mbed_official 35:f72ccc6892ee 691 /* ---- Next1 Register Set ---- */
mbed_official 35:f72ccc6892ee 692 DMAC2.N1SA_n = src_addr; /* Start address of transfer source */
mbed_official 35:f72ccc6892ee 693 DMAC2.N1DA_n = dst_addr; /* Start address of transfer destination */
mbed_official 35:f72ccc6892ee 694 DMAC2.N1TB_n = count; /* Total transfer byte count */
mbed_official 35:f72ccc6892ee 695 }
mbed_official 35:f72ccc6892ee 696 }
mbed_official 35:f72ccc6892ee 697
mbed_official 35:f72ccc6892ee 698 /* End of File */