USBHost library. NOTE: This library is only officially supported on the LPC1768 platform. For more information, please see the handbook page.
Dependencies: FATFileSystem mbed-rtos
Dependents: BTstack WallbotWii SD to Flash Data Transfer USBHost-MSD_HelloWorld ... more
Legacy Warning
This is an mbed 2 library. To learn more about mbed OS 5, visit the docs.
Pull requests against this repository are no longer supported. Please raise against mbed OS 5 as documented above.
targets/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_host_dmacdrv.c@39:d96aa62afc5b, 2017-07-27 (annotated)
- Committer:
- Kojto
- Date:
- Thu Jul 27 12:24:30 2017 +0100
- Revision:
- 39:d96aa62afc5b
Update USBHost - add targets directory
This corresponds to mbed-os/master commit 9207365
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Kojto | 39:d96aa62afc5b | 1 | /******************************************************************************* |
Kojto | 39:d96aa62afc5b | 2 | * DISCLAIMER |
Kojto | 39:d96aa62afc5b | 3 | * This software is supplied by Renesas Electronics Corporation and is only |
Kojto | 39:d96aa62afc5b | 4 | * intended for use with Renesas products. No other uses are authorized. This |
Kojto | 39:d96aa62afc5b | 5 | * software is owned by Renesas Electronics Corporation and is protected under |
Kojto | 39:d96aa62afc5b | 6 | * all applicable laws, including copyright laws. |
Kojto | 39:d96aa62afc5b | 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING |
Kojto | 39:d96aa62afc5b | 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT |
Kojto | 39:d96aa62afc5b | 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE |
Kojto | 39:d96aa62afc5b | 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. |
Kojto | 39:d96aa62afc5b | 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS |
Kojto | 39:d96aa62afc5b | 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE |
Kojto | 39:d96aa62afc5b | 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR |
Kojto | 39:d96aa62afc5b | 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE |
Kojto | 39:d96aa62afc5b | 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. |
Kojto | 39:d96aa62afc5b | 16 | * Renesas reserves the right, without notice, to make changes to this software |
Kojto | 39:d96aa62afc5b | 17 | * and to discontinue the availability of this software. By using this software, |
Kojto | 39:d96aa62afc5b | 18 | * you agree to the additional terms and conditions found by accessing the |
Kojto | 39:d96aa62afc5b | 19 | * following link: |
Kojto | 39:d96aa62afc5b | 20 | * http://www.renesas.com/disclaimer |
Kojto | 39:d96aa62afc5b | 21 | * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. |
Kojto | 39:d96aa62afc5b | 22 | *******************************************************************************/ |
Kojto | 39:d96aa62afc5b | 23 | /******************************************************************************* |
Kojto | 39:d96aa62afc5b | 24 | * File Name : usb1_host_dmacdrv.c |
Kojto | 39:d96aa62afc5b | 25 | * $Rev: 1116 $ |
Kojto | 39:d96aa62afc5b | 26 | * $Date:: 2014-07-09 16:29:19 +0900#$ |
Kojto | 39:d96aa62afc5b | 27 | * Device(s) : RZ/A1H |
Kojto | 39:d96aa62afc5b | 28 | * Tool-Chain : |
Kojto | 39:d96aa62afc5b | 29 | * OS : None |
Kojto | 39:d96aa62afc5b | 30 | * H/W Platform : |
Kojto | 39:d96aa62afc5b | 31 | * Description : RZ/A1H R7S72100 USB Sample Program |
Kojto | 39:d96aa62afc5b | 32 | * Operation : |
Kojto | 39:d96aa62afc5b | 33 | * Limitations : |
Kojto | 39:d96aa62afc5b | 34 | *******************************************************************************/ |
Kojto | 39:d96aa62afc5b | 35 | |
Kojto | 39:d96aa62afc5b | 36 | |
Kojto | 39:d96aa62afc5b | 37 | /******************************************************************************* |
Kojto | 39:d96aa62afc5b | 38 | Includes <System Includes> , "Project Includes" |
Kojto | 39:d96aa62afc5b | 39 | *******************************************************************************/ |
Kojto | 39:d96aa62afc5b | 40 | #include "r_typedefs.h" |
Kojto | 39:d96aa62afc5b | 41 | #include "iodefine.h" |
Kojto | 39:d96aa62afc5b | 42 | #include "rza_io_regrw.h" |
Kojto | 39:d96aa62afc5b | 43 | #include "usb1_host_dmacdrv.h" |
Kojto | 39:d96aa62afc5b | 44 | |
Kojto | 39:d96aa62afc5b | 45 | |
Kojto | 39:d96aa62afc5b | 46 | /******************************************************************************* |
Kojto | 39:d96aa62afc5b | 47 | Typedef definitions |
Kojto | 39:d96aa62afc5b | 48 | *******************************************************************************/ |
Kojto | 39:d96aa62afc5b | 49 | |
Kojto | 39:d96aa62afc5b | 50 | |
Kojto | 39:d96aa62afc5b | 51 | /******************************************************************************* |
Kojto | 39:d96aa62afc5b | 52 | Macro definitions |
Kojto | 39:d96aa62afc5b | 53 | *******************************************************************************/ |
Kojto | 39:d96aa62afc5b | 54 | #define DMAC_INDEFINE (255) /* Macro definition when REQD bit is not used */ |
Kojto | 39:d96aa62afc5b | 55 | |
Kojto | 39:d96aa62afc5b | 56 | /* ==== Request setting information for on-chip peripheral module ==== */ |
Kojto | 39:d96aa62afc5b | 57 | typedef enum dmac_peri_req_reg_type |
Kojto | 39:d96aa62afc5b | 58 | { |
Kojto | 39:d96aa62afc5b | 59 | DMAC_REQ_MID, |
Kojto | 39:d96aa62afc5b | 60 | DMAC_REQ_RID, |
Kojto | 39:d96aa62afc5b | 61 | DMAC_REQ_AM, |
Kojto | 39:d96aa62afc5b | 62 | DMAC_REQ_LVL, |
Kojto | 39:d96aa62afc5b | 63 | DMAC_REQ_REQD |
Kojto | 39:d96aa62afc5b | 64 | } dmac_peri_req_reg_type_t; |
Kojto | 39:d96aa62afc5b | 65 | |
Kojto | 39:d96aa62afc5b | 66 | |
Kojto | 39:d96aa62afc5b | 67 | /******************************************************************************* |
Kojto | 39:d96aa62afc5b | 68 | Imported global variables and functions (from other files) |
Kojto | 39:d96aa62afc5b | 69 | *******************************************************************************/ |
Kojto | 39:d96aa62afc5b | 70 | |
Kojto | 39:d96aa62afc5b | 71 | |
Kojto | 39:d96aa62afc5b | 72 | /******************************************************************************* |
Kojto | 39:d96aa62afc5b | 73 | Exported global variables and functions (to be accessed by other files) |
Kojto | 39:d96aa62afc5b | 74 | *******************************************************************************/ |
Kojto | 39:d96aa62afc5b | 75 | |
Kojto | 39:d96aa62afc5b | 76 | |
Kojto | 39:d96aa62afc5b | 77 | /******************************************************************************* |
Kojto | 39:d96aa62afc5b | 78 | Private global variables and functions |
Kojto | 39:d96aa62afc5b | 79 | *******************************************************************************/ |
Kojto | 39:d96aa62afc5b | 80 | /* ==== Prototype declaration ==== */ |
Kojto | 39:d96aa62afc5b | 81 | |
Kojto | 39:d96aa62afc5b | 82 | /* ==== Global variable ==== */ |
Kojto | 39:d96aa62afc5b | 83 | /* On-chip peripheral module request setting table */ |
Kojto | 39:d96aa62afc5b | 84 | static const uint8_t usb1_host_dmac_peri_req_init_table[8][5] = |
Kojto | 39:d96aa62afc5b | 85 | { |
Kojto | 39:d96aa62afc5b | 86 | /* MID,RID, AM,LVL,REQD */ |
Kojto | 39:d96aa62afc5b | 87 | { 32, 3, 2, 1, 1}, /* USB_0 channel 0 transmit FIFO empty */ |
Kojto | 39:d96aa62afc5b | 88 | { 32, 3, 2, 1, 0}, /* USB_0 channel 0 receive FIFO full */ |
Kojto | 39:d96aa62afc5b | 89 | { 33, 3, 2, 1, 1}, /* USB_0 channel 1 transmit FIFO empty */ |
Kojto | 39:d96aa62afc5b | 90 | { 33, 3, 2, 1, 0}, /* USB_0 channel 1 receive FIFO full */ |
Kojto | 39:d96aa62afc5b | 91 | { 34, 3, 2, 1, 1}, /* USB_1 channel 0 transmit FIFO empty */ |
Kojto | 39:d96aa62afc5b | 92 | { 34, 3, 2, 1, 0}, /* USB_1 channel 0 receive FIFO full */ |
Kojto | 39:d96aa62afc5b | 93 | { 35, 3, 2, 1, 1}, /* USB_1 channel 1 transmit FIFO empty */ |
Kojto | 39:d96aa62afc5b | 94 | { 35, 3, 2, 1, 0}, /* USB_1 channel 1 receive FIFO full */ |
Kojto | 39:d96aa62afc5b | 95 | }; |
Kojto | 39:d96aa62afc5b | 96 | |
Kojto | 39:d96aa62afc5b | 97 | |
Kojto | 39:d96aa62afc5b | 98 | /******************************************************************************* |
Kojto | 39:d96aa62afc5b | 99 | * Function Name: usb1_host_DMAC3_PeriReqInit |
Kojto | 39:d96aa62afc5b | 100 | * Description : Sets the register mode for DMA mode and the on-chip peripheral |
Kojto | 39:d96aa62afc5b | 101 | * : module request for transfer request for DMAC channel 3. |
Kojto | 39:d96aa62afc5b | 102 | * : Executes DMAC initial setting using the DMA information |
Kojto | 39:d96aa62afc5b | 103 | * : specified by the argument *trans_info and the enabled/disabled |
Kojto | 39:d96aa62afc5b | 104 | * : continuous transfer specified by the argument continuation. |
Kojto | 39:d96aa62afc5b | 105 | * : Registers DMAC channel 3 interrupt handler function and sets |
Kojto | 39:d96aa62afc5b | 106 | * : the interrupt priority level. Then enables transfer completion |
Kojto | 39:d96aa62afc5b | 107 | * : interrupt. |
Kojto | 39:d96aa62afc5b | 108 | * Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC |
Kojto | 39:d96aa62afc5b | 109 | * : : register |
Kojto | 39:d96aa62afc5b | 110 | * : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER) |
Kojto | 39:d96aa62afc5b | 111 | * : uint32_t continuation : Set continuous transfer to be valid |
Kojto | 39:d96aa62afc5b | 112 | * : : after DMA transfer has been completed |
Kojto | 39:d96aa62afc5b | 113 | * : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer |
Kojto | 39:d96aa62afc5b | 114 | * : DMAC_SAMPLE_SINGLE : Do not execute continuous |
Kojto | 39:d96aa62afc5b | 115 | * : : transfer |
Kojto | 39:d96aa62afc5b | 116 | * : uint32_t request_factor : Factor for on-chip peripheral module |
Kojto | 39:d96aa62afc5b | 117 | * : : request |
Kojto | 39:d96aa62afc5b | 118 | * : DMAC_REQ_OSTM0TINT : OSTM_0 compare match |
Kojto | 39:d96aa62afc5b | 119 | * : DMAC_REQ_OSTM1TINT : OSTM_1 compare match |
Kojto | 39:d96aa62afc5b | 120 | * : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match |
Kojto | 39:d96aa62afc5b | 121 | * : : |
Kojto | 39:d96aa62afc5b | 122 | * : uint32_t req_direction : Setting value of CHCFG_n register |
Kojto | 39:d96aa62afc5b | 123 | * : : REQD bit |
Kojto | 39:d96aa62afc5b | 124 | * Return Value : none |
Kojto | 39:d96aa62afc5b | 125 | *******************************************************************************/ |
Kojto | 39:d96aa62afc5b | 126 | void usb1_host_DMAC3_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation, |
Kojto | 39:d96aa62afc5b | 127 | uint32_t request_factor, uint32_t req_direction) |
Kojto | 39:d96aa62afc5b | 128 | { |
Kojto | 39:d96aa62afc5b | 129 | /* ==== Register mode ==== */ |
Kojto | 39:d96aa62afc5b | 130 | if (DMAC_MODE_REGISTER == dmamode) |
Kojto | 39:d96aa62afc5b | 131 | { |
Kojto | 39:d96aa62afc5b | 132 | /* ==== Next0 register set ==== */ |
Kojto | 39:d96aa62afc5b | 133 | DMAC3.N0SA_n = trans_info->src_addr; /* Start address of transfer source */ |
Kojto | 39:d96aa62afc5b | 134 | DMAC3.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */ |
Kojto | 39:d96aa62afc5b | 135 | DMAC3.N0TB_n = trans_info->count; /* Total transfer byte count */ |
Kojto | 39:d96aa62afc5b | 136 | |
Kojto | 39:d96aa62afc5b | 137 | /* DAD : Transfer destination address counting direction */ |
Kojto | 39:d96aa62afc5b | 138 | /* SAD : Transfer source address counting direction */ |
Kojto | 39:d96aa62afc5b | 139 | /* DDS : Transfer destination transfer size */ |
Kojto | 39:d96aa62afc5b | 140 | /* SDS : Transfer source transfer size */ |
Kojto | 39:d96aa62afc5b | 141 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 142 | trans_info->daddr_dir, |
Kojto | 39:d96aa62afc5b | 143 | DMAC3_CHCFG_n_DAD_SHIFT, |
Kojto | 39:d96aa62afc5b | 144 | DMAC3_CHCFG_n_DAD); |
Kojto | 39:d96aa62afc5b | 145 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 146 | trans_info->saddr_dir, |
Kojto | 39:d96aa62afc5b | 147 | DMAC3_CHCFG_n_SAD_SHIFT, |
Kojto | 39:d96aa62afc5b | 148 | DMAC3_CHCFG_n_SAD); |
Kojto | 39:d96aa62afc5b | 149 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 150 | trans_info->dst_size, |
Kojto | 39:d96aa62afc5b | 151 | DMAC3_CHCFG_n_DDS_SHIFT, |
Kojto | 39:d96aa62afc5b | 152 | DMAC3_CHCFG_n_DDS); |
Kojto | 39:d96aa62afc5b | 153 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 154 | trans_info->src_size, |
Kojto | 39:d96aa62afc5b | 155 | DMAC3_CHCFG_n_SDS_SHIFT, |
Kojto | 39:d96aa62afc5b | 156 | DMAC3_CHCFG_n_SDS); |
Kojto | 39:d96aa62afc5b | 157 | |
Kojto | 39:d96aa62afc5b | 158 | /* DMS : Register mode */ |
Kojto | 39:d96aa62afc5b | 159 | /* RSEL : Select Next0 register set */ |
Kojto | 39:d96aa62afc5b | 160 | /* SBE : No discharge of buffer data when aborted */ |
Kojto | 39:d96aa62afc5b | 161 | /* DEM : No DMA interrupt mask */ |
Kojto | 39:d96aa62afc5b | 162 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 163 | 0, |
Kojto | 39:d96aa62afc5b | 164 | DMAC3_CHCFG_n_DMS_SHIFT, |
Kojto | 39:d96aa62afc5b | 165 | DMAC3_CHCFG_n_DMS); |
Kojto | 39:d96aa62afc5b | 166 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 167 | 0, |
Kojto | 39:d96aa62afc5b | 168 | DMAC3_CHCFG_n_RSEL_SHIFT, |
Kojto | 39:d96aa62afc5b | 169 | DMAC3_CHCFG_n_RSEL); |
Kojto | 39:d96aa62afc5b | 170 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 171 | 0, |
Kojto | 39:d96aa62afc5b | 172 | DMAC3_CHCFG_n_SBE_SHIFT, |
Kojto | 39:d96aa62afc5b | 173 | DMAC3_CHCFG_n_SBE); |
Kojto | 39:d96aa62afc5b | 174 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 175 | 0, |
Kojto | 39:d96aa62afc5b | 176 | DMAC3_CHCFG_n_DEM_SHIFT, |
Kojto | 39:d96aa62afc5b | 177 | DMAC3_CHCFG_n_DEM); |
Kojto | 39:d96aa62afc5b | 178 | |
Kojto | 39:d96aa62afc5b | 179 | /* ---- Continuous transfer ---- */ |
Kojto | 39:d96aa62afc5b | 180 | if (DMAC_SAMPLE_CONTINUATION == continuation) |
Kojto | 39:d96aa62afc5b | 181 | { |
Kojto | 39:d96aa62afc5b | 182 | /* REN : Execute continuous transfer */ |
Kojto | 39:d96aa62afc5b | 183 | /* RSW : Change register set when DMA transfer is completed. */ |
Kojto | 39:d96aa62afc5b | 184 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 185 | 1, |
Kojto | 39:d96aa62afc5b | 186 | DMAC3_CHCFG_n_REN_SHIFT, |
Kojto | 39:d96aa62afc5b | 187 | DMAC3_CHCFG_n_REN); |
Kojto | 39:d96aa62afc5b | 188 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 189 | 1, |
Kojto | 39:d96aa62afc5b | 190 | DMAC3_CHCFG_n_RSW_SHIFT, |
Kojto | 39:d96aa62afc5b | 191 | DMAC3_CHCFG_n_RSW); |
Kojto | 39:d96aa62afc5b | 192 | } |
Kojto | 39:d96aa62afc5b | 193 | /* ---- Single transfer ---- */ |
Kojto | 39:d96aa62afc5b | 194 | else |
Kojto | 39:d96aa62afc5b | 195 | { |
Kojto | 39:d96aa62afc5b | 196 | /* REN : Do not execute continuous transfer */ |
Kojto | 39:d96aa62afc5b | 197 | /* RSW : Do not change register set when DMA transfer is completed. */ |
Kojto | 39:d96aa62afc5b | 198 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 199 | 0, |
Kojto | 39:d96aa62afc5b | 200 | DMAC3_CHCFG_n_REN_SHIFT, |
Kojto | 39:d96aa62afc5b | 201 | DMAC3_CHCFG_n_REN); |
Kojto | 39:d96aa62afc5b | 202 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 203 | 0, |
Kojto | 39:d96aa62afc5b | 204 | DMAC3_CHCFG_n_RSW_SHIFT, |
Kojto | 39:d96aa62afc5b | 205 | DMAC3_CHCFG_n_RSW); |
Kojto | 39:d96aa62afc5b | 206 | } |
Kojto | 39:d96aa62afc5b | 207 | |
Kojto | 39:d96aa62afc5b | 208 | /* TM : Single transfer */ |
Kojto | 39:d96aa62afc5b | 209 | /* SEL : Channel setting */ |
Kojto | 39:d96aa62afc5b | 210 | /* HIEN, LOEN : On-chip peripheral module request */ |
Kojto | 39:d96aa62afc5b | 211 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 212 | 0, |
Kojto | 39:d96aa62afc5b | 213 | DMAC3_CHCFG_n_TM_SHIFT, |
Kojto | 39:d96aa62afc5b | 214 | DMAC3_CHCFG_n_TM); |
Kojto | 39:d96aa62afc5b | 215 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 216 | 3, |
Kojto | 39:d96aa62afc5b | 217 | DMAC3_CHCFG_n_SEL_SHIFT, |
Kojto | 39:d96aa62afc5b | 218 | DMAC3_CHCFG_n_SEL); |
Kojto | 39:d96aa62afc5b | 219 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 220 | 1, |
Kojto | 39:d96aa62afc5b | 221 | DMAC3_CHCFG_n_HIEN_SHIFT, |
Kojto | 39:d96aa62afc5b | 222 | DMAC3_CHCFG_n_HIEN); |
Kojto | 39:d96aa62afc5b | 223 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 224 | 0, |
Kojto | 39:d96aa62afc5b | 225 | DMAC3_CHCFG_n_LOEN_SHIFT, |
Kojto | 39:d96aa62afc5b | 226 | DMAC3_CHCFG_n_LOEN); |
Kojto | 39:d96aa62afc5b | 227 | |
Kojto | 39:d96aa62afc5b | 228 | /* ---- Set factor by specified on-chip peripheral module request ---- */ |
Kojto | 39:d96aa62afc5b | 229 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 230 | usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM], |
Kojto | 39:d96aa62afc5b | 231 | DMAC3_CHCFG_n_AM_SHIFT, |
Kojto | 39:d96aa62afc5b | 232 | DMAC3_CHCFG_n_AM); |
Kojto | 39:d96aa62afc5b | 233 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 234 | usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL], |
Kojto | 39:d96aa62afc5b | 235 | DMAC3_CHCFG_n_LVL_SHIFT, |
Kojto | 39:d96aa62afc5b | 236 | DMAC3_CHCFG_n_LVL); |
Kojto | 39:d96aa62afc5b | 237 | if (usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE) |
Kojto | 39:d96aa62afc5b | 238 | { |
Kojto | 39:d96aa62afc5b | 239 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 240 | usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD], |
Kojto | 39:d96aa62afc5b | 241 | DMAC3_CHCFG_n_REQD_SHIFT, |
Kojto | 39:d96aa62afc5b | 242 | DMAC3_CHCFG_n_REQD); |
Kojto | 39:d96aa62afc5b | 243 | } |
Kojto | 39:d96aa62afc5b | 244 | else |
Kojto | 39:d96aa62afc5b | 245 | { |
Kojto | 39:d96aa62afc5b | 246 | RZA_IO_RegWrite_32(&DMAC3.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 247 | req_direction, |
Kojto | 39:d96aa62afc5b | 248 | DMAC3_CHCFG_n_REQD_SHIFT, |
Kojto | 39:d96aa62afc5b | 249 | DMAC3_CHCFG_n_REQD); |
Kojto | 39:d96aa62afc5b | 250 | } |
Kojto | 39:d96aa62afc5b | 251 | RZA_IO_RegWrite_32(&DMAC23.DMARS, |
Kojto | 39:d96aa62afc5b | 252 | usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID], |
Kojto | 39:d96aa62afc5b | 253 | DMAC23_DMARS_CH3_RID_SHIFT, |
Kojto | 39:d96aa62afc5b | 254 | DMAC23_DMARS_CH3_RID); |
Kojto | 39:d96aa62afc5b | 255 | RZA_IO_RegWrite_32(&DMAC23.DMARS, |
Kojto | 39:d96aa62afc5b | 256 | usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID], |
Kojto | 39:d96aa62afc5b | 257 | DMAC23_DMARS_CH3_MID_SHIFT, |
Kojto | 39:d96aa62afc5b | 258 | DMAC23_DMARS_CH3_MID); |
Kojto | 39:d96aa62afc5b | 259 | |
Kojto | 39:d96aa62afc5b | 260 | /* PR : Round robin mode */ |
Kojto | 39:d96aa62afc5b | 261 | RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7, |
Kojto | 39:d96aa62afc5b | 262 | 1, |
Kojto | 39:d96aa62afc5b | 263 | DMAC07_DCTRL_0_7_PR_SHIFT, |
Kojto | 39:d96aa62afc5b | 264 | DMAC07_DCTRL_0_7_PR); |
Kojto | 39:d96aa62afc5b | 265 | } |
Kojto | 39:d96aa62afc5b | 266 | } |
Kojto | 39:d96aa62afc5b | 267 | |
Kojto | 39:d96aa62afc5b | 268 | /******************************************************************************* |
Kojto | 39:d96aa62afc5b | 269 | * Function Name: usb1_host_DMAC3_Open |
Kojto | 39:d96aa62afc5b | 270 | * Description : Enables DMAC channel 3 transfer. |
Kojto | 39:d96aa62afc5b | 271 | * Arguments : uint32_t req : DMAC request mode |
Kojto | 39:d96aa62afc5b | 272 | * Return Value : 0 : Succeeded in enabling DMA transfer |
Kojto | 39:d96aa62afc5b | 273 | * : -1 : Failed to enable DMA transfer (due to DMA operation) |
Kojto | 39:d96aa62afc5b | 274 | *******************************************************************************/ |
Kojto | 39:d96aa62afc5b | 275 | int32_t usb1_host_DMAC3_Open (uint32_t req) |
Kojto | 39:d96aa62afc5b | 276 | { |
Kojto | 39:d96aa62afc5b | 277 | int32_t ret; |
Kojto | 39:d96aa62afc5b | 278 | volatile uint8_t dummy; |
Kojto | 39:d96aa62afc5b | 279 | |
Kojto | 39:d96aa62afc5b | 280 | /* Transferable? */ |
Kojto | 39:d96aa62afc5b | 281 | if ((0 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n, |
Kojto | 39:d96aa62afc5b | 282 | DMAC3_CHSTAT_n_EN_SHIFT, |
Kojto | 39:d96aa62afc5b | 283 | DMAC3_CHSTAT_n_EN)) && |
Kojto | 39:d96aa62afc5b | 284 | (0 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n, |
Kojto | 39:d96aa62afc5b | 285 | DMAC3_CHSTAT_n_TACT_SHIFT, |
Kojto | 39:d96aa62afc5b | 286 | DMAC3_CHSTAT_n_TACT))) |
Kojto | 39:d96aa62afc5b | 287 | { |
Kojto | 39:d96aa62afc5b | 288 | /* Clear Channel Status Register */ |
Kojto | 39:d96aa62afc5b | 289 | RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n, |
Kojto | 39:d96aa62afc5b | 290 | 1, |
Kojto | 39:d96aa62afc5b | 291 | DMAC3_CHCTRL_n_SWRST_SHIFT, |
Kojto | 39:d96aa62afc5b | 292 | DMAC3_CHCTRL_n_SWRST); |
Kojto | 39:d96aa62afc5b | 293 | dummy = RZA_IO_RegRead_32(&DMAC3.CHCTRL_n, |
Kojto | 39:d96aa62afc5b | 294 | DMAC3_CHCTRL_n_SWRST_SHIFT, |
Kojto | 39:d96aa62afc5b | 295 | DMAC3_CHCTRL_n_SWRST); |
Kojto | 39:d96aa62afc5b | 296 | /* Enable DMA transfer */ |
Kojto | 39:d96aa62afc5b | 297 | RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n, |
Kojto | 39:d96aa62afc5b | 298 | 1, |
Kojto | 39:d96aa62afc5b | 299 | DMAC3_CHCTRL_n_SETEN_SHIFT, |
Kojto | 39:d96aa62afc5b | 300 | DMAC3_CHCTRL_n_SETEN); |
Kojto | 39:d96aa62afc5b | 301 | |
Kojto | 39:d96aa62afc5b | 302 | /* ---- Request by software ---- */ |
Kojto | 39:d96aa62afc5b | 303 | if (DMAC_REQ_MODE_SOFT == req) |
Kojto | 39:d96aa62afc5b | 304 | { |
Kojto | 39:d96aa62afc5b | 305 | /* DMA transfer Request by software */ |
Kojto | 39:d96aa62afc5b | 306 | RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n, |
Kojto | 39:d96aa62afc5b | 307 | 1, |
Kojto | 39:d96aa62afc5b | 308 | DMAC3_CHCTRL_n_STG_SHIFT, |
Kojto | 39:d96aa62afc5b | 309 | DMAC3_CHCTRL_n_STG); |
Kojto | 39:d96aa62afc5b | 310 | } |
Kojto | 39:d96aa62afc5b | 311 | |
Kojto | 39:d96aa62afc5b | 312 | ret = 0; |
Kojto | 39:d96aa62afc5b | 313 | } |
Kojto | 39:d96aa62afc5b | 314 | else |
Kojto | 39:d96aa62afc5b | 315 | { |
Kojto | 39:d96aa62afc5b | 316 | ret = -1; |
Kojto | 39:d96aa62afc5b | 317 | } |
Kojto | 39:d96aa62afc5b | 318 | |
Kojto | 39:d96aa62afc5b | 319 | return ret; |
Kojto | 39:d96aa62afc5b | 320 | } |
Kojto | 39:d96aa62afc5b | 321 | |
Kojto | 39:d96aa62afc5b | 322 | /******************************************************************************* |
Kojto | 39:d96aa62afc5b | 323 | * Function Name: usb1_host_DMAC3_Close |
Kojto | 39:d96aa62afc5b | 324 | * Description : Aborts DMAC channel 3 transfer. Returns the remaining transfer |
Kojto | 39:d96aa62afc5b | 325 | * : byte count at the time of DMA transfer abort to the argument |
Kojto | 39:d96aa62afc5b | 326 | * : *remain. |
Kojto | 39:d96aa62afc5b | 327 | * Arguments : uint32_t * remain : Remaining transfer byte count when |
Kojto | 39:d96aa62afc5b | 328 | * : : DMA transfer is aborted |
Kojto | 39:d96aa62afc5b | 329 | * Return Value : none |
Kojto | 39:d96aa62afc5b | 330 | *******************************************************************************/ |
Kojto | 39:d96aa62afc5b | 331 | void usb1_host_DMAC3_Close (uint32_t * remain) |
Kojto | 39:d96aa62afc5b | 332 | { |
Kojto | 39:d96aa62afc5b | 333 | |
Kojto | 39:d96aa62afc5b | 334 | /* ==== Abort transfer ==== */ |
Kojto | 39:d96aa62afc5b | 335 | RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n, |
Kojto | 39:d96aa62afc5b | 336 | 1, |
Kojto | 39:d96aa62afc5b | 337 | DMAC3_CHCTRL_n_CLREN_SHIFT, |
Kojto | 39:d96aa62afc5b | 338 | DMAC3_CHCTRL_n_CLREN); |
Kojto | 39:d96aa62afc5b | 339 | |
Kojto | 39:d96aa62afc5b | 340 | while (1 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n, |
Kojto | 39:d96aa62afc5b | 341 | DMAC3_CHSTAT_n_TACT_SHIFT, |
Kojto | 39:d96aa62afc5b | 342 | DMAC3_CHSTAT_n_TACT)) |
Kojto | 39:d96aa62afc5b | 343 | { |
Kojto | 39:d96aa62afc5b | 344 | /* Loop until transfer is aborted */ |
Kojto | 39:d96aa62afc5b | 345 | } |
Kojto | 39:d96aa62afc5b | 346 | |
Kojto | 39:d96aa62afc5b | 347 | while (1 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n, |
Kojto | 39:d96aa62afc5b | 348 | DMAC3_CHSTAT_n_EN_SHIFT, |
Kojto | 39:d96aa62afc5b | 349 | DMAC3_CHSTAT_n_EN)) |
Kojto | 39:d96aa62afc5b | 350 | { |
Kojto | 39:d96aa62afc5b | 351 | /* Loop until 0 is set in EN before checking the remaining transfer byte count */ |
Kojto | 39:d96aa62afc5b | 352 | } |
Kojto | 39:d96aa62afc5b | 353 | /* ==== Obtain remaining transfer byte count ==== */ |
Kojto | 39:d96aa62afc5b | 354 | *remain = DMAC3.CRTB_n; |
Kojto | 39:d96aa62afc5b | 355 | } |
Kojto | 39:d96aa62afc5b | 356 | |
Kojto | 39:d96aa62afc5b | 357 | /******************************************************************************* |
Kojto | 39:d96aa62afc5b | 358 | * Function Name: usb1_host_DMAC3_Load_Set |
Kojto | 39:d96aa62afc5b | 359 | * Description : Sets the transfer source address, transfer destination |
Kojto | 39:d96aa62afc5b | 360 | * : address, and total transfer byte count respectively |
Kojto | 39:d96aa62afc5b | 361 | * : specified by the argument src_addr, dst_addr, and count to |
Kojto | 39:d96aa62afc5b | 362 | * : DMAC channel 3 as DMA transfer information. |
Kojto | 39:d96aa62afc5b | 363 | * : Sets the register set selected by the CHCFG_n register |
Kojto | 39:d96aa62afc5b | 364 | * : RSEL bit from the Next0 or Next1 register set. |
Kojto | 39:d96aa62afc5b | 365 | * : This function should be called when DMA transfer of DMAC |
Kojto | 39:d96aa62afc5b | 366 | * : channel 3 is aboted. |
Kojto | 39:d96aa62afc5b | 367 | * Arguments : uint32_t src_addr : Transfer source address |
Kojto | 39:d96aa62afc5b | 368 | * : uint32_t dst_addr : Transfer destination address |
Kojto | 39:d96aa62afc5b | 369 | * : uint32_t count : Total transfer byte count |
Kojto | 39:d96aa62afc5b | 370 | * Return Value : none |
Kojto | 39:d96aa62afc5b | 371 | *******************************************************************************/ |
Kojto | 39:d96aa62afc5b | 372 | void usb1_host_DMAC3_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count) |
Kojto | 39:d96aa62afc5b | 373 | { |
Kojto | 39:d96aa62afc5b | 374 | uint8_t reg_set; |
Kojto | 39:d96aa62afc5b | 375 | |
Kojto | 39:d96aa62afc5b | 376 | /* Obtain register set in use */ |
Kojto | 39:d96aa62afc5b | 377 | reg_set = RZA_IO_RegRead_32(&DMAC3.CHSTAT_n, |
Kojto | 39:d96aa62afc5b | 378 | DMAC3_CHSTAT_n_SR_SHIFT, |
Kojto | 39:d96aa62afc5b | 379 | DMAC3_CHSTAT_n_SR); |
Kojto | 39:d96aa62afc5b | 380 | |
Kojto | 39:d96aa62afc5b | 381 | /* ==== Load ==== */ |
Kojto | 39:d96aa62afc5b | 382 | if (0 == reg_set) |
Kojto | 39:d96aa62afc5b | 383 | { |
Kojto | 39:d96aa62afc5b | 384 | /* ---- Next0 Register Set ---- */ |
Kojto | 39:d96aa62afc5b | 385 | DMAC3.N0SA_n = src_addr; /* Start address of transfer source */ |
Kojto | 39:d96aa62afc5b | 386 | DMAC3.N0DA_n = dst_addr; /* Start address of transfer destination */ |
Kojto | 39:d96aa62afc5b | 387 | DMAC3.N0TB_n = count; /* Total transfer byte count */ |
Kojto | 39:d96aa62afc5b | 388 | } |
Kojto | 39:d96aa62afc5b | 389 | else |
Kojto | 39:d96aa62afc5b | 390 | { |
Kojto | 39:d96aa62afc5b | 391 | /* ---- Next1 Register Set ---- */ |
Kojto | 39:d96aa62afc5b | 392 | DMAC3.N1SA_n = src_addr; /* Start address of transfer source */ |
Kojto | 39:d96aa62afc5b | 393 | DMAC3.N1DA_n = dst_addr; /* Start address of transfer destination */ |
Kojto | 39:d96aa62afc5b | 394 | DMAC3.N1TB_n = count; /* Total transfer byte count */ |
Kojto | 39:d96aa62afc5b | 395 | } |
Kojto | 39:d96aa62afc5b | 396 | } |
Kojto | 39:d96aa62afc5b | 397 | |
Kojto | 39:d96aa62afc5b | 398 | /******************************************************************************* |
Kojto | 39:d96aa62afc5b | 399 | * Function Name: usb1_host_DMAC4_PeriReqInit |
Kojto | 39:d96aa62afc5b | 400 | * Description : Sets the register mode for DMA mode and the on-chip peripheral |
Kojto | 39:d96aa62afc5b | 401 | * : module request for transfer request for DMAC channel 4. |
Kojto | 39:d96aa62afc5b | 402 | * : Executes DMAC initial setting using the DMA information |
Kojto | 39:d96aa62afc5b | 403 | * : specified by the argument *trans_info and the enabled/disabled |
Kojto | 39:d96aa62afc5b | 404 | * : continuous transfer specified by the argument continuation. |
Kojto | 39:d96aa62afc5b | 405 | * : Registers DMAC channel 4 interrupt handler function and sets |
Kojto | 39:d96aa62afc5b | 406 | * : the interrupt priority level. Then enables transfer completion |
Kojto | 39:d96aa62afc5b | 407 | * : interrupt. |
Kojto | 39:d96aa62afc5b | 408 | * Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC |
Kojto | 39:d96aa62afc5b | 409 | * : : register |
Kojto | 39:d96aa62afc5b | 410 | * : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER) |
Kojto | 39:d96aa62afc5b | 411 | * : uint32_t continuation : Set continuous transfer to be valid |
Kojto | 39:d96aa62afc5b | 412 | * : : after DMA transfer has been completed |
Kojto | 39:d96aa62afc5b | 413 | * : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer |
Kojto | 39:d96aa62afc5b | 414 | * : DMAC_SAMPLE_SINGLE : Do not execute continuous |
Kojto | 39:d96aa62afc5b | 415 | * : : transfer |
Kojto | 39:d96aa62afc5b | 416 | * : uint32_t request_factor : Factor for on-chip peripheral module |
Kojto | 39:d96aa62afc5b | 417 | * : : request |
Kojto | 39:d96aa62afc5b | 418 | * : DMAC_REQ_OSTM0TINT : OSTM_0 compare match |
Kojto | 39:d96aa62afc5b | 419 | * : DMAC_REQ_OSTM1TINT : OSTM_1 compare match |
Kojto | 39:d96aa62afc5b | 420 | * : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match |
Kojto | 39:d96aa62afc5b | 421 | * : : |
Kojto | 39:d96aa62afc5b | 422 | * : uint32_t req_direction : Setting value of CHCFG_n register |
Kojto | 39:d96aa62afc5b | 423 | * : : REQD bit |
Kojto | 39:d96aa62afc5b | 424 | * Return Value : none |
Kojto | 39:d96aa62afc5b | 425 | *******************************************************************************/ |
Kojto | 39:d96aa62afc5b | 426 | void usb1_host_DMAC4_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation, |
Kojto | 39:d96aa62afc5b | 427 | uint32_t request_factor, uint32_t req_direction) |
Kojto | 39:d96aa62afc5b | 428 | { |
Kojto | 39:d96aa62afc5b | 429 | /* ==== Register mode ==== */ |
Kojto | 39:d96aa62afc5b | 430 | if (DMAC_MODE_REGISTER == dmamode) |
Kojto | 39:d96aa62afc5b | 431 | { |
Kojto | 39:d96aa62afc5b | 432 | /* ==== Next0 register set ==== */ |
Kojto | 39:d96aa62afc5b | 433 | DMAC4.N0SA_n = trans_info->src_addr; /* Start address of transfer source */ |
Kojto | 39:d96aa62afc5b | 434 | DMAC4.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */ |
Kojto | 39:d96aa62afc5b | 435 | DMAC4.N0TB_n = trans_info->count; /* Total transfer byte count */ |
Kojto | 39:d96aa62afc5b | 436 | |
Kojto | 39:d96aa62afc5b | 437 | /* DAD : Transfer destination address counting direction */ |
Kojto | 39:d96aa62afc5b | 438 | /* SAD : Transfer source address counting direction */ |
Kojto | 39:d96aa62afc5b | 439 | /* DDS : Transfer destination transfer size */ |
Kojto | 39:d96aa62afc5b | 440 | /* SDS : Transfer source transfer size */ |
Kojto | 39:d96aa62afc5b | 441 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 442 | trans_info->daddr_dir, |
Kojto | 39:d96aa62afc5b | 443 | DMAC4_CHCFG_n_DAD_SHIFT, |
Kojto | 39:d96aa62afc5b | 444 | DMAC4_CHCFG_n_DAD); |
Kojto | 39:d96aa62afc5b | 445 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 446 | trans_info->saddr_dir, |
Kojto | 39:d96aa62afc5b | 447 | DMAC4_CHCFG_n_SAD_SHIFT, |
Kojto | 39:d96aa62afc5b | 448 | DMAC4_CHCFG_n_SAD); |
Kojto | 39:d96aa62afc5b | 449 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 450 | trans_info->dst_size, |
Kojto | 39:d96aa62afc5b | 451 | DMAC4_CHCFG_n_DDS_SHIFT, |
Kojto | 39:d96aa62afc5b | 452 | DMAC4_CHCFG_n_DDS); |
Kojto | 39:d96aa62afc5b | 453 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 454 | trans_info->src_size, |
Kojto | 39:d96aa62afc5b | 455 | DMAC4_CHCFG_n_SDS_SHIFT, |
Kojto | 39:d96aa62afc5b | 456 | DMAC4_CHCFG_n_SDS); |
Kojto | 39:d96aa62afc5b | 457 | |
Kojto | 39:d96aa62afc5b | 458 | /* DMS : Register mode */ |
Kojto | 39:d96aa62afc5b | 459 | /* RSEL : Select Next0 register set */ |
Kojto | 39:d96aa62afc5b | 460 | /* SBE : No discharge of buffer data when aborted */ |
Kojto | 39:d96aa62afc5b | 461 | /* DEM : No DMA interrupt mask */ |
Kojto | 39:d96aa62afc5b | 462 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 463 | 0, |
Kojto | 39:d96aa62afc5b | 464 | DMAC4_CHCFG_n_DMS_SHIFT, |
Kojto | 39:d96aa62afc5b | 465 | DMAC4_CHCFG_n_DMS); |
Kojto | 39:d96aa62afc5b | 466 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 467 | 0, |
Kojto | 39:d96aa62afc5b | 468 | DMAC4_CHCFG_n_RSEL_SHIFT, |
Kojto | 39:d96aa62afc5b | 469 | DMAC4_CHCFG_n_RSEL); |
Kojto | 39:d96aa62afc5b | 470 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 471 | 0, |
Kojto | 39:d96aa62afc5b | 472 | DMAC4_CHCFG_n_SBE_SHIFT, |
Kojto | 39:d96aa62afc5b | 473 | DMAC4_CHCFG_n_SBE); |
Kojto | 39:d96aa62afc5b | 474 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 475 | 0, |
Kojto | 39:d96aa62afc5b | 476 | DMAC4_CHCFG_n_DEM_SHIFT, |
Kojto | 39:d96aa62afc5b | 477 | DMAC4_CHCFG_n_DEM); |
Kojto | 39:d96aa62afc5b | 478 | |
Kojto | 39:d96aa62afc5b | 479 | /* ---- Continuous transfer ---- */ |
Kojto | 39:d96aa62afc5b | 480 | if (DMAC_SAMPLE_CONTINUATION == continuation) |
Kojto | 39:d96aa62afc5b | 481 | { |
Kojto | 39:d96aa62afc5b | 482 | /* REN : Execute continuous transfer */ |
Kojto | 39:d96aa62afc5b | 483 | /* RSW : Change register set when DMA transfer is completed. */ |
Kojto | 39:d96aa62afc5b | 484 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 485 | 1, |
Kojto | 39:d96aa62afc5b | 486 | DMAC4_CHCFG_n_REN_SHIFT, |
Kojto | 39:d96aa62afc5b | 487 | DMAC4_CHCFG_n_REN); |
Kojto | 39:d96aa62afc5b | 488 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 489 | 1, |
Kojto | 39:d96aa62afc5b | 490 | DMAC4_CHCFG_n_RSW_SHIFT, |
Kojto | 39:d96aa62afc5b | 491 | DMAC4_CHCFG_n_RSW); |
Kojto | 39:d96aa62afc5b | 492 | } |
Kojto | 39:d96aa62afc5b | 493 | /* ---- Single transfer ---- */ |
Kojto | 39:d96aa62afc5b | 494 | else |
Kojto | 39:d96aa62afc5b | 495 | { |
Kojto | 39:d96aa62afc5b | 496 | /* REN : Do not execute continuous transfer */ |
Kojto | 39:d96aa62afc5b | 497 | /* RSW : Do not change register set when DMA transfer is completed. */ |
Kojto | 39:d96aa62afc5b | 498 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 499 | 0, |
Kojto | 39:d96aa62afc5b | 500 | DMAC4_CHCFG_n_REN_SHIFT, |
Kojto | 39:d96aa62afc5b | 501 | DMAC4_CHCFG_n_REN); |
Kojto | 39:d96aa62afc5b | 502 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 503 | 0, |
Kojto | 39:d96aa62afc5b | 504 | DMAC4_CHCFG_n_RSW_SHIFT, |
Kojto | 39:d96aa62afc5b | 505 | DMAC4_CHCFG_n_RSW); |
Kojto | 39:d96aa62afc5b | 506 | } |
Kojto | 39:d96aa62afc5b | 507 | |
Kojto | 39:d96aa62afc5b | 508 | /* TM : Single transfer */ |
Kojto | 39:d96aa62afc5b | 509 | /* SEL : Channel setting */ |
Kojto | 39:d96aa62afc5b | 510 | /* HIEN, LOEN : On-chip peripheral module request */ |
Kojto | 39:d96aa62afc5b | 511 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 512 | 0, |
Kojto | 39:d96aa62afc5b | 513 | DMAC4_CHCFG_n_TM_SHIFT, |
Kojto | 39:d96aa62afc5b | 514 | DMAC4_CHCFG_n_TM); |
Kojto | 39:d96aa62afc5b | 515 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 516 | 4, |
Kojto | 39:d96aa62afc5b | 517 | DMAC4_CHCFG_n_SEL_SHIFT, |
Kojto | 39:d96aa62afc5b | 518 | DMAC4_CHCFG_n_SEL); |
Kojto | 39:d96aa62afc5b | 519 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 520 | 1, |
Kojto | 39:d96aa62afc5b | 521 | DMAC4_CHCFG_n_HIEN_SHIFT, |
Kojto | 39:d96aa62afc5b | 522 | DMAC4_CHCFG_n_HIEN); |
Kojto | 39:d96aa62afc5b | 523 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 524 | 0, |
Kojto | 39:d96aa62afc5b | 525 | DMAC4_CHCFG_n_LOEN_SHIFT, |
Kojto | 39:d96aa62afc5b | 526 | DMAC4_CHCFG_n_LOEN); |
Kojto | 39:d96aa62afc5b | 527 | |
Kojto | 39:d96aa62afc5b | 528 | /* ---- Set factor by specified on-chip peripheral module request ---- */ |
Kojto | 39:d96aa62afc5b | 529 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 530 | usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM], |
Kojto | 39:d96aa62afc5b | 531 | DMAC4_CHCFG_n_AM_SHIFT, |
Kojto | 39:d96aa62afc5b | 532 | DMAC4_CHCFG_n_AM); |
Kojto | 39:d96aa62afc5b | 533 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 534 | usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL], |
Kojto | 39:d96aa62afc5b | 535 | DMAC4_CHCFG_n_LVL_SHIFT, |
Kojto | 39:d96aa62afc5b | 536 | DMAC4_CHCFG_n_LVL); |
Kojto | 39:d96aa62afc5b | 537 | if (usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE) |
Kojto | 39:d96aa62afc5b | 538 | { |
Kojto | 39:d96aa62afc5b | 539 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 540 | usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD], |
Kojto | 39:d96aa62afc5b | 541 | DMAC4_CHCFG_n_REQD_SHIFT, |
Kojto | 39:d96aa62afc5b | 542 | DMAC4_CHCFG_n_REQD); |
Kojto | 39:d96aa62afc5b | 543 | } |
Kojto | 39:d96aa62afc5b | 544 | else |
Kojto | 39:d96aa62afc5b | 545 | { |
Kojto | 39:d96aa62afc5b | 546 | RZA_IO_RegWrite_32(&DMAC4.CHCFG_n, |
Kojto | 39:d96aa62afc5b | 547 | req_direction, |
Kojto | 39:d96aa62afc5b | 548 | DMAC4_CHCFG_n_REQD_SHIFT, |
Kojto | 39:d96aa62afc5b | 549 | DMAC4_CHCFG_n_REQD); |
Kojto | 39:d96aa62afc5b | 550 | } |
Kojto | 39:d96aa62afc5b | 551 | RZA_IO_RegWrite_32(&DMAC45.DMARS, |
Kojto | 39:d96aa62afc5b | 552 | usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID], |
Kojto | 39:d96aa62afc5b | 553 | DMAC45_DMARS_CH4_RID_SHIFT, |
Kojto | 39:d96aa62afc5b | 554 | DMAC45_DMARS_CH4_RID); |
Kojto | 39:d96aa62afc5b | 555 | RZA_IO_RegWrite_32(&DMAC45.DMARS, |
Kojto | 39:d96aa62afc5b | 556 | usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID], |
Kojto | 39:d96aa62afc5b | 557 | DMAC45_DMARS_CH4_MID_SHIFT, |
Kojto | 39:d96aa62afc5b | 558 | DMAC45_DMARS_CH4_MID); |
Kojto | 39:d96aa62afc5b | 559 | |
Kojto | 39:d96aa62afc5b | 560 | /* PR : Round robin mode */ |
Kojto | 39:d96aa62afc5b | 561 | RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7, |
Kojto | 39:d96aa62afc5b | 562 | 1, |
Kojto | 39:d96aa62afc5b | 563 | DMAC07_DCTRL_0_7_PR_SHIFT, |
Kojto | 39:d96aa62afc5b | 564 | DMAC07_DCTRL_0_7_PR); |
Kojto | 39:d96aa62afc5b | 565 | } |
Kojto | 39:d96aa62afc5b | 566 | } |
Kojto | 39:d96aa62afc5b | 567 | |
Kojto | 39:d96aa62afc5b | 568 | /******************************************************************************* |
Kojto | 39:d96aa62afc5b | 569 | * Function Name: usb1_host_DMAC4_Open |
Kojto | 39:d96aa62afc5b | 570 | * Description : Enables DMAC channel 4 transfer. |
Kojto | 39:d96aa62afc5b | 571 | * Arguments : uint32_t req : DMAC request mode |
Kojto | 39:d96aa62afc5b | 572 | * Return Value : 0 : Succeeded in enabling DMA transfer |
Kojto | 39:d96aa62afc5b | 573 | * : -1 : Failed to enable DMA transfer (due to DMA operation) |
Kojto | 39:d96aa62afc5b | 574 | *******************************************************************************/ |
Kojto | 39:d96aa62afc5b | 575 | int32_t usb1_host_DMAC4_Open (uint32_t req) |
Kojto | 39:d96aa62afc5b | 576 | { |
Kojto | 39:d96aa62afc5b | 577 | int32_t ret; |
Kojto | 39:d96aa62afc5b | 578 | volatile uint8_t dummy; |
Kojto | 39:d96aa62afc5b | 579 | |
Kojto | 39:d96aa62afc5b | 580 | /* Transferable? */ |
Kojto | 39:d96aa62afc5b | 581 | if ((0 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n, |
Kojto | 39:d96aa62afc5b | 582 | DMAC4_CHSTAT_n_EN_SHIFT, |
Kojto | 39:d96aa62afc5b | 583 | DMAC4_CHSTAT_n_EN)) && |
Kojto | 39:d96aa62afc5b | 584 | (0 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n, |
Kojto | 39:d96aa62afc5b | 585 | DMAC4_CHSTAT_n_TACT_SHIFT, |
Kojto | 39:d96aa62afc5b | 586 | DMAC4_CHSTAT_n_TACT))) |
Kojto | 39:d96aa62afc5b | 587 | { |
Kojto | 39:d96aa62afc5b | 588 | /* Clear Channel Status Register */ |
Kojto | 39:d96aa62afc5b | 589 | RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n, |
Kojto | 39:d96aa62afc5b | 590 | 1, |
Kojto | 39:d96aa62afc5b | 591 | DMAC4_CHCTRL_n_SWRST_SHIFT, |
Kojto | 39:d96aa62afc5b | 592 | DMAC4_CHCTRL_n_SWRST); |
Kojto | 39:d96aa62afc5b | 593 | dummy = RZA_IO_RegRead_32(&DMAC4.CHCTRL_n, |
Kojto | 39:d96aa62afc5b | 594 | DMAC4_CHCTRL_n_SWRST_SHIFT, |
Kojto | 39:d96aa62afc5b | 595 | DMAC4_CHCTRL_n_SWRST); |
Kojto | 39:d96aa62afc5b | 596 | /* Enable DMA transfer */ |
Kojto | 39:d96aa62afc5b | 597 | RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n, |
Kojto | 39:d96aa62afc5b | 598 | 1, |
Kojto | 39:d96aa62afc5b | 599 | DMAC4_CHCTRL_n_SETEN_SHIFT, |
Kojto | 39:d96aa62afc5b | 600 | DMAC4_CHCTRL_n_SETEN); |
Kojto | 39:d96aa62afc5b | 601 | |
Kojto | 39:d96aa62afc5b | 602 | /* ---- Request by software ---- */ |
Kojto | 39:d96aa62afc5b | 603 | if (DMAC_REQ_MODE_SOFT == req) |
Kojto | 39:d96aa62afc5b | 604 | { |
Kojto | 39:d96aa62afc5b | 605 | /* DMA transfer Request by software */ |
Kojto | 39:d96aa62afc5b | 606 | RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n, |
Kojto | 39:d96aa62afc5b | 607 | 1, |
Kojto | 39:d96aa62afc5b | 608 | DMAC4_CHCTRL_n_STG_SHIFT, |
Kojto | 39:d96aa62afc5b | 609 | DMAC4_CHCTRL_n_STG); |
Kojto | 39:d96aa62afc5b | 610 | } |
Kojto | 39:d96aa62afc5b | 611 | |
Kojto | 39:d96aa62afc5b | 612 | ret = 0; |
Kojto | 39:d96aa62afc5b | 613 | } |
Kojto | 39:d96aa62afc5b | 614 | else |
Kojto | 39:d96aa62afc5b | 615 | { |
Kojto | 39:d96aa62afc5b | 616 | ret = -1; |
Kojto | 39:d96aa62afc5b | 617 | } |
Kojto | 39:d96aa62afc5b | 618 | |
Kojto | 39:d96aa62afc5b | 619 | return ret; |
Kojto | 39:d96aa62afc5b | 620 | } |
Kojto | 39:d96aa62afc5b | 621 | |
Kojto | 39:d96aa62afc5b | 622 | /******************************************************************************* |
Kojto | 39:d96aa62afc5b | 623 | * Function Name: usb1_host_DMAC4_Close |
Kojto | 39:d96aa62afc5b | 624 | * Description : Aborts DMAC channel 4 transfer. Returns the remaining transfer |
Kojto | 39:d96aa62afc5b | 625 | * : byte count at the time of DMA transfer abort to the argument |
Kojto | 39:d96aa62afc5b | 626 | * : *remain. |
Kojto | 39:d96aa62afc5b | 627 | * Arguments : uint32_t * remain : Remaining transfer byte count when |
Kojto | 39:d96aa62afc5b | 628 | * : : DMA transfer is aborted |
Kojto | 39:d96aa62afc5b | 629 | * Return Value : none |
Kojto | 39:d96aa62afc5b | 630 | *******************************************************************************/ |
Kojto | 39:d96aa62afc5b | 631 | void usb1_host_DMAC4_Close (uint32_t * remain) |
Kojto | 39:d96aa62afc5b | 632 | { |
Kojto | 39:d96aa62afc5b | 633 | |
Kojto | 39:d96aa62afc5b | 634 | /* ==== Abort transfer ==== */ |
Kojto | 39:d96aa62afc5b | 635 | RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n, |
Kojto | 39:d96aa62afc5b | 636 | 1, |
Kojto | 39:d96aa62afc5b | 637 | DMAC4_CHCTRL_n_CLREN_SHIFT, |
Kojto | 39:d96aa62afc5b | 638 | DMAC4_CHCTRL_n_CLREN); |
Kojto | 39:d96aa62afc5b | 639 | |
Kojto | 39:d96aa62afc5b | 640 | while (1 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n, |
Kojto | 39:d96aa62afc5b | 641 | DMAC4_CHSTAT_n_TACT_SHIFT, |
Kojto | 39:d96aa62afc5b | 642 | DMAC4_CHSTAT_n_TACT)) |
Kojto | 39:d96aa62afc5b | 643 | { |
Kojto | 39:d96aa62afc5b | 644 | /* Loop until transfer is aborted */ |
Kojto | 39:d96aa62afc5b | 645 | } |
Kojto | 39:d96aa62afc5b | 646 | |
Kojto | 39:d96aa62afc5b | 647 | while (1 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n, |
Kojto | 39:d96aa62afc5b | 648 | DMAC4_CHSTAT_n_EN_SHIFT, |
Kojto | 39:d96aa62afc5b | 649 | DMAC4_CHSTAT_n_EN)) |
Kojto | 39:d96aa62afc5b | 650 | { |
Kojto | 39:d96aa62afc5b | 651 | /* Loop until 0 is set in EN before checking the remaining transfer byte count */ |
Kojto | 39:d96aa62afc5b | 652 | } |
Kojto | 39:d96aa62afc5b | 653 | /* ==== Obtain remaining transfer byte count ==== */ |
Kojto | 39:d96aa62afc5b | 654 | *remain = DMAC4.CRTB_n; |
Kojto | 39:d96aa62afc5b | 655 | } |
Kojto | 39:d96aa62afc5b | 656 | |
Kojto | 39:d96aa62afc5b | 657 | /******************************************************************************* |
Kojto | 39:d96aa62afc5b | 658 | * Function Name: usb1_host_DMAC4_Load_Set |
Kojto | 39:d96aa62afc5b | 659 | * Description : Sets the transfer source address, transfer destination |
Kojto | 39:d96aa62afc5b | 660 | * : address, and total transfer byte count respectively |
Kojto | 39:d96aa62afc5b | 661 | * : specified by the argument src_addr, dst_addr, and count to |
Kojto | 39:d96aa62afc5b | 662 | * : DMAC channel 4 as DMA transfer information. |
Kojto | 39:d96aa62afc5b | 663 | * : Sets the register set selected by the CHCFG_n register |
Kojto | 39:d96aa62afc5b | 664 | * : RSEL bit from the Next0 or Next1 register set. |
Kojto | 39:d96aa62afc5b | 665 | * : This function should be called when DMA transfer of DMAC |
Kojto | 39:d96aa62afc5b | 666 | * : channel 4 is aboted. |
Kojto | 39:d96aa62afc5b | 667 | * Arguments : uint32_t src_addr : Transfer source address |
Kojto | 39:d96aa62afc5b | 668 | * : uint32_t dst_addr : Transfer destination address |
Kojto | 39:d96aa62afc5b | 669 | * : uint32_t count : Total transfer byte count |
Kojto | 39:d96aa62afc5b | 670 | * Return Value : none |
Kojto | 39:d96aa62afc5b | 671 | *******************************************************************************/ |
Kojto | 39:d96aa62afc5b | 672 | void usb1_host_DMAC4_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count) |
Kojto | 39:d96aa62afc5b | 673 | { |
Kojto | 39:d96aa62afc5b | 674 | uint8_t reg_set; |
Kojto | 39:d96aa62afc5b | 675 | |
Kojto | 39:d96aa62afc5b | 676 | /* Obtain register set in use */ |
Kojto | 39:d96aa62afc5b | 677 | reg_set = RZA_IO_RegRead_32(&DMAC4.CHSTAT_n, |
Kojto | 39:d96aa62afc5b | 678 | DMAC4_CHSTAT_n_SR_SHIFT, |
Kojto | 39:d96aa62afc5b | 679 | DMAC4_CHSTAT_n_SR); |
Kojto | 39:d96aa62afc5b | 680 | |
Kojto | 39:d96aa62afc5b | 681 | /* ==== Load ==== */ |
Kojto | 39:d96aa62afc5b | 682 | if (0 == reg_set) |
Kojto | 39:d96aa62afc5b | 683 | { |
Kojto | 39:d96aa62afc5b | 684 | /* ---- Next0 Register Set ---- */ |
Kojto | 39:d96aa62afc5b | 685 | DMAC4.N0SA_n = src_addr; /* Start address of transfer source */ |
Kojto | 39:d96aa62afc5b | 686 | DMAC4.N0DA_n = dst_addr; /* Start address of transfer destination */ |
Kojto | 39:d96aa62afc5b | 687 | DMAC4.N0TB_n = count; /* Total transfer byte count */ |
Kojto | 39:d96aa62afc5b | 688 | } |
Kojto | 39:d96aa62afc5b | 689 | else |
Kojto | 39:d96aa62afc5b | 690 | { |
Kojto | 39:d96aa62afc5b | 691 | /* ---- Next1 Register Set ---- */ |
Kojto | 39:d96aa62afc5b | 692 | DMAC4.N1SA_n = src_addr; /* Start address of transfer source */ |
Kojto | 39:d96aa62afc5b | 693 | DMAC4.N1DA_n = dst_addr; /* Start address of transfer destination */ |
Kojto | 39:d96aa62afc5b | 694 | DMAC4.N1TB_n = count; /* Total transfer byte count */ |
Kojto | 39:d96aa62afc5b | 695 | } |
Kojto | 39:d96aa62afc5b | 696 | } |
Kojto | 39:d96aa62afc5b | 697 | |
Kojto | 39:d96aa62afc5b | 698 | /* End of File */ |