Matthew Sims
Lab 1 Program C
Fork of mbed by
LPC23xx.h@0:82220227f4fa, 2008-04-08 (annotated)
- Committer:
- simon.ford@mbed.co.uk
- Date:
- Tue Apr 08 14:12:21 2008 +0000
- Revision:
- 0:82220227f4fa
- Child:
- 1:6b7f447ca868
A first develoment release of the mbed libraries
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1 | /****************************************************************************** |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 2 | * LPC23xx.h: Header file for NXP LPC23xx/24xx Family Microprocessors |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 3 | * The header file is the super set of all hardware definition of the |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 4 | * peripherals for the LPC23xx/24xx family microprocessor. |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 5 | * |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 6 | * Copyright(C) 2006, NXP Semiconductor |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 7 | * All rights reserved. |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 8 | * |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 9 | * History |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 10 | * 2005.10.01 ver 1.00 Prelimnary version, first Release |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 11 | * 2007.05.17 ver 1.01 several corrections |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 12 | * |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 13 | ******************************************************************************/ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 14 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 15 | #ifndef __LPC23xx_H |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 16 | #define __LPC23xx_H |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 17 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 18 | /* Vectored Interrupt Controller (VIC) */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 19 | #define VIC_BASE_ADDR 0xFFFFF000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 20 | #define VICIRQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x000)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 21 | #define VICFIQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x004)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 22 | #define VICRawIntr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x008)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 23 | #define VICIntSelect (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x00C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 24 | #define VICIntEnable (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x010)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 25 | #define VICIntEnClr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x014)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 26 | #define VICSoftInt (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x018)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 27 | #define VICSoftIntClr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x01C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 28 | #define VICProtection (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x020)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 29 | #define VICSWPrioMask (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x024)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 30 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 31 | #define VICVectAddr0 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x100)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 32 | #define VICVectAddr1 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x104)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 33 | #define VICVectAddr2 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x108)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 34 | #define VICVectAddr3 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x10C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 35 | #define VICVectAddr4 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x110)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 36 | #define VICVectAddr5 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x114)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 37 | #define VICVectAddr6 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x118)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 38 | #define VICVectAddr7 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x11C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 39 | #define VICVectAddr8 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x120)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 40 | #define VICVectAddr9 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x124)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 41 | #define VICVectAddr10 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x128)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 42 | #define VICVectAddr11 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x12C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 43 | #define VICVectAddr12 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x130)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 44 | #define VICVectAddr13 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x134)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 45 | #define VICVectAddr14 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x138)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 46 | #define VICVectAddr15 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x13C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 47 | #define VICVectAddr16 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x140)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 48 | #define VICVectAddr17 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x144)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 49 | #define VICVectAddr18 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x148)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 50 | #define VICVectAddr19 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x14C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 51 | #define VICVectAddr20 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x150)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 52 | #define VICVectAddr21 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x154)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 53 | #define VICVectAddr22 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x158)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 54 | #define VICVectAddr23 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x15C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 55 | #define VICVectAddr24 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x160)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 56 | #define VICVectAddr25 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x164)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 57 | #define VICVectAddr26 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x168)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 58 | #define VICVectAddr27 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x16C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 59 | #define VICVectAddr28 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x170)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 60 | #define VICVectAddr29 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x174)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 61 | #define VICVectAddr30 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x178)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 62 | #define VICVectAddr31 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x17C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 63 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 64 | /* The name convention below is from previous LPC2000 family MCUs, in LPC23xx/24xx, |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 65 | these registers are known as "VICVectPriority(x)". */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 66 | #define VICVectCntl0 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x200)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 67 | #define VICVectCntl1 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x204)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 68 | #define VICVectCntl2 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x208)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 69 | #define VICVectCntl3 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x20C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 70 | #define VICVectCntl4 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x210)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 71 | #define VICVectCntl5 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x214)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 72 | #define VICVectCntl6 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x218)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 73 | #define VICVectCntl7 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x21C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 74 | #define VICVectCntl8 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x220)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 75 | #define VICVectCntl9 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x224)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 76 | #define VICVectCntl10 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x228)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 77 | #define VICVectCntl11 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x22C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 78 | #define VICVectCntl12 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x230)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 79 | #define VICVectCntl13 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x234)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 80 | #define VICVectCntl14 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x238)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 81 | #define VICVectCntl15 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x23C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 82 | #define VICVectCntl16 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x240)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 83 | #define VICVectCntl17 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x244)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 84 | #define VICVectCntl18 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x248)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 85 | #define VICVectCntl19 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x24C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 86 | #define VICVectCntl20 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x250)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 87 | #define VICVectCntl21 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x254)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 88 | #define VICVectCntl22 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x258)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 89 | #define VICVectCntl23 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x25C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 90 | #define VICVectCntl24 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x260)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 91 | #define VICVectCntl25 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x264)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 92 | #define VICVectCntl26 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x268)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 93 | #define VICVectCntl27 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x26C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 94 | #define VICVectCntl28 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x270)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 95 | #define VICVectCntl29 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x274)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 96 | #define VICVectCntl30 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x278)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 97 | #define VICVectCntl31 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x27C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 98 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 99 | #define VICVectAddr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0xF00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 100 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 101 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 102 | /* Pin Connect Block */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 103 | #define PINSEL_BASE_ADDR 0xE002C000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 104 | #define PINSEL0 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 105 | #define PINSEL1 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 106 | #define PINSEL2 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x08)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 107 | #define PINSEL3 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x0C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 108 | #define PINSEL4 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x10)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 109 | #define PINSEL5 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x14)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 110 | #define PINSEL6 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x18)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 111 | #define PINSEL7 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x1C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 112 | #define PINSEL8 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x20)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 113 | #define PINSEL9 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x24)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 114 | #define PINSEL10 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x28)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 115 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 116 | #define PINMODE0 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x40)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 117 | #define PINMODE1 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x44)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 118 | #define PINMODE2 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x48)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 119 | #define PINMODE3 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x4C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 120 | #define PINMODE4 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x50)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 121 | #define PINMODE5 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x54)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 122 | #define PINMODE6 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x58)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 123 | #define PINMODE7 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x5C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 124 | #define PINMODE8 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x60)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 125 | #define PINMODE9 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x64)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 126 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 127 | /* General Purpose Input/Output (GPIO) */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 128 | #define GPIO_BASE_ADDR 0xE0028000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 129 | #define IOPIN0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 130 | #define IOSET0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 131 | #define IODIR0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x08)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 132 | #define IOCLR0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x0C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 133 | #define IOPIN1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x10)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 134 | #define IOSET1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x14)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 135 | #define IODIR1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x18)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 136 | #define IOCLR1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x1C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 137 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 138 | /* GPIO Interrupt Registers */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 139 | #define IO0_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x90)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 140 | #define IO0_INT_EN_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x94)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 141 | #define IO0_INT_STAT_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x84)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 142 | #define IO0_INT_STAT_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x88)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 143 | #define IO0_INT_CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x8C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 144 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 145 | #define IO2_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB0)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 146 | #define IO2_INT_EN_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB4)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 147 | #define IO2_INT_STAT_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA4)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 148 | #define IO2_INT_STAT_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA8)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 149 | #define IO2_INT_CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xAC)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 150 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 151 | #define IO_INT_STAT (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x80)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 152 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 153 | #define PARTCFG_BASE_ADDR 0x3FFF8000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 154 | #define PARTCFG (*(volatile unsigned long *)(PARTCFG_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 155 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 156 | /* Fast I/O setup */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 157 | #define FIO_BASE_ADDR 0x3FFFC000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 158 | #define FIO0DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 159 | #define FIO0MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x10)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 160 | #define FIO0PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x14)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 161 | #define FIO0SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x18)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 162 | #define FIO0CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x1C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 163 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 164 | #define FIO1DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x20)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 165 | #define FIO1MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x30)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 166 | #define FIO1PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x34)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 167 | #define FIO1SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x38)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 168 | #define FIO1CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x3C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 169 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 170 | #define FIO2DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x40)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 171 | #define FIO2MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x50)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 172 | #define FIO2PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x54)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 173 | #define FIO2SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x58)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 174 | #define FIO2CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x5C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 175 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 176 | #define FIO3DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x60)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 177 | #define FIO3MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x70)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 178 | #define FIO3PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x74)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 179 | #define FIO3SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x78)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 180 | #define FIO3CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x7C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 181 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 182 | #define FIO4DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x80)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 183 | #define FIO4MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x90)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 184 | #define FIO4PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x94)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 185 | #define FIO4SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x98)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 186 | #define FIO4CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x9C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 187 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 188 | /* FIOs can be accessed through WORD, HALF-WORD or BYTE. */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 189 | #define FIO0DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 190 | #define FIO1DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x20)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 191 | #define FIO2DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x40)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 192 | #define FIO3DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x60)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 193 | #define FIO4DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x80)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 194 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 195 | #define FIO0DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x01)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 196 | #define FIO1DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 197 | #define FIO2DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x41)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 198 | #define FIO3DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x61)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 199 | #define FIO4DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x81)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 200 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 201 | #define FIO0DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x02)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 202 | #define FIO1DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x22)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 203 | #define FIO2DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x42)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 204 | #define FIO3DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x62)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 205 | #define FIO4DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x82)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 206 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 207 | #define FIO0DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x03)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 208 | #define FIO1DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x23)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 209 | #define FIO2DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x43)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 210 | #define FIO3DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x63)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 211 | #define FIO4DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x83)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 212 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 213 | #define FIO0DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 214 | #define FIO1DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x20)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 215 | #define FIO2DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x40)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 216 | #define FIO3DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x60)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 217 | #define FIO4DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x80)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 218 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 219 | #define FIO0DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x02)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 220 | #define FIO1DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x22)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 221 | #define FIO2DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x42)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 222 | #define FIO3DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x62)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 223 | #define FIO4DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x82)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 224 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 225 | #define FIO0MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x10)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 226 | #define FIO1MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x30)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 227 | #define FIO2MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x50)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 228 | #define FIO3MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x70)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 229 | #define FIO4MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x90)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 230 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 231 | #define FIO0MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x11)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 232 | #define FIO1MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 233 | #define FIO2MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x51)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 234 | #define FIO3MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x71)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 235 | #define FIO4MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x91)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 236 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 237 | #define FIO0MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x12)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 238 | #define FIO1MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x32)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 239 | #define FIO2MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x52)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 240 | #define FIO3MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x72)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 241 | #define FIO4MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x92)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 242 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 243 | #define FIO0MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x13)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 244 | #define FIO1MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x33)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 245 | #define FIO2MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x53)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 246 | #define FIO3MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x73)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 247 | #define FIO4MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x93)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 248 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 249 | #define FIO0MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x10)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 250 | #define FIO1MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x30)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 251 | #define FIO2MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x50)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 252 | #define FIO3MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x70)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 253 | #define FIO4MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x90)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 254 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 255 | #define FIO0MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x12)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 256 | #define FIO1MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x32)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 257 | #define FIO2MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x52)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 258 | #define FIO3MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x72)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 259 | #define FIO4MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x92)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 260 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 261 | #define FIO0PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x14)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 262 | #define FIO1PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x34)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 263 | #define FIO2PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x54)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 264 | #define FIO3PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x74)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 265 | #define FIO4PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x94)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 266 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 267 | #define FIO0PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x15)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 268 | #define FIO1PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x25)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 269 | #define FIO2PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x55)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 270 | #define FIO3PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x75)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 271 | #define FIO4PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x95)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 272 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 273 | #define FIO0PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x16)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 274 | #define FIO1PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x36)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 275 | #define FIO2PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x56)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 276 | #define FIO3PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x76)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 277 | #define FIO4PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x96)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 278 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 279 | #define FIO0PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x17)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 280 | #define FIO1PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x37)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 281 | #define FIO2PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x57)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 282 | #define FIO3PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x77)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 283 | #define FIO4PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x97)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 284 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 285 | #define FIO0PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x14)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 286 | #define FIO1PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x34)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 287 | #define FIO2PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x54)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 288 | #define FIO3PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x74)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 289 | #define FIO4PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x94)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 290 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 291 | #define FIO0PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x16)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 292 | #define FIO1PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x36)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 293 | #define FIO2PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x56)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 294 | #define FIO3PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x76)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 295 | #define FIO4PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x96)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 296 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 297 | #define FIO0SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x18)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 298 | #define FIO1SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x38)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 299 | #define FIO2SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x58)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 300 | #define FIO3SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x78)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 301 | #define FIO4SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x98)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 302 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 303 | #define FIO0SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x19)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 304 | #define FIO1SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x29)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 305 | #define FIO2SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x59)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 306 | #define FIO3SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x79)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 307 | #define FIO4SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x99)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 308 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 309 | #define FIO0SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1A)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 310 | #define FIO1SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3A)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 311 | #define FIO2SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5A)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 312 | #define FIO3SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7A)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 313 | #define FIO4SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9A)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 314 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 315 | #define FIO0SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1B)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 316 | #define FIO1SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3B)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 317 | #define FIO2SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5B)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 318 | #define FIO3SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7B)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 319 | #define FIO4SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9B)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 320 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 321 | #define FIO0SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x18)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 322 | #define FIO1SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x38)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 323 | #define FIO2SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x58)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 324 | #define FIO3SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x78)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 325 | #define FIO4SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x98)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 326 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 327 | #define FIO0SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1A)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 328 | #define FIO1SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3A)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 329 | #define FIO2SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5A)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 330 | #define FIO3SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7A)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 331 | #define FIO4SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9A)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 332 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 333 | #define FIO0CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 334 | #define FIO1CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 335 | #define FIO2CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 336 | #define FIO3CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 337 | #define FIO4CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 338 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 339 | #define FIO0CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1D)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 340 | #define FIO1CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x2D)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 341 | #define FIO2CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5D)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 342 | #define FIO3CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7D)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 343 | #define FIO4CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9D)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 344 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 345 | #define FIO0CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1E)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 346 | #define FIO1CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3E)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 347 | #define FIO2CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5E)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 348 | #define FIO3CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7E)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 349 | #define FIO4CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9E)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 350 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 351 | #define FIO0CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1F)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 352 | #define FIO1CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3F)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 353 | #define FIO2CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5F)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 354 | #define FIO3CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7F)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 355 | #define FIO4CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9F)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 356 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 357 | #define FIO0CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 358 | #define FIO1CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 359 | #define FIO2CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 360 | #define FIO3CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 361 | #define FIO4CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 362 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 363 | #define FIO0CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1E)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 364 | #define FIO1CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3E)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 365 | #define FIO2CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5E)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 366 | #define FIO3CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7E)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 367 | #define FIO4CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9E)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 368 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 369 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 370 | /* System Control Block(SCB) modules include Memory Accelerator Module, |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 371 | Phase Locked Loop, VPB divider, Power Control, External Interrupt, |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 372 | Reset, and Code Security/Debugging */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 373 | #define SCB_BASE_ADDR 0xE01FC000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 374 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 375 | /* Memory Accelerator Module (MAM) */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 376 | #define MAMCR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x000)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 377 | #define MAMTIM (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x004)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 378 | #define MEMMAP (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x040)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 379 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 380 | /* Phase Locked Loop (PLL) */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 381 | #define PLLCON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x080)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 382 | #define PLLCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x084)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 383 | #define PLLSTAT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x088)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 384 | #define PLLFEED (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x08C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 385 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 386 | /* Power Control */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 387 | #define PCON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C0)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 388 | #define PCONP (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C4)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 389 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 390 | /* Clock Divider */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 391 | // #define APBDIV (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x100)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 392 | #define CCLKCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x104)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 393 | #define USBCLKCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x108)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 394 | #define CLKSRCSEL (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x10C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 395 | #define PCLKSEL0 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A8)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 396 | #define PCLKSEL1 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1AC)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 397 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 398 | /* External Interrupts */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 399 | #define EXTINT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x140)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 400 | #define INTWAKE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x144)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 401 | #define EXTMODE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x148)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 402 | #define EXTPOLAR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x14C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 403 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 404 | /* Reset, reset source identification */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 405 | #define RSIR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x180)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 406 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 407 | /* RSID, code security protection */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 408 | #define CSPR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x184)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 409 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 410 | /* AHB configuration */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 411 | #define AHBCFG1 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x188)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 412 | #define AHBCFG2 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x18C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 413 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 414 | /* System Controls and Status */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 415 | #define SCS (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 416 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 417 | /* MPMC(EMC) registers, note: all the external memory controller(EMC) registers |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 418 | are for LPC24xx only. */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 419 | #define STATIC_MEM0_BASE 0x80000000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 420 | #define STATIC_MEM1_BASE 0x81000000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 421 | #define STATIC_MEM2_BASE 0x82000000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 422 | #define STATIC_MEM3_BASE 0x83000000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 423 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 424 | #define DYNAMIC_MEM0_BASE 0xA0000000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 425 | #define DYNAMIC_MEM1_BASE 0xB0000000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 426 | #define DYNAMIC_MEM2_BASE 0xC0000000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 427 | #define DYNAMIC_MEM3_BASE 0xD0000000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 428 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 429 | /* External Memory Controller (EMC) */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 430 | #define EMC_BASE_ADDR 0xFFE08000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 431 | #define EMC_CTRL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x000)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 432 | #define EMC_STAT (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x004)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 433 | #define EMC_CONFIG (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x008)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 434 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 435 | /* Dynamic RAM access registers */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 436 | #define EMC_DYN_CTRL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x020)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 437 | #define EMC_DYN_RFSH (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x024)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 438 | #define EMC_DYN_RD_CFG (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x028)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 439 | #define EMC_DYN_RP (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x030)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 440 | #define EMC_DYN_RAS (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x034)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 441 | #define EMC_DYN_SREX (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x038)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 442 | #define EMC_DYN_APR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x03C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 443 | #define EMC_DYN_DAL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x040)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 444 | #define EMC_DYN_WR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x044)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 445 | #define EMC_DYN_RC (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x048)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 446 | #define EMC_DYN_RFC (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x04C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 447 | #define EMC_DYN_XSR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x050)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 448 | #define EMC_DYN_RRD (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x054)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 449 | #define EMC_DYN_MRD (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x058)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 450 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 451 | #define EMC_DYN_CFG0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x100)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 452 | #define EMC_DYN_RASCAS0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x104)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 453 | #define EMC_DYN_CFG1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x140)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 454 | #define EMC_DYN_RASCAS1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x144)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 455 | #define EMC_DYN_CFG2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x160)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 456 | #define EMC_DYN_RASCAS2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x164)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 457 | #define EMC_DYN_CFG3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x180)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 458 | #define EMC_DYN_RASCAS3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x184)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 459 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 460 | /* static RAM access registers */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 461 | #define EMC_STA_CFG0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x200)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 462 | #define EMC_STA_WAITWEN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x204)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 463 | #define EMC_STA_WAITOEN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x208)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 464 | #define EMC_STA_WAITRD0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x20C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 465 | #define EMC_STA_WAITPAGE0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x210)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 466 | #define EMC_STA_WAITWR0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x214)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 467 | #define EMC_STA_WAITTURN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x218)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 468 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 469 | #define EMC_STA_CFG1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x220)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 470 | #define EMC_STA_WAITWEN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x224)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 471 | #define EMC_STA_WAITOEN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x228)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 472 | #define EMC_STA_WAITRD1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x22C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 473 | #define EMC_STA_WAITPAGE1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x230)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 474 | #define EMC_STA_WAITWR1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x234)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 475 | #define EMC_STA_WAITTURN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x238)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 476 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 477 | #define EMC_STA_CFG2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x240)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 478 | #define EMC_STA_WAITWEN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x244)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 479 | #define EMC_STA_WAITOEN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x248)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 480 | #define EMC_STA_WAITRD2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x24C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 481 | #define EMC_STA_WAITPAGE2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x250)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 482 | #define EMC_STA_WAITWR2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x254)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 483 | #define EMC_STA_WAITTURN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x258)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 484 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 485 | #define EMC_STA_CFG3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x260)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 486 | #define EMC_STA_WAITWEN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x264)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 487 | #define EMC_STA_WAITOEN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x268)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 488 | #define EMC_STA_WAITRD3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x26C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 489 | #define EMC_STA_WAITPAGE3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x270)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 490 | #define EMC_STA_WAITWR3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x274)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 491 | #define EMC_STA_WAITTURN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x278)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 492 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 493 | #define EMC_STA_EXT_WAIT (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x880)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 494 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 495 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 496 | /* Timer 0 */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 497 | #define TMR0_BASE_ADDR 0xE0004000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 498 | #define T0IR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 499 | #define T0TCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 500 | #define T0TC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x08)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 501 | #define T0PR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x0C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 502 | #define T0PC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x10)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 503 | #define T0MCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x14)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 504 | #define T0MR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x18)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 505 | #define T0MR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x1C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 506 | #define T0MR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x20)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 507 | #define T0MR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x24)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 508 | #define T0CCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x28)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 509 | #define T0CR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x2C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 510 | #define T0CR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x30)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 511 | #define T0CR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x34)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 512 | #define T0CR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x38)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 513 | #define T0EMR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x3C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 514 | #define T0CTCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x70)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 515 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 516 | /* Timer 1 */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 517 | #define TMR1_BASE_ADDR 0xE0008000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 518 | #define T1IR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 519 | #define T1TCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 520 | #define T1TC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x08)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 521 | #define T1PR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x0C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 522 | #define T1PC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x10)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 523 | #define T1MCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x14)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 524 | #define T1MR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x18)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 525 | #define T1MR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x1C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 526 | #define T1MR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x20)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 527 | #define T1MR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x24)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 528 | #define T1CCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x28)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 529 | #define T1CR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x2C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 530 | #define T1CR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x30)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 531 | #define T1CR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x34)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 532 | #define T1CR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x38)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 533 | #define T1EMR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x3C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 534 | #define T1CTCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x70)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 535 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 536 | /* Timer 2 */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 537 | #define TMR2_BASE_ADDR 0xE0070000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 538 | #define T2IR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 539 | #define T2TCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 540 | #define T2TC (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x08)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 541 | #define T2PR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x0C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 542 | #define T2PC (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x10)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 543 | #define T2MCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x14)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 544 | #define T2MR0 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x18)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 545 | #define T2MR1 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x1C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 546 | #define T2MR2 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x20)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 547 | #define T2MR3 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x24)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 548 | #define T2CCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x28)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 549 | #define T2CR0 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x2C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 550 | #define T2CR1 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x30)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 551 | #define T2CR2 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x34)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 552 | #define T2CR3 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x38)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 553 | #define T2EMR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x3C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 554 | #define T2CTCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x70)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 555 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 556 | /* Timer 3 */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 557 | #define TMR3_BASE_ADDR 0xE0074000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 558 | #define T3IR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 559 | #define T3TCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 560 | #define T3TC (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x08)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 561 | #define T3PR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x0C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 562 | #define T3PC (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x10)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 563 | #define T3MCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x14)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 564 | #define T3MR0 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x18)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 565 | #define T3MR1 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x1C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 566 | #define T3MR2 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x20)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 567 | #define T3MR3 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x24)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 568 | #define T3CCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x28)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 569 | #define T3CR0 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x2C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 570 | #define T3CR1 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x30)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 571 | #define T3CR2 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x34)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 572 | #define T3CR3 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x38)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 573 | #define T3EMR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x3C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 574 | #define T3CTCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x70)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 575 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 576 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 577 | /* Pulse Width Modulator (PWM) */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 578 | #define PWM0_BASE_ADDR 0xE0014000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 579 | #define PWM0IR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 580 | #define PWM0TCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 581 | #define PWM0TC (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x08)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 582 | #define PWM0PR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x0C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 583 | #define PWM0PC (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x10)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 584 | #define PWM0MCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x14)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 585 | #define PWM0MR0 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x18)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 586 | #define PWM0MR1 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x1C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 587 | #define PWM0MR2 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x20)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 588 | #define PWM0MR3 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x24)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 589 | #define PWM0CCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x28)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 590 | #define PWM0CR0 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x2C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 591 | #define PWM0CR1 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x30)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 592 | #define PWM0CR2 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x34)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 593 | #define PWM0CR3 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x38)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 594 | #define PWM0EMR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x3C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 595 | #define PWM0MR4 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x40)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 596 | #define PWM0MR5 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x44)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 597 | #define PWM0MR6 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x48)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 598 | #define PWM0PCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x4C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 599 | #define PWM0LER (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x50)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 600 | #define PWM0CTCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x70)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 601 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 602 | #define PWM1_BASE_ADDR 0xE0018000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 603 | #define PWM1IR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 604 | #define PWM1TCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 605 | #define PWM1TC (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x08)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 606 | #define PWM1PR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x0C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 607 | #define PWM1PC (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x10)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 608 | #define PWM1MCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x14)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 609 | #define PWM1MR0 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x18)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 610 | #define PWM1MR1 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x1C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 611 | #define PWM1MR2 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x20)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 612 | #define PWM1MR3 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x24)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 613 | #define PWM1CCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x28)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 614 | #define PWM1CR0 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x2C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 615 | #define PWM1CR1 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x30)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 616 | #define PWM1CR2 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x34)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 617 | #define PWM1CR3 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x38)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 618 | #define PWM1EMR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x3C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 619 | #define PWM1MR4 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x40)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 620 | #define PWM1MR5 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x44)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 621 | #define PWM1MR6 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x48)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 622 | #define PWM1PCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x4C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 623 | #define PWM1LER (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x50)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 624 | #define PWM1CTCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x70)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 625 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 626 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 627 | /* Universal Asynchronous Receiver Transmitter 0 (UART0) */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 628 | #define UART0_BASE_ADDR 0xE000C000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 629 | #define U0RBR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 630 | #define U0THR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 631 | #define U0DLL (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 632 | #define U0DLM (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 633 | #define U0IER (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 634 | #define U0IIR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 635 | #define U0FCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 636 | #define U0LCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x0C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 637 | #define U0LSR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x14)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 638 | #define U0SCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x1C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 639 | #define U0ACR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x20)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 640 | #define U0ICR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x24)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 641 | #define U0FDR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x28)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 642 | #define U0TER (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x30)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 643 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 644 | /* Universal Asynchronous Receiver Transmitter 1 (UART1) */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 645 | #define UART1_BASE_ADDR 0xE0010000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 646 | #define U1RBR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 647 | #define U1THR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 648 | #define U1DLL (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 649 | #define U1DLM (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 650 | #define U1IER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 651 | #define U1IIR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 652 | #define U1FCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 653 | #define U1LCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x0C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 654 | #define U1MCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x10)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 655 | #define U1LSR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x14)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 656 | #define U1MSR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x18)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 657 | #define U1SCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x1C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 658 | #define U1ACR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x20)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 659 | #define U1FDR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x28)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 660 | #define U1TER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x30)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 661 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 662 | /* Universal Asynchronous Receiver Transmitter 2 (UART2) */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 663 | #define UART2_BASE_ADDR 0xE0078000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 664 | #define U2RBR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 665 | #define U2THR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 666 | #define U2DLL (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 667 | #define U2DLM (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 668 | #define U2IER (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 669 | #define U2IIR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 670 | #define U2FCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 671 | #define U2LCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x0C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 672 | #define U2LSR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x14)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 673 | #define U2SCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x1C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 674 | #define U2ACR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x20)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 675 | #define U2ICR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x24)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 676 | #define U2FDR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x28)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 677 | #define U2TER (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x30)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 678 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 679 | /* Universal Asynchronous Receiver Transmitter 3 (UART3) */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 680 | #define UART3_BASE_ADDR 0xE007C000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 681 | #define U3RBR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 682 | #define U3THR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 683 | #define U3DLL (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 684 | #define U3DLM (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 685 | #define U3IER (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 686 | #define U3IIR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 687 | #define U3FCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 688 | #define U3LCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x0C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 689 | #define U3LSR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x14)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 690 | #define U3SCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x1C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 691 | #define U3ACR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x20)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 692 | #define U3ICR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x24)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 693 | #define U3FDR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x28)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 694 | #define U3TER (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x30)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 695 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 696 | /* I2C Interface 0 */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 697 | #define I2C0_BASE_ADDR 0xE001C000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 698 | #define I20CONSET (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 699 | #define I20STAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 700 | #define I20DAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x08)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 701 | #define I20ADR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x0C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 702 | #define I20SCLH (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x10)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 703 | #define I20SCLL (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x14)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 704 | #define I20CONCLR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x18)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 705 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 706 | /* I2C Interface 1 */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 707 | #define I2C1_BASE_ADDR 0xE005C000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 708 | #define I21CONSET (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 709 | #define I21STAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 710 | #define I21DAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x08)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 711 | #define I21ADR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x0C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 712 | #define I21SCLH (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x10)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 713 | #define I21SCLL (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x14)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 714 | #define I21CONCLR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x18)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 715 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 716 | /* I2C Interface 2 */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 717 | #define I2C2_BASE_ADDR 0xE0080000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 718 | #define I22CONSET (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 719 | #define I22STAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 720 | #define I22DAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x08)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 721 | #define I22ADR (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x0C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 722 | #define I22SCLH (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x10)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 723 | #define I22SCLL (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x14)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 724 | #define I22CONCLR (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x18)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 725 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 726 | /* SPI0 (Serial Peripheral Interface 0) */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 727 | #define SPI0_BASE_ADDR 0xE0020000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 728 | #define S0SPCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 729 | #define S0SPSR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 730 | #define S0SPDR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x08)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 731 | #define S0SPCCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x0C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 732 | #define S0SPINT (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x1C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 733 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 734 | /* SSP0 Controller */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 735 | #define SSP0_BASE_ADDR 0xE0068000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 736 | #define SSP0CR0 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 737 | #define SSP0CR1 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 738 | #define SSP0DR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x08)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 739 | #define SSP0SR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x0C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 740 | #define SSP0CPSR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x10)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 741 | #define SSP0IMSC (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x14)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 742 | #define SSP0RIS (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x18)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 743 | #define SSP0MIS (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x1C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 744 | #define SSP0ICR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x20)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 745 | #define SSP0DMACR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x24)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 746 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 747 | /* SSP1 Controller */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 748 | #define SSP1_BASE_ADDR 0xE0030000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 749 | #define SSP1CR0 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 750 | #define SSP1CR1 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 751 | #define SSP1DR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x08)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 752 | #define SSP1SR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x0C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 753 | #define SSP1CPSR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x10)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 754 | #define SSP1IMSC (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x14)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 755 | #define SSP1RIS (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x18)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 756 | #define SSP1MIS (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x1C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 757 | #define SSP1ICR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x20)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 758 | #define SSP1DMACR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x24)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 759 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 760 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 761 | /* Real Time Clock */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 762 | #define RTC_BASE_ADDR 0xE0024000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 763 | #define RTC_ILR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 764 | #define RTC_CTC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 765 | #define RTC_CCR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x08)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 766 | #define RTC_CIIR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x0C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 767 | #define RTC_AMR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x10)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 768 | #define RTC_CTIME0 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x14)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 769 | #define RTC_CTIME1 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x18)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 770 | #define RTC_CTIME2 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x1C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 771 | #define RTC_SEC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x20)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 772 | #define RTC_MIN (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x24)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 773 | #define RTC_HOUR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x28)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 774 | #define RTC_DOM (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x2C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 775 | #define RTC_DOW (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x30)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 776 | #define RTC_DOY (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x34)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 777 | #define RTC_MONTH (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x38)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 778 | #define RTC_YEAR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x3C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 779 | #define RTC_CISS (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x40)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 780 | #define RTC_ALSEC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x60)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 781 | #define RTC_ALMIN (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x64)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 782 | #define RTC_ALHOUR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x68)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 783 | #define RTC_ALDOM (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x6C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 784 | #define RTC_ALDOW (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x70)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 785 | #define RTC_ALDOY (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x74)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 786 | #define RTC_ALMON (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x78)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 787 | #define RTC_ALYEAR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x7C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 788 | #define RTC_PREINT (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x80)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 789 | #define RTC_PREFRAC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x84)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 790 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 791 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 792 | /* A/D Converter 0 (AD0) */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 793 | #define AD0_BASE_ADDR 0xE0034000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 794 | #define AD0CR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 795 | #define AD0GDR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 796 | #define AD0INTEN (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x0C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 797 | #define AD0DR0 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x10)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 798 | #define AD0DR1 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x14)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 799 | #define AD0DR2 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x18)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 800 | #define AD0DR3 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x1C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 801 | #define AD0DR4 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x20)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 802 | #define AD0DR5 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x24)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 803 | #define AD0DR6 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x28)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 804 | #define AD0DR7 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x2C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 805 | #define AD0STAT (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x30)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 806 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 807 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 808 | /* D/A Converter */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 809 | #define DAC_BASE_ADDR 0xE006C000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 810 | #define DACR (*(volatile unsigned long *)(DAC_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 811 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 812 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 813 | /* Watchdog */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 814 | #define WDG_BASE_ADDR 0xE0000000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 815 | #define WDMOD (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 816 | #define WDTC (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 817 | #define WDFEED (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x08)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 818 | #define WDTV (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x0C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 819 | #define WDCLKSEL (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x10)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 820 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 821 | /* CAN CONTROLLERS AND ACCEPTANCE FILTER */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 822 | #define CAN_ACCEPT_BASE_ADDR 0xE003C000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 823 | #define CAN_AFMR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 824 | #define CAN_SFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 825 | #define CAN_SFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x08)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 826 | #define CAN_EFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x0C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 827 | #define CAN_EFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x10)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 828 | #define CAN_EOT (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x14)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 829 | #define CAN_LUT_ERR_ADR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x18)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 830 | #define CAN_LUT_ERR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x1C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 831 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 832 | #define CAN_CENTRAL_BASE_ADDR 0xE0040000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 833 | #define CAN_TX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 834 | #define CAN_RX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 835 | #define CAN_MSR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x08)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 836 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 837 | #define CAN1_BASE_ADDR 0xE0044000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 838 | #define CAN1MOD (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 839 | #define CAN1CMR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 840 | #define CAN1GSR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x08)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 841 | #define CAN1ICR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x0C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 842 | #define CAN1IER (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x10)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 843 | #define CAN1BTR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x14)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 844 | #define CAN1EWL (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x18)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 845 | #define CAN1SR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x1C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 846 | #define CAN1RFS (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x20)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 847 | #define CAN1RID (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x24)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 848 | #define CAN1RDA (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x28)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 849 | #define CAN1RDB (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x2C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 850 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 851 | #define CAN1TFI1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x30)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 852 | #define CAN1TID1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x34)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 853 | #define CAN1TDA1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x38)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 854 | #define CAN1TDB1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x3C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 855 | #define CAN1TFI2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x40)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 856 | #define CAN1TID2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x44)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 857 | #define CAN1TDA2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x48)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 858 | #define CAN1TDB2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x4C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 859 | #define CAN1TFI3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x50)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 860 | #define CAN1TID3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x54)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 861 | #define CAN1TDA3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x58)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 862 | #define CAN1TDB3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x5C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 863 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 864 | #define CAN2_BASE_ADDR 0xE0048000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 865 | #define CAN2MOD (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 866 | #define CAN2CMR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 867 | #define CAN2GSR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x08)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 868 | #define CAN2ICR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x0C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 869 | #define CAN2IER (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x10)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 870 | #define CAN2BTR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x14)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 871 | #define CAN2EWL (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x18)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 872 | #define CAN2SR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x1C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 873 | #define CAN2RFS (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x20)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 874 | #define CAN2RID (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x24)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 875 | #define CAN2RDA (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x28)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 876 | #define CAN2RDB (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x2C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 877 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 878 | #define CAN2TFI1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x30)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 879 | #define CAN2TID1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x34)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 880 | #define CAN2TDA1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x38)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 881 | #define CAN2TDB1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x3C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 882 | #define CAN2TFI2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x40)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 883 | #define CAN2TID2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x44)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 884 | #define CAN2TDA2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x48)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 885 | #define CAN2TDB2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x4C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 886 | #define CAN2TFI3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x50)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 887 | #define CAN2TID3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x54)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 888 | #define CAN2TDA3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x58)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 889 | #define CAN2TDB3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x5C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 890 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 891 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 892 | /* MultiMedia Card Interface(MCI) Controller */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 893 | #define MCI_BASE_ADDR 0xE008C000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 894 | #define MCI_POWER (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 895 | #define MCI_CLOCK (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 896 | #define MCI_ARGUMENT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x08)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 897 | #define MCI_COMMAND (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x0C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 898 | #define MCI_RESP_CMD (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x10)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 899 | #define MCI_RESP0 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x14)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 900 | #define MCI_RESP1 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x18)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 901 | #define MCI_RESP2 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x1C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 902 | #define MCI_RESP3 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x20)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 903 | #define MCI_DATA_TMR (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x24)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 904 | #define MCI_DATA_LEN (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x28)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 905 | #define MCI_DATA_CTRL (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x2C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 906 | #define MCI_DATA_CNT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x30)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 907 | #define MCI_STATUS (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x34)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 908 | #define MCI_CLEAR (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x38)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 909 | #define MCI_MASK0 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x3C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 910 | #define MCI_MASK1 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x40)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 911 | #define MCI_FIFO_CNT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x48)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 912 | #define MCI_FIFO (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x80)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 913 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 914 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 915 | /* I2S Interface Controller (I2S) */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 916 | #define I2S_BASE_ADDR 0xE0088000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 917 | #define I2S_DAO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 918 | #define I2S_DAI (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 919 | #define I2S_TX_FIFO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x08)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 920 | #define I2S_RX_FIFO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x0C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 921 | #define I2S_STATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x10)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 922 | #define I2S_DMA1 (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x14)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 923 | #define I2S_DMA2 (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x18)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 924 | #define I2S_IRQ (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x1C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 925 | #define I2S_TXRATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x20)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 926 | #define I2S_RXRATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x24)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 927 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 928 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 929 | /* General-purpose DMA Controller */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 930 | #define DMA_BASE_ADDR 0xFFE04000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 931 | #define GPDMA_INT_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x000)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 932 | #define GPDMA_INT_TCSTAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x004)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 933 | #define GPDMA_INT_TCCLR (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x008)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 934 | #define GPDMA_INT_ERR_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x00C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 935 | #define GPDMA_INT_ERR_CLR (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x010)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 936 | #define GPDMA_RAW_INT_TCSTAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x014)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 937 | #define GPDMA_RAW_INT_ERR_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x018)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 938 | #define GPDMA_ENABLED_CHNS (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x01C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 939 | #define GPDMA_SOFT_BREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x020)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 940 | #define GPDMA_SOFT_SREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x024)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 941 | #define GPDMA_SOFT_LBREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x028)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 942 | #define GPDMA_SOFT_LSREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x02C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 943 | #define GPDMA_CONFIG (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x030)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 944 | #define GPDMA_SYNC (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x034)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 945 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 946 | /* DMA channel 0 registers */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 947 | #define GPDMA_CH0_SRC (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x100)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 948 | #define GPDMA_CH0_DEST (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x104)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 949 | #define GPDMA_CH0_LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x108)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 950 | #define GPDMA_CH0_CTRL (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x10C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 951 | #define GPDMA_CH0_CFG (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x110)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 952 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 953 | /* DMA channel 1 registers */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 954 | #define GPDMA_CH1_SRC (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x120)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 955 | #define GPDMA_CH1_DEST (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x124)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 956 | #define GPDMA_CH1_LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x128)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 957 | #define GPDMA_CH1_CTRL (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x12C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 958 | #define GPDMA_CH1_CFG (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x130)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 959 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 960 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 961 | /* USB Controller */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 962 | #define USB_INT_BASE_ADDR 0xE01FC1C0 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 963 | #define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 964 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 965 | #define USB_INT_STAT (*(volatile unsigned long *)(USB_INT_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 966 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 967 | /* USB Device Interrupt Registers */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 968 | #define DEV_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 969 | #define DEV_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 970 | #define DEV_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x08)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 971 | #define DEV_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x0C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 972 | #define DEV_INT_PRIO (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 973 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 974 | /* USB Device Endpoint Interrupt Registers */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 975 | #define EP_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x30)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 976 | #define EP_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x34)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 977 | #define EP_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x38)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 978 | #define EP_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x3C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 979 | #define EP_INT_PRIO (*(volatile unsigned long *)(USB_BASE_ADDR + 0x40)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 980 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 981 | /* USB Device Endpoint Realization Registers */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 982 | #define REALIZE_EP (*(volatile unsigned long *)(USB_BASE_ADDR + 0x44)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 983 | #define EP_INDEX (*(volatile unsigned long *)(USB_BASE_ADDR + 0x48)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 984 | #define MAXPACKET_SIZE (*(volatile unsigned long *)(USB_BASE_ADDR + 0x4C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 985 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 986 | /* USB Device Command Reagisters */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 987 | #define CMD_CODE (*(volatile unsigned long *)(USB_BASE_ADDR + 0x10)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 988 | #define CMD_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x14)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 989 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 990 | /* USB Device Data Transfer Registers */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 991 | #define RX_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x18)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 992 | #define TX_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x1C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 993 | #define RX_PLENGTH (*(volatile unsigned long *)(USB_BASE_ADDR + 0x20)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 994 | #define TX_PLENGTH (*(volatile unsigned long *)(USB_BASE_ADDR + 0x24)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 995 | #define USB_CTRL (*(volatile unsigned long *)(USB_BASE_ADDR + 0x28)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 996 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 997 | /* USB Device DMA Registers */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 998 | #define DMA_REQ_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x50)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 999 | #define DMA_REQ_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x54)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1000 | #define DMA_REQ_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x58)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1001 | #define UDCA_HEAD (*(volatile unsigned long *)(USB_BASE_ADDR + 0x80)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1002 | #define EP_DMA_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x84)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1003 | #define EP_DMA_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x88)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1004 | #define EP_DMA_DIS (*(volatile unsigned long *)(USB_BASE_ADDR + 0x8C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1005 | #define DMA_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x90)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1006 | #define DMA_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x94)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1007 | #define EOT_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA0)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1008 | #define EOT_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA4)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1009 | #define EOT_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA8)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1010 | #define NDD_REQ_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0xAC)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1011 | #define NDD_REQ_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB0)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1012 | #define NDD_REQ_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB4)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1013 | #define SYS_ERR_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB8)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1014 | #define SYS_ERR_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0xBC)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1015 | #define SYS_ERR_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0xC0)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1016 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1017 | /* USB Host and OTG registers are for LPC24xx only */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1018 | /* USB Host Controller */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1019 | #define USBHC_BASE_ADDR 0xFFE0C000 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1020 | #define HC_REVISION (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1021 | #define HC_CONTROL (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1022 | #define HC_CMD_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x08)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1023 | #define HC_INT_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x0C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1024 | #define HC_INT_EN (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x10)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1025 | #define HC_INT_DIS (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x14)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1026 | #define HC_HCCA (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x18)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1027 | #define HC_PERIOD_CUR_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x1C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1028 | #define HC_CTRL_HEAD_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x20)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1029 | #define HC_CTRL_CUR_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x24)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1030 | #define HC_BULK_HEAD_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x28)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1031 | #define HC_BULK_CUR_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x2C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1032 | #define HC_DONE_HEAD (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x30)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1033 | #define HC_FM_INTERVAL (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x34)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1034 | #define HC_FM_REMAINING (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x38)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1035 | #define HC_FM_NUMBER (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x3C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1036 | #define HC_PERIOD_START (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x40)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1037 | #define HC_LS_THRHLD (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x44)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1038 | #define HC_RH_DESCA (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x48)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1039 | #define HC_RH_DESCB (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x4C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1040 | #define HC_RH_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x50)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1041 | #define HC_RH_PORT_STAT1 (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x54)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1042 | #define HC_RH_PORT_STAT2 (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x58)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1043 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1044 | /* USB OTG Controller */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1045 | #define USBOTG_BASE_ADDR 0xFFE0C100 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1046 | #define OTG_INT_STAT (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1047 | #define OTG_INT_EN (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1048 | #define OTG_INT_SET (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x08)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1049 | #define OTG_INT_CLR (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x0C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1050 | /* On LPC23xx, the name is USBPortSel, on LPC24xx, the name is OTG_STAT_CTRL */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1051 | #define OTG_STAT_CTRL (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1052 | #define OTG_TIMER (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x14)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1053 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1054 | #define USBOTG_I2C_BASE_ADDR 0xFFE0C300 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1055 | #define OTG_I2C_RX (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1056 | #define OTG_I2C_TX (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1057 | #define OTG_I2C_STS (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1058 | #define OTG_I2C_CTL (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x08)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1059 | #define OTG_I2C_CLKHI (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x0C)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1060 | #define OTG_I2C_CLKLO (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x10)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1061 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1062 | /* On LPC23xx, the names are USBClkCtrl and USBClkSt; on LPC24xx, the names are |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1063 | OTG_CLK_CTRL and OTG_CLK_STAT respectively. */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1064 | #define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0 |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1065 | #define OTG_CLK_CTRL (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1066 | #define OTG_CLK_STAT (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1067 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1068 | /* Note: below three register name convention is for LPC23xx USB device only, match |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1069 | with the spec. update in USB Device Section. */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1070 | #define USBPortSel (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1071 | #define USBClkCtrl (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1072 | #define USBClkSt (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08)) |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1073 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1074 | /* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1075 | #define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1076 | #define MAC_MAC1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1077 | #define MAC_MAC2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1078 | #define MAC_IPGT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1079 | #define MAC_IPGR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1080 | #define MAC_CLRT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1081 | #define MAC_MAXF (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1082 | #define MAC_SUPP (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1083 | #define MAC_TEST (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x01C)) /* TEST reg */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1084 | #define MAC_MCFG (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1085 | #define MAC_MCMD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1086 | #define MAC_MADR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1087 | #define MAC_MWTD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1088 | #define MAC_MRDD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1089 | #define MAC_MIND (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1090 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1091 | #define MAC_SA0 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1092 | #define MAC_SA1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1093 | #define MAC_SA2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1094 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1095 | #define MAC_COMMAND (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x100)) /* Command reg */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1096 | #define MAC_STATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1097 | #define MAC_RXDESCRIPTOR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1098 | #define MAC_RXSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1099 | #define MAC_RXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1100 | #define MAC_RXPRODUCEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1101 | #define MAC_RXCONSUMEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1102 | #define MAC_TXDESCRIPTOR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1103 | #define MAC_TXSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1104 | #define MAC_TXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1105 | #define MAC_TXPRODUCEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1106 | #define MAC_TXCONSUMEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1107 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1108 | #define MAC_TSV0 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1109 | #define MAC_TSV1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1110 | #define MAC_RSV (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1111 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1112 | #define MAC_FLOWCONTROLCNT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1113 | #define MAC_FLOWCONTROLSTS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x174)) /* Flow control status reg */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1114 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1115 | #define MAC_RXFILTERCTRL (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1116 | #define MAC_RXFILTERWOLSTS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1117 | #define MAC_RXFILTERWOLCLR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1118 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1119 | #define MAC_HASHFILTERL (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1120 | #define MAC_HASHFILTERH (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1121 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1122 | #define MAC_INTSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1123 | #define MAC_INTENABLE (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1124 | #define MAC_INTCLEAR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1125 | #define MAC_INTSET (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1126 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1127 | #define MAC_POWERDOWN (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1128 | #define MAC_MODULEID (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */ |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1129 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1130 | |
| simon.ford@mbed.co.uk | 0:82220227f4fa | 1131 | #endif // __LPC23xx_H |