Generic communication interface between the wireless board (mote) and the sensor board. Any kind of sensor board can be connected to the mote using this specification given it provides a SPI peripheral, one input pin with interrupt capability and one digital output. The sensor board must implement a special register set from which all required information can be retrieved. Protocol: http://is.gd/wuQorh Github: http://is.gd/ySj1L9
SLCD/LCDconfig.h@1:acdf490d94a7, 2014-04-08 (annotated)
- Committer:
- marcelobarrosalmeida
- Date:
- Tue Apr 08 16:34:20 2014 +0000
- Revision:
- 1:acdf490d94a7
Adding accel to sensor list
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| marcelobarrosalmeida | 1:acdf490d94a7 | 1 | #include "FRDM-s401.h" // 4x7 segdisplay |
| marcelobarrosalmeida | 1:acdf490d94a7 | 2 | |
| marcelobarrosalmeida | 1:acdf490d94a7 | 3 | |
| marcelobarrosalmeida | 1:acdf490d94a7 | 4 | #if 1 // VREF to VLL1 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 5 | /* Following configuration is used for LCD default initialization */ |
| marcelobarrosalmeida | 1:acdf490d94a7 | 6 | #define _LCDRVEN (1) // |
| marcelobarrosalmeida | 1:acdf490d94a7 | 7 | #define _LCDRVTRIM (8) // CPSEL = 1 0 -- 8000 pf 1 -- 6000 pf 2 -- 4000 pf 3 -- 2000 pf |
| marcelobarrosalmeida | 1:acdf490d94a7 | 8 | #define _LCDCPSEL (1) // charge pump select 0 or 1 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 9 | #define _LCDLOADADJUST (3) // CPSEL = 1 0 -- 8000 pf 1 -- 6000 pf 2 -- 4000 pf 3 -- 2000 pf |
| marcelobarrosalmeida | 1:acdf490d94a7 | 10 | #define _LCDALTDIV (0) // CPSEL = 1 0 -- 8000 pf 1 -- 6000 pf 2 -- 4000 pf 3 -- 2000 pf |
| marcelobarrosalmeida | 1:acdf490d94a7 | 11 | #define _LCDALRCLKSOURCE (0) // 0 -- External clock 1 -- Alternate clock |
| marcelobarrosalmeida | 1:acdf490d94a7 | 12 | |
| marcelobarrosalmeida | 1:acdf490d94a7 | 13 | #define _LCDCLKPSL (0) // Clock divider to generate the LCD Waveforms |
| marcelobarrosalmeida | 1:acdf490d94a7 | 14 | #define _LCDSUPPLY (1) |
| marcelobarrosalmeida | 1:acdf490d94a7 | 15 | #define _LCDHREF (0) // 0 or 1 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 16 | #define _LCDCLKSOURCE (1) // 0 -- External clock 1 -- Alternate clock |
| marcelobarrosalmeida | 1:acdf490d94a7 | 17 | #define _LCDLCK (1) //Any number between 0 and 7 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 18 | #define _LCDBLINKRATE (3) //Any number between 0 and 7 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 19 | |
| marcelobarrosalmeida | 1:acdf490d94a7 | 20 | |
| marcelobarrosalmeida | 1:acdf490d94a7 | 21 | #else //VLL3 to VDD internally |
| marcelobarrosalmeida | 1:acdf490d94a7 | 22 | /* Following configuration is used for LCD default initialization */ |
| marcelobarrosalmeida | 1:acdf490d94a7 | 23 | #define _LCDCLKSOURCE (1) // 0 -- External clock 1 -- Alternate clock |
| marcelobarrosalmeida | 1:acdf490d94a7 | 24 | #define _LCDALRCLKSOURCE (0) // 0 -- External clock 1 -- Alternate clock |
| marcelobarrosalmeida | 1:acdf490d94a7 | 25 | #define _LCDCLKPSL (0) // Clock divider to generate the LCD Waveforms |
| marcelobarrosalmeida | 1:acdf490d94a7 | 26 | #define _LCDSUPPLY (0) |
| marcelobarrosalmeida | 1:acdf490d94a7 | 27 | #define _LCDLOADADJUST (3) // CPSEL = 1 0 -- 8000 pf 1 -- 6000 pf 2 -- 4000 pf 3 -- 2000 pf |
| marcelobarrosalmeida | 1:acdf490d94a7 | 28 | #define _LCDALTDIV (0) // CPSEL = 1 0 -- 8000 pf 1 -- 6000 pf 2 -- 4000 pf 3 -- 2000 pf |
| marcelobarrosalmeida | 1:acdf490d94a7 | 29 | #define _LCDRVTRIM (0) // CPSEL = 1 0 -- 8000 pf 1 -- 6000 pf 2 -- 4000 pf 3 -- 2000 pf |
| marcelobarrosalmeida | 1:acdf490d94a7 | 30 | #define _LCDHREF (0) // 0 or 1 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 31 | #define _LCDCPSEL (1) // 0 or 1 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 32 | #define _LCDRVEN (0) // |
| marcelobarrosalmeida | 1:acdf490d94a7 | 33 | #define _LCDBLINKRATE (3) // Any number between 0 and 7 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 34 | #define _LCDLCK (0) // Any number between 0 and 7 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 35 | |
| marcelobarrosalmeida | 1:acdf490d94a7 | 36 | #endif |
| marcelobarrosalmeida | 1:acdf490d94a7 | 37 | |
| marcelobarrosalmeida | 1:acdf490d94a7 | 38 | |
| marcelobarrosalmeida | 1:acdf490d94a7 | 39 | |
| marcelobarrosalmeida | 1:acdf490d94a7 | 40 | |
| marcelobarrosalmeida | 1:acdf490d94a7 | 41 | /*~|~|~|~|~|~|~|~|~|~|~|~|~|~ LCD Control Register 0 ~|~|~|~|~|~|~|~|~|~|~|~|~*/ |
| marcelobarrosalmeida | 1:acdf490d94a7 | 42 | /*~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|*/ |
| marcelobarrosalmeida | 1:acdf490d94a7 | 43 | #define _LCDINTENABLE (1) |
| marcelobarrosalmeida | 1:acdf490d94a7 | 44 | |
| marcelobarrosalmeida | 1:acdf490d94a7 | 45 | /*~|~|~|~|~|~|~|~|~|~|~|~|~|~ LCD Control Register 1 ~|~|~|~|~|~|~|~|~|~|~|~|~|*/ |
| marcelobarrosalmeida | 1:acdf490d94a7 | 46 | /*~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|*/ |
| marcelobarrosalmeida | 1:acdf490d94a7 | 47 | #define _LCDFRAMEINTERRUPT (0) //0 Disable Frame Frequency Interrupt |
| marcelobarrosalmeida | 1:acdf490d94a7 | 48 | //1 Enable an LCD interrupt that coincides with the LCD frame frequency |
| marcelobarrosalmeida | 1:acdf490d94a7 | 49 | #define _LCDFULLCPLDIRIVE (0) // 0 GPIO shared with the LCD. Inputs levels and internal pullup reference to VDD |
| marcelobarrosalmeida | 1:acdf490d94a7 | 50 | // 1 If VSUPPLY=11and RVEN=0. Inputs levels and internal pullup reference to VLL3 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 51 | #define _LCDWAITMODE (0) // 0 Allows the LCD driver and charge pump to continue running during wait mode |
| marcelobarrosalmeida | 1:acdf490d94a7 | 52 | // 1 Disable the LCD when the MCU goes into wait mode |
| marcelobarrosalmeida | 1:acdf490d94a7 | 53 | #define _LCDSTOPMODE (0) // 0 Allows the LCD driver and charge pump to continue running during stop2 or stop3 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 54 | // 1 Disable the LCD when and charge pump when the MCU goes into stop2 or stop3 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 55 | |
| marcelobarrosalmeida | 1:acdf490d94a7 | 56 | /*~|~|~|~|~|~|~|~|~|~|~|~|~|~ LCD Voltage Supply Register ~|~|~|~|~|~|~|~|~|~|~|~*/ |
| marcelobarrosalmeida | 1:acdf490d94a7 | 57 | /*~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|*/ |
| marcelobarrosalmeida | 1:acdf490d94a7 | 58 | #define _LCDHIGHREF (0) //0 Divide input VIREG=1.0v |
| marcelobarrosalmeida | 1:acdf490d94a7 | 59 | //1 Do not divide the input VIREG=1.67v |
| marcelobarrosalmeida | 1:acdf490d94a7 | 60 | #define _LCDBBYPASS (0) //Determines whether the internal LCD op amp buffer is bypassed |
| marcelobarrosalmeida | 1:acdf490d94a7 | 61 | //0 Buffered mode |
| marcelobarrosalmeida | 1:acdf490d94a7 | 62 | //1 Unbuffered mode |
| marcelobarrosalmeida | 1:acdf490d94a7 | 63 | |
| marcelobarrosalmeida | 1:acdf490d94a7 | 64 | /*~|~|~|~|~|~|~|~|~|~|~|~|~|~ LCD Regulated Voltage Control |~|~|~|~|~|~|~|~|~|~*/ |
| marcelobarrosalmeida | 1:acdf490d94a7 | 65 | /*~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|*/ |
| marcelobarrosalmeida | 1:acdf490d94a7 | 66 | #define _LCDCONTRAST (1) //Contrast by software 0 -- Disable 1-- Enable |
| marcelobarrosalmeida | 1:acdf490d94a7 | 67 | #define _LVLCONTRAST (0) //Any number between 0 and 15, if the number is bigger the glass gets darker |
| marcelobarrosalmeida | 1:acdf490d94a7 | 68 | |
| marcelobarrosalmeida | 1:acdf490d94a7 | 69 | /*~|~|~|~|~|~|~|~|~|~|~|~|~|~ LCD Blink Control Register ~|~|~|~|~|~|~|~|~|~|~|~*/ |
| marcelobarrosalmeida | 1:acdf490d94a7 | 70 | /*~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|*/ |
| marcelobarrosalmeida | 1:acdf490d94a7 | 71 | #define _LCDBLINKCONTROL (1) //0 Disable blink mode |
| marcelobarrosalmeida | 1:acdf490d94a7 | 72 | //1 Enable blink mode |
| marcelobarrosalmeida | 1:acdf490d94a7 | 73 | #define _LCDALTMODE (0) //0 Normal display |
| marcelobarrosalmeida | 1:acdf490d94a7 | 74 | //1 Alternate display for 4 backplanes or less the LCD backplane sequencer changes to otuput an alternate display |
| marcelobarrosalmeida | 1:acdf490d94a7 | 75 | #define _LCDBLANKDISP (0) //0 Do not blank display |
| marcelobarrosalmeida | 1:acdf490d94a7 | 76 | //1 Blank display if you put it in 0 the text before blank is manteined |
| marcelobarrosalmeida | 1:acdf490d94a7 | 77 | #define _LCDBLINKMODE (0) //0 Display blank during the blink period |
| marcelobarrosalmeida | 1:acdf490d94a7 | 78 | //1 Display alternate displat during blink period (Ignored if duty is 5 or greater) |
| marcelobarrosalmeida | 1:acdf490d94a7 | 79 | |
| marcelobarrosalmeida | 1:acdf490d94a7 | 80 | |
| marcelobarrosalmeida | 1:acdf490d94a7 | 81 | //Calculated values |
| marcelobarrosalmeida | 1:acdf490d94a7 | 82 | #define _LCDUSEDPINS (_LCDFRONTPLANES + _LCDBACKPLANES) |
| marcelobarrosalmeida | 1:acdf490d94a7 | 83 | #define _LCDDUTY (_LCDBACKPLANES-1) //Any number between 0 and 7 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 84 | #define LCD_WF_BASE LCD->WF8B[0] |
| marcelobarrosalmeida | 1:acdf490d94a7 | 85 | |
| marcelobarrosalmeida | 1:acdf490d94a7 | 86 | // General definitions used by the LCD library |
| marcelobarrosalmeida | 1:acdf490d94a7 | 87 | #define LCD_WF(x) *((uint8 *)&LCD_WF_BASE + x) |
| marcelobarrosalmeida | 1:acdf490d94a7 | 88 | |
| marcelobarrosalmeida | 1:acdf490d94a7 | 89 | /*LCD Fault Detections Consts*/ |
| marcelobarrosalmeida | 1:acdf490d94a7 | 90 | #define FP_TYPE 0x00 // pin is a Front Plane |
| marcelobarrosalmeida | 1:acdf490d94a7 | 91 | #define BP_TYPE 0x80 // pin is Back Plane |
| marcelobarrosalmeida | 1:acdf490d94a7 | 92 | |
| marcelobarrosalmeida | 1:acdf490d94a7 | 93 | // Fault Detect Preescaler Options |
| marcelobarrosalmeida | 1:acdf490d94a7 | 94 | #define FDPRS_1 0 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 95 | #define FDPRS_2 1 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 96 | #define FDPRS_4 2 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 97 | #define FDPRS_8 3 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 98 | #define FDPRS_16 4 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 99 | #define FDPRS_32 5 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 100 | #define FDPRS_64 6 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 101 | #define FDPRS_128 7 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 102 | |
| marcelobarrosalmeida | 1:acdf490d94a7 | 103 | // Fault Detect Sample Window Width Values |
| marcelobarrosalmeida | 1:acdf490d94a7 | 104 | #define FDSWW_4 0 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 105 | #define FDSWW_8 1 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 106 | #define FDSWW_16 2 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 107 | #define FDSWW_32 3 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 108 | #define FDSWW_64 4 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 109 | #define FDSWW_128 5 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 110 | #define FDSWW_256 6 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 111 | #define FDSWW_512 7 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 112 | |
| marcelobarrosalmeida | 1:acdf490d94a7 | 113 | /* |
| marcelobarrosalmeida | 1:acdf490d94a7 | 114 | Mask Bit definitions used f |
| marcelobarrosalmeida | 1:acdf490d94a7 | 115 | */ |
| marcelobarrosalmeida | 1:acdf490d94a7 | 116 | #define mBIT0 1 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 117 | #define mBIT1 2 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 118 | #define mBIT2 4 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 119 | #define mBIT3 8 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 120 | #define mBIT4 16 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 121 | #define mBIT5 32 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 122 | #define mBIT6 64 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 123 | #define mBIT7 128 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 124 | #define mBIT8 256 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 125 | #define mBIT9 512 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 126 | #define mBIT10 1024 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 127 | #define mBIT11 2048 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 128 | #define mBIT12 4096 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 129 | #define mBIT13 8192 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 130 | #define mBIT14 16384 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 131 | #define mBIT15 32768 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 132 | #define mBIT16 65536 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 133 | #define mBIT17 131072 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 134 | #define mBIT18 262144 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 135 | #define mBIT19 524288 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 136 | #define mBIT20 1048576 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 137 | #define mBIT21 2097152 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 138 | #define mBIT22 4194304 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 139 | #define mBIT23 8388608 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 140 | #define mBIT24 16777216 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 141 | #define mBIT25 33554432 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 142 | #define mBIT26 67108864 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 143 | #define mBIT27 134217728 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 144 | #define mBIT28 268435456 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 145 | #define mBIT29 536870912 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 146 | #define mBIT30 1073741824 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 147 | #define mBIT31 2147483648 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 148 | |
| marcelobarrosalmeida | 1:acdf490d94a7 | 149 | #define mBIT32 1 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 150 | #define mBIT33 2 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 151 | #define mBIT34 4 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 152 | #define mBIT35 8 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 153 | #define mBIT36 16 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 154 | #define mBIT37 32 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 155 | #define mBIT38 64 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 156 | #define mBIT39 128 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 157 | #define mBIT40 256 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 158 | #define mBIT41 512 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 159 | #define mBIT42 1024 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 160 | #define mBIT43 2048 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 161 | #define mBIT44 4096 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 162 | #define mBIT45 8192 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 163 | #define mBIT46 16384 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 164 | #define mBIT47 32768 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 165 | #define mBIT48 65536 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 166 | #define mBIT49 131072 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 167 | #define mBIT50 262144 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 168 | #define mBIT51 524288 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 169 | #define mBIT52 1048576 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 170 | #define mBIT53 2097152 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 171 | #define mBIT54 4194304 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 172 | #define mBIT55 8388608 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 173 | #define mBIT56 16777216 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 174 | #define mBIT57 33554432 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 175 | #define mBIT58 67108864 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 176 | #define mBIT59 134217728 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 177 | #define mBIT60 268435456 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 178 | #define mBIT61 536870912 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 179 | #define mBIT62 1073741824 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 180 | #define mBIT63 2147483648 |
| marcelobarrosalmeida | 1:acdf490d94a7 | 181 | |
| marcelobarrosalmeida | 1:acdf490d94a7 | 182 | |
| marcelobarrosalmeida | 1:acdf490d94a7 | 183 |