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targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/stm32f411xe.h@613:bc40b8d2aec4, 2015-08-20 (annotated)

Committer:
mbed_official
Date:
Thu Aug 20 10:45:13 2015 +0100
Revision:
613:bc40b8d2aec4
Parent:
532:fe11edbda85c 
Synchronized with git revision 92ca8c7b60a283b6bb60eb65b183dac1599f0ade



Full URL: https://github.com/mbedmicro/mbed/commit/92ca8c7b60a283b6bb60eb65b183dac1599f0ade/



Nordic: update application start address in GCC linker script

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UserRevisionLine numberNew contents of line
mbed_official 441:d2c15dda23c1 1 /**
mbed_official 441:d2c15dda23c1 2 ******************************************************************************
mbed_official 441:d2c15dda23c1 3 * @file stm32f411xe.h
mbed_official 441:d2c15dda23c1 4 * @author MCD Application Team
mbed_official 613:bc40b8d2aec4 5 * @version V2.3.2
mbed_official 613:bc40b8d2aec4 6 * @date 26-June-2015
mbed_official 441:d2c15dda23c1 7 * @brief CMSIS STM32F411xExx Device Peripheral Access Layer Header File.
mbed_official 441:d2c15dda23c1 8 *
mbed_official 441:d2c15dda23c1 9 * This file contains:
mbed_official 441:d2c15dda23c1 10 * - Data structures and the address mapping for all peripherals
mbed_official 441:d2c15dda23c1 11 * - Peripheral's registers declarations and bits definition
mbed_official 532:fe11edbda85c 12 * - Macros to access peripheral’s registers hardware
mbed_official 441:d2c15dda23c1 13 *
mbed_official 441:d2c15dda23c1 14 ******************************************************************************
mbed_official 441:d2c15dda23c1 15 * @attention
mbed_official 441:d2c15dda23c1 16 *
mbed_official 532:fe11edbda85c 17 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official 441:d2c15dda23c1 18 *
mbed_official 441:d2c15dda23c1 19 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 441:d2c15dda23c1 20 * are permitted provided that the following conditions are met:
mbed_official 441:d2c15dda23c1 21 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 441:d2c15dda23c1 22 * this list of conditions and the following disclaimer.
mbed_official 441:d2c15dda23c1 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 441:d2c15dda23c1 24 * this list of conditions and the following disclaimer in the documentation
mbed_official 441:d2c15dda23c1 25 * and/or other materials provided with the distribution.
mbed_official 441:d2c15dda23c1 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 441:d2c15dda23c1 27 * may be used to endorse or promote products derived from this software
mbed_official 441:d2c15dda23c1 28 * without specific prior written permission.
mbed_official 441:d2c15dda23c1 29 *
mbed_official 441:d2c15dda23c1 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 441:d2c15dda23c1 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 441:d2c15dda23c1 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 441:d2c15dda23c1 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 441:d2c15dda23c1 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 441:d2c15dda23c1 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 441:d2c15dda23c1 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 441:d2c15dda23c1 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 441:d2c15dda23c1 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 441:d2c15dda23c1 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 441:d2c15dda23c1 40 *
mbed_official 441:d2c15dda23c1 41 ******************************************************************************
mbed_official 441:d2c15dda23c1 42 */
mbed_official 441:d2c15dda23c1 43
mbed_official 441:d2c15dda23c1 44 /** @addtogroup CMSIS
mbed_official 441:d2c15dda23c1 45 * @{
mbed_official 441:d2c15dda23c1 46 */
mbed_official 441:d2c15dda23c1 47
mbed_official 532:fe11edbda85c 48 /** @addtogroup stm32f401xe
mbed_official 441:d2c15dda23c1 49 * @{
mbed_official 441:d2c15dda23c1 50 */
mbed_official 441:d2c15dda23c1 51
mbed_official 532:fe11edbda85c 52 #ifndef __STM32F401xE_H
mbed_official 532:fe11edbda85c 53 #define __STM32F401xE_H
mbed_official 441:d2c15dda23c1 54
mbed_official 441:d2c15dda23c1 55 #ifdef __cplusplus
mbed_official 441:d2c15dda23c1 56 extern "C" {
mbed_official 441:d2c15dda23c1 57 #endif /* __cplusplus */
mbed_official 441:d2c15dda23c1 58
mbed_official 441:d2c15dda23c1 59
mbed_official 441:d2c15dda23c1 60 /** @addtogroup Configuration_section_for_CMSIS
mbed_official 441:d2c15dda23c1 61 * @{
mbed_official 441:d2c15dda23c1 62 */
mbed_official 441:d2c15dda23c1 63
mbed_official 441:d2c15dda23c1 64 /**
mbed_official 441:d2c15dda23c1 65 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
mbed_official 441:d2c15dda23c1 66 */
mbed_official 441:d2c15dda23c1 67 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
mbed_official 441:d2c15dda23c1 68 #define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
mbed_official 441:d2c15dda23c1 69 #define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
mbed_official 441:d2c15dda23c1 70 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
mbed_official 441:d2c15dda23c1 71 #define __FPU_PRESENT 1 /*!< FPU present */
mbed_official 441:d2c15dda23c1 72
mbed_official 441:d2c15dda23c1 73 /**
mbed_official 441:d2c15dda23c1 74 * @}
mbed_official 441:d2c15dda23c1 75 */
mbed_official 441:d2c15dda23c1 76
mbed_official 441:d2c15dda23c1 77 /** @addtogroup Peripheral_interrupt_number_definition
mbed_official 441:d2c15dda23c1 78 * @{
mbed_official 441:d2c15dda23c1 79 */
mbed_official 441:d2c15dda23c1 80
mbed_official 441:d2c15dda23c1 81 /**
mbed_official 441:d2c15dda23c1 82 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
mbed_official 441:d2c15dda23c1 83 * in @ref Library_configuration_section
mbed_official 441:d2c15dda23c1 84 */
mbed_official 441:d2c15dda23c1 85 typedef enum
mbed_official 441:d2c15dda23c1 86 {
mbed_official 441:d2c15dda23c1 87 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
mbed_official 441:d2c15dda23c1 88 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
mbed_official 441:d2c15dda23c1 89 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
mbed_official 441:d2c15dda23c1 90 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
mbed_official 441:d2c15dda23c1 91 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
mbed_official 441:d2c15dda23c1 92 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
mbed_official 441:d2c15dda23c1 93 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
mbed_official 441:d2c15dda23c1 94 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
mbed_official 441:d2c15dda23c1 95 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
mbed_official 441:d2c15dda23c1 96 /****** STM32 specific Interrupt Numbers **********************************************************************/
mbed_official 441:d2c15dda23c1 97 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
mbed_official 441:d2c15dda23c1 98 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
mbed_official 441:d2c15dda23c1 99 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
mbed_official 441:d2c15dda23c1 100 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
mbed_official 441:d2c15dda23c1 101 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
mbed_official 441:d2c15dda23c1 102 RCC_IRQn = 5, /*!< RCC global Interrupt */
mbed_official 441:d2c15dda23c1 103 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
mbed_official 441:d2c15dda23c1 104 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
mbed_official 441:d2c15dda23c1 105 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
mbed_official 441:d2c15dda23c1 106 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
mbed_official 441:d2c15dda23c1 107 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
mbed_official 441:d2c15dda23c1 108 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
mbed_official 441:d2c15dda23c1 109 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
mbed_official 441:d2c15dda23c1 110 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
mbed_official 441:d2c15dda23c1 111 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
mbed_official 441:d2c15dda23c1 112 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
mbed_official 441:d2c15dda23c1 113 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
mbed_official 441:d2c15dda23c1 114 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
mbed_official 441:d2c15dda23c1 115 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
mbed_official 441:d2c15dda23c1 116 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
mbed_official 441:d2c15dda23c1 117 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
mbed_official 441:d2c15dda23c1 118 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
mbed_official 441:d2c15dda23c1 119 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
mbed_official 441:d2c15dda23c1 120 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
mbed_official 441:d2c15dda23c1 121 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
mbed_official 441:d2c15dda23c1 122 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
mbed_official 441:d2c15dda23c1 123 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
mbed_official 441:d2c15dda23c1 124 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
mbed_official 441:d2c15dda23c1 125 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
mbed_official 441:d2c15dda23c1 126 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
mbed_official 441:d2c15dda23c1 127 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
mbed_official 441:d2c15dda23c1 128 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
mbed_official 441:d2c15dda23c1 129 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
mbed_official 441:d2c15dda23c1 130 USART1_IRQn = 37, /*!< USART1 global Interrupt */
mbed_official 441:d2c15dda23c1 131 USART2_IRQn = 38, /*!< USART2 global Interrupt */
mbed_official 441:d2c15dda23c1 132 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
mbed_official 441:d2c15dda23c1 133 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
mbed_official 441:d2c15dda23c1 134 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
mbed_official 441:d2c15dda23c1 135 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
mbed_official 441:d2c15dda23c1 136 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
mbed_official 441:d2c15dda23c1 137 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
mbed_official 441:d2c15dda23c1 138 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
mbed_official 441:d2c15dda23c1 139 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
mbed_official 441:d2c15dda23c1 140 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
mbed_official 441:d2c15dda23c1 141 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
mbed_official 441:d2c15dda23c1 142 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
mbed_official 441:d2c15dda23c1 143 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
mbed_official 441:d2c15dda23c1 144 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
mbed_official 441:d2c15dda23c1 145 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
mbed_official 441:d2c15dda23c1 146 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
mbed_official 441:d2c15dda23c1 147 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
mbed_official 441:d2c15dda23c1 148 USART6_IRQn = 71, /*!< USART6 global interrupt */
mbed_official 441:d2c15dda23c1 149 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
mbed_official 441:d2c15dda23c1 150 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
mbed_official 441:d2c15dda23c1 151 FPU_IRQn = 81, /*!< FPU global interrupt */
mbed_official 441:d2c15dda23c1 152 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
mbed_official 441:d2c15dda23c1 153 SPI5_IRQn = 85 /*!< SPI5 global Interrupt */
mbed_official 441:d2c15dda23c1 154 } IRQn_Type;
mbed_official 441:d2c15dda23c1 155
mbed_official 441:d2c15dda23c1 156 /**
mbed_official 441:d2c15dda23c1 157 * @}
mbed_official 441:d2c15dda23c1 158 */
mbed_official 441:d2c15dda23c1 159
mbed_official 441:d2c15dda23c1 160 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
mbed_official 441:d2c15dda23c1 161 #include "system_stm32f4xx.h"
mbed_official 441:d2c15dda23c1 162 #include <stdint.h>
mbed_official 441:d2c15dda23c1 163
mbed_official 441:d2c15dda23c1 164 /** @addtogroup Peripheral_registers_structures
mbed_official 441:d2c15dda23c1 165 * @{
mbed_official 441:d2c15dda23c1 166 */
mbed_official 441:d2c15dda23c1 167
mbed_official 441:d2c15dda23c1 168 /**
mbed_official 441:d2c15dda23c1 169 * @brief Analog to Digital Converter
mbed_official 441:d2c15dda23c1 170 */
mbed_official 441:d2c15dda23c1 171
mbed_official 441:d2c15dda23c1 172 typedef struct
mbed_official 441:d2c15dda23c1 173 {
mbed_official 441:d2c15dda23c1 174 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
mbed_official 441:d2c15dda23c1 175 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
mbed_official 441:d2c15dda23c1 176 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
mbed_official 441:d2c15dda23c1 177 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
mbed_official 441:d2c15dda23c1 178 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
mbed_official 441:d2c15dda23c1 179 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
mbed_official 441:d2c15dda23c1 180 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
mbed_official 441:d2c15dda23c1 181 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
mbed_official 441:d2c15dda23c1 182 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
mbed_official 441:d2c15dda23c1 183 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
mbed_official 441:d2c15dda23c1 184 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
mbed_official 441:d2c15dda23c1 185 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
mbed_official 441:d2c15dda23c1 186 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
mbed_official 441:d2c15dda23c1 187 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
mbed_official 441:d2c15dda23c1 188 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
mbed_official 441:d2c15dda23c1 189 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
mbed_official 441:d2c15dda23c1 190 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
mbed_official 441:d2c15dda23c1 191 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
mbed_official 441:d2c15dda23c1 192 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
mbed_official 441:d2c15dda23c1 193 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
mbed_official 441:d2c15dda23c1 194 } ADC_TypeDef;
mbed_official 441:d2c15dda23c1 195
mbed_official 441:d2c15dda23c1 196 typedef struct
mbed_official 441:d2c15dda23c1 197 {
mbed_official 441:d2c15dda23c1 198 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
mbed_official 441:d2c15dda23c1 199 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
mbed_official 441:d2c15dda23c1 200 __IO uint32_t CDR; /*!< ADC common regular data register for dual
mbed_official 441:d2c15dda23c1 201 AND triple modes, Address offset: ADC1 base address + 0x308 */
mbed_official 441:d2c15dda23c1 202 } ADC_Common_TypeDef;
mbed_official 441:d2c15dda23c1 203
mbed_official 441:d2c15dda23c1 204 /**
mbed_official 441:d2c15dda23c1 205 * @brief CRC calculation unit
mbed_official 441:d2c15dda23c1 206 */
mbed_official 441:d2c15dda23c1 207
mbed_official 441:d2c15dda23c1 208 typedef struct
mbed_official 441:d2c15dda23c1 209 {
mbed_official 441:d2c15dda23c1 210 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
mbed_official 441:d2c15dda23c1 211 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
mbed_official 441:d2c15dda23c1 212 uint8_t RESERVED0; /*!< Reserved, 0x05 */
mbed_official 441:d2c15dda23c1 213 uint16_t RESERVED1; /*!< Reserved, 0x06 */
mbed_official 441:d2c15dda23c1 214 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
mbed_official 441:d2c15dda23c1 215 } CRC_TypeDef;
mbed_official 441:d2c15dda23c1 216
mbed_official 441:d2c15dda23c1 217 /**
mbed_official 441:d2c15dda23c1 218 * @brief Debug MCU
mbed_official 441:d2c15dda23c1 219 */
mbed_official 441:d2c15dda23c1 220
mbed_official 441:d2c15dda23c1 221 typedef struct
mbed_official 441:d2c15dda23c1 222 {
mbed_official 441:d2c15dda23c1 223 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
mbed_official 441:d2c15dda23c1 224 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
mbed_official 441:d2c15dda23c1 225 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
mbed_official 441:d2c15dda23c1 226 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
mbed_official 441:d2c15dda23c1 227 }DBGMCU_TypeDef;
mbed_official 441:d2c15dda23c1 228
mbed_official 441:d2c15dda23c1 229
mbed_official 441:d2c15dda23c1 230 /**
mbed_official 441:d2c15dda23c1 231 * @brief DMA Controller
mbed_official 441:d2c15dda23c1 232 */
mbed_official 441:d2c15dda23c1 233
mbed_official 441:d2c15dda23c1 234 typedef struct
mbed_official 441:d2c15dda23c1 235 {
mbed_official 441:d2c15dda23c1 236 __IO uint32_t CR; /*!< DMA stream x configuration register */
mbed_official 441:d2c15dda23c1 237 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
mbed_official 441:d2c15dda23c1 238 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
mbed_official 441:d2c15dda23c1 239 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
mbed_official 441:d2c15dda23c1 240 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
mbed_official 441:d2c15dda23c1 241 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
mbed_official 441:d2c15dda23c1 242 } DMA_Stream_TypeDef;
mbed_official 441:d2c15dda23c1 243
mbed_official 441:d2c15dda23c1 244 typedef struct
mbed_official 441:d2c15dda23c1 245 {
mbed_official 441:d2c15dda23c1 246 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
mbed_official 441:d2c15dda23c1 247 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
mbed_official 441:d2c15dda23c1 248 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
mbed_official 441:d2c15dda23c1 249 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
mbed_official 441:d2c15dda23c1 250 } DMA_TypeDef;
mbed_official 441:d2c15dda23c1 251
mbed_official 441:d2c15dda23c1 252
mbed_official 441:d2c15dda23c1 253 /**
mbed_official 441:d2c15dda23c1 254 * @brief External Interrupt/Event Controller
mbed_official 441:d2c15dda23c1 255 */
mbed_official 441:d2c15dda23c1 256
mbed_official 441:d2c15dda23c1 257 typedef struct
mbed_official 441:d2c15dda23c1 258 {
mbed_official 441:d2c15dda23c1 259 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
mbed_official 441:d2c15dda23c1 260 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
mbed_official 441:d2c15dda23c1 261 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
mbed_official 441:d2c15dda23c1 262 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
mbed_official 441:d2c15dda23c1 263 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
mbed_official 441:d2c15dda23c1 264 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
mbed_official 441:d2c15dda23c1 265 } EXTI_TypeDef;
mbed_official 441:d2c15dda23c1 266
mbed_official 441:d2c15dda23c1 267 /**
mbed_official 441:d2c15dda23c1 268 * @brief FLASH Registers
mbed_official 441:d2c15dda23c1 269 */
mbed_official 441:d2c15dda23c1 270
mbed_official 441:d2c15dda23c1 271 typedef struct
mbed_official 441:d2c15dda23c1 272 {
mbed_official 441:d2c15dda23c1 273 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
mbed_official 441:d2c15dda23c1 274 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
mbed_official 441:d2c15dda23c1 275 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
mbed_official 441:d2c15dda23c1 276 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
mbed_official 441:d2c15dda23c1 277 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
mbed_official 441:d2c15dda23c1 278 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
mbed_official 441:d2c15dda23c1 279 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
mbed_official 441:d2c15dda23c1 280 } FLASH_TypeDef;
mbed_official 441:d2c15dda23c1 281
mbed_official 441:d2c15dda23c1 282 /**
mbed_official 441:d2c15dda23c1 283 * @brief General Purpose I/O
mbed_official 441:d2c15dda23c1 284 */
mbed_official 441:d2c15dda23c1 285
mbed_official 441:d2c15dda23c1 286 typedef struct
mbed_official 441:d2c15dda23c1 287 {
mbed_official 441:d2c15dda23c1 288 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
mbed_official 441:d2c15dda23c1 289 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
mbed_official 441:d2c15dda23c1 290 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
mbed_official 441:d2c15dda23c1 291 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
mbed_official 441:d2c15dda23c1 292 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
mbed_official 441:d2c15dda23c1 293 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
mbed_official 532:fe11edbda85c 294 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
mbed_official 441:d2c15dda23c1 295 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
mbed_official 441:d2c15dda23c1 296 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
mbed_official 441:d2c15dda23c1 297 } GPIO_TypeDef;
mbed_official 441:d2c15dda23c1 298
mbed_official 441:d2c15dda23c1 299 /**
mbed_official 441:d2c15dda23c1 300 * @brief System configuration controller
mbed_official 441:d2c15dda23c1 301 */
mbed_official 441:d2c15dda23c1 302
mbed_official 441:d2c15dda23c1 303 typedef struct
mbed_official 441:d2c15dda23c1 304 {
mbed_official 441:d2c15dda23c1 305 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
mbed_official 441:d2c15dda23c1 306 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
mbed_official 441:d2c15dda23c1 307 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
mbed_official 441:d2c15dda23c1 308 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
mbed_official 441:d2c15dda23c1 309 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
mbed_official 441:d2c15dda23c1 310 } SYSCFG_TypeDef;
mbed_official 441:d2c15dda23c1 311
mbed_official 441:d2c15dda23c1 312 /**
mbed_official 441:d2c15dda23c1 313 * @brief Inter-integrated Circuit Interface
mbed_official 441:d2c15dda23c1 314 */
mbed_official 441:d2c15dda23c1 315
mbed_official 441:d2c15dda23c1 316 typedef struct
mbed_official 441:d2c15dda23c1 317 {
mbed_official 441:d2c15dda23c1 318 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
mbed_official 441:d2c15dda23c1 319 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
mbed_official 441:d2c15dda23c1 320 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
mbed_official 441:d2c15dda23c1 321 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
mbed_official 441:d2c15dda23c1 322 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
mbed_official 441:d2c15dda23c1 323 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
mbed_official 441:d2c15dda23c1 324 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
mbed_official 441:d2c15dda23c1 325 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
mbed_official 441:d2c15dda23c1 326 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
mbed_official 441:d2c15dda23c1 327 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
mbed_official 441:d2c15dda23c1 328 } I2C_TypeDef;
mbed_official 441:d2c15dda23c1 329
mbed_official 441:d2c15dda23c1 330 /**
mbed_official 441:d2c15dda23c1 331 * @brief Independent WATCHDOG
mbed_official 441:d2c15dda23c1 332 */
mbed_official 441:d2c15dda23c1 333
mbed_official 441:d2c15dda23c1 334 typedef struct
mbed_official 441:d2c15dda23c1 335 {
mbed_official 441:d2c15dda23c1 336 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
mbed_official 441:d2c15dda23c1 337 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
mbed_official 441:d2c15dda23c1 338 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
mbed_official 441:d2c15dda23c1 339 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
mbed_official 441:d2c15dda23c1 340 } IWDG_TypeDef;
mbed_official 441:d2c15dda23c1 341
mbed_official 441:d2c15dda23c1 342 /**
mbed_official 441:d2c15dda23c1 343 * @brief Power Control
mbed_official 441:d2c15dda23c1 344 */
mbed_official 441:d2c15dda23c1 345
mbed_official 441:d2c15dda23c1 346 typedef struct
mbed_official 441:d2c15dda23c1 347 {
mbed_official 441:d2c15dda23c1 348 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
mbed_official 441:d2c15dda23c1 349 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
mbed_official 441:d2c15dda23c1 350 } PWR_TypeDef;
mbed_official 441:d2c15dda23c1 351
mbed_official 441:d2c15dda23c1 352 /**
mbed_official 441:d2c15dda23c1 353 * @brief Reset and Clock Control
mbed_official 441:d2c15dda23c1 354 */
mbed_official 441:d2c15dda23c1 355
mbed_official 441:d2c15dda23c1 356 typedef struct
mbed_official 441:d2c15dda23c1 357 {
mbed_official 441:d2c15dda23c1 358 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
mbed_official 441:d2c15dda23c1 359 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
mbed_official 441:d2c15dda23c1 360 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
mbed_official 441:d2c15dda23c1 361 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
mbed_official 441:d2c15dda23c1 362 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
mbed_official 441:d2c15dda23c1 363 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
mbed_official 441:d2c15dda23c1 364 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
mbed_official 441:d2c15dda23c1 365 uint32_t RESERVED0; /*!< Reserved, 0x1C */
mbed_official 441:d2c15dda23c1 366 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
mbed_official 441:d2c15dda23c1 367 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
mbed_official 441:d2c15dda23c1 368 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
mbed_official 441:d2c15dda23c1 369 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
mbed_official 441:d2c15dda23c1 370 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
mbed_official 441:d2c15dda23c1 371 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
mbed_official 441:d2c15dda23c1 372 uint32_t RESERVED2; /*!< Reserved, 0x3C */
mbed_official 441:d2c15dda23c1 373 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
mbed_official 441:d2c15dda23c1 374 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
mbed_official 441:d2c15dda23c1 375 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
mbed_official 441:d2c15dda23c1 376 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
mbed_official 441:d2c15dda23c1 377 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
mbed_official 441:d2c15dda23c1 378 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
mbed_official 441:d2c15dda23c1 379 uint32_t RESERVED4; /*!< Reserved, 0x5C */
mbed_official 441:d2c15dda23c1 380 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
mbed_official 441:d2c15dda23c1 381 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
mbed_official 441:d2c15dda23c1 382 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
mbed_official 441:d2c15dda23c1 383 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
mbed_official 441:d2c15dda23c1 384 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
mbed_official 441:d2c15dda23c1 385 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
mbed_official 441:d2c15dda23c1 386 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
mbed_official 441:d2c15dda23c1 387 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
mbed_official 441:d2c15dda23c1 388
mbed_official 441:d2c15dda23c1 389 } RCC_TypeDef;
mbed_official 441:d2c15dda23c1 390
mbed_official 441:d2c15dda23c1 391 /**
mbed_official 441:d2c15dda23c1 392 * @brief Real-Time Clock
mbed_official 441:d2c15dda23c1 393 */
mbed_official 441:d2c15dda23c1 394
mbed_official 441:d2c15dda23c1 395 typedef struct
mbed_official 441:d2c15dda23c1 396 {
mbed_official 441:d2c15dda23c1 397 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
mbed_official 441:d2c15dda23c1 398 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
mbed_official 441:d2c15dda23c1 399 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
mbed_official 441:d2c15dda23c1 400 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
mbed_official 441:d2c15dda23c1 401 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
mbed_official 441:d2c15dda23c1 402 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
mbed_official 441:d2c15dda23c1 403 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
mbed_official 441:d2c15dda23c1 404 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
mbed_official 441:d2c15dda23c1 405 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
mbed_official 441:d2c15dda23c1 406 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
mbed_official 441:d2c15dda23c1 407 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
mbed_official 441:d2c15dda23c1 408 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
mbed_official 441:d2c15dda23c1 409 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
mbed_official 441:d2c15dda23c1 410 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
mbed_official 441:d2c15dda23c1 411 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
mbed_official 441:d2c15dda23c1 412 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
mbed_official 441:d2c15dda23c1 413 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
mbed_official 441:d2c15dda23c1 414 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
mbed_official 441:d2c15dda23c1 415 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
mbed_official 441:d2c15dda23c1 416 uint32_t RESERVED7; /*!< Reserved, 0x4C */
mbed_official 441:d2c15dda23c1 417 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
mbed_official 441:d2c15dda23c1 418 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
mbed_official 441:d2c15dda23c1 419 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
mbed_official 441:d2c15dda23c1 420 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
mbed_official 441:d2c15dda23c1 421 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
mbed_official 441:d2c15dda23c1 422 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
mbed_official 441:d2c15dda23c1 423 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
mbed_official 441:d2c15dda23c1 424 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
mbed_official 441:d2c15dda23c1 425 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
mbed_official 441:d2c15dda23c1 426 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
mbed_official 441:d2c15dda23c1 427 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
mbed_official 441:d2c15dda23c1 428 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
mbed_official 441:d2c15dda23c1 429 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
mbed_official 441:d2c15dda23c1 430 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
mbed_official 441:d2c15dda23c1 431 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
mbed_official 441:d2c15dda23c1 432 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
mbed_official 441:d2c15dda23c1 433 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
mbed_official 441:d2c15dda23c1 434 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
mbed_official 441:d2c15dda23c1 435 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
mbed_official 441:d2c15dda23c1 436 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
mbed_official 441:d2c15dda23c1 437 } RTC_TypeDef;
mbed_official 441:d2c15dda23c1 438
mbed_official 441:d2c15dda23c1 439
mbed_official 441:d2c15dda23c1 440 /**
mbed_official 441:d2c15dda23c1 441 * @brief SD host Interface
mbed_official 441:d2c15dda23c1 442 */
mbed_official 441:d2c15dda23c1 443
mbed_official 441:d2c15dda23c1 444 typedef struct
mbed_official 441:d2c15dda23c1 445 {
mbed_official 441:d2c15dda23c1 446 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
mbed_official 441:d2c15dda23c1 447 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
mbed_official 441:d2c15dda23c1 448 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
mbed_official 441:d2c15dda23c1 449 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
mbed_official 441:d2c15dda23c1 450 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
mbed_official 441:d2c15dda23c1 451 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
mbed_official 441:d2c15dda23c1 452 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
mbed_official 441:d2c15dda23c1 453 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
mbed_official 441:d2c15dda23c1 454 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
mbed_official 441:d2c15dda23c1 455 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
mbed_official 441:d2c15dda23c1 456 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
mbed_official 441:d2c15dda23c1 457 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
mbed_official 441:d2c15dda23c1 458 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
mbed_official 441:d2c15dda23c1 459 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
mbed_official 441:d2c15dda23c1 460 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
mbed_official 441:d2c15dda23c1 461 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
mbed_official 441:d2c15dda23c1 462 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
mbed_official 441:d2c15dda23c1 463 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
mbed_official 441:d2c15dda23c1 464 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
mbed_official 441:d2c15dda23c1 465 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
mbed_official 441:d2c15dda23c1 466 } SDIO_TypeDef;
mbed_official 441:d2c15dda23c1 467
mbed_official 441:d2c15dda23c1 468 /**
mbed_official 441:d2c15dda23c1 469 * @brief Serial Peripheral Interface
mbed_official 441:d2c15dda23c1 470 */
mbed_official 441:d2c15dda23c1 471
mbed_official 441:d2c15dda23c1 472 typedef struct
mbed_official 441:d2c15dda23c1 473 {
mbed_official 441:d2c15dda23c1 474 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
mbed_official 441:d2c15dda23c1 475 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
mbed_official 441:d2c15dda23c1 476 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
mbed_official 441:d2c15dda23c1 477 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
mbed_official 441:d2c15dda23c1 478 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
mbed_official 441:d2c15dda23c1 479 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
mbed_official 441:d2c15dda23c1 480 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
mbed_official 441:d2c15dda23c1 481 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
mbed_official 441:d2c15dda23c1 482 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
mbed_official 441:d2c15dda23c1 483 } SPI_TypeDef;
mbed_official 441:d2c15dda23c1 484
mbed_official 441:d2c15dda23c1 485 /**
mbed_official 441:d2c15dda23c1 486 * @brief TIM
mbed_official 441:d2c15dda23c1 487 */
mbed_official 441:d2c15dda23c1 488
mbed_official 441:d2c15dda23c1 489 typedef struct
mbed_official 441:d2c15dda23c1 490 {
mbed_official 441:d2c15dda23c1 491 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
mbed_official 441:d2c15dda23c1 492 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
mbed_official 441:d2c15dda23c1 493 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
mbed_official 441:d2c15dda23c1 494 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
mbed_official 441:d2c15dda23c1 495 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
mbed_official 441:d2c15dda23c1 496 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
mbed_official 441:d2c15dda23c1 497 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
mbed_official 441:d2c15dda23c1 498 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
mbed_official 441:d2c15dda23c1 499 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
mbed_official 441:d2c15dda23c1 500 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
mbed_official 441:d2c15dda23c1 501 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
mbed_official 441:d2c15dda23c1 502 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
mbed_official 441:d2c15dda23c1 503 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
mbed_official 441:d2c15dda23c1 504 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
mbed_official 441:d2c15dda23c1 505 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
mbed_official 441:d2c15dda23c1 506 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
mbed_official 441:d2c15dda23c1 507 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
mbed_official 441:d2c15dda23c1 508 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
mbed_official 441:d2c15dda23c1 509 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
mbed_official 441:d2c15dda23c1 510 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
mbed_official 441:d2c15dda23c1 511 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
mbed_official 441:d2c15dda23c1 512 } TIM_TypeDef;
mbed_official 441:d2c15dda23c1 513
mbed_official 441:d2c15dda23c1 514 /**
mbed_official 441:d2c15dda23c1 515 * @brief Universal Synchronous Asynchronous Receiver Transmitter
mbed_official 441:d2c15dda23c1 516 */
mbed_official 441:d2c15dda23c1 517
mbed_official 441:d2c15dda23c1 518 typedef struct
mbed_official 441:d2c15dda23c1 519 {
mbed_official 441:d2c15dda23c1 520 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
mbed_official 441:d2c15dda23c1 521 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
mbed_official 441:d2c15dda23c1 522 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
mbed_official 441:d2c15dda23c1 523 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
mbed_official 441:d2c15dda23c1 524 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
mbed_official 441:d2c15dda23c1 525 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
mbed_official 441:d2c15dda23c1 526 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
mbed_official 441:d2c15dda23c1 527 } USART_TypeDef;
mbed_official 441:d2c15dda23c1 528
mbed_official 441:d2c15dda23c1 529 /**
mbed_official 441:d2c15dda23c1 530 * @brief Window WATCHDOG
mbed_official 441:d2c15dda23c1 531 */
mbed_official 441:d2c15dda23c1 532
mbed_official 441:d2c15dda23c1 533 typedef struct
mbed_official 441:d2c15dda23c1 534 {
mbed_official 441:d2c15dda23c1 535 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
mbed_official 441:d2c15dda23c1 536 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
mbed_official 441:d2c15dda23c1 537 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
mbed_official 441:d2c15dda23c1 538 } WWDG_TypeDef;
mbed_official 441:d2c15dda23c1 539
mbed_official 441:d2c15dda23c1 540
mbed_official 441:d2c15dda23c1 541 /**
mbed_official 441:d2c15dda23c1 542 * @brief __USB_OTG_Core_register
mbed_official 441:d2c15dda23c1 543 */
mbed_official 441:d2c15dda23c1 544 typedef struct
mbed_official 441:d2c15dda23c1 545 {
mbed_official 441:d2c15dda23c1 546 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset : 0x00 */
mbed_official 441:d2c15dda23c1 547 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset : 0x04 */
mbed_official 441:d2c15dda23c1 548 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset : 0x08 */
mbed_official 441:d2c15dda23c1 549 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset : 0x0C */
mbed_official 441:d2c15dda23c1 550 __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset : 0x10 */
mbed_official 441:d2c15dda23c1 551 __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset : 0x14 */
mbed_official 441:d2c15dda23c1 552 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset : 0x18 */
mbed_official 441:d2c15dda23c1 553 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset : 0x1C */
mbed_official 441:d2c15dda23c1 554 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset : 0x20 */
mbed_official 441:d2c15dda23c1 555 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */
mbed_official 441:d2c15dda23c1 556 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28 */
mbed_official 441:d2c15dda23c1 557 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset : 0x2C */
mbed_official 441:d2c15dda23c1 558 uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */
mbed_official 441:d2c15dda23c1 559 __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset : 0x38 */
mbed_official 441:d2c15dda23c1 560 __IO uint32_t CID; /*!< User ID Register Address offset : 0x3C */
mbed_official 441:d2c15dda23c1 561 uint32_t Reserved40[48]; /*!< Reserved Address offset : 0x40-0xFF */
mbed_official 441:d2c15dda23c1 562 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset : 0x100 */
mbed_official 441:d2c15dda23c1 563 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
mbed_official 441:d2c15dda23c1 564 }
mbed_official 441:d2c15dda23c1 565 USB_OTG_GlobalTypeDef;
mbed_official 441:d2c15dda23c1 566
mbed_official 441:d2c15dda23c1 567
mbed_official 441:d2c15dda23c1 568
mbed_official 441:d2c15dda23c1 569 /**
mbed_official 441:d2c15dda23c1 570 * @brief __device_Registers
mbed_official 441:d2c15dda23c1 571 */
mbed_official 441:d2c15dda23c1 572 typedef struct
mbed_official 441:d2c15dda23c1 573 {
mbed_official 441:d2c15dda23c1 574 __IO uint32_t DCFG; /*!< dev Configuration Register Address offset : 0x800 */
mbed_official 441:d2c15dda23c1 575 __IO uint32_t DCTL; /*!< dev Control Register Address offset : 0x804 */
mbed_official 441:d2c15dda23c1 576 __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset : 0x808 */
mbed_official 441:d2c15dda23c1 577 uint32_t Reserved0C; /*!< Reserved Address offset : 0x80C */
mbed_official 441:d2c15dda23c1 578 __IO uint32_t DIEPMSK; /* !< dev IN Endpoint Mask Address offset : 0x810 */
mbed_official 441:d2c15dda23c1 579 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset : 0x814 */
mbed_official 441:d2c15dda23c1 580 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset : 0x818 */
mbed_official 441:d2c15dda23c1 581 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset : 0x81C */
mbed_official 441:d2c15dda23c1 582 uint32_t Reserved20; /*!< Reserved Address offset : 0x820 */
mbed_official 441:d2c15dda23c1 583 uint32_t Reserved9; /*!< Reserved Address offset : 0x824 */
mbed_official 441:d2c15dda23c1 584 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset : 0x828 */
mbed_official 441:d2c15dda23c1 585 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset : 0x82C */
mbed_official 441:d2c15dda23c1 586 __IO uint32_t DTHRCTL; /*!< dev thr Address offset : 0x830 */
mbed_official 441:d2c15dda23c1 587 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset : 0x834 */
mbed_official 441:d2c15dda23c1 588 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset : 0x838 */
mbed_official 441:d2c15dda23c1 589 __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */
mbed_official 441:d2c15dda23c1 590 uint32_t Reserved40; /*!< dedicated EP mask Address offset : 0x840 */
mbed_official 441:d2c15dda23c1 591 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset : 0x844 */
mbed_official 441:d2c15dda23c1 592 uint32_t Reserved44[15]; /*!< Reserved Address offset : 0x844-0x87C */
mbed_official 441:d2c15dda23c1 593 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */
mbed_official 441:d2c15dda23c1 594 }
mbed_official 441:d2c15dda23c1 595 USB_OTG_DeviceTypeDef;
mbed_official 441:d2c15dda23c1 596
mbed_official 441:d2c15dda23c1 597
mbed_official 441:d2c15dda23c1 598 /**
mbed_official 441:d2c15dda23c1 599 * @brief __IN_Endpoint-Specific_Register
mbed_official 441:d2c15dda23c1 600 */
mbed_official 441:d2c15dda23c1 601 typedef struct
mbed_official 441:d2c15dda23c1 602 {
mbed_official 441:d2c15dda23c1 603 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
mbed_official 441:d2c15dda23c1 604 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */
mbed_official 441:d2c15dda23c1 605 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
mbed_official 441:d2c15dda23c1 606 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */
mbed_official 441:d2c15dda23c1 607 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
mbed_official 441:d2c15dda23c1 608 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
mbed_official 441:d2c15dda23c1 609 __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
mbed_official 441:d2c15dda23c1 610 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
mbed_official 441:d2c15dda23c1 611 }
mbed_official 441:d2c15dda23c1 612 USB_OTG_INEndpointTypeDef;
mbed_official 441:d2c15dda23c1 613
mbed_official 441:d2c15dda23c1 614
mbed_official 441:d2c15dda23c1 615 /**
mbed_official 441:d2c15dda23c1 616 * @brief __OUT_Endpoint-Specific_Registers
mbed_official 441:d2c15dda23c1 617 */
mbed_official 441:d2c15dda23c1 618 typedef struct
mbed_official 441:d2c15dda23c1 619 {
mbed_official 441:d2c15dda23c1 620 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
mbed_official 441:d2c15dda23c1 621 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
mbed_official 441:d2c15dda23c1 622 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
mbed_official 441:d2c15dda23c1 623 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
mbed_official 441:d2c15dda23c1 624 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
mbed_official 441:d2c15dda23c1 625 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
mbed_official 441:d2c15dda23c1 626 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
mbed_official 441:d2c15dda23c1 627 }
mbed_official 441:d2c15dda23c1 628 USB_OTG_OUTEndpointTypeDef;
mbed_official 441:d2c15dda23c1 629
mbed_official 441:d2c15dda23c1 630
mbed_official 441:d2c15dda23c1 631 /**
mbed_official 441:d2c15dda23c1 632 * @brief __Host_Mode_Register_Structures
mbed_official 441:d2c15dda23c1 633 */
mbed_official 441:d2c15dda23c1 634 typedef struct
mbed_official 441:d2c15dda23c1 635 {
mbed_official 441:d2c15dda23c1 636 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
mbed_official 441:d2c15dda23c1 637 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
mbed_official 441:d2c15dda23c1 638 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
mbed_official 441:d2c15dda23c1 639 uint32_t Reserved40C; /* Reserved 40Ch*/
mbed_official 441:d2c15dda23c1 640 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
mbed_official 441:d2c15dda23c1 641 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
mbed_official 441:d2c15dda23c1 642 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
mbed_official 441:d2c15dda23c1 643 }
mbed_official 441:d2c15dda23c1 644 USB_OTG_HostTypeDef;
mbed_official 441:d2c15dda23c1 645
mbed_official 441:d2c15dda23c1 646
mbed_official 441:d2c15dda23c1 647 /**
mbed_official 441:d2c15dda23c1 648 * @brief __Host_Channel_Specific_Registers
mbed_official 441:d2c15dda23c1 649 */
mbed_official 441:d2c15dda23c1 650 typedef struct
mbed_official 441:d2c15dda23c1 651 {
mbed_official 441:d2c15dda23c1 652 __IO uint32_t HCCHAR;
mbed_official 441:d2c15dda23c1 653 __IO uint32_t HCSPLT;
mbed_official 441:d2c15dda23c1 654 __IO uint32_t HCINT;
mbed_official 441:d2c15dda23c1 655 __IO uint32_t HCINTMSK;
mbed_official 441:d2c15dda23c1 656 __IO uint32_t HCTSIZ;
mbed_official 441:d2c15dda23c1 657 __IO uint32_t HCDMA;
mbed_official 441:d2c15dda23c1 658 uint32_t Reserved[2];
mbed_official 441:d2c15dda23c1 659 }
mbed_official 441:d2c15dda23c1 660 USB_OTG_HostChannelTypeDef;
mbed_official 441:d2c15dda23c1 661
mbed_official 441:d2c15dda23c1 662
mbed_official 441:d2c15dda23c1 663 /**
mbed_official 441:d2c15dda23c1 664 * @brief Peripheral_memory_map
mbed_official 441:d2c15dda23c1 665 */
mbed_official 441:d2c15dda23c1 666 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
mbed_official 441:d2c15dda23c1 667 #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
mbed_official 441:d2c15dda23c1 668 #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
mbed_official 441:d2c15dda23c1 669 #define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
mbed_official 441:d2c15dda23c1 670 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
mbed_official 441:d2c15dda23c1 671 #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
mbed_official 441:d2c15dda23c1 672 #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
mbed_official 613:bc40b8d2aec4 673 #define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
mbed_official 441:d2c15dda23c1 674 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
mbed_official 613:bc40b8d2aec4 675 #define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
mbed_official 441:d2c15dda23c1 676 #define FLASH_END ((uint32_t)0x0807FFFF) /*!< FLASH end address */
mbed_official 441:d2c15dda23c1 677
mbed_official 441:d2c15dda23c1 678 /* Legacy defines */
mbed_official 441:d2c15dda23c1 679 #define SRAM_BASE SRAM1_BASE
mbed_official 441:d2c15dda23c1 680 #define SRAM_BB_BASE SRAM1_BB_BASE
mbed_official 441:d2c15dda23c1 681
mbed_official 441:d2c15dda23c1 682
mbed_official 441:d2c15dda23c1 683 /*!< Peripheral memory map */
mbed_official 441:d2c15dda23c1 684 #define APB1PERIPH_BASE PERIPH_BASE
mbed_official 441:d2c15dda23c1 685 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
mbed_official 441:d2c15dda23c1 686 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
mbed_official 441:d2c15dda23c1 687 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
mbed_official 441:d2c15dda23c1 688
mbed_official 441:d2c15dda23c1 689 /*!< APB1 peripherals */
mbed_official 441:d2c15dda23c1 690 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
mbed_official 441:d2c15dda23c1 691 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
mbed_official 441:d2c15dda23c1 692 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
mbed_official 441:d2c15dda23c1 693 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
mbed_official 441:d2c15dda23c1 694 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
mbed_official 441:d2c15dda23c1 695 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
mbed_official 441:d2c15dda23c1 696 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
mbed_official 441:d2c15dda23c1 697 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
mbed_official 441:d2c15dda23c1 698 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
mbed_official 441:d2c15dda23c1 699 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
mbed_official 441:d2c15dda23c1 700 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
mbed_official 441:d2c15dda23c1 701 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
mbed_official 441:d2c15dda23c1 702 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
mbed_official 441:d2c15dda23c1 703 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
mbed_official 441:d2c15dda23c1 704 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
mbed_official 441:d2c15dda23c1 705 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
mbed_official 441:d2c15dda23c1 706
mbed_official 441:d2c15dda23c1 707 /*!< APB2 peripherals */
mbed_official 441:d2c15dda23c1 708 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
mbed_official 441:d2c15dda23c1 709 #define USART1_BASE (APB2PERIPH_BASE + 0x1000)
mbed_official 441:d2c15dda23c1 710 #define USART6_BASE (APB2PERIPH_BASE + 0x1400)
mbed_official 441:d2c15dda23c1 711 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
mbed_official 441:d2c15dda23c1 712 #define ADC_BASE (APB2PERIPH_BASE + 0x2300)
mbed_official 441:d2c15dda23c1 713 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
mbed_official 441:d2c15dda23c1 714 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
mbed_official 441:d2c15dda23c1 715 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
mbed_official 441:d2c15dda23c1 716 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
mbed_official 441:d2c15dda23c1 717 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
mbed_official 441:d2c15dda23c1 718 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
mbed_official 441:d2c15dda23c1 719 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
mbed_official 441:d2c15dda23c1 720 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
mbed_official 441:d2c15dda23c1 721 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000)
mbed_official 441:d2c15dda23c1 722
mbed_official 441:d2c15dda23c1 723 /*!< AHB1 peripherals */
mbed_official 441:d2c15dda23c1 724 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
mbed_official 441:d2c15dda23c1 725 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
mbed_official 441:d2c15dda23c1 726 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
mbed_official 441:d2c15dda23c1 727 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
mbed_official 441:d2c15dda23c1 728 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
mbed_official 441:d2c15dda23c1 729 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
mbed_official 441:d2c15dda23c1 730 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
mbed_official 441:d2c15dda23c1 731 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
mbed_official 441:d2c15dda23c1 732 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
mbed_official 441:d2c15dda23c1 733 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
mbed_official 441:d2c15dda23c1 734 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
mbed_official 441:d2c15dda23c1 735 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
mbed_official 441:d2c15dda23c1 736 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
mbed_official 441:d2c15dda23c1 737 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
mbed_official 441:d2c15dda23c1 738 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
mbed_official 441:d2c15dda23c1 739 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
mbed_official 441:d2c15dda23c1 740 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
mbed_official 441:d2c15dda23c1 741 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
mbed_official 441:d2c15dda23c1 742 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
mbed_official 441:d2c15dda23c1 743 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
mbed_official 441:d2c15dda23c1 744 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
mbed_official 441:d2c15dda23c1 745 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
mbed_official 441:d2c15dda23c1 746 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
mbed_official 441:d2c15dda23c1 747 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
mbed_official 441:d2c15dda23c1 748 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
mbed_official 441:d2c15dda23c1 749 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
mbed_official 441:d2c15dda23c1 750 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
mbed_official 441:d2c15dda23c1 751
mbed_official 441:d2c15dda23c1 752 /* Debug MCU registers base address */
mbed_official 441:d2c15dda23c1 753 #define DBGMCU_BASE ((uint32_t )0xE0042000)
mbed_official 441:d2c15dda23c1 754
mbed_official 441:d2c15dda23c1 755 /*!< USB registers base address */
mbed_official 441:d2c15dda23c1 756 #define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
mbed_official 441:d2c15dda23c1 757
mbed_official 441:d2c15dda23c1 758 #define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
mbed_official 441:d2c15dda23c1 759 #define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
mbed_official 441:d2c15dda23c1 760 #define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
mbed_official 441:d2c15dda23c1 761 #define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
mbed_official 441:d2c15dda23c1 762 #define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
mbed_official 441:d2c15dda23c1 763 #define USB_OTG_HOST_BASE ((uint32_t )0x400)
mbed_official 441:d2c15dda23c1 764 #define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
mbed_official 441:d2c15dda23c1 765 #define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
mbed_official 441:d2c15dda23c1 766 #define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
mbed_official 441:d2c15dda23c1 767 #define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
mbed_official 441:d2c15dda23c1 768 #define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
mbed_official 441:d2c15dda23c1 769 #define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
mbed_official 441:d2c15dda23c1 770
mbed_official 441:d2c15dda23c1 771 /**
mbed_official 441:d2c15dda23c1 772 * @}
mbed_official 441:d2c15dda23c1 773 */
mbed_official 441:d2c15dda23c1 774
mbed_official 441:d2c15dda23c1 775 /** @addtogroup Peripheral_declaration
mbed_official 441:d2c15dda23c1 776 * @{
mbed_official 441:d2c15dda23c1 777 */
mbed_official 441:d2c15dda23c1 778 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
mbed_official 441:d2c15dda23c1 779 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
mbed_official 441:d2c15dda23c1 780 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
mbed_official 441:d2c15dda23c1 781 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
mbed_official 441:d2c15dda23c1 782 #define RTC ((RTC_TypeDef *) RTC_BASE)
mbed_official 441:d2c15dda23c1 783 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
mbed_official 441:d2c15dda23c1 784 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
mbed_official 441:d2c15dda23c1 785 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
mbed_official 441:d2c15dda23c1 786 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
mbed_official 441:d2c15dda23c1 787 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
mbed_official 441:d2c15dda23c1 788 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
mbed_official 441:d2c15dda23c1 789 #define USART2 ((USART_TypeDef *) USART2_BASE)
mbed_official 441:d2c15dda23c1 790 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
mbed_official 441:d2c15dda23c1 791 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
mbed_official 441:d2c15dda23c1 792 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
mbed_official 441:d2c15dda23c1 793 #define PWR ((PWR_TypeDef *) PWR_BASE)
mbed_official 441:d2c15dda23c1 794 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
mbed_official 441:d2c15dda23c1 795 #define USART1 ((USART_TypeDef *) USART1_BASE)
mbed_official 441:d2c15dda23c1 796 #define USART6 ((USART_TypeDef *) USART6_BASE)
mbed_official 441:d2c15dda23c1 797 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
mbed_official 441:d2c15dda23c1 798 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
mbed_official 441:d2c15dda23c1 799 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
mbed_official 441:d2c15dda23c1 800 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
mbed_official 441:d2c15dda23c1 801 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
mbed_official 441:d2c15dda23c1 802 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
mbed_official 441:d2c15dda23c1 803 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
mbed_official 441:d2c15dda23c1 804 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
mbed_official 441:d2c15dda23c1 805 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
mbed_official 441:d2c15dda23c1 806 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
mbed_official 441:d2c15dda23c1 807 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
mbed_official 441:d2c15dda23c1 808 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
mbed_official 441:d2c15dda23c1 809 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
mbed_official 441:d2c15dda23c1 810 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
mbed_official 441:d2c15dda23c1 811 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
mbed_official 441:d2c15dda23c1 812 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
mbed_official 441:d2c15dda23c1 813 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
mbed_official 441:d2c15dda23c1 814 #define CRC ((CRC_TypeDef *) CRC_BASE)
mbed_official 441:d2c15dda23c1 815 #define RCC ((RCC_TypeDef *) RCC_BASE)
mbed_official 441:d2c15dda23c1 816 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
mbed_official 441:d2c15dda23c1 817 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
mbed_official 441:d2c15dda23c1 818 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
mbed_official 441:d2c15dda23c1 819 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
mbed_official 441:d2c15dda23c1 820 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
mbed_official 441:d2c15dda23c1 821 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
mbed_official 441:d2c15dda23c1 822 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
mbed_official 441:d2c15dda23c1 823 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
mbed_official 441:d2c15dda23c1 824 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
mbed_official 441:d2c15dda23c1 825 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
mbed_official 441:d2c15dda23c1 826 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
mbed_official 441:d2c15dda23c1 827 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
mbed_official 441:d2c15dda23c1 828 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
mbed_official 441:d2c15dda23c1 829 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
mbed_official 441:d2c15dda23c1 830 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
mbed_official 441:d2c15dda23c1 831 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
mbed_official 441:d2c15dda23c1 832 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
mbed_official 441:d2c15dda23c1 833 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
mbed_official 441:d2c15dda23c1 834 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
mbed_official 441:d2c15dda23c1 835
mbed_official 441:d2c15dda23c1 836 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
mbed_official 441:d2c15dda23c1 837
mbed_official 441:d2c15dda23c1 838 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
mbed_official 441:d2c15dda23c1 839
mbed_official 441:d2c15dda23c1 840 /**
mbed_official 441:d2c15dda23c1 841 * @}
mbed_official 441:d2c15dda23c1 842 */
mbed_official 441:d2c15dda23c1 843
mbed_official 441:d2c15dda23c1 844 /** @addtogroup Exported_constants
mbed_official 441:d2c15dda23c1 845 * @{
mbed_official 441:d2c15dda23c1 846 */
mbed_official 441:d2c15dda23c1 847
mbed_official 441:d2c15dda23c1 848 /** @addtogroup Peripheral_Registers_Bits_Definition
mbed_official 441:d2c15dda23c1 849 * @{
mbed_official 441:d2c15dda23c1 850 */
mbed_official 441:d2c15dda23c1 851
mbed_official 441:d2c15dda23c1 852 /******************************************************************************/
mbed_official 441:d2c15dda23c1 853 /* Peripheral Registers_Bits_Definition */
mbed_official 441:d2c15dda23c1 854 /******************************************************************************/
mbed_official 441:d2c15dda23c1 855
mbed_official 441:d2c15dda23c1 856 /******************************************************************************/
mbed_official 441:d2c15dda23c1 857 /* */
mbed_official 441:d2c15dda23c1 858 /* Analog to Digital Converter */
mbed_official 441:d2c15dda23c1 859 /* */
mbed_official 441:d2c15dda23c1 860 /******************************************************************************/
mbed_official 441:d2c15dda23c1 861 /******************** Bit definition for ADC_SR register ********************/
mbed_official 441:d2c15dda23c1 862 #define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
mbed_official 441:d2c15dda23c1 863 #define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
mbed_official 441:d2c15dda23c1 864 #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
mbed_official 441:d2c15dda23c1 865 #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
mbed_official 441:d2c15dda23c1 866 #define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
mbed_official 441:d2c15dda23c1 867 #define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
mbed_official 441:d2c15dda23c1 868
mbed_official 441:d2c15dda23c1 869 /******************* Bit definition for ADC_CR1 register ********************/
mbed_official 441:d2c15dda23c1 870 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
mbed_official 441:d2c15dda23c1 871 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 872 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 873 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 874 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 875 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 876 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
mbed_official 441:d2c15dda23c1 877 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
mbed_official 441:d2c15dda23c1 878 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
mbed_official 441:d2c15dda23c1 879 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
mbed_official 441:d2c15dda23c1 880 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
mbed_official 441:d2c15dda23c1 881 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
mbed_official 441:d2c15dda23c1 882 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
mbed_official 441:d2c15dda23c1 883 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
mbed_official 441:d2c15dda23c1 884 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
mbed_official 441:d2c15dda23c1 885 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 886 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 887 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 888 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
mbed_official 441:d2c15dda23c1 889 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
mbed_official 441:d2c15dda23c1 890 #define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
mbed_official 441:d2c15dda23c1 891 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 892 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 893 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
mbed_official 441:d2c15dda23c1 894
mbed_official 441:d2c15dda23c1 895 /******************* Bit definition for ADC_CR2 register ********************/
mbed_official 441:d2c15dda23c1 896 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
mbed_official 441:d2c15dda23c1 897 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
mbed_official 441:d2c15dda23c1 898 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
mbed_official 441:d2c15dda23c1 899 #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
mbed_official 441:d2c15dda23c1 900 #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
mbed_official 441:d2c15dda23c1 901 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
mbed_official 441:d2c15dda23c1 902 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
mbed_official 441:d2c15dda23c1 903 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 904 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 905 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 906 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 907 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
mbed_official 441:d2c15dda23c1 908 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 909 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 910 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
mbed_official 441:d2c15dda23c1 911 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
mbed_official 441:d2c15dda23c1 912 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 913 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 914 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 915 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 916 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
mbed_official 441:d2c15dda23c1 917 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 918 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 919 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
mbed_official 441:d2c15dda23c1 920
mbed_official 441:d2c15dda23c1 921 /****************** Bit definition for ADC_SMPR1 register *******************/
mbed_official 441:d2c15dda23c1 922 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
mbed_official 441:d2c15dda23c1 923 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 924 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 925 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 926 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
mbed_official 441:d2c15dda23c1 927 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 928 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 929 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 930 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
mbed_official 441:d2c15dda23c1 931 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 932 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 933 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 934 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
mbed_official 441:d2c15dda23c1 935 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 936 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 937 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 938 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
mbed_official 441:d2c15dda23c1 939 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 940 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 941 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 942 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
mbed_official 441:d2c15dda23c1 943 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 944 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 945 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 946 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
mbed_official 441:d2c15dda23c1 947 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 948 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 949 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 950 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
mbed_official 441:d2c15dda23c1 951 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 952 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 953 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 954 #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
mbed_official 441:d2c15dda23c1 955 #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 956 #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 957 #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 958
mbed_official 441:d2c15dda23c1 959 /****************** Bit definition for ADC_SMPR2 register *******************/
mbed_official 441:d2c15dda23c1 960 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
mbed_official 441:d2c15dda23c1 961 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 962 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 963 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 964 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
mbed_official 441:d2c15dda23c1 965 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 966 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 967 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 968 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
mbed_official 441:d2c15dda23c1 969 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 970 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 971 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 972 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
mbed_official 441:d2c15dda23c1 973 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 974 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 975 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 976 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
mbed_official 441:d2c15dda23c1 977 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 978 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 979 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 980 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
mbed_official 441:d2c15dda23c1 981 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 982 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 983 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 984 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
mbed_official 441:d2c15dda23c1 985 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 986 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 987 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 988 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
mbed_official 441:d2c15dda23c1 989 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 990 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 991 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 992 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
mbed_official 441:d2c15dda23c1 993 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 994 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 995 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 996 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
mbed_official 441:d2c15dda23c1 997 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 998 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 999 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 1000
mbed_official 441:d2c15dda23c1 1001 /****************** Bit definition for ADC_JOFR1 register *******************/
mbed_official 441:d2c15dda23c1 1002 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
mbed_official 441:d2c15dda23c1 1003
mbed_official 441:d2c15dda23c1 1004 /****************** Bit definition for ADC_JOFR2 register *******************/
mbed_official 441:d2c15dda23c1 1005 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
mbed_official 441:d2c15dda23c1 1006
mbed_official 441:d2c15dda23c1 1007 /****************** Bit definition for ADC_JOFR3 register *******************/
mbed_official 441:d2c15dda23c1 1008 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
mbed_official 441:d2c15dda23c1 1009
mbed_official 441:d2c15dda23c1 1010 /****************** Bit definition for ADC_JOFR4 register *******************/
mbed_official 441:d2c15dda23c1 1011 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
mbed_official 441:d2c15dda23c1 1012
mbed_official 441:d2c15dda23c1 1013 /******************* Bit definition for ADC_HTR register ********************/
mbed_official 441:d2c15dda23c1 1014 #define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
mbed_official 441:d2c15dda23c1 1015
mbed_official 441:d2c15dda23c1 1016 /******************* Bit definition for ADC_LTR register ********************/
mbed_official 441:d2c15dda23c1 1017 #define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
mbed_official 441:d2c15dda23c1 1018
mbed_official 441:d2c15dda23c1 1019 /******************* Bit definition for ADC_SQR1 register *******************/
mbed_official 441:d2c15dda23c1 1020 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
mbed_official 441:d2c15dda23c1 1021 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 1022 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 1023 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 1024 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 1025 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 1026 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
mbed_official 441:d2c15dda23c1 1027 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 1028 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 1029 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 1030 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 1031 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 1032 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
mbed_official 441:d2c15dda23c1 1033 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 1034 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 1035 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 1036 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 1037 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 1038 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
mbed_official 441:d2c15dda23c1 1039 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 1040 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 1041 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 1042 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 1043 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 1044 #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
mbed_official 441:d2c15dda23c1 1045 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 1046 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 1047 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 1048 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 1049
mbed_official 441:d2c15dda23c1 1050 /******************* Bit definition for ADC_SQR2 register *******************/
mbed_official 441:d2c15dda23c1 1051 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
mbed_official 441:d2c15dda23c1 1052 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 1053 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 1054 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 1055 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 1056 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 1057 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
mbed_official 441:d2c15dda23c1 1058 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 1059 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 1060 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 1061 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 1062 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 1063 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
mbed_official 441:d2c15dda23c1 1064 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 1065 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 1066 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 1067 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 1068 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 1069 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
mbed_official 441:d2c15dda23c1 1070 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 1071 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 1072 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 1073 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 1074 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 1075 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
mbed_official 441:d2c15dda23c1 1076 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 1077 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 1078 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 1079 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 1080 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 1081 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
mbed_official 441:d2c15dda23c1 1082 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 1083 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 1084 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 1085 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 1086 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 1087
mbed_official 441:d2c15dda23c1 1088 /******************* Bit definition for ADC_SQR3 register *******************/
mbed_official 441:d2c15dda23c1 1089 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
mbed_official 441:d2c15dda23c1 1090 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 1091 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 1092 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 1093 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 1094 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 1095 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
mbed_official 441:d2c15dda23c1 1096 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 1097 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 1098 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 1099 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 1100 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 1101 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
mbed_official 441:d2c15dda23c1 1102 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 1103 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 1104 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 1105 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 1106 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 1107 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
mbed_official 441:d2c15dda23c1 1108 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 1109 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 1110 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 1111 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 1112 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 1113 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
mbed_official 441:d2c15dda23c1 1114 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 1115 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 1116 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 1117 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 1118 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 1119 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
mbed_official 441:d2c15dda23c1 1120 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 1121 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 1122 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 1123 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 1124 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 1125
mbed_official 441:d2c15dda23c1 1126 /******************* Bit definition for ADC_JSQR register *******************/
mbed_official 441:d2c15dda23c1 1127 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
mbed_official 441:d2c15dda23c1 1128 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 1129 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 1130 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 1131 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 1132 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 1133 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
mbed_official 441:d2c15dda23c1 1134 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 1135 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 1136 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 1137 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 1138 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 1139 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
mbed_official 441:d2c15dda23c1 1140 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 1141 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 1142 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 1143 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 1144 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 1145 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
mbed_official 441:d2c15dda23c1 1146 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 1147 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 1148 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 1149 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 1150 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 1151 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
mbed_official 441:d2c15dda23c1 1152 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 1153 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 1154
mbed_official 441:d2c15dda23c1 1155 /******************* Bit definition for ADC_JDR1 register *******************/
mbed_official 441:d2c15dda23c1 1156 #define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
mbed_official 441:d2c15dda23c1 1157
mbed_official 441:d2c15dda23c1 1158 /******************* Bit definition for ADC_JDR2 register *******************/
mbed_official 441:d2c15dda23c1 1159 #define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
mbed_official 441:d2c15dda23c1 1160
mbed_official 441:d2c15dda23c1 1161 /******************* Bit definition for ADC_JDR3 register *******************/
mbed_official 441:d2c15dda23c1 1162 #define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
mbed_official 441:d2c15dda23c1 1163
mbed_official 441:d2c15dda23c1 1164 /******************* Bit definition for ADC_JDR4 register *******************/
mbed_official 441:d2c15dda23c1 1165 #define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
mbed_official 441:d2c15dda23c1 1166
mbed_official 441:d2c15dda23c1 1167 /******************** Bit definition for ADC_DR register ********************/
mbed_official 441:d2c15dda23c1 1168 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
mbed_official 441:d2c15dda23c1 1169 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
mbed_official 441:d2c15dda23c1 1170
mbed_official 441:d2c15dda23c1 1171 /******************* Bit definition for ADC_CSR register ********************/
mbed_official 441:d2c15dda23c1 1172 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
mbed_official 441:d2c15dda23c1 1173 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
mbed_official 441:d2c15dda23c1 1174 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
mbed_official 441:d2c15dda23c1 1175 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
mbed_official 441:d2c15dda23c1 1176 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
mbed_official 441:d2c15dda23c1 1177 #define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
mbed_official 441:d2c15dda23c1 1178 #define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
mbed_official 441:d2c15dda23c1 1179 #define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
mbed_official 441:d2c15dda23c1 1180 #define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
mbed_official 441:d2c15dda23c1 1181 #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
mbed_official 441:d2c15dda23c1 1182 #define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
mbed_official 441:d2c15dda23c1 1183 #define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
mbed_official 441:d2c15dda23c1 1184 #define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
mbed_official 441:d2c15dda23c1 1185 #define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
mbed_official 441:d2c15dda23c1 1186 #define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
mbed_official 441:d2c15dda23c1 1187 #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
mbed_official 441:d2c15dda23c1 1188 #define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
mbed_official 441:d2c15dda23c1 1189 #define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
mbed_official 441:d2c15dda23c1 1190
mbed_official 441:d2c15dda23c1 1191 /******************* Bit definition for ADC_CCR register ********************/
mbed_official 441:d2c15dda23c1 1192 #define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
mbed_official 441:d2c15dda23c1 1193 #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 1194 #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 1195 #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 1196 #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 1197 #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 1198 #define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
mbed_official 441:d2c15dda23c1 1199 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 1200 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 1201 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 1202 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 1203 #define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
mbed_official 441:d2c15dda23c1 1204 #define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
mbed_official 441:d2c15dda23c1 1205 #define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 1206 #define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 1207 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
mbed_official 441:d2c15dda23c1 1208 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 1209 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 1210 #define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
mbed_official 441:d2c15dda23c1 1211 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
mbed_official 441:d2c15dda23c1 1212
mbed_official 441:d2c15dda23c1 1213 /******************* Bit definition for ADC_CDR register ********************/
mbed_official 441:d2c15dda23c1 1214 #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
mbed_official 441:d2c15dda23c1 1215 #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
mbed_official 441:d2c15dda23c1 1216
mbed_official 441:d2c15dda23c1 1217 /******************************************************************************/
mbed_official 441:d2c15dda23c1 1218 /* */
mbed_official 441:d2c15dda23c1 1219 /* CRC calculation unit */
mbed_official 441:d2c15dda23c1 1220 /* */
mbed_official 441:d2c15dda23c1 1221 /******************************************************************************/
mbed_official 441:d2c15dda23c1 1222 /******************* Bit definition for CRC_DR register *********************/
mbed_official 441:d2c15dda23c1 1223 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
mbed_official 441:d2c15dda23c1 1224
mbed_official 441:d2c15dda23c1 1225
mbed_official 441:d2c15dda23c1 1226 /******************* Bit definition for CRC_IDR register ********************/
mbed_official 441:d2c15dda23c1 1227 #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
mbed_official 441:d2c15dda23c1 1228
mbed_official 441:d2c15dda23c1 1229
mbed_official 441:d2c15dda23c1 1230 /******************** Bit definition for CRC_CR register ********************/
mbed_official 441:d2c15dda23c1 1231 #define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */
mbed_official 441:d2c15dda23c1 1232
mbed_official 441:d2c15dda23c1 1233 /******************************************************************************/
mbed_official 441:d2c15dda23c1 1234 /* */
mbed_official 441:d2c15dda23c1 1235 /* Debug MCU */
mbed_official 441:d2c15dda23c1 1236 /* */
mbed_official 441:d2c15dda23c1 1237 /******************************************************************************/
mbed_official 441:d2c15dda23c1 1238
mbed_official 441:d2c15dda23c1 1239 /******************************************************************************/
mbed_official 441:d2c15dda23c1 1240 /* */
mbed_official 441:d2c15dda23c1 1241 /* DMA Controller */
mbed_official 441:d2c15dda23c1 1242 /* */
mbed_official 441:d2c15dda23c1 1243 /******************************************************************************/
mbed_official 441:d2c15dda23c1 1244 /******************** Bits definition for DMA_SxCR register *****************/
mbed_official 441:d2c15dda23c1 1245 #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
mbed_official 441:d2c15dda23c1 1246 #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
mbed_official 441:d2c15dda23c1 1247 #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
mbed_official 441:d2c15dda23c1 1248 #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
mbed_official 441:d2c15dda23c1 1249 #define DMA_SxCR_MBURST ((uint32_t)0x01800000)
mbed_official 441:d2c15dda23c1 1250 #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
mbed_official 441:d2c15dda23c1 1251 #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
mbed_official 441:d2c15dda23c1 1252 #define DMA_SxCR_PBURST ((uint32_t)0x00600000)
mbed_official 441:d2c15dda23c1 1253 #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
mbed_official 441:d2c15dda23c1 1254 #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
mbed_official 441:d2c15dda23c1 1255 #define DMA_SxCR_ACK ((uint32_t)0x00100000)
mbed_official 441:d2c15dda23c1 1256 #define DMA_SxCR_CT ((uint32_t)0x00080000)
mbed_official 441:d2c15dda23c1 1257 #define DMA_SxCR_DBM ((uint32_t)0x00040000)
mbed_official 441:d2c15dda23c1 1258 #define DMA_SxCR_PL ((uint32_t)0x00030000)
mbed_official 441:d2c15dda23c1 1259 #define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
mbed_official 441:d2c15dda23c1 1260 #define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
mbed_official 441:d2c15dda23c1 1261 #define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
mbed_official 441:d2c15dda23c1 1262 #define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
mbed_official 441:d2c15dda23c1 1263 #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
mbed_official 441:d2c15dda23c1 1264 #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
mbed_official 441:d2c15dda23c1 1265 #define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
mbed_official 441:d2c15dda23c1 1266 #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
mbed_official 441:d2c15dda23c1 1267 #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
mbed_official 441:d2c15dda23c1 1268 #define DMA_SxCR_MINC ((uint32_t)0x00000400)
mbed_official 441:d2c15dda23c1 1269 #define DMA_SxCR_PINC ((uint32_t)0x00000200)
mbed_official 441:d2c15dda23c1 1270 #define DMA_SxCR_CIRC ((uint32_t)0x00000100)
mbed_official 441:d2c15dda23c1 1271 #define DMA_SxCR_DIR ((uint32_t)0x000000C0)
mbed_official 441:d2c15dda23c1 1272 #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
mbed_official 441:d2c15dda23c1 1273 #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
mbed_official 441:d2c15dda23c1 1274 #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
mbed_official 441:d2c15dda23c1 1275 #define DMA_SxCR_TCIE ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 1276 #define DMA_SxCR_HTIE ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 1277 #define DMA_SxCR_TEIE ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 1278 #define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 1279 #define DMA_SxCR_EN ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 1280
mbed_official 441:d2c15dda23c1 1281 /******************** Bits definition for DMA_SxCNDTR register **************/
mbed_official 441:d2c15dda23c1 1282 #define DMA_SxNDT ((uint32_t)0x0000FFFF)
mbed_official 441:d2c15dda23c1 1283 #define DMA_SxNDT_0 ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 1284 #define DMA_SxNDT_1 ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 1285 #define DMA_SxNDT_2 ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 1286 #define DMA_SxNDT_3 ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 1287 #define DMA_SxNDT_4 ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 1288 #define DMA_SxNDT_5 ((uint32_t)0x00000020)
mbed_official 441:d2c15dda23c1 1289 #define DMA_SxNDT_6 ((uint32_t)0x00000040)
mbed_official 441:d2c15dda23c1 1290 #define DMA_SxNDT_7 ((uint32_t)0x00000080)
mbed_official 441:d2c15dda23c1 1291 #define DMA_SxNDT_8 ((uint32_t)0x00000100)
mbed_official 441:d2c15dda23c1 1292 #define DMA_SxNDT_9 ((uint32_t)0x00000200)
mbed_official 441:d2c15dda23c1 1293 #define DMA_SxNDT_10 ((uint32_t)0x00000400)
mbed_official 441:d2c15dda23c1 1294 #define DMA_SxNDT_11 ((uint32_t)0x00000800)
mbed_official 441:d2c15dda23c1 1295 #define DMA_SxNDT_12 ((uint32_t)0x00001000)
mbed_official 441:d2c15dda23c1 1296 #define DMA_SxNDT_13 ((uint32_t)0x00002000)
mbed_official 441:d2c15dda23c1 1297 #define DMA_SxNDT_14 ((uint32_t)0x00004000)
mbed_official 441:d2c15dda23c1 1298 #define DMA_SxNDT_15 ((uint32_t)0x00008000)
mbed_official 441:d2c15dda23c1 1299
mbed_official 441:d2c15dda23c1 1300 /******************** Bits definition for DMA_SxFCR register ****************/
mbed_official 441:d2c15dda23c1 1301 #define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
mbed_official 441:d2c15dda23c1 1302 #define DMA_SxFCR_FS ((uint32_t)0x00000038)
mbed_official 441:d2c15dda23c1 1303 #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 1304 #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 1305 #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
mbed_official 441:d2c15dda23c1 1306 #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 1307 #define DMA_SxFCR_FTH ((uint32_t)0x00000003)
mbed_official 441:d2c15dda23c1 1308 #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 1309 #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 1310
mbed_official 441:d2c15dda23c1 1311 /******************** Bits definition for DMA_LISR register *****************/
mbed_official 441:d2c15dda23c1 1312 #define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
mbed_official 441:d2c15dda23c1 1313 #define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
mbed_official 441:d2c15dda23c1 1314 #define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
mbed_official 441:d2c15dda23c1 1315 #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
mbed_official 441:d2c15dda23c1 1316 #define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
mbed_official 441:d2c15dda23c1 1317 #define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
mbed_official 441:d2c15dda23c1 1318 #define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
mbed_official 441:d2c15dda23c1 1319 #define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
mbed_official 441:d2c15dda23c1 1320 #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
mbed_official 441:d2c15dda23c1 1321 #define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
mbed_official 441:d2c15dda23c1 1322 #define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
mbed_official 441:d2c15dda23c1 1323 #define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
mbed_official 441:d2c15dda23c1 1324 #define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
mbed_official 441:d2c15dda23c1 1325 #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
mbed_official 441:d2c15dda23c1 1326 #define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
mbed_official 441:d2c15dda23c1 1327 #define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
mbed_official 441:d2c15dda23c1 1328 #define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 1329 #define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 1330 #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 1331 #define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 1332
mbed_official 441:d2c15dda23c1 1333 /******************** Bits definition for DMA_HISR register *****************/
mbed_official 441:d2c15dda23c1 1334 #define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
mbed_official 441:d2c15dda23c1 1335 #define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
mbed_official 441:d2c15dda23c1 1336 #define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
mbed_official 441:d2c15dda23c1 1337 #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
mbed_official 441:d2c15dda23c1 1338 #define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
mbed_official 441:d2c15dda23c1 1339 #define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
mbed_official 441:d2c15dda23c1 1340 #define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
mbed_official 441:d2c15dda23c1 1341 #define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
mbed_official 441:d2c15dda23c1 1342 #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
mbed_official 441:d2c15dda23c1 1343 #define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
mbed_official 441:d2c15dda23c1 1344 #define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
mbed_official 441:d2c15dda23c1 1345 #define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
mbed_official 441:d2c15dda23c1 1346 #define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
mbed_official 441:d2c15dda23c1 1347 #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
mbed_official 441:d2c15dda23c1 1348 #define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
mbed_official 441:d2c15dda23c1 1349 #define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
mbed_official 441:d2c15dda23c1 1350 #define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 1351 #define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 1352 #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 1353 #define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 1354
mbed_official 441:d2c15dda23c1 1355 /******************** Bits definition for DMA_LIFCR register ****************/
mbed_official 441:d2c15dda23c1 1356 #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
mbed_official 441:d2c15dda23c1 1357 #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
mbed_official 441:d2c15dda23c1 1358 #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
mbed_official 441:d2c15dda23c1 1359 #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
mbed_official 441:d2c15dda23c1 1360 #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
mbed_official 441:d2c15dda23c1 1361 #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
mbed_official 441:d2c15dda23c1 1362 #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
mbed_official 441:d2c15dda23c1 1363 #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
mbed_official 441:d2c15dda23c1 1364 #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
mbed_official 441:d2c15dda23c1 1365 #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
mbed_official 441:d2c15dda23c1 1366 #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
mbed_official 441:d2c15dda23c1 1367 #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
mbed_official 441:d2c15dda23c1 1368 #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
mbed_official 441:d2c15dda23c1 1369 #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
mbed_official 441:d2c15dda23c1 1370 #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
mbed_official 441:d2c15dda23c1 1371 #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
mbed_official 441:d2c15dda23c1 1372 #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 1373 #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 1374 #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 1375 #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 1376
mbed_official 441:d2c15dda23c1 1377 /******************** Bits definition for DMA_HIFCR register ****************/
mbed_official 441:d2c15dda23c1 1378 #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
mbed_official 441:d2c15dda23c1 1379 #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
mbed_official 441:d2c15dda23c1 1380 #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
mbed_official 441:d2c15dda23c1 1381 #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
mbed_official 441:d2c15dda23c1 1382 #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
mbed_official 441:d2c15dda23c1 1383 #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
mbed_official 441:d2c15dda23c1 1384 #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
mbed_official 441:d2c15dda23c1 1385 #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
mbed_official 441:d2c15dda23c1 1386 #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
mbed_official 441:d2c15dda23c1 1387 #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
mbed_official 441:d2c15dda23c1 1388 #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
mbed_official 441:d2c15dda23c1 1389 #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
mbed_official 441:d2c15dda23c1 1390 #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
mbed_official 441:d2c15dda23c1 1391 #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
mbed_official 441:d2c15dda23c1 1392 #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
mbed_official 441:d2c15dda23c1 1393 #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
mbed_official 441:d2c15dda23c1 1394 #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 1395 #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 1396 #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 1397 #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 1398
mbed_official 441:d2c15dda23c1 1399
mbed_official 441:d2c15dda23c1 1400 /******************************************************************************/
mbed_official 441:d2c15dda23c1 1401 /* */
mbed_official 441:d2c15dda23c1 1402 /* External Interrupt/Event Controller */
mbed_official 441:d2c15dda23c1 1403 /* */
mbed_official 441:d2c15dda23c1 1404 /******************************************************************************/
mbed_official 441:d2c15dda23c1 1405 /******************* Bit definition for EXTI_IMR register *******************/
mbed_official 441:d2c15dda23c1 1406 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
mbed_official 441:d2c15dda23c1 1407 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
mbed_official 441:d2c15dda23c1 1408 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
mbed_official 441:d2c15dda23c1 1409 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
mbed_official 441:d2c15dda23c1 1410 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
mbed_official 441:d2c15dda23c1 1411 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
mbed_official 441:d2c15dda23c1 1412 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
mbed_official 441:d2c15dda23c1 1413 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
mbed_official 441:d2c15dda23c1 1414 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
mbed_official 441:d2c15dda23c1 1415 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
mbed_official 441:d2c15dda23c1 1416 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
mbed_official 441:d2c15dda23c1 1417 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
mbed_official 441:d2c15dda23c1 1418 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
mbed_official 441:d2c15dda23c1 1419 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
mbed_official 441:d2c15dda23c1 1420 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
mbed_official 441:d2c15dda23c1 1421 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
mbed_official 441:d2c15dda23c1 1422 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
mbed_official 441:d2c15dda23c1 1423 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
mbed_official 441:d2c15dda23c1 1424 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
mbed_official 441:d2c15dda23c1 1425 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
mbed_official 532:fe11edbda85c 1426 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
mbed_official 532:fe11edbda85c 1427 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
mbed_official 532:fe11edbda85c 1428 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
mbed_official 441:d2c15dda23c1 1429
mbed_official 441:d2c15dda23c1 1430 /******************* Bit definition for EXTI_EMR register *******************/
mbed_official 441:d2c15dda23c1 1431 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
mbed_official 441:d2c15dda23c1 1432 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
mbed_official 441:d2c15dda23c1 1433 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
mbed_official 441:d2c15dda23c1 1434 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
mbed_official 441:d2c15dda23c1 1435 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
mbed_official 441:d2c15dda23c1 1436 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
mbed_official 441:d2c15dda23c1 1437 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
mbed_official 441:d2c15dda23c1 1438 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
mbed_official 441:d2c15dda23c1 1439 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
mbed_official 441:d2c15dda23c1 1440 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
mbed_official 441:d2c15dda23c1 1441 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
mbed_official 441:d2c15dda23c1 1442 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
mbed_official 441:d2c15dda23c1 1443 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
mbed_official 441:d2c15dda23c1 1444 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
mbed_official 441:d2c15dda23c1 1445 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
mbed_official 441:d2c15dda23c1 1446 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
mbed_official 441:d2c15dda23c1 1447 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
mbed_official 441:d2c15dda23c1 1448 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
mbed_official 441:d2c15dda23c1 1449 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
mbed_official 441:d2c15dda23c1 1450 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
mbed_official 532:fe11edbda85c 1451 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
mbed_official 532:fe11edbda85c 1452 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
mbed_official 532:fe11edbda85c 1453 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
mbed_official 441:d2c15dda23c1 1454
mbed_official 441:d2c15dda23c1 1455 /****************** Bit definition for EXTI_RTSR register *******************/
mbed_official 441:d2c15dda23c1 1456 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
mbed_official 441:d2c15dda23c1 1457 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
mbed_official 441:d2c15dda23c1 1458 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
mbed_official 441:d2c15dda23c1 1459 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
mbed_official 441:d2c15dda23c1 1460 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
mbed_official 441:d2c15dda23c1 1461 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
mbed_official 441:d2c15dda23c1 1462 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
mbed_official 441:d2c15dda23c1 1463 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
mbed_official 441:d2c15dda23c1 1464 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
mbed_official 441:d2c15dda23c1 1465 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
mbed_official 441:d2c15dda23c1 1466 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
mbed_official 441:d2c15dda23c1 1467 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
mbed_official 441:d2c15dda23c1 1468 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
mbed_official 441:d2c15dda23c1 1469 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
mbed_official 441:d2c15dda23c1 1470 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
mbed_official 441:d2c15dda23c1 1471 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
mbed_official 441:d2c15dda23c1 1472 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
mbed_official 441:d2c15dda23c1 1473 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
mbed_official 441:d2c15dda23c1 1474 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
mbed_official 441:d2c15dda23c1 1475 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
mbed_official 532:fe11edbda85c 1476 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
mbed_official 532:fe11edbda85c 1477 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
mbed_official 532:fe11edbda85c 1478 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
mbed_official 441:d2c15dda23c1 1479
mbed_official 441:d2c15dda23c1 1480 /****************** Bit definition for EXTI_FTSR register *******************/
mbed_official 441:d2c15dda23c1 1481 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
mbed_official 441:d2c15dda23c1 1482 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
mbed_official 441:d2c15dda23c1 1483 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
mbed_official 441:d2c15dda23c1 1484 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
mbed_official 441:d2c15dda23c1 1485 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
mbed_official 441:d2c15dda23c1 1486 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
mbed_official 441:d2c15dda23c1 1487 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
mbed_official 441:d2c15dda23c1 1488 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
mbed_official 441:d2c15dda23c1 1489 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
mbed_official 441:d2c15dda23c1 1490 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
mbed_official 441:d2c15dda23c1 1491 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
mbed_official 441:d2c15dda23c1 1492 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
mbed_official 441:d2c15dda23c1 1493 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
mbed_official 441:d2c15dda23c1 1494 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
mbed_official 441:d2c15dda23c1 1495 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
mbed_official 441:d2c15dda23c1 1496 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
mbed_official 441:d2c15dda23c1 1497 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
mbed_official 441:d2c15dda23c1 1498 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
mbed_official 441:d2c15dda23c1 1499 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
mbed_official 441:d2c15dda23c1 1500 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
mbed_official 532:fe11edbda85c 1501 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
mbed_official 532:fe11edbda85c 1502 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
mbed_official 532:fe11edbda85c 1503 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
mbed_official 441:d2c15dda23c1 1504
mbed_official 441:d2c15dda23c1 1505 /****************** Bit definition for EXTI_SWIER register ******************/
mbed_official 441:d2c15dda23c1 1506 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
mbed_official 441:d2c15dda23c1 1507 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
mbed_official 441:d2c15dda23c1 1508 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
mbed_official 441:d2c15dda23c1 1509 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
mbed_official 441:d2c15dda23c1 1510 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
mbed_official 441:d2c15dda23c1 1511 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
mbed_official 441:d2c15dda23c1 1512 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
mbed_official 441:d2c15dda23c1 1513 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
mbed_official 441:d2c15dda23c1 1514 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
mbed_official 441:d2c15dda23c1 1515 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
mbed_official 441:d2c15dda23c1 1516 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
mbed_official 441:d2c15dda23c1 1517 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
mbed_official 441:d2c15dda23c1 1518 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
mbed_official 441:d2c15dda23c1 1519 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
mbed_official 441:d2c15dda23c1 1520 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
mbed_official 441:d2c15dda23c1 1521 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
mbed_official 441:d2c15dda23c1 1522 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
mbed_official 441:d2c15dda23c1 1523 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
mbed_official 441:d2c15dda23c1 1524 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
mbed_official 441:d2c15dda23c1 1525 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
mbed_official 532:fe11edbda85c 1526 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
mbed_official 532:fe11edbda85c 1527 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
mbed_official 532:fe11edbda85c 1528 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
mbed_official 441:d2c15dda23c1 1529
mbed_official 441:d2c15dda23c1 1530 /******************* Bit definition for EXTI_PR register ********************/
mbed_official 441:d2c15dda23c1 1531 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
mbed_official 441:d2c15dda23c1 1532 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
mbed_official 441:d2c15dda23c1 1533 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
mbed_official 441:d2c15dda23c1 1534 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
mbed_official 441:d2c15dda23c1 1535 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
mbed_official 441:d2c15dda23c1 1536 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
mbed_official 441:d2c15dda23c1 1537 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
mbed_official 441:d2c15dda23c1 1538 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
mbed_official 441:d2c15dda23c1 1539 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
mbed_official 441:d2c15dda23c1 1540 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
mbed_official 441:d2c15dda23c1 1541 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
mbed_official 441:d2c15dda23c1 1542 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
mbed_official 441:d2c15dda23c1 1543 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
mbed_official 441:d2c15dda23c1 1544 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
mbed_official 441:d2c15dda23c1 1545 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
mbed_official 441:d2c15dda23c1 1546 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
mbed_official 441:d2c15dda23c1 1547 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
mbed_official 441:d2c15dda23c1 1548 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
mbed_official 441:d2c15dda23c1 1549 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
mbed_official 441:d2c15dda23c1 1550 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
mbed_official 532:fe11edbda85c 1551 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
mbed_official 532:fe11edbda85c 1552 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
mbed_official 532:fe11edbda85c 1553 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
mbed_official 441:d2c15dda23c1 1554
mbed_official 441:d2c15dda23c1 1555 /******************************************************************************/
mbed_official 441:d2c15dda23c1 1556 /* */
mbed_official 441:d2c15dda23c1 1557 /* FLASH */
mbed_official 441:d2c15dda23c1 1558 /* */
mbed_official 441:d2c15dda23c1 1559 /******************************************************************************/
mbed_official 441:d2c15dda23c1 1560 /******************* Bits definition for FLASH_ACR register *****************/
mbed_official 441:d2c15dda23c1 1561 #define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
mbed_official 441:d2c15dda23c1 1562 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
mbed_official 441:d2c15dda23c1 1563 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 1564 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 1565 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
mbed_official 441:d2c15dda23c1 1566 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 1567 #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
mbed_official 441:d2c15dda23c1 1568 #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
mbed_official 441:d2c15dda23c1 1569 #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
mbed_official 441:d2c15dda23c1 1570
mbed_official 441:d2c15dda23c1 1571 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
mbed_official 441:d2c15dda23c1 1572 #define FLASH_ACR_ICEN ((uint32_t)0x00000200)
mbed_official 441:d2c15dda23c1 1573 #define FLASH_ACR_DCEN ((uint32_t)0x00000400)
mbed_official 441:d2c15dda23c1 1574 #define FLASH_ACR_ICRST ((uint32_t)0x00000800)
mbed_official 441:d2c15dda23c1 1575 #define FLASH_ACR_DCRST ((uint32_t)0x00001000)
mbed_official 441:d2c15dda23c1 1576 #define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
mbed_official 441:d2c15dda23c1 1577 #define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
mbed_official 441:d2c15dda23c1 1578
mbed_official 441:d2c15dda23c1 1579 /******************* Bits definition for FLASH_SR register ******************/
mbed_official 441:d2c15dda23c1 1580 #define FLASH_SR_EOP ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 1581 #define FLASH_SR_SOP ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 1582 #define FLASH_SR_WRPERR ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 1583 #define FLASH_SR_PGAERR ((uint32_t)0x00000020)
mbed_official 441:d2c15dda23c1 1584 #define FLASH_SR_PGPERR ((uint32_t)0x00000040)
mbed_official 441:d2c15dda23c1 1585 #define FLASH_SR_PGSERR ((uint32_t)0x00000080)
mbed_official 441:d2c15dda23c1 1586 #define FLASH_SR_BSY ((uint32_t)0x00010000)
mbed_official 441:d2c15dda23c1 1587
mbed_official 441:d2c15dda23c1 1588 /******************* Bits definition for FLASH_CR register ******************/
mbed_official 441:d2c15dda23c1 1589 #define FLASH_CR_PG ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 1590 #define FLASH_CR_SER ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 1591 #define FLASH_CR_MER ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 1592 #define FLASH_CR_SNB ((uint32_t)0x000000F8)
mbed_official 441:d2c15dda23c1 1593 #define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 1594 #define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 1595 #define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
mbed_official 441:d2c15dda23c1 1596 #define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
mbed_official 441:d2c15dda23c1 1597 #define FLASH_CR_SNB_4 ((uint32_t)0x00000080)
mbed_official 441:d2c15dda23c1 1598 #define FLASH_CR_PSIZE ((uint32_t)0x00000300)
mbed_official 441:d2c15dda23c1 1599 #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
mbed_official 441:d2c15dda23c1 1600 #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
mbed_official 441:d2c15dda23c1 1601 #define FLASH_CR_STRT ((uint32_t)0x00010000)
mbed_official 441:d2c15dda23c1 1602 #define FLASH_CR_EOPIE ((uint32_t)0x01000000)
mbed_official 441:d2c15dda23c1 1603 #define FLASH_CR_LOCK ((uint32_t)0x80000000)
mbed_official 441:d2c15dda23c1 1604
mbed_official 441:d2c15dda23c1 1605 /******************* Bits definition for FLASH_OPTCR register ***************/
mbed_official 441:d2c15dda23c1 1606 #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 1607 #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 1608 #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 1609 #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 1610 #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
mbed_official 441:d2c15dda23c1 1611
mbed_official 441:d2c15dda23c1 1612 #define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
mbed_official 441:d2c15dda23c1 1613 #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
mbed_official 441:d2c15dda23c1 1614 #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
mbed_official 441:d2c15dda23c1 1615 #define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
mbed_official 441:d2c15dda23c1 1616 #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
mbed_official 441:d2c15dda23c1 1617 #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
mbed_official 441:d2c15dda23c1 1618 #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
mbed_official 441:d2c15dda23c1 1619 #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
mbed_official 441:d2c15dda23c1 1620 #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
mbed_official 441:d2c15dda23c1 1621 #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
mbed_official 441:d2c15dda23c1 1622 #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
mbed_official 441:d2c15dda23c1 1623 #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
mbed_official 441:d2c15dda23c1 1624 #define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
mbed_official 441:d2c15dda23c1 1625 #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
mbed_official 441:d2c15dda23c1 1626 #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
mbed_official 441:d2c15dda23c1 1627 #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
mbed_official 441:d2c15dda23c1 1628 #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
mbed_official 441:d2c15dda23c1 1629 #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
mbed_official 441:d2c15dda23c1 1630 #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
mbed_official 441:d2c15dda23c1 1631 #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
mbed_official 441:d2c15dda23c1 1632 #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
mbed_official 441:d2c15dda23c1 1633 #define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
mbed_official 441:d2c15dda23c1 1634 #define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
mbed_official 441:d2c15dda23c1 1635 #define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
mbed_official 441:d2c15dda23c1 1636 #define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
mbed_official 441:d2c15dda23c1 1637
mbed_official 441:d2c15dda23c1 1638 /****************** Bits definition for FLASH_OPTCR1 register ***************/
mbed_official 441:d2c15dda23c1 1639 #define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
mbed_official 441:d2c15dda23c1 1640 #define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
mbed_official 441:d2c15dda23c1 1641 #define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
mbed_official 441:d2c15dda23c1 1642 #define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
mbed_official 441:d2c15dda23c1 1643 #define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
mbed_official 441:d2c15dda23c1 1644 #define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
mbed_official 441:d2c15dda23c1 1645 #define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
mbed_official 441:d2c15dda23c1 1646 #define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
mbed_official 441:d2c15dda23c1 1647 #define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
mbed_official 441:d2c15dda23c1 1648 #define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
mbed_official 441:d2c15dda23c1 1649 #define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
mbed_official 441:d2c15dda23c1 1650 #define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
mbed_official 441:d2c15dda23c1 1651 #define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
mbed_official 441:d2c15dda23c1 1652
mbed_official 441:d2c15dda23c1 1653 /******************************************************************************/
mbed_official 441:d2c15dda23c1 1654 /* */
mbed_official 441:d2c15dda23c1 1655 /* General Purpose I/O */
mbed_official 441:d2c15dda23c1 1656 /* */
mbed_official 441:d2c15dda23c1 1657 /******************************************************************************/
mbed_official 441:d2c15dda23c1 1658 /****************** Bits definition for GPIO_MODER register *****************/
mbed_official 441:d2c15dda23c1 1659 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
mbed_official 441:d2c15dda23c1 1660 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 1661 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 1662
mbed_official 441:d2c15dda23c1 1663 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
mbed_official 441:d2c15dda23c1 1664 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 1665 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 1666
mbed_official 441:d2c15dda23c1 1667 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
mbed_official 441:d2c15dda23c1 1668 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 1669 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
mbed_official 441:d2c15dda23c1 1670
mbed_official 441:d2c15dda23c1 1671 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
mbed_official 441:d2c15dda23c1 1672 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
mbed_official 441:d2c15dda23c1 1673 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
mbed_official 441:d2c15dda23c1 1674
mbed_official 441:d2c15dda23c1 1675 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
mbed_official 441:d2c15dda23c1 1676 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
mbed_official 441:d2c15dda23c1 1677 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
mbed_official 441:d2c15dda23c1 1678
mbed_official 441:d2c15dda23c1 1679 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
mbed_official 441:d2c15dda23c1 1680 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
mbed_official 441:d2c15dda23c1 1681 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
mbed_official 441:d2c15dda23c1 1682
mbed_official 441:d2c15dda23c1 1683 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
mbed_official 441:d2c15dda23c1 1684 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
mbed_official 441:d2c15dda23c1 1685 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
mbed_official 441:d2c15dda23c1 1686
mbed_official 441:d2c15dda23c1 1687 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
mbed_official 441:d2c15dda23c1 1688 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
mbed_official 441:d2c15dda23c1 1689 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
mbed_official 441:d2c15dda23c1 1690
mbed_official 441:d2c15dda23c1 1691 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
mbed_official 441:d2c15dda23c1 1692 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
mbed_official 441:d2c15dda23c1 1693 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
mbed_official 441:d2c15dda23c1 1694
mbed_official 441:d2c15dda23c1 1695 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
mbed_official 441:d2c15dda23c1 1696 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
mbed_official 441:d2c15dda23c1 1697 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
mbed_official 441:d2c15dda23c1 1698
mbed_official 441:d2c15dda23c1 1699 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
mbed_official 441:d2c15dda23c1 1700 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
mbed_official 441:d2c15dda23c1 1701 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
mbed_official 441:d2c15dda23c1 1702
mbed_official 441:d2c15dda23c1 1703 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
mbed_official 441:d2c15dda23c1 1704 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
mbed_official 441:d2c15dda23c1 1705 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
mbed_official 441:d2c15dda23c1 1706
mbed_official 441:d2c15dda23c1 1707 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
mbed_official 441:d2c15dda23c1 1708 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
mbed_official 441:d2c15dda23c1 1709 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
mbed_official 441:d2c15dda23c1 1710
mbed_official 441:d2c15dda23c1 1711 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
mbed_official 441:d2c15dda23c1 1712 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
mbed_official 441:d2c15dda23c1 1713 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
mbed_official 441:d2c15dda23c1 1714
mbed_official 441:d2c15dda23c1 1715 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
mbed_official 441:d2c15dda23c1 1716 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
mbed_official 441:d2c15dda23c1 1717 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
mbed_official 441:d2c15dda23c1 1718
mbed_official 441:d2c15dda23c1 1719 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
mbed_official 441:d2c15dda23c1 1720 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
mbed_official 441:d2c15dda23c1 1721 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
mbed_official 441:d2c15dda23c1 1722
mbed_official 441:d2c15dda23c1 1723 /****************** Bits definition for GPIO_OTYPER register ****************/
mbed_official 441:d2c15dda23c1 1724 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 1725 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 1726 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 1727 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 1728 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 1729 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
mbed_official 441:d2c15dda23c1 1730 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
mbed_official 441:d2c15dda23c1 1731 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
mbed_official 441:d2c15dda23c1 1732 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
mbed_official 441:d2c15dda23c1 1733 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
mbed_official 441:d2c15dda23c1 1734 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
mbed_official 441:d2c15dda23c1 1735 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
mbed_official 441:d2c15dda23c1 1736 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
mbed_official 441:d2c15dda23c1 1737 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
mbed_official 441:d2c15dda23c1 1738 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
mbed_official 441:d2c15dda23c1 1739 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
mbed_official 441:d2c15dda23c1 1740
mbed_official 441:d2c15dda23c1 1741 /****************** Bits definition for GPIO_OSPEEDR register ***************/
mbed_official 441:d2c15dda23c1 1742 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
mbed_official 441:d2c15dda23c1 1743 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 1744 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 1745
mbed_official 441:d2c15dda23c1 1746 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
mbed_official 441:d2c15dda23c1 1747 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 1748 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 1749
mbed_official 441:d2c15dda23c1 1750 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
mbed_official 441:d2c15dda23c1 1751 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 1752 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
mbed_official 441:d2c15dda23c1 1753
mbed_official 441:d2c15dda23c1 1754 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
mbed_official 441:d2c15dda23c1 1755 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
mbed_official 441:d2c15dda23c1 1756 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
mbed_official 441:d2c15dda23c1 1757
mbed_official 441:d2c15dda23c1 1758 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
mbed_official 441:d2c15dda23c1 1759 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
mbed_official 441:d2c15dda23c1 1760 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
mbed_official 441:d2c15dda23c1 1761
mbed_official 441:d2c15dda23c1 1762 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
mbed_official 441:d2c15dda23c1 1763 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
mbed_official 441:d2c15dda23c1 1764 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
mbed_official 441:d2c15dda23c1 1765
mbed_official 441:d2c15dda23c1 1766 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
mbed_official 441:d2c15dda23c1 1767 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
mbed_official 441:d2c15dda23c1 1768 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
mbed_official 441:d2c15dda23c1 1769
mbed_official 441:d2c15dda23c1 1770 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
mbed_official 441:d2c15dda23c1 1771 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
mbed_official 441:d2c15dda23c1 1772 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
mbed_official 441:d2c15dda23c1 1773
mbed_official 441:d2c15dda23c1 1774 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
mbed_official 441:d2c15dda23c1 1775 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
mbed_official 441:d2c15dda23c1 1776 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
mbed_official 441:d2c15dda23c1 1777
mbed_official 441:d2c15dda23c1 1778 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
mbed_official 441:d2c15dda23c1 1779 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
mbed_official 441:d2c15dda23c1 1780 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
mbed_official 441:d2c15dda23c1 1781
mbed_official 441:d2c15dda23c1 1782 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
mbed_official 441:d2c15dda23c1 1783 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
mbed_official 441:d2c15dda23c1 1784 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
mbed_official 441:d2c15dda23c1 1785
mbed_official 441:d2c15dda23c1 1786 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
mbed_official 441:d2c15dda23c1 1787 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
mbed_official 441:d2c15dda23c1 1788 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
mbed_official 441:d2c15dda23c1 1789
mbed_official 441:d2c15dda23c1 1790 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
mbed_official 441:d2c15dda23c1 1791 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
mbed_official 441:d2c15dda23c1 1792 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
mbed_official 441:d2c15dda23c1 1793
mbed_official 441:d2c15dda23c1 1794 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
mbed_official 441:d2c15dda23c1 1795 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
mbed_official 441:d2c15dda23c1 1796 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
mbed_official 441:d2c15dda23c1 1797
mbed_official 441:d2c15dda23c1 1798 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
mbed_official 441:d2c15dda23c1 1799 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
mbed_official 441:d2c15dda23c1 1800 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
mbed_official 441:d2c15dda23c1 1801
mbed_official 441:d2c15dda23c1 1802 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
mbed_official 441:d2c15dda23c1 1803 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
mbed_official 441:d2c15dda23c1 1804 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
mbed_official 441:d2c15dda23c1 1805
mbed_official 441:d2c15dda23c1 1806 /****************** Bits definition for GPIO_PUPDR register *****************/
mbed_official 441:d2c15dda23c1 1807 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
mbed_official 441:d2c15dda23c1 1808 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 1809 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 1810
mbed_official 441:d2c15dda23c1 1811 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
mbed_official 441:d2c15dda23c1 1812 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 1813 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 1814
mbed_official 441:d2c15dda23c1 1815 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
mbed_official 441:d2c15dda23c1 1816 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 1817 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
mbed_official 441:d2c15dda23c1 1818
mbed_official 441:d2c15dda23c1 1819 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
mbed_official 441:d2c15dda23c1 1820 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
mbed_official 441:d2c15dda23c1 1821 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
mbed_official 441:d2c15dda23c1 1822
mbed_official 441:d2c15dda23c1 1823 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
mbed_official 441:d2c15dda23c1 1824 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
mbed_official 441:d2c15dda23c1 1825 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
mbed_official 441:d2c15dda23c1 1826
mbed_official 441:d2c15dda23c1 1827 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
mbed_official 441:d2c15dda23c1 1828 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
mbed_official 441:d2c15dda23c1 1829 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
mbed_official 441:d2c15dda23c1 1830
mbed_official 441:d2c15dda23c1 1831 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
mbed_official 441:d2c15dda23c1 1832 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
mbed_official 441:d2c15dda23c1 1833 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
mbed_official 441:d2c15dda23c1 1834
mbed_official 441:d2c15dda23c1 1835 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
mbed_official 441:d2c15dda23c1 1836 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
mbed_official 441:d2c15dda23c1 1837 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
mbed_official 441:d2c15dda23c1 1838
mbed_official 441:d2c15dda23c1 1839 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
mbed_official 441:d2c15dda23c1 1840 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
mbed_official 441:d2c15dda23c1 1841 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
mbed_official 441:d2c15dda23c1 1842
mbed_official 441:d2c15dda23c1 1843 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
mbed_official 441:d2c15dda23c1 1844 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
mbed_official 441:d2c15dda23c1 1845 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
mbed_official 441:d2c15dda23c1 1846
mbed_official 441:d2c15dda23c1 1847 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
mbed_official 441:d2c15dda23c1 1848 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
mbed_official 441:d2c15dda23c1 1849 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
mbed_official 441:d2c15dda23c1 1850
mbed_official 441:d2c15dda23c1 1851 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
mbed_official 441:d2c15dda23c1 1852 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
mbed_official 441:d2c15dda23c1 1853 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
mbed_official 441:d2c15dda23c1 1854
mbed_official 441:d2c15dda23c1 1855 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
mbed_official 441:d2c15dda23c1 1856 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
mbed_official 441:d2c15dda23c1 1857 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
mbed_official 441:d2c15dda23c1 1858
mbed_official 441:d2c15dda23c1 1859 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
mbed_official 441:d2c15dda23c1 1860 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
mbed_official 441:d2c15dda23c1 1861 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
mbed_official 441:d2c15dda23c1 1862
mbed_official 441:d2c15dda23c1 1863 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
mbed_official 441:d2c15dda23c1 1864 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
mbed_official 441:d2c15dda23c1 1865 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
mbed_official 441:d2c15dda23c1 1866
mbed_official 441:d2c15dda23c1 1867 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
mbed_official 441:d2c15dda23c1 1868 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
mbed_official 441:d2c15dda23c1 1869 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
mbed_official 441:d2c15dda23c1 1870
mbed_official 441:d2c15dda23c1 1871 /****************** Bits definition for GPIO_IDR register *******************/
mbed_official 441:d2c15dda23c1 1872 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 1873 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 1874 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 1875 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 1876 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 1877 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
mbed_official 441:d2c15dda23c1 1878 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
mbed_official 441:d2c15dda23c1 1879 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
mbed_official 441:d2c15dda23c1 1880 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
mbed_official 441:d2c15dda23c1 1881 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
mbed_official 441:d2c15dda23c1 1882 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
mbed_official 441:d2c15dda23c1 1883 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
mbed_official 441:d2c15dda23c1 1884 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
mbed_official 441:d2c15dda23c1 1885 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
mbed_official 441:d2c15dda23c1 1886 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
mbed_official 441:d2c15dda23c1 1887 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
mbed_official 441:d2c15dda23c1 1888 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
mbed_official 441:d2c15dda23c1 1889 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
mbed_official 441:d2c15dda23c1 1890 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
mbed_official 441:d2c15dda23c1 1891 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
mbed_official 441:d2c15dda23c1 1892 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
mbed_official 441:d2c15dda23c1 1893 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
mbed_official 441:d2c15dda23c1 1894 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
mbed_official 441:d2c15dda23c1 1895 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
mbed_official 441:d2c15dda23c1 1896 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
mbed_official 441:d2c15dda23c1 1897 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
mbed_official 441:d2c15dda23c1 1898 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
mbed_official 441:d2c15dda23c1 1899 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
mbed_official 441:d2c15dda23c1 1900 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
mbed_official 441:d2c15dda23c1 1901 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
mbed_official 441:d2c15dda23c1 1902 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
mbed_official 441:d2c15dda23c1 1903 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
mbed_official 441:d2c15dda23c1 1904 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
mbed_official 441:d2c15dda23c1 1905
mbed_official 441:d2c15dda23c1 1906 /****************** Bits definition for GPIO_ODR register *******************/
mbed_official 441:d2c15dda23c1 1907 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 1908 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 1909 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 1910 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 1911 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 1912 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
mbed_official 441:d2c15dda23c1 1913 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
mbed_official 441:d2c15dda23c1 1914 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
mbed_official 441:d2c15dda23c1 1915 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
mbed_official 441:d2c15dda23c1 1916 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
mbed_official 441:d2c15dda23c1 1917 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
mbed_official 441:d2c15dda23c1 1918 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
mbed_official 441:d2c15dda23c1 1919 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
mbed_official 441:d2c15dda23c1 1920 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
mbed_official 441:d2c15dda23c1 1921 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
mbed_official 441:d2c15dda23c1 1922 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
mbed_official 441:d2c15dda23c1 1923 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
mbed_official 441:d2c15dda23c1 1924 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
mbed_official 441:d2c15dda23c1 1925 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
mbed_official 441:d2c15dda23c1 1926 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
mbed_official 441:d2c15dda23c1 1927 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
mbed_official 441:d2c15dda23c1 1928 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
mbed_official 441:d2c15dda23c1 1929 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
mbed_official 441:d2c15dda23c1 1930 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
mbed_official 441:d2c15dda23c1 1931 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
mbed_official 441:d2c15dda23c1 1932 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
mbed_official 441:d2c15dda23c1 1933 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
mbed_official 441:d2c15dda23c1 1934 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
mbed_official 441:d2c15dda23c1 1935 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
mbed_official 441:d2c15dda23c1 1936 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
mbed_official 441:d2c15dda23c1 1937 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
mbed_official 441:d2c15dda23c1 1938 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
mbed_official 441:d2c15dda23c1 1939 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
mbed_official 441:d2c15dda23c1 1940
mbed_official 441:d2c15dda23c1 1941 /****************** Bits definition for GPIO_BSRR register ******************/
mbed_official 441:d2c15dda23c1 1942 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 1943 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 1944 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 1945 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 1946 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 1947 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
mbed_official 441:d2c15dda23c1 1948 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
mbed_official 441:d2c15dda23c1 1949 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
mbed_official 441:d2c15dda23c1 1950 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
mbed_official 441:d2c15dda23c1 1951 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
mbed_official 441:d2c15dda23c1 1952 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
mbed_official 441:d2c15dda23c1 1953 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
mbed_official 441:d2c15dda23c1 1954 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
mbed_official 441:d2c15dda23c1 1955 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
mbed_official 441:d2c15dda23c1 1956 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
mbed_official 441:d2c15dda23c1 1957 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
mbed_official 441:d2c15dda23c1 1958 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
mbed_official 441:d2c15dda23c1 1959 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
mbed_official 441:d2c15dda23c1 1960 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
mbed_official 441:d2c15dda23c1 1961 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
mbed_official 441:d2c15dda23c1 1962 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
mbed_official 441:d2c15dda23c1 1963 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
mbed_official 441:d2c15dda23c1 1964 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
mbed_official 441:d2c15dda23c1 1965 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
mbed_official 441:d2c15dda23c1 1966 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
mbed_official 441:d2c15dda23c1 1967 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
mbed_official 441:d2c15dda23c1 1968 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
mbed_official 441:d2c15dda23c1 1969 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
mbed_official 441:d2c15dda23c1 1970 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
mbed_official 441:d2c15dda23c1 1971 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
mbed_official 441:d2c15dda23c1 1972 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
mbed_official 441:d2c15dda23c1 1973 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
mbed_official 441:d2c15dda23c1 1974
mbed_official 441:d2c15dda23c1 1975 /****************** Bit definition for GPIO_LCKR register *********************/
mbed_official 441:d2c15dda23c1 1976 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 1977 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 1978 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 1979 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 1980 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 1981 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
mbed_official 441:d2c15dda23c1 1982 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
mbed_official 441:d2c15dda23c1 1983 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
mbed_official 441:d2c15dda23c1 1984 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
mbed_official 441:d2c15dda23c1 1985 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
mbed_official 441:d2c15dda23c1 1986 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
mbed_official 441:d2c15dda23c1 1987 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
mbed_official 441:d2c15dda23c1 1988 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
mbed_official 441:d2c15dda23c1 1989 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
mbed_official 441:d2c15dda23c1 1990 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
mbed_official 441:d2c15dda23c1 1991 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
mbed_official 441:d2c15dda23c1 1992 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
mbed_official 441:d2c15dda23c1 1993
mbed_official 441:d2c15dda23c1 1994 /******************************************************************************/
mbed_official 441:d2c15dda23c1 1995 /* */
mbed_official 441:d2c15dda23c1 1996 /* Inter-integrated Circuit Interface */
mbed_official 441:d2c15dda23c1 1997 /* */
mbed_official 441:d2c15dda23c1 1998 /******************************************************************************/
mbed_official 441:d2c15dda23c1 1999 /******************* Bit definition for I2C_CR1 register ********************/
mbed_official 441:d2c15dda23c1 2000 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */
mbed_official 441:d2c15dda23c1 2001 #define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */
mbed_official 441:d2c15dda23c1 2002 #define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */
mbed_official 441:d2c15dda23c1 2003 #define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */
mbed_official 441:d2c15dda23c1 2004 #define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */
mbed_official 441:d2c15dda23c1 2005 #define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */
mbed_official 441:d2c15dda23c1 2006 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */
mbed_official 441:d2c15dda23c1 2007 #define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */
mbed_official 441:d2c15dda23c1 2008 #define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */
mbed_official 441:d2c15dda23c1 2009 #define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */
mbed_official 441:d2c15dda23c1 2010 #define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */
mbed_official 441:d2c15dda23c1 2011 #define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */
mbed_official 441:d2c15dda23c1 2012 #define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */
mbed_official 441:d2c15dda23c1 2013 #define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */
mbed_official 441:d2c15dda23c1 2014
mbed_official 441:d2c15dda23c1 2015 /******************* Bit definition for I2C_CR2 register ********************/
mbed_official 441:d2c15dda23c1 2016 #define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
mbed_official 441:d2c15dda23c1 2017 #define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 2018 #define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 2019 #define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 2020 #define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 2021 #define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 2022 #define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 441:d2c15dda23c1 2023
mbed_official 441:d2c15dda23c1 2024 #define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */
mbed_official 441:d2c15dda23c1 2025 #define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */
mbed_official 441:d2c15dda23c1 2026 #define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */
mbed_official 441:d2c15dda23c1 2027 #define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */
mbed_official 441:d2c15dda23c1 2028 #define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */
mbed_official 441:d2c15dda23c1 2029
mbed_official 441:d2c15dda23c1 2030 /******************* Bit definition for I2C_OAR1 register *******************/
mbed_official 441:d2c15dda23c1 2031 #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */
mbed_official 441:d2c15dda23c1 2032 #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */
mbed_official 441:d2c15dda23c1 2033
mbed_official 441:d2c15dda23c1 2034 #define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 2035 #define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 2036 #define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 2037 #define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 2038 #define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 2039 #define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 441:d2c15dda23c1 2040 #define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 441:d2c15dda23c1 2041 #define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 441:d2c15dda23c1 2042 #define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */
mbed_official 441:d2c15dda23c1 2043 #define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */
mbed_official 441:d2c15dda23c1 2044
mbed_official 441:d2c15dda23c1 2045 #define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */
mbed_official 441:d2c15dda23c1 2046
mbed_official 441:d2c15dda23c1 2047 /******************* Bit definition for I2C_OAR2 register *******************/
mbed_official 441:d2c15dda23c1 2048 #define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */
mbed_official 441:d2c15dda23c1 2049 #define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */
mbed_official 441:d2c15dda23c1 2050
mbed_official 441:d2c15dda23c1 2051 /******************** Bit definition for I2C_DR register ********************/
mbed_official 441:d2c15dda23c1 2052 #define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */
mbed_official 441:d2c15dda23c1 2053
mbed_official 441:d2c15dda23c1 2054 /******************* Bit definition for I2C_SR1 register ********************/
mbed_official 441:d2c15dda23c1 2055 #define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */
mbed_official 441:d2c15dda23c1 2056 #define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */
mbed_official 441:d2c15dda23c1 2057 #define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */
mbed_official 441:d2c15dda23c1 2058 #define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */
mbed_official 441:d2c15dda23c1 2059 #define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */
mbed_official 441:d2c15dda23c1 2060 #define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */
mbed_official 441:d2c15dda23c1 2061 #define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */
mbed_official 441:d2c15dda23c1 2062 #define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */
mbed_official 441:d2c15dda23c1 2063 #define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */
mbed_official 441:d2c15dda23c1 2064 #define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */
mbed_official 441:d2c15dda23c1 2065 #define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */
mbed_official 441:d2c15dda23c1 2066 #define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */
mbed_official 441:d2c15dda23c1 2067 #define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */
mbed_official 441:d2c15dda23c1 2068 #define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */
mbed_official 441:d2c15dda23c1 2069
mbed_official 441:d2c15dda23c1 2070 /******************* Bit definition for I2C_SR2 register ********************/
mbed_official 441:d2c15dda23c1 2071 #define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */
mbed_official 441:d2c15dda23c1 2072 #define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */
mbed_official 441:d2c15dda23c1 2073 #define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */
mbed_official 441:d2c15dda23c1 2074 #define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */
mbed_official 441:d2c15dda23c1 2075 #define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */
mbed_official 441:d2c15dda23c1 2076 #define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */
mbed_official 441:d2c15dda23c1 2077 #define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */
mbed_official 441:d2c15dda23c1 2078 #define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */
mbed_official 441:d2c15dda23c1 2079
mbed_official 441:d2c15dda23c1 2080 /******************* Bit definition for I2C_CCR register ********************/
mbed_official 441:d2c15dda23c1 2081 #define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
mbed_official 441:d2c15dda23c1 2082 #define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */
mbed_official 441:d2c15dda23c1 2083 #define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */
mbed_official 441:d2c15dda23c1 2084
mbed_official 441:d2c15dda23c1 2085 /****************** Bit definition for I2C_TRISE register *******************/
mbed_official 441:d2c15dda23c1 2086 #define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
mbed_official 441:d2c15dda23c1 2087
mbed_official 441:d2c15dda23c1 2088 /****************** Bit definition for I2C_FLTR register *******************/
mbed_official 441:d2c15dda23c1 2089 #define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */
mbed_official 441:d2c15dda23c1 2090 #define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */
mbed_official 441:d2c15dda23c1 2091
mbed_official 441:d2c15dda23c1 2092 /******************************************************************************/
mbed_official 441:d2c15dda23c1 2093 /* */
mbed_official 441:d2c15dda23c1 2094 /* Independent WATCHDOG */
mbed_official 441:d2c15dda23c1 2095 /* */
mbed_official 441:d2c15dda23c1 2096 /******************************************************************************/
mbed_official 441:d2c15dda23c1 2097 /******************* Bit definition for IWDG_KR register ********************/
mbed_official 441:d2c15dda23c1 2098 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
mbed_official 441:d2c15dda23c1 2099
mbed_official 441:d2c15dda23c1 2100 /******************* Bit definition for IWDG_PR register ********************/
mbed_official 441:d2c15dda23c1 2101 #define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
mbed_official 441:d2c15dda23c1 2102 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 2103 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 2104 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 2105
mbed_official 441:d2c15dda23c1 2106 /******************* Bit definition for IWDG_RLR register *******************/
mbed_official 441:d2c15dda23c1 2107 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
mbed_official 441:d2c15dda23c1 2108
mbed_official 441:d2c15dda23c1 2109 /******************* Bit definition for IWDG_SR register ********************/
mbed_official 441:d2c15dda23c1 2110 #define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */
mbed_official 441:d2c15dda23c1 2111 #define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */
mbed_official 441:d2c15dda23c1 2112
mbed_official 441:d2c15dda23c1 2113
mbed_official 441:d2c15dda23c1 2114 /******************************************************************************/
mbed_official 441:d2c15dda23c1 2115 /* */
mbed_official 441:d2c15dda23c1 2116 /* Power Control */
mbed_official 441:d2c15dda23c1 2117 /* */
mbed_official 441:d2c15dda23c1 2118 /******************************************************************************/
mbed_official 441:d2c15dda23c1 2119 /******************** Bit definition for PWR_CR register ********************/
mbed_official 441:d2c15dda23c1 2120 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
mbed_official 441:d2c15dda23c1 2121 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
mbed_official 441:d2c15dda23c1 2122 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
mbed_official 441:d2c15dda23c1 2123 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
mbed_official 441:d2c15dda23c1 2124 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
mbed_official 441:d2c15dda23c1 2125
mbed_official 441:d2c15dda23c1 2126 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
mbed_official 441:d2c15dda23c1 2127 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 441:d2c15dda23c1 2128 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 441:d2c15dda23c1 2129 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
mbed_official 441:d2c15dda23c1 2130
mbed_official 441:d2c15dda23c1 2131 /*!< PVD level configuration */
mbed_official 441:d2c15dda23c1 2132 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
mbed_official 441:d2c15dda23c1 2133 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
mbed_official 441:d2c15dda23c1 2134 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
mbed_official 441:d2c15dda23c1 2135 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
mbed_official 441:d2c15dda23c1 2136 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
mbed_official 441:d2c15dda23c1 2137 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
mbed_official 441:d2c15dda23c1 2138 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
mbed_official 441:d2c15dda23c1 2139 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
mbed_official 441:d2c15dda23c1 2140
mbed_official 441:d2c15dda23c1 2141 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
mbed_official 441:d2c15dda23c1 2142 #define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
mbed_official 441:d2c15dda23c1 2143 #define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
mbed_official 441:d2c15dda23c1 2144 #define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main Regulator Low Voltage in Deep Sleep mode */
mbed_official 441:d2c15dda23c1 2145 #define PWR_CR_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */
mbed_official 441:d2c15dda23c1 2146
mbed_official 441:d2c15dda23c1 2147 #define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
mbed_official 441:d2c15dda23c1 2148 #define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
mbed_official 441:d2c15dda23c1 2149 #define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
mbed_official 441:d2c15dda23c1 2150
mbed_official 441:d2c15dda23c1 2151 #define PWR_CR_FMSSR ((uint32_t)0x00100000) /*!< Flash Memory Sleep System Run */
mbed_official 441:d2c15dda23c1 2152 #define PWR_CR_FISSR ((uint32_t)0x00200000) /*!< Flash Interface Stop while System Run */
mbed_official 441:d2c15dda23c1 2153 /* Legacy define */
mbed_official 441:d2c15dda23c1 2154 #define PWR_CR_PMODE PWR_CR_VOS
mbed_official 441:d2c15dda23c1 2155
mbed_official 441:d2c15dda23c1 2156 /******************* Bit definition for PWR_CSR register ********************/
mbed_official 441:d2c15dda23c1 2157 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
mbed_official 441:d2c15dda23c1 2158 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
mbed_official 441:d2c15dda23c1 2159 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
mbed_official 441:d2c15dda23c1 2160 #define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
mbed_official 441:d2c15dda23c1 2161 #define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
mbed_official 441:d2c15dda23c1 2162 #define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
mbed_official 441:d2c15dda23c1 2163 #define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
mbed_official 441:d2c15dda23c1 2164
mbed_official 441:d2c15dda23c1 2165 /* Legacy define */
mbed_official 441:d2c15dda23c1 2166 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
mbed_official 441:d2c15dda23c1 2167
mbed_official 441:d2c15dda23c1 2168 /******************************************************************************/
mbed_official 441:d2c15dda23c1 2169 /* */
mbed_official 441:d2c15dda23c1 2170 /* Reset and Clock Control */
mbed_official 441:d2c15dda23c1 2171 /* */
mbed_official 441:d2c15dda23c1 2172 /******************************************************************************/
mbed_official 441:d2c15dda23c1 2173 /******************** Bit definition for RCC_CR register ********************/
mbed_official 441:d2c15dda23c1 2174 #define RCC_CR_HSION ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 2175 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 2176
mbed_official 441:d2c15dda23c1 2177 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
mbed_official 441:d2c15dda23c1 2178 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
mbed_official 441:d2c15dda23c1 2179 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
mbed_official 441:d2c15dda23c1 2180 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
mbed_official 441:d2c15dda23c1 2181 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
mbed_official 441:d2c15dda23c1 2182 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
mbed_official 441:d2c15dda23c1 2183
mbed_official 441:d2c15dda23c1 2184 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
mbed_official 441:d2c15dda23c1 2185 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
mbed_official 441:d2c15dda23c1 2186 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
mbed_official 441:d2c15dda23c1 2187 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
mbed_official 441:d2c15dda23c1 2188 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
mbed_official 441:d2c15dda23c1 2189 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
mbed_official 441:d2c15dda23c1 2190 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
mbed_official 441:d2c15dda23c1 2191 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
mbed_official 441:d2c15dda23c1 2192 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
mbed_official 441:d2c15dda23c1 2193
mbed_official 441:d2c15dda23c1 2194 #define RCC_CR_HSEON ((uint32_t)0x00010000)
mbed_official 441:d2c15dda23c1 2195 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
mbed_official 441:d2c15dda23c1 2196 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
mbed_official 441:d2c15dda23c1 2197 #define RCC_CR_CSSON ((uint32_t)0x00080000)
mbed_official 441:d2c15dda23c1 2198 #define RCC_CR_PLLON ((uint32_t)0x01000000)
mbed_official 441:d2c15dda23c1 2199 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
mbed_official 441:d2c15dda23c1 2200 #define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
mbed_official 441:d2c15dda23c1 2201 #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
mbed_official 441:d2c15dda23c1 2202
mbed_official 441:d2c15dda23c1 2203 /******************** Bit definition for RCC_PLLCFGR register ***************/
mbed_official 441:d2c15dda23c1 2204 #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
mbed_official 441:d2c15dda23c1 2205 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 2206 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 2207 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 2208 #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 2209 #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 2210 #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
mbed_official 441:d2c15dda23c1 2211
mbed_official 441:d2c15dda23c1 2212 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
mbed_official 441:d2c15dda23c1 2213 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
mbed_official 441:d2c15dda23c1 2214 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
mbed_official 441:d2c15dda23c1 2215 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
mbed_official 441:d2c15dda23c1 2216 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
mbed_official 441:d2c15dda23c1 2217 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
mbed_official 441:d2c15dda23c1 2218 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
mbed_official 441:d2c15dda23c1 2219 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
mbed_official 441:d2c15dda23c1 2220 #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
mbed_official 441:d2c15dda23c1 2221 #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
mbed_official 441:d2c15dda23c1 2222
mbed_official 441:d2c15dda23c1 2223 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
mbed_official 441:d2c15dda23c1 2224 #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
mbed_official 441:d2c15dda23c1 2225 #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
mbed_official 441:d2c15dda23c1 2226
mbed_official 441:d2c15dda23c1 2227 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
mbed_official 441:d2c15dda23c1 2228 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
mbed_official 441:d2c15dda23c1 2229 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
mbed_official 441:d2c15dda23c1 2230
mbed_official 441:d2c15dda23c1 2231 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
mbed_official 441:d2c15dda23c1 2232 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
mbed_official 441:d2c15dda23c1 2233 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
mbed_official 441:d2c15dda23c1 2234 #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
mbed_official 441:d2c15dda23c1 2235 #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
mbed_official 441:d2c15dda23c1 2236
mbed_official 441:d2c15dda23c1 2237 /******************** Bit definition for RCC_CFGR register ******************/
mbed_official 441:d2c15dda23c1 2238 /*!< SW configuration */
mbed_official 441:d2c15dda23c1 2239 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
mbed_official 441:d2c15dda23c1 2240 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 441:d2c15dda23c1 2241 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 441:d2c15dda23c1 2242
mbed_official 441:d2c15dda23c1 2243 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
mbed_official 441:d2c15dda23c1 2244 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
mbed_official 441:d2c15dda23c1 2245 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
mbed_official 441:d2c15dda23c1 2246
mbed_official 441:d2c15dda23c1 2247 /*!< SWS configuration */
mbed_official 441:d2c15dda23c1 2248 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
mbed_official 441:d2c15dda23c1 2249 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 441:d2c15dda23c1 2250 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 441:d2c15dda23c1 2251
mbed_official 441:d2c15dda23c1 2252 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
mbed_official 441:d2c15dda23c1 2253 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
mbed_official 441:d2c15dda23c1 2254 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
mbed_official 441:d2c15dda23c1 2255
mbed_official 441:d2c15dda23c1 2256 /*!< HPRE configuration */
mbed_official 441:d2c15dda23c1 2257 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
mbed_official 441:d2c15dda23c1 2258 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
mbed_official 441:d2c15dda23c1 2259 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
mbed_official 441:d2c15dda23c1 2260 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
mbed_official 441:d2c15dda23c1 2261 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
mbed_official 441:d2c15dda23c1 2262
mbed_official 441:d2c15dda23c1 2263 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
mbed_official 441:d2c15dda23c1 2264 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
mbed_official 441:d2c15dda23c1 2265 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
mbed_official 441:d2c15dda23c1 2266 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
mbed_official 441:d2c15dda23c1 2267 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
mbed_official 441:d2c15dda23c1 2268 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
mbed_official 441:d2c15dda23c1 2269 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
mbed_official 441:d2c15dda23c1 2270 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
mbed_official 441:d2c15dda23c1 2271 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
mbed_official 441:d2c15dda23c1 2272
mbed_official 441:d2c15dda23c1 2273 /*!< PPRE1 configuration */
mbed_official 441:d2c15dda23c1 2274 #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
mbed_official 441:d2c15dda23c1 2275 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 441:d2c15dda23c1 2276 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 441:d2c15dda23c1 2277 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 441:d2c15dda23c1 2278
mbed_official 441:d2c15dda23c1 2279 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
mbed_official 441:d2c15dda23c1 2280 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
mbed_official 441:d2c15dda23c1 2281 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
mbed_official 441:d2c15dda23c1 2282 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
mbed_official 441:d2c15dda23c1 2283 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
mbed_official 441:d2c15dda23c1 2284
mbed_official 441:d2c15dda23c1 2285 /*!< PPRE2 configuration */
mbed_official 441:d2c15dda23c1 2286 #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
mbed_official 441:d2c15dda23c1 2287 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
mbed_official 441:d2c15dda23c1 2288 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
mbed_official 441:d2c15dda23c1 2289 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
mbed_official 441:d2c15dda23c1 2290
mbed_official 441:d2c15dda23c1 2291 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
mbed_official 441:d2c15dda23c1 2292 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
mbed_official 441:d2c15dda23c1 2293 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
mbed_official 441:d2c15dda23c1 2294 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
mbed_official 441:d2c15dda23c1 2295 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
mbed_official 441:d2c15dda23c1 2296
mbed_official 441:d2c15dda23c1 2297 /*!< RTCPRE configuration */
mbed_official 441:d2c15dda23c1 2298 #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
mbed_official 441:d2c15dda23c1 2299 #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
mbed_official 441:d2c15dda23c1 2300 #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
mbed_official 441:d2c15dda23c1 2301 #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
mbed_official 441:d2c15dda23c1 2302 #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
mbed_official 441:d2c15dda23c1 2303 #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
mbed_official 441:d2c15dda23c1 2304
mbed_official 441:d2c15dda23c1 2305 /*!< MCO1 configuration */
mbed_official 441:d2c15dda23c1 2306 #define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
mbed_official 441:d2c15dda23c1 2307 #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
mbed_official 441:d2c15dda23c1 2308 #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
mbed_official 441:d2c15dda23c1 2309
mbed_official 441:d2c15dda23c1 2310 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
mbed_official 441:d2c15dda23c1 2311
mbed_official 441:d2c15dda23c1 2312 #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
mbed_official 441:d2c15dda23c1 2313 #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
mbed_official 441:d2c15dda23c1 2314 #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
mbed_official 441:d2c15dda23c1 2315 #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
mbed_official 441:d2c15dda23c1 2316
mbed_official 441:d2c15dda23c1 2317 #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
mbed_official 441:d2c15dda23c1 2318 #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
mbed_official 441:d2c15dda23c1 2319 #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
mbed_official 441:d2c15dda23c1 2320 #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
mbed_official 441:d2c15dda23c1 2321
mbed_official 441:d2c15dda23c1 2322 #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
mbed_official 441:d2c15dda23c1 2323 #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
mbed_official 441:d2c15dda23c1 2324 #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
mbed_official 441:d2c15dda23c1 2325
mbed_official 441:d2c15dda23c1 2326 /******************** Bit definition for RCC_CIR register *******************/
mbed_official 441:d2c15dda23c1 2327 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 2328 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 2329 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 2330 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 2331 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 2332 #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
mbed_official 441:d2c15dda23c1 2333
mbed_official 441:d2c15dda23c1 2334 #define RCC_CIR_CSSF ((uint32_t)0x00000080)
mbed_official 441:d2c15dda23c1 2335 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
mbed_official 441:d2c15dda23c1 2336 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
mbed_official 441:d2c15dda23c1 2337 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
mbed_official 441:d2c15dda23c1 2338 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
mbed_official 441:d2c15dda23c1 2339 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
mbed_official 441:d2c15dda23c1 2340 #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
mbed_official 441:d2c15dda23c1 2341
mbed_official 441:d2c15dda23c1 2342 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
mbed_official 441:d2c15dda23c1 2343 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
mbed_official 441:d2c15dda23c1 2344 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
mbed_official 441:d2c15dda23c1 2345 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
mbed_official 441:d2c15dda23c1 2346 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
mbed_official 441:d2c15dda23c1 2347 #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
mbed_official 441:d2c15dda23c1 2348
mbed_official 441:d2c15dda23c1 2349 #define RCC_CIR_CSSC ((uint32_t)0x00800000)
mbed_official 441:d2c15dda23c1 2350
mbed_official 441:d2c15dda23c1 2351 /******************** Bit definition for RCC_AHB1RSTR register **************/
mbed_official 441:d2c15dda23c1 2352 #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 2353 #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 2354 #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 2355 #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 2356 #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 2357 #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
mbed_official 441:d2c15dda23c1 2358 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
mbed_official 441:d2c15dda23c1 2359 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
mbed_official 441:d2c15dda23c1 2360 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
mbed_official 441:d2c15dda23c1 2361
mbed_official 441:d2c15dda23c1 2362 /******************** Bit definition for RCC_AHB2RSTR register **************/
mbed_official 441:d2c15dda23c1 2363 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
mbed_official 441:d2c15dda23c1 2364
mbed_official 441:d2c15dda23c1 2365 /******************** Bit definition for RCC_AHB3RSTR register **************/
mbed_official 441:d2c15dda23c1 2366
mbed_official 441:d2c15dda23c1 2367 /******************** Bit definition for RCC_APB1RSTR register **************/
mbed_official 441:d2c15dda23c1 2368 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 2369 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 2370 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 2371 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 2372 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
mbed_official 441:d2c15dda23c1 2373 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
mbed_official 441:d2c15dda23c1 2374 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
mbed_official 441:d2c15dda23c1 2375 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
mbed_official 441:d2c15dda23c1 2376 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
mbed_official 441:d2c15dda23c1 2377 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
mbed_official 441:d2c15dda23c1 2378 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
mbed_official 441:d2c15dda23c1 2379 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
mbed_official 441:d2c15dda23c1 2380
mbed_official 441:d2c15dda23c1 2381 /******************** Bit definition for RCC_APB2RSTR register **************/
mbed_official 441:d2c15dda23c1 2382 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 2383 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 2384 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
mbed_official 441:d2c15dda23c1 2385 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
mbed_official 441:d2c15dda23c1 2386 #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
mbed_official 441:d2c15dda23c1 2387 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
mbed_official 441:d2c15dda23c1 2388 #define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
mbed_official 441:d2c15dda23c1 2389 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
mbed_official 441:d2c15dda23c1 2390 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
mbed_official 441:d2c15dda23c1 2391 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
mbed_official 441:d2c15dda23c1 2392 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
mbed_official 441:d2c15dda23c1 2393 #define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)
mbed_official 441:d2c15dda23c1 2394
mbed_official 441:d2c15dda23c1 2395 /* Old SPI1RST bit definition, maintained for legacy purpose */
mbed_official 441:d2c15dda23c1 2396 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
mbed_official 441:d2c15dda23c1 2397
mbed_official 441:d2c15dda23c1 2398 /******************** Bit definition for RCC_AHB1ENR register ***************/
mbed_official 441:d2c15dda23c1 2399 #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 2400 #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 2401 #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 2402 #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 2403 #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 2404 #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
mbed_official 441:d2c15dda23c1 2405 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
mbed_official 441:d2c15dda23c1 2406 #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
mbed_official 441:d2c15dda23c1 2407 #define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
mbed_official 441:d2c15dda23c1 2408 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
mbed_official 441:d2c15dda23c1 2409 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
mbed_official 441:d2c15dda23c1 2410
mbed_official 441:d2c15dda23c1 2411 /******************** Bit definition for RCC_AHB2ENR register ***************/
mbed_official 441:d2c15dda23c1 2412 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
mbed_official 441:d2c15dda23c1 2413
mbed_official 441:d2c15dda23c1 2414 /******************** Bit definition for RCC_AHB3ENR register ***************/
mbed_official 441:d2c15dda23c1 2415
mbed_official 441:d2c15dda23c1 2416 /******************** Bit definition for RCC_APB1ENR register ***************/
mbed_official 441:d2c15dda23c1 2417 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 2418 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 2419 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 2420 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 2421 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
mbed_official 441:d2c15dda23c1 2422 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
mbed_official 441:d2c15dda23c1 2423 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
mbed_official 441:d2c15dda23c1 2424 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
mbed_official 441:d2c15dda23c1 2425 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
mbed_official 441:d2c15dda23c1 2426 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
mbed_official 441:d2c15dda23c1 2427 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
mbed_official 441:d2c15dda23c1 2428 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
mbed_official 441:d2c15dda23c1 2429
mbed_official 441:d2c15dda23c1 2430 /******************** Bit definition for RCC_APB2ENR register ***************/
mbed_official 441:d2c15dda23c1 2431 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 2432 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 2433 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
mbed_official 441:d2c15dda23c1 2434 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
mbed_official 441:d2c15dda23c1 2435 #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
mbed_official 441:d2c15dda23c1 2436 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
mbed_official 441:d2c15dda23c1 2437 #define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
mbed_official 441:d2c15dda23c1 2438 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
mbed_official 441:d2c15dda23c1 2439 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
mbed_official 441:d2c15dda23c1 2440 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
mbed_official 441:d2c15dda23c1 2441 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
mbed_official 441:d2c15dda23c1 2442 #define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
mbed_official 441:d2c15dda23c1 2443
mbed_official 441:d2c15dda23c1 2444 /******************** Bit definition for RCC_AHB1LPENR register *************/
mbed_official 441:d2c15dda23c1 2445 #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 2446 #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 2447 #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 2448 #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 2449 #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 2450 #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
mbed_official 441:d2c15dda23c1 2451 #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
mbed_official 441:d2c15dda23c1 2452 #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
mbed_official 441:d2c15dda23c1 2453 #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
mbed_official 441:d2c15dda23c1 2454 #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
mbed_official 441:d2c15dda23c1 2455 #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
mbed_official 441:d2c15dda23c1 2456 #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
mbed_official 441:d2c15dda23c1 2457 #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
mbed_official 441:d2c15dda23c1 2458
mbed_official 441:d2c15dda23c1 2459 /******************** Bit definition for RCC_AHB2LPENR register *************/
mbed_official 441:d2c15dda23c1 2460 #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
mbed_official 441:d2c15dda23c1 2461
mbed_official 441:d2c15dda23c1 2462 /******************** Bit definition for RCC_AHB3LPENR register *************/
mbed_official 441:d2c15dda23c1 2463
mbed_official 441:d2c15dda23c1 2464 /******************** Bit definition for RCC_APB1LPENR register *************/
mbed_official 441:d2c15dda23c1 2465 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 2466 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 2467 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 2468 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 2469 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
mbed_official 441:d2c15dda23c1 2470 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
mbed_official 441:d2c15dda23c1 2471 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
mbed_official 441:d2c15dda23c1 2472 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
mbed_official 441:d2c15dda23c1 2473 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
mbed_official 441:d2c15dda23c1 2474 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
mbed_official 441:d2c15dda23c1 2475 #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
mbed_official 441:d2c15dda23c1 2476 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
mbed_official 441:d2c15dda23c1 2477 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
mbed_official 441:d2c15dda23c1 2478
mbed_official 441:d2c15dda23c1 2479 /******************** Bit definition for RCC_APB2LPENR register *************/
mbed_official 441:d2c15dda23c1 2480 #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 2481 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 2482 #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
mbed_official 441:d2c15dda23c1 2483 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
mbed_official 441:d2c15dda23c1 2484 #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
mbed_official 441:d2c15dda23c1 2485 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
mbed_official 441:d2c15dda23c1 2486 #define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
mbed_official 441:d2c15dda23c1 2487 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
mbed_official 441:d2c15dda23c1 2488 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
mbed_official 441:d2c15dda23c1 2489 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
mbed_official 441:d2c15dda23c1 2490 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
mbed_official 441:d2c15dda23c1 2491 #define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)
mbed_official 441:d2c15dda23c1 2492
mbed_official 441:d2c15dda23c1 2493 /******************** Bit definition for RCC_BDCR register ******************/
mbed_official 441:d2c15dda23c1 2494 #define RCC_BDCR_LSEON ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 2495 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 2496 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 2497 #define RCC_BDCR_LSEMOD ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 2498
mbed_official 441:d2c15dda23c1 2499 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
mbed_official 441:d2c15dda23c1 2500 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
mbed_official 441:d2c15dda23c1 2501 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
mbed_official 441:d2c15dda23c1 2502
mbed_official 441:d2c15dda23c1 2503 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
mbed_official 441:d2c15dda23c1 2504 #define RCC_BDCR_BDRST ((uint32_t)0x00010000)
mbed_official 441:d2c15dda23c1 2505
mbed_official 441:d2c15dda23c1 2506 /******************** Bit definition for RCC_CSR register *******************/
mbed_official 441:d2c15dda23c1 2507 #define RCC_CSR_LSION ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 2508 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 2509 #define RCC_CSR_RMVF ((uint32_t)0x01000000)
mbed_official 441:d2c15dda23c1 2510 #define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
mbed_official 441:d2c15dda23c1 2511 #define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
mbed_official 441:d2c15dda23c1 2512 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
mbed_official 441:d2c15dda23c1 2513 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
mbed_official 441:d2c15dda23c1 2514 #define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
mbed_official 441:d2c15dda23c1 2515 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
mbed_official 441:d2c15dda23c1 2516 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
mbed_official 441:d2c15dda23c1 2517
mbed_official 441:d2c15dda23c1 2518 /******************** Bit definition for RCC_SSCGR register *****************/
mbed_official 441:d2c15dda23c1 2519 #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
mbed_official 441:d2c15dda23c1 2520 #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
mbed_official 441:d2c15dda23c1 2521 #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
mbed_official 441:d2c15dda23c1 2522 #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
mbed_official 441:d2c15dda23c1 2523
mbed_official 441:d2c15dda23c1 2524 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
mbed_official 441:d2c15dda23c1 2525 #define RCC_PLLI2SCFGR_PLLI2SM ((uint32_t)0x0000003F)
mbed_official 441:d2c15dda23c1 2526 #define RCC_PLLI2SCFGR_PLLI2SM_0 ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 2527 #define RCC_PLLI2SCFGR_PLLI2SM_1 ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 2528 #define RCC_PLLI2SCFGR_PLLI2SM_2 ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 2529 #define RCC_PLLI2SCFGR_PLLI2SM_3 ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 2530 #define RCC_PLLI2SCFGR_PLLI2SM_4 ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 2531 #define RCC_PLLI2SCFGR_PLLI2SM_5 ((uint32_t)0x00000020)
mbed_official 441:d2c15dda23c1 2532
mbed_official 441:d2c15dda23c1 2533 #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
mbed_official 441:d2c15dda23c1 2534 #define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
mbed_official 441:d2c15dda23c1 2535 #define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
mbed_official 441:d2c15dda23c1 2536 #define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
mbed_official 441:d2c15dda23c1 2537 #define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
mbed_official 441:d2c15dda23c1 2538 #define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
mbed_official 441:d2c15dda23c1 2539 #define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
mbed_official 441:d2c15dda23c1 2540 #define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
mbed_official 441:d2c15dda23c1 2541 #define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
mbed_official 441:d2c15dda23c1 2542 #define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
mbed_official 441:d2c15dda23c1 2543
mbed_official 441:d2c15dda23c1 2544 #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
mbed_official 441:d2c15dda23c1 2545 #define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
mbed_official 441:d2c15dda23c1 2546 #define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
mbed_official 441:d2c15dda23c1 2547 #define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
mbed_official 441:d2c15dda23c1 2548
mbed_official 441:d2c15dda23c1 2549
mbed_official 441:d2c15dda23c1 2550 /******************************************************************************/
mbed_official 441:d2c15dda23c1 2551 /* */
mbed_official 441:d2c15dda23c1 2552 /* Real-Time Clock (RTC) */
mbed_official 441:d2c15dda23c1 2553 /* */
mbed_official 441:d2c15dda23c1 2554 /******************************************************************************/
mbed_official 441:d2c15dda23c1 2555 /******************** Bits definition for RTC_TR register *******************/
mbed_official 441:d2c15dda23c1 2556 #define RTC_TR_PM ((uint32_t)0x00400000)
mbed_official 441:d2c15dda23c1 2557 #define RTC_TR_HT ((uint32_t)0x00300000)
mbed_official 441:d2c15dda23c1 2558 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
mbed_official 441:d2c15dda23c1 2559 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
mbed_official 441:d2c15dda23c1 2560 #define RTC_TR_HU ((uint32_t)0x000F0000)
mbed_official 441:d2c15dda23c1 2561 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
mbed_official 441:d2c15dda23c1 2562 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
mbed_official 441:d2c15dda23c1 2563 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
mbed_official 441:d2c15dda23c1 2564 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
mbed_official 441:d2c15dda23c1 2565 #define RTC_TR_MNT ((uint32_t)0x00007000)
mbed_official 441:d2c15dda23c1 2566 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
mbed_official 441:d2c15dda23c1 2567 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
mbed_official 441:d2c15dda23c1 2568 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
mbed_official 441:d2c15dda23c1 2569 #define RTC_TR_MNU ((uint32_t)0x00000F00)
mbed_official 441:d2c15dda23c1 2570 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
mbed_official 441:d2c15dda23c1 2571 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
mbed_official 441:d2c15dda23c1 2572 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
mbed_official 441:d2c15dda23c1 2573 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
mbed_official 441:d2c15dda23c1 2574 #define RTC_TR_ST ((uint32_t)0x00000070)
mbed_official 441:d2c15dda23c1 2575 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 2576 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
mbed_official 441:d2c15dda23c1 2577 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
mbed_official 441:d2c15dda23c1 2578 #define RTC_TR_SU ((uint32_t)0x0000000F)
mbed_official 441:d2c15dda23c1 2579 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 2580 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 2581 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 2582 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 2583
mbed_official 441:d2c15dda23c1 2584 /******************** Bits definition for RTC_DR register *******************/
mbed_official 441:d2c15dda23c1 2585 #define RTC_DR_YT ((uint32_t)0x00F00000)
mbed_official 441:d2c15dda23c1 2586 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
mbed_official 441:d2c15dda23c1 2587 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
mbed_official 441:d2c15dda23c1 2588 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
mbed_official 441:d2c15dda23c1 2589 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
mbed_official 441:d2c15dda23c1 2590 #define RTC_DR_YU ((uint32_t)0x000F0000)
mbed_official 441:d2c15dda23c1 2591 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
mbed_official 441:d2c15dda23c1 2592 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
mbed_official 441:d2c15dda23c1 2593 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
mbed_official 441:d2c15dda23c1 2594 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
mbed_official 441:d2c15dda23c1 2595 #define RTC_DR_WDU ((uint32_t)0x0000E000)
mbed_official 441:d2c15dda23c1 2596 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
mbed_official 441:d2c15dda23c1 2597 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
mbed_official 441:d2c15dda23c1 2598 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
mbed_official 441:d2c15dda23c1 2599 #define RTC_DR_MT ((uint32_t)0x00001000)
mbed_official 441:d2c15dda23c1 2600 #define RTC_DR_MU ((uint32_t)0x00000F00)
mbed_official 441:d2c15dda23c1 2601 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
mbed_official 441:d2c15dda23c1 2602 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
mbed_official 441:d2c15dda23c1 2603 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
mbed_official 441:d2c15dda23c1 2604 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
mbed_official 441:d2c15dda23c1 2605 #define RTC_DR_DT ((uint32_t)0x00000030)
mbed_official 441:d2c15dda23c1 2606 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 2607 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
mbed_official 441:d2c15dda23c1 2608 #define RTC_DR_DU ((uint32_t)0x0000000F)
mbed_official 441:d2c15dda23c1 2609 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 2610 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 2611 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 2612 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 2613
mbed_official 441:d2c15dda23c1 2614 /******************** Bits definition for RTC_CR register *******************/
mbed_official 441:d2c15dda23c1 2615 #define RTC_CR_COE ((uint32_t)0x00800000)
mbed_official 441:d2c15dda23c1 2616 #define RTC_CR_OSEL ((uint32_t)0x00600000)
mbed_official 441:d2c15dda23c1 2617 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
mbed_official 441:d2c15dda23c1 2618 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
mbed_official 441:d2c15dda23c1 2619 #define RTC_CR_POL ((uint32_t)0x00100000)
mbed_official 441:d2c15dda23c1 2620 #define RTC_CR_COSEL ((uint32_t)0x00080000)
mbed_official 441:d2c15dda23c1 2621 #define RTC_CR_BCK ((uint32_t)0x00040000)
mbed_official 441:d2c15dda23c1 2622 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
mbed_official 441:d2c15dda23c1 2623 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
mbed_official 441:d2c15dda23c1 2624 #define RTC_CR_TSIE ((uint32_t)0x00008000)
mbed_official 441:d2c15dda23c1 2625 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
mbed_official 441:d2c15dda23c1 2626 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
mbed_official 441:d2c15dda23c1 2627 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
mbed_official 441:d2c15dda23c1 2628 #define RTC_CR_TSE ((uint32_t)0x00000800)
mbed_official 441:d2c15dda23c1 2629 #define RTC_CR_WUTE ((uint32_t)0x00000400)
mbed_official 441:d2c15dda23c1 2630 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
mbed_official 441:d2c15dda23c1 2631 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
mbed_official 441:d2c15dda23c1 2632 #define RTC_CR_DCE ((uint32_t)0x00000080)
mbed_official 441:d2c15dda23c1 2633 #define RTC_CR_FMT ((uint32_t)0x00000040)
mbed_official 441:d2c15dda23c1 2634 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
mbed_official 441:d2c15dda23c1 2635 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 2636 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 2637 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
mbed_official 441:d2c15dda23c1 2638 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 2639 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 2640 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 2641
mbed_official 441:d2c15dda23c1 2642 /******************** Bits definition for RTC_ISR register ******************/
mbed_official 441:d2c15dda23c1 2643 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
mbed_official 441:d2c15dda23c1 2644 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
mbed_official 441:d2c15dda23c1 2645 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
mbed_official 441:d2c15dda23c1 2646 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
mbed_official 441:d2c15dda23c1 2647 #define RTC_ISR_TSF ((uint32_t)0x00000800)
mbed_official 441:d2c15dda23c1 2648 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
mbed_official 441:d2c15dda23c1 2649 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
mbed_official 441:d2c15dda23c1 2650 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
mbed_official 441:d2c15dda23c1 2651 #define RTC_ISR_INIT ((uint32_t)0x00000080)
mbed_official 441:d2c15dda23c1 2652 #define RTC_ISR_INITF ((uint32_t)0x00000040)
mbed_official 441:d2c15dda23c1 2653 #define RTC_ISR_RSF ((uint32_t)0x00000020)
mbed_official 441:d2c15dda23c1 2654 #define RTC_ISR_INITS ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 2655 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 2656 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 2657 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 2658 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 2659
mbed_official 441:d2c15dda23c1 2660 /******************** Bits definition for RTC_PRER register *****************/
mbed_official 441:d2c15dda23c1 2661 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
mbed_official 613:bc40b8d2aec4 2662 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
mbed_official 441:d2c15dda23c1 2663
mbed_official 441:d2c15dda23c1 2664 /******************** Bits definition for RTC_WUTR register *****************/
mbed_official 441:d2c15dda23c1 2665 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
mbed_official 441:d2c15dda23c1 2666
mbed_official 441:d2c15dda23c1 2667 /******************** Bits definition for RTC_CALIBR register ***************/
mbed_official 441:d2c15dda23c1 2668 #define RTC_CALIBR_DCS ((uint32_t)0x00000080)
mbed_official 441:d2c15dda23c1 2669 #define RTC_CALIBR_DC ((uint32_t)0x0000001F)
mbed_official 441:d2c15dda23c1 2670
mbed_official 441:d2c15dda23c1 2671 /******************** Bits definition for RTC_ALRMAR register ***************/
mbed_official 441:d2c15dda23c1 2672 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
mbed_official 441:d2c15dda23c1 2673 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
mbed_official 441:d2c15dda23c1 2674 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
mbed_official 441:d2c15dda23c1 2675 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
mbed_official 441:d2c15dda23c1 2676 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
mbed_official 441:d2c15dda23c1 2677 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
mbed_official 441:d2c15dda23c1 2678 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
mbed_official 441:d2c15dda23c1 2679 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
mbed_official 441:d2c15dda23c1 2680 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
mbed_official 441:d2c15dda23c1 2681 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
mbed_official 441:d2c15dda23c1 2682 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
mbed_official 441:d2c15dda23c1 2683 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
mbed_official 441:d2c15dda23c1 2684 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
mbed_official 441:d2c15dda23c1 2685 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
mbed_official 441:d2c15dda23c1 2686 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
mbed_official 441:d2c15dda23c1 2687 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
mbed_official 441:d2c15dda23c1 2688 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
mbed_official 441:d2c15dda23c1 2689 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
mbed_official 441:d2c15dda23c1 2690 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
mbed_official 441:d2c15dda23c1 2691 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
mbed_official 441:d2c15dda23c1 2692 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
mbed_official 441:d2c15dda23c1 2693 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
mbed_official 441:d2c15dda23c1 2694 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
mbed_official 441:d2c15dda23c1 2695 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
mbed_official 441:d2c15dda23c1 2696 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
mbed_official 441:d2c15dda23c1 2697 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
mbed_official 441:d2c15dda23c1 2698 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
mbed_official 441:d2c15dda23c1 2699 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
mbed_official 441:d2c15dda23c1 2700 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
mbed_official 441:d2c15dda23c1 2701 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
mbed_official 441:d2c15dda23c1 2702 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
mbed_official 441:d2c15dda23c1 2703 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
mbed_official 441:d2c15dda23c1 2704 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 2705 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
mbed_official 441:d2c15dda23c1 2706 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
mbed_official 441:d2c15dda23c1 2707 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
mbed_official 441:d2c15dda23c1 2708 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 2709 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 2710 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 2711 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 2712
mbed_official 441:d2c15dda23c1 2713 /******************** Bits definition for RTC_ALRMBR register ***************/
mbed_official 441:d2c15dda23c1 2714 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
mbed_official 441:d2c15dda23c1 2715 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
mbed_official 441:d2c15dda23c1 2716 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
mbed_official 441:d2c15dda23c1 2717 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
mbed_official 441:d2c15dda23c1 2718 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
mbed_official 441:d2c15dda23c1 2719 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
mbed_official 441:d2c15dda23c1 2720 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
mbed_official 441:d2c15dda23c1 2721 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
mbed_official 441:d2c15dda23c1 2722 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
mbed_official 441:d2c15dda23c1 2723 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
mbed_official 441:d2c15dda23c1 2724 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
mbed_official 441:d2c15dda23c1 2725 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
mbed_official 441:d2c15dda23c1 2726 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
mbed_official 441:d2c15dda23c1 2727 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
mbed_official 441:d2c15dda23c1 2728 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
mbed_official 441:d2c15dda23c1 2729 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
mbed_official 441:d2c15dda23c1 2730 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
mbed_official 441:d2c15dda23c1 2731 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
mbed_official 441:d2c15dda23c1 2732 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
mbed_official 441:d2c15dda23c1 2733 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
mbed_official 441:d2c15dda23c1 2734 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
mbed_official 441:d2c15dda23c1 2735 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
mbed_official 441:d2c15dda23c1 2736 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
mbed_official 441:d2c15dda23c1 2737 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
mbed_official 441:d2c15dda23c1 2738 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
mbed_official 441:d2c15dda23c1 2739 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
mbed_official 441:d2c15dda23c1 2740 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
mbed_official 441:d2c15dda23c1 2741 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
mbed_official 441:d2c15dda23c1 2742 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
mbed_official 441:d2c15dda23c1 2743 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
mbed_official 441:d2c15dda23c1 2744 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
mbed_official 441:d2c15dda23c1 2745 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
mbed_official 441:d2c15dda23c1 2746 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 2747 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
mbed_official 441:d2c15dda23c1 2748 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
mbed_official 441:d2c15dda23c1 2749 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
mbed_official 441:d2c15dda23c1 2750 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 2751 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 2752 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 2753 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 2754
mbed_official 441:d2c15dda23c1 2755 /******************** Bits definition for RTC_WPR register ******************/
mbed_official 441:d2c15dda23c1 2756 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
mbed_official 441:d2c15dda23c1 2757
mbed_official 441:d2c15dda23c1 2758 /******************** Bits definition for RTC_SSR register ******************/
mbed_official 441:d2c15dda23c1 2759 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
mbed_official 441:d2c15dda23c1 2760
mbed_official 441:d2c15dda23c1 2761 /******************** Bits definition for RTC_SHIFTR register ***************/
mbed_official 441:d2c15dda23c1 2762 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
mbed_official 441:d2c15dda23c1 2763 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
mbed_official 441:d2c15dda23c1 2764
mbed_official 441:d2c15dda23c1 2765 /******************** Bits definition for RTC_TSTR register *****************/
mbed_official 441:d2c15dda23c1 2766 #define RTC_TSTR_PM ((uint32_t)0x00400000)
mbed_official 441:d2c15dda23c1 2767 #define RTC_TSTR_HT ((uint32_t)0x00300000)
mbed_official 441:d2c15dda23c1 2768 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
mbed_official 441:d2c15dda23c1 2769 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
mbed_official 441:d2c15dda23c1 2770 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
mbed_official 441:d2c15dda23c1 2771 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
mbed_official 441:d2c15dda23c1 2772 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
mbed_official 441:d2c15dda23c1 2773 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
mbed_official 441:d2c15dda23c1 2774 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
mbed_official 441:d2c15dda23c1 2775 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
mbed_official 441:d2c15dda23c1 2776 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
mbed_official 441:d2c15dda23c1 2777 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
mbed_official 441:d2c15dda23c1 2778 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
mbed_official 441:d2c15dda23c1 2779 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
mbed_official 441:d2c15dda23c1 2780 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
mbed_official 441:d2c15dda23c1 2781 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
mbed_official 441:d2c15dda23c1 2782 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
mbed_official 441:d2c15dda23c1 2783 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
mbed_official 441:d2c15dda23c1 2784 #define RTC_TSTR_ST ((uint32_t)0x00000070)
mbed_official 441:d2c15dda23c1 2785 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 2786 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
mbed_official 441:d2c15dda23c1 2787 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
mbed_official 441:d2c15dda23c1 2788 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
mbed_official 441:d2c15dda23c1 2789 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 2790 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 2791 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 2792 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 2793
mbed_official 441:d2c15dda23c1 2794 /******************** Bits definition for RTC_TSDR register *****************/
mbed_official 441:d2c15dda23c1 2795 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
mbed_official 441:d2c15dda23c1 2796 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
mbed_official 441:d2c15dda23c1 2797 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
mbed_official 441:d2c15dda23c1 2798 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
mbed_official 441:d2c15dda23c1 2799 #define RTC_TSDR_MT ((uint32_t)0x00001000)
mbed_official 441:d2c15dda23c1 2800 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
mbed_official 441:d2c15dda23c1 2801 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
mbed_official 441:d2c15dda23c1 2802 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
mbed_official 441:d2c15dda23c1 2803 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
mbed_official 441:d2c15dda23c1 2804 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
mbed_official 441:d2c15dda23c1 2805 #define RTC_TSDR_DT ((uint32_t)0x00000030)
mbed_official 441:d2c15dda23c1 2806 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 2807 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
mbed_official 441:d2c15dda23c1 2808 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
mbed_official 441:d2c15dda23c1 2809 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 2810 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 2811 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 2812 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 2813
mbed_official 441:d2c15dda23c1 2814 /******************** Bits definition for RTC_TSSSR register ****************/
mbed_official 441:d2c15dda23c1 2815 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
mbed_official 441:d2c15dda23c1 2816
mbed_official 441:d2c15dda23c1 2817 /******************** Bits definition for RTC_CAL register *****************/
mbed_official 441:d2c15dda23c1 2818 #define RTC_CALR_CALP ((uint32_t)0x00008000)
mbed_official 441:d2c15dda23c1 2819 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
mbed_official 441:d2c15dda23c1 2820 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
mbed_official 441:d2c15dda23c1 2821 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
mbed_official 441:d2c15dda23c1 2822 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 2823 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 2824 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 2825 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 2826 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 2827 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
mbed_official 441:d2c15dda23c1 2828 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
mbed_official 441:d2c15dda23c1 2829 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
mbed_official 441:d2c15dda23c1 2830 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
mbed_official 441:d2c15dda23c1 2831
mbed_official 441:d2c15dda23c1 2832 /******************** Bits definition for RTC_TAFCR register ****************/
mbed_official 441:d2c15dda23c1 2833 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
mbed_official 441:d2c15dda23c1 2834 #define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
mbed_official 441:d2c15dda23c1 2835 #define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
mbed_official 441:d2c15dda23c1 2836 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
mbed_official 441:d2c15dda23c1 2837 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
mbed_official 441:d2c15dda23c1 2838 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
mbed_official 441:d2c15dda23c1 2839 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
mbed_official 441:d2c15dda23c1 2840 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
mbed_official 441:d2c15dda23c1 2841 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
mbed_official 441:d2c15dda23c1 2842 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
mbed_official 441:d2c15dda23c1 2843 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
mbed_official 441:d2c15dda23c1 2844 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
mbed_official 441:d2c15dda23c1 2845 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
mbed_official 441:d2c15dda23c1 2846 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
mbed_official 441:d2c15dda23c1 2847 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
mbed_official 441:d2c15dda23c1 2848 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 2849 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 2850 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 2851 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 2852 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 2853
mbed_official 441:d2c15dda23c1 2854 /******************** Bits definition for RTC_ALRMASSR register *************/
mbed_official 441:d2c15dda23c1 2855 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
mbed_official 441:d2c15dda23c1 2856 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
mbed_official 441:d2c15dda23c1 2857 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
mbed_official 441:d2c15dda23c1 2858 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
mbed_official 441:d2c15dda23c1 2859 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
mbed_official 441:d2c15dda23c1 2860 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
mbed_official 441:d2c15dda23c1 2861
mbed_official 441:d2c15dda23c1 2862 /******************** Bits definition for RTC_ALRMBSSR register *************/
mbed_official 441:d2c15dda23c1 2863 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
mbed_official 441:d2c15dda23c1 2864 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
mbed_official 441:d2c15dda23c1 2865 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
mbed_official 441:d2c15dda23c1 2866 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
mbed_official 441:d2c15dda23c1 2867 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
mbed_official 441:d2c15dda23c1 2868 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
mbed_official 441:d2c15dda23c1 2869
mbed_official 441:d2c15dda23c1 2870 /******************** Bits definition for RTC_BKP0R register ****************/
mbed_official 441:d2c15dda23c1 2871 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
mbed_official 441:d2c15dda23c1 2872
mbed_official 441:d2c15dda23c1 2873 /******************** Bits definition for RTC_BKP1R register ****************/
mbed_official 441:d2c15dda23c1 2874 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
mbed_official 441:d2c15dda23c1 2875
mbed_official 441:d2c15dda23c1 2876 /******************** Bits definition for RTC_BKP2R register ****************/
mbed_official 441:d2c15dda23c1 2877 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
mbed_official 441:d2c15dda23c1 2878
mbed_official 441:d2c15dda23c1 2879 /******************** Bits definition for RTC_BKP3R register ****************/
mbed_official 441:d2c15dda23c1 2880 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
mbed_official 441:d2c15dda23c1 2881
mbed_official 441:d2c15dda23c1 2882 /******************** Bits definition for RTC_BKP4R register ****************/
mbed_official 441:d2c15dda23c1 2883 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
mbed_official 441:d2c15dda23c1 2884
mbed_official 441:d2c15dda23c1 2885 /******************** Bits definition for RTC_BKP5R register ****************/
mbed_official 441:d2c15dda23c1 2886 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
mbed_official 441:d2c15dda23c1 2887
mbed_official 441:d2c15dda23c1 2888 /******************** Bits definition for RTC_BKP6R register ****************/
mbed_official 441:d2c15dda23c1 2889 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
mbed_official 441:d2c15dda23c1 2890
mbed_official 441:d2c15dda23c1 2891 /******************** Bits definition for RTC_BKP7R register ****************/
mbed_official 441:d2c15dda23c1 2892 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
mbed_official 441:d2c15dda23c1 2893
mbed_official 441:d2c15dda23c1 2894 /******************** Bits definition for RTC_BKP8R register ****************/
mbed_official 441:d2c15dda23c1 2895 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
mbed_official 441:d2c15dda23c1 2896
mbed_official 441:d2c15dda23c1 2897 /******************** Bits definition for RTC_BKP9R register ****************/
mbed_official 441:d2c15dda23c1 2898 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
mbed_official 441:d2c15dda23c1 2899
mbed_official 441:d2c15dda23c1 2900 /******************** Bits definition for RTC_BKP10R register ***************/
mbed_official 441:d2c15dda23c1 2901 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
mbed_official 441:d2c15dda23c1 2902
mbed_official 441:d2c15dda23c1 2903 /******************** Bits definition for RTC_BKP11R register ***************/
mbed_official 441:d2c15dda23c1 2904 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
mbed_official 441:d2c15dda23c1 2905
mbed_official 441:d2c15dda23c1 2906 /******************** Bits definition for RTC_BKP12R register ***************/
mbed_official 441:d2c15dda23c1 2907 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
mbed_official 441:d2c15dda23c1 2908
mbed_official 441:d2c15dda23c1 2909 /******************** Bits definition for RTC_BKP13R register ***************/
mbed_official 441:d2c15dda23c1 2910 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
mbed_official 441:d2c15dda23c1 2911
mbed_official 441:d2c15dda23c1 2912 /******************** Bits definition for RTC_BKP14R register ***************/
mbed_official 441:d2c15dda23c1 2913 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
mbed_official 441:d2c15dda23c1 2914
mbed_official 441:d2c15dda23c1 2915 /******************** Bits definition for RTC_BKP15R register ***************/
mbed_official 441:d2c15dda23c1 2916 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
mbed_official 441:d2c15dda23c1 2917
mbed_official 441:d2c15dda23c1 2918 /******************** Bits definition for RTC_BKP16R register ***************/
mbed_official 441:d2c15dda23c1 2919 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
mbed_official 441:d2c15dda23c1 2920
mbed_official 441:d2c15dda23c1 2921 /******************** Bits definition for RTC_BKP17R register ***************/
mbed_official 441:d2c15dda23c1 2922 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
mbed_official 441:d2c15dda23c1 2923
mbed_official 441:d2c15dda23c1 2924 /******************** Bits definition for RTC_BKP18R register ***************/
mbed_official 441:d2c15dda23c1 2925 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
mbed_official 441:d2c15dda23c1 2926
mbed_official 441:d2c15dda23c1 2927 /******************** Bits definition for RTC_BKP19R register ***************/
mbed_official 441:d2c15dda23c1 2928 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
mbed_official 441:d2c15dda23c1 2929
mbed_official 441:d2c15dda23c1 2930
mbed_official 441:d2c15dda23c1 2931
mbed_official 441:d2c15dda23c1 2932 /******************************************************************************/
mbed_official 441:d2c15dda23c1 2933 /* */
mbed_official 441:d2c15dda23c1 2934 /* SD host Interface */
mbed_official 441:d2c15dda23c1 2935 /* */
mbed_official 441:d2c15dda23c1 2936 /******************************************************************************/
mbed_official 441:d2c15dda23c1 2937 /****************** Bit definition for SDIO_POWER register ******************/
mbed_official 441:d2c15dda23c1 2938 #define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
mbed_official 441:d2c15dda23c1 2939 #define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 2940 #define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 2941
mbed_official 441:d2c15dda23c1 2942 /****************** Bit definition for SDIO_CLKCR register ******************/
mbed_official 441:d2c15dda23c1 2943 #define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */
mbed_official 441:d2c15dda23c1 2944 #define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */
mbed_official 441:d2c15dda23c1 2945 #define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */
mbed_official 441:d2c15dda23c1 2946 #define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */
mbed_official 441:d2c15dda23c1 2947
mbed_official 441:d2c15dda23c1 2948 #define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
mbed_official 441:d2c15dda23c1 2949 #define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 2950 #define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 2951
mbed_official 441:d2c15dda23c1 2952 #define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDIO_CK dephasing selection bit */
mbed_official 441:d2c15dda23c1 2953 #define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */
mbed_official 441:d2c15dda23c1 2954
mbed_official 441:d2c15dda23c1 2955 /******************* Bit definition for SDIO_ARG register *******************/
mbed_official 441:d2c15dda23c1 2956 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
mbed_official 441:d2c15dda23c1 2957
mbed_official 441:d2c15dda23c1 2958 /******************* Bit definition for SDIO_CMD register *******************/
mbed_official 441:d2c15dda23c1 2959 #define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */
mbed_official 441:d2c15dda23c1 2960
mbed_official 441:d2c15dda23c1 2961 #define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
mbed_official 441:d2c15dda23c1 2962 #define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
mbed_official 441:d2c15dda23c1 2963 #define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
mbed_official 441:d2c15dda23c1 2964
mbed_official 441:d2c15dda23c1 2965 #define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */
mbed_official 441:d2c15dda23c1 2966 #define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
mbed_official 441:d2c15dda23c1 2967 #define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
mbed_official 441:d2c15dda23c1 2968 #define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */
mbed_official 441:d2c15dda23c1 2969 #define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /*!<Enable CMD completion */
mbed_official 441:d2c15dda23c1 2970 #define SDIO_CMD_NIEN ((uint32_t)0x2000) /*!<Not Interrupt Enable */
mbed_official 441:d2c15dda23c1 2971 #define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /*!<CE-ATA command */
mbed_official 441:d2c15dda23c1 2972
mbed_official 441:d2c15dda23c1 2973 /***************** Bit definition for SDIO_RESPCMD register *****************/
mbed_official 441:d2c15dda23c1 2974 #define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */
mbed_official 441:d2c15dda23c1 2975
mbed_official 441:d2c15dda23c1 2976 /****************** Bit definition for SDIO_RESP0 register ******************/
mbed_official 441:d2c15dda23c1 2977 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
mbed_official 441:d2c15dda23c1 2978
mbed_official 441:d2c15dda23c1 2979 /****************** Bit definition for SDIO_RESP1 register ******************/
mbed_official 441:d2c15dda23c1 2980 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
mbed_official 441:d2c15dda23c1 2981
mbed_official 441:d2c15dda23c1 2982 /****************** Bit definition for SDIO_RESP2 register ******************/
mbed_official 441:d2c15dda23c1 2983 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
mbed_official 441:d2c15dda23c1 2984
mbed_official 441:d2c15dda23c1 2985 /****************** Bit definition for SDIO_RESP3 register ******************/
mbed_official 441:d2c15dda23c1 2986 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
mbed_official 441:d2c15dda23c1 2987
mbed_official 441:d2c15dda23c1 2988 /****************** Bit definition for SDIO_RESP4 register ******************/
mbed_official 441:d2c15dda23c1 2989 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
mbed_official 441:d2c15dda23c1 2990
mbed_official 441:d2c15dda23c1 2991 /****************** Bit definition for SDIO_DTIMER register *****************/
mbed_official 441:d2c15dda23c1 2992 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
mbed_official 441:d2c15dda23c1 2993
mbed_official 441:d2c15dda23c1 2994 /****************** Bit definition for SDIO_DLEN register *******************/
mbed_official 441:d2c15dda23c1 2995 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
mbed_official 441:d2c15dda23c1 2996
mbed_official 441:d2c15dda23c1 2997 /****************** Bit definition for SDIO_DCTRL register ******************/
mbed_official 441:d2c15dda23c1 2998 #define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */
mbed_official 441:d2c15dda23c1 2999 #define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */
mbed_official 441:d2c15dda23c1 3000 #define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */
mbed_official 441:d2c15dda23c1 3001 #define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */
mbed_official 441:d2c15dda23c1 3002
mbed_official 441:d2c15dda23c1 3003 #define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
mbed_official 441:d2c15dda23c1 3004 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3005 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3006 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 3007 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 3008
mbed_official 441:d2c15dda23c1 3009 #define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */
mbed_official 441:d2c15dda23c1 3010 #define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */
mbed_official 441:d2c15dda23c1 3011 #define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */
mbed_official 441:d2c15dda23c1 3012 #define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */
mbed_official 441:d2c15dda23c1 3013
mbed_official 441:d2c15dda23c1 3014 /****************** Bit definition for SDIO_DCOUNT register *****************/
mbed_official 441:d2c15dda23c1 3015 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
mbed_official 441:d2c15dda23c1 3016
mbed_official 441:d2c15dda23c1 3017 /****************** Bit definition for SDIO_STA register ********************/
mbed_official 441:d2c15dda23c1 3018 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
mbed_official 441:d2c15dda23c1 3019 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
mbed_official 441:d2c15dda23c1 3020 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
mbed_official 441:d2c15dda23c1 3021 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
mbed_official 441:d2c15dda23c1 3022 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
mbed_official 441:d2c15dda23c1 3023 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
mbed_official 441:d2c15dda23c1 3024 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
mbed_official 441:d2c15dda23c1 3025 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
mbed_official 441:d2c15dda23c1 3026 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
mbed_official 441:d2c15dda23c1 3027 #define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
mbed_official 441:d2c15dda23c1 3028 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
mbed_official 441:d2c15dda23c1 3029 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
mbed_official 441:d2c15dda23c1 3030 #define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
mbed_official 441:d2c15dda23c1 3031 #define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
mbed_official 441:d2c15dda23c1 3032 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
mbed_official 441:d2c15dda23c1 3033 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
mbed_official 441:d2c15dda23c1 3034 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
mbed_official 441:d2c15dda23c1 3035 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
mbed_official 441:d2c15dda23c1 3036 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
mbed_official 441:d2c15dda23c1 3037 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
mbed_official 441:d2c15dda23c1 3038 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
mbed_official 441:d2c15dda23c1 3039 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
mbed_official 441:d2c15dda23c1 3040 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
mbed_official 441:d2c15dda23c1 3041 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
mbed_official 441:d2c15dda23c1 3042
mbed_official 441:d2c15dda23c1 3043 /******************* Bit definition for SDIO_ICR register *******************/
mbed_official 441:d2c15dda23c1 3044 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
mbed_official 441:d2c15dda23c1 3045 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
mbed_official 441:d2c15dda23c1 3046 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
mbed_official 441:d2c15dda23c1 3047 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
mbed_official 441:d2c15dda23c1 3048 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
mbed_official 441:d2c15dda23c1 3049 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
mbed_official 441:d2c15dda23c1 3050 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
mbed_official 441:d2c15dda23c1 3051 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
mbed_official 441:d2c15dda23c1 3052 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
mbed_official 441:d2c15dda23c1 3053 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
mbed_official 441:d2c15dda23c1 3054 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
mbed_official 441:d2c15dda23c1 3055 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
mbed_official 441:d2c15dda23c1 3056 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
mbed_official 441:d2c15dda23c1 3057
mbed_official 441:d2c15dda23c1 3058 /****************** Bit definition for SDIO_MASK register *******************/
mbed_official 441:d2c15dda23c1 3059 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
mbed_official 441:d2c15dda23c1 3060 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
mbed_official 441:d2c15dda23c1 3061 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
mbed_official 441:d2c15dda23c1 3062 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
mbed_official 441:d2c15dda23c1 3063 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
mbed_official 441:d2c15dda23c1 3064 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
mbed_official 441:d2c15dda23c1 3065 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
mbed_official 441:d2c15dda23c1 3066 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
mbed_official 441:d2c15dda23c1 3067 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
mbed_official 441:d2c15dda23c1 3068 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
mbed_official 441:d2c15dda23c1 3069 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
mbed_official 441:d2c15dda23c1 3070 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
mbed_official 441:d2c15dda23c1 3071 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
mbed_official 441:d2c15dda23c1 3072 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
mbed_official 441:d2c15dda23c1 3073 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
mbed_official 441:d2c15dda23c1 3074 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
mbed_official 441:d2c15dda23c1 3075 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
mbed_official 441:d2c15dda23c1 3076 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
mbed_official 441:d2c15dda23c1 3077 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
mbed_official 441:d2c15dda23c1 3078 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
mbed_official 441:d2c15dda23c1 3079 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
mbed_official 441:d2c15dda23c1 3080 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
mbed_official 441:d2c15dda23c1 3081 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
mbed_official 441:d2c15dda23c1 3082 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
mbed_official 441:d2c15dda23c1 3083
mbed_official 441:d2c15dda23c1 3084 /***************** Bit definition for SDIO_FIFOCNT register *****************/
mbed_official 441:d2c15dda23c1 3085 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
mbed_official 441:d2c15dda23c1 3086
mbed_official 441:d2c15dda23c1 3087 /****************** Bit definition for SDIO_FIFO register *******************/
mbed_official 441:d2c15dda23c1 3088 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
mbed_official 441:d2c15dda23c1 3089
mbed_official 441:d2c15dda23c1 3090 /******************************************************************************/
mbed_official 441:d2c15dda23c1 3091 /* */
mbed_official 441:d2c15dda23c1 3092 /* Serial Peripheral Interface */
mbed_official 441:d2c15dda23c1 3093 /* */
mbed_official 441:d2c15dda23c1 3094 /******************************************************************************/
mbed_official 441:d2c15dda23c1 3095 /******************* Bit definition for SPI_CR1 register ********************/
mbed_official 441:d2c15dda23c1 3096 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */
mbed_official 441:d2c15dda23c1 3097 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */
mbed_official 441:d2c15dda23c1 3098 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */
mbed_official 441:d2c15dda23c1 3099
mbed_official 441:d2c15dda23c1 3100 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */
mbed_official 441:d2c15dda23c1 3101 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3102 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3103 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 3104
mbed_official 441:d2c15dda23c1 3105 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */
mbed_official 441:d2c15dda23c1 3106 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */
mbed_official 441:d2c15dda23c1 3107 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */
mbed_official 441:d2c15dda23c1 3108 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */
mbed_official 441:d2c15dda23c1 3109 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */
mbed_official 441:d2c15dda23c1 3110 #define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */
mbed_official 441:d2c15dda23c1 3111 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */
mbed_official 441:d2c15dda23c1 3112 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */
mbed_official 441:d2c15dda23c1 3113 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */
mbed_official 441:d2c15dda23c1 3114 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */
mbed_official 441:d2c15dda23c1 3115
mbed_official 441:d2c15dda23c1 3116 /******************* Bit definition for SPI_CR2 register ********************/
mbed_official 441:d2c15dda23c1 3117 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */
mbed_official 441:d2c15dda23c1 3118 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */
mbed_official 441:d2c15dda23c1 3119 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */
mbed_official 441:d2c15dda23c1 3120 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */
mbed_official 441:d2c15dda23c1 3121 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */
mbed_official 441:d2c15dda23c1 3122 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */
mbed_official 441:d2c15dda23c1 3123 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */
mbed_official 441:d2c15dda23c1 3124
mbed_official 441:d2c15dda23c1 3125 /******************** Bit definition for SPI_SR register ********************/
mbed_official 441:d2c15dda23c1 3126 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */
mbed_official 441:d2c15dda23c1 3127 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */
mbed_official 441:d2c15dda23c1 3128 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */
mbed_official 441:d2c15dda23c1 3129 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */
mbed_official 441:d2c15dda23c1 3130 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */
mbed_official 441:d2c15dda23c1 3131 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */
mbed_official 441:d2c15dda23c1 3132 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */
mbed_official 441:d2c15dda23c1 3133 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */
mbed_official 441:d2c15dda23c1 3134 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
mbed_official 441:d2c15dda23c1 3135
mbed_official 441:d2c15dda23c1 3136 /******************** Bit definition for SPI_DR register ********************/
mbed_official 441:d2c15dda23c1 3137 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */
mbed_official 441:d2c15dda23c1 3138
mbed_official 441:d2c15dda23c1 3139 /******************* Bit definition for SPI_CRCPR register ******************/
mbed_official 441:d2c15dda23c1 3140 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */
mbed_official 441:d2c15dda23c1 3141
mbed_official 441:d2c15dda23c1 3142 /****************** Bit definition for SPI_RXCRCR register ******************/
mbed_official 441:d2c15dda23c1 3143 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */
mbed_official 441:d2c15dda23c1 3144
mbed_official 441:d2c15dda23c1 3145 /****************** Bit definition for SPI_TXCRCR register ******************/
mbed_official 441:d2c15dda23c1 3146 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */
mbed_official 441:d2c15dda23c1 3147
mbed_official 441:d2c15dda23c1 3148 /****************** Bit definition for SPI_I2SCFGR register *****************/
mbed_official 441:d2c15dda23c1 3149 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
mbed_official 441:d2c15dda23c1 3150
mbed_official 441:d2c15dda23c1 3151 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
mbed_official 441:d2c15dda23c1 3152 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3153 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3154
mbed_official 441:d2c15dda23c1 3155 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
mbed_official 441:d2c15dda23c1 3156
mbed_official 441:d2c15dda23c1 3157 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
mbed_official 441:d2c15dda23c1 3158 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3159 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3160
mbed_official 441:d2c15dda23c1 3161 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
mbed_official 441:d2c15dda23c1 3162
mbed_official 441:d2c15dda23c1 3163 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
mbed_official 441:d2c15dda23c1 3164 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3165 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3166
mbed_official 441:d2c15dda23c1 3167 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
mbed_official 441:d2c15dda23c1 3168 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
mbed_official 441:d2c15dda23c1 3169
mbed_official 441:d2c15dda23c1 3170 /****************** Bit definition for SPI_I2SPR register *******************/
mbed_official 441:d2c15dda23c1 3171 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
mbed_official 441:d2c15dda23c1 3172 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
mbed_official 441:d2c15dda23c1 3173 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
mbed_official 441:d2c15dda23c1 3174
mbed_official 441:d2c15dda23c1 3175 /******************************************************************************/
mbed_official 441:d2c15dda23c1 3176 /* */
mbed_official 441:d2c15dda23c1 3177 /* SYSCFG */
mbed_official 441:d2c15dda23c1 3178 /* */
mbed_official 441:d2c15dda23c1 3179 /******************************************************************************/
mbed_official 441:d2c15dda23c1 3180 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
mbed_official 441:d2c15dda23c1 3181 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
mbed_official 441:d2c15dda23c1 3182 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 3183 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 3184 #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 3185
mbed_official 441:d2c15dda23c1 3186 /****************** Bit definition for SYSCFG_PMC register ******************/
mbed_official 441:d2c15dda23c1 3187 #define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */
mbed_official 441:d2c15dda23c1 3188
mbed_official 441:d2c15dda23c1 3189 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
mbed_official 441:d2c15dda23c1 3190 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
mbed_official 441:d2c15dda23c1 3191 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
mbed_official 441:d2c15dda23c1 3192 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
mbed_official 441:d2c15dda23c1 3193 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
mbed_official 441:d2c15dda23c1 3194 /**
mbed_official 441:d2c15dda23c1 3195 * @brief EXTI0 configuration
mbed_official 441:d2c15dda23c1 3196 */
mbed_official 441:d2c15dda23c1 3197 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
mbed_official 441:d2c15dda23c1 3198 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
mbed_official 441:d2c15dda23c1 3199 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
mbed_official 441:d2c15dda23c1 3200 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */
mbed_official 441:d2c15dda23c1 3201 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */
mbed_official 441:d2c15dda23c1 3202 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
mbed_official 441:d2c15dda23c1 3203
mbed_official 441:d2c15dda23c1 3204 /**
mbed_official 441:d2c15dda23c1 3205 * @brief EXTI1 configuration
mbed_official 441:d2c15dda23c1 3206 */
mbed_official 441:d2c15dda23c1 3207 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
mbed_official 441:d2c15dda23c1 3208 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
mbed_official 441:d2c15dda23c1 3209 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
mbed_official 441:d2c15dda23c1 3210 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */
mbed_official 441:d2c15dda23c1 3211 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */
mbed_official 441:d2c15dda23c1 3212 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
mbed_official 441:d2c15dda23c1 3213
mbed_official 441:d2c15dda23c1 3214 /**
mbed_official 441:d2c15dda23c1 3215 * @brief EXTI2 configuration
mbed_official 441:d2c15dda23c1 3216 */
mbed_official 441:d2c15dda23c1 3217 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
mbed_official 441:d2c15dda23c1 3218 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
mbed_official 441:d2c15dda23c1 3219 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
mbed_official 441:d2c15dda23c1 3220 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */
mbed_official 441:d2c15dda23c1 3221 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */
mbed_official 441:d2c15dda23c1 3222 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
mbed_official 441:d2c15dda23c1 3223
mbed_official 441:d2c15dda23c1 3224 /**
mbed_official 441:d2c15dda23c1 3225 * @brief EXTI3 configuration
mbed_official 441:d2c15dda23c1 3226 */
mbed_official 441:d2c15dda23c1 3227 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
mbed_official 441:d2c15dda23c1 3228 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
mbed_official 441:d2c15dda23c1 3229 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
mbed_official 441:d2c15dda23c1 3230 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */
mbed_official 441:d2c15dda23c1 3231 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */
mbed_official 441:d2c15dda23c1 3232 #define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
mbed_official 441:d2c15dda23c1 3233
mbed_official 441:d2c15dda23c1 3234 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
mbed_official 441:d2c15dda23c1 3235 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
mbed_official 441:d2c15dda23c1 3236 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
mbed_official 441:d2c15dda23c1 3237 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
mbed_official 441:d2c15dda23c1 3238 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
mbed_official 441:d2c15dda23c1 3239 /**
mbed_official 441:d2c15dda23c1 3240 * @brief EXTI4 configuration
mbed_official 441:d2c15dda23c1 3241 */
mbed_official 441:d2c15dda23c1 3242 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
mbed_official 441:d2c15dda23c1 3243 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
mbed_official 441:d2c15dda23c1 3244 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
mbed_official 441:d2c15dda23c1 3245 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */
mbed_official 441:d2c15dda23c1 3246 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */
mbed_official 441:d2c15dda23c1 3247 #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
mbed_official 441:d2c15dda23c1 3248
mbed_official 441:d2c15dda23c1 3249 /**
mbed_official 441:d2c15dda23c1 3250 * @brief EXTI5 configuration
mbed_official 441:d2c15dda23c1 3251 */
mbed_official 441:d2c15dda23c1 3252 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
mbed_official 441:d2c15dda23c1 3253 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
mbed_official 441:d2c15dda23c1 3254 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
mbed_official 441:d2c15dda23c1 3255 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */
mbed_official 441:d2c15dda23c1 3256 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */
mbed_official 441:d2c15dda23c1 3257 #define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
mbed_official 441:d2c15dda23c1 3258
mbed_official 441:d2c15dda23c1 3259 /**
mbed_official 441:d2c15dda23c1 3260 * @brief EXTI6 configuration
mbed_official 441:d2c15dda23c1 3261 */
mbed_official 441:d2c15dda23c1 3262 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
mbed_official 441:d2c15dda23c1 3263 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
mbed_official 441:d2c15dda23c1 3264 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
mbed_official 441:d2c15dda23c1 3265 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */
mbed_official 441:d2c15dda23c1 3266 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */
mbed_official 441:d2c15dda23c1 3267 #define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
mbed_official 441:d2c15dda23c1 3268
mbed_official 441:d2c15dda23c1 3269 /**
mbed_official 441:d2c15dda23c1 3270 * @brief EXTI7 configuration
mbed_official 441:d2c15dda23c1 3271 */
mbed_official 441:d2c15dda23c1 3272 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
mbed_official 441:d2c15dda23c1 3273 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
mbed_official 441:d2c15dda23c1 3274 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
mbed_official 441:d2c15dda23c1 3275 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */
mbed_official 441:d2c15dda23c1 3276 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */
mbed_official 441:d2c15dda23c1 3277 #define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
mbed_official 441:d2c15dda23c1 3278
mbed_official 441:d2c15dda23c1 3279
mbed_official 441:d2c15dda23c1 3280 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
mbed_official 441:d2c15dda23c1 3281 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
mbed_official 441:d2c15dda23c1 3282 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
mbed_official 441:d2c15dda23c1 3283 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
mbed_official 441:d2c15dda23c1 3284 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
mbed_official 441:d2c15dda23c1 3285
mbed_official 441:d2c15dda23c1 3286 /**
mbed_official 441:d2c15dda23c1 3287 * @brief EXTI8 configuration
mbed_official 441:d2c15dda23c1 3288 */
mbed_official 441:d2c15dda23c1 3289 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
mbed_official 441:d2c15dda23c1 3290 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
mbed_official 441:d2c15dda23c1 3291 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
mbed_official 441:d2c15dda23c1 3292 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */
mbed_official 441:d2c15dda23c1 3293 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */
mbed_official 441:d2c15dda23c1 3294 #define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
mbed_official 441:d2c15dda23c1 3295
mbed_official 441:d2c15dda23c1 3296 /**
mbed_official 441:d2c15dda23c1 3297 * @brief EXTI9 configuration
mbed_official 441:d2c15dda23c1 3298 */
mbed_official 441:d2c15dda23c1 3299 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
mbed_official 441:d2c15dda23c1 3300 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
mbed_official 441:d2c15dda23c1 3301 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
mbed_official 441:d2c15dda23c1 3302 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */
mbed_official 441:d2c15dda23c1 3303 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */
mbed_official 441:d2c15dda23c1 3304 #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
mbed_official 441:d2c15dda23c1 3305
mbed_official 441:d2c15dda23c1 3306 /**
mbed_official 441:d2c15dda23c1 3307 * @brief EXTI10 configuration
mbed_official 441:d2c15dda23c1 3308 */
mbed_official 441:d2c15dda23c1 3309 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
mbed_official 441:d2c15dda23c1 3310 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
mbed_official 441:d2c15dda23c1 3311 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
mbed_official 441:d2c15dda23c1 3312 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */
mbed_official 441:d2c15dda23c1 3313 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */
mbed_official 441:d2c15dda23c1 3314 #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
mbed_official 441:d2c15dda23c1 3315
mbed_official 441:d2c15dda23c1 3316 /**
mbed_official 441:d2c15dda23c1 3317 * @brief EXTI11 configuration
mbed_official 441:d2c15dda23c1 3318 */
mbed_official 441:d2c15dda23c1 3319 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
mbed_official 441:d2c15dda23c1 3320 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
mbed_official 441:d2c15dda23c1 3321 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
mbed_official 441:d2c15dda23c1 3322 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */
mbed_official 441:d2c15dda23c1 3323 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */
mbed_official 441:d2c15dda23c1 3324 #define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
mbed_official 441:d2c15dda23c1 3325
mbed_official 441:d2c15dda23c1 3326 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
mbed_official 441:d2c15dda23c1 3327 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
mbed_official 441:d2c15dda23c1 3328 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
mbed_official 441:d2c15dda23c1 3329 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
mbed_official 441:d2c15dda23c1 3330 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
mbed_official 441:d2c15dda23c1 3331 /**
mbed_official 441:d2c15dda23c1 3332 * @brief EXTI12 configuration
mbed_official 441:d2c15dda23c1 3333 */
mbed_official 441:d2c15dda23c1 3334 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
mbed_official 441:d2c15dda23c1 3335 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
mbed_official 441:d2c15dda23c1 3336 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
mbed_official 441:d2c15dda23c1 3337 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */
mbed_official 441:d2c15dda23c1 3338 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */
mbed_official 441:d2c15dda23c1 3339 #define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
mbed_official 441:d2c15dda23c1 3340
mbed_official 441:d2c15dda23c1 3341 /**
mbed_official 441:d2c15dda23c1 3342 * @brief EXTI13 configuration
mbed_official 441:d2c15dda23c1 3343 */
mbed_official 441:d2c15dda23c1 3344 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
mbed_official 441:d2c15dda23c1 3345 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
mbed_official 441:d2c15dda23c1 3346 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
mbed_official 441:d2c15dda23c1 3347 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */
mbed_official 441:d2c15dda23c1 3348 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */
mbed_official 441:d2c15dda23c1 3349 #define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
mbed_official 441:d2c15dda23c1 3350
mbed_official 441:d2c15dda23c1 3351 /**
mbed_official 441:d2c15dda23c1 3352 * @brief EXTI14 configuration
mbed_official 441:d2c15dda23c1 3353 */
mbed_official 441:d2c15dda23c1 3354 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
mbed_official 441:d2c15dda23c1 3355 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
mbed_official 441:d2c15dda23c1 3356 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
mbed_official 441:d2c15dda23c1 3357 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */
mbed_official 441:d2c15dda23c1 3358 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */
mbed_official 441:d2c15dda23c1 3359 #define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
mbed_official 441:d2c15dda23c1 3360
mbed_official 441:d2c15dda23c1 3361 /**
mbed_official 441:d2c15dda23c1 3362 * @brief EXTI15 configuration
mbed_official 441:d2c15dda23c1 3363 */
mbed_official 441:d2c15dda23c1 3364 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
mbed_official 441:d2c15dda23c1 3365 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
mbed_official 441:d2c15dda23c1 3366 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
mbed_official 441:d2c15dda23c1 3367 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */
mbed_official 441:d2c15dda23c1 3368 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */
mbed_official 441:d2c15dda23c1 3369 #define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
mbed_official 441:d2c15dda23c1 3370
mbed_official 441:d2c15dda23c1 3371 /****************** Bit definition for SYSCFG_CMPCR register ****************/
mbed_official 441:d2c15dda23c1 3372 #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
mbed_official 441:d2c15dda23c1 3373 #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
mbed_official 441:d2c15dda23c1 3374
mbed_official 441:d2c15dda23c1 3375 /******************************************************************************/
mbed_official 441:d2c15dda23c1 3376 /* */
mbed_official 441:d2c15dda23c1 3377 /* TIM */
mbed_official 441:d2c15dda23c1 3378 /* */
mbed_official 441:d2c15dda23c1 3379 /******************************************************************************/
mbed_official 441:d2c15dda23c1 3380 /******************* Bit definition for TIM_CR1 register ********************/
mbed_official 441:d2c15dda23c1 3381 #define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
mbed_official 441:d2c15dda23c1 3382 #define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
mbed_official 441:d2c15dda23c1 3383 #define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
mbed_official 441:d2c15dda23c1 3384 #define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
mbed_official 441:d2c15dda23c1 3385 #define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
mbed_official 441:d2c15dda23c1 3386
mbed_official 441:d2c15dda23c1 3387 #define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
mbed_official 441:d2c15dda23c1 3388 #define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3389 #define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3390
mbed_official 441:d2c15dda23c1 3391 #define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
mbed_official 441:d2c15dda23c1 3392
mbed_official 441:d2c15dda23c1 3393 #define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
mbed_official 441:d2c15dda23c1 3394 #define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3395 #define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3396
mbed_official 441:d2c15dda23c1 3397 /******************* Bit definition for TIM_CR2 register ********************/
mbed_official 441:d2c15dda23c1 3398 #define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */
mbed_official 441:d2c15dda23c1 3399 #define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */
mbed_official 441:d2c15dda23c1 3400 #define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */
mbed_official 441:d2c15dda23c1 3401
mbed_official 441:d2c15dda23c1 3402 #define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
mbed_official 441:d2c15dda23c1 3403 #define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3404 #define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3405 #define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 3406
mbed_official 441:d2c15dda23c1 3407 #define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
mbed_official 441:d2c15dda23c1 3408 #define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
mbed_official 441:d2c15dda23c1 3409 #define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
mbed_official 441:d2c15dda23c1 3410 #define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
mbed_official 441:d2c15dda23c1 3411 #define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
mbed_official 441:d2c15dda23c1 3412 #define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
mbed_official 441:d2c15dda23c1 3413 #define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
mbed_official 441:d2c15dda23c1 3414 #define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
mbed_official 441:d2c15dda23c1 3415
mbed_official 441:d2c15dda23c1 3416 /******************* Bit definition for TIM_SMCR register *******************/
mbed_official 441:d2c15dda23c1 3417 #define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
mbed_official 441:d2c15dda23c1 3418 #define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3419 #define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3420 #define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 3421
mbed_official 441:d2c15dda23c1 3422 #define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
mbed_official 441:d2c15dda23c1 3423 #define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3424 #define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3425 #define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 3426
mbed_official 441:d2c15dda23c1 3427 #define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
mbed_official 441:d2c15dda23c1 3428
mbed_official 441:d2c15dda23c1 3429 #define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
mbed_official 441:d2c15dda23c1 3430 #define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3431 #define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3432 #define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 3433 #define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 3434
mbed_official 441:d2c15dda23c1 3435 #define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
mbed_official 441:d2c15dda23c1 3436 #define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3437 #define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3438
mbed_official 441:d2c15dda23c1 3439 #define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
mbed_official 441:d2c15dda23c1 3440 #define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
mbed_official 441:d2c15dda23c1 3441
mbed_official 441:d2c15dda23c1 3442 /******************* Bit definition for TIM_DIER register *******************/
mbed_official 441:d2c15dda23c1 3443 #define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
mbed_official 441:d2c15dda23c1 3444 #define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
mbed_official 441:d2c15dda23c1 3445 #define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
mbed_official 441:d2c15dda23c1 3446 #define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
mbed_official 441:d2c15dda23c1 3447 #define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
mbed_official 441:d2c15dda23c1 3448 #define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
mbed_official 441:d2c15dda23c1 3449 #define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
mbed_official 441:d2c15dda23c1 3450 #define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
mbed_official 441:d2c15dda23c1 3451 #define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
mbed_official 441:d2c15dda23c1 3452 #define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
mbed_official 441:d2c15dda23c1 3453 #define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
mbed_official 441:d2c15dda23c1 3454 #define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
mbed_official 441:d2c15dda23c1 3455 #define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
mbed_official 441:d2c15dda23c1 3456 #define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
mbed_official 441:d2c15dda23c1 3457 #define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
mbed_official 441:d2c15dda23c1 3458
mbed_official 441:d2c15dda23c1 3459 /******************** Bit definition for TIM_SR register ********************/
mbed_official 441:d2c15dda23c1 3460 #define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
mbed_official 441:d2c15dda23c1 3461 #define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
mbed_official 441:d2c15dda23c1 3462 #define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
mbed_official 441:d2c15dda23c1 3463 #define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
mbed_official 441:d2c15dda23c1 3464 #define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
mbed_official 441:d2c15dda23c1 3465 #define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
mbed_official 441:d2c15dda23c1 3466 #define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
mbed_official 441:d2c15dda23c1 3467 #define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
mbed_official 441:d2c15dda23c1 3468 #define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
mbed_official 441:d2c15dda23c1 3469 #define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
mbed_official 441:d2c15dda23c1 3470 #define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
mbed_official 441:d2c15dda23c1 3471 #define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
mbed_official 441:d2c15dda23c1 3472
mbed_official 441:d2c15dda23c1 3473 /******************* Bit definition for TIM_EGR register ********************/
mbed_official 441:d2c15dda23c1 3474 #define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */
mbed_official 441:d2c15dda23c1 3475 #define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */
mbed_official 441:d2c15dda23c1 3476 #define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */
mbed_official 441:d2c15dda23c1 3477 #define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */
mbed_official 441:d2c15dda23c1 3478 #define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */
mbed_official 441:d2c15dda23c1 3479 #define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */
mbed_official 441:d2c15dda23c1 3480 #define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */
mbed_official 441:d2c15dda23c1 3481 #define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */
mbed_official 441:d2c15dda23c1 3482
mbed_official 441:d2c15dda23c1 3483 /****************** Bit definition for TIM_CCMR1 register *******************/
mbed_official 441:d2c15dda23c1 3484 #define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
mbed_official 441:d2c15dda23c1 3485 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3486 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3487
mbed_official 441:d2c15dda23c1 3488 #define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */
mbed_official 441:d2c15dda23c1 3489 #define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */
mbed_official 441:d2c15dda23c1 3490
mbed_official 441:d2c15dda23c1 3491 #define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
mbed_official 441:d2c15dda23c1 3492 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3493 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3494 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 3495
mbed_official 441:d2c15dda23c1 3496 #define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */
mbed_official 441:d2c15dda23c1 3497
mbed_official 441:d2c15dda23c1 3498 #define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
mbed_official 441:d2c15dda23c1 3499 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3500 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3501
mbed_official 441:d2c15dda23c1 3502 #define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */
mbed_official 441:d2c15dda23c1 3503 #define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */
mbed_official 441:d2c15dda23c1 3504
mbed_official 441:d2c15dda23c1 3505 #define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
mbed_official 441:d2c15dda23c1 3506 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3507 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3508 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 3509
mbed_official 441:d2c15dda23c1 3510 #define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */
mbed_official 441:d2c15dda23c1 3511
mbed_official 441:d2c15dda23c1 3512 /*----------------------------------------------------------------------------*/
mbed_official 441:d2c15dda23c1 3513
mbed_official 441:d2c15dda23c1 3514 #define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
mbed_official 441:d2c15dda23c1 3515 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3516 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3517
mbed_official 441:d2c15dda23c1 3518 #define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
mbed_official 441:d2c15dda23c1 3519 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3520 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3521 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 3522 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 3523
mbed_official 441:d2c15dda23c1 3524 #define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
mbed_official 441:d2c15dda23c1 3525 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3526 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3527
mbed_official 441:d2c15dda23c1 3528 #define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
mbed_official 441:d2c15dda23c1 3529 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3530 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3531 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 3532 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 3533
mbed_official 441:d2c15dda23c1 3534 /****************** Bit definition for TIM_CCMR2 register *******************/
mbed_official 441:d2c15dda23c1 3535 #define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
mbed_official 441:d2c15dda23c1 3536 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3537 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3538
mbed_official 441:d2c15dda23c1 3539 #define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */
mbed_official 441:d2c15dda23c1 3540 #define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */
mbed_official 441:d2c15dda23c1 3541
mbed_official 441:d2c15dda23c1 3542 #define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
mbed_official 441:d2c15dda23c1 3543 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3544 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3545 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 3546
mbed_official 441:d2c15dda23c1 3547 #define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */
mbed_official 441:d2c15dda23c1 3548
mbed_official 441:d2c15dda23c1 3549 #define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
mbed_official 441:d2c15dda23c1 3550 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3551 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3552
mbed_official 441:d2c15dda23c1 3553 #define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */
mbed_official 441:d2c15dda23c1 3554 #define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */
mbed_official 441:d2c15dda23c1 3555
mbed_official 441:d2c15dda23c1 3556 #define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
mbed_official 441:d2c15dda23c1 3557 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3558 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3559 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 3560
mbed_official 441:d2c15dda23c1 3561 #define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
mbed_official 441:d2c15dda23c1 3562
mbed_official 441:d2c15dda23c1 3563 /*----------------------------------------------------------------------------*/
mbed_official 441:d2c15dda23c1 3564
mbed_official 441:d2c15dda23c1 3565 #define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
mbed_official 441:d2c15dda23c1 3566 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3567 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3568
mbed_official 441:d2c15dda23c1 3569 #define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
mbed_official 441:d2c15dda23c1 3570 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3571 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3572 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 3573 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 3574
mbed_official 441:d2c15dda23c1 3575 #define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
mbed_official 441:d2c15dda23c1 3576 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3577 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3578
mbed_official 441:d2c15dda23c1 3579 #define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
mbed_official 441:d2c15dda23c1 3580 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3581 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3582 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 3583 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 3584
mbed_official 441:d2c15dda23c1 3585 /******************* Bit definition for TIM_CCER register *******************/
mbed_official 441:d2c15dda23c1 3586 #define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */
mbed_official 441:d2c15dda23c1 3587 #define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */
mbed_official 441:d2c15dda23c1 3588 #define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
mbed_official 441:d2c15dda23c1 3589 #define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
mbed_official 441:d2c15dda23c1 3590 #define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */
mbed_official 441:d2c15dda23c1 3591 #define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */
mbed_official 441:d2c15dda23c1 3592 #define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
mbed_official 441:d2c15dda23c1 3593 #define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
mbed_official 441:d2c15dda23c1 3594 #define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */
mbed_official 441:d2c15dda23c1 3595 #define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */
mbed_official 441:d2c15dda23c1 3596 #define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
mbed_official 441:d2c15dda23c1 3597 #define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
mbed_official 441:d2c15dda23c1 3598 #define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */
mbed_official 441:d2c15dda23c1 3599 #define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */
mbed_official 441:d2c15dda23c1 3600 #define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
mbed_official 441:d2c15dda23c1 3601
mbed_official 441:d2c15dda23c1 3602 /******************* Bit definition for TIM_CNT register ********************/
mbed_official 441:d2c15dda23c1 3603 #define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
mbed_official 441:d2c15dda23c1 3604
mbed_official 441:d2c15dda23c1 3605 /******************* Bit definition for TIM_PSC register ********************/
mbed_official 441:d2c15dda23c1 3606 #define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
mbed_official 441:d2c15dda23c1 3607
mbed_official 441:d2c15dda23c1 3608 /******************* Bit definition for TIM_ARR register ********************/
mbed_official 441:d2c15dda23c1 3609 #define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
mbed_official 441:d2c15dda23c1 3610
mbed_official 441:d2c15dda23c1 3611 /******************* Bit definition for TIM_RCR register ********************/
mbed_official 441:d2c15dda23c1 3612 #define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */
mbed_official 441:d2c15dda23c1 3613
mbed_official 441:d2c15dda23c1 3614 /******************* Bit definition for TIM_CCR1 register *******************/
mbed_official 441:d2c15dda23c1 3615 #define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
mbed_official 441:d2c15dda23c1 3616
mbed_official 441:d2c15dda23c1 3617 /******************* Bit definition for TIM_CCR2 register *******************/
mbed_official 441:d2c15dda23c1 3618 #define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
mbed_official 441:d2c15dda23c1 3619
mbed_official 441:d2c15dda23c1 3620 /******************* Bit definition for TIM_CCR3 register *******************/
mbed_official 441:d2c15dda23c1 3621 #define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
mbed_official 441:d2c15dda23c1 3622
mbed_official 441:d2c15dda23c1 3623 /******************* Bit definition for TIM_CCR4 register *******************/
mbed_official 441:d2c15dda23c1 3624 #define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
mbed_official 441:d2c15dda23c1 3625
mbed_official 441:d2c15dda23c1 3626 /******************* Bit definition for TIM_BDTR register *******************/
mbed_official 441:d2c15dda23c1 3627 #define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
mbed_official 441:d2c15dda23c1 3628 #define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3629 #define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3630 #define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 3631 #define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 3632 #define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 3633 #define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */
mbed_official 441:d2c15dda23c1 3634 #define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */
mbed_official 441:d2c15dda23c1 3635 #define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */
mbed_official 441:d2c15dda23c1 3636
mbed_official 441:d2c15dda23c1 3637 #define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
mbed_official 441:d2c15dda23c1 3638 #define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3639 #define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3640
mbed_official 441:d2c15dda23c1 3641 #define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */
mbed_official 441:d2c15dda23c1 3642 #define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */
mbed_official 441:d2c15dda23c1 3643 #define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */
mbed_official 441:d2c15dda23c1 3644 #define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */
mbed_official 441:d2c15dda23c1 3645 #define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */
mbed_official 441:d2c15dda23c1 3646 #define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */
mbed_official 441:d2c15dda23c1 3647
mbed_official 441:d2c15dda23c1 3648 /******************* Bit definition for TIM_DCR register ********************/
mbed_official 441:d2c15dda23c1 3649 #define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
mbed_official 441:d2c15dda23c1 3650 #define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3651 #define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3652 #define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 3653 #define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 3654 #define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 3655
mbed_official 441:d2c15dda23c1 3656 #define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
mbed_official 441:d2c15dda23c1 3657 #define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3658 #define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3659 #define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 3660 #define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 3661 #define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 3662
mbed_official 441:d2c15dda23c1 3663 /******************* Bit definition for TIM_DMAR register *******************/
mbed_official 441:d2c15dda23c1 3664 #define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
mbed_official 441:d2c15dda23c1 3665
mbed_official 441:d2c15dda23c1 3666 /******************* Bit definition for TIM_OR register *********************/
mbed_official 441:d2c15dda23c1 3667 #define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
mbed_official 441:d2c15dda23c1 3668 #define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3669 #define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3670 #define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
mbed_official 441:d2c15dda23c1 3671 #define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3672 #define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3673
mbed_official 441:d2c15dda23c1 3674
mbed_official 441:d2c15dda23c1 3675 /******************************************************************************/
mbed_official 441:d2c15dda23c1 3676 /* */
mbed_official 441:d2c15dda23c1 3677 /* Universal Synchronous Asynchronous Receiver Transmitter */
mbed_official 441:d2c15dda23c1 3678 /* */
mbed_official 441:d2c15dda23c1 3679 /******************************************************************************/
mbed_official 441:d2c15dda23c1 3680 /******************* Bit definition for USART_SR register *******************/
mbed_official 441:d2c15dda23c1 3681 #define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */
mbed_official 441:d2c15dda23c1 3682 #define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */
mbed_official 441:d2c15dda23c1 3683 #define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */
mbed_official 441:d2c15dda23c1 3684 #define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */
mbed_official 441:d2c15dda23c1 3685 #define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */
mbed_official 441:d2c15dda23c1 3686 #define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */
mbed_official 441:d2c15dda23c1 3687 #define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */
mbed_official 441:d2c15dda23c1 3688 #define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */
mbed_official 441:d2c15dda23c1 3689 #define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */
mbed_official 441:d2c15dda23c1 3690 #define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */
mbed_official 441:d2c15dda23c1 3691
mbed_official 441:d2c15dda23c1 3692 /******************* Bit definition for USART_DR register *******************/
mbed_official 441:d2c15dda23c1 3693 #define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */
mbed_official 441:d2c15dda23c1 3694
mbed_official 441:d2c15dda23c1 3695 /****************** Bit definition for USART_BRR register *******************/
mbed_official 441:d2c15dda23c1 3696 #define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */
mbed_official 441:d2c15dda23c1 3697 #define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */
mbed_official 441:d2c15dda23c1 3698
mbed_official 441:d2c15dda23c1 3699 /****************** Bit definition for USART_CR1 register *******************/
mbed_official 441:d2c15dda23c1 3700 #define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */
mbed_official 441:d2c15dda23c1 3701 #define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */
mbed_official 441:d2c15dda23c1 3702 #define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */
mbed_official 441:d2c15dda23c1 3703 #define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */
mbed_official 441:d2c15dda23c1 3704 #define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */
mbed_official 441:d2c15dda23c1 3705 #define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */
mbed_official 441:d2c15dda23c1 3706 #define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */
mbed_official 441:d2c15dda23c1 3707 #define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */
mbed_official 441:d2c15dda23c1 3708 #define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */
mbed_official 441:d2c15dda23c1 3709 #define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */
mbed_official 441:d2c15dda23c1 3710 #define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */
mbed_official 441:d2c15dda23c1 3711 #define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */
mbed_official 441:d2c15dda23c1 3712 #define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */
mbed_official 441:d2c15dda23c1 3713 #define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */
mbed_official 441:d2c15dda23c1 3714 #define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */
mbed_official 441:d2c15dda23c1 3715
mbed_official 441:d2c15dda23c1 3716 /****************** Bit definition for USART_CR2 register *******************/
mbed_official 441:d2c15dda23c1 3717 #define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */
mbed_official 441:d2c15dda23c1 3718 #define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */
mbed_official 441:d2c15dda23c1 3719 #define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
mbed_official 441:d2c15dda23c1 3720 #define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */
mbed_official 441:d2c15dda23c1 3721 #define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */
mbed_official 441:d2c15dda23c1 3722 #define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */
mbed_official 441:d2c15dda23c1 3723 #define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */
mbed_official 441:d2c15dda23c1 3724
mbed_official 441:d2c15dda23c1 3725 #define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
mbed_official 441:d2c15dda23c1 3726 #define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3727 #define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3728
mbed_official 441:d2c15dda23c1 3729 #define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */
mbed_official 441:d2c15dda23c1 3730
mbed_official 441:d2c15dda23c1 3731 /****************** Bit definition for USART_CR3 register *******************/
mbed_official 441:d2c15dda23c1 3732 #define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */
mbed_official 441:d2c15dda23c1 3733 #define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */
mbed_official 441:d2c15dda23c1 3734 #define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */
mbed_official 441:d2c15dda23c1 3735 #define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */
mbed_official 441:d2c15dda23c1 3736 #define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */
mbed_official 441:d2c15dda23c1 3737 #define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */
mbed_official 441:d2c15dda23c1 3738 #define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */
mbed_official 441:d2c15dda23c1 3739 #define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */
mbed_official 441:d2c15dda23c1 3740 #define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */
mbed_official 441:d2c15dda23c1 3741 #define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */
mbed_official 441:d2c15dda23c1 3742 #define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */
mbed_official 441:d2c15dda23c1 3743 #define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */
mbed_official 441:d2c15dda23c1 3744
mbed_official 441:d2c15dda23c1 3745 /****************** Bit definition for USART_GTPR register ******************/
mbed_official 441:d2c15dda23c1 3746 #define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
mbed_official 441:d2c15dda23c1 3747 #define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3748 #define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3749 #define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 3750 #define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 3751 #define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 3752 #define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */
mbed_official 441:d2c15dda23c1 3753 #define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */
mbed_official 441:d2c15dda23c1 3754 #define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */
mbed_official 441:d2c15dda23c1 3755
mbed_official 441:d2c15dda23c1 3756 #define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */
mbed_official 441:d2c15dda23c1 3757
mbed_official 441:d2c15dda23c1 3758 /******************************************************************************/
mbed_official 441:d2c15dda23c1 3759 /* */
mbed_official 441:d2c15dda23c1 3760 /* Window WATCHDOG */
mbed_official 441:d2c15dda23c1 3761 /* */
mbed_official 441:d2c15dda23c1 3762 /******************************************************************************/
mbed_official 441:d2c15dda23c1 3763 /******************* Bit definition for WWDG_CR register ********************/
mbed_official 441:d2c15dda23c1 3764 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
mbed_official 441:d2c15dda23c1 3765 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3766 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3767 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 3768 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 3769 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 3770 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
mbed_official 441:d2c15dda23c1 3771 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
mbed_official 441:d2c15dda23c1 3772
mbed_official 441:d2c15dda23c1 3773 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
mbed_official 441:d2c15dda23c1 3774
mbed_official 441:d2c15dda23c1 3775 /******************* Bit definition for WWDG_CFR register *******************/
mbed_official 441:d2c15dda23c1 3776 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
mbed_official 441:d2c15dda23c1 3777 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3778 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3779 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 3780 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 3781 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 3782 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
mbed_official 441:d2c15dda23c1 3783 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
mbed_official 441:d2c15dda23c1 3784
mbed_official 441:d2c15dda23c1 3785 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
mbed_official 441:d2c15dda23c1 3786 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3787 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3788
mbed_official 441:d2c15dda23c1 3789 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
mbed_official 441:d2c15dda23c1 3790
mbed_official 441:d2c15dda23c1 3791 /******************* Bit definition for WWDG_SR register ********************/
mbed_official 441:d2c15dda23c1 3792 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
mbed_official 441:d2c15dda23c1 3793
mbed_official 441:d2c15dda23c1 3794
mbed_official 441:d2c15dda23c1 3795 /******************************************************************************/
mbed_official 441:d2c15dda23c1 3796 /* */
mbed_official 441:d2c15dda23c1 3797 /* DBG */
mbed_official 441:d2c15dda23c1 3798 /* */
mbed_official 441:d2c15dda23c1 3799 /******************************************************************************/
mbed_official 441:d2c15dda23c1 3800 /******************** Bit definition for DBGMCU_IDCODE register *************/
mbed_official 441:d2c15dda23c1 3801 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
mbed_official 441:d2c15dda23c1 3802 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
mbed_official 441:d2c15dda23c1 3803
mbed_official 441:d2c15dda23c1 3804 /******************** Bit definition for DBGMCU_CR register *****************/
mbed_official 441:d2c15dda23c1 3805 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 3806 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 3807 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 3808 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
mbed_official 441:d2c15dda23c1 3809
mbed_official 441:d2c15dda23c1 3810 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
mbed_official 441:d2c15dda23c1 3811 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3812 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3813
mbed_official 441:d2c15dda23c1 3814 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
mbed_official 441:d2c15dda23c1 3815 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 3816 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 3817 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
mbed_official 441:d2c15dda23c1 3818 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
mbed_official 441:d2c15dda23c1 3819 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
mbed_official 441:d2c15dda23c1 3820 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
mbed_official 441:d2c15dda23c1 3821 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
mbed_official 441:d2c15dda23c1 3822 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
mbed_official 441:d2c15dda23c1 3823 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
mbed_official 441:d2c15dda23c1 3824 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
mbed_official 441:d2c15dda23c1 3825 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
mbed_official 441:d2c15dda23c1 3826 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
mbed_official 441:d2c15dda23c1 3827 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
mbed_official 441:d2c15dda23c1 3828 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
mbed_official 441:d2c15dda23c1 3829 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
mbed_official 441:d2c15dda23c1 3830 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
mbed_official 441:d2c15dda23c1 3831 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
mbed_official 441:d2c15dda23c1 3832 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
mbed_official 441:d2c15dda23c1 3833 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
mbed_official 441:d2c15dda23c1 3834
mbed_official 441:d2c15dda23c1 3835 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
mbed_official 441:d2c15dda23c1 3836 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
mbed_official 441:d2c15dda23c1 3837 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
mbed_official 441:d2c15dda23c1 3838 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
mbed_official 441:d2c15dda23c1 3839 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
mbed_official 441:d2c15dda23c1 3840 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
mbed_official 441:d2c15dda23c1 3841
mbed_official 441:d2c15dda23c1 3842 /******************************************************************************/
mbed_official 441:d2c15dda23c1 3843 /* */
mbed_official 441:d2c15dda23c1 3844 /* USB_OTG */
mbed_official 441:d2c15dda23c1 3845 /* */
mbed_official 441:d2c15dda23c1 3846 /******************************************************************************/
mbed_official 441:d2c15dda23c1 3847 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
mbed_official 441:d2c15dda23c1 3848 #define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */
mbed_official 441:d2c15dda23c1 3849 #define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */
mbed_official 441:d2c15dda23c1 3850 #define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host negotiation success */
mbed_official 441:d2c15dda23c1 3851 #define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */
mbed_official 441:d2c15dda23c1 3852 #define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */
mbed_official 441:d2c15dda23c1 3853 #define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */
mbed_official 441:d2c15dda23c1 3854 #define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */
mbed_official 441:d2c15dda23c1 3855 #define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */
mbed_official 441:d2c15dda23c1 3856 #define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */
mbed_official 441:d2c15dda23c1 3857 #define USB_OTG_GOTGCTL_BSVLD ((uint32_t)0x00080000) /*!< B-session valid */
mbed_official 441:d2c15dda23c1 3858
mbed_official 441:d2c15dda23c1 3859 /******************** Bit definition forUSB_OTG_HCFG register ********************/
mbed_official 441:d2c15dda23c1 3860
mbed_official 441:d2c15dda23c1 3861 #define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */
mbed_official 441:d2c15dda23c1 3862 #define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3863 #define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3864 #define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */
mbed_official 441:d2c15dda23c1 3865
mbed_official 441:d2c15dda23c1 3866 /******************** Bit definition forUSB_OTG_DCFG register ********************/
mbed_official 441:d2c15dda23c1 3867
mbed_official 441:d2c15dda23c1 3868 #define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */
mbed_official 441:d2c15dda23c1 3869 #define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3870 #define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3871 #define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */
mbed_official 441:d2c15dda23c1 3872
mbed_official 441:d2c15dda23c1 3873 #define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */
mbed_official 441:d2c15dda23c1 3874 #define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3875 #define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3876 #define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 3877 #define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 3878 #define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 3879 #define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */
mbed_official 441:d2c15dda23c1 3880 #define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */
mbed_official 441:d2c15dda23c1 3881
mbed_official 441:d2c15dda23c1 3882 #define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */
mbed_official 441:d2c15dda23c1 3883 #define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3884 #define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3885
mbed_official 441:d2c15dda23c1 3886 #define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */
mbed_official 441:d2c15dda23c1 3887 #define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3888 #define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3889
mbed_official 441:d2c15dda23c1 3890 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
mbed_official 441:d2c15dda23c1 3891 #define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */
mbed_official 441:d2c15dda23c1 3892 #define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */
mbed_official 441:d2c15dda23c1 3893 #define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */
mbed_official 441:d2c15dda23c1 3894
mbed_official 441:d2c15dda23c1 3895 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
mbed_official 441:d2c15dda23c1 3896 #define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */
mbed_official 441:d2c15dda23c1 3897 #define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */
mbed_official 441:d2c15dda23c1 3898 #define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */
mbed_official 441:d2c15dda23c1 3899 #define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */
mbed_official 441:d2c15dda23c1 3900 #define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */
mbed_official 441:d2c15dda23c1 3901 #define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */
mbed_official 441:d2c15dda23c1 3902
mbed_official 441:d2c15dda23c1 3903 /******************** Bit definition forUSB_OTG_DCTL register ********************/
mbed_official 441:d2c15dda23c1 3904 #define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */
mbed_official 441:d2c15dda23c1 3905 #define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */
mbed_official 441:d2c15dda23c1 3906 #define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */
mbed_official 441:d2c15dda23c1 3907 #define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */
mbed_official 441:d2c15dda23c1 3908
mbed_official 441:d2c15dda23c1 3909 #define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */
mbed_official 441:d2c15dda23c1 3910 #define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3911 #define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3912 #define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 3913 #define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */
mbed_official 441:d2c15dda23c1 3914 #define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */
mbed_official 441:d2c15dda23c1 3915 #define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */
mbed_official 441:d2c15dda23c1 3916 #define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */
mbed_official 441:d2c15dda23c1 3917 #define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */
mbed_official 441:d2c15dda23c1 3918
mbed_official 441:d2c15dda23c1 3919 /******************** Bit definition forUSB_OTG_HFIR register ********************/
mbed_official 441:d2c15dda23c1 3920 #define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */
mbed_official 441:d2c15dda23c1 3921
mbed_official 441:d2c15dda23c1 3922 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
mbed_official 441:d2c15dda23c1 3923 #define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */
mbed_official 441:d2c15dda23c1 3924 #define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */
mbed_official 441:d2c15dda23c1 3925
mbed_official 441:d2c15dda23c1 3926 /******************** Bit definition forUSB_OTG_DSTS register ********************/
mbed_official 441:d2c15dda23c1 3927 #define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */
mbed_official 441:d2c15dda23c1 3928
mbed_official 441:d2c15dda23c1 3929 #define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */
mbed_official 441:d2c15dda23c1 3930 #define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3931 #define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3932 #define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */
mbed_official 441:d2c15dda23c1 3933 #define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */
mbed_official 441:d2c15dda23c1 3934
mbed_official 441:d2c15dda23c1 3935 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
mbed_official 441:d2c15dda23c1 3936 #define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */
mbed_official 441:d2c15dda23c1 3937
mbed_official 441:d2c15dda23c1 3938 #define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */
mbed_official 441:d2c15dda23c1 3939 #define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3940 #define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3941 #define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 3942 #define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 3943 #define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */
mbed_official 441:d2c15dda23c1 3944 #define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */
mbed_official 441:d2c15dda23c1 3945 #define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */
mbed_official 441:d2c15dda23c1 3946
mbed_official 441:d2c15dda23c1 3947 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
mbed_official 441:d2c15dda23c1 3948
mbed_official 441:d2c15dda23c1 3949 #define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */
mbed_official 441:d2c15dda23c1 3950 #define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3951 #define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3952 #define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 3953 #define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
mbed_official 441:d2c15dda23c1 3954 #define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */
mbed_official 441:d2c15dda23c1 3955 #define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */
mbed_official 441:d2c15dda23c1 3956
mbed_official 441:d2c15dda23c1 3957 #define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */
mbed_official 441:d2c15dda23c1 3958 #define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3959 #define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3960 #define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 3961 #define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 3962 #define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */
mbed_official 441:d2c15dda23c1 3963 #define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */
mbed_official 441:d2c15dda23c1 3964 #define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */
mbed_official 441:d2c15dda23c1 3965 #define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */
mbed_official 441:d2c15dda23c1 3966 #define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */
mbed_official 441:d2c15dda23c1 3967 #define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */
mbed_official 441:d2c15dda23c1 3968 #define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */
mbed_official 441:d2c15dda23c1 3969 #define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */
mbed_official 441:d2c15dda23c1 3970 #define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */
mbed_official 441:d2c15dda23c1 3971 #define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */
mbed_official 441:d2c15dda23c1 3972 #define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */
mbed_official 441:d2c15dda23c1 3973 #define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */
mbed_official 441:d2c15dda23c1 3974 #define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */
mbed_official 441:d2c15dda23c1 3975
mbed_official 441:d2c15dda23c1 3976 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
mbed_official 441:d2c15dda23c1 3977 #define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */
mbed_official 441:d2c15dda23c1 3978 #define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */
mbed_official 441:d2c15dda23c1 3979 #define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */
mbed_official 441:d2c15dda23c1 3980 #define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */
mbed_official 441:d2c15dda23c1 3981 #define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */
mbed_official 441:d2c15dda23c1 3982
mbed_official 441:d2c15dda23c1 3983 #define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */
mbed_official 441:d2c15dda23c1 3984 #define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 3985 #define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 3986 #define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 3987 #define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 3988 #define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 3989 #define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */
mbed_official 441:d2c15dda23c1 3990 #define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */
mbed_official 441:d2c15dda23c1 3991
mbed_official 441:d2c15dda23c1 3992 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
mbed_official 441:d2c15dda23c1 3993 #define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
mbed_official 441:d2c15dda23c1 3994 #define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
mbed_official 441:d2c15dda23c1 3995 #define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
mbed_official 441:d2c15dda23c1 3996 #define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
mbed_official 441:d2c15dda23c1 3997 #define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
mbed_official 441:d2c15dda23c1 3998 #define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
mbed_official 441:d2c15dda23c1 3999 #define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
mbed_official 441:d2c15dda23c1 4000 #define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
mbed_official 441:d2c15dda23c1 4001
mbed_official 441:d2c15dda23c1 4002 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
mbed_official 441:d2c15dda23c1 4003 #define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */
mbed_official 441:d2c15dda23c1 4004
mbed_official 441:d2c15dda23c1 4005 #define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */
mbed_official 441:d2c15dda23c1 4006 #define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 4007 #define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 4008 #define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 4009 #define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 4010 #define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 4011 #define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 441:d2c15dda23c1 4012 #define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 441:d2c15dda23c1 4013 #define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 441:d2c15dda23c1 4014
mbed_official 441:d2c15dda23c1 4015 #define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */
mbed_official 441:d2c15dda23c1 4016 #define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 4017 #define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 4018 #define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 4019 #define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 4020 #define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 4021 #define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 441:d2c15dda23c1 4022 #define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 441:d2c15dda23c1 4023 #define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 441:d2c15dda23c1 4024
mbed_official 441:d2c15dda23c1 4025 /******************** Bit definition forUSB_OTG_HAINT register ********************/
mbed_official 441:d2c15dda23c1 4026 #define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */
mbed_official 441:d2c15dda23c1 4027
mbed_official 441:d2c15dda23c1 4028 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
mbed_official 441:d2c15dda23c1 4029 #define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
mbed_official 441:d2c15dda23c1 4030 #define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
mbed_official 441:d2c15dda23c1 4031 #define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
mbed_official 441:d2c15dda23c1 4032 #define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
mbed_official 441:d2c15dda23c1 4033 #define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
mbed_official 441:d2c15dda23c1 4034 #define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
mbed_official 441:d2c15dda23c1 4035 #define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
mbed_official 441:d2c15dda23c1 4036
mbed_official 441:d2c15dda23c1 4037 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
mbed_official 441:d2c15dda23c1 4038 #define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */
mbed_official 441:d2c15dda23c1 4039 #define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */
mbed_official 441:d2c15dda23c1 4040 #define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */
mbed_official 441:d2c15dda23c1 4041 #define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */
mbed_official 441:d2c15dda23c1 4042 #define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */
mbed_official 441:d2c15dda23c1 4043 #define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */
mbed_official 441:d2c15dda23c1 4044 #define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */
mbed_official 441:d2c15dda23c1 4045 #define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */
mbed_official 441:d2c15dda23c1 4046 #define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */
mbed_official 441:d2c15dda23c1 4047 #define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */
mbed_official 441:d2c15dda23c1 4048 #define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */
mbed_official 441:d2c15dda23c1 4049 #define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */
mbed_official 441:d2c15dda23c1 4050 #define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */
mbed_official 441:d2c15dda23c1 4051 #define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */
mbed_official 441:d2c15dda23c1 4052 #define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */
mbed_official 441:d2c15dda23c1 4053 #define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */
mbed_official 441:d2c15dda23c1 4054 #define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */
mbed_official 441:d2c15dda23c1 4055 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */
mbed_official 441:d2c15dda23c1 4056 #define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */
mbed_official 441:d2c15dda23c1 4057 #define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */
mbed_official 441:d2c15dda23c1 4058 #define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */
mbed_official 441:d2c15dda23c1 4059 #define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */
mbed_official 441:d2c15dda23c1 4060 #define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */
mbed_official 441:d2c15dda23c1 4061 #define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */
mbed_official 441:d2c15dda23c1 4062 #define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */
mbed_official 441:d2c15dda23c1 4063 #define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */
mbed_official 441:d2c15dda23c1 4064
mbed_official 441:d2c15dda23c1 4065 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
mbed_official 441:d2c15dda23c1 4066 #define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */
mbed_official 441:d2c15dda23c1 4067 #define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */
mbed_official 441:d2c15dda23c1 4068 #define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */
mbed_official 441:d2c15dda23c1 4069 #define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */
mbed_official 441:d2c15dda23c1 4070 #define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */
mbed_official 441:d2c15dda23c1 4071 #define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */
mbed_official 441:d2c15dda23c1 4072 #define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */
mbed_official 441:d2c15dda23c1 4073 #define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */
mbed_official 441:d2c15dda23c1 4074 #define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */
mbed_official 441:d2c15dda23c1 4075 #define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */
mbed_official 441:d2c15dda23c1 4076 #define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */
mbed_official 441:d2c15dda23c1 4077 #define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */
mbed_official 441:d2c15dda23c1 4078 #define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */
mbed_official 441:d2c15dda23c1 4079 #define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */
mbed_official 441:d2c15dda23c1 4080 #define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */
mbed_official 441:d2c15dda23c1 4081 #define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */
mbed_official 441:d2c15dda23c1 4082 #define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */
mbed_official 441:d2c15dda23c1 4083 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */
mbed_official 441:d2c15dda23c1 4084 #define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */
mbed_official 441:d2c15dda23c1 4085 #define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */
mbed_official 441:d2c15dda23c1 4086 #define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */
mbed_official 441:d2c15dda23c1 4087 #define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */
mbed_official 441:d2c15dda23c1 4088 #define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */
mbed_official 441:d2c15dda23c1 4089 #define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */
mbed_official 441:d2c15dda23c1 4090 #define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */
mbed_official 441:d2c15dda23c1 4091 #define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */
mbed_official 441:d2c15dda23c1 4092
mbed_official 441:d2c15dda23c1 4093 /******************** Bit definition forUSB_OTG_DAINT register ********************/
mbed_official 441:d2c15dda23c1 4094 #define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */
mbed_official 441:d2c15dda23c1 4095 #define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */
mbed_official 441:d2c15dda23c1 4096
mbed_official 441:d2c15dda23c1 4097 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
mbed_official 441:d2c15dda23c1 4098 #define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */
mbed_official 441:d2c15dda23c1 4099
mbed_official 441:d2c15dda23c1 4100 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
mbed_official 441:d2c15dda23c1 4101 #define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */
mbed_official 441:d2c15dda23c1 4102 #define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */
mbed_official 441:d2c15dda23c1 4103 #define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */
mbed_official 441:d2c15dda23c1 4104 #define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */
mbed_official 441:d2c15dda23c1 4105
mbed_official 441:d2c15dda23c1 4106 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
mbed_official 441:d2c15dda23c1 4107 #define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */
mbed_official 441:d2c15dda23c1 4108 #define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */
mbed_official 441:d2c15dda23c1 4109
mbed_official 441:d2c15dda23c1 4110 /******************** Bit definition for OTG register ********************/
mbed_official 441:d2c15dda23c1 4111
mbed_official 441:d2c15dda23c1 4112 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
mbed_official 441:d2c15dda23c1 4113 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 4114 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 4115 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 4116 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 4117 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
mbed_official 441:d2c15dda23c1 4118
mbed_official 441:d2c15dda23c1 4119 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
mbed_official 441:d2c15dda23c1 4120 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 4121 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 4122
mbed_official 441:d2c15dda23c1 4123 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
mbed_official 441:d2c15dda23c1 4124 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 4125 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 4126 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 4127 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 4128
mbed_official 441:d2c15dda23c1 4129 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
mbed_official 441:d2c15dda23c1 4130 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 4131 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 4132 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 4133 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 4134
mbed_official 441:d2c15dda23c1 4135 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
mbed_official 441:d2c15dda23c1 4136 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 4137 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 4138 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 4139 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 4140
mbed_official 441:d2c15dda23c1 4141 /******************** Bit definition for OTG register ********************/
mbed_official 441:d2c15dda23c1 4142
mbed_official 441:d2c15dda23c1 4143 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
mbed_official 441:d2c15dda23c1 4144 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 4145 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 4146 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 4147 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 4148 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
mbed_official 441:d2c15dda23c1 4149
mbed_official 441:d2c15dda23c1 4150 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
mbed_official 441:d2c15dda23c1 4151 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 4152 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 4153
mbed_official 441:d2c15dda23c1 4154 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
mbed_official 441:d2c15dda23c1 4155 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 4156 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 4157 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 4158 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 4159
mbed_official 441:d2c15dda23c1 4160 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
mbed_official 441:d2c15dda23c1 4161 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 4162 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 4163 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 4164 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 4165
mbed_official 441:d2c15dda23c1 4166 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
mbed_official 441:d2c15dda23c1 4167 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 4168 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 4169 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 4170 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 4171
mbed_official 441:d2c15dda23c1 4172 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
mbed_official 441:d2c15dda23c1 4173 #define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */
mbed_official 441:d2c15dda23c1 4174
mbed_official 441:d2c15dda23c1 4175 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
mbed_official 441:d2c15dda23c1 4176 #define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */
mbed_official 441:d2c15dda23c1 4177
mbed_official 441:d2c15dda23c1 4178 /******************** Bit definition for OTG register ********************/
mbed_official 441:d2c15dda23c1 4179 #define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */
mbed_official 441:d2c15dda23c1 4180 #define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */
mbed_official 441:d2c15dda23c1 4181 #define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */
mbed_official 441:d2c15dda23c1 4182 #define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */
mbed_official 441:d2c15dda23c1 4183
mbed_official 441:d2c15dda23c1 4184 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
mbed_official 441:d2c15dda23c1 4185 #define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */
mbed_official 441:d2c15dda23c1 4186
mbed_official 441:d2c15dda23c1 4187 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
mbed_official 441:d2c15dda23c1 4188 #define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */
mbed_official 441:d2c15dda23c1 4189
mbed_official 441:d2c15dda23c1 4190 #define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */
mbed_official 441:d2c15dda23c1 4191 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 4192 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 4193 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 4194 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 4195 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 4196 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 441:d2c15dda23c1 4197 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 441:d2c15dda23c1 4198 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 441:d2c15dda23c1 4199
mbed_official 441:d2c15dda23c1 4200 #define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */
mbed_official 441:d2c15dda23c1 4201 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 4202 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 4203 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 4204 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 4205 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 4206 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 441:d2c15dda23c1 4207 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 441:d2c15dda23c1 4208
mbed_official 441:d2c15dda23c1 4209 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
mbed_official 441:d2c15dda23c1 4210 #define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */
mbed_official 441:d2c15dda23c1 4211 #define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */
mbed_official 441:d2c15dda23c1 4212
mbed_official 441:d2c15dda23c1 4213 #define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */
mbed_official 441:d2c15dda23c1 4214 #define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 4215 #define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 4216 #define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 4217 #define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 4218 #define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 4219 #define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */
mbed_official 441:d2c15dda23c1 4220 #define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */
mbed_official 441:d2c15dda23c1 4221 #define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */
mbed_official 441:d2c15dda23c1 4222 #define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */
mbed_official 441:d2c15dda23c1 4223 #define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */
mbed_official 441:d2c15dda23c1 4224
mbed_official 441:d2c15dda23c1 4225 #define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */
mbed_official 441:d2c15dda23c1 4226 #define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 4227 #define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 4228 #define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 4229 #define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 4230 #define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 4231 #define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */
mbed_official 441:d2c15dda23c1 4232 #define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */
mbed_official 441:d2c15dda23c1 4233 #define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */
mbed_official 441:d2c15dda23c1 4234 #define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */
mbed_official 441:d2c15dda23c1 4235 #define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */
mbed_official 441:d2c15dda23c1 4236
mbed_official 441:d2c15dda23c1 4237 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
mbed_official 441:d2c15dda23c1 4238 #define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */
mbed_official 441:d2c15dda23c1 4239
mbed_official 441:d2c15dda23c1 4240 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
mbed_official 441:d2c15dda23c1 4241 #define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */
mbed_official 441:d2c15dda23c1 4242 #define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */
mbed_official 441:d2c15dda23c1 4243
mbed_official 441:d2c15dda23c1 4244 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
mbed_official 441:d2c15dda23c1 4245 #define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */
mbed_official 441:d2c15dda23c1 4246 #define USB_OTG_GCCFG_I2CPADEN ((uint32_t)0x00020000) /*!< Enable I2C bus connection for the external I2C PHY interface */
mbed_official 441:d2c15dda23c1 4247 #define USB_OTG_GCCFG_VBUSASEN ((uint32_t)0x00040000) /*!< Enable the VBUS sensing device */
mbed_official 441:d2c15dda23c1 4248 #define USB_OTG_GCCFG_VBUSBSEN ((uint32_t)0x00080000) /*!< Enable the VBUS sensing device */
mbed_official 441:d2c15dda23c1 4249 #define USB_OTG_GCCFG_SOFOUTEN ((uint32_t)0x00100000) /*!< SOF output enable */
mbed_official 441:d2c15dda23c1 4250 #define USB_OTG_GCCFG_NOVBUSSENS ((uint32_t)0x00200000) /*!< VBUS sensing disable option */
mbed_official 441:d2c15dda23c1 4251
mbed_official 441:d2c15dda23c1 4252 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
mbed_official 441:d2c15dda23c1 4253 #define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */
mbed_official 441:d2c15dda23c1 4254 #define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */
mbed_official 441:d2c15dda23c1 4255
mbed_official 441:d2c15dda23c1 4256 /******************** Bit definition forUSB_OTG_CID register ********************/
mbed_official 441:d2c15dda23c1 4257 #define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */
mbed_official 441:d2c15dda23c1 4258
mbed_official 441:d2c15dda23c1 4259 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
mbed_official 441:d2c15dda23c1 4260 #define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
mbed_official 441:d2c15dda23c1 4261 #define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
mbed_official 441:d2c15dda23c1 4262 #define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
mbed_official 441:d2c15dda23c1 4263 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
mbed_official 441:d2c15dda23c1 4264 #define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
mbed_official 441:d2c15dda23c1 4265 #define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
mbed_official 441:d2c15dda23c1 4266 #define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
mbed_official 441:d2c15dda23c1 4267 #define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
mbed_official 441:d2c15dda23c1 4268 #define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
mbed_official 441:d2c15dda23c1 4269
mbed_official 441:d2c15dda23c1 4270 /******************** Bit definition forUSB_OTG_HPRT register ********************/
mbed_official 441:d2c15dda23c1 4271 #define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */
mbed_official 441:d2c15dda23c1 4272 #define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */
mbed_official 441:d2c15dda23c1 4273 #define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */
mbed_official 441:d2c15dda23c1 4274 #define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */
mbed_official 441:d2c15dda23c1 4275 #define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */
mbed_official 441:d2c15dda23c1 4276 #define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */
mbed_official 441:d2c15dda23c1 4277 #define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */
mbed_official 441:d2c15dda23c1 4278 #define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */
mbed_official 441:d2c15dda23c1 4279 #define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */
mbed_official 441:d2c15dda23c1 4280
mbed_official 441:d2c15dda23c1 4281 #define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */
mbed_official 441:d2c15dda23c1 4282 #define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 4283 #define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 4284 #define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */
mbed_official 441:d2c15dda23c1 4285
mbed_official 441:d2c15dda23c1 4286 #define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */
mbed_official 441:d2c15dda23c1 4287 #define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 4288 #define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 4289 #define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 4290 #define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 4291
mbed_official 441:d2c15dda23c1 4292 #define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */
mbed_official 441:d2c15dda23c1 4293 #define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 4294 #define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 4295
mbed_official 441:d2c15dda23c1 4296 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
mbed_official 441:d2c15dda23c1 4297 #define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
mbed_official 441:d2c15dda23c1 4298 #define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
mbed_official 441:d2c15dda23c1 4299 #define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */
mbed_official 441:d2c15dda23c1 4300 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
mbed_official 441:d2c15dda23c1 4301 #define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
mbed_official 441:d2c15dda23c1 4302 #define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
mbed_official 441:d2c15dda23c1 4303 #define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */
mbed_official 441:d2c15dda23c1 4304 #define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
mbed_official 441:d2c15dda23c1 4305 #define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */
mbed_official 441:d2c15dda23c1 4306 #define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
mbed_official 441:d2c15dda23c1 4307 #define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */
mbed_official 441:d2c15dda23c1 4308
mbed_official 441:d2c15dda23c1 4309 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
mbed_official 441:d2c15dda23c1 4310 #define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */
mbed_official 441:d2c15dda23c1 4311 #define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */
mbed_official 441:d2c15dda23c1 4312
mbed_official 441:d2c15dda23c1 4313 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
mbed_official 441:d2c15dda23c1 4314 #define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
mbed_official 441:d2c15dda23c1 4315 #define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
mbed_official 441:d2c15dda23c1 4316 #define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */
mbed_official 441:d2c15dda23c1 4317 #define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
mbed_official 441:d2c15dda23c1 4318
mbed_official 441:d2c15dda23c1 4319 #define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
mbed_official 441:d2c15dda23c1 4320 #define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 4321 #define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 4322 #define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
mbed_official 441:d2c15dda23c1 4323
mbed_official 441:d2c15dda23c1 4324 #define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */
mbed_official 441:d2c15dda23c1 4325 #define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 4326 #define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 4327 #define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 4328 #define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 4329 #define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
mbed_official 441:d2c15dda23c1 4330 #define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
mbed_official 441:d2c15dda23c1 4331 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
mbed_official 441:d2c15dda23c1 4332 #define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
mbed_official 441:d2c15dda23c1 4333 #define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
mbed_official 441:d2c15dda23c1 4334 #define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
mbed_official 441:d2c15dda23c1 4335
mbed_official 441:d2c15dda23c1 4336 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
mbed_official 441:d2c15dda23c1 4337 #define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
mbed_official 441:d2c15dda23c1 4338
mbed_official 441:d2c15dda23c1 4339 #define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */
mbed_official 441:d2c15dda23c1 4340 #define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 4341 #define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 4342 #define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 4343 #define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 4344 #define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */
mbed_official 441:d2c15dda23c1 4345 #define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */
mbed_official 441:d2c15dda23c1 4346
mbed_official 441:d2c15dda23c1 4347 #define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
mbed_official 441:d2c15dda23c1 4348 #define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 4349 #define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 4350
mbed_official 441:d2c15dda23c1 4351 #define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */
mbed_official 441:d2c15dda23c1 4352 #define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 4353 #define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 4354
mbed_official 441:d2c15dda23c1 4355 #define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */
mbed_official 441:d2c15dda23c1 4356 #define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 4357 #define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 4358 #define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 4359 #define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 4360 #define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 4361 #define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */
mbed_official 441:d2c15dda23c1 4362 #define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */
mbed_official 441:d2c15dda23c1 4363 #define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */
mbed_official 441:d2c15dda23c1 4364 #define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */
mbed_official 441:d2c15dda23c1 4365 #define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */
mbed_official 441:d2c15dda23c1 4366
mbed_official 441:d2c15dda23c1 4367 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
mbed_official 441:d2c15dda23c1 4368
mbed_official 441:d2c15dda23c1 4369 #define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */
mbed_official 441:d2c15dda23c1 4370 #define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 4371 #define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 4372 #define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 4373 #define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 4374 #define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 4375 #define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 441:d2c15dda23c1 4376 #define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 441:d2c15dda23c1 4377
mbed_official 441:d2c15dda23c1 4378 #define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */
mbed_official 441:d2c15dda23c1 4379 #define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 4380 #define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 4381 #define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */
mbed_official 441:d2c15dda23c1 4382 #define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */
mbed_official 441:d2c15dda23c1 4383 #define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */
mbed_official 441:d2c15dda23c1 4384 #define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */
mbed_official 441:d2c15dda23c1 4385 #define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */
mbed_official 441:d2c15dda23c1 4386
mbed_official 441:d2c15dda23c1 4387 #define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */
mbed_official 441:d2c15dda23c1 4388 #define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 4389 #define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 4390 #define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */
mbed_official 441:d2c15dda23c1 4391 #define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */
mbed_official 441:d2c15dda23c1 4392
mbed_official 441:d2c15dda23c1 4393 /******************** Bit definition forUSB_OTG_HCINT register ********************/
mbed_official 441:d2c15dda23c1 4394 #define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */
mbed_official 441:d2c15dda23c1 4395 #define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */
mbed_official 441:d2c15dda23c1 4396 #define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
mbed_official 441:d2c15dda23c1 4397 #define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */
mbed_official 441:d2c15dda23c1 4398 #define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */
mbed_official 441:d2c15dda23c1 4399 #define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */
mbed_official 441:d2c15dda23c1 4400 #define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */
mbed_official 441:d2c15dda23c1 4401 #define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */
mbed_official 441:d2c15dda23c1 4402 #define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */
mbed_official 441:d2c15dda23c1 4403 #define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */
mbed_official 441:d2c15dda23c1 4404 #define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */
mbed_official 441:d2c15dda23c1 4405
mbed_official 441:d2c15dda23c1 4406 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
mbed_official 441:d2c15dda23c1 4407 #define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
mbed_official 441:d2c15dda23c1 4408 #define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
mbed_official 441:d2c15dda23c1 4409 #define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */
mbed_official 441:d2c15dda23c1 4410 #define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */
mbed_official 441:d2c15dda23c1 4411 #define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */
mbed_official 441:d2c15dda23c1 4412 #define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */
mbed_official 441:d2c15dda23c1 4413 #define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */
mbed_official 441:d2c15dda23c1 4414 #define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */
mbed_official 441:d2c15dda23c1 4415 #define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */
mbed_official 441:d2c15dda23c1 4416 #define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */
mbed_official 441:d2c15dda23c1 4417 #define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */
mbed_official 441:d2c15dda23c1 4418
mbed_official 441:d2c15dda23c1 4419 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
mbed_official 441:d2c15dda23c1 4420 #define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */
mbed_official 441:d2c15dda23c1 4421 #define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */
mbed_official 441:d2c15dda23c1 4422 #define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
mbed_official 441:d2c15dda23c1 4423 #define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */
mbed_official 441:d2c15dda23c1 4424 #define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */
mbed_official 441:d2c15dda23c1 4425 #define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */
mbed_official 441:d2c15dda23c1 4426 #define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */
mbed_official 441:d2c15dda23c1 4427 #define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */
mbed_official 441:d2c15dda23c1 4428 #define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */
mbed_official 441:d2c15dda23c1 4429 #define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */
mbed_official 441:d2c15dda23c1 4430 #define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */
mbed_official 441:d2c15dda23c1 4431
mbed_official 441:d2c15dda23c1 4432 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
mbed_official 441:d2c15dda23c1 4433
mbed_official 441:d2c15dda23c1 4434 #define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
mbed_official 441:d2c15dda23c1 4435 #define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
mbed_official 441:d2c15dda23c1 4436 #define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */
mbed_official 441:d2c15dda23c1 4437 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
mbed_official 441:d2c15dda23c1 4438 #define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
mbed_official 441:d2c15dda23c1 4439 #define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
mbed_official 441:d2c15dda23c1 4440 #define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */
mbed_official 441:d2c15dda23c1 4441 #define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */
mbed_official 441:d2c15dda23c1 4442 #define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 4443 #define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 4444
mbed_official 441:d2c15dda23c1 4445 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
mbed_official 441:d2c15dda23c1 4446 #define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
mbed_official 441:d2c15dda23c1 4447
mbed_official 441:d2c15dda23c1 4448 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
mbed_official 441:d2c15dda23c1 4449 #define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
mbed_official 441:d2c15dda23c1 4450
mbed_official 441:d2c15dda23c1 4451 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
mbed_official 441:d2c15dda23c1 4452 #define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space avail */
mbed_official 441:d2c15dda23c1 4453
mbed_official 441:d2c15dda23c1 4454 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
mbed_official 441:d2c15dda23c1 4455 #define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */
mbed_official 441:d2c15dda23c1 4456 #define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */
mbed_official 441:d2c15dda23c1 4457
mbed_official 441:d2c15dda23c1 4458 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
mbed_official 441:d2c15dda23c1 4459
mbed_official 441:d2c15dda23c1 4460 #define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 4461 #define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
mbed_official 441:d2c15dda23c1 4462 #define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
mbed_official 441:d2c15dda23c1 4463 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
mbed_official 441:d2c15dda23c1 4464 #define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
mbed_official 441:d2c15dda23c1 4465 #define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
mbed_official 441:d2c15dda23c1 4466 #define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 4467 #define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 4468 #define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */
mbed_official 441:d2c15dda23c1 4469 #define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
mbed_official 441:d2c15dda23c1 4470 #define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
mbed_official 441:d2c15dda23c1 4471 #define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
mbed_official 441:d2c15dda23c1 4472 #define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
mbed_official 441:d2c15dda23c1 4473 #define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
mbed_official 441:d2c15dda23c1 4474
mbed_official 441:d2c15dda23c1 4475 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
mbed_official 441:d2c15dda23c1 4476 #define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
mbed_official 441:d2c15dda23c1 4477 #define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
mbed_official 441:d2c15dda23c1 4478 #define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
mbed_official 441:d2c15dda23c1 4479 #define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
mbed_official 441:d2c15dda23c1 4480 #define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
mbed_official 441:d2c15dda23c1 4481 #define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
mbed_official 441:d2c15dda23c1 4482
mbed_official 441:d2c15dda23c1 4483 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
mbed_official 441:d2c15dda23c1 4484
mbed_official 441:d2c15dda23c1 4485 #define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
mbed_official 441:d2c15dda23c1 4486 #define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
mbed_official 441:d2c15dda23c1 4487
mbed_official 441:d2c15dda23c1 4488 #define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */
mbed_official 441:d2c15dda23c1 4489 #define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 4490 #define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 4491
mbed_official 441:d2c15dda23c1 4492 /******************** Bit definition for PCGCCTL register ********************/
mbed_official 441:d2c15dda23c1 4493 #define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */
mbed_official 441:d2c15dda23c1 4494 #define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */
mbed_official 441:d2c15dda23c1 4495 #define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 441:d2c15dda23c1 4496
mbed_official 441:d2c15dda23c1 4497 /**
mbed_official 441:d2c15dda23c1 4498 * @}
mbed_official 441:d2c15dda23c1 4499 */
mbed_official 441:d2c15dda23c1 4500
mbed_official 441:d2c15dda23c1 4501 /**
mbed_official 441:d2c15dda23c1 4502 * @}
mbed_official 441:d2c15dda23c1 4503 */
mbed_official 441:d2c15dda23c1 4504
mbed_official 441:d2c15dda23c1 4505 /** @addtogroup Exported_macros
mbed_official 441:d2c15dda23c1 4506 * @{
mbed_official 441:d2c15dda23c1 4507 */
mbed_official 441:d2c15dda23c1 4508
mbed_official 441:d2c15dda23c1 4509 /******************************* ADC Instances ********************************/
mbed_official 441:d2c15dda23c1 4510 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
mbed_official 441:d2c15dda23c1 4511
mbed_official 441:d2c15dda23c1 4512 /******************************* CRC Instances ********************************/
mbed_official 441:d2c15dda23c1 4513 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
mbed_official 441:d2c15dda23c1 4514
mbed_official 441:d2c15dda23c1 4515 /******************************** DMA Instances *******************************/
mbed_official 441:d2c15dda23c1 4516 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
mbed_official 441:d2c15dda23c1 4517 ((INSTANCE) == DMA1_Stream1) || \
mbed_official 441:d2c15dda23c1 4518 ((INSTANCE) == DMA1_Stream2) || \
mbed_official 441:d2c15dda23c1 4519 ((INSTANCE) == DMA1_Stream3) || \
mbed_official 441:d2c15dda23c1 4520 ((INSTANCE) == DMA1_Stream4) || \
mbed_official 441:d2c15dda23c1 4521 ((INSTANCE) == DMA1_Stream5) || \
mbed_official 441:d2c15dda23c1 4522 ((INSTANCE) == DMA1_Stream6) || \
mbed_official 441:d2c15dda23c1 4523 ((INSTANCE) == DMA1_Stream7) || \
mbed_official 441:d2c15dda23c1 4524 ((INSTANCE) == DMA2_Stream0) || \
mbed_official 441:d2c15dda23c1 4525 ((INSTANCE) == DMA2_Stream1) || \
mbed_official 441:d2c15dda23c1 4526 ((INSTANCE) == DMA2_Stream2) || \
mbed_official 441:d2c15dda23c1 4527 ((INSTANCE) == DMA2_Stream3) || \
mbed_official 441:d2c15dda23c1 4528 ((INSTANCE) == DMA2_Stream4) || \
mbed_official 441:d2c15dda23c1 4529 ((INSTANCE) == DMA2_Stream5) || \
mbed_official 441:d2c15dda23c1 4530 ((INSTANCE) == DMA2_Stream6) || \
mbed_official 441:d2c15dda23c1 4531 ((INSTANCE) == DMA2_Stream7))
mbed_official 441:d2c15dda23c1 4532
mbed_official 441:d2c15dda23c1 4533 /******************************* GPIO Instances *******************************/
mbed_official 441:d2c15dda23c1 4534 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
mbed_official 441:d2c15dda23c1 4535 ((INSTANCE) == GPIOB) || \
mbed_official 441:d2c15dda23c1 4536 ((INSTANCE) == GPIOC) || \
mbed_official 441:d2c15dda23c1 4537 ((INSTANCE) == GPIOD) || \
mbed_official 441:d2c15dda23c1 4538 ((INSTANCE) == GPIOE) || \
mbed_official 441:d2c15dda23c1 4539 ((INSTANCE) == GPIOH))
mbed_official 441:d2c15dda23c1 4540
mbed_official 441:d2c15dda23c1 4541 /******************************** I2C Instances *******************************/
mbed_official 441:d2c15dda23c1 4542 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
mbed_official 441:d2c15dda23c1 4543 ((INSTANCE) == I2C2) || \
mbed_official 441:d2c15dda23c1 4544 ((INSTANCE) == I2C3))
mbed_official 441:d2c15dda23c1 4545
mbed_official 441:d2c15dda23c1 4546 /******************************** I2S Instances *******************************/
mbed_official 532:fe11edbda85c 4547 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
mbed_official 441:d2c15dda23c1 4548 ((INSTANCE) == SPI2) || \
mbed_official 441:d2c15dda23c1 4549 ((INSTANCE) == SPI3) || \
mbed_official 441:d2c15dda23c1 4550 ((INSTANCE) == SPI4) || \
mbed_official 441:d2c15dda23c1 4551 ((INSTANCE) == SPI5))
mbed_official 441:d2c15dda23c1 4552
mbed_official 441:d2c15dda23c1 4553 /*************************** I2S Extended Instances ***************************/
mbed_official 532:fe11edbda85c 4554 #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
mbed_official 532:fe11edbda85c 4555 ((INSTANCE) == SPI3) || \
mbed_official 532:fe11edbda85c 4556 ((INSTANCE) == I2S2ext) || \
mbed_official 532:fe11edbda85c 4557 ((INSTANCE) == I2S3ext))
mbed_official 441:d2c15dda23c1 4558
mbed_official 441:d2c15dda23c1 4559
mbed_official 441:d2c15dda23c1 4560 /****************************** RTC Instances *********************************/
mbed_official 441:d2c15dda23c1 4561 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
mbed_official 441:d2c15dda23c1 4562
mbed_official 441:d2c15dda23c1 4563 /******************************** SPI Instances *******************************/
mbed_official 441:d2c15dda23c1 4564 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
mbed_official 441:d2c15dda23c1 4565 ((INSTANCE) == SPI2) || \
mbed_official 441:d2c15dda23c1 4566 ((INSTANCE) == SPI3) || \
mbed_official 441:d2c15dda23c1 4567 ((INSTANCE) == SPI4) || \
mbed_official 441:d2c15dda23c1 4568 ((INSTANCE) == SPI5))
mbed_official 441:d2c15dda23c1 4569 /*************************** SPI Extended Instances ***************************/
mbed_official 441:d2c15dda23c1 4570 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
mbed_official 441:d2c15dda23c1 4571 ((INSTANCE) == SPI2) || \
mbed_official 441:d2c15dda23c1 4572 ((INSTANCE) == SPI3) || \
mbed_official 441:d2c15dda23c1 4573 ((INSTANCE) == SPI4) || \
mbed_official 441:d2c15dda23c1 4574 ((INSTANCE) == SPI5) || \
mbed_official 441:d2c15dda23c1 4575 ((INSTANCE) == I2S2ext) || \
mbed_official 441:d2c15dda23c1 4576 ((INSTANCE) == I2S3ext))
mbed_official 441:d2c15dda23c1 4577
mbed_official 441:d2c15dda23c1 4578 /****************** TIM Instances : All supported instances *******************/
mbed_official 441:d2c15dda23c1 4579 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 441:d2c15dda23c1 4580 ((INSTANCE) == TIM2) || \
mbed_official 441:d2c15dda23c1 4581 ((INSTANCE) == TIM3) || \
mbed_official 441:d2c15dda23c1 4582 ((INSTANCE) == TIM4) || \
mbed_official 441:d2c15dda23c1 4583 ((INSTANCE) == TIM5) || \
mbed_official 441:d2c15dda23c1 4584 ((INSTANCE) == TIM9) || \
mbed_official 441:d2c15dda23c1 4585 ((INSTANCE) == TIM10) || \
mbed_official 441:d2c15dda23c1 4586 ((INSTANCE) == TIM11))
mbed_official 441:d2c15dda23c1 4587
mbed_official 441:d2c15dda23c1 4588 /************* TIM Instances : at least 1 capture/compare channel *************/
mbed_official 441:d2c15dda23c1 4589 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 441:d2c15dda23c1 4590 ((INSTANCE) == TIM2) || \
mbed_official 441:d2c15dda23c1 4591 ((INSTANCE) == TIM3) || \
mbed_official 441:d2c15dda23c1 4592 ((INSTANCE) == TIM4) || \
mbed_official 441:d2c15dda23c1 4593 ((INSTANCE) == TIM5) || \
mbed_official 441:d2c15dda23c1 4594 ((INSTANCE) == TIM9) || \
mbed_official 441:d2c15dda23c1 4595 ((INSTANCE) == TIM10) || \
mbed_official 441:d2c15dda23c1 4596 ((INSTANCE) == TIM11))
mbed_official 441:d2c15dda23c1 4597
mbed_official 441:d2c15dda23c1 4598 /************ TIM Instances : at least 2 capture/compare channels *************/
mbed_official 441:d2c15dda23c1 4599 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 441:d2c15dda23c1 4600 ((INSTANCE) == TIM2) || \
mbed_official 441:d2c15dda23c1 4601 ((INSTANCE) == TIM3) || \
mbed_official 441:d2c15dda23c1 4602 ((INSTANCE) == TIM4) || \
mbed_official 441:d2c15dda23c1 4603 ((INSTANCE) == TIM5) || \
mbed_official 441:d2c15dda23c1 4604 ((INSTANCE) == TIM9))
mbed_official 441:d2c15dda23c1 4605
mbed_official 441:d2c15dda23c1 4606 /************ TIM Instances : at least 3 capture/compare channels *************/
mbed_official 441:d2c15dda23c1 4607 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 441:d2c15dda23c1 4608 ((INSTANCE) == TIM2) || \
mbed_official 441:d2c15dda23c1 4609 ((INSTANCE) == TIM3) || \
mbed_official 441:d2c15dda23c1 4610 ((INSTANCE) == TIM4) || \
mbed_official 441:d2c15dda23c1 4611 ((INSTANCE) == TIM5))
mbed_official 441:d2c15dda23c1 4612
mbed_official 441:d2c15dda23c1 4613 /************ TIM Instances : at least 4 capture/compare channels *************/
mbed_official 441:d2c15dda23c1 4614 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 441:d2c15dda23c1 4615 ((INSTANCE) == TIM2) || \
mbed_official 441:d2c15dda23c1 4616 ((INSTANCE) == TIM3) || \
mbed_official 441:d2c15dda23c1 4617 ((INSTANCE) == TIM4) || \
mbed_official 441:d2c15dda23c1 4618 ((INSTANCE) == TIM5))
mbed_official 441:d2c15dda23c1 4619
mbed_official 441:d2c15dda23c1 4620 /******************** TIM Instances : Advanced-control timers *****************/
mbed_official 441:d2c15dda23c1 4621 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
mbed_official 441:d2c15dda23c1 4622
mbed_official 441:d2c15dda23c1 4623 /******************* TIM Instances : Timer input XOR function *****************/
mbed_official 441:d2c15dda23c1 4624 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 441:d2c15dda23c1 4625 ((INSTANCE) == TIM2) || \
mbed_official 441:d2c15dda23c1 4626 ((INSTANCE) == TIM3) || \
mbed_official 441:d2c15dda23c1 4627 ((INSTANCE) == TIM4) || \
mbed_official 441:d2c15dda23c1 4628 ((INSTANCE) == TIM5))
mbed_official 441:d2c15dda23c1 4629
mbed_official 441:d2c15dda23c1 4630 /****************** TIM Instances : DMA requests generation (UDE) *************/
mbed_official 441:d2c15dda23c1 4631 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 441:d2c15dda23c1 4632 ((INSTANCE) == TIM2) || \
mbed_official 441:d2c15dda23c1 4633 ((INSTANCE) == TIM3) || \
mbed_official 441:d2c15dda23c1 4634 ((INSTANCE) == TIM4) || \
mbed_official 441:d2c15dda23c1 4635 ((INSTANCE) == TIM5))
mbed_official 441:d2c15dda23c1 4636
mbed_official 441:d2c15dda23c1 4637 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
mbed_official 441:d2c15dda23c1 4638 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 441:d2c15dda23c1 4639 ((INSTANCE) == TIM2) || \
mbed_official 441:d2c15dda23c1 4640 ((INSTANCE) == TIM3) || \
mbed_official 441:d2c15dda23c1 4641 ((INSTANCE) == TIM4) || \
mbed_official 441:d2c15dda23c1 4642 ((INSTANCE) == TIM5))
mbed_official 441:d2c15dda23c1 4643
mbed_official 441:d2c15dda23c1 4644 /************ TIM Instances : DMA requests generation (COMDE) *****************/
mbed_official 441:d2c15dda23c1 4645 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 441:d2c15dda23c1 4646 ((INSTANCE) == TIM2) || \
mbed_official 441:d2c15dda23c1 4647 ((INSTANCE) == TIM3) || \
mbed_official 441:d2c15dda23c1 4648 ((INSTANCE) == TIM4) || \
mbed_official 441:d2c15dda23c1 4649 ((INSTANCE) == TIM5))
mbed_official 441:d2c15dda23c1 4650
mbed_official 441:d2c15dda23c1 4651 /******************** TIM Instances : DMA burst feature ***********************/
mbed_official 441:d2c15dda23c1 4652 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 441:d2c15dda23c1 4653 ((INSTANCE) == TIM2) || \
mbed_official 441:d2c15dda23c1 4654 ((INSTANCE) == TIM3) || \
mbed_official 441:d2c15dda23c1 4655 ((INSTANCE) == TIM4) || \
mbed_official 441:d2c15dda23c1 4656 ((INSTANCE) == TIM5))
mbed_official 441:d2c15dda23c1 4657
mbed_official 441:d2c15dda23c1 4658 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
mbed_official 441:d2c15dda23c1 4659 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 441:d2c15dda23c1 4660 ((INSTANCE) == TIM2) || \
mbed_official 441:d2c15dda23c1 4661 ((INSTANCE) == TIM3) || \
mbed_official 441:d2c15dda23c1 4662 ((INSTANCE) == TIM4) || \
mbed_official 441:d2c15dda23c1 4663 ((INSTANCE) == TIM5) || \
mbed_official 441:d2c15dda23c1 4664 ((INSTANCE) == TIM9))
mbed_official 441:d2c15dda23c1 4665
mbed_official 441:d2c15dda23c1 4666 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
mbed_official 441:d2c15dda23c1 4667 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 441:d2c15dda23c1 4668 ((INSTANCE) == TIM2) || \
mbed_official 441:d2c15dda23c1 4669 ((INSTANCE) == TIM3) || \
mbed_official 441:d2c15dda23c1 4670 ((INSTANCE) == TIM4) || \
mbed_official 441:d2c15dda23c1 4671 ((INSTANCE) == TIM5) || \
mbed_official 441:d2c15dda23c1 4672 ((INSTANCE) == TIM9))
mbed_official 441:d2c15dda23c1 4673
mbed_official 441:d2c15dda23c1 4674 /********************** TIM Instances : 32 bit Counter ************************/
mbed_official 441:d2c15dda23c1 4675 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
mbed_official 441:d2c15dda23c1 4676 ((INSTANCE) == TIM5))
mbed_official 441:d2c15dda23c1 4677
mbed_official 441:d2c15dda23c1 4678 /***************** TIM Instances : external trigger input availabe ************/
mbed_official 441:d2c15dda23c1 4679 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 441:d2c15dda23c1 4680 ((INSTANCE) == TIM2) || \
mbed_official 441:d2c15dda23c1 4681 ((INSTANCE) == TIM3) || \
mbed_official 441:d2c15dda23c1 4682 ((INSTANCE) == TIM4) || \
mbed_official 441:d2c15dda23c1 4683 ((INSTANCE) == TIM5))
mbed_official 441:d2c15dda23c1 4684
mbed_official 441:d2c15dda23c1 4685 /****************** TIM Instances : remapping capability **********************/
mbed_official 441:d2c15dda23c1 4686 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 441:d2c15dda23c1 4687 ((INSTANCE) == TIM5) || \
mbed_official 441:d2c15dda23c1 4688 ((INSTANCE) == TIM11))
mbed_official 441:d2c15dda23c1 4689
mbed_official 441:d2c15dda23c1 4690 /******************* TIM Instances : output(s) available **********************/
mbed_official 441:d2c15dda23c1 4691 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 441:d2c15dda23c1 4692 ((((INSTANCE) == TIM1) && \
mbed_official 441:d2c15dda23c1 4693 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 441:d2c15dda23c1 4694 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 441:d2c15dda23c1 4695 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 441:d2c15dda23c1 4696 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 441:d2c15dda23c1 4697 || \
mbed_official 441:d2c15dda23c1 4698 (((INSTANCE) == TIM2) && \
mbed_official 441:d2c15dda23c1 4699 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 441:d2c15dda23c1 4700 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 441:d2c15dda23c1 4701 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 441:d2c15dda23c1 4702 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 441:d2c15dda23c1 4703 || \
mbed_official 441:d2c15dda23c1 4704 (((INSTANCE) == TIM3) && \
mbed_official 441:d2c15dda23c1 4705 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 441:d2c15dda23c1 4706 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 441:d2c15dda23c1 4707 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 441:d2c15dda23c1 4708 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 441:d2c15dda23c1 4709 || \
mbed_official 441:d2c15dda23c1 4710 (((INSTANCE) == TIM4) && \
mbed_official 441:d2c15dda23c1 4711 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 441:d2c15dda23c1 4712 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 441:d2c15dda23c1 4713 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 441:d2c15dda23c1 4714 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 441:d2c15dda23c1 4715 || \
mbed_official 441:d2c15dda23c1 4716 (((INSTANCE) == TIM5) && \
mbed_official 441:d2c15dda23c1 4717 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 441:d2c15dda23c1 4718 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 441:d2c15dda23c1 4719 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 441:d2c15dda23c1 4720 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 441:d2c15dda23c1 4721 || \
mbed_official 441:d2c15dda23c1 4722 (((INSTANCE) == TIM9) && \
mbed_official 441:d2c15dda23c1 4723 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 441:d2c15dda23c1 4724 ((CHANNEL) == TIM_CHANNEL_2))) \
mbed_official 441:d2c15dda23c1 4725 || \
mbed_official 441:d2c15dda23c1 4726 (((INSTANCE) == TIM10) && \
mbed_official 441:d2c15dda23c1 4727 (((CHANNEL) == TIM_CHANNEL_1))) \
mbed_official 441:d2c15dda23c1 4728 || \
mbed_official 441:d2c15dda23c1 4729 (((INSTANCE) == TIM11) && \
mbed_official 441:d2c15dda23c1 4730 (((CHANNEL) == TIM_CHANNEL_1))))
mbed_official 441:d2c15dda23c1 4731
mbed_official 441:d2c15dda23c1 4732 /************ TIM Instances : complementary output(s) available ***************/
mbed_official 441:d2c15dda23c1 4733 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 441:d2c15dda23c1 4734 ((((INSTANCE) == TIM1) && \
mbed_official 441:d2c15dda23c1 4735 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 441:d2c15dda23c1 4736 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 441:d2c15dda23c1 4737 ((CHANNEL) == TIM_CHANNEL_3))))
mbed_official 441:d2c15dda23c1 4738
mbed_official 441:d2c15dda23c1 4739 /******************** USART Instances : Synchronous mode **********************/
mbed_official 441:d2c15dda23c1 4740 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 441:d2c15dda23c1 4741 ((INSTANCE) == USART2) || \
mbed_official 441:d2c15dda23c1 4742 ((INSTANCE) == USART6))
mbed_official 441:d2c15dda23c1 4743
mbed_official 441:d2c15dda23c1 4744 /******************** UART Instances : Asynchronous mode **********************/
mbed_official 441:d2c15dda23c1 4745 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 441:d2c15dda23c1 4746 ((INSTANCE) == USART2) || \
mbed_official 441:d2c15dda23c1 4747 ((INSTANCE) == USART6))
mbed_official 441:d2c15dda23c1 4748
mbed_official 441:d2c15dda23c1 4749 /****************** UART Instances : Hardware Flow control ********************/
mbed_official 441:d2c15dda23c1 4750 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 441:d2c15dda23c1 4751 ((INSTANCE) == USART2) || \
mbed_official 441:d2c15dda23c1 4752 ((INSTANCE) == USART6))
mbed_official 441:d2c15dda23c1 4753
mbed_official 441:d2c15dda23c1 4754 /********************* UART Instances : Smard card mode ***********************/
mbed_official 441:d2c15dda23c1 4755 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 441:d2c15dda23c1 4756 ((INSTANCE) == USART2) || \
mbed_official 441:d2c15dda23c1 4757 ((INSTANCE) == USART6))
mbed_official 441:d2c15dda23c1 4758
mbed_official 441:d2c15dda23c1 4759 /*********************** UART Instances : IRDA mode ***************************/
mbed_official 441:d2c15dda23c1 4760 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 441:d2c15dda23c1 4761 ((INSTANCE) == USART2) || \
mbed_official 441:d2c15dda23c1 4762 ((INSTANCE) == USART6))
mbed_official 441:d2c15dda23c1 4763
mbed_official 441:d2c15dda23c1 4764 /****************************** IWDG Instances ********************************/
mbed_official 441:d2c15dda23c1 4765 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
mbed_official 441:d2c15dda23c1 4766
mbed_official 441:d2c15dda23c1 4767 /****************************** WWDG Instances ********************************/
mbed_official 441:d2c15dda23c1 4768 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
mbed_official 441:d2c15dda23c1 4769
mbed_official 532:fe11edbda85c 4770 /****************************** SDIO Instances ********************************/
mbed_official 532:fe11edbda85c 4771 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
mbed_official 532:fe11edbda85c 4772
mbed_official 532:fe11edbda85c 4773 /****************************** USB Exported Constants ************************/
mbed_official 532:fe11edbda85c 4774 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
mbed_official 532:fe11edbda85c 4775 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
mbed_official 532:fe11edbda85c 4776 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
mbed_official 532:fe11edbda85c 4777 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
mbed_official 441:d2c15dda23c1 4778
mbed_official 441:d2c15dda23c1 4779 /**
mbed_official 441:d2c15dda23c1 4780 * @}
mbed_official 441:d2c15dda23c1 4781 */
mbed_official 441:d2c15dda23c1 4782
mbed_official 441:d2c15dda23c1 4783 /**
mbed_official 441:d2c15dda23c1 4784 * @}
mbed_official 441:d2c15dda23c1 4785 */
mbed_official 441:d2c15dda23c1 4786
mbed_official 441:d2c15dda23c1 4787 /**
mbed_official 441:d2c15dda23c1 4788 * @}
mbed_official 441:d2c15dda23c1 4789 */
mbed_official 441:d2c15dda23c1 4790
mbed_official 441:d2c15dda23c1 4791 #ifdef __cplusplus
mbed_official 441:d2c15dda23c1 4792 }
mbed_official 441:d2c15dda23c1 4793 #endif /* __cplusplus */
mbed_official 441:d2c15dda23c1 4794
mbed_official 441:d2c15dda23c1 4795 #endif /* __STM32F411xE_H */
mbed_official 441:d2c15dda23c1 4796
mbed_official 441:d2c15dda23c1 4797
mbed_official 441:d2c15dda23c1 4798
mbed_official 441:d2c15dda23c1 4799 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/