DMA_LLI_TEST - LINKED LIST TEST on mbed

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xeye_ atsu / Mbed 2 deprecated DMA_LLI_TEST

LINKED LIST TEST on mbed

I2S_Example/lpc17xx_gpdma.h@0:e8bfffbb3ab6, 2011-02-26 (annotated)

Committer:: lynxeyed_atsu
Date:: Sat Feb 26 03:55:12 2011 +0000
Revision:: 0:e8bfffbb3ab6

Who changed what in which revision?

User	Revision	Line number	New contents of line
lynxeyed_atsu	0:e8bfffbb3ab6	1	/*********************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	2	* @file lpc17xx_gpdma.h
lynxeyed_atsu	0:e8bfffbb3ab6	3	* @brief Contains all macro definitions and function prototypes
lynxeyed_atsu	0:e8bfffbb3ab6	4	* support for GPDMA firmware library on LPC17xx
lynxeyed_atsu	0:e8bfffbb3ab6	5	* @version 2.0
lynxeyed_atsu	0:e8bfffbb3ab6	6	* @date 21. May. 2010
lynxeyed_atsu	0:e8bfffbb3ab6	7	* @author NXP MCU SW Application Team
lynxeyed_atsu	0:e8bfffbb3ab6	8	**************************************************************************
lynxeyed_atsu	0:e8bfffbb3ab6	9	* Software that is described herein is for illustrative purposes only
lynxeyed_atsu	0:e8bfffbb3ab6	10	* which provides customers with programming information regarding the
lynxeyed_atsu	0:e8bfffbb3ab6	11	* products. This software is supplied "AS IS" without any warranties.
lynxeyed_atsu	0:e8bfffbb3ab6	12	* NXP Semiconductors assumes no responsibility or liability for the
lynxeyed_atsu	0:e8bfffbb3ab6	13	* use of the software, conveys no license or title under any patent,
lynxeyed_atsu	0:e8bfffbb3ab6	14	* copyright, or mask work right to the product. NXP Semiconductors
lynxeyed_atsu	0:e8bfffbb3ab6	15	* reserves the right to make changes in the software without
lynxeyed_atsu	0:e8bfffbb3ab6	16	* notification. NXP Semiconductors also make no representation or
lynxeyed_atsu	0:e8bfffbb3ab6	17	* warranty that such application will be suitable for the specified
lynxeyed_atsu	0:e8bfffbb3ab6	18	* use without further testing or modification.
lynxeyed_atsu	0:e8bfffbb3ab6	19	**************************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	20
lynxeyed_atsu	0:e8bfffbb3ab6	21	/* Peripheral group ----------------------------------------------------------- */
lynxeyed_atsu	0:e8bfffbb3ab6	22	/** @defgroup GPDMA GPDMA
lynxeyed_atsu	0:e8bfffbb3ab6	23	* @ingroup LPC1700CMSIS_FwLib_Drivers
lynxeyed_atsu	0:e8bfffbb3ab6	24	* @{
lynxeyed_atsu	0:e8bfffbb3ab6	25	*/
lynxeyed_atsu	0:e8bfffbb3ab6	26
lynxeyed_atsu	0:e8bfffbb3ab6	27	#ifndef LPC17XX_GPDMA_H_
lynxeyed_atsu	0:e8bfffbb3ab6	28	#define LPC17XX_GPDMA_H_
lynxeyed_atsu	0:e8bfffbb3ab6	29
lynxeyed_atsu	0:e8bfffbb3ab6	30	/* Includes ------------------------------------------------------------------- */
lynxeyed_atsu	0:e8bfffbb3ab6	31	#include "LPC17xx.h"
lynxeyed_atsu	0:e8bfffbb3ab6	32	#include "lpc_types.h"
lynxeyed_atsu	0:e8bfffbb3ab6	33
lynxeyed_atsu	0:e8bfffbb3ab6	34
lynxeyed_atsu	0:e8bfffbb3ab6	35	#ifdef __cplusplus
lynxeyed_atsu	0:e8bfffbb3ab6	36	extern "C"
lynxeyed_atsu	0:e8bfffbb3ab6	37	{
lynxeyed_atsu	0:e8bfffbb3ab6	38	#endif
lynxeyed_atsu	0:e8bfffbb3ab6	39
lynxeyed_atsu	0:e8bfffbb3ab6	40	/* Public Macros -------------------------------------------------------------- */
lynxeyed_atsu	0:e8bfffbb3ab6	41	/** @defgroup GPDMA_Public_Macros GPDMA Public Macros
lynxeyed_atsu	0:e8bfffbb3ab6	42	* @{
lynxeyed_atsu	0:e8bfffbb3ab6	43	*/
lynxeyed_atsu	0:e8bfffbb3ab6	44
lynxeyed_atsu	0:e8bfffbb3ab6	45	/** DMA Connection number definitions */
lynxeyed_atsu	0:e8bfffbb3ab6	46	#define GPDMA_CONN_SSP0_Tx ((0UL)) /*< SSP0 Tx /
lynxeyed_atsu	0:e8bfffbb3ab6	47	#define GPDMA_CONN_SSP0_Rx ((1UL)) /*< SSP0 Rx /
lynxeyed_atsu	0:e8bfffbb3ab6	48	#define GPDMA_CONN_SSP1_Tx ((2UL)) /*< SSP1 Tx /
lynxeyed_atsu	0:e8bfffbb3ab6	49	#define GPDMA_CONN_SSP1_Rx ((3UL)) /*< SSP1 Rx /
lynxeyed_atsu	0:e8bfffbb3ab6	50	#define GPDMA_CONN_ADC ((4UL)) /*< ADC /
lynxeyed_atsu	0:e8bfffbb3ab6	51	#define GPDMA_CONN_I2S_Channel_0 ((5UL)) /*< I2S channel 0 /
lynxeyed_atsu	0:e8bfffbb3ab6	52	#define GPDMA_CONN_I2S_Channel_1 ((6UL)) /*< I2S channel 1 /
lynxeyed_atsu	0:e8bfffbb3ab6	53	#define GPDMA_CONN_DAC ((7UL)) /*< DAC /
lynxeyed_atsu	0:e8bfffbb3ab6	54	#define GPDMA_CONN_UART0_Tx ((8UL)) /*< UART0 Tx /
lynxeyed_atsu	0:e8bfffbb3ab6	55	#define GPDMA_CONN_UART0_Rx ((9UL)) /*< UART0 Rx /
lynxeyed_atsu	0:e8bfffbb3ab6	56	#define GPDMA_CONN_UART1_Tx ((10UL)) /*< UART1 Tx /
lynxeyed_atsu	0:e8bfffbb3ab6	57	#define GPDMA_CONN_UART1_Rx ((11UL)) /*< UART1 Rx /
lynxeyed_atsu	0:e8bfffbb3ab6	58	#define GPDMA_CONN_UART2_Tx ((12UL)) /*< UART2 Tx /
lynxeyed_atsu	0:e8bfffbb3ab6	59	#define GPDMA_CONN_UART2_Rx ((13UL)) /*< UART2 Rx /
lynxeyed_atsu	0:e8bfffbb3ab6	60	#define GPDMA_CONN_UART3_Tx ((14UL)) /*< UART3 Tx /
lynxeyed_atsu	0:e8bfffbb3ab6	61	#define GPDMA_CONN_UART3_Rx ((15UL)) /*< UART3 Rx /
lynxeyed_atsu	0:e8bfffbb3ab6	62	#define GPDMA_CONN_MAT0_0 ((16UL)) /*< MAT0.0 /
lynxeyed_atsu	0:e8bfffbb3ab6	63	#define GPDMA_CONN_MAT0_1 ((17UL)) /*< MAT0.1 /
lynxeyed_atsu	0:e8bfffbb3ab6	64	#define GPDMA_CONN_MAT1_0 ((18UL)) /*< MAT1.0 /
lynxeyed_atsu	0:e8bfffbb3ab6	65	#define GPDMA_CONN_MAT1_1 ((19UL)) /*< MAT1.1 /
lynxeyed_atsu	0:e8bfffbb3ab6	66	#define GPDMA_CONN_MAT2_0 ((20UL)) /*< MAT2.0 /
lynxeyed_atsu	0:e8bfffbb3ab6	67	#define GPDMA_CONN_MAT2_1 ((21UL)) /*< MAT2.1 /
lynxeyed_atsu	0:e8bfffbb3ab6	68	#define GPDMA_CONN_MAT3_0 ((22UL)) /*< MAT3.0 /
lynxeyed_atsu	0:e8bfffbb3ab6	69	#define GPDMA_CONN_MAT3_1 ((23UL)) /*< MAT3.1 /
lynxeyed_atsu	0:e8bfffbb3ab6	70
lynxeyed_atsu	0:e8bfffbb3ab6	71	/** GPDMA Transfer type definitions */
lynxeyed_atsu	0:e8bfffbb3ab6	72	#define GPDMA_TRANSFERTYPE_M2M ((0UL)) /*< Memory to memory - DMA control /
lynxeyed_atsu	0:e8bfffbb3ab6	73	#define GPDMA_TRANSFERTYPE_M2P ((1UL)) /*< Memory to peripheral - DMA control /
lynxeyed_atsu	0:e8bfffbb3ab6	74	#define GPDMA_TRANSFERTYPE_P2M ((2UL)) /*< Peripheral to memory - DMA control /
lynxeyed_atsu	0:e8bfffbb3ab6	75	#define GPDMA_TRANSFERTYPE_P2P ((3UL)) /*< Source peripheral to destination peripheral - DMA control /
lynxeyed_atsu	0:e8bfffbb3ab6	76
lynxeyed_atsu	0:e8bfffbb3ab6	77	/** Burst size in Source and Destination definitions */
lynxeyed_atsu	0:e8bfffbb3ab6	78	#define GPDMA_BSIZE_1 ((0UL)) /*< Burst size = 1 /
lynxeyed_atsu	0:e8bfffbb3ab6	79	#define GPDMA_BSIZE_4 ((1UL)) /*< Burst size = 4 /
lynxeyed_atsu	0:e8bfffbb3ab6	80	#define GPDMA_BSIZE_8 ((2UL)) /*< Burst size = 8 /
lynxeyed_atsu	0:e8bfffbb3ab6	81	#define GPDMA_BSIZE_16 ((3UL)) /*< Burst size = 16 /
lynxeyed_atsu	0:e8bfffbb3ab6	82	#define GPDMA_BSIZE_32 ((4UL)) /*< Burst size = 32 /
lynxeyed_atsu	0:e8bfffbb3ab6	83	#define GPDMA_BSIZE_64 ((5UL)) /*< Burst size = 64 /
lynxeyed_atsu	0:e8bfffbb3ab6	84	#define GPDMA_BSIZE_128 ((6UL)) /*< Burst size = 128 /
lynxeyed_atsu	0:e8bfffbb3ab6	85	#define GPDMA_BSIZE_256 ((7UL)) /*< Burst size = 256 /
lynxeyed_atsu	0:e8bfffbb3ab6	86
lynxeyed_atsu	0:e8bfffbb3ab6	87	/** Width in Source transfer width and Destination transfer width definitions */
lynxeyed_atsu	0:e8bfffbb3ab6	88	#define GPDMA_WIDTH_BYTE ((0UL)) /*< Width = 1 byte /
lynxeyed_atsu	0:e8bfffbb3ab6	89	#define GPDMA_WIDTH_HALFWORD ((1UL)) /*< Width = 2 bytes /
lynxeyed_atsu	0:e8bfffbb3ab6	90	#define GPDMA_WIDTH_WORD ((2UL)) /*< Width = 4 bytes /
lynxeyed_atsu	0:e8bfffbb3ab6	91
lynxeyed_atsu	0:e8bfffbb3ab6	92	/** DMA Request Select Mode definitions */
lynxeyed_atsu	0:e8bfffbb3ab6	93	#define GPDMA_REQSEL_UART ((0UL)) /*< UART TX/RX is selected /
lynxeyed_atsu	0:e8bfffbb3ab6	94	#define GPDMA_REQSEL_TIMER ((1UL)) /*< Timer match is selected /
lynxeyed_atsu	0:e8bfffbb3ab6	95
lynxeyed_atsu	0:e8bfffbb3ab6	96	/**
lynxeyed_atsu	0:e8bfffbb3ab6	97	* @}
lynxeyed_atsu	0:e8bfffbb3ab6	98	*/
lynxeyed_atsu	0:e8bfffbb3ab6	99
lynxeyed_atsu	0:e8bfffbb3ab6	100
lynxeyed_atsu	0:e8bfffbb3ab6	101	/* Private Macros ------------------------------------------------------------- */
lynxeyed_atsu	0:e8bfffbb3ab6	102	/** @defgroup GPDMA_Private_Macros GPDMA Private Macros
lynxeyed_atsu	0:e8bfffbb3ab6	103	* @{
lynxeyed_atsu	0:e8bfffbb3ab6	104	*/
lynxeyed_atsu	0:e8bfffbb3ab6	105
lynxeyed_atsu	0:e8bfffbb3ab6	106	/* --------------------- BIT DEFINITIONS -------------------------------------- */
lynxeyed_atsu	0:e8bfffbb3ab6	107	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	108	* Macro defines for DMA Interrupt Status register
lynxeyed_atsu	0:e8bfffbb3ab6	109	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	110	#define GPDMA_DMACIntStat_Ch(n) (((1UL<<n)&0xFF))
lynxeyed_atsu	0:e8bfffbb3ab6	111	#define GPDMA_DMACIntStat_BITMASK ((0xFF))
lynxeyed_atsu	0:e8bfffbb3ab6	112
lynxeyed_atsu	0:e8bfffbb3ab6	113	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	114	* Macro defines for DMA Interrupt Terminal Count Request Status register
lynxeyed_atsu	0:e8bfffbb3ab6	115	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	116	#define GPDMA_DMACIntTCStat_Ch(n) (((1UL<<n)&0xFF))
lynxeyed_atsu	0:e8bfffbb3ab6	117	#define GPDMA_DMACIntTCStat_BITMASK ((0xFF))
lynxeyed_atsu	0:e8bfffbb3ab6	118
lynxeyed_atsu	0:e8bfffbb3ab6	119	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	120	* Macro defines for DMA Interrupt Terminal Count Request Clear register
lynxeyed_atsu	0:e8bfffbb3ab6	121	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	122	#define GPDMA_DMACIntTCClear_Ch(n) (((1UL<<n)&0xFF))
lynxeyed_atsu	0:e8bfffbb3ab6	123	#define GPDMA_DMACIntTCClear_BITMASK ((0xFF))
lynxeyed_atsu	0:e8bfffbb3ab6	124
lynxeyed_atsu	0:e8bfffbb3ab6	125	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	126	* Macro defines for DMA Interrupt Error Status register
lynxeyed_atsu	0:e8bfffbb3ab6	127	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	128	#define GPDMA_DMACIntErrStat_Ch(n) (((1UL<<n)&0xFF))
lynxeyed_atsu	0:e8bfffbb3ab6	129	#define GPDMA_DMACIntErrStat_BITMASK ((0xFF))
lynxeyed_atsu	0:e8bfffbb3ab6	130
lynxeyed_atsu	0:e8bfffbb3ab6	131	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	132	* Macro defines for DMA Interrupt Error Clear register
lynxeyed_atsu	0:e8bfffbb3ab6	133	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	134	#define GPDMA_DMACIntErrClr_Ch(n) (((1UL<<n)&0xFF))
lynxeyed_atsu	0:e8bfffbb3ab6	135	#define GPDMA_DMACIntErrClr_BITMASK ((0xFF))
lynxeyed_atsu	0:e8bfffbb3ab6	136
lynxeyed_atsu	0:e8bfffbb3ab6	137	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	138	* Macro defines for DMA Raw Interrupt Terminal Count Status register
lynxeyed_atsu	0:e8bfffbb3ab6	139	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	140	#define GPDMA_DMACRawIntTCStat_Ch(n) (((1UL<<n)&0xFF))
lynxeyed_atsu	0:e8bfffbb3ab6	141	#define GPDMA_DMACRawIntTCStat_BITMASK ((0xFF))
lynxeyed_atsu	0:e8bfffbb3ab6	142
lynxeyed_atsu	0:e8bfffbb3ab6	143	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	144	* Macro defines for DMA Raw Error Interrupt Status register
lynxeyed_atsu	0:e8bfffbb3ab6	145	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	146	#define GPDMA_DMACRawIntErrStat_Ch(n) (((1UL<<n)&0xFF))
lynxeyed_atsu	0:e8bfffbb3ab6	147	#define GPDMA_DMACRawIntErrStat_BITMASK ((0xFF))
lynxeyed_atsu	0:e8bfffbb3ab6	148
lynxeyed_atsu	0:e8bfffbb3ab6	149	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	150	* Macro defines for DMA Enabled Channel register
lynxeyed_atsu	0:e8bfffbb3ab6	151	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	152	#define GPDMA_DMACEnbldChns_Ch(n) (((1UL<<n)&0xFF))
lynxeyed_atsu	0:e8bfffbb3ab6	153	#define GPDMA_DMACEnbldChns_BITMASK ((0xFF))
lynxeyed_atsu	0:e8bfffbb3ab6	154
lynxeyed_atsu	0:e8bfffbb3ab6	155	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	156	* Macro defines for DMA Software Burst Request register
lynxeyed_atsu	0:e8bfffbb3ab6	157	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	158	#define GPDMA_DMACSoftBReq_Src(n) (((1UL<<n)&0xFFFF))
lynxeyed_atsu	0:e8bfffbb3ab6	159	#define GPDMA_DMACSoftBReq_BITMASK ((0xFFFF))
lynxeyed_atsu	0:e8bfffbb3ab6	160
lynxeyed_atsu	0:e8bfffbb3ab6	161	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	162	* Macro defines for DMA Software Single Request register
lynxeyed_atsu	0:e8bfffbb3ab6	163	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	164	#define GPDMA_DMACSoftSReq_Src(n) (((1UL<<n)&0xFFFF))
lynxeyed_atsu	0:e8bfffbb3ab6	165	#define GPDMA_DMACSoftSReq_BITMASK ((0xFFFF))
lynxeyed_atsu	0:e8bfffbb3ab6	166
lynxeyed_atsu	0:e8bfffbb3ab6	167	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	168	* Macro defines for DMA Software Last Burst Request register
lynxeyed_atsu	0:e8bfffbb3ab6	169	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	170	#define GPDMA_DMACSoftLBReq_Src(n) (((1UL<<n)&0xFFFF))
lynxeyed_atsu	0:e8bfffbb3ab6	171	#define GPDMA_DMACSoftLBReq_BITMASK ((0xFFFF))
lynxeyed_atsu	0:e8bfffbb3ab6	172
lynxeyed_atsu	0:e8bfffbb3ab6	173	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	174	* Macro defines for DMA Software Last Single Request register
lynxeyed_atsu	0:e8bfffbb3ab6	175	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	176	#define GPDMA_DMACSoftLSReq_Src(n) (((1UL<<n)&0xFFFF))
lynxeyed_atsu	0:e8bfffbb3ab6	177	#define GPDMA_DMACSoftLSReq_BITMASK ((0xFFFF))
lynxeyed_atsu	0:e8bfffbb3ab6	178
lynxeyed_atsu	0:e8bfffbb3ab6	179	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	180	* Macro defines for DMA Configuration register
lynxeyed_atsu	0:e8bfffbb3ab6	181	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	182	#define GPDMA_DMACConfig_E ((0x01)) /*< DMA Controller enable/
lynxeyed_atsu	0:e8bfffbb3ab6	183	#define GPDMA_DMACConfig_M ((0x02)) /*< AHB Master endianness configuration/
lynxeyed_atsu	0:e8bfffbb3ab6	184	#define GPDMA_DMACConfig_BITMASK ((0x03))
lynxeyed_atsu	0:e8bfffbb3ab6	185
lynxeyed_atsu	0:e8bfffbb3ab6	186	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	187	* Macro defines for DMA Synchronization register
lynxeyed_atsu	0:e8bfffbb3ab6	188	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	189	#define GPDMA_DMACSync_Src(n) (((1UL<<n)&0xFFFF))
lynxeyed_atsu	0:e8bfffbb3ab6	190	#define GPDMA_DMACSync_BITMASK ((0xFFFF))
lynxeyed_atsu	0:e8bfffbb3ab6	191
lynxeyed_atsu	0:e8bfffbb3ab6	192	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	193	* Macro defines for DMA Request Select register
lynxeyed_atsu	0:e8bfffbb3ab6	194	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	195	#define GPDMA_DMAReqSel_Input(n) (((1UL<<(n-8))&0xFF))
lynxeyed_atsu	0:e8bfffbb3ab6	196	#define GPDMA_DMAReqSel_BITMASK ((0xFF))
lynxeyed_atsu	0:e8bfffbb3ab6	197
lynxeyed_atsu	0:e8bfffbb3ab6	198	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	199	* Macro defines for DMA Channel Linked List Item registers
lynxeyed_atsu	0:e8bfffbb3ab6	200	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	201	/** DMA Channel Linked List Item registers bit mask*/
lynxeyed_atsu	0:e8bfffbb3ab6	202	#define GPDMA_DMACCxLLI_BITMASK ((0xFFFFFFFC))
lynxeyed_atsu	0:e8bfffbb3ab6	203
lynxeyed_atsu	0:e8bfffbb3ab6	204	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	205	* Macro defines for DMA channel control registers
lynxeyed_atsu	0:e8bfffbb3ab6	206	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	207	#define GPDMA_DMACCxControl_TransferSize(n) (((n&0xFFF)<<0)) /*< Transfer size/
lynxeyed_atsu	0:e8bfffbb3ab6	208	#define GPDMA_DMACCxControl_SBSize(n) (((n&0x07)<<12)) /*< Source burst size/
lynxeyed_atsu	0:e8bfffbb3ab6	209	#define GPDMA_DMACCxControl_DBSize(n) (((n&0x07)<<15)) /*< Destination burst size/
lynxeyed_atsu	0:e8bfffbb3ab6	210	#define GPDMA_DMACCxControl_SWidth(n) (((n&0x07)<<18)) /*< Source transfer width/
lynxeyed_atsu	0:e8bfffbb3ab6	211	#define GPDMA_DMACCxControl_DWidth(n) (((n&0x07)<<21)) /*< Destination transfer width/
lynxeyed_atsu	0:e8bfffbb3ab6	212	#define GPDMA_DMACCxControl_SI ((1UL<<26)) /*< Source increment/
lynxeyed_atsu	0:e8bfffbb3ab6	213	#define GPDMA_DMACCxControl_DI ((1UL<<27)) /*< Destination increment/
lynxeyed_atsu	0:e8bfffbb3ab6	214	#define GPDMA_DMACCxControl_Prot1 ((1UL<<28)) /*< Indicates that the access is in user mode or privileged mode/
lynxeyed_atsu	0:e8bfffbb3ab6	215	#define GPDMA_DMACCxControl_Prot2 ((1UL<<29)) /*< Indicates that the access is bufferable or not bufferable/
lynxeyed_atsu	0:e8bfffbb3ab6	216	#define GPDMA_DMACCxControl_Prot3 ((1UL<<30)) /*< Indicates that the access is cacheable or not cacheable/
lynxeyed_atsu	0:e8bfffbb3ab6	217	#define GPDMA_DMACCxControl_I ((1UL<<31)) /*< Terminal count interrupt enable bit /
lynxeyed_atsu	0:e8bfffbb3ab6	218	/** DMA channel control registers bit mask */
lynxeyed_atsu	0:e8bfffbb3ab6	219	#define GPDMA_DMACCxControl_BITMASK ((0xFCFFFFFF))
lynxeyed_atsu	0:e8bfffbb3ab6	220
lynxeyed_atsu	0:e8bfffbb3ab6	221	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	222	* Macro defines for DMA Channel Configuration registers
lynxeyed_atsu	0:e8bfffbb3ab6	223	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	224	#define GPDMA_DMACCxConfig_E ((1UL<<0)) /*< DMA control enable/
lynxeyed_atsu	0:e8bfffbb3ab6	225	#define GPDMA_DMACCxConfig_SrcPeripheral(n) (((n&0x1F)<<1)) /*< Source peripheral/
lynxeyed_atsu	0:e8bfffbb3ab6	226	#define GPDMA_DMACCxConfig_DestPeripheral(n) (((n&0x1F)<<6)) /*< Destination peripheral/
lynxeyed_atsu	0:e8bfffbb3ab6	227	#define GPDMA_DMACCxConfig_TransferType(n) (((n&0x7)<<11)) /*< This value indicates the type of transfer/
lynxeyed_atsu	0:e8bfffbb3ab6	228	#define GPDMA_DMACCxConfig_IE ((1UL<<14)) /*< Interrupt error mask/
lynxeyed_atsu	0:e8bfffbb3ab6	229	#define GPDMA_DMACCxConfig_ITC ((1UL<<15)) /*< Terminal count interrupt mask/
lynxeyed_atsu	0:e8bfffbb3ab6	230	#define GPDMA_DMACCxConfig_L ((1UL<<16)) /*< Lock/
lynxeyed_atsu	0:e8bfffbb3ab6	231	#define GPDMA_DMACCxConfig_A ((1UL<<17)) /*< Active/
lynxeyed_atsu	0:e8bfffbb3ab6	232	#define GPDMA_DMACCxConfig_H ((1UL<<18)) /*< Halt/
lynxeyed_atsu	0:e8bfffbb3ab6	233	/** DMA Channel Configuration registers bit mask */
lynxeyed_atsu	0:e8bfffbb3ab6	234	#define GPDMA_DMACCxConfig_BITMASK ((0x7FFFF))
lynxeyed_atsu	0:e8bfffbb3ab6	235
lynxeyed_atsu	0:e8bfffbb3ab6	236	/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
lynxeyed_atsu	0:e8bfffbb3ab6	237	/* Macros check GPDMA channel */
lynxeyed_atsu	0:e8bfffbb3ab6	238	#define PARAM_GPDMA_CHANNEL(n) ((n>=0) && (n<=7))
lynxeyed_atsu	0:e8bfffbb3ab6	239
lynxeyed_atsu	0:e8bfffbb3ab6	240	/* Macros check GPDMA connection type */
lynxeyed_atsu	0:e8bfffbb3ab6	241	#define PARAM_GPDMA_CONN(n) ((n==GPDMA_CONN_SSP0_Tx) \|\| (n==GPDMA_CONN_SSP0_Rx) \
lynxeyed_atsu	0:e8bfffbb3ab6	242	\|\| (n==GPDMA_CONN_SSP1_Tx) \|\| (n==GPDMA_CONN_SSP1_Rx) \
lynxeyed_atsu	0:e8bfffbb3ab6	243	\|\| (n==GPDMA_CONN_ADC) \|\| (n==GPDMA_CONN_I2S_Channel_0) \
lynxeyed_atsu	0:e8bfffbb3ab6	244	\|\| (n==GPDMA_CONN_I2S_Channel_1) \|\| (n==GPDMA_CONN_DAC) \
lynxeyed_atsu	0:e8bfffbb3ab6	245	\|\| (n==GPDMA_CONN_UART0_Tx) \|\| (n==GPDMA_CONN_UART0_Rx) \
lynxeyed_atsu	0:e8bfffbb3ab6	246	\|\| (n==GPDMA_CONN_UART1_Tx) \|\| (n==GPDMA_CONN_UART1_Rx) \
lynxeyed_atsu	0:e8bfffbb3ab6	247	\|\| (n==GPDMA_CONN_UART2_Tx) \|\| (n==GPDMA_CONN_UART2_Rx) \
lynxeyed_atsu	0:e8bfffbb3ab6	248	\|\| (n==GPDMA_CONN_UART3_Tx) \|\| (n==GPDMA_CONN_UART3_Rx) \
lynxeyed_atsu	0:e8bfffbb3ab6	249	\|\| (n==GPDMA_CONN_MAT0_0) \|\| (n==GPDMA_CONN_MAT0_1) \
lynxeyed_atsu	0:e8bfffbb3ab6	250	\|\| (n==GPDMA_CONN_MAT1_0) \|\| (n==GPDMA_CONN_MAT1_1) \
lynxeyed_atsu	0:e8bfffbb3ab6	251	\|\| (n==GPDMA_CONN_MAT2_0) \|\| (n==GPDMA_CONN_MAT2_1) \
lynxeyed_atsu	0:e8bfffbb3ab6	252	\|\| (n==GPDMA_CONN_MAT3_0) \|\| (n==GPDMA_CONN_MAT3_1))
lynxeyed_atsu	0:e8bfffbb3ab6	253
lynxeyed_atsu	0:e8bfffbb3ab6	254	/* Macros check GPDMA burst size type */
lynxeyed_atsu	0:e8bfffbb3ab6	255	#define PARAM_GPDMA_BSIZE(n) ((n==GPDMA_BSIZE_1) \|\| (n==GPDMA_BSIZE_4) \
lynxeyed_atsu	0:e8bfffbb3ab6	256	\|\| (n==GPDMA_BSIZE_8) \|\| (n==GPDMA_BSIZE_16) \
lynxeyed_atsu	0:e8bfffbb3ab6	257	\|\| (n==GPDMA_BSIZE_32) \|\| (n==GPDMA_BSIZE_64) \
lynxeyed_atsu	0:e8bfffbb3ab6	258	\|\| (n==GPDMA_BSIZE_128) \|\| (n==GPDMA_BSIZE_256))
lynxeyed_atsu	0:e8bfffbb3ab6	259
lynxeyed_atsu	0:e8bfffbb3ab6	260	/* Macros check GPDMA width type */
lynxeyed_atsu	0:e8bfffbb3ab6	261	#define PARAM_GPDMA_WIDTH(n) ((n==GPDMA_WIDTH_BYTE) \|\| (n==GPDMA_WIDTH_HALFWORD) \
lynxeyed_atsu	0:e8bfffbb3ab6	262	\|\| (n==GPDMA_WIDTH_WORD))
lynxeyed_atsu	0:e8bfffbb3ab6	263
lynxeyed_atsu	0:e8bfffbb3ab6	264	/* Macros check GPDMA status type */
lynxeyed_atsu	0:e8bfffbb3ab6	265	#define PARAM_GPDMA_STAT(n) ((n==GPDMA_STAT_INT) \|\| (n==GPDMA_STAT_INTTC) \
lynxeyed_atsu	0:e8bfffbb3ab6	266	\|\| (n==GPDMA_STAT_INTERR) \|\| (n==GPDMA_STAT_RAWINTTC) \
lynxeyed_atsu	0:e8bfffbb3ab6	267	\|\| (n==GPDMA_STAT_RAWINTERR) \|\| (n==GPDMA_STAT_ENABLED_CH))
lynxeyed_atsu	0:e8bfffbb3ab6	268
lynxeyed_atsu	0:e8bfffbb3ab6	269	/* Macros check GPDMA transfer type */
lynxeyed_atsu	0:e8bfffbb3ab6	270	#define PARAM_GPDMA_TRANSFERTYPE(n) ((n==GPDMA_TRANSFERTYPE_M2M)\|\|(n==GPDMA_TRANSFERTYPE_M2P) \
lynxeyed_atsu	0:e8bfffbb3ab6	271	\|\|(n==GPDMA_TRANSFERTYPE_P2M)\|\|(n==GPDMA_TRANSFERTYPE_P2P))
lynxeyed_atsu	0:e8bfffbb3ab6	272
lynxeyed_atsu	0:e8bfffbb3ab6	273	/* Macros check GPDMA state clear type */
lynxeyed_atsu	0:e8bfffbb3ab6	274	#define PARAM_GPDMA_STATCLR(n) ((n==GPDMA_STATCLR_INTTC) \|\| (n==GPDMA_STATCLR_INTERR))
lynxeyed_atsu	0:e8bfffbb3ab6	275
lynxeyed_atsu	0:e8bfffbb3ab6	276	/* Macros check GPDMA request select type */
lynxeyed_atsu	0:e8bfffbb3ab6	277	#define PARAM_GPDMA_REQSEL(n) ((n==GPDMA_REQSEL_UART) \|\| (n==GPDMA_REQSEL_TIMER))
lynxeyed_atsu	0:e8bfffbb3ab6	278	/**
lynxeyed_atsu	0:e8bfffbb3ab6	279	* @}
lynxeyed_atsu	0:e8bfffbb3ab6	280	*/
lynxeyed_atsu	0:e8bfffbb3ab6	281
lynxeyed_atsu	0:e8bfffbb3ab6	282
lynxeyed_atsu	0:e8bfffbb3ab6	283	/* Public Types --------------------------------------------------------------- */
lynxeyed_atsu	0:e8bfffbb3ab6	284	/** @defgroup GPDMA_Public_Types GPDMA Public Types
lynxeyed_atsu	0:e8bfffbb3ab6	285	* @{
lynxeyed_atsu	0:e8bfffbb3ab6	286	*/
lynxeyed_atsu	0:e8bfffbb3ab6	287
lynxeyed_atsu	0:e8bfffbb3ab6	288	/**
lynxeyed_atsu	0:e8bfffbb3ab6	289	* @brief GPDMA Status enumeration
lynxeyed_atsu	0:e8bfffbb3ab6	290	*/
lynxeyed_atsu	0:e8bfffbb3ab6	291	typedef enum {
lynxeyed_atsu	0:e8bfffbb3ab6	292	GPDMA_STAT_INT, /*< GPDMA Interrupt Status /
lynxeyed_atsu	0:e8bfffbb3ab6	293	GPDMA_STAT_INTTC, /*< GPDMA Interrupt Terminal Count Request Status /
lynxeyed_atsu	0:e8bfffbb3ab6	294	GPDMA_STAT_INTERR, /*< GPDMA Interrupt Error Status /
lynxeyed_atsu	0:e8bfffbb3ab6	295	GPDMA_STAT_RAWINTTC, /*< GPDMA Raw Interrupt Terminal Count Status /
lynxeyed_atsu	0:e8bfffbb3ab6	296	GPDMA_STAT_RAWINTERR, /*< GPDMA Raw Error Interrupt Status /
lynxeyed_atsu	0:e8bfffbb3ab6	297	GPDMA_STAT_ENABLED_CH /*< GPDMA Enabled Channel Status /
lynxeyed_atsu	0:e8bfffbb3ab6	298	} GPDMA_Status_Type;
lynxeyed_atsu	0:e8bfffbb3ab6	299
lynxeyed_atsu	0:e8bfffbb3ab6	300	/**
lynxeyed_atsu	0:e8bfffbb3ab6	301	* @brief GPDMA Interrupt clear status enumeration
lynxeyed_atsu	0:e8bfffbb3ab6	302	*/
lynxeyed_atsu	0:e8bfffbb3ab6	303	typedef enum{
lynxeyed_atsu	0:e8bfffbb3ab6	304	GPDMA_STATCLR_INTTC, /*< GPDMA Interrupt Terminal Count Request Clear /
lynxeyed_atsu	0:e8bfffbb3ab6	305	GPDMA_STATCLR_INTERR /*< GPDMA Interrupt Error Clear /
lynxeyed_atsu	0:e8bfffbb3ab6	306	}GPDMA_StateClear_Type;
lynxeyed_atsu	0:e8bfffbb3ab6	307
lynxeyed_atsu	0:e8bfffbb3ab6	308	/**
lynxeyed_atsu	0:e8bfffbb3ab6	309	* @brief GPDMA Channel configuration structure type definition
lynxeyed_atsu	0:e8bfffbb3ab6	310	*/
lynxeyed_atsu	0:e8bfffbb3ab6	311	typedef struct {
lynxeyed_atsu	0:e8bfffbb3ab6	312	uint32_t ChannelNum; /**< DMA channel number, should be in
lynxeyed_atsu	0:e8bfffbb3ab6	313	range from 0 to 7.
lynxeyed_atsu	0:e8bfffbb3ab6	314	Note: DMA channel 0 has the highest priority
lynxeyed_atsu	0:e8bfffbb3ab6	315	and DMA channel 7 the lowest priority.
lynxeyed_atsu	0:e8bfffbb3ab6	316	*/
lynxeyed_atsu	0:e8bfffbb3ab6	317	uint32_t TransferSize; /*< Length/Size of transfer /
lynxeyed_atsu	0:e8bfffbb3ab6	318	uint32_t TransferWidth; /*< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_M2M only /
lynxeyed_atsu	0:e8bfffbb3ab6	319	uint32_t SrcMemAddr; /**< Physical Source Address, used in case TransferType is chosen as
lynxeyed_atsu	0:e8bfffbb3ab6	320	GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_M2P */
lynxeyed_atsu	0:e8bfffbb3ab6	321	uint32_t DstMemAddr; /**< Physical Destination Address, used in case TransferType is chosen as
lynxeyed_atsu	0:e8bfffbb3ab6	322	GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_P2M */
lynxeyed_atsu	0:e8bfffbb3ab6	323	uint32_t TransferType; /**< Transfer Type, should be one of the following:
lynxeyed_atsu	0:e8bfffbb3ab6	324	- GPDMA_TRANSFERTYPE_M2M: Memory to memory - DMA control
lynxeyed_atsu	0:e8bfffbb3ab6	325	- GPDMA_TRANSFERTYPE_M2P: Memory to peripheral - DMA control
lynxeyed_atsu	0:e8bfffbb3ab6	326	- GPDMA_TRANSFERTYPE_P2M: Peripheral to memory - DMA control
lynxeyed_atsu	0:e8bfffbb3ab6	327	- GPDMA_TRANSFERTYPE_P2P: Source peripheral to destination peripheral - DMA control
lynxeyed_atsu	0:e8bfffbb3ab6	328	*/
lynxeyed_atsu	0:e8bfffbb3ab6	329	uint32_t SrcConn; /**< Peripheral Source Connection type, used in case TransferType is chosen as
lynxeyed_atsu	0:e8bfffbb3ab6	330	GPDMA_TRANSFERTYPE_P2M or GPDMA_TRANSFERTYPE_P2P, should be one of
lynxeyed_atsu	0:e8bfffbb3ab6	331	following:
lynxeyed_atsu	0:e8bfffbb3ab6	332	- GPDMA_CONN_SSP0_Tx: SSP0, Tx
lynxeyed_atsu	0:e8bfffbb3ab6	333	- GPDMA_CONN_SSP0_Rx: SSP0, Rx
lynxeyed_atsu	0:e8bfffbb3ab6	334	- GPDMA_CONN_SSP1_Tx: SSP1, Tx
lynxeyed_atsu	0:e8bfffbb3ab6	335	- GPDMA_CONN_SSP1_Rx: SSP1, Rx
lynxeyed_atsu	0:e8bfffbb3ab6	336	- GPDMA_CONN_ADC: ADC
lynxeyed_atsu	0:e8bfffbb3ab6	337	- GPDMA_CONN_I2S_Channel_0: I2S Channel 0
lynxeyed_atsu	0:e8bfffbb3ab6	338	- GPDMA_CONN_I2S_Channel_1: I2S Channel 1
lynxeyed_atsu	0:e8bfffbb3ab6	339	- GPDMA_CONN_DAC: DAC
lynxeyed_atsu	0:e8bfffbb3ab6	340	- GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
lynxeyed_atsu	0:e8bfffbb3ab6	341	- GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
lynxeyed_atsu	0:e8bfffbb3ab6	342	- GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
lynxeyed_atsu	0:e8bfffbb3ab6	343	- GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
lynxeyed_atsu	0:e8bfffbb3ab6	344	- GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
lynxeyed_atsu	0:e8bfffbb3ab6	345	- GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
lynxeyed_atsu	0:e8bfffbb3ab6	346	- GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
lynxeyed_atsu	0:e8bfffbb3ab6	347	- GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
lynxeyed_atsu	0:e8bfffbb3ab6	348	*/
lynxeyed_atsu	0:e8bfffbb3ab6	349	uint32_t DstConn; /**< Peripheral Destination Connection type, used in case TransferType is chosen as
lynxeyed_atsu	0:e8bfffbb3ab6	350	GPDMA_TRANSFERTYPE_M2P or GPDMA_TRANSFERTYPE_P2P, should be one of
lynxeyed_atsu	0:e8bfffbb3ab6	351	following:
lynxeyed_atsu	0:e8bfffbb3ab6	352	- GPDMA_CONN_SSP0_Tx: SSP0, Tx
lynxeyed_atsu	0:e8bfffbb3ab6	353	- GPDMA_CONN_SSP0_Rx: SSP0, Rx
lynxeyed_atsu	0:e8bfffbb3ab6	354	- GPDMA_CONN_SSP1_Tx: SSP1, Tx
lynxeyed_atsu	0:e8bfffbb3ab6	355	- GPDMA_CONN_SSP1_Rx: SSP1, Rx
lynxeyed_atsu	0:e8bfffbb3ab6	356	- GPDMA_CONN_ADC: ADC
lynxeyed_atsu	0:e8bfffbb3ab6	357	- GPDMA_CONN_I2S_Channel_0: I2S Channel 0
lynxeyed_atsu	0:e8bfffbb3ab6	358	- GPDMA_CONN_I2S_Channel_1: I2S Channel 1
lynxeyed_atsu	0:e8bfffbb3ab6	359	- GPDMA_CONN_DAC: DAC
lynxeyed_atsu	0:e8bfffbb3ab6	360	- GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
lynxeyed_atsu	0:e8bfffbb3ab6	361	- GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
lynxeyed_atsu	0:e8bfffbb3ab6	362	- GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
lynxeyed_atsu	0:e8bfffbb3ab6	363	- GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
lynxeyed_atsu	0:e8bfffbb3ab6	364	- GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
lynxeyed_atsu	0:e8bfffbb3ab6	365	- GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
lynxeyed_atsu	0:e8bfffbb3ab6	366	- GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
lynxeyed_atsu	0:e8bfffbb3ab6	367	- GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
lynxeyed_atsu	0:e8bfffbb3ab6	368	*/
lynxeyed_atsu	0:e8bfffbb3ab6	369	uint32_t DMALLI; /**< Linker List Item structure data address
lynxeyed_atsu	0:e8bfffbb3ab6	370	if there's no Linker List, set as '0'
lynxeyed_atsu	0:e8bfffbb3ab6	371	*/
lynxeyed_atsu	0:e8bfffbb3ab6	372	} GPDMA_Channel_CFG_Type;
lynxeyed_atsu	0:e8bfffbb3ab6	373
lynxeyed_atsu	0:e8bfffbb3ab6	374	/**
lynxeyed_atsu	0:e8bfffbb3ab6	375	* @brief GPDMA Linker List Item structure type definition
lynxeyed_atsu	0:e8bfffbb3ab6	376	*/
lynxeyed_atsu	0:e8bfffbb3ab6	377	typedef struct {
lynxeyed_atsu	0:e8bfffbb3ab6	378	uint32_t SrcAddr; /*< Source Address /
lynxeyed_atsu	0:e8bfffbb3ab6	379	uint32_t DstAddr; /*< Destination address /
lynxeyed_atsu	0:e8bfffbb3ab6	380	uint32_t NextLLI; /*< Next LLI address, otherwise set to '0' /
lynxeyed_atsu	0:e8bfffbb3ab6	381	uint32_t Control; /*< GPDMA Control of this LLI /
lynxeyed_atsu	0:e8bfffbb3ab6	382	} GPDMA_LLI_Type;
lynxeyed_atsu	0:e8bfffbb3ab6	383
lynxeyed_atsu	0:e8bfffbb3ab6	384
lynxeyed_atsu	0:e8bfffbb3ab6	385	/**
lynxeyed_atsu	0:e8bfffbb3ab6	386	* @}
lynxeyed_atsu	0:e8bfffbb3ab6	387	*/
lynxeyed_atsu	0:e8bfffbb3ab6	388
lynxeyed_atsu	0:e8bfffbb3ab6	389	/* Public Functions ----------------------------------------------------------- */
lynxeyed_atsu	0:e8bfffbb3ab6	390	/** @defgroup GPDMA_Public_Functions GPDMA Public Functions
lynxeyed_atsu	0:e8bfffbb3ab6	391	* @{
lynxeyed_atsu	0:e8bfffbb3ab6	392	*/
lynxeyed_atsu	0:e8bfffbb3ab6	393
lynxeyed_atsu	0:e8bfffbb3ab6	394	void GPDMA_Init(void);
lynxeyed_atsu	0:e8bfffbb3ab6	395	//Status GPDMA_Setup(GPDMA_Channel_CFG_Type GPDMAChannelConfig, fnGPDMACbs_Type pfnGPDMACbs);
lynxeyed_atsu	0:e8bfffbb3ab6	396	Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig);
lynxeyed_atsu	0:e8bfffbb3ab6	397	IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel);
lynxeyed_atsu	0:e8bfffbb3ab6	398	void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel);
lynxeyed_atsu	0:e8bfffbb3ab6	399	void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState);
lynxeyed_atsu	0:e8bfffbb3ab6	400	//void GPDMA_IntHandler(void);
lynxeyed_atsu	0:e8bfffbb3ab6	401
lynxeyed_atsu	0:e8bfffbb3ab6	402	/**
lynxeyed_atsu	0:e8bfffbb3ab6	403	* @}
lynxeyed_atsu	0:e8bfffbb3ab6	404	*/
lynxeyed_atsu	0:e8bfffbb3ab6	405
lynxeyed_atsu	0:e8bfffbb3ab6	406
lynxeyed_atsu	0:e8bfffbb3ab6	407	#ifdef __cplusplus
lynxeyed_atsu	0:e8bfffbb3ab6	408	}
lynxeyed_atsu	0:e8bfffbb3ab6	409	#endif
lynxeyed_atsu	0:e8bfffbb3ab6	410
lynxeyed_atsu	0:e8bfffbb3ab6	411	#endif /* LPC17XX_GPDMA_H_ */
lynxeyed_atsu	0:e8bfffbb3ab6	412
lynxeyed_atsu	0:e8bfffbb3ab6	413	/**
lynxeyed_atsu	0:e8bfffbb3ab6	414	* @}
lynxeyed_atsu	0:e8bfffbb3ab6	415	*/
lynxeyed_atsu	0:e8bfffbb3ab6	416
lynxeyed_atsu	0:e8bfffbb3ab6	417	/* --------------------------------- End Of File ------------------------------ */

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	26 Feb 2011
Imports:	12
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	1

I2S_Example/lpc17xx_gpdma.h@0:e8bfffbb3ab6, 2011-02-26 (annotated)

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