DMA_LLI_TEST - LINKED LIST TEST on mbed

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xeye_ atsu / Mbed 2 deprecated DMA_LLI_TEST

LINKED LIST TEST on mbed

I2S_Example/lpc17xx_gpdma.c@0:e8bfffbb3ab6, 2011-02-26 (annotated)

Committer:: lynxeyed_atsu
Date:: Sat Feb 26 03:55:12 2011 +0000
Revision:: 0:e8bfffbb3ab6

Who changed what in which revision?

User	Revision	Line number	New contents of line
lynxeyed_atsu	0:e8bfffbb3ab6	1	/*********************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	2	* @file lpc17xx_gpdma.c
lynxeyed_atsu	0:e8bfffbb3ab6	3	* @brief Contains all functions support for GPDMA firmware library on LPC17xx
lynxeyed_atsu	0:e8bfffbb3ab6	4	* @version 2.0
lynxeyed_atsu	0:e8bfffbb3ab6	5	* @date 21. May. 2010
lynxeyed_atsu	0:e8bfffbb3ab6	6	* @author NXP MCU SW Application Team
lynxeyed_atsu	0:e8bfffbb3ab6	7	**************************************************************************
lynxeyed_atsu	0:e8bfffbb3ab6	8	* Software that is described herein is for illustrative purposes only
lynxeyed_atsu	0:e8bfffbb3ab6	9	* which provides customers with programming information regarding the
lynxeyed_atsu	0:e8bfffbb3ab6	10	* products. This software is supplied "AS IS" without any warranties.
lynxeyed_atsu	0:e8bfffbb3ab6	11	* NXP Semiconductors assumes no responsibility or liability for the
lynxeyed_atsu	0:e8bfffbb3ab6	12	* use of the software, conveys no license or title under any patent,
lynxeyed_atsu	0:e8bfffbb3ab6	13	* copyright, or mask work right to the product. NXP Semiconductors
lynxeyed_atsu	0:e8bfffbb3ab6	14	* reserves the right to make changes in the software without
lynxeyed_atsu	0:e8bfffbb3ab6	15	* notification. NXP Semiconductors also make no representation or
lynxeyed_atsu	0:e8bfffbb3ab6	16	* warranty that such application will be suitable for the specified
lynxeyed_atsu	0:e8bfffbb3ab6	17	* use without further testing or modification.
lynxeyed_atsu	0:e8bfffbb3ab6	18	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	19
lynxeyed_atsu	0:e8bfffbb3ab6	20	/* Peripheral group ----------------------------------------------------------- */
lynxeyed_atsu	0:e8bfffbb3ab6	21	/** @addtogroup GPDMA
lynxeyed_atsu	0:e8bfffbb3ab6	22	* @{
lynxeyed_atsu	0:e8bfffbb3ab6	23	*/
lynxeyed_atsu	0:e8bfffbb3ab6	24
lynxeyed_atsu	0:e8bfffbb3ab6	25	/* Includes ------------------------------------------------------------------- */
lynxeyed_atsu	0:e8bfffbb3ab6	26	#include "lpc17xx_gpdma.h"
lynxeyed_atsu	0:e8bfffbb3ab6	27	#include "lpc17xx_clkpwr.h"
lynxeyed_atsu	0:e8bfffbb3ab6	28
lynxeyed_atsu	0:e8bfffbb3ab6	29	/* If this source file built with example, the LPC17xx FW library configuration
lynxeyed_atsu	0:e8bfffbb3ab6	30	* file in each example directory ("lpc17xx_libcfg.h") must be included,
lynxeyed_atsu	0:e8bfffbb3ab6	31	* otherwise the default FW library configuration file must be included instead
lynxeyed_atsu	0:e8bfffbb3ab6	32	*/
lynxeyed_atsu	0:e8bfffbb3ab6	33	#ifdef __BUILD_WITH_EXAMPLE__
lynxeyed_atsu	0:e8bfffbb3ab6	34	#include "lpc17xx_libcfg.h"
lynxeyed_atsu	0:e8bfffbb3ab6	35	#else
lynxeyed_atsu	0:e8bfffbb3ab6	36	#include "lpc17xx_libcfg_default.h"
lynxeyed_atsu	0:e8bfffbb3ab6	37	#endif /* __BUILD_WITH_EXAMPLE__ */
lynxeyed_atsu	0:e8bfffbb3ab6	38
lynxeyed_atsu	0:e8bfffbb3ab6	39	#ifdef _GPDMA
lynxeyed_atsu	0:e8bfffbb3ab6	40
lynxeyed_atsu	0:e8bfffbb3ab6	41
lynxeyed_atsu	0:e8bfffbb3ab6	42	/* Private Variables ---------------------------------------------------------- */
lynxeyed_atsu	0:e8bfffbb3ab6	43	/** @defgroup GPDMA_Private_Variables GPDMA Private Variables
lynxeyed_atsu	0:e8bfffbb3ab6	44	* @{
lynxeyed_atsu	0:e8bfffbb3ab6	45	*/
lynxeyed_atsu	0:e8bfffbb3ab6	46
lynxeyed_atsu	0:e8bfffbb3ab6	47	/**
lynxeyed_atsu	0:e8bfffbb3ab6	48	* @brief Lookup Table of Connection Type matched with
lynxeyed_atsu	0:e8bfffbb3ab6	49	* Peripheral Data (FIFO) register base address
lynxeyed_atsu	0:e8bfffbb3ab6	50	*/
lynxeyed_atsu	0:e8bfffbb3ab6	51	#ifdef __IAR_SYSTEMS_ICC__
lynxeyed_atsu	0:e8bfffbb3ab6	52	volatile const void *GPDMA_LUTPerAddr[] = {
lynxeyed_atsu	0:e8bfffbb3ab6	53	(&LPC_SSP0->DR), // SSP0 Tx
lynxeyed_atsu	0:e8bfffbb3ab6	54	(&LPC_SSP0->DR), // SSP0 Rx
lynxeyed_atsu	0:e8bfffbb3ab6	55	(&LPC_SSP1->DR), // SSP1 Tx
lynxeyed_atsu	0:e8bfffbb3ab6	56	(&LPC_SSP1->DR), // SSP1 Rx
lynxeyed_atsu	0:e8bfffbb3ab6	57	(&LPC_ADC->ADGDR), // ADC
lynxeyed_atsu	0:e8bfffbb3ab6	58	(&LPC_I2S->I2STXFIFO), // I2S Tx
lynxeyed_atsu	0:e8bfffbb3ab6	59	(&LPC_I2S->I2SRXFIFO), // I2S Rx
lynxeyed_atsu	0:e8bfffbb3ab6	60	(&LPC_DAC->DACR), // DAC
lynxeyed_atsu	0:e8bfffbb3ab6	61	(&LPC_UART0->/RBTHDLR./THR), // UART0 Tx
lynxeyed_atsu	0:e8bfffbb3ab6	62	(&LPC_UART0->/RBTHDLR./RBR), // UART0 Rx
lynxeyed_atsu	0:e8bfffbb3ab6	63	(&LPC_UART1->/RBTHDLR./THR), // UART1 Tx
lynxeyed_atsu	0:e8bfffbb3ab6	64	(&LPC_UART1->/RBTHDLR./RBR), // UART1 Rx
lynxeyed_atsu	0:e8bfffbb3ab6	65	(&LPC_UART2->/RBTHDLR./THR), // UART2 Tx
lynxeyed_atsu	0:e8bfffbb3ab6	66	(&LPC_UART2->/RBTHDLR./RBR), // UART2 Rx
lynxeyed_atsu	0:e8bfffbb3ab6	67	(&LPC_UART3->/RBTHDLR./THR), // UART3 Tx
lynxeyed_atsu	0:e8bfffbb3ab6	68	(&LPC_UART3->/RBTHDLR./RBR), // UART3 Rx
lynxeyed_atsu	0:e8bfffbb3ab6	69	(&LPC_TIM0->MR0), // MAT0.0
lynxeyed_atsu	0:e8bfffbb3ab6	70	(&LPC_TIM0->MR1), // MAT0.1
lynxeyed_atsu	0:e8bfffbb3ab6	71	(&LPC_TIM1->MR0), // MAT1.0
lynxeyed_atsu	0:e8bfffbb3ab6	72	(&LPC_TIM1->MR1), // MAT1.1
lynxeyed_atsu	0:e8bfffbb3ab6	73	(&LPC_TIM2->MR0), // MAT2.0
lynxeyed_atsu	0:e8bfffbb3ab6	74	(&LPC_TIM2->MR1), // MAT2.1
lynxeyed_atsu	0:e8bfffbb3ab6	75	(&LPC_TIM3->MR0), // MAT3.0
lynxeyed_atsu	0:e8bfffbb3ab6	76	(&LPC_TIM3->MR1), // MAT3.1
lynxeyed_atsu	0:e8bfffbb3ab6	77	};
lynxeyed_atsu	0:e8bfffbb3ab6	78	#else
lynxeyed_atsu	0:e8bfffbb3ab6	79	const uint32_t GPDMA_LUTPerAddr[] = {
lynxeyed_atsu	0:e8bfffbb3ab6	80	((uint32_t)&LPC_SSP0->DR), // SSP0 Tx
lynxeyed_atsu	0:e8bfffbb3ab6	81	((uint32_t)&LPC_SSP0->DR), // SSP0 Rx
lynxeyed_atsu	0:e8bfffbb3ab6	82	((uint32_t)&LPC_SSP1->DR), // SSP1 Tx
lynxeyed_atsu	0:e8bfffbb3ab6	83	((uint32_t)&LPC_SSP1->DR), // SSP1 Rx
lynxeyed_atsu	0:e8bfffbb3ab6	84	((uint32_t)&LPC_ADC->ADGDR), // ADC
lynxeyed_atsu	0:e8bfffbb3ab6	85	((uint32_t)&LPC_I2S->I2STXFIFO), // I2S Tx
lynxeyed_atsu	0:e8bfffbb3ab6	86	((uint32_t)&LPC_I2S->I2SRXFIFO), // I2S Rx
lynxeyed_atsu	0:e8bfffbb3ab6	87	((uint32_t)&LPC_DAC->DACR), // DAC
lynxeyed_atsu	0:e8bfffbb3ab6	88	((uint32_t)&LPC_UART0->/RBTHDLR./THR), // UART0 Tx
lynxeyed_atsu	0:e8bfffbb3ab6	89	((uint32_t)&LPC_UART0->/RBTHDLR./RBR), // UART0 Rx
lynxeyed_atsu	0:e8bfffbb3ab6	90	((uint32_t)&LPC_UART1->/RBTHDLR./THR), // UART1 Tx
lynxeyed_atsu	0:e8bfffbb3ab6	91	((uint32_t)&LPC_UART1->/RBTHDLR./RBR), // UART1 Rx
lynxeyed_atsu	0:e8bfffbb3ab6	92	((uint32_t)&LPC_UART2->/RBTHDLR./THR), // UART2 Tx
lynxeyed_atsu	0:e8bfffbb3ab6	93	((uint32_t)&LPC_UART2->/RBTHDLR./RBR), // UART2 Rx
lynxeyed_atsu	0:e8bfffbb3ab6	94	((uint32_t)&LPC_UART3->/RBTHDLR./THR), // UART3 Tx
lynxeyed_atsu	0:e8bfffbb3ab6	95	((uint32_t)&LPC_UART3->/RBTHDLR./RBR), // UART3 Rx
lynxeyed_atsu	0:e8bfffbb3ab6	96	((uint32_t)&LPC_TIM0->MR0), // MAT0.0
lynxeyed_atsu	0:e8bfffbb3ab6	97	((uint32_t)&LPC_TIM0->MR1), // MAT0.1
lynxeyed_atsu	0:e8bfffbb3ab6	98	((uint32_t)&LPC_TIM1->MR0), // MAT1.0
lynxeyed_atsu	0:e8bfffbb3ab6	99	((uint32_t)&LPC_TIM1->MR1), // MAT1.1
lynxeyed_atsu	0:e8bfffbb3ab6	100	((uint32_t)&LPC_TIM2->MR0), // MAT2.0
lynxeyed_atsu	0:e8bfffbb3ab6	101	((uint32_t)&LPC_TIM2->MR1), // MAT2.1
lynxeyed_atsu	0:e8bfffbb3ab6	102	((uint32_t)&LPC_TIM3->MR0), // MAT3.0
lynxeyed_atsu	0:e8bfffbb3ab6	103	((uint32_t)&LPC_TIM3->MR1), // MAT3.1
lynxeyed_atsu	0:e8bfffbb3ab6	104	};
lynxeyed_atsu	0:e8bfffbb3ab6	105	#endif
lynxeyed_atsu	0:e8bfffbb3ab6	106	/**
lynxeyed_atsu	0:e8bfffbb3ab6	107	* @brief Lookup Table of GPDMA Channel Number matched with
lynxeyed_atsu	0:e8bfffbb3ab6	108	* GPDMA channel pointer
lynxeyed_atsu	0:e8bfffbb3ab6	109	*/
lynxeyed_atsu	0:e8bfffbb3ab6	110	const LPC_GPDMACH_TypeDef *pGPDMACh[8] = {
lynxeyed_atsu	0:e8bfffbb3ab6	111	LPC_GPDMACH0, // GPDMA Channel 0
lynxeyed_atsu	0:e8bfffbb3ab6	112	LPC_GPDMACH1, // GPDMA Channel 1
lynxeyed_atsu	0:e8bfffbb3ab6	113	LPC_GPDMACH2, // GPDMA Channel 2
lynxeyed_atsu	0:e8bfffbb3ab6	114	LPC_GPDMACH3, // GPDMA Channel 3
lynxeyed_atsu	0:e8bfffbb3ab6	115	LPC_GPDMACH4, // GPDMA Channel 4
lynxeyed_atsu	0:e8bfffbb3ab6	116	LPC_GPDMACH5, // GPDMA Channel 5
lynxeyed_atsu	0:e8bfffbb3ab6	117	LPC_GPDMACH6, // GPDMA Channel 6
lynxeyed_atsu	0:e8bfffbb3ab6	118	LPC_GPDMACH7, // GPDMA Channel 7
lynxeyed_atsu	0:e8bfffbb3ab6	119	};
lynxeyed_atsu	0:e8bfffbb3ab6	120	/**
lynxeyed_atsu	0:e8bfffbb3ab6	121	* @brief Optimized Peripheral Source and Destination burst size
lynxeyed_atsu	0:e8bfffbb3ab6	122	*/
lynxeyed_atsu	0:e8bfffbb3ab6	123	const uint8_t GPDMA_LUTPerBurst[] = {
lynxeyed_atsu	0:e8bfffbb3ab6	124	GPDMA_BSIZE_4, // SSP0 Tx
lynxeyed_atsu	0:e8bfffbb3ab6	125	GPDMA_BSIZE_4, // SSP0 Rx
lynxeyed_atsu	0:e8bfffbb3ab6	126	GPDMA_BSIZE_4, // SSP1 Tx
lynxeyed_atsu	0:e8bfffbb3ab6	127	GPDMA_BSIZE_4, // SSP1 Rx
lynxeyed_atsu	0:e8bfffbb3ab6	128	GPDMA_BSIZE_4, // ADC
lynxeyed_atsu	0:e8bfffbb3ab6	129	GPDMA_BSIZE_32, // I2S channel 0
lynxeyed_atsu	0:e8bfffbb3ab6	130	GPDMA_BSIZE_32, // I2S channel 1
lynxeyed_atsu	0:e8bfffbb3ab6	131	GPDMA_BSIZE_1, // DAC
lynxeyed_atsu	0:e8bfffbb3ab6	132	GPDMA_BSIZE_1, // UART0 Tx
lynxeyed_atsu	0:e8bfffbb3ab6	133	GPDMA_BSIZE_1, // UART0 Rx
lynxeyed_atsu	0:e8bfffbb3ab6	134	GPDMA_BSIZE_1, // UART1 Tx
lynxeyed_atsu	0:e8bfffbb3ab6	135	GPDMA_BSIZE_1, // UART1 Rx
lynxeyed_atsu	0:e8bfffbb3ab6	136	GPDMA_BSIZE_1, // UART2 Tx
lynxeyed_atsu	0:e8bfffbb3ab6	137	GPDMA_BSIZE_1, // UART2 Rx
lynxeyed_atsu	0:e8bfffbb3ab6	138	GPDMA_BSIZE_1, // UART3 Tx
lynxeyed_atsu	0:e8bfffbb3ab6	139	GPDMA_BSIZE_1, // UART3 Rx
lynxeyed_atsu	0:e8bfffbb3ab6	140	GPDMA_BSIZE_1, // MAT0.0
lynxeyed_atsu	0:e8bfffbb3ab6	141	GPDMA_BSIZE_1, // MAT0.1
lynxeyed_atsu	0:e8bfffbb3ab6	142	GPDMA_BSIZE_1, // MAT1.0
lynxeyed_atsu	0:e8bfffbb3ab6	143	GPDMA_BSIZE_1, // MAT1.1
lynxeyed_atsu	0:e8bfffbb3ab6	144	GPDMA_BSIZE_1, // MAT2.0
lynxeyed_atsu	0:e8bfffbb3ab6	145	GPDMA_BSIZE_1, // MAT2.1
lynxeyed_atsu	0:e8bfffbb3ab6	146	GPDMA_BSIZE_1, // MAT3.0
lynxeyed_atsu	0:e8bfffbb3ab6	147	GPDMA_BSIZE_1, // MAT3.1
lynxeyed_atsu	0:e8bfffbb3ab6	148	};
lynxeyed_atsu	0:e8bfffbb3ab6	149	/**
lynxeyed_atsu	0:e8bfffbb3ab6	150	* @brief Optimized Peripheral Source and Destination transfer width
lynxeyed_atsu	0:e8bfffbb3ab6	151	*/
lynxeyed_atsu	0:e8bfffbb3ab6	152	const uint8_t GPDMA_LUTPerWid[] = {
lynxeyed_atsu	0:e8bfffbb3ab6	153	GPDMA_WIDTH_BYTE, // SSP0 Tx
lynxeyed_atsu	0:e8bfffbb3ab6	154	GPDMA_WIDTH_BYTE, // SSP0 Rx
lynxeyed_atsu	0:e8bfffbb3ab6	155	GPDMA_WIDTH_BYTE, // SSP1 Tx
lynxeyed_atsu	0:e8bfffbb3ab6	156	GPDMA_WIDTH_BYTE, // SSP1 Rx
lynxeyed_atsu	0:e8bfffbb3ab6	157	GPDMA_WIDTH_WORD, // ADC
lynxeyed_atsu	0:e8bfffbb3ab6	158	GPDMA_WIDTH_WORD, // I2S channel 0
lynxeyed_atsu	0:e8bfffbb3ab6	159	GPDMA_WIDTH_WORD, // I2S channel 1
lynxeyed_atsu	0:e8bfffbb3ab6	160	GPDMA_WIDTH_BYTE, // DAC
lynxeyed_atsu	0:e8bfffbb3ab6	161	GPDMA_WIDTH_BYTE, // UART0 Tx
lynxeyed_atsu	0:e8bfffbb3ab6	162	GPDMA_WIDTH_BYTE, // UART0 Rx
lynxeyed_atsu	0:e8bfffbb3ab6	163	GPDMA_WIDTH_BYTE, // UART1 Tx
lynxeyed_atsu	0:e8bfffbb3ab6	164	GPDMA_WIDTH_BYTE, // UART1 Rx
lynxeyed_atsu	0:e8bfffbb3ab6	165	GPDMA_WIDTH_BYTE, // UART2 Tx
lynxeyed_atsu	0:e8bfffbb3ab6	166	GPDMA_WIDTH_BYTE, // UART2 Rx
lynxeyed_atsu	0:e8bfffbb3ab6	167	GPDMA_WIDTH_BYTE, // UART3 Tx
lynxeyed_atsu	0:e8bfffbb3ab6	168	GPDMA_WIDTH_BYTE, // UART3 Rx
lynxeyed_atsu	0:e8bfffbb3ab6	169	GPDMA_WIDTH_WORD, // MAT0.0
lynxeyed_atsu	0:e8bfffbb3ab6	170	GPDMA_WIDTH_WORD, // MAT0.1
lynxeyed_atsu	0:e8bfffbb3ab6	171	GPDMA_WIDTH_WORD, // MAT1.0
lynxeyed_atsu	0:e8bfffbb3ab6	172	GPDMA_WIDTH_WORD, // MAT1.1
lynxeyed_atsu	0:e8bfffbb3ab6	173	GPDMA_WIDTH_WORD, // MAT2.0
lynxeyed_atsu	0:e8bfffbb3ab6	174	GPDMA_WIDTH_WORD, // MAT2.1
lynxeyed_atsu	0:e8bfffbb3ab6	175	GPDMA_WIDTH_WORD, // MAT3.0
lynxeyed_atsu	0:e8bfffbb3ab6	176	GPDMA_WIDTH_WORD, // MAT3.1
lynxeyed_atsu	0:e8bfffbb3ab6	177	};
lynxeyed_atsu	0:e8bfffbb3ab6	178
lynxeyed_atsu	0:e8bfffbb3ab6	179	/**
lynxeyed_atsu	0:e8bfffbb3ab6	180	* @}
lynxeyed_atsu	0:e8bfffbb3ab6	181	*/
lynxeyed_atsu	0:e8bfffbb3ab6	182
lynxeyed_atsu	0:e8bfffbb3ab6	183	/* Public Functions ----------------------------------------------------------- */
lynxeyed_atsu	0:e8bfffbb3ab6	184	/** @addtogroup GPDMA_Public_Functions
lynxeyed_atsu	0:e8bfffbb3ab6	185	* @{
lynxeyed_atsu	0:e8bfffbb3ab6	186	*/
lynxeyed_atsu	0:e8bfffbb3ab6	187
lynxeyed_atsu	0:e8bfffbb3ab6	188	/******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	189	* @brief Initialize GPDMA controller
lynxeyed_atsu	0:e8bfffbb3ab6	190	* @param None
lynxeyed_atsu	0:e8bfffbb3ab6	191	* @return None
lynxeyed_atsu	0:e8bfffbb3ab6	192	*********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	193	void GPDMA_Init(void)
lynxeyed_atsu	0:e8bfffbb3ab6	194	{
lynxeyed_atsu	0:e8bfffbb3ab6	195	/* Enable GPDMA clock */
lynxeyed_atsu	0:e8bfffbb3ab6	196	CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCGPDMA, ENABLE);
lynxeyed_atsu	0:e8bfffbb3ab6	197
lynxeyed_atsu	0:e8bfffbb3ab6	198	// Reset all channel configuration register
lynxeyed_atsu	0:e8bfffbb3ab6	199	LPC_GPDMACH0->DMACCConfig = 0;
lynxeyed_atsu	0:e8bfffbb3ab6	200	LPC_GPDMACH1->DMACCConfig = 0;
lynxeyed_atsu	0:e8bfffbb3ab6	201	LPC_GPDMACH2->DMACCConfig = 0;
lynxeyed_atsu	0:e8bfffbb3ab6	202	LPC_GPDMACH3->DMACCConfig = 0;
lynxeyed_atsu	0:e8bfffbb3ab6	203	LPC_GPDMACH4->DMACCConfig = 0;
lynxeyed_atsu	0:e8bfffbb3ab6	204	LPC_GPDMACH5->DMACCConfig = 0;
lynxeyed_atsu	0:e8bfffbb3ab6	205	LPC_GPDMACH6->DMACCConfig = 0;
lynxeyed_atsu	0:e8bfffbb3ab6	206	LPC_GPDMACH7->DMACCConfig = 0;
lynxeyed_atsu	0:e8bfffbb3ab6	207
lynxeyed_atsu	0:e8bfffbb3ab6	208	/* Clear all DMA interrupt and error flag */
lynxeyed_atsu	0:e8bfffbb3ab6	209	LPC_GPDMA->DMACIntTCClear = 0xFF;
lynxeyed_atsu	0:e8bfffbb3ab6	210	LPC_GPDMA->DMACIntErrClr = 0xFF;
lynxeyed_atsu	0:e8bfffbb3ab6	211	}
lynxeyed_atsu	0:e8bfffbb3ab6	212
lynxeyed_atsu	0:e8bfffbb3ab6	213	/******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	214	* @brief Setup GPDMA channel peripheral according to the specified
lynxeyed_atsu	0:e8bfffbb3ab6	215	* parameters in the GPDMAChannelConfig.
lynxeyed_atsu	0:e8bfffbb3ab6	216	* @param[in] GPDMAChannelConfig Pointer to a GPDMA_CH_CFG_Type
lynxeyed_atsu	0:e8bfffbb3ab6	217	* structure that contains the configuration
lynxeyed_atsu	0:e8bfffbb3ab6	218	* information for the specified GPDMA channel peripheral.
lynxeyed_atsu	0:e8bfffbb3ab6	219	* @return ERROR if selected channel is enabled before
lynxeyed_atsu	0:e8bfffbb3ab6	220	* or SUCCESS if channel is configured successfully
lynxeyed_atsu	0:e8bfffbb3ab6	221	*********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	222	Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig)
lynxeyed_atsu	0:e8bfffbb3ab6	223	{
lynxeyed_atsu	0:e8bfffbb3ab6	224	LPC_GPDMACH_TypeDef *pDMAch;
lynxeyed_atsu	0:e8bfffbb3ab6	225	uint32_t tmp1, tmp2;
lynxeyed_atsu	0:e8bfffbb3ab6	226
lynxeyed_atsu	0:e8bfffbb3ab6	227	if (LPC_GPDMA->DMACEnbldChns & (GPDMA_DMACEnbldChns_Ch(GPDMAChannelConfig->ChannelNum))) {
lynxeyed_atsu	0:e8bfffbb3ab6	228	// This channel is enabled, return ERROR, need to release this channel first
lynxeyed_atsu	0:e8bfffbb3ab6	229	return ERROR;
lynxeyed_atsu	0:e8bfffbb3ab6	230	}
lynxeyed_atsu	0:e8bfffbb3ab6	231
lynxeyed_atsu	0:e8bfffbb3ab6	232	// Get Channel pointer
lynxeyed_atsu	0:e8bfffbb3ab6	233	pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[GPDMAChannelConfig->ChannelNum];
lynxeyed_atsu	0:e8bfffbb3ab6	234
lynxeyed_atsu	0:e8bfffbb3ab6	235	// Reset the Interrupt status
lynxeyed_atsu	0:e8bfffbb3ab6	236	LPC_GPDMA->DMACIntTCClear = GPDMA_DMACIntTCClear_Ch(GPDMAChannelConfig->ChannelNum);
lynxeyed_atsu	0:e8bfffbb3ab6	237	LPC_GPDMA->DMACIntErrClr = GPDMA_DMACIntErrClr_Ch(GPDMAChannelConfig->ChannelNum);
lynxeyed_atsu	0:e8bfffbb3ab6	238
lynxeyed_atsu	0:e8bfffbb3ab6	239	// Clear DMA configure
lynxeyed_atsu	0:e8bfffbb3ab6	240	pDMAch->DMACCControl = 0x00;
lynxeyed_atsu	0:e8bfffbb3ab6	241	pDMAch->DMACCConfig = 0x00;
lynxeyed_atsu	0:e8bfffbb3ab6	242
lynxeyed_atsu	0:e8bfffbb3ab6	243	/* Assign Linker List Item value */
lynxeyed_atsu	0:e8bfffbb3ab6	244	pDMAch->DMACCLLI = GPDMAChannelConfig->DMALLI;
lynxeyed_atsu	0:e8bfffbb3ab6	245
lynxeyed_atsu	0:e8bfffbb3ab6	246	/* Set value to Channel Control Registers */
lynxeyed_atsu	0:e8bfffbb3ab6	247	switch (GPDMAChannelConfig->TransferType)
lynxeyed_atsu	0:e8bfffbb3ab6	248	{
lynxeyed_atsu	0:e8bfffbb3ab6	249	// Memory to memory
lynxeyed_atsu	0:e8bfffbb3ab6	250	case GPDMA_TRANSFERTYPE_M2M:
lynxeyed_atsu	0:e8bfffbb3ab6	251	// Assign physical source and destination address
lynxeyed_atsu	0:e8bfffbb3ab6	252	pDMAch->DMACCSrcAddr = GPDMAChannelConfig->SrcMemAddr;
lynxeyed_atsu	0:e8bfffbb3ab6	253	pDMAch->DMACCDestAddr = GPDMAChannelConfig->DstMemAddr;
lynxeyed_atsu	0:e8bfffbb3ab6	254	pDMAch->DMACCControl
lynxeyed_atsu	0:e8bfffbb3ab6	255	= GPDMA_DMACCxControl_TransferSize(GPDMAChannelConfig->TransferSize) \
lynxeyed_atsu	0:e8bfffbb3ab6	256	\| GPDMA_DMACCxControl_SBSize(GPDMA_BSIZE_32) \
lynxeyed_atsu	0:e8bfffbb3ab6	257	\| GPDMA_DMACCxControl_DBSize(GPDMA_BSIZE_32) \
lynxeyed_atsu	0:e8bfffbb3ab6	258	\| GPDMA_DMACCxControl_SWidth(GPDMAChannelConfig->TransferWidth) \
lynxeyed_atsu	0:e8bfffbb3ab6	259	\| GPDMA_DMACCxControl_DWidth(GPDMAChannelConfig->TransferWidth) \
lynxeyed_atsu	0:e8bfffbb3ab6	260	\| GPDMA_DMACCxControl_SI \
lynxeyed_atsu	0:e8bfffbb3ab6	261	\| GPDMA_DMACCxControl_DI \
lynxeyed_atsu	0:e8bfffbb3ab6	262	\| GPDMA_DMACCxControl_I;
lynxeyed_atsu	0:e8bfffbb3ab6	263	break;
lynxeyed_atsu	0:e8bfffbb3ab6	264	// Memory to peripheral
lynxeyed_atsu	0:e8bfffbb3ab6	265	case GPDMA_TRANSFERTYPE_M2P:
lynxeyed_atsu	0:e8bfffbb3ab6	266	// Assign physical source
lynxeyed_atsu	0:e8bfffbb3ab6	267	pDMAch->DMACCSrcAddr = GPDMAChannelConfig->SrcMemAddr;
lynxeyed_atsu	0:e8bfffbb3ab6	268	// Assign peripheral destination address
lynxeyed_atsu	0:e8bfffbb3ab6	269	pDMAch->DMACCDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];
lynxeyed_atsu	0:e8bfffbb3ab6	270	pDMAch->DMACCControl
lynxeyed_atsu	0:e8bfffbb3ab6	271	= GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
lynxeyed_atsu	0:e8bfffbb3ab6	272	\| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
lynxeyed_atsu	0:e8bfffbb3ab6	273	\| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
lynxeyed_atsu	0:e8bfffbb3ab6	274	\| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
lynxeyed_atsu	0:e8bfffbb3ab6	275	\| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
lynxeyed_atsu	0:e8bfffbb3ab6	276	\| GPDMA_DMACCxControl_SI \
lynxeyed_atsu	0:e8bfffbb3ab6	277	\| GPDMA_DMACCxControl_I;
lynxeyed_atsu	0:e8bfffbb3ab6	278	break;
lynxeyed_atsu	0:e8bfffbb3ab6	279	// Peripheral to memory
lynxeyed_atsu	0:e8bfffbb3ab6	280	case GPDMA_TRANSFERTYPE_P2M:
lynxeyed_atsu	0:e8bfffbb3ab6	281	// Assign peripheral source address
lynxeyed_atsu	0:e8bfffbb3ab6	282	pDMAch->DMACCSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];
lynxeyed_atsu	0:e8bfffbb3ab6	283	// Assign memory destination address
lynxeyed_atsu	0:e8bfffbb3ab6	284	pDMAch->DMACCDestAddr = GPDMAChannelConfig->DstMemAddr;
lynxeyed_atsu	0:e8bfffbb3ab6	285	pDMAch->DMACCControl
lynxeyed_atsu	0:e8bfffbb3ab6	286	= GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
lynxeyed_atsu	0:e8bfffbb3ab6	287	\| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
lynxeyed_atsu	0:e8bfffbb3ab6	288	\| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
lynxeyed_atsu	0:e8bfffbb3ab6	289	\| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
lynxeyed_atsu	0:e8bfffbb3ab6	290	\| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
lynxeyed_atsu	0:e8bfffbb3ab6	291	\| GPDMA_DMACCxControl_DI \
lynxeyed_atsu	0:e8bfffbb3ab6	292	\| GPDMA_DMACCxControl_I;
lynxeyed_atsu	0:e8bfffbb3ab6	293	break;
lynxeyed_atsu	0:e8bfffbb3ab6	294	// Peripheral to peripheral
lynxeyed_atsu	0:e8bfffbb3ab6	295	case GPDMA_TRANSFERTYPE_P2P:
lynxeyed_atsu	0:e8bfffbb3ab6	296	// Assign peripheral source address
lynxeyed_atsu	0:e8bfffbb3ab6	297	pDMAch->DMACCSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];
lynxeyed_atsu	0:e8bfffbb3ab6	298	// Assign peripheral destination address
lynxeyed_atsu	0:e8bfffbb3ab6	299	pDMAch->DMACCDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];
lynxeyed_atsu	0:e8bfffbb3ab6	300	pDMAch->DMACCControl
lynxeyed_atsu	0:e8bfffbb3ab6	301	= GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
lynxeyed_atsu	0:e8bfffbb3ab6	302	\| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
lynxeyed_atsu	0:e8bfffbb3ab6	303	\| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
lynxeyed_atsu	0:e8bfffbb3ab6	304	\| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
lynxeyed_atsu	0:e8bfffbb3ab6	305	\| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
lynxeyed_atsu	0:e8bfffbb3ab6	306	\| GPDMA_DMACCxControl_I;
lynxeyed_atsu	0:e8bfffbb3ab6	307	break;
lynxeyed_atsu	0:e8bfffbb3ab6	308	// Do not support any more transfer type, return ERROR
lynxeyed_atsu	0:e8bfffbb3ab6	309	default:
lynxeyed_atsu	0:e8bfffbb3ab6	310	return ERROR;
lynxeyed_atsu	0:e8bfffbb3ab6	311	}
lynxeyed_atsu	0:e8bfffbb3ab6	312
lynxeyed_atsu	0:e8bfffbb3ab6	313	/* Re-Configure DMA Request Select for source peripheral */
lynxeyed_atsu	0:e8bfffbb3ab6	314	if (GPDMAChannelConfig->SrcConn > 15)
lynxeyed_atsu	0:e8bfffbb3ab6	315	{
lynxeyed_atsu	0:e8bfffbb3ab6	316	DMAREQSEL \|= (1<<(GPDMAChannelConfig->SrcConn - 16));
lynxeyed_atsu	0:e8bfffbb3ab6	317	} else {
lynxeyed_atsu	0:e8bfffbb3ab6	318	DMAREQSEL &= ~(1<<(GPDMAChannelConfig->SrcConn - 8));
lynxeyed_atsu	0:e8bfffbb3ab6	319	}
lynxeyed_atsu	0:e8bfffbb3ab6	320
lynxeyed_atsu	0:e8bfffbb3ab6	321	/* Re-Configure DMA Request Select for Destination peripheral */
lynxeyed_atsu	0:e8bfffbb3ab6	322	if (GPDMAChannelConfig->DstConn > 15)
lynxeyed_atsu	0:e8bfffbb3ab6	323	{
lynxeyed_atsu	0:e8bfffbb3ab6	324	DMAREQSEL \|= (1<<(GPDMAChannelConfig->DstConn - 16));
lynxeyed_atsu	0:e8bfffbb3ab6	325	} else {
lynxeyed_atsu	0:e8bfffbb3ab6	326	DMAREQSEL &= ~(1<<(GPDMAChannelConfig->DstConn - 8));
lynxeyed_atsu	0:e8bfffbb3ab6	327	}
lynxeyed_atsu	0:e8bfffbb3ab6	328
lynxeyed_atsu	0:e8bfffbb3ab6	329	/* Enable DMA channels, little endian */
lynxeyed_atsu	0:e8bfffbb3ab6	330	LPC_GPDMA->DMACConfig = GPDMA_DMACConfig_E;
lynxeyed_atsu	0:e8bfffbb3ab6	331	while (!(LPC_GPDMA->DMACConfig & GPDMA_DMACConfig_E));
lynxeyed_atsu	0:e8bfffbb3ab6	332
lynxeyed_atsu	0:e8bfffbb3ab6	333	// Calculate absolute value for Connection number
lynxeyed_atsu	0:e8bfffbb3ab6	334	tmp1 = GPDMAChannelConfig->SrcConn;
lynxeyed_atsu	0:e8bfffbb3ab6	335	tmp1 = ((tmp1 > 15) ? (tmp1 - 8) : tmp1);
lynxeyed_atsu	0:e8bfffbb3ab6	336	tmp2 = GPDMAChannelConfig->DstConn;
lynxeyed_atsu	0:e8bfffbb3ab6	337	tmp2 = ((tmp2 > 15) ? (tmp2 - 8) : tmp2);
lynxeyed_atsu	0:e8bfffbb3ab6	338
lynxeyed_atsu	0:e8bfffbb3ab6	339	// Configure DMA Channel, enable Error Counter and Terminate counter
lynxeyed_atsu	0:e8bfffbb3ab6	340	pDMAch->DMACCConfig = GPDMA_DMACCxConfig_IE \| GPDMA_DMACCxConfig_ITC /\| GPDMA_DMACCxConfig_E/ \
lynxeyed_atsu	0:e8bfffbb3ab6	341	\| GPDMA_DMACCxConfig_TransferType((uint32_t)GPDMAChannelConfig->TransferType) \
lynxeyed_atsu	0:e8bfffbb3ab6	342	\| GPDMA_DMACCxConfig_SrcPeripheral(tmp1) \
lynxeyed_atsu	0:e8bfffbb3ab6	343	\| GPDMA_DMACCxConfig_DestPeripheral(tmp2);
lynxeyed_atsu	0:e8bfffbb3ab6	344
lynxeyed_atsu	0:e8bfffbb3ab6	345	return SUCCESS;
lynxeyed_atsu	0:e8bfffbb3ab6	346	}
lynxeyed_atsu	0:e8bfffbb3ab6	347
lynxeyed_atsu	0:e8bfffbb3ab6	348
lynxeyed_atsu	0:e8bfffbb3ab6	349	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	350	* @brief Enable/Disable DMA channel
lynxeyed_atsu	0:e8bfffbb3ab6	351	* @param[in] channelNum GPDMA channel, should be in range from 0 to 7
lynxeyed_atsu	0:e8bfffbb3ab6	352	* @param[in] NewState New State of this command, should be:
lynxeyed_atsu	0:e8bfffbb3ab6	353	* - ENABLE.
lynxeyed_atsu	0:e8bfffbb3ab6	354	* - DISABLE.
lynxeyed_atsu	0:e8bfffbb3ab6	355	* @return None
lynxeyed_atsu	0:e8bfffbb3ab6	356	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	357	void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState)
lynxeyed_atsu	0:e8bfffbb3ab6	358	{
lynxeyed_atsu	0:e8bfffbb3ab6	359	LPC_GPDMACH_TypeDef *pDMAch;
lynxeyed_atsu	0:e8bfffbb3ab6	360
lynxeyed_atsu	0:e8bfffbb3ab6	361	// Get Channel pointer
lynxeyed_atsu	0:e8bfffbb3ab6	362	pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[channelNum];
lynxeyed_atsu	0:e8bfffbb3ab6	363
lynxeyed_atsu	0:e8bfffbb3ab6	364	if (NewState == ENABLE) {
lynxeyed_atsu	0:e8bfffbb3ab6	365	pDMAch->DMACCConfig \|= GPDMA_DMACCxConfig_E;
lynxeyed_atsu	0:e8bfffbb3ab6	366	} else {
lynxeyed_atsu	0:e8bfffbb3ab6	367	pDMAch->DMACCConfig &= ~GPDMA_DMACCxConfig_E;
lynxeyed_atsu	0:e8bfffbb3ab6	368	}
lynxeyed_atsu	0:e8bfffbb3ab6	369	}
lynxeyed_atsu	0:e8bfffbb3ab6	370	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	371	* @brief Check if corresponding channel does have an active interrupt
lynxeyed_atsu	0:e8bfffbb3ab6	372	* request or not
lynxeyed_atsu	0:e8bfffbb3ab6	373	* @param[in] type type of status, should be:
lynxeyed_atsu	0:e8bfffbb3ab6	374	* - GPDMA_STAT_INT: GPDMA Interrupt Status
lynxeyed_atsu	0:e8bfffbb3ab6	375	* - GPDMA_STAT_INTTC: GPDMA Interrupt Terminal Count Request Status
lynxeyed_atsu	0:e8bfffbb3ab6	376	* - GPDMA_STAT_INTERR: GPDMA Interrupt Error Status
lynxeyed_atsu	0:e8bfffbb3ab6	377	* - GPDMA_STAT_RAWINTTC: GPDMA Raw Interrupt Terminal Count Status
lynxeyed_atsu	0:e8bfffbb3ab6	378	* - GPDMA_STAT_RAWINTERR: GPDMA Raw Error Interrupt Status
lynxeyed_atsu	0:e8bfffbb3ab6	379	* - GPDMA_STAT_ENABLED_CH:GPDMA Enabled Channel Status
lynxeyed_atsu	0:e8bfffbb3ab6	380	* @param[in] channel GPDMA channel, should be in range from 0 to 7
lynxeyed_atsu	0:e8bfffbb3ab6	381	* @return IntStatus status of DMA channel interrupt after masking
lynxeyed_atsu	0:e8bfffbb3ab6	382	* Should be:
lynxeyed_atsu	0:e8bfffbb3ab6	383	* - SET: the corresponding channel has no active interrupt request
lynxeyed_atsu	0:e8bfffbb3ab6	384	* - RESET: the corresponding channel does have an active interrupt request
lynxeyed_atsu	0:e8bfffbb3ab6	385	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	386	IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel)
lynxeyed_atsu	0:e8bfffbb3ab6	387	{
lynxeyed_atsu	0:e8bfffbb3ab6	388	CHECK_PARAM(PARAM_GPDMA_STAT(type));
lynxeyed_atsu	0:e8bfffbb3ab6	389	CHECK_PARAM(PARAM_GPDMA_CHANNEL(channel));
lynxeyed_atsu	0:e8bfffbb3ab6	390
lynxeyed_atsu	0:e8bfffbb3ab6	391	switch (type)
lynxeyed_atsu	0:e8bfffbb3ab6	392	{
lynxeyed_atsu	0:e8bfffbb3ab6	393	case GPDMA_STAT_INT: //check status of DMA channel interrupts
lynxeyed_atsu	0:e8bfffbb3ab6	394	if (LPC_GPDMA->DMACIntStat & (GPDMA_DMACIntStat_Ch(channel)))
lynxeyed_atsu	0:e8bfffbb3ab6	395	return SET;
lynxeyed_atsu	0:e8bfffbb3ab6	396	return RESET;
lynxeyed_atsu	0:e8bfffbb3ab6	397	case GPDMA_STAT_INTTC: // check terminal count interrupt request status for DMA
lynxeyed_atsu	0:e8bfffbb3ab6	398	if (LPC_GPDMA->DMACIntTCStat & GPDMA_DMACIntTCStat_Ch(channel))
lynxeyed_atsu	0:e8bfffbb3ab6	399	return SET;
lynxeyed_atsu	0:e8bfffbb3ab6	400	return RESET;
lynxeyed_atsu	0:e8bfffbb3ab6	401	case GPDMA_STAT_INTERR: //check interrupt status for DMA channels
lynxeyed_atsu	0:e8bfffbb3ab6	402	if (LPC_GPDMA->DMACIntErrStat & GPDMA_DMACIntTCClear_Ch(channel))
lynxeyed_atsu	0:e8bfffbb3ab6	403	return SET;
lynxeyed_atsu	0:e8bfffbb3ab6	404	return RESET;
lynxeyed_atsu	0:e8bfffbb3ab6	405	case GPDMA_STAT_RAWINTTC: //check status of the terminal count interrupt for DMA channels
lynxeyed_atsu	0:e8bfffbb3ab6	406	if (LPC_GPDMA->DMACRawIntErrStat & GPDMA_DMACRawIntTCStat_Ch(channel))
lynxeyed_atsu	0:e8bfffbb3ab6	407	return SET;
lynxeyed_atsu	0:e8bfffbb3ab6	408	return RESET;
lynxeyed_atsu	0:e8bfffbb3ab6	409	case GPDMA_STAT_RAWINTERR: //check status of the error interrupt for DMA channels
lynxeyed_atsu	0:e8bfffbb3ab6	410	if (LPC_GPDMA->DMACRawIntTCStat & GPDMA_DMACRawIntErrStat_Ch(channel))
lynxeyed_atsu	0:e8bfffbb3ab6	411	return SET;
lynxeyed_atsu	0:e8bfffbb3ab6	412	return RESET;
lynxeyed_atsu	0:e8bfffbb3ab6	413	default: //check enable status for DMA channels
lynxeyed_atsu	0:e8bfffbb3ab6	414	if (LPC_GPDMA->DMACEnbldChns & GPDMA_DMACEnbldChns_Ch(channel))
lynxeyed_atsu	0:e8bfffbb3ab6	415	return SET;
lynxeyed_atsu	0:e8bfffbb3ab6	416	return RESET;
lynxeyed_atsu	0:e8bfffbb3ab6	417	}
lynxeyed_atsu	0:e8bfffbb3ab6	418	}
lynxeyed_atsu	0:e8bfffbb3ab6	419
lynxeyed_atsu	0:e8bfffbb3ab6	420	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	421	* @brief Clear one or more interrupt requests on DMA channels
lynxeyed_atsu	0:e8bfffbb3ab6	422	* @param[in] type type of interrupt request, should be:
lynxeyed_atsu	0:e8bfffbb3ab6	423	* - GPDMA_STATCLR_INTTC: GPDMA Interrupt Terminal Count Request Clear
lynxeyed_atsu	0:e8bfffbb3ab6	424	* - GPDMA_STATCLR_INTERR: GPDMA Interrupt Error Clear
lynxeyed_atsu	0:e8bfffbb3ab6	425	* @param[in] channel GPDMA channel, should be in range from 0 to 7
lynxeyed_atsu	0:e8bfffbb3ab6	426	* @return None
lynxeyed_atsu	0:e8bfffbb3ab6	427	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	428	void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel)
lynxeyed_atsu	0:e8bfffbb3ab6	429	{
lynxeyed_atsu	0:e8bfffbb3ab6	430	CHECK_PARAM(PARAM_GPDMA_STATCLR(type));
lynxeyed_atsu	0:e8bfffbb3ab6	431	CHECK_PARAM(PARAM_GPDMA_CHANNEL(channel));
lynxeyed_atsu	0:e8bfffbb3ab6	432
lynxeyed_atsu	0:e8bfffbb3ab6	433	if (type == GPDMA_STATCLR_INTTC) // clears the terminal count interrupt request on DMA channel
lynxeyed_atsu	0:e8bfffbb3ab6	434	LPC_GPDMA->DMACIntTCClear = GPDMA_DMACIntTCClear_Ch(channel);
lynxeyed_atsu	0:e8bfffbb3ab6	435	else // clear the error interrupt request
lynxeyed_atsu	0:e8bfffbb3ab6	436	LPC_GPDMA->DMACIntErrClr = GPDMA_DMACIntErrClr_Ch(channel);
lynxeyed_atsu	0:e8bfffbb3ab6	437	}
lynxeyed_atsu	0:e8bfffbb3ab6	438
lynxeyed_atsu	0:e8bfffbb3ab6	439	/**
lynxeyed_atsu	0:e8bfffbb3ab6	440	* @}
lynxeyed_atsu	0:e8bfffbb3ab6	441	*/
lynxeyed_atsu	0:e8bfffbb3ab6	442
lynxeyed_atsu	0:e8bfffbb3ab6	443	#endif /* _GPDMA */
lynxeyed_atsu	0:e8bfffbb3ab6	444
lynxeyed_atsu	0:e8bfffbb3ab6	445	/**
lynxeyed_atsu	0:e8bfffbb3ab6	446	* @}
lynxeyed_atsu	0:e8bfffbb3ab6	447	*/
lynxeyed_atsu	0:e8bfffbb3ab6	448
lynxeyed_atsu	0:e8bfffbb3ab6	449	/* --------------------------------- End Of File ------------------------------ */

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	26 Feb 2011
Imports:	12
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	1

I2S_Example/lpc17xx_gpdma.c@0:e8bfffbb3ab6, 2011-02-26 (annotated)

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