DMA_LLI_TEST - LINKED LIST TEST on mbed

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xeye_ atsu / Mbed 2 deprecated DMA_LLI_TEST

LINKED LIST TEST on mbed

I2S_Example/lpc17xx_clkpwr.h@0:e8bfffbb3ab6, 2011-02-26 (annotated)

Committer:: lynxeyed_atsu
Date:: Sat Feb 26 03:55:12 2011 +0000
Revision:: 0:e8bfffbb3ab6

Who changed what in which revision?

User	Revision	Line number	New contents of line
lynxeyed_atsu	0:e8bfffbb3ab6	1	/*********************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	2	* @file lpc17xx_clkpwr.h
lynxeyed_atsu	0:e8bfffbb3ab6	3	* @brief Contains all macro definitions and function prototypes
lynxeyed_atsu	0:e8bfffbb3ab6	4	* support for Clock and Power Control firmware library on LPC17xx
lynxeyed_atsu	0:e8bfffbb3ab6	5	* @version 2.0
lynxeyed_atsu	0:e8bfffbb3ab6	6	* @date 21. May. 2010
lynxeyed_atsu	0:e8bfffbb3ab6	7	* @author NXP MCU SW Application Team
lynxeyed_atsu	0:e8bfffbb3ab6	8	**************************************************************************
lynxeyed_atsu	0:e8bfffbb3ab6	9	* Software that is described herein is for illustrative purposes only
lynxeyed_atsu	0:e8bfffbb3ab6	10	* which provides customers with programming information regarding the
lynxeyed_atsu	0:e8bfffbb3ab6	11	* products. This software is supplied "AS IS" without any warranties.
lynxeyed_atsu	0:e8bfffbb3ab6	12	* NXP Semiconductors assumes no responsibility or liability for the
lynxeyed_atsu	0:e8bfffbb3ab6	13	* use of the software, conveys no license or title under any patent,
lynxeyed_atsu	0:e8bfffbb3ab6	14	* copyright, or mask work right to the product. NXP Semiconductors
lynxeyed_atsu	0:e8bfffbb3ab6	15	* reserves the right to make changes in the software without
lynxeyed_atsu	0:e8bfffbb3ab6	16	* notification. NXP Semiconductors also make no representation or
lynxeyed_atsu	0:e8bfffbb3ab6	17	* warranty that such application will be suitable for the specified
lynxeyed_atsu	0:e8bfffbb3ab6	18	* use without further testing or modification.
lynxeyed_atsu	0:e8bfffbb3ab6	19	**************************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	20
lynxeyed_atsu	0:e8bfffbb3ab6	21	/* Peripheral group ----------------------------------------------------------- */
lynxeyed_atsu	0:e8bfffbb3ab6	22	/** @defgroup CLKPWR CLKPWR
lynxeyed_atsu	0:e8bfffbb3ab6	23	* @ingroup LPC1700CMSIS_FwLib_Drivers
lynxeyed_atsu	0:e8bfffbb3ab6	24	* @{
lynxeyed_atsu	0:e8bfffbb3ab6	25	*/
lynxeyed_atsu	0:e8bfffbb3ab6	26
lynxeyed_atsu	0:e8bfffbb3ab6	27	#ifndef LPC17XX_CLKPWR_H_
lynxeyed_atsu	0:e8bfffbb3ab6	28	#define LPC17XX_CLKPWR_H_
lynxeyed_atsu	0:e8bfffbb3ab6	29
lynxeyed_atsu	0:e8bfffbb3ab6	30	/* Includes ------------------------------------------------------------------- */
lynxeyed_atsu	0:e8bfffbb3ab6	31	#include "LPC17xx.h"
lynxeyed_atsu	0:e8bfffbb3ab6	32	#include "lpc_types.h"
lynxeyed_atsu	0:e8bfffbb3ab6	33
lynxeyed_atsu	0:e8bfffbb3ab6	34	#ifdef __cplusplus
lynxeyed_atsu	0:e8bfffbb3ab6	35	extern "C"
lynxeyed_atsu	0:e8bfffbb3ab6	36	{
lynxeyed_atsu	0:e8bfffbb3ab6	37	#endif
lynxeyed_atsu	0:e8bfffbb3ab6	38
lynxeyed_atsu	0:e8bfffbb3ab6	39	/* Public Macros -------------------------------------------------------------- */
lynxeyed_atsu	0:e8bfffbb3ab6	40	/** @defgroup CLKPWR_Public_Macros CLKPWR Public Macros
lynxeyed_atsu	0:e8bfffbb3ab6	41	* @{
lynxeyed_atsu	0:e8bfffbb3ab6	42	*/
lynxeyed_atsu	0:e8bfffbb3ab6	43
lynxeyed_atsu	0:e8bfffbb3ab6	44	/**********************************************************************
lynxeyed_atsu	0:e8bfffbb3ab6	45	* Peripheral Clock Selection Definitions
lynxeyed_atsu	0:e8bfffbb3ab6	46	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	47	/** Peripheral clock divider bit position for WDT */
lynxeyed_atsu	0:e8bfffbb3ab6	48	#define CLKPWR_PCLKSEL_WDT ((uint32_t)(0))
lynxeyed_atsu	0:e8bfffbb3ab6	49	/** Peripheral clock divider bit position for TIMER0 */
lynxeyed_atsu	0:e8bfffbb3ab6	50	#define CLKPWR_PCLKSEL_TIMER0 ((uint32_t)(2))
lynxeyed_atsu	0:e8bfffbb3ab6	51	/** Peripheral clock divider bit position for TIMER1 */
lynxeyed_atsu	0:e8bfffbb3ab6	52	#define CLKPWR_PCLKSEL_TIMER1 ((uint32_t)(4))
lynxeyed_atsu	0:e8bfffbb3ab6	53	/** Peripheral clock divider bit position for UART0 */
lynxeyed_atsu	0:e8bfffbb3ab6	54	#define CLKPWR_PCLKSEL_UART0 ((uint32_t)(6))
lynxeyed_atsu	0:e8bfffbb3ab6	55	/** Peripheral clock divider bit position for UART1 */
lynxeyed_atsu	0:e8bfffbb3ab6	56	#define CLKPWR_PCLKSEL_UART1 ((uint32_t)(8))
lynxeyed_atsu	0:e8bfffbb3ab6	57	/** Peripheral clock divider bit position for PWM1 */
lynxeyed_atsu	0:e8bfffbb3ab6	58	#define CLKPWR_PCLKSEL_PWM1 ((uint32_t)(12))
lynxeyed_atsu	0:e8bfffbb3ab6	59	/** Peripheral clock divider bit position for I2C0 */
lynxeyed_atsu	0:e8bfffbb3ab6	60	#define CLKPWR_PCLKSEL_I2C0 ((uint32_t)(14))
lynxeyed_atsu	0:e8bfffbb3ab6	61	/** Peripheral clock divider bit position for SPI */
lynxeyed_atsu	0:e8bfffbb3ab6	62	#define CLKPWR_PCLKSEL_SPI ((uint32_t)(16))
lynxeyed_atsu	0:e8bfffbb3ab6	63	/** Peripheral clock divider bit position for SSP1 */
lynxeyed_atsu	0:e8bfffbb3ab6	64	#define CLKPWR_PCLKSEL_SSP1 ((uint32_t)(20))
lynxeyed_atsu	0:e8bfffbb3ab6	65	/** Peripheral clock divider bit position for DAC */
lynxeyed_atsu	0:e8bfffbb3ab6	66	#define CLKPWR_PCLKSEL_DAC ((uint32_t)(22))
lynxeyed_atsu	0:e8bfffbb3ab6	67	/** Peripheral clock divider bit position for ADC */
lynxeyed_atsu	0:e8bfffbb3ab6	68	#define CLKPWR_PCLKSEL_ADC ((uint32_t)(24))
lynxeyed_atsu	0:e8bfffbb3ab6	69	/** Peripheral clock divider bit position for CAN1 */
lynxeyed_atsu	0:e8bfffbb3ab6	70	#define CLKPWR_PCLKSEL_CAN1 ((uint32_t)(26))
lynxeyed_atsu	0:e8bfffbb3ab6	71	/** Peripheral clock divider bit position for CAN2 */
lynxeyed_atsu	0:e8bfffbb3ab6	72	#define CLKPWR_PCLKSEL_CAN2 ((uint32_t)(28))
lynxeyed_atsu	0:e8bfffbb3ab6	73	/** Peripheral clock divider bit position for ACF */
lynxeyed_atsu	0:e8bfffbb3ab6	74	#define CLKPWR_PCLKSEL_ACF ((uint32_t)(30))
lynxeyed_atsu	0:e8bfffbb3ab6	75	/** Peripheral clock divider bit position for QEI */
lynxeyed_atsu	0:e8bfffbb3ab6	76	#define CLKPWR_PCLKSEL_QEI ((uint32_t)(32))
lynxeyed_atsu	0:e8bfffbb3ab6	77	/** Peripheral clock divider bit position for PCB */
lynxeyed_atsu	0:e8bfffbb3ab6	78	#define CLKPWR_PCLKSEL_PCB ((uint32_t)(36))
lynxeyed_atsu	0:e8bfffbb3ab6	79	/** Peripheral clock divider bit position for I2C1 */
lynxeyed_atsu	0:e8bfffbb3ab6	80	#define CLKPWR_PCLKSEL_I2C1 ((uint32_t)(38))
lynxeyed_atsu	0:e8bfffbb3ab6	81	/** Peripheral clock divider bit position for SSP0 */
lynxeyed_atsu	0:e8bfffbb3ab6	82	#define CLKPWR_PCLKSEL_SSP0 ((uint32_t)(42))
lynxeyed_atsu	0:e8bfffbb3ab6	83	/** Peripheral clock divider bit position for TIMER2 */
lynxeyed_atsu	0:e8bfffbb3ab6	84	#define CLKPWR_PCLKSEL_TIMER2 ((uint32_t)(44))
lynxeyed_atsu	0:e8bfffbb3ab6	85	/** Peripheral clock divider bit position for TIMER3 */
lynxeyed_atsu	0:e8bfffbb3ab6	86	#define CLKPWR_PCLKSEL_TIMER3 ((uint32_t)(46))
lynxeyed_atsu	0:e8bfffbb3ab6	87	/** Peripheral clock divider bit position for UART2 */
lynxeyed_atsu	0:e8bfffbb3ab6	88	#define CLKPWR_PCLKSEL_UART2 ((uint32_t)(48))
lynxeyed_atsu	0:e8bfffbb3ab6	89	/** Peripheral clock divider bit position for UART3 */
lynxeyed_atsu	0:e8bfffbb3ab6	90	#define CLKPWR_PCLKSEL_UART3 ((uint32_t)(50))
lynxeyed_atsu	0:e8bfffbb3ab6	91	/** Peripheral clock divider bit position for I2C2 */
lynxeyed_atsu	0:e8bfffbb3ab6	92	#define CLKPWR_PCLKSEL_I2C2 ((uint32_t)(52))
lynxeyed_atsu	0:e8bfffbb3ab6	93	/** Peripheral clock divider bit position for I2S */
lynxeyed_atsu	0:e8bfffbb3ab6	94	#define CLKPWR_PCLKSEL_I2S ((uint32_t)(54))
lynxeyed_atsu	0:e8bfffbb3ab6	95	/** Peripheral clock divider bit position for RIT */
lynxeyed_atsu	0:e8bfffbb3ab6	96	#define CLKPWR_PCLKSEL_RIT ((uint32_t)(58))
lynxeyed_atsu	0:e8bfffbb3ab6	97	/** Peripheral clock divider bit position for SYSCON */
lynxeyed_atsu	0:e8bfffbb3ab6	98	#define CLKPWR_PCLKSEL_SYSCON ((uint32_t)(60))
lynxeyed_atsu	0:e8bfffbb3ab6	99	/** Peripheral clock divider bit position for MC */
lynxeyed_atsu	0:e8bfffbb3ab6	100	#define CLKPWR_PCLKSEL_MC ((uint32_t)(62))
lynxeyed_atsu	0:e8bfffbb3ab6	101
lynxeyed_atsu	0:e8bfffbb3ab6	102	/** Macro for Peripheral Clock Selection register bit values
lynxeyed_atsu	0:e8bfffbb3ab6	103	* Note: When CCLK_DIV_8, Peripheral�s clock is selected to
lynxeyed_atsu	0:e8bfffbb3ab6	104	* PCLK_xyz = CCLK/8 except for CAN1, CAN2, and CAN filtering
lynxeyed_atsu	0:e8bfffbb3ab6	105	* when �11�selects PCLK_xyz = CCLK/6 */
lynxeyed_atsu	0:e8bfffbb3ab6	106	/* Peripheral clock divider is set to 4 from CCLK */
lynxeyed_atsu	0:e8bfffbb3ab6	107	#define CLKPWR_PCLKSEL_CCLK_DIV_4 ((uint32_t)(0))
lynxeyed_atsu	0:e8bfffbb3ab6	108	/** Peripheral clock divider is the same with CCLK */
lynxeyed_atsu	0:e8bfffbb3ab6	109	#define CLKPWR_PCLKSEL_CCLK_DIV_1 ((uint32_t)(1))
lynxeyed_atsu	0:e8bfffbb3ab6	110	/** Peripheral clock divider is set to 2 from CCLK */
lynxeyed_atsu	0:e8bfffbb3ab6	111	#define CLKPWR_PCLKSEL_CCLK_DIV_2 ((uint32_t)(2))
lynxeyed_atsu	0:e8bfffbb3ab6	112
lynxeyed_atsu	0:e8bfffbb3ab6	113
lynxeyed_atsu	0:e8bfffbb3ab6	114	/********************************************************************
lynxeyed_atsu	0:e8bfffbb3ab6	115	* Power Control for Peripherals Definitions
lynxeyed_atsu	0:e8bfffbb3ab6	116	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	117	/** Timer/Counter 0 power/clock control bit */
lynxeyed_atsu	0:e8bfffbb3ab6	118	#define CLKPWR_PCONP_PCTIM0 ((uint32_t)(1<<1))
lynxeyed_atsu	0:e8bfffbb3ab6	119	/* Timer/Counter 1 power/clock control bit */
lynxeyed_atsu	0:e8bfffbb3ab6	120	#define CLKPWR_PCONP_PCTIM1 ((uint32_t)(1<<2))
lynxeyed_atsu	0:e8bfffbb3ab6	121	/** UART0 power/clock control bit */
lynxeyed_atsu	0:e8bfffbb3ab6	122	#define CLKPWR_PCONP_PCUART0 ((uint32_t)(1<<3))
lynxeyed_atsu	0:e8bfffbb3ab6	123	/** UART1 power/clock control bit */
lynxeyed_atsu	0:e8bfffbb3ab6	124	#define CLKPWR_PCONP_PCUART1 ((uint32_t)(1<<4))
lynxeyed_atsu	0:e8bfffbb3ab6	125	/** PWM1 power/clock control bit */
lynxeyed_atsu	0:e8bfffbb3ab6	126	#define CLKPWR_PCONP_PCPWM1 ((uint32_t)(1<<6))
lynxeyed_atsu	0:e8bfffbb3ab6	127	/** The I2C0 interface power/clock control bit */
lynxeyed_atsu	0:e8bfffbb3ab6	128	#define CLKPWR_PCONP_PCI2C0 ((uint32_t)(1<<7))
lynxeyed_atsu	0:e8bfffbb3ab6	129	/** The SPI interface power/clock control bit */
lynxeyed_atsu	0:e8bfffbb3ab6	130	#define CLKPWR_PCONP_PCSPI ((uint32_t)(1<<8))
lynxeyed_atsu	0:e8bfffbb3ab6	131	/** The RTC power/clock control bit */
lynxeyed_atsu	0:e8bfffbb3ab6	132	#define CLKPWR_PCONP_PCRTC ((uint32_t)(1<<9))
lynxeyed_atsu	0:e8bfffbb3ab6	133	/** The SSP1 interface power/clock control bit */
lynxeyed_atsu	0:e8bfffbb3ab6	134	#define CLKPWR_PCONP_PCSSP1 ((uint32_t)(1<<10))
lynxeyed_atsu	0:e8bfffbb3ab6	135	/** A/D converter 0 (ADC0) power/clock control bit */
lynxeyed_atsu	0:e8bfffbb3ab6	136	#define CLKPWR_PCONP_PCAD ((uint32_t)(1<<12))
lynxeyed_atsu	0:e8bfffbb3ab6	137	/** CAN Controller 1 power/clock control bit */
lynxeyed_atsu	0:e8bfffbb3ab6	138	#define CLKPWR_PCONP_PCAN1 ((uint32_t)(1<<13))
lynxeyed_atsu	0:e8bfffbb3ab6	139	/** CAN Controller 2 power/clock control bit */
lynxeyed_atsu	0:e8bfffbb3ab6	140	#define CLKPWR_PCONP_PCAN2 ((uint32_t)(1<<14))
lynxeyed_atsu	0:e8bfffbb3ab6	141	/** GPIO power/clock control bit */
lynxeyed_atsu	0:e8bfffbb3ab6	142	#define CLKPWR_PCONP_PCGPIO ((uint32_t)(1<<15))
lynxeyed_atsu	0:e8bfffbb3ab6	143	/** Repetitive Interrupt Timer power/clock control bit */
lynxeyed_atsu	0:e8bfffbb3ab6	144	#define CLKPWR_PCONP_PCRIT ((uint32_t)(1<<16))
lynxeyed_atsu	0:e8bfffbb3ab6	145	/** Motor Control PWM */
lynxeyed_atsu	0:e8bfffbb3ab6	146	#define CLKPWR_PCONP_PCMC ((uint32_t)(1<<17))
lynxeyed_atsu	0:e8bfffbb3ab6	147	/** Quadrature Encoder Interface power/clock control bit */
lynxeyed_atsu	0:e8bfffbb3ab6	148	#define CLKPWR_PCONP_PCQEI ((uint32_t)(1<<18))
lynxeyed_atsu	0:e8bfffbb3ab6	149	/** The I2C1 interface power/clock control bit */
lynxeyed_atsu	0:e8bfffbb3ab6	150	#define CLKPWR_PCONP_PCI2C1 ((uint32_t)(1<<19))
lynxeyed_atsu	0:e8bfffbb3ab6	151	/** The SSP0 interface power/clock control bit */
lynxeyed_atsu	0:e8bfffbb3ab6	152	#define CLKPWR_PCONP_PCSSP0 ((uint32_t)(1<<21))
lynxeyed_atsu	0:e8bfffbb3ab6	153	/** Timer 2 power/clock control bit */
lynxeyed_atsu	0:e8bfffbb3ab6	154	#define CLKPWR_PCONP_PCTIM2 ((uint32_t)(1<<22))
lynxeyed_atsu	0:e8bfffbb3ab6	155	/** Timer 3 power/clock control bit */
lynxeyed_atsu	0:e8bfffbb3ab6	156	#define CLKPWR_PCONP_PCTIM3 ((uint32_t)(1<<23))
lynxeyed_atsu	0:e8bfffbb3ab6	157	/** UART 2 power/clock control bit */
lynxeyed_atsu	0:e8bfffbb3ab6	158	#define CLKPWR_PCONP_PCUART2 ((uint32_t)(1<<24))
lynxeyed_atsu	0:e8bfffbb3ab6	159	/** UART 3 power/clock control bit */
lynxeyed_atsu	0:e8bfffbb3ab6	160	#define CLKPWR_PCONP_PCUART3 ((uint32_t)(1<<25))
lynxeyed_atsu	0:e8bfffbb3ab6	161	/** I2C interface 2 power/clock control bit */
lynxeyed_atsu	0:e8bfffbb3ab6	162	#define CLKPWR_PCONP_PCI2C2 ((uint32_t)(1<<26))
lynxeyed_atsu	0:e8bfffbb3ab6	163	/** I2S interface power/clock control bit*/
lynxeyed_atsu	0:e8bfffbb3ab6	164	#define CLKPWR_PCONP_PCI2S ((uint32_t)(1<<27))
lynxeyed_atsu	0:e8bfffbb3ab6	165	/** GP DMA function power/clock control bit*/
lynxeyed_atsu	0:e8bfffbb3ab6	166	#define CLKPWR_PCONP_PCGPDMA ((uint32_t)(1<<29))
lynxeyed_atsu	0:e8bfffbb3ab6	167	/** Ethernet block power/clock control bit*/
lynxeyed_atsu	0:e8bfffbb3ab6	168	#define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30))
lynxeyed_atsu	0:e8bfffbb3ab6	169	/** USB interface power/clock control bit*/
lynxeyed_atsu	0:e8bfffbb3ab6	170	#define CLKPWR_PCONP_PCUSB ((uint32_t)(1<<31))
lynxeyed_atsu	0:e8bfffbb3ab6	171
lynxeyed_atsu	0:e8bfffbb3ab6	172
lynxeyed_atsu	0:e8bfffbb3ab6	173	/**
lynxeyed_atsu	0:e8bfffbb3ab6	174	* @}
lynxeyed_atsu	0:e8bfffbb3ab6	175	*/
lynxeyed_atsu	0:e8bfffbb3ab6	176	/* Private Macros ------------------------------------------------------------- */
lynxeyed_atsu	0:e8bfffbb3ab6	177	/** @defgroup CLKPWR_Private_Macros CLKPWR Private Macros
lynxeyed_atsu	0:e8bfffbb3ab6	178	* @{
lynxeyed_atsu	0:e8bfffbb3ab6	179	*/
lynxeyed_atsu	0:e8bfffbb3ab6	180
lynxeyed_atsu	0:e8bfffbb3ab6	181	/* --------------------- BIT DEFINITIONS -------------------------------------- */
lynxeyed_atsu	0:e8bfffbb3ab6	182	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	183	* Macro defines for Clock Source Select Register
lynxeyed_atsu	0:e8bfffbb3ab6	184	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	185	/** Internal RC oscillator */
lynxeyed_atsu	0:e8bfffbb3ab6	186	#define CLKPWR_CLKSRCSEL_CLKSRC_IRC ((uint32_t)(0x00))
lynxeyed_atsu	0:e8bfffbb3ab6	187	/** Main oscillator */
lynxeyed_atsu	0:e8bfffbb3ab6	188	#define CLKPWR_CLKSRCSEL_CLKSRC_MAINOSC ((uint32_t)(0x01))
lynxeyed_atsu	0:e8bfffbb3ab6	189	/** RTC oscillator */
lynxeyed_atsu	0:e8bfffbb3ab6	190	#define CLKPWR_CLKSRCSEL_CLKSRC_RTC ((uint32_t)(0x02))
lynxeyed_atsu	0:e8bfffbb3ab6	191	/** Clock source selection bit mask */
lynxeyed_atsu	0:e8bfffbb3ab6	192	#define CLKPWR_CLKSRCSEL_BITMASK ((uint32_t)(0x03))
lynxeyed_atsu	0:e8bfffbb3ab6	193
lynxeyed_atsu	0:e8bfffbb3ab6	194	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	195	* Macro defines for Clock Output Configuration Register
lynxeyed_atsu	0:e8bfffbb3ab6	196	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	197	/* Clock Output Configuration register definition */
lynxeyed_atsu	0:e8bfffbb3ab6	198	/** Selects the CPU clock as the CLKOUT source */
lynxeyed_atsu	0:e8bfffbb3ab6	199	#define CLKPWR_CLKOUTCFG_CLKOUTSEL_CPU ((uint32_t)(0x00))
lynxeyed_atsu	0:e8bfffbb3ab6	200	/** Selects the main oscillator as the CLKOUT source */
lynxeyed_atsu	0:e8bfffbb3ab6	201	#define CLKPWR_CLKOUTCFG_CLKOUTSEL_MAINOSC ((uint32_t)(0x01))
lynxeyed_atsu	0:e8bfffbb3ab6	202	/** Selects the Internal RC oscillator as the CLKOUT source */
lynxeyed_atsu	0:e8bfffbb3ab6	203	#define CLKPWR_CLKOUTCFG_CLKOUTSEL_RC ((uint32_t)(0x02))
lynxeyed_atsu	0:e8bfffbb3ab6	204	/** Selects the USB clock as the CLKOUT source */
lynxeyed_atsu	0:e8bfffbb3ab6	205	#define CLKPWR_CLKOUTCFG_CLKOUTSEL_USB ((uint32_t)(0x03))
lynxeyed_atsu	0:e8bfffbb3ab6	206	/** Selects the RTC oscillator as the CLKOUT source */
lynxeyed_atsu	0:e8bfffbb3ab6	207	#define CLKPWR_CLKOUTCFG_CLKOUTSEL_RTC ((uint32_t)(0x04))
lynxeyed_atsu	0:e8bfffbb3ab6	208	/** Integer value to divide the output clock by, minus one */
lynxeyed_atsu	0:e8bfffbb3ab6	209	#define CLKPWR_CLKOUTCFG_CLKOUTDIV(n) ((uint32_t)((n&0x0F)<<4))
lynxeyed_atsu	0:e8bfffbb3ab6	210	/** CLKOUT enable control */
lynxeyed_atsu	0:e8bfffbb3ab6	211	#define CLKPWR_CLKOUTCFG_CLKOUT_EN ((uint32_t)(1<<8))
lynxeyed_atsu	0:e8bfffbb3ab6	212	/** CLKOUT activity indication */
lynxeyed_atsu	0:e8bfffbb3ab6	213	#define CLKPWR_CLKOUTCFG_CLKOUT_ACT ((uint32_t)(1<<9))
lynxeyed_atsu	0:e8bfffbb3ab6	214	/** Clock source selection bit mask */
lynxeyed_atsu	0:e8bfffbb3ab6	215	#define CLKPWR_CLKOUTCFG_BITMASK ((uint32_t)(0x3FF))
lynxeyed_atsu	0:e8bfffbb3ab6	216
lynxeyed_atsu	0:e8bfffbb3ab6	217	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	218	* Macro defines for PPL0 Control Register
lynxeyed_atsu	0:e8bfffbb3ab6	219	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	220	/** PLL 0 control enable */
lynxeyed_atsu	0:e8bfffbb3ab6	221	#define CLKPWR_PLL0CON_ENABLE ((uint32_t)(0x01))
lynxeyed_atsu	0:e8bfffbb3ab6	222	/** PLL 0 control connect */
lynxeyed_atsu	0:e8bfffbb3ab6	223	#define CLKPWR_PLL0CON_CONNECT ((uint32_t)(0x02))
lynxeyed_atsu	0:e8bfffbb3ab6	224	/** PLL 0 control bit mask */
lynxeyed_atsu	0:e8bfffbb3ab6	225	#define CLKPWR_PLL0CON_BITMASK ((uint32_t)(0x03))
lynxeyed_atsu	0:e8bfffbb3ab6	226
lynxeyed_atsu	0:e8bfffbb3ab6	227	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	228	* Macro defines for PPL0 Configuration Register
lynxeyed_atsu	0:e8bfffbb3ab6	229	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	230	/** PLL 0 Configuration MSEL field */
lynxeyed_atsu	0:e8bfffbb3ab6	231	#define CLKPWR_PLL0CFG_MSEL(n) ((uint32_t)(n&0x7FFF))
lynxeyed_atsu	0:e8bfffbb3ab6	232	/** PLL 0 Configuration NSEL field */
lynxeyed_atsu	0:e8bfffbb3ab6	233	#define CLKPWR_PLL0CFG_NSEL(n) ((uint32_t)((n<<16)&0xFF0000))
lynxeyed_atsu	0:e8bfffbb3ab6	234	/** PLL 0 Configuration bit mask */
lynxeyed_atsu	0:e8bfffbb3ab6	235	#define CLKPWR_PLL0CFG_BITMASK ((uint32_t)(0xFF7FFF))
lynxeyed_atsu	0:e8bfffbb3ab6	236
lynxeyed_atsu	0:e8bfffbb3ab6	237
lynxeyed_atsu	0:e8bfffbb3ab6	238	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	239	* Macro defines for PPL0 Status Register
lynxeyed_atsu	0:e8bfffbb3ab6	240	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	241	/** PLL 0 MSEL value */
lynxeyed_atsu	0:e8bfffbb3ab6	242	#define CLKPWR_PLL0STAT_MSEL(n) ((uint32_t)(n&0x7FFF))
lynxeyed_atsu	0:e8bfffbb3ab6	243	/** PLL NSEL get value */
lynxeyed_atsu	0:e8bfffbb3ab6	244	#define CLKPWR_PLL0STAT_NSEL(n) ((uint32_t)((n>>16)&0xFF))
lynxeyed_atsu	0:e8bfffbb3ab6	245	/** PLL status enable bit */
lynxeyed_atsu	0:e8bfffbb3ab6	246	#define CLKPWR_PLL0STAT_PLLE ((uint32_t)(1<<24))
lynxeyed_atsu	0:e8bfffbb3ab6	247	/** PLL status Connect bit */
lynxeyed_atsu	0:e8bfffbb3ab6	248	#define CLKPWR_PLL0STAT_PLLC ((uint32_t)(1<<25))
lynxeyed_atsu	0:e8bfffbb3ab6	249	/** PLL status lock */
lynxeyed_atsu	0:e8bfffbb3ab6	250	#define CLKPWR_PLL0STAT_PLOCK ((uint32_t)(1<<26))
lynxeyed_atsu	0:e8bfffbb3ab6	251
lynxeyed_atsu	0:e8bfffbb3ab6	252	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	253	* Macro defines for PPL0 Feed Register
lynxeyed_atsu	0:e8bfffbb3ab6	254	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	255	/** PLL0 Feed bit mask */
lynxeyed_atsu	0:e8bfffbb3ab6	256	#define CLKPWR_PLL0FEED_BITMASK ((uint32_t)0xFF)
lynxeyed_atsu	0:e8bfffbb3ab6	257
lynxeyed_atsu	0:e8bfffbb3ab6	258	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	259	* Macro defines for PLL1 Control Register
lynxeyed_atsu	0:e8bfffbb3ab6	260	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	261	/** USB PLL control enable */
lynxeyed_atsu	0:e8bfffbb3ab6	262	#define CLKPWR_PLL1CON_ENABLE ((uint32_t)(0x01))
lynxeyed_atsu	0:e8bfffbb3ab6	263	/** USB PLL control connect */
lynxeyed_atsu	0:e8bfffbb3ab6	264	#define CLKPWR_PLL1CON_CONNECT ((uint32_t)(0x02))
lynxeyed_atsu	0:e8bfffbb3ab6	265	/** USB PLL control bit mask */
lynxeyed_atsu	0:e8bfffbb3ab6	266	#define CLKPWR_PLL1CON_BITMASK ((uint32_t)(0x03))
lynxeyed_atsu	0:e8bfffbb3ab6	267
lynxeyed_atsu	0:e8bfffbb3ab6	268	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	269	* Macro defines for PLL1 Configuration Register
lynxeyed_atsu	0:e8bfffbb3ab6	270	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	271	/** USB PLL MSEL set value */
lynxeyed_atsu	0:e8bfffbb3ab6	272	#define CLKPWR_PLL1CFG_MSEL(n) ((uint32_t)(n&0x1F))
lynxeyed_atsu	0:e8bfffbb3ab6	273	/** USB PLL PSEL set value */
lynxeyed_atsu	0:e8bfffbb3ab6	274	#define CLKPWR_PLL1CFG_PSEL(n) ((uint32_t)((n&0x03)<<5))
lynxeyed_atsu	0:e8bfffbb3ab6	275	/** USB PLL configuration bit mask */
lynxeyed_atsu	0:e8bfffbb3ab6	276	#define CLKPWR_PLL1CFG_BITMASK ((uint32_t)(0x7F))
lynxeyed_atsu	0:e8bfffbb3ab6	277
lynxeyed_atsu	0:e8bfffbb3ab6	278	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	279	* Macro defines for PLL1 Status Register
lynxeyed_atsu	0:e8bfffbb3ab6	280	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	281	/** USB PLL MSEL get value */
lynxeyed_atsu	0:e8bfffbb3ab6	282	#define CLKPWR_PLL1STAT_MSEL(n) ((uint32_t)(n&0x1F))
lynxeyed_atsu	0:e8bfffbb3ab6	283	/** USB PLL PSEL get value */
lynxeyed_atsu	0:e8bfffbb3ab6	284	#define CLKPWR_PLL1STAT_PSEL(n) ((uint32_t)((n>>5)&0x03))
lynxeyed_atsu	0:e8bfffbb3ab6	285	/** USB PLL status enable bit */
lynxeyed_atsu	0:e8bfffbb3ab6	286	#define CLKPWR_PLL1STAT_PLLE ((uint32_t)(1<<8))
lynxeyed_atsu	0:e8bfffbb3ab6	287	/** USB PLL status Connect bit */
lynxeyed_atsu	0:e8bfffbb3ab6	288	#define CLKPWR_PLL1STAT_PLLC ((uint32_t)(1<<9))
lynxeyed_atsu	0:e8bfffbb3ab6	289	/** USB PLL status lock */
lynxeyed_atsu	0:e8bfffbb3ab6	290	#define CLKPWR_PLL1STAT_PLOCK ((uint32_t)(1<<10))
lynxeyed_atsu	0:e8bfffbb3ab6	291
lynxeyed_atsu	0:e8bfffbb3ab6	292	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	293	* Macro defines for PLL1 Feed Register
lynxeyed_atsu	0:e8bfffbb3ab6	294	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	295	/** PLL1 Feed bit mask */
lynxeyed_atsu	0:e8bfffbb3ab6	296	#define CLKPWR_PLL1FEED_BITMASK ((uint32_t)0xFF)
lynxeyed_atsu	0:e8bfffbb3ab6	297
lynxeyed_atsu	0:e8bfffbb3ab6	298	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	299	* Macro defines for CPU Clock Configuration Register
lynxeyed_atsu	0:e8bfffbb3ab6	300	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	301	/** CPU Clock configuration bit mask */
lynxeyed_atsu	0:e8bfffbb3ab6	302	#define CLKPWR_CCLKCFG_BITMASK ((uint32_t)(0xFF))
lynxeyed_atsu	0:e8bfffbb3ab6	303
lynxeyed_atsu	0:e8bfffbb3ab6	304	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	305	* Macro defines for USB Clock Configuration Register
lynxeyed_atsu	0:e8bfffbb3ab6	306	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	307	/** USB Clock Configuration bit mask */
lynxeyed_atsu	0:e8bfffbb3ab6	308	#define CLKPWR_USBCLKCFG_BITMASK ((uint32_t)(0x0F))
lynxeyed_atsu	0:e8bfffbb3ab6	309
lynxeyed_atsu	0:e8bfffbb3ab6	310	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	311	* Macro defines for IRC Trim Register
lynxeyed_atsu	0:e8bfffbb3ab6	312	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	313	/** IRC Trim bit mask */
lynxeyed_atsu	0:e8bfffbb3ab6	314	#define CLKPWR_IRCTRIM_BITMASK ((uint32_t)(0x0F))
lynxeyed_atsu	0:e8bfffbb3ab6	315
lynxeyed_atsu	0:e8bfffbb3ab6	316	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	317	* Macro defines for Peripheral Clock Selection Register 0 and 1
lynxeyed_atsu	0:e8bfffbb3ab6	318	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	319	/** Peripheral Clock Selection 0 mask bit */
lynxeyed_atsu	0:e8bfffbb3ab6	320	#define CLKPWR_PCLKSEL0_BITMASK ((uint32_t)(0xFFF3F3FF))
lynxeyed_atsu	0:e8bfffbb3ab6	321	/** Peripheral Clock Selection 1 mask bit */
lynxeyed_atsu	0:e8bfffbb3ab6	322	#define CLKPWR_PCLKSEL1_BITMASK ((uint32_t)(0xFCF3F0F3))
lynxeyed_atsu	0:e8bfffbb3ab6	323	/** Macro to set peripheral clock of each type
lynxeyed_atsu	0:e8bfffbb3ab6	324	* p: position of two bits that hold divider of peripheral clock
lynxeyed_atsu	0:e8bfffbb3ab6	325	* n: value of divider of peripheral clock to be set */
lynxeyed_atsu	0:e8bfffbb3ab6	326	#define CLKPWR_PCLKSEL_SET(p,n) _SBF(p,n)
lynxeyed_atsu	0:e8bfffbb3ab6	327	/** Macro to mask peripheral clock of each type */
lynxeyed_atsu	0:e8bfffbb3ab6	328	#define CLKPWR_PCLKSEL_BITMASK(p) _SBF(p,0x03)
lynxeyed_atsu	0:e8bfffbb3ab6	329	/** Macro to get peripheral clock of each type */
lynxeyed_atsu	0:e8bfffbb3ab6	330	#define CLKPWR_PCLKSEL_GET(p, n) ((uint32_t)((n>>p)&0x03))
lynxeyed_atsu	0:e8bfffbb3ab6	331
lynxeyed_atsu	0:e8bfffbb3ab6	332	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	333	* Macro defines for Power Mode Control Register
lynxeyed_atsu	0:e8bfffbb3ab6	334	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	335	/** Power mode control bit 0 */
lynxeyed_atsu	0:e8bfffbb3ab6	336	#define CLKPWR_PCON_PM0 ((uint32_t)(1<<0))
lynxeyed_atsu	0:e8bfffbb3ab6	337	/** Power mode control bit 1 */
lynxeyed_atsu	0:e8bfffbb3ab6	338	#define CLKPWR_PCON_PM1 ((uint32_t)(1<<1))
lynxeyed_atsu	0:e8bfffbb3ab6	339	/** Brown-Out Reduced Power Mode */
lynxeyed_atsu	0:e8bfffbb3ab6	340	#define CLKPWR_PCON_BODPDM ((uint32_t)(1<<2))
lynxeyed_atsu	0:e8bfffbb3ab6	341	/** Brown-Out Global Disable */
lynxeyed_atsu	0:e8bfffbb3ab6	342	#define CLKPWR_PCON_BOGD ((uint32_t)(1<<3))
lynxeyed_atsu	0:e8bfffbb3ab6	343	/** Brown Out Reset Disable */
lynxeyed_atsu	0:e8bfffbb3ab6	344	#define CLKPWR_PCON_BORD ((uint32_t)(1<<4))
lynxeyed_atsu	0:e8bfffbb3ab6	345	/** Sleep Mode entry flag */
lynxeyed_atsu	0:e8bfffbb3ab6	346	#define CLKPWR_PCON_SMFLAG ((uint32_t)(1<<8))
lynxeyed_atsu	0:e8bfffbb3ab6	347	/** Deep Sleep entry flag */
lynxeyed_atsu	0:e8bfffbb3ab6	348	#define CLKPWR_PCON_DSFLAG ((uint32_t)(1<<9))
lynxeyed_atsu	0:e8bfffbb3ab6	349	/** Power-down entry flag */
lynxeyed_atsu	0:e8bfffbb3ab6	350	#define CLKPWR_PCON_PDFLAG ((uint32_t)(1<<10))
lynxeyed_atsu	0:e8bfffbb3ab6	351	/** Deep Power-down entry flag */
lynxeyed_atsu	0:e8bfffbb3ab6	352	#define CLKPWR_PCON_DPDFLAG ((uint32_t)(1<<11))
lynxeyed_atsu	0:e8bfffbb3ab6	353
lynxeyed_atsu	0:e8bfffbb3ab6	354	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	355	* Macro defines for Power Control for Peripheral Register
lynxeyed_atsu	0:e8bfffbb3ab6	356	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	357	/** Power Control for Peripherals bit mask */
lynxeyed_atsu	0:e8bfffbb3ab6	358	#define CLKPWR_PCONP_BITMASK 0xEFEFF7DE
lynxeyed_atsu	0:e8bfffbb3ab6	359
lynxeyed_atsu	0:e8bfffbb3ab6	360	/**
lynxeyed_atsu	0:e8bfffbb3ab6	361	* @}
lynxeyed_atsu	0:e8bfffbb3ab6	362	*/
lynxeyed_atsu	0:e8bfffbb3ab6	363
lynxeyed_atsu	0:e8bfffbb3ab6	364
lynxeyed_atsu	0:e8bfffbb3ab6	365	/* Public Functions ----------------------------------------------------------- */
lynxeyed_atsu	0:e8bfffbb3ab6	366	/** @defgroup CLKPWR_Public_Functions CLKPWR Public Functions
lynxeyed_atsu	0:e8bfffbb3ab6	367	* @{
lynxeyed_atsu	0:e8bfffbb3ab6	368	*/
lynxeyed_atsu	0:e8bfffbb3ab6	369
lynxeyed_atsu	0:e8bfffbb3ab6	370	void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal);
lynxeyed_atsu	0:e8bfffbb3ab6	371	uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType);
lynxeyed_atsu	0:e8bfffbb3ab6	372	uint32_t CLKPWR_GetPCLK (uint32_t ClkType);
lynxeyed_atsu	0:e8bfffbb3ab6	373	void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState);
lynxeyed_atsu	0:e8bfffbb3ab6	374	void CLKPWR_Sleep(void);
lynxeyed_atsu	0:e8bfffbb3ab6	375	void CLKPWR_DeepSleep(void);
lynxeyed_atsu	0:e8bfffbb3ab6	376	void CLKPWR_PowerDown(void);
lynxeyed_atsu	0:e8bfffbb3ab6	377	void CLKPWR_DeepPowerDown(void);
lynxeyed_atsu	0:e8bfffbb3ab6	378
lynxeyed_atsu	0:e8bfffbb3ab6	379	/**
lynxeyed_atsu	0:e8bfffbb3ab6	380	* @}
lynxeyed_atsu	0:e8bfffbb3ab6	381	*/
lynxeyed_atsu	0:e8bfffbb3ab6	382
lynxeyed_atsu	0:e8bfffbb3ab6	383
lynxeyed_atsu	0:e8bfffbb3ab6	384	#ifdef __cplusplus
lynxeyed_atsu	0:e8bfffbb3ab6	385	}
lynxeyed_atsu	0:e8bfffbb3ab6	386	#endif
lynxeyed_atsu	0:e8bfffbb3ab6	387
lynxeyed_atsu	0:e8bfffbb3ab6	388	#endif /* LPC17XX_CLKPWR_H_ */
lynxeyed_atsu	0:e8bfffbb3ab6	389
lynxeyed_atsu	0:e8bfffbb3ab6	390	/**
lynxeyed_atsu	0:e8bfffbb3ab6	391	* @}
lynxeyed_atsu	0:e8bfffbb3ab6	392	*/
lynxeyed_atsu	0:e8bfffbb3ab6	393
lynxeyed_atsu	0:e8bfffbb3ab6	394	/* --------------------------------- End Of File ------------------------------ */

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	26 Feb 2011
Imports:	12
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	1

I2S_Example/lpc17xx_clkpwr.h@0:e8bfffbb3ab6, 2011-02-26 (annotated)

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