DMA_LLI_TEST - LINKED LIST TEST on mbed

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xeye_ atsu / Mbed 2 deprecated DMA_LLI_TEST

LINKED LIST TEST on mbed

I2S_Example/lpc17xx_clkpwr.c@0:e8bfffbb3ab6, 2011-02-26 (annotated)

Committer:: lynxeyed_atsu
Date:: Sat Feb 26 03:55:12 2011 +0000
Revision:: 0:e8bfffbb3ab6

Who changed what in which revision?

User	Revision	Line number	New contents of line
lynxeyed_atsu	0:e8bfffbb3ab6	1	/*********************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	2	* @file lpc17xx_clkpwr.c
lynxeyed_atsu	0:e8bfffbb3ab6	3	* @brief Contains all functions support for Clock and Power Control
lynxeyed_atsu	0:e8bfffbb3ab6	4	* firmware library on LPC17xx
lynxeyed_atsu	0:e8bfffbb3ab6	5	* @version 3.0
lynxeyed_atsu	0:e8bfffbb3ab6	6	* @date 18. June. 2010
lynxeyed_atsu	0:e8bfffbb3ab6	7	* @author NXP MCU SW Application Team
lynxeyed_atsu	0:e8bfffbb3ab6	8	**************************************************************************
lynxeyed_atsu	0:e8bfffbb3ab6	9	* Software that is described herein is for illustrative purposes only
lynxeyed_atsu	0:e8bfffbb3ab6	10	* which provides customers with programming information regarding the
lynxeyed_atsu	0:e8bfffbb3ab6	11	* products. This software is supplied "AS IS" without any warranties.
lynxeyed_atsu	0:e8bfffbb3ab6	12	* NXP Semiconductors assumes no responsibility or liability for the
lynxeyed_atsu	0:e8bfffbb3ab6	13	* use of the software, conveys no license or title under any patent,
lynxeyed_atsu	0:e8bfffbb3ab6	14	* copyright, or mask work right to the product. NXP Semiconductors
lynxeyed_atsu	0:e8bfffbb3ab6	15	* reserves the right to make changes in the software without
lynxeyed_atsu	0:e8bfffbb3ab6	16	* notification. NXP Semiconductors also make no representation or
lynxeyed_atsu	0:e8bfffbb3ab6	17	* warranty that such application will be suitable for the specified
lynxeyed_atsu	0:e8bfffbb3ab6	18	* use without further testing or modification.
lynxeyed_atsu	0:e8bfffbb3ab6	19	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	20
lynxeyed_atsu	0:e8bfffbb3ab6	21	/* Peripheral group ----------------------------------------------------------- */
lynxeyed_atsu	0:e8bfffbb3ab6	22	/** @addtogroup CLKPWR
lynxeyed_atsu	0:e8bfffbb3ab6	23	* @{
lynxeyed_atsu	0:e8bfffbb3ab6	24	*/
lynxeyed_atsu	0:e8bfffbb3ab6	25
lynxeyed_atsu	0:e8bfffbb3ab6	26	/* Includes ------------------------------------------------------------------- */
lynxeyed_atsu	0:e8bfffbb3ab6	27	#include "lpc17xx_clkpwr.h"
lynxeyed_atsu	0:e8bfffbb3ab6	28
lynxeyed_atsu	0:e8bfffbb3ab6	29
lynxeyed_atsu	0:e8bfffbb3ab6	30	/* Public Functions ----------------------------------------------------------- */
lynxeyed_atsu	0:e8bfffbb3ab6	31	/** @addtogroup CLKPWR_Public_Functions
lynxeyed_atsu	0:e8bfffbb3ab6	32	* @{
lynxeyed_atsu	0:e8bfffbb3ab6	33	*/
lynxeyed_atsu	0:e8bfffbb3ab6	34
lynxeyed_atsu	0:e8bfffbb3ab6	35	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	36	* @brief Set value of each Peripheral Clock Selection
lynxeyed_atsu	0:e8bfffbb3ab6	37	* @param[in] ClkType Peripheral Clock Selection of each type,
lynxeyed_atsu	0:e8bfffbb3ab6	38	* should be one of the following:
lynxeyed_atsu	0:e8bfffbb3ab6	39	* - CLKPWR_PCLKSEL_WDT : WDT
lynxeyed_atsu	0:e8bfffbb3ab6	40	- CLKPWR_PCLKSEL_TIMER0 : Timer 0
lynxeyed_atsu	0:e8bfffbb3ab6	41	- CLKPWR_PCLKSEL_TIMER1 : Timer 1
lynxeyed_atsu	0:e8bfffbb3ab6	42	- CLKPWR_PCLKSEL_UART0 : UART 0
lynxeyed_atsu	0:e8bfffbb3ab6	43	- CLKPWR_PCLKSEL_UART1 : UART 1
lynxeyed_atsu	0:e8bfffbb3ab6	44	- CLKPWR_PCLKSEL_PWM1 : PWM 1
lynxeyed_atsu	0:e8bfffbb3ab6	45	- CLKPWR_PCLKSEL_I2C0 : I2C 0
lynxeyed_atsu	0:e8bfffbb3ab6	46	- CLKPWR_PCLKSEL_SPI : SPI
lynxeyed_atsu	0:e8bfffbb3ab6	47	- CLKPWR_PCLKSEL_SSP1 : SSP 1
lynxeyed_atsu	0:e8bfffbb3ab6	48	- CLKPWR_PCLKSEL_DAC : DAC
lynxeyed_atsu	0:e8bfffbb3ab6	49	- CLKPWR_PCLKSEL_ADC : ADC
lynxeyed_atsu	0:e8bfffbb3ab6	50	- CLKPWR_PCLKSEL_CAN1 : CAN 1
lynxeyed_atsu	0:e8bfffbb3ab6	51	- CLKPWR_PCLKSEL_CAN2 : CAN 2
lynxeyed_atsu	0:e8bfffbb3ab6	52	- CLKPWR_PCLKSEL_ACF : ACF
lynxeyed_atsu	0:e8bfffbb3ab6	53	- CLKPWR_PCLKSEL_QEI : QEI
lynxeyed_atsu	0:e8bfffbb3ab6	54	- CLKPWR_PCLKSEL_PCB : PCB
lynxeyed_atsu	0:e8bfffbb3ab6	55	- CLKPWR_PCLKSEL_I2C1 : I2C 1
lynxeyed_atsu	0:e8bfffbb3ab6	56	- CLKPWR_PCLKSEL_SSP0 : SSP 0
lynxeyed_atsu	0:e8bfffbb3ab6	57	- CLKPWR_PCLKSEL_TIMER2 : Timer 2
lynxeyed_atsu	0:e8bfffbb3ab6	58	- CLKPWR_PCLKSEL_TIMER3 : Timer 3
lynxeyed_atsu	0:e8bfffbb3ab6	59	- CLKPWR_PCLKSEL_UART2 : UART 2
lynxeyed_atsu	0:e8bfffbb3ab6	60	- CLKPWR_PCLKSEL_UART3 : UART 3
lynxeyed_atsu	0:e8bfffbb3ab6	61	- CLKPWR_PCLKSEL_I2C2 : I2C 2
lynxeyed_atsu	0:e8bfffbb3ab6	62	- CLKPWR_PCLKSEL_I2S : I2S
lynxeyed_atsu	0:e8bfffbb3ab6	63	- CLKPWR_PCLKSEL_RIT : RIT
lynxeyed_atsu	0:e8bfffbb3ab6	64	- CLKPWR_PCLKSEL_SYSCON : SYSCON
lynxeyed_atsu	0:e8bfffbb3ab6	65	- CLKPWR_PCLKSEL_MC : MC
lynxeyed_atsu	0:e8bfffbb3ab6	66
lynxeyed_atsu	0:e8bfffbb3ab6	67	* @param[in] DivVal Value of divider, should be:
lynxeyed_atsu	0:e8bfffbb3ab6	68	* - CLKPWR_PCLKSEL_CCLK_DIV_4 : PCLK_peripheral = CCLK/4
lynxeyed_atsu	0:e8bfffbb3ab6	69	* - CLKPWR_PCLKSEL_CCLK_DIV_1 : PCLK_peripheral = CCLK/1
lynxeyed_atsu	0:e8bfffbb3ab6	70	* - CLKPWR_PCLKSEL_CCLK_DIV_2 : PCLK_peripheral = CCLK/2
lynxeyed_atsu	0:e8bfffbb3ab6	71	*
lynxeyed_atsu	0:e8bfffbb3ab6	72	* @return none
lynxeyed_atsu	0:e8bfffbb3ab6	73	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	74	void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal)
lynxeyed_atsu	0:e8bfffbb3ab6	75	{
lynxeyed_atsu	0:e8bfffbb3ab6	76	uint32_t bitpos;
lynxeyed_atsu	0:e8bfffbb3ab6	77
lynxeyed_atsu	0:e8bfffbb3ab6	78	bitpos = (ClkType < 32) ? (ClkType) : (ClkType - 32);
lynxeyed_atsu	0:e8bfffbb3ab6	79
lynxeyed_atsu	0:e8bfffbb3ab6	80	/* PCLKSEL0 selected */
lynxeyed_atsu	0:e8bfffbb3ab6	81	if (ClkType < 32)
lynxeyed_atsu	0:e8bfffbb3ab6	82	{
lynxeyed_atsu	0:e8bfffbb3ab6	83	/* Clear two bit at bit position */
lynxeyed_atsu	0:e8bfffbb3ab6	84	LPC_SC->PCLKSEL0 &= (~(CLKPWR_PCLKSEL_BITMASK(bitpos)));
lynxeyed_atsu	0:e8bfffbb3ab6	85
lynxeyed_atsu	0:e8bfffbb3ab6	86	/* Set two selected bit */
lynxeyed_atsu	0:e8bfffbb3ab6	87	LPC_SC->PCLKSEL0 \|= (CLKPWR_PCLKSEL_SET(bitpos, DivVal));
lynxeyed_atsu	0:e8bfffbb3ab6	88	}
lynxeyed_atsu	0:e8bfffbb3ab6	89	/* PCLKSEL1 selected */
lynxeyed_atsu	0:e8bfffbb3ab6	90	else
lynxeyed_atsu	0:e8bfffbb3ab6	91	{
lynxeyed_atsu	0:e8bfffbb3ab6	92	/* Clear two bit at bit position */
lynxeyed_atsu	0:e8bfffbb3ab6	93	LPC_SC->PCLKSEL1 &= ~(CLKPWR_PCLKSEL_BITMASK(bitpos));
lynxeyed_atsu	0:e8bfffbb3ab6	94
lynxeyed_atsu	0:e8bfffbb3ab6	95	/* Set two selected bit */
lynxeyed_atsu	0:e8bfffbb3ab6	96	LPC_SC->PCLKSEL1 \|= (CLKPWR_PCLKSEL_SET(bitpos, DivVal));
lynxeyed_atsu	0:e8bfffbb3ab6	97	}
lynxeyed_atsu	0:e8bfffbb3ab6	98	}
lynxeyed_atsu	0:e8bfffbb3ab6	99
lynxeyed_atsu	0:e8bfffbb3ab6	100
lynxeyed_atsu	0:e8bfffbb3ab6	101	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	102	* @brief Get current value of each Peripheral Clock Selection
lynxeyed_atsu	0:e8bfffbb3ab6	103	* @param[in] ClkType Peripheral Clock Selection of each type,
lynxeyed_atsu	0:e8bfffbb3ab6	104	* should be one of the following:
lynxeyed_atsu	0:e8bfffbb3ab6	105	* - CLKPWR_PCLKSEL_WDT : WDT
lynxeyed_atsu	0:e8bfffbb3ab6	106	- CLKPWR_PCLKSEL_TIMER0 : Timer 0
lynxeyed_atsu	0:e8bfffbb3ab6	107	- CLKPWR_PCLKSEL_TIMER1 : Timer 1
lynxeyed_atsu	0:e8bfffbb3ab6	108	- CLKPWR_PCLKSEL_UART0 : UART 0
lynxeyed_atsu	0:e8bfffbb3ab6	109	- CLKPWR_PCLKSEL_UART1 : UART 1
lynxeyed_atsu	0:e8bfffbb3ab6	110	- CLKPWR_PCLKSEL_PWM1 : PWM 1
lynxeyed_atsu	0:e8bfffbb3ab6	111	- CLKPWR_PCLKSEL_I2C0 : I2C 0
lynxeyed_atsu	0:e8bfffbb3ab6	112	- CLKPWR_PCLKSEL_SPI : SPI
lynxeyed_atsu	0:e8bfffbb3ab6	113	- CLKPWR_PCLKSEL_SSP1 : SSP 1
lynxeyed_atsu	0:e8bfffbb3ab6	114	- CLKPWR_PCLKSEL_DAC : DAC
lynxeyed_atsu	0:e8bfffbb3ab6	115	- CLKPWR_PCLKSEL_ADC : ADC
lynxeyed_atsu	0:e8bfffbb3ab6	116	- CLKPWR_PCLKSEL_CAN1 : CAN 1
lynxeyed_atsu	0:e8bfffbb3ab6	117	- CLKPWR_PCLKSEL_CAN2 : CAN 2
lynxeyed_atsu	0:e8bfffbb3ab6	118	- CLKPWR_PCLKSEL_ACF : ACF
lynxeyed_atsu	0:e8bfffbb3ab6	119	- CLKPWR_PCLKSEL_QEI : QEI
lynxeyed_atsu	0:e8bfffbb3ab6	120	- CLKPWR_PCLKSEL_PCB : PCB
lynxeyed_atsu	0:e8bfffbb3ab6	121	- CLKPWR_PCLKSEL_I2C1 : I2C 1
lynxeyed_atsu	0:e8bfffbb3ab6	122	- CLKPWR_PCLKSEL_SSP0 : SSP 0
lynxeyed_atsu	0:e8bfffbb3ab6	123	- CLKPWR_PCLKSEL_TIMER2 : Timer 2
lynxeyed_atsu	0:e8bfffbb3ab6	124	- CLKPWR_PCLKSEL_TIMER3 : Timer 3
lynxeyed_atsu	0:e8bfffbb3ab6	125	- CLKPWR_PCLKSEL_UART2 : UART 2
lynxeyed_atsu	0:e8bfffbb3ab6	126	- CLKPWR_PCLKSEL_UART3 : UART 3
lynxeyed_atsu	0:e8bfffbb3ab6	127	- CLKPWR_PCLKSEL_I2C2 : I2C 2
lynxeyed_atsu	0:e8bfffbb3ab6	128	- CLKPWR_PCLKSEL_I2S : I2S
lynxeyed_atsu	0:e8bfffbb3ab6	129	- CLKPWR_PCLKSEL_RIT : RIT
lynxeyed_atsu	0:e8bfffbb3ab6	130	- CLKPWR_PCLKSEL_SYSCON : SYSCON
lynxeyed_atsu	0:e8bfffbb3ab6	131	- CLKPWR_PCLKSEL_MC : MC
lynxeyed_atsu	0:e8bfffbb3ab6	132
lynxeyed_atsu	0:e8bfffbb3ab6	133	* @return Value of Selected Peripheral Clock Selection
lynxeyed_atsu	0:e8bfffbb3ab6	134	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	135	uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType)
lynxeyed_atsu	0:e8bfffbb3ab6	136	{
lynxeyed_atsu	0:e8bfffbb3ab6	137	uint32_t bitpos, retval;
lynxeyed_atsu	0:e8bfffbb3ab6	138
lynxeyed_atsu	0:e8bfffbb3ab6	139	if (ClkType < 32)
lynxeyed_atsu	0:e8bfffbb3ab6	140	{
lynxeyed_atsu	0:e8bfffbb3ab6	141	bitpos = ClkType;
lynxeyed_atsu	0:e8bfffbb3ab6	142	retval = LPC_SC->PCLKSEL0;
lynxeyed_atsu	0:e8bfffbb3ab6	143	}
lynxeyed_atsu	0:e8bfffbb3ab6	144	else
lynxeyed_atsu	0:e8bfffbb3ab6	145	{
lynxeyed_atsu	0:e8bfffbb3ab6	146	bitpos = ClkType - 32;
lynxeyed_atsu	0:e8bfffbb3ab6	147	retval = LPC_SC->PCLKSEL1;
lynxeyed_atsu	0:e8bfffbb3ab6	148	}
lynxeyed_atsu	0:e8bfffbb3ab6	149
lynxeyed_atsu	0:e8bfffbb3ab6	150	retval = CLKPWR_PCLKSEL_GET(bitpos, retval);
lynxeyed_atsu	0:e8bfffbb3ab6	151	return retval;
lynxeyed_atsu	0:e8bfffbb3ab6	152	}
lynxeyed_atsu	0:e8bfffbb3ab6	153
lynxeyed_atsu	0:e8bfffbb3ab6	154
lynxeyed_atsu	0:e8bfffbb3ab6	155
lynxeyed_atsu	0:e8bfffbb3ab6	156	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	157	* @brief Get current value of each Peripheral Clock
lynxeyed_atsu	0:e8bfffbb3ab6	158	* @param[in] ClkType Peripheral Clock Selection of each type,
lynxeyed_atsu	0:e8bfffbb3ab6	159	* should be one of the following:
lynxeyed_atsu	0:e8bfffbb3ab6	160	* - CLKPWR_PCLKSEL_WDT : WDT
lynxeyed_atsu	0:e8bfffbb3ab6	161	- CLKPWR_PCLKSEL_TIMER0 : Timer 0
lynxeyed_atsu	0:e8bfffbb3ab6	162	- CLKPWR_PCLKSEL_TIMER1 : Timer 1
lynxeyed_atsu	0:e8bfffbb3ab6	163	- CLKPWR_PCLKSEL_UART0 : UART 0
lynxeyed_atsu	0:e8bfffbb3ab6	164	- CLKPWR_PCLKSEL_UART1 : UART 1
lynxeyed_atsu	0:e8bfffbb3ab6	165	- CLKPWR_PCLKSEL_PWM1 : PWM 1
lynxeyed_atsu	0:e8bfffbb3ab6	166	- CLKPWR_PCLKSEL_I2C0 : I2C 0
lynxeyed_atsu	0:e8bfffbb3ab6	167	- CLKPWR_PCLKSEL_SPI : SPI
lynxeyed_atsu	0:e8bfffbb3ab6	168	- CLKPWR_PCLKSEL_SSP1 : SSP 1
lynxeyed_atsu	0:e8bfffbb3ab6	169	- CLKPWR_PCLKSEL_DAC : DAC
lynxeyed_atsu	0:e8bfffbb3ab6	170	- CLKPWR_PCLKSEL_ADC : ADC
lynxeyed_atsu	0:e8bfffbb3ab6	171	- CLKPWR_PCLKSEL_CAN1 : CAN 1
lynxeyed_atsu	0:e8bfffbb3ab6	172	- CLKPWR_PCLKSEL_CAN2 : CAN 2
lynxeyed_atsu	0:e8bfffbb3ab6	173	- CLKPWR_PCLKSEL_ACF : ACF
lynxeyed_atsu	0:e8bfffbb3ab6	174	- CLKPWR_PCLKSEL_QEI : QEI
lynxeyed_atsu	0:e8bfffbb3ab6	175	- CLKPWR_PCLKSEL_PCB : PCB
lynxeyed_atsu	0:e8bfffbb3ab6	176	- CLKPWR_PCLKSEL_I2C1 : I2C 1
lynxeyed_atsu	0:e8bfffbb3ab6	177	- CLKPWR_PCLKSEL_SSP0 : SSP 0
lynxeyed_atsu	0:e8bfffbb3ab6	178	- CLKPWR_PCLKSEL_TIMER2 : Timer 2
lynxeyed_atsu	0:e8bfffbb3ab6	179	- CLKPWR_PCLKSEL_TIMER3 : Timer 3
lynxeyed_atsu	0:e8bfffbb3ab6	180	- CLKPWR_PCLKSEL_UART2 : UART 2
lynxeyed_atsu	0:e8bfffbb3ab6	181	- CLKPWR_PCLKSEL_UART3 : UART 3
lynxeyed_atsu	0:e8bfffbb3ab6	182	- CLKPWR_PCLKSEL_I2C2 : I2C 2
lynxeyed_atsu	0:e8bfffbb3ab6	183	- CLKPWR_PCLKSEL_I2S : I2S
lynxeyed_atsu	0:e8bfffbb3ab6	184	- CLKPWR_PCLKSEL_RIT : RIT
lynxeyed_atsu	0:e8bfffbb3ab6	185	- CLKPWR_PCLKSEL_SYSCON : SYSCON
lynxeyed_atsu	0:e8bfffbb3ab6	186	- CLKPWR_PCLKSEL_MC : MC
lynxeyed_atsu	0:e8bfffbb3ab6	187
lynxeyed_atsu	0:e8bfffbb3ab6	188	* @return Value of Selected Peripheral Clock
lynxeyed_atsu	0:e8bfffbb3ab6	189	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	190	uint32_t CLKPWR_GetPCLK (uint32_t ClkType)
lynxeyed_atsu	0:e8bfffbb3ab6	191	{
lynxeyed_atsu	0:e8bfffbb3ab6	192	uint32_t retval, div;
lynxeyed_atsu	0:e8bfffbb3ab6	193
lynxeyed_atsu	0:e8bfffbb3ab6	194	retval = SystemCoreClock;
lynxeyed_atsu	0:e8bfffbb3ab6	195	div = CLKPWR_GetPCLKSEL(ClkType);
lynxeyed_atsu	0:e8bfffbb3ab6	196
lynxeyed_atsu	0:e8bfffbb3ab6	197	switch (div)
lynxeyed_atsu	0:e8bfffbb3ab6	198	{
lynxeyed_atsu	0:e8bfffbb3ab6	199	case 0:
lynxeyed_atsu	0:e8bfffbb3ab6	200	div = 4;
lynxeyed_atsu	0:e8bfffbb3ab6	201	break;
lynxeyed_atsu	0:e8bfffbb3ab6	202
lynxeyed_atsu	0:e8bfffbb3ab6	203	case 1:
lynxeyed_atsu	0:e8bfffbb3ab6	204	div = 1;
lynxeyed_atsu	0:e8bfffbb3ab6	205	break;
lynxeyed_atsu	0:e8bfffbb3ab6	206
lynxeyed_atsu	0:e8bfffbb3ab6	207	case 2:
lynxeyed_atsu	0:e8bfffbb3ab6	208	div = 2;
lynxeyed_atsu	0:e8bfffbb3ab6	209	break;
lynxeyed_atsu	0:e8bfffbb3ab6	210
lynxeyed_atsu	0:e8bfffbb3ab6	211	case 3:
lynxeyed_atsu	0:e8bfffbb3ab6	212	div = 8;
lynxeyed_atsu	0:e8bfffbb3ab6	213	break;
lynxeyed_atsu	0:e8bfffbb3ab6	214	}
lynxeyed_atsu	0:e8bfffbb3ab6	215	retval /= div;
lynxeyed_atsu	0:e8bfffbb3ab6	216
lynxeyed_atsu	0:e8bfffbb3ab6	217	return retval;
lynxeyed_atsu	0:e8bfffbb3ab6	218	}
lynxeyed_atsu	0:e8bfffbb3ab6	219
lynxeyed_atsu	0:e8bfffbb3ab6	220
lynxeyed_atsu	0:e8bfffbb3ab6	221
lynxeyed_atsu	0:e8bfffbb3ab6	222	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	223	* @brief Configure power supply for each peripheral according to NewState
lynxeyed_atsu	0:e8bfffbb3ab6	224	* @param[in] PPType Type of peripheral used to enable power,
lynxeyed_atsu	0:e8bfffbb3ab6	225	* should be one of the following:
lynxeyed_atsu	0:e8bfffbb3ab6	226	* - CLKPWR_PCONP_PCTIM0 : Timer 0
lynxeyed_atsu	0:e8bfffbb3ab6	227	- CLKPWR_PCONP_PCTIM1 : Timer 1
lynxeyed_atsu	0:e8bfffbb3ab6	228	- CLKPWR_PCONP_PCUART0 : UART 0
lynxeyed_atsu	0:e8bfffbb3ab6	229	- CLKPWR_PCONP_PCUART1 : UART 1
lynxeyed_atsu	0:e8bfffbb3ab6	230	- CLKPWR_PCONP_PCPWM1 : PWM 1
lynxeyed_atsu	0:e8bfffbb3ab6	231	- CLKPWR_PCONP_PCI2C0 : I2C 0
lynxeyed_atsu	0:e8bfffbb3ab6	232	- CLKPWR_PCONP_PCSPI : SPI
lynxeyed_atsu	0:e8bfffbb3ab6	233	- CLKPWR_PCONP_PCRTC : RTC
lynxeyed_atsu	0:e8bfffbb3ab6	234	- CLKPWR_PCONP_PCSSP1 : SSP 1
lynxeyed_atsu	0:e8bfffbb3ab6	235	- CLKPWR_PCONP_PCAD : ADC
lynxeyed_atsu	0:e8bfffbb3ab6	236	- CLKPWR_PCONP_PCAN1 : CAN 1
lynxeyed_atsu	0:e8bfffbb3ab6	237	- CLKPWR_PCONP_PCAN2 : CAN 2
lynxeyed_atsu	0:e8bfffbb3ab6	238	- CLKPWR_PCONP_PCGPIO : GPIO
lynxeyed_atsu	0:e8bfffbb3ab6	239	- CLKPWR_PCONP_PCRIT : RIT
lynxeyed_atsu	0:e8bfffbb3ab6	240	- CLKPWR_PCONP_PCMC : MC
lynxeyed_atsu	0:e8bfffbb3ab6	241	- CLKPWR_PCONP_PCQEI : QEI
lynxeyed_atsu	0:e8bfffbb3ab6	242	- CLKPWR_PCONP_PCI2C1 : I2C 1
lynxeyed_atsu	0:e8bfffbb3ab6	243	- CLKPWR_PCONP_PCSSP0 : SSP 0
lynxeyed_atsu	0:e8bfffbb3ab6	244	- CLKPWR_PCONP_PCTIM2 : Timer 2
lynxeyed_atsu	0:e8bfffbb3ab6	245	- CLKPWR_PCONP_PCTIM3 : Timer 3
lynxeyed_atsu	0:e8bfffbb3ab6	246	- CLKPWR_PCONP_PCUART2 : UART 2
lynxeyed_atsu	0:e8bfffbb3ab6	247	- CLKPWR_PCONP_PCUART3 : UART 3
lynxeyed_atsu	0:e8bfffbb3ab6	248	- CLKPWR_PCONP_PCI2C2 : I2C 2
lynxeyed_atsu	0:e8bfffbb3ab6	249	- CLKPWR_PCONP_PCI2S : I2S
lynxeyed_atsu	0:e8bfffbb3ab6	250	- CLKPWR_PCONP_PCGPDMA : GPDMA
lynxeyed_atsu	0:e8bfffbb3ab6	251	- CLKPWR_PCONP_PCENET : Ethernet
lynxeyed_atsu	0:e8bfffbb3ab6	252	- CLKPWR_PCONP_PCUSB : USB
lynxeyed_atsu	0:e8bfffbb3ab6	253	*
lynxeyed_atsu	0:e8bfffbb3ab6	254	* @param[in] NewState New state of Peripheral Power, should be:
lynxeyed_atsu	0:e8bfffbb3ab6	255	* - ENABLE : Enable power for this peripheral
lynxeyed_atsu	0:e8bfffbb3ab6	256	* - DISABLE : Disable power for this peripheral
lynxeyed_atsu	0:e8bfffbb3ab6	257	*
lynxeyed_atsu	0:e8bfffbb3ab6	258	* @return none
lynxeyed_atsu	0:e8bfffbb3ab6	259	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	260	void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState)
lynxeyed_atsu	0:e8bfffbb3ab6	261	{
lynxeyed_atsu	0:e8bfffbb3ab6	262	if (NewState == ENABLE)
lynxeyed_atsu	0:e8bfffbb3ab6	263	{
lynxeyed_atsu	0:e8bfffbb3ab6	264	LPC_SC->PCONP \|= PPType & CLKPWR_PCONP_BITMASK;
lynxeyed_atsu	0:e8bfffbb3ab6	265	}
lynxeyed_atsu	0:e8bfffbb3ab6	266	else if (NewState == DISABLE)
lynxeyed_atsu	0:e8bfffbb3ab6	267	{
lynxeyed_atsu	0:e8bfffbb3ab6	268	LPC_SC->PCONP &= (~PPType) & CLKPWR_PCONP_BITMASK;
lynxeyed_atsu	0:e8bfffbb3ab6	269	}
lynxeyed_atsu	0:e8bfffbb3ab6	270	}
lynxeyed_atsu	0:e8bfffbb3ab6	271
lynxeyed_atsu	0:e8bfffbb3ab6	272
lynxeyed_atsu	0:e8bfffbb3ab6	273	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	274	* @brief Enter Sleep mode with co-operated instruction by the Cortex-M3.
lynxeyed_atsu	0:e8bfffbb3ab6	275	* @param[in] None
lynxeyed_atsu	0:e8bfffbb3ab6	276	* @return None
lynxeyed_atsu	0:e8bfffbb3ab6	277	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	278	void CLKPWR_Sleep(void)
lynxeyed_atsu	0:e8bfffbb3ab6	279	{
lynxeyed_atsu	0:e8bfffbb3ab6	280	LPC_SC->PCON = 0x00;
lynxeyed_atsu	0:e8bfffbb3ab6	281	/* Sleep Mode*/
lynxeyed_atsu	0:e8bfffbb3ab6	282	__WFI();
lynxeyed_atsu	0:e8bfffbb3ab6	283	}
lynxeyed_atsu	0:e8bfffbb3ab6	284
lynxeyed_atsu	0:e8bfffbb3ab6	285
lynxeyed_atsu	0:e8bfffbb3ab6	286	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	287	* @brief Enter Deep Sleep mode with co-operated instruction by the Cortex-M3.
lynxeyed_atsu	0:e8bfffbb3ab6	288	* @param[in] None
lynxeyed_atsu	0:e8bfffbb3ab6	289	* @return None
lynxeyed_atsu	0:e8bfffbb3ab6	290	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	291	void CLKPWR_DeepSleep(void)
lynxeyed_atsu	0:e8bfffbb3ab6	292	{
lynxeyed_atsu	0:e8bfffbb3ab6	293	/* Deep-Sleep Mode, set SLEEPDEEP bit */
lynxeyed_atsu	0:e8bfffbb3ab6	294	SCB->SCR = 0x4;
lynxeyed_atsu	0:e8bfffbb3ab6	295	LPC_SC->PCON = 0x8;
lynxeyed_atsu	0:e8bfffbb3ab6	296	/* Deep Sleep Mode*/
lynxeyed_atsu	0:e8bfffbb3ab6	297	__WFI();
lynxeyed_atsu	0:e8bfffbb3ab6	298	}
lynxeyed_atsu	0:e8bfffbb3ab6	299
lynxeyed_atsu	0:e8bfffbb3ab6	300
lynxeyed_atsu	0:e8bfffbb3ab6	301	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	302	* @brief Enter Power Down mode with co-operated instruction by the Cortex-M3.
lynxeyed_atsu	0:e8bfffbb3ab6	303	* @param[in] None
lynxeyed_atsu	0:e8bfffbb3ab6	304	* @return None
lynxeyed_atsu	0:e8bfffbb3ab6	305	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	306	void CLKPWR_PowerDown(void)
lynxeyed_atsu	0:e8bfffbb3ab6	307	{
lynxeyed_atsu	0:e8bfffbb3ab6	308	/* Deep-Sleep Mode, set SLEEPDEEP bit */
lynxeyed_atsu	0:e8bfffbb3ab6	309	SCB->SCR = 0x4;
lynxeyed_atsu	0:e8bfffbb3ab6	310	LPC_SC->PCON = 0x09;
lynxeyed_atsu	0:e8bfffbb3ab6	311	/* Power Down Mode*/
lynxeyed_atsu	0:e8bfffbb3ab6	312	__WFI();
lynxeyed_atsu	0:e8bfffbb3ab6	313	}
lynxeyed_atsu	0:e8bfffbb3ab6	314
lynxeyed_atsu	0:e8bfffbb3ab6	315
lynxeyed_atsu	0:e8bfffbb3ab6	316	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	317	* @brief Enter Deep Power Down mode with co-operated instruction by the Cortex-M3.
lynxeyed_atsu	0:e8bfffbb3ab6	318	* @param[in] None
lynxeyed_atsu	0:e8bfffbb3ab6	319	* @return None
lynxeyed_atsu	0:e8bfffbb3ab6	320	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	321	void CLKPWR_DeepPowerDown(void)
lynxeyed_atsu	0:e8bfffbb3ab6	322	{
lynxeyed_atsu	0:e8bfffbb3ab6	323	/* Deep-Sleep Mode, set SLEEPDEEP bit */
lynxeyed_atsu	0:e8bfffbb3ab6	324	SCB->SCR = 0x4;
lynxeyed_atsu	0:e8bfffbb3ab6	325	LPC_SC->PCON = 0x03;
lynxeyed_atsu	0:e8bfffbb3ab6	326	/* Deep Power Down Mode*/
lynxeyed_atsu	0:e8bfffbb3ab6	327	__WFI();
lynxeyed_atsu	0:e8bfffbb3ab6	328	}
lynxeyed_atsu	0:e8bfffbb3ab6	329
lynxeyed_atsu	0:e8bfffbb3ab6	330	/**
lynxeyed_atsu	0:e8bfffbb3ab6	331	* @}
lynxeyed_atsu	0:e8bfffbb3ab6	332	*/
lynxeyed_atsu	0:e8bfffbb3ab6	333
lynxeyed_atsu	0:e8bfffbb3ab6	334	/**
lynxeyed_atsu	0:e8bfffbb3ab6	335	* @}
lynxeyed_atsu	0:e8bfffbb3ab6	336	*/
lynxeyed_atsu	0:e8bfffbb3ab6	337
lynxeyed_atsu	0:e8bfffbb3ab6	338	/* --------------------------------- End Of File ------------------------------ */

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	26 Feb 2011
Imports:	12
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	1

I2S_Example/lpc17xx_clkpwr.c@0:e8bfffbb3ab6, 2011-02-26 (annotated)

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