DMA_LLI_TEST - LINKED LIST TEST on mbed

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xeye_ atsu / Mbed 2 deprecated DMA_LLI_TEST

LINKED LIST TEST on mbed

I2S_Example/LPC17xx.h@0:e8bfffbb3ab6, 2011-02-26 (annotated)

Committer:: lynxeyed_atsu
Date:: Sat Feb 26 03:55:12 2011 +0000
Revision:: 0:e8bfffbb3ab6

Who changed what in which revision?

User	Revision	Line number	New contents of line
lynxeyed_atsu	0:e8bfffbb3ab6	1	/************************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	2	* @file LPC17xx.h
lynxeyed_atsu	0:e8bfffbb3ab6	3	* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
lynxeyed_atsu	0:e8bfffbb3ab6	4	* NXP LPC17xx Device Series
lynxeyed_atsu	0:e8bfffbb3ab6	5	* @version: V1.08
lynxeyed_atsu	0:e8bfffbb3ab6	6	* @date: 21. December 2009
lynxeyed_atsu	0:e8bfffbb3ab6	7	*
lynxeyed_atsu	0:e8bfffbb3ab6	8	* @note
lynxeyed_atsu	0:e8bfffbb3ab6	9	* Copyright (C) 2009 ARM Limited. All rights reserved.
lynxeyed_atsu	0:e8bfffbb3ab6	10	*
lynxeyed_atsu	0:e8bfffbb3ab6	11	* @par
lynxeyed_atsu	0:e8bfffbb3ab6	12	* ARM Limited (ARM) is supplying this software for use with Cortex-M
lynxeyed_atsu	0:e8bfffbb3ab6	13	* processor based microcontrollers. This file can be freely distributed
lynxeyed_atsu	0:e8bfffbb3ab6	14	* within development tools that are supporting such ARM based processors.
lynxeyed_atsu	0:e8bfffbb3ab6	15	*
lynxeyed_atsu	0:e8bfffbb3ab6	16	* @par
lynxeyed_atsu	0:e8bfffbb3ab6	17	* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
lynxeyed_atsu	0:e8bfffbb3ab6	18	* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
lynxeyed_atsu	0:e8bfffbb3ab6	19	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
lynxeyed_atsu	0:e8bfffbb3ab6	20	* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
lynxeyed_atsu	0:e8bfffbb3ab6	21	* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
lynxeyed_atsu	0:e8bfffbb3ab6	22	*
lynxeyed_atsu	0:e8bfffbb3ab6	23	******************************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	24
lynxeyed_atsu	0:e8bfffbb3ab6	25
lynxeyed_atsu	0:e8bfffbb3ab6	26	#ifndef __LPC17xx_H__
lynxeyed_atsu	0:e8bfffbb3ab6	27	#define __LPC17xx_H__
lynxeyed_atsu	0:e8bfffbb3ab6	28
lynxeyed_atsu	0:e8bfffbb3ab6	29	/*
lynxeyed_atsu	0:e8bfffbb3ab6	30	* ==========================================================================
lynxeyed_atsu	0:e8bfffbb3ab6	31	* ---------- Interrupt Number Definition -----------------------------------
lynxeyed_atsu	0:e8bfffbb3ab6	32	* ==========================================================================
lynxeyed_atsu	0:e8bfffbb3ab6	33	*/
lynxeyed_atsu	0:e8bfffbb3ab6	34
lynxeyed_atsu	0:e8bfffbb3ab6	35	/** @addtogroup LPC17xx_System
lynxeyed_atsu	0:e8bfffbb3ab6	36	* @{
lynxeyed_atsu	0:e8bfffbb3ab6	37	*/
lynxeyed_atsu	0:e8bfffbb3ab6	38
lynxeyed_atsu	0:e8bfffbb3ab6	39	/** @brief IRQ interrupt source definition */
lynxeyed_atsu	0:e8bfffbb3ab6	40	typedef enum IRQn
lynxeyed_atsu	0:e8bfffbb3ab6	41	{
lynxeyed_atsu	0:e8bfffbb3ab6	42	/**** Cortex-M3 Processor Exceptions Numbers *************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	43	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	44	MemoryManagement_IRQn = -12, /!< 4 Cortex-M3 Memory Management Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	45	BusFault_IRQn = -11, /!< 5 Cortex-M3 Bus Fault Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	46	UsageFault_IRQn = -10, /!< 6 Cortex-M3 Usage Fault Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	47	SVCall_IRQn = -5, /!< 11 Cortex-M3 SV Call Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	48	DebugMonitor_IRQn = -4, /!< 12 Cortex-M3 Debug Monitor Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	49	PendSV_IRQn = -2, /!< 14 Cortex-M3 Pend SV Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	50	SysTick_IRQn = -1, /!< 15 Cortex-M3 System Tick Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	51
lynxeyed_atsu	0:e8bfffbb3ab6	52	/**** LPC17xx Specific Interrupt Numbers *****************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	53	WDT_IRQn = 0, /!< Watchdog Timer Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	54	TIMER0_IRQn = 1, /!< Timer0 Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	55	TIMER1_IRQn = 2, /!< Timer1 Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	56	TIMER2_IRQn = 3, /!< Timer2 Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	57	TIMER3_IRQn = 4, /!< Timer3 Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	58	UART0_IRQn = 5, /!< UART0 Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	59	UART1_IRQn = 6, /!< UART1 Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	60	UART2_IRQn = 7, /!< UART2 Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	61	UART3_IRQn = 8, /!< UART3 Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	62	PWM1_IRQn = 9, /!< PWM1 Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	63	I2C0_IRQn = 10, /!< I2C0 Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	64	I2C1_IRQn = 11, /!< I2C1 Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	65	I2C2_IRQn = 12, /!< I2C2 Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	66	SPI_IRQn = 13, /!< SPI Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	67	SSP0_IRQn = 14, /!< SSP0 Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	68	SSP1_IRQn = 15, /!< SSP1 Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	69	PLL0_IRQn = 16, /!< PLL0 Lock (Main PLL) Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	70	RTC_IRQn = 17, /!< Real Time Clock Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	71	EINT0_IRQn = 18, /!< External Interrupt 0 Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	72	EINT1_IRQn = 19, /!< External Interrupt 1 Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	73	EINT2_IRQn = 20, /!< External Interrupt 2 Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	74	EINT3_IRQn = 21, /!< External Interrupt 3 Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	75	ADC_IRQn = 22, /!< A/D Converter Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	76	BOD_IRQn = 23, /!< Brown-Out Detect Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	77	USB_IRQn = 24, /!< USB Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	78	CAN_IRQn = 25, /!< CAN Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	79	DMA_IRQn = 26, /!< General Purpose DMA Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	80	I2S_IRQn = 27, /!< I2S Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	81	ENET_IRQn = 28, /!< Ethernet Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	82	RIT_IRQn = 29, /!< Repetitive Interrupt Timer Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	83	MCPWM_IRQn = 30, /!< Motor Control PWM Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	84	QEI_IRQn = 31, /!< Quadrature Encoder Interface Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	85	PLL1_IRQn = 32, /!< PLL1 Lock (USB PLL) Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	86	USBActivity_IRQn = 33, /!< USB Activity Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	87	CANActivity_IRQn = 34, /!< CAN Activity Interrupt /
lynxeyed_atsu	0:e8bfffbb3ab6	88	} IRQn_Type;
lynxeyed_atsu	0:e8bfffbb3ab6	89
lynxeyed_atsu	0:e8bfffbb3ab6	90
lynxeyed_atsu	0:e8bfffbb3ab6	91	/*
lynxeyed_atsu	0:e8bfffbb3ab6	92	* ==========================================================================
lynxeyed_atsu	0:e8bfffbb3ab6	93	* ----------- Processor and Core Peripheral Section ------------------------
lynxeyed_atsu	0:e8bfffbb3ab6	94	* ==========================================================================
lynxeyed_atsu	0:e8bfffbb3ab6	95	*/
lynxeyed_atsu	0:e8bfffbb3ab6	96
lynxeyed_atsu	0:e8bfffbb3ab6	97	/* Configuration of the Cortex-M3 Processor and Core Peripherals */
lynxeyed_atsu	0:e8bfffbb3ab6	98	#define __MPU_PRESENT 1 /!< MPU present or not /
lynxeyed_atsu	0:e8bfffbb3ab6	99	#define __NVIC_PRIO_BITS 5 /!< Number of Bits used for Priority Levels /
lynxeyed_atsu	0:e8bfffbb3ab6	100	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
lynxeyed_atsu	0:e8bfffbb3ab6	101
lynxeyed_atsu	0:e8bfffbb3ab6	102
lynxeyed_atsu	0:e8bfffbb3ab6	103	#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
lynxeyed_atsu	0:e8bfffbb3ab6	104	#include "system_LPC17xx.h" /* System Header */
lynxeyed_atsu	0:e8bfffbb3ab6	105
lynxeyed_atsu	0:e8bfffbb3ab6	106
lynxeyed_atsu	0:e8bfffbb3ab6	107	/******************************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	108	/* Device Specific Peripheral registers structures */
lynxeyed_atsu	0:e8bfffbb3ab6	109	/******************************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	110
lynxeyed_atsu	0:e8bfffbb3ab6	111	#if defined ( __CC_ARM )
lynxeyed_atsu	0:e8bfffbb3ab6	112	#pragma anon_unions
lynxeyed_atsu	0:e8bfffbb3ab6	113	#endif
lynxeyed_atsu	0:e8bfffbb3ab6	114
lynxeyed_atsu	0:e8bfffbb3ab6	115	/------------- System Control (SC) ------------------------------------------/
lynxeyed_atsu	0:e8bfffbb3ab6	116	/** @brief System Control (SC) register structure definition */
lynxeyed_atsu	0:e8bfffbb3ab6	117	typedef struct
lynxeyed_atsu	0:e8bfffbb3ab6	118	{
lynxeyed_atsu	0:e8bfffbb3ab6	119	__IO uint32_t FLASHCFG; /* Flash Accelerator Module */
lynxeyed_atsu	0:e8bfffbb3ab6	120	uint32_t RESERVED0[31];
lynxeyed_atsu	0:e8bfffbb3ab6	121	__IO uint32_t PLL0CON; /* Clocking and Power Control */
lynxeyed_atsu	0:e8bfffbb3ab6	122	__IO uint32_t PLL0CFG;
lynxeyed_atsu	0:e8bfffbb3ab6	123	__I uint32_t PLL0STAT;
lynxeyed_atsu	0:e8bfffbb3ab6	124	__O uint32_t PLL0FEED;
lynxeyed_atsu	0:e8bfffbb3ab6	125	uint32_t RESERVED1[4];
lynxeyed_atsu	0:e8bfffbb3ab6	126	__IO uint32_t PLL1CON;
lynxeyed_atsu	0:e8bfffbb3ab6	127	__IO uint32_t PLL1CFG;
lynxeyed_atsu	0:e8bfffbb3ab6	128	__I uint32_t PLL1STAT;
lynxeyed_atsu	0:e8bfffbb3ab6	129	__O uint32_t PLL1FEED;
lynxeyed_atsu	0:e8bfffbb3ab6	130	uint32_t RESERVED2[4];
lynxeyed_atsu	0:e8bfffbb3ab6	131	__IO uint32_t PCON;
lynxeyed_atsu	0:e8bfffbb3ab6	132	__IO uint32_t PCONP;
lynxeyed_atsu	0:e8bfffbb3ab6	133	uint32_t RESERVED3[15];
lynxeyed_atsu	0:e8bfffbb3ab6	134	__IO uint32_t CCLKCFG;
lynxeyed_atsu	0:e8bfffbb3ab6	135	__IO uint32_t USBCLKCFG;
lynxeyed_atsu	0:e8bfffbb3ab6	136	__IO uint32_t CLKSRCSEL;
lynxeyed_atsu	0:e8bfffbb3ab6	137	__IO uint32_t CANSLEEPCLR;
lynxeyed_atsu	0:e8bfffbb3ab6	138	__IO uint32_t CANWAKEFLAGS;
lynxeyed_atsu	0:e8bfffbb3ab6	139	uint32_t RESERVED4[10];
lynxeyed_atsu	0:e8bfffbb3ab6	140	__IO uint32_t EXTINT; /* External Interrupts */
lynxeyed_atsu	0:e8bfffbb3ab6	141	uint32_t RESERVED5;
lynxeyed_atsu	0:e8bfffbb3ab6	142	__IO uint32_t EXTMODE;
lynxeyed_atsu	0:e8bfffbb3ab6	143	__IO uint32_t EXTPOLAR;
lynxeyed_atsu	0:e8bfffbb3ab6	144	uint32_t RESERVED6[12];
lynxeyed_atsu	0:e8bfffbb3ab6	145	__IO uint32_t RSID; /* Reset */
lynxeyed_atsu	0:e8bfffbb3ab6	146	uint32_t RESERVED7[7];
lynxeyed_atsu	0:e8bfffbb3ab6	147	__IO uint32_t SCS; /* Syscon Miscellaneous Registers */
lynxeyed_atsu	0:e8bfffbb3ab6	148	__IO uint32_t IRCTRIM; /* Clock Dividers */
lynxeyed_atsu	0:e8bfffbb3ab6	149	__IO uint32_t PCLKSEL0;
lynxeyed_atsu	0:e8bfffbb3ab6	150	__IO uint32_t PCLKSEL1;
lynxeyed_atsu	0:e8bfffbb3ab6	151	uint32_t RESERVED8[4];
lynxeyed_atsu	0:e8bfffbb3ab6	152	__IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
lynxeyed_atsu	0:e8bfffbb3ab6	153	__IO uint32_t DMAREQSEL;
lynxeyed_atsu	0:e8bfffbb3ab6	154	__IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
lynxeyed_atsu	0:e8bfffbb3ab6	155	} LPC_SC_TypeDef;
lynxeyed_atsu	0:e8bfffbb3ab6	156
lynxeyed_atsu	0:e8bfffbb3ab6	157	/------------- Pin Connect Block (PINCON) -----------------------------------/
lynxeyed_atsu	0:e8bfffbb3ab6	158	/** @brief Pin Connect Block (PINCON) register structure definition */
lynxeyed_atsu	0:e8bfffbb3ab6	159	typedef struct
lynxeyed_atsu	0:e8bfffbb3ab6	160	{
lynxeyed_atsu	0:e8bfffbb3ab6	161	__IO uint32_t PINSEL0;
lynxeyed_atsu	0:e8bfffbb3ab6	162	__IO uint32_t PINSEL1;
lynxeyed_atsu	0:e8bfffbb3ab6	163	__IO uint32_t PINSEL2;
lynxeyed_atsu	0:e8bfffbb3ab6	164	__IO uint32_t PINSEL3;
lynxeyed_atsu	0:e8bfffbb3ab6	165	__IO uint32_t PINSEL4;
lynxeyed_atsu	0:e8bfffbb3ab6	166	__IO uint32_t PINSEL5;
lynxeyed_atsu	0:e8bfffbb3ab6	167	__IO uint32_t PINSEL6;
lynxeyed_atsu	0:e8bfffbb3ab6	168	__IO uint32_t PINSEL7;
lynxeyed_atsu	0:e8bfffbb3ab6	169	__IO uint32_t PINSEL8;
lynxeyed_atsu	0:e8bfffbb3ab6	170	__IO uint32_t PINSEL9;
lynxeyed_atsu	0:e8bfffbb3ab6	171	__IO uint32_t PINSEL10;
lynxeyed_atsu	0:e8bfffbb3ab6	172	uint32_t RESERVED0[5];
lynxeyed_atsu	0:e8bfffbb3ab6	173	__IO uint32_t PINMODE0;
lynxeyed_atsu	0:e8bfffbb3ab6	174	__IO uint32_t PINMODE1;
lynxeyed_atsu	0:e8bfffbb3ab6	175	__IO uint32_t PINMODE2;
lynxeyed_atsu	0:e8bfffbb3ab6	176	__IO uint32_t PINMODE3;
lynxeyed_atsu	0:e8bfffbb3ab6	177	__IO uint32_t PINMODE4;
lynxeyed_atsu	0:e8bfffbb3ab6	178	__IO uint32_t PINMODE5;
lynxeyed_atsu	0:e8bfffbb3ab6	179	__IO uint32_t PINMODE6;
lynxeyed_atsu	0:e8bfffbb3ab6	180	__IO uint32_t PINMODE7;
lynxeyed_atsu	0:e8bfffbb3ab6	181	__IO uint32_t PINMODE8;
lynxeyed_atsu	0:e8bfffbb3ab6	182	__IO uint32_t PINMODE9;
lynxeyed_atsu	0:e8bfffbb3ab6	183	__IO uint32_t PINMODE_OD0;
lynxeyed_atsu	0:e8bfffbb3ab6	184	__IO uint32_t PINMODE_OD1;
lynxeyed_atsu	0:e8bfffbb3ab6	185	__IO uint32_t PINMODE_OD2;
lynxeyed_atsu	0:e8bfffbb3ab6	186	__IO uint32_t PINMODE_OD3;
lynxeyed_atsu	0:e8bfffbb3ab6	187	__IO uint32_t PINMODE_OD4;
lynxeyed_atsu	0:e8bfffbb3ab6	188	__IO uint32_t I2CPADCFG;
lynxeyed_atsu	0:e8bfffbb3ab6	189	} LPC_PINCON_TypeDef;
lynxeyed_atsu	0:e8bfffbb3ab6	190
lynxeyed_atsu	0:e8bfffbb3ab6	191	/------------- General Purpose Input/Output (GPIO) --------------------------/
lynxeyed_atsu	0:e8bfffbb3ab6	192	/** @brief General Purpose Input/Output (GPIO) register structure definition */
lynxeyed_atsu	0:e8bfffbb3ab6	193	typedef struct
lynxeyed_atsu	0:e8bfffbb3ab6	194	{
lynxeyed_atsu	0:e8bfffbb3ab6	195	union {
lynxeyed_atsu	0:e8bfffbb3ab6	196	__IO uint32_t FIODIR;
lynxeyed_atsu	0:e8bfffbb3ab6	197	struct {
lynxeyed_atsu	0:e8bfffbb3ab6	198	__IO uint16_t FIODIRL;
lynxeyed_atsu	0:e8bfffbb3ab6	199	__IO uint16_t FIODIRH;
lynxeyed_atsu	0:e8bfffbb3ab6	200	};
lynxeyed_atsu	0:e8bfffbb3ab6	201	struct {
lynxeyed_atsu	0:e8bfffbb3ab6	202	__IO uint8_t FIODIR0;
lynxeyed_atsu	0:e8bfffbb3ab6	203	__IO uint8_t FIODIR1;
lynxeyed_atsu	0:e8bfffbb3ab6	204	__IO uint8_t FIODIR2;
lynxeyed_atsu	0:e8bfffbb3ab6	205	__IO uint8_t FIODIR3;
lynxeyed_atsu	0:e8bfffbb3ab6	206	};
lynxeyed_atsu	0:e8bfffbb3ab6	207	};
lynxeyed_atsu	0:e8bfffbb3ab6	208	uint32_t RESERVED0[3];
lynxeyed_atsu	0:e8bfffbb3ab6	209	union {
lynxeyed_atsu	0:e8bfffbb3ab6	210	__IO uint32_t FIOMASK;
lynxeyed_atsu	0:e8bfffbb3ab6	211	struct {
lynxeyed_atsu	0:e8bfffbb3ab6	212	__IO uint16_t FIOMASKL;
lynxeyed_atsu	0:e8bfffbb3ab6	213	__IO uint16_t FIOMASKH;
lynxeyed_atsu	0:e8bfffbb3ab6	214	};
lynxeyed_atsu	0:e8bfffbb3ab6	215	struct {
lynxeyed_atsu	0:e8bfffbb3ab6	216	__IO uint8_t FIOMASK0;
lynxeyed_atsu	0:e8bfffbb3ab6	217	__IO uint8_t FIOMASK1;
lynxeyed_atsu	0:e8bfffbb3ab6	218	__IO uint8_t FIOMASK2;
lynxeyed_atsu	0:e8bfffbb3ab6	219	__IO uint8_t FIOMASK3;
lynxeyed_atsu	0:e8bfffbb3ab6	220	};
lynxeyed_atsu	0:e8bfffbb3ab6	221	};
lynxeyed_atsu	0:e8bfffbb3ab6	222	union {
lynxeyed_atsu	0:e8bfffbb3ab6	223	__IO uint32_t FIOPIN;
lynxeyed_atsu	0:e8bfffbb3ab6	224	struct {
lynxeyed_atsu	0:e8bfffbb3ab6	225	__IO uint16_t FIOPINL;
lynxeyed_atsu	0:e8bfffbb3ab6	226	__IO uint16_t FIOPINH;
lynxeyed_atsu	0:e8bfffbb3ab6	227	};
lynxeyed_atsu	0:e8bfffbb3ab6	228	struct {
lynxeyed_atsu	0:e8bfffbb3ab6	229	__IO uint8_t FIOPIN0;
lynxeyed_atsu	0:e8bfffbb3ab6	230	__IO uint8_t FIOPIN1;
lynxeyed_atsu	0:e8bfffbb3ab6	231	__IO uint8_t FIOPIN2;
lynxeyed_atsu	0:e8bfffbb3ab6	232	__IO uint8_t FIOPIN3;
lynxeyed_atsu	0:e8bfffbb3ab6	233	};
lynxeyed_atsu	0:e8bfffbb3ab6	234	};
lynxeyed_atsu	0:e8bfffbb3ab6	235	union {
lynxeyed_atsu	0:e8bfffbb3ab6	236	__IO uint32_t FIOSET;
lynxeyed_atsu	0:e8bfffbb3ab6	237	struct {
lynxeyed_atsu	0:e8bfffbb3ab6	238	__IO uint16_t FIOSETL;
lynxeyed_atsu	0:e8bfffbb3ab6	239	__IO uint16_t FIOSETH;
lynxeyed_atsu	0:e8bfffbb3ab6	240	};
lynxeyed_atsu	0:e8bfffbb3ab6	241	struct {
lynxeyed_atsu	0:e8bfffbb3ab6	242	__IO uint8_t FIOSET0;
lynxeyed_atsu	0:e8bfffbb3ab6	243	__IO uint8_t FIOSET1;
lynxeyed_atsu	0:e8bfffbb3ab6	244	__IO uint8_t FIOSET2;
lynxeyed_atsu	0:e8bfffbb3ab6	245	__IO uint8_t FIOSET3;
lynxeyed_atsu	0:e8bfffbb3ab6	246	};
lynxeyed_atsu	0:e8bfffbb3ab6	247	};
lynxeyed_atsu	0:e8bfffbb3ab6	248	union {
lynxeyed_atsu	0:e8bfffbb3ab6	249	__O uint32_t FIOCLR;
lynxeyed_atsu	0:e8bfffbb3ab6	250	struct {
lynxeyed_atsu	0:e8bfffbb3ab6	251	__O uint16_t FIOCLRL;
lynxeyed_atsu	0:e8bfffbb3ab6	252	__O uint16_t FIOCLRH;
lynxeyed_atsu	0:e8bfffbb3ab6	253	};
lynxeyed_atsu	0:e8bfffbb3ab6	254	struct {
lynxeyed_atsu	0:e8bfffbb3ab6	255	__O uint8_t FIOCLR0;
lynxeyed_atsu	0:e8bfffbb3ab6	256	__O uint8_t FIOCLR1;
lynxeyed_atsu	0:e8bfffbb3ab6	257	__O uint8_t FIOCLR2;
lynxeyed_atsu	0:e8bfffbb3ab6	258	__O uint8_t FIOCLR3;
lynxeyed_atsu	0:e8bfffbb3ab6	259	};
lynxeyed_atsu	0:e8bfffbb3ab6	260	};
lynxeyed_atsu	0:e8bfffbb3ab6	261	} LPC_GPIO_TypeDef;
lynxeyed_atsu	0:e8bfffbb3ab6	262
lynxeyed_atsu	0:e8bfffbb3ab6	263	/** @brief General Purpose Input/Output interrupt (GPIOINT) register structure definition */
lynxeyed_atsu	0:e8bfffbb3ab6	264	typedef struct
lynxeyed_atsu	0:e8bfffbb3ab6	265	{
lynxeyed_atsu	0:e8bfffbb3ab6	266	__I uint32_t IntStatus;
lynxeyed_atsu	0:e8bfffbb3ab6	267	__I uint32_t IO0IntStatR;
lynxeyed_atsu	0:e8bfffbb3ab6	268	__I uint32_t IO0IntStatF;
lynxeyed_atsu	0:e8bfffbb3ab6	269	__O uint32_t IO0IntClr;
lynxeyed_atsu	0:e8bfffbb3ab6	270	__IO uint32_t IO0IntEnR;
lynxeyed_atsu	0:e8bfffbb3ab6	271	__IO uint32_t IO0IntEnF;
lynxeyed_atsu	0:e8bfffbb3ab6	272	uint32_t RESERVED0[3];
lynxeyed_atsu	0:e8bfffbb3ab6	273	__I uint32_t IO2IntStatR;
lynxeyed_atsu	0:e8bfffbb3ab6	274	__I uint32_t IO2IntStatF;
lynxeyed_atsu	0:e8bfffbb3ab6	275	__O uint32_t IO2IntClr;
lynxeyed_atsu	0:e8bfffbb3ab6	276	__IO uint32_t IO2IntEnR;
lynxeyed_atsu	0:e8bfffbb3ab6	277	__IO uint32_t IO2IntEnF;
lynxeyed_atsu	0:e8bfffbb3ab6	278	} LPC_GPIOINT_TypeDef;
lynxeyed_atsu	0:e8bfffbb3ab6	279
lynxeyed_atsu	0:e8bfffbb3ab6	280	/------------- Timer (TIM) --------------------------------------------------/
lynxeyed_atsu	0:e8bfffbb3ab6	281	/** @brief Timer (TIM) register structure definition */
lynxeyed_atsu	0:e8bfffbb3ab6	282	typedef struct
lynxeyed_atsu	0:e8bfffbb3ab6	283	{
lynxeyed_atsu	0:e8bfffbb3ab6	284	__IO uint32_t IR;
lynxeyed_atsu	0:e8bfffbb3ab6	285	__IO uint32_t TCR;
lynxeyed_atsu	0:e8bfffbb3ab6	286	__IO uint32_t TC;
lynxeyed_atsu	0:e8bfffbb3ab6	287	__IO uint32_t PR;
lynxeyed_atsu	0:e8bfffbb3ab6	288	__IO uint32_t PC;
lynxeyed_atsu	0:e8bfffbb3ab6	289	__IO uint32_t MCR;
lynxeyed_atsu	0:e8bfffbb3ab6	290	__IO uint32_t MR0;
lynxeyed_atsu	0:e8bfffbb3ab6	291	__IO uint32_t MR1;
lynxeyed_atsu	0:e8bfffbb3ab6	292	__IO uint32_t MR2;
lynxeyed_atsu	0:e8bfffbb3ab6	293	__IO uint32_t MR3;
lynxeyed_atsu	0:e8bfffbb3ab6	294	__IO uint32_t CCR;
lynxeyed_atsu	0:e8bfffbb3ab6	295	__I uint32_t CR0;
lynxeyed_atsu	0:e8bfffbb3ab6	296	__I uint32_t CR1;
lynxeyed_atsu	0:e8bfffbb3ab6	297	uint32_t RESERVED0[2];
lynxeyed_atsu	0:e8bfffbb3ab6	298	__IO uint32_t EMR;
lynxeyed_atsu	0:e8bfffbb3ab6	299	uint32_t RESERVED1[12];
lynxeyed_atsu	0:e8bfffbb3ab6	300	__IO uint32_t CTCR;
lynxeyed_atsu	0:e8bfffbb3ab6	301	} LPC_TIM_TypeDef;
lynxeyed_atsu	0:e8bfffbb3ab6	302
lynxeyed_atsu	0:e8bfffbb3ab6	303	/------------- Pulse-Width Modulation (PWM) ---------------------------------/
lynxeyed_atsu	0:e8bfffbb3ab6	304	/** @brief Pulse-Width Modulation (PWM) register structure definition */
lynxeyed_atsu	0:e8bfffbb3ab6	305	typedef struct
lynxeyed_atsu	0:e8bfffbb3ab6	306	{
lynxeyed_atsu	0:e8bfffbb3ab6	307	__IO uint32_t IR;
lynxeyed_atsu	0:e8bfffbb3ab6	308	__IO uint32_t TCR;
lynxeyed_atsu	0:e8bfffbb3ab6	309	__IO uint32_t TC;
lynxeyed_atsu	0:e8bfffbb3ab6	310	__IO uint32_t PR;
lynxeyed_atsu	0:e8bfffbb3ab6	311	__IO uint32_t PC;
lynxeyed_atsu	0:e8bfffbb3ab6	312	__IO uint32_t MCR;
lynxeyed_atsu	0:e8bfffbb3ab6	313	__IO uint32_t MR0;
lynxeyed_atsu	0:e8bfffbb3ab6	314	__IO uint32_t MR1;
lynxeyed_atsu	0:e8bfffbb3ab6	315	__IO uint32_t MR2;
lynxeyed_atsu	0:e8bfffbb3ab6	316	__IO uint32_t MR3;
lynxeyed_atsu	0:e8bfffbb3ab6	317	__IO uint32_t CCR;
lynxeyed_atsu	0:e8bfffbb3ab6	318	__I uint32_t CR0;
lynxeyed_atsu	0:e8bfffbb3ab6	319	__I uint32_t CR1;
lynxeyed_atsu	0:e8bfffbb3ab6	320	__I uint32_t CR2;
lynxeyed_atsu	0:e8bfffbb3ab6	321	__I uint32_t CR3;
lynxeyed_atsu	0:e8bfffbb3ab6	322	uint32_t RESERVED0;
lynxeyed_atsu	0:e8bfffbb3ab6	323	__IO uint32_t MR4;
lynxeyed_atsu	0:e8bfffbb3ab6	324	__IO uint32_t MR5;
lynxeyed_atsu	0:e8bfffbb3ab6	325	__IO uint32_t MR6;
lynxeyed_atsu	0:e8bfffbb3ab6	326	__IO uint32_t PCR;
lynxeyed_atsu	0:e8bfffbb3ab6	327	__IO uint32_t LER;
lynxeyed_atsu	0:e8bfffbb3ab6	328	uint32_t RESERVED1[7];
lynxeyed_atsu	0:e8bfffbb3ab6	329	__IO uint32_t CTCR;
lynxeyed_atsu	0:e8bfffbb3ab6	330	} LPC_PWM_TypeDef;
lynxeyed_atsu	0:e8bfffbb3ab6	331
lynxeyed_atsu	0:e8bfffbb3ab6	332	/------------- Universal Asynchronous Receiver Transmitter (UART) -----------/
lynxeyed_atsu	0:e8bfffbb3ab6	333	/** @brief Universal Asynchronous Receiver Transmitter (UART) register structure definition */
lynxeyed_atsu	0:e8bfffbb3ab6	334	typedef struct
lynxeyed_atsu	0:e8bfffbb3ab6	335	{
lynxeyed_atsu	0:e8bfffbb3ab6	336	union {
lynxeyed_atsu	0:e8bfffbb3ab6	337	__I uint8_t RBR;
lynxeyed_atsu	0:e8bfffbb3ab6	338	__O uint8_t THR;
lynxeyed_atsu	0:e8bfffbb3ab6	339	__IO uint8_t DLL;
lynxeyed_atsu	0:e8bfffbb3ab6	340	uint32_t RESERVED0;
lynxeyed_atsu	0:e8bfffbb3ab6	341	};
lynxeyed_atsu	0:e8bfffbb3ab6	342	union {
lynxeyed_atsu	0:e8bfffbb3ab6	343	__IO uint8_t DLM;
lynxeyed_atsu	0:e8bfffbb3ab6	344	__IO uint32_t IER;
lynxeyed_atsu	0:e8bfffbb3ab6	345	};
lynxeyed_atsu	0:e8bfffbb3ab6	346	union {
lynxeyed_atsu	0:e8bfffbb3ab6	347	__I uint32_t IIR;
lynxeyed_atsu	0:e8bfffbb3ab6	348	__O uint8_t FCR;
lynxeyed_atsu	0:e8bfffbb3ab6	349	};
lynxeyed_atsu	0:e8bfffbb3ab6	350	__IO uint8_t LCR;
lynxeyed_atsu	0:e8bfffbb3ab6	351	uint8_t RESERVED1[7];
lynxeyed_atsu	0:e8bfffbb3ab6	352	__I uint8_t LSR;
lynxeyed_atsu	0:e8bfffbb3ab6	353	uint8_t RESERVED2[7];
lynxeyed_atsu	0:e8bfffbb3ab6	354	__IO uint8_t SCR;
lynxeyed_atsu	0:e8bfffbb3ab6	355	uint8_t RESERVED3[3];
lynxeyed_atsu	0:e8bfffbb3ab6	356	__IO uint32_t ACR;
lynxeyed_atsu	0:e8bfffbb3ab6	357	__IO uint8_t ICR;
lynxeyed_atsu	0:e8bfffbb3ab6	358	uint8_t RESERVED4[3];
lynxeyed_atsu	0:e8bfffbb3ab6	359	__IO uint8_t FDR;
lynxeyed_atsu	0:e8bfffbb3ab6	360	uint8_t RESERVED5[7];
lynxeyed_atsu	0:e8bfffbb3ab6	361	__IO uint8_t TER;
lynxeyed_atsu	0:e8bfffbb3ab6	362	uint8_t RESERVED6[39];
lynxeyed_atsu	0:e8bfffbb3ab6	363	__I uint8_t FIFOLVL;
lynxeyed_atsu	0:e8bfffbb3ab6	364	} LPC_UART_TypeDef;
lynxeyed_atsu	0:e8bfffbb3ab6	365
lynxeyed_atsu	0:e8bfffbb3ab6	366	/** @brief Universal Asynchronous Receiver Transmitter 0 (UART0) register structure definition */
lynxeyed_atsu	0:e8bfffbb3ab6	367	typedef struct
lynxeyed_atsu	0:e8bfffbb3ab6	368	{
lynxeyed_atsu	0:e8bfffbb3ab6	369	union {
lynxeyed_atsu	0:e8bfffbb3ab6	370	__I uint8_t RBR;
lynxeyed_atsu	0:e8bfffbb3ab6	371	__O uint8_t THR;
lynxeyed_atsu	0:e8bfffbb3ab6	372	__IO uint8_t DLL;
lynxeyed_atsu	0:e8bfffbb3ab6	373	uint32_t RESERVED0;
lynxeyed_atsu	0:e8bfffbb3ab6	374	};
lynxeyed_atsu	0:e8bfffbb3ab6	375	union {
lynxeyed_atsu	0:e8bfffbb3ab6	376	__IO uint8_t DLM;
lynxeyed_atsu	0:e8bfffbb3ab6	377	__IO uint32_t IER;
lynxeyed_atsu	0:e8bfffbb3ab6	378	};
lynxeyed_atsu	0:e8bfffbb3ab6	379	union {
lynxeyed_atsu	0:e8bfffbb3ab6	380	__I uint32_t IIR;
lynxeyed_atsu	0:e8bfffbb3ab6	381	__O uint8_t FCR;
lynxeyed_atsu	0:e8bfffbb3ab6	382	};
lynxeyed_atsu	0:e8bfffbb3ab6	383	__IO uint8_t LCR;
lynxeyed_atsu	0:e8bfffbb3ab6	384	uint8_t RESERVED1[7];
lynxeyed_atsu	0:e8bfffbb3ab6	385	__I uint8_t LSR;
lynxeyed_atsu	0:e8bfffbb3ab6	386	uint8_t RESERVED2[7];
lynxeyed_atsu	0:e8bfffbb3ab6	387	__IO uint8_t SCR;
lynxeyed_atsu	0:e8bfffbb3ab6	388	uint8_t RESERVED3[3];
lynxeyed_atsu	0:e8bfffbb3ab6	389	__IO uint32_t ACR;
lynxeyed_atsu	0:e8bfffbb3ab6	390	__IO uint8_t ICR;
lynxeyed_atsu	0:e8bfffbb3ab6	391	uint8_t RESERVED4[3];
lynxeyed_atsu	0:e8bfffbb3ab6	392	__IO uint8_t FDR;
lynxeyed_atsu	0:e8bfffbb3ab6	393	uint8_t RESERVED5[7];
lynxeyed_atsu	0:e8bfffbb3ab6	394	__IO uint8_t TER;
lynxeyed_atsu	0:e8bfffbb3ab6	395	uint8_t RESERVED6[39];
lynxeyed_atsu	0:e8bfffbb3ab6	396	__I uint8_t FIFOLVL;
lynxeyed_atsu	0:e8bfffbb3ab6	397	} LPC_UART0_TypeDef;
lynxeyed_atsu	0:e8bfffbb3ab6	398
lynxeyed_atsu	0:e8bfffbb3ab6	399	/** @brief Universal Asynchronous Receiver Transmitter 1 (UART1) register structure definition */
lynxeyed_atsu	0:e8bfffbb3ab6	400	typedef struct
lynxeyed_atsu	0:e8bfffbb3ab6	401	{
lynxeyed_atsu	0:e8bfffbb3ab6	402	union {
lynxeyed_atsu	0:e8bfffbb3ab6	403	__I uint8_t RBR;
lynxeyed_atsu	0:e8bfffbb3ab6	404	__O uint8_t THR;
lynxeyed_atsu	0:e8bfffbb3ab6	405	__IO uint8_t DLL;
lynxeyed_atsu	0:e8bfffbb3ab6	406	uint32_t RESERVED0;
lynxeyed_atsu	0:e8bfffbb3ab6	407	};
lynxeyed_atsu	0:e8bfffbb3ab6	408	union {
lynxeyed_atsu	0:e8bfffbb3ab6	409	__IO uint8_t DLM;
lynxeyed_atsu	0:e8bfffbb3ab6	410	__IO uint32_t IER;
lynxeyed_atsu	0:e8bfffbb3ab6	411	};
lynxeyed_atsu	0:e8bfffbb3ab6	412	union {
lynxeyed_atsu	0:e8bfffbb3ab6	413	__I uint32_t IIR;
lynxeyed_atsu	0:e8bfffbb3ab6	414	__O uint8_t FCR;
lynxeyed_atsu	0:e8bfffbb3ab6	415	};
lynxeyed_atsu	0:e8bfffbb3ab6	416	__IO uint8_t LCR;
lynxeyed_atsu	0:e8bfffbb3ab6	417	uint8_t RESERVED1[3];
lynxeyed_atsu	0:e8bfffbb3ab6	418	__IO uint8_t MCR;
lynxeyed_atsu	0:e8bfffbb3ab6	419	uint8_t RESERVED2[3];
lynxeyed_atsu	0:e8bfffbb3ab6	420	__I uint8_t LSR;
lynxeyed_atsu	0:e8bfffbb3ab6	421	uint8_t RESERVED3[3];
lynxeyed_atsu	0:e8bfffbb3ab6	422	__I uint8_t MSR;
lynxeyed_atsu	0:e8bfffbb3ab6	423	uint8_t RESERVED4[3];
lynxeyed_atsu	0:e8bfffbb3ab6	424	__IO uint8_t SCR;
lynxeyed_atsu	0:e8bfffbb3ab6	425	uint8_t RESERVED5[3];
lynxeyed_atsu	0:e8bfffbb3ab6	426	__IO uint32_t ACR;
lynxeyed_atsu	0:e8bfffbb3ab6	427	uint32_t RESERVED6;
lynxeyed_atsu	0:e8bfffbb3ab6	428	__IO uint32_t FDR;
lynxeyed_atsu	0:e8bfffbb3ab6	429	uint32_t RESERVED7;
lynxeyed_atsu	0:e8bfffbb3ab6	430	__IO uint8_t TER;
lynxeyed_atsu	0:e8bfffbb3ab6	431	uint8_t RESERVED8[27];
lynxeyed_atsu	0:e8bfffbb3ab6	432	__IO uint8_t RS485CTRL;
lynxeyed_atsu	0:e8bfffbb3ab6	433	uint8_t RESERVED9[3];
lynxeyed_atsu	0:e8bfffbb3ab6	434	__IO uint8_t ADRMATCH;
lynxeyed_atsu	0:e8bfffbb3ab6	435	uint8_t RESERVED10[3];
lynxeyed_atsu	0:e8bfffbb3ab6	436	__IO uint8_t RS485DLY;
lynxeyed_atsu	0:e8bfffbb3ab6	437	uint8_t RESERVED11[3];
lynxeyed_atsu	0:e8bfffbb3ab6	438	__I uint8_t FIFOLVL;
lynxeyed_atsu	0:e8bfffbb3ab6	439	} LPC_UART1_TypeDef;
lynxeyed_atsu	0:e8bfffbb3ab6	440
lynxeyed_atsu	0:e8bfffbb3ab6	441	/------------- Serial Peripheral Interface (SPI) ----------------------------/
lynxeyed_atsu	0:e8bfffbb3ab6	442	/** @brief Serial Peripheral Interface (SPI) register structure definition */
lynxeyed_atsu	0:e8bfffbb3ab6	443	typedef struct
lynxeyed_atsu	0:e8bfffbb3ab6	444	{
lynxeyed_atsu	0:e8bfffbb3ab6	445	__IO uint32_t SPCR;
lynxeyed_atsu	0:e8bfffbb3ab6	446	__I uint32_t SPSR;
lynxeyed_atsu	0:e8bfffbb3ab6	447	__IO uint32_t SPDR;
lynxeyed_atsu	0:e8bfffbb3ab6	448	__IO uint32_t SPCCR;
lynxeyed_atsu	0:e8bfffbb3ab6	449	uint32_t RESERVED0[3];
lynxeyed_atsu	0:e8bfffbb3ab6	450	__IO uint32_t SPINT;
lynxeyed_atsu	0:e8bfffbb3ab6	451	} LPC_SPI_TypeDef;
lynxeyed_atsu	0:e8bfffbb3ab6	452
lynxeyed_atsu	0:e8bfffbb3ab6	453	/------------- Synchronous Serial Communication (SSP) -----------------------/
lynxeyed_atsu	0:e8bfffbb3ab6	454	/** @brief Synchronous Serial Communication (SSP) register structure definition */
lynxeyed_atsu	0:e8bfffbb3ab6	455	typedef struct
lynxeyed_atsu	0:e8bfffbb3ab6	456	{
lynxeyed_atsu	0:e8bfffbb3ab6	457	__IO uint32_t CR0;
lynxeyed_atsu	0:e8bfffbb3ab6	458	__IO uint32_t CR1;
lynxeyed_atsu	0:e8bfffbb3ab6	459	__IO uint32_t DR;
lynxeyed_atsu	0:e8bfffbb3ab6	460	__I uint32_t SR;
lynxeyed_atsu	0:e8bfffbb3ab6	461	__IO uint32_t CPSR;
lynxeyed_atsu	0:e8bfffbb3ab6	462	__IO uint32_t IMSC;
lynxeyed_atsu	0:e8bfffbb3ab6	463	__IO uint32_t RIS;
lynxeyed_atsu	0:e8bfffbb3ab6	464	__IO uint32_t MIS;
lynxeyed_atsu	0:e8bfffbb3ab6	465	__IO uint32_t ICR;
lynxeyed_atsu	0:e8bfffbb3ab6	466	__IO uint32_t DMACR;
lynxeyed_atsu	0:e8bfffbb3ab6	467	} LPC_SSP_TypeDef;
lynxeyed_atsu	0:e8bfffbb3ab6	468
lynxeyed_atsu	0:e8bfffbb3ab6	469	/------------- Inter-Integrated Circuit (I2C) -------------------------------/
lynxeyed_atsu	0:e8bfffbb3ab6	470	/** @brief Inter-Integrated Circuit (I2C) register structure definition */
lynxeyed_atsu	0:e8bfffbb3ab6	471	typedef struct
lynxeyed_atsu	0:e8bfffbb3ab6	472	{
lynxeyed_atsu	0:e8bfffbb3ab6	473	__IO uint32_t I2CONSET;
lynxeyed_atsu	0:e8bfffbb3ab6	474	__I uint32_t I2STAT;
lynxeyed_atsu	0:e8bfffbb3ab6	475	__IO uint32_t I2DAT;
lynxeyed_atsu	0:e8bfffbb3ab6	476	__IO uint32_t I2ADR0;
lynxeyed_atsu	0:e8bfffbb3ab6	477	__IO uint32_t I2SCLH;
lynxeyed_atsu	0:e8bfffbb3ab6	478	__IO uint32_t I2SCLL;
lynxeyed_atsu	0:e8bfffbb3ab6	479	__O uint32_t I2CONCLR;
lynxeyed_atsu	0:e8bfffbb3ab6	480	__IO uint32_t MMCTRL;
lynxeyed_atsu	0:e8bfffbb3ab6	481	__IO uint32_t I2ADR1;
lynxeyed_atsu	0:e8bfffbb3ab6	482	__IO uint32_t I2ADR2;
lynxeyed_atsu	0:e8bfffbb3ab6	483	__IO uint32_t I2ADR3;
lynxeyed_atsu	0:e8bfffbb3ab6	484	__I uint32_t I2DATA_BUFFER;
lynxeyed_atsu	0:e8bfffbb3ab6	485	__IO uint32_t I2MASK0;
lynxeyed_atsu	0:e8bfffbb3ab6	486	__IO uint32_t I2MASK1;
lynxeyed_atsu	0:e8bfffbb3ab6	487	__IO uint32_t I2MASK2;
lynxeyed_atsu	0:e8bfffbb3ab6	488	__IO uint32_t I2MASK3;
lynxeyed_atsu	0:e8bfffbb3ab6	489	} LPC_I2C_TypeDef;
lynxeyed_atsu	0:e8bfffbb3ab6	490
lynxeyed_atsu	0:e8bfffbb3ab6	491	/------------- Inter IC Sound (I2S) -----------------------------------------/
lynxeyed_atsu	0:e8bfffbb3ab6	492	/** @brief Inter IC Sound (I2S) register structure definition */
lynxeyed_atsu	0:e8bfffbb3ab6	493	typedef struct
lynxeyed_atsu	0:e8bfffbb3ab6	494	{
lynxeyed_atsu	0:e8bfffbb3ab6	495	__IO uint32_t I2SDAO;
lynxeyed_atsu	0:e8bfffbb3ab6	496	__IO uint32_t I2SDAI;
lynxeyed_atsu	0:e8bfffbb3ab6	497	__O uint32_t I2STXFIFO;
lynxeyed_atsu	0:e8bfffbb3ab6	498	__I uint32_t I2SRXFIFO;
lynxeyed_atsu	0:e8bfffbb3ab6	499	__I uint32_t I2SSTATE;
lynxeyed_atsu	0:e8bfffbb3ab6	500	__IO uint32_t I2SDMA1;
lynxeyed_atsu	0:e8bfffbb3ab6	501	__IO uint32_t I2SDMA2;
lynxeyed_atsu	0:e8bfffbb3ab6	502	__IO uint32_t I2SIRQ;
lynxeyed_atsu	0:e8bfffbb3ab6	503	__IO uint32_t I2STXRATE;
lynxeyed_atsu	0:e8bfffbb3ab6	504	__IO uint32_t I2SRXRATE;
lynxeyed_atsu	0:e8bfffbb3ab6	505	__IO uint32_t I2STXBITRATE;
lynxeyed_atsu	0:e8bfffbb3ab6	506	__IO uint32_t I2SRXBITRATE;
lynxeyed_atsu	0:e8bfffbb3ab6	507	__IO uint32_t I2STXMODE;
lynxeyed_atsu	0:e8bfffbb3ab6	508	__IO uint32_t I2SRXMODE;
lynxeyed_atsu	0:e8bfffbb3ab6	509	} LPC_I2S_TypeDef;
lynxeyed_atsu	0:e8bfffbb3ab6	510
lynxeyed_atsu	0:e8bfffbb3ab6	511	/------------- Repetitive Interrupt Timer (RIT) -----------------------------/
lynxeyed_atsu	0:e8bfffbb3ab6	512	/** @brief Repetitive Interrupt Timer (RIT) register structure definition */
lynxeyed_atsu	0:e8bfffbb3ab6	513	typedef struct
lynxeyed_atsu	0:e8bfffbb3ab6	514	{
lynxeyed_atsu	0:e8bfffbb3ab6	515	__IO uint32_t RICOMPVAL;
lynxeyed_atsu	0:e8bfffbb3ab6	516	__IO uint32_t RIMASK;
lynxeyed_atsu	0:e8bfffbb3ab6	517	__IO uint8_t RICTRL;
lynxeyed_atsu	0:e8bfffbb3ab6	518	uint8_t RESERVED0[3];
lynxeyed_atsu	0:e8bfffbb3ab6	519	__IO uint32_t RICOUNTER;
lynxeyed_atsu	0:e8bfffbb3ab6	520	} LPC_RIT_TypeDef;
lynxeyed_atsu	0:e8bfffbb3ab6	521
lynxeyed_atsu	0:e8bfffbb3ab6	522	/------------- Real-Time Clock (RTC) ----------------------------------------/
lynxeyed_atsu	0:e8bfffbb3ab6	523	/** @brief Real-Time Clock (RTC) register structure definition */
lynxeyed_atsu	0:e8bfffbb3ab6	524	typedef struct
lynxeyed_atsu	0:e8bfffbb3ab6	525	{
lynxeyed_atsu	0:e8bfffbb3ab6	526	__IO uint8_t ILR;
lynxeyed_atsu	0:e8bfffbb3ab6	527	uint8_t RESERVED0[7];
lynxeyed_atsu	0:e8bfffbb3ab6	528	__IO uint8_t CCR;
lynxeyed_atsu	0:e8bfffbb3ab6	529	uint8_t RESERVED1[3];
lynxeyed_atsu	0:e8bfffbb3ab6	530	__IO uint8_t CIIR;
lynxeyed_atsu	0:e8bfffbb3ab6	531	uint8_t RESERVED2[3];
lynxeyed_atsu	0:e8bfffbb3ab6	532	__IO uint8_t AMR;
lynxeyed_atsu	0:e8bfffbb3ab6	533	uint8_t RESERVED3[3];
lynxeyed_atsu	0:e8bfffbb3ab6	534	__I uint32_t CTIME0;
lynxeyed_atsu	0:e8bfffbb3ab6	535	__I uint32_t CTIME1;
lynxeyed_atsu	0:e8bfffbb3ab6	536	__I uint32_t CTIME2;
lynxeyed_atsu	0:e8bfffbb3ab6	537	__IO uint8_t SEC;
lynxeyed_atsu	0:e8bfffbb3ab6	538	uint8_t RESERVED4[3];
lynxeyed_atsu	0:e8bfffbb3ab6	539	__IO uint8_t MIN;
lynxeyed_atsu	0:e8bfffbb3ab6	540	uint8_t RESERVED5[3];
lynxeyed_atsu	0:e8bfffbb3ab6	541	__IO uint8_t HOUR;
lynxeyed_atsu	0:e8bfffbb3ab6	542	uint8_t RESERVED6[3];
lynxeyed_atsu	0:e8bfffbb3ab6	543	__IO uint8_t DOM;
lynxeyed_atsu	0:e8bfffbb3ab6	544	uint8_t RESERVED7[3];
lynxeyed_atsu	0:e8bfffbb3ab6	545	__IO uint8_t DOW;
lynxeyed_atsu	0:e8bfffbb3ab6	546	uint8_t RESERVED8[3];
lynxeyed_atsu	0:e8bfffbb3ab6	547	__IO uint16_t DOY;
lynxeyed_atsu	0:e8bfffbb3ab6	548	uint16_t RESERVED9;
lynxeyed_atsu	0:e8bfffbb3ab6	549	__IO uint8_t MONTH;
lynxeyed_atsu	0:e8bfffbb3ab6	550	uint8_t RESERVED10[3];
lynxeyed_atsu	0:e8bfffbb3ab6	551	__IO uint16_t YEAR;
lynxeyed_atsu	0:e8bfffbb3ab6	552	uint16_t RESERVED11;
lynxeyed_atsu	0:e8bfffbb3ab6	553	__IO uint32_t CALIBRATION;
lynxeyed_atsu	0:e8bfffbb3ab6	554	__IO uint32_t GPREG0;
lynxeyed_atsu	0:e8bfffbb3ab6	555	__IO uint32_t GPREG1;
lynxeyed_atsu	0:e8bfffbb3ab6	556	__IO uint32_t GPREG2;
lynxeyed_atsu	0:e8bfffbb3ab6	557	__IO uint32_t GPREG3;
lynxeyed_atsu	0:e8bfffbb3ab6	558	__IO uint32_t GPREG4;
lynxeyed_atsu	0:e8bfffbb3ab6	559	__IO uint8_t RTC_AUXEN;
lynxeyed_atsu	0:e8bfffbb3ab6	560	uint8_t RESERVED12[3];
lynxeyed_atsu	0:e8bfffbb3ab6	561	__IO uint8_t RTC_AUX;
lynxeyed_atsu	0:e8bfffbb3ab6	562	uint8_t RESERVED13[3];
lynxeyed_atsu	0:e8bfffbb3ab6	563	__IO uint8_t ALSEC;
lynxeyed_atsu	0:e8bfffbb3ab6	564	uint8_t RESERVED14[3];
lynxeyed_atsu	0:e8bfffbb3ab6	565	__IO uint8_t ALMIN;
lynxeyed_atsu	0:e8bfffbb3ab6	566	uint8_t RESERVED15[3];
lynxeyed_atsu	0:e8bfffbb3ab6	567	__IO uint8_t ALHOUR;
lynxeyed_atsu	0:e8bfffbb3ab6	568	uint8_t RESERVED16[3];
lynxeyed_atsu	0:e8bfffbb3ab6	569	__IO uint8_t ALDOM;
lynxeyed_atsu	0:e8bfffbb3ab6	570	uint8_t RESERVED17[3];
lynxeyed_atsu	0:e8bfffbb3ab6	571	__IO uint8_t ALDOW;
lynxeyed_atsu	0:e8bfffbb3ab6	572	uint8_t RESERVED18[3];
lynxeyed_atsu	0:e8bfffbb3ab6	573	__IO uint16_t ALDOY;
lynxeyed_atsu	0:e8bfffbb3ab6	574	uint16_t RESERVED19;
lynxeyed_atsu	0:e8bfffbb3ab6	575	__IO uint8_t ALMON;
lynxeyed_atsu	0:e8bfffbb3ab6	576	uint8_t RESERVED20[3];
lynxeyed_atsu	0:e8bfffbb3ab6	577	__IO uint16_t ALYEAR;
lynxeyed_atsu	0:e8bfffbb3ab6	578	uint16_t RESERVED21;
lynxeyed_atsu	0:e8bfffbb3ab6	579	} LPC_RTC_TypeDef;
lynxeyed_atsu	0:e8bfffbb3ab6	580
lynxeyed_atsu	0:e8bfffbb3ab6	581	/------------- Watchdog Timer (WDT) -----------------------------------------/
lynxeyed_atsu	0:e8bfffbb3ab6	582	/** @brief Watchdog Timer (WDT) register structure definition */
lynxeyed_atsu	0:e8bfffbb3ab6	583	typedef struct
lynxeyed_atsu	0:e8bfffbb3ab6	584	{
lynxeyed_atsu	0:e8bfffbb3ab6	585	__IO uint8_t WDMOD;
lynxeyed_atsu	0:e8bfffbb3ab6	586	uint8_t RESERVED0[3];
lynxeyed_atsu	0:e8bfffbb3ab6	587	__IO uint32_t WDTC;
lynxeyed_atsu	0:e8bfffbb3ab6	588	__O uint8_t WDFEED;
lynxeyed_atsu	0:e8bfffbb3ab6	589	uint8_t RESERVED1[3];
lynxeyed_atsu	0:e8bfffbb3ab6	590	__I uint32_t WDTV;
lynxeyed_atsu	0:e8bfffbb3ab6	591	__IO uint32_t WDCLKSEL;
lynxeyed_atsu	0:e8bfffbb3ab6	592	} LPC_WDT_TypeDef;
lynxeyed_atsu	0:e8bfffbb3ab6	593
lynxeyed_atsu	0:e8bfffbb3ab6	594	/------------- Analog-to-Digital Converter (ADC) ----------------------------/
lynxeyed_atsu	0:e8bfffbb3ab6	595	/** @brief Analog-to-Digital Converter (ADC) register structure definition */
lynxeyed_atsu	0:e8bfffbb3ab6	596	typedef struct
lynxeyed_atsu	0:e8bfffbb3ab6	597	{
lynxeyed_atsu	0:e8bfffbb3ab6	598	__IO uint32_t ADCR;
lynxeyed_atsu	0:e8bfffbb3ab6	599	__IO uint32_t ADGDR;
lynxeyed_atsu	0:e8bfffbb3ab6	600	uint32_t RESERVED0;
lynxeyed_atsu	0:e8bfffbb3ab6	601	__IO uint32_t ADINTEN;
lynxeyed_atsu	0:e8bfffbb3ab6	602	__I uint32_t ADDR0;
lynxeyed_atsu	0:e8bfffbb3ab6	603	__I uint32_t ADDR1;
lynxeyed_atsu	0:e8bfffbb3ab6	604	__I uint32_t ADDR2;
lynxeyed_atsu	0:e8bfffbb3ab6	605	__I uint32_t ADDR3;
lynxeyed_atsu	0:e8bfffbb3ab6	606	__I uint32_t ADDR4;
lynxeyed_atsu	0:e8bfffbb3ab6	607	__I uint32_t ADDR5;
lynxeyed_atsu	0:e8bfffbb3ab6	608	__I uint32_t ADDR6;
lynxeyed_atsu	0:e8bfffbb3ab6	609	__I uint32_t ADDR7;
lynxeyed_atsu	0:e8bfffbb3ab6	610	__I uint32_t ADSTAT;
lynxeyed_atsu	0:e8bfffbb3ab6	611	__IO uint32_t ADTRM;
lynxeyed_atsu	0:e8bfffbb3ab6	612	} LPC_ADC_TypeDef;
lynxeyed_atsu	0:e8bfffbb3ab6	613
lynxeyed_atsu	0:e8bfffbb3ab6	614	/------------- Digital-to-Analog Converter (DAC) ----------------------------/
lynxeyed_atsu	0:e8bfffbb3ab6	615	/** @brief Digital-to-Analog Converter (DAC) register structure definition */
lynxeyed_atsu	0:e8bfffbb3ab6	616	typedef struct
lynxeyed_atsu	0:e8bfffbb3ab6	617	{
lynxeyed_atsu	0:e8bfffbb3ab6	618	__IO uint32_t DACR;
lynxeyed_atsu	0:e8bfffbb3ab6	619	__IO uint32_t DACCTRL;
lynxeyed_atsu	0:e8bfffbb3ab6	620	__IO uint16_t DACCNTVAL;
lynxeyed_atsu	0:e8bfffbb3ab6	621	} LPC_DAC_TypeDef;
lynxeyed_atsu	0:e8bfffbb3ab6	622
lynxeyed_atsu	0:e8bfffbb3ab6	623	/------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------/
lynxeyed_atsu	0:e8bfffbb3ab6	624	/** @brief Motor Control Pulse-Width Modulation (MCPWM) register structure definition */
lynxeyed_atsu	0:e8bfffbb3ab6	625	typedef struct
lynxeyed_atsu	0:e8bfffbb3ab6	626	{
lynxeyed_atsu	0:e8bfffbb3ab6	627	__I uint32_t MCCON;
lynxeyed_atsu	0:e8bfffbb3ab6	628	__O uint32_t MCCON_SET;
lynxeyed_atsu	0:e8bfffbb3ab6	629	__O uint32_t MCCON_CLR;
lynxeyed_atsu	0:e8bfffbb3ab6	630	__I uint32_t MCCAPCON;
lynxeyed_atsu	0:e8bfffbb3ab6	631	__O uint32_t MCCAPCON_SET;
lynxeyed_atsu	0:e8bfffbb3ab6	632	__O uint32_t MCCAPCON_CLR;
lynxeyed_atsu	0:e8bfffbb3ab6	633	__IO uint32_t MCTIM0;
lynxeyed_atsu	0:e8bfffbb3ab6	634	__IO uint32_t MCTIM1;
lynxeyed_atsu	0:e8bfffbb3ab6	635	__IO uint32_t MCTIM2;
lynxeyed_atsu	0:e8bfffbb3ab6	636	__IO uint32_t MCPER0;
lynxeyed_atsu	0:e8bfffbb3ab6	637	__IO uint32_t MCPER1;
lynxeyed_atsu	0:e8bfffbb3ab6	638	__IO uint32_t MCPER2;
lynxeyed_atsu	0:e8bfffbb3ab6	639	__IO uint32_t MCPW0;
lynxeyed_atsu	0:e8bfffbb3ab6	640	__IO uint32_t MCPW1;
lynxeyed_atsu	0:e8bfffbb3ab6	641	__IO uint32_t MCPW2;
lynxeyed_atsu	0:e8bfffbb3ab6	642	__IO uint32_t MCDEADTIME;
lynxeyed_atsu	0:e8bfffbb3ab6	643	__IO uint32_t MCCCP;
lynxeyed_atsu	0:e8bfffbb3ab6	644	__IO uint32_t MCCR0;
lynxeyed_atsu	0:e8bfffbb3ab6	645	__IO uint32_t MCCR1;
lynxeyed_atsu	0:e8bfffbb3ab6	646	__IO uint32_t MCCR2;
lynxeyed_atsu	0:e8bfffbb3ab6	647	__I uint32_t MCINTEN;
lynxeyed_atsu	0:e8bfffbb3ab6	648	__O uint32_t MCINTEN_SET;
lynxeyed_atsu	0:e8bfffbb3ab6	649	__O uint32_t MCINTEN_CLR;
lynxeyed_atsu	0:e8bfffbb3ab6	650	__I uint32_t MCCNTCON;
lynxeyed_atsu	0:e8bfffbb3ab6	651	__O uint32_t MCCNTCON_SET;
lynxeyed_atsu	0:e8bfffbb3ab6	652	__O uint32_t MCCNTCON_CLR;
lynxeyed_atsu	0:e8bfffbb3ab6	653	__I uint32_t MCINTFLAG;
lynxeyed_atsu	0:e8bfffbb3ab6	654	__O uint32_t MCINTFLAG_SET;
lynxeyed_atsu	0:e8bfffbb3ab6	655	__O uint32_t MCINTFLAG_CLR;
lynxeyed_atsu	0:e8bfffbb3ab6	656	__O uint32_t MCCAP_CLR;
lynxeyed_atsu	0:e8bfffbb3ab6	657	} LPC_MCPWM_TypeDef;
lynxeyed_atsu	0:e8bfffbb3ab6	658
lynxeyed_atsu	0:e8bfffbb3ab6	659	/------------- Quadrature Encoder Interface (QEI) ---------------------------/
lynxeyed_atsu	0:e8bfffbb3ab6	660	/** @brief Quadrature Encoder Interface (QEI) register structure definition */
lynxeyed_atsu	0:e8bfffbb3ab6	661	typedef struct
lynxeyed_atsu	0:e8bfffbb3ab6	662	{
lynxeyed_atsu	0:e8bfffbb3ab6	663	__O uint32_t QEICON;
lynxeyed_atsu	0:e8bfffbb3ab6	664	__I uint32_t QEISTAT;
lynxeyed_atsu	0:e8bfffbb3ab6	665	__IO uint32_t QEICONF;
lynxeyed_atsu	0:e8bfffbb3ab6	666	__I uint32_t QEIPOS;
lynxeyed_atsu	0:e8bfffbb3ab6	667	__IO uint32_t QEIMAXPOS;
lynxeyed_atsu	0:e8bfffbb3ab6	668	__IO uint32_t CMPOS0;
lynxeyed_atsu	0:e8bfffbb3ab6	669	__IO uint32_t CMPOS1;
lynxeyed_atsu	0:e8bfffbb3ab6	670	__IO uint32_t CMPOS2;
lynxeyed_atsu	0:e8bfffbb3ab6	671	__I uint32_t INXCNT;
lynxeyed_atsu	0:e8bfffbb3ab6	672	__IO uint32_t INXCMP;
lynxeyed_atsu	0:e8bfffbb3ab6	673	__IO uint32_t QEILOAD;
lynxeyed_atsu	0:e8bfffbb3ab6	674	__I uint32_t QEITIME;
lynxeyed_atsu	0:e8bfffbb3ab6	675	__I uint32_t QEIVEL;
lynxeyed_atsu	0:e8bfffbb3ab6	676	__I uint32_t QEICAP;
lynxeyed_atsu	0:e8bfffbb3ab6	677	__IO uint32_t VELCOMP;
lynxeyed_atsu	0:e8bfffbb3ab6	678	__IO uint32_t FILTER;
lynxeyed_atsu	0:e8bfffbb3ab6	679	uint32_t RESERVED0[998];
lynxeyed_atsu	0:e8bfffbb3ab6	680	__O uint32_t QEIIEC;
lynxeyed_atsu	0:e8bfffbb3ab6	681	__O uint32_t QEIIES;
lynxeyed_atsu	0:e8bfffbb3ab6	682	__I uint32_t QEIINTSTAT;
lynxeyed_atsu	0:e8bfffbb3ab6	683	__I uint32_t QEIIE;
lynxeyed_atsu	0:e8bfffbb3ab6	684	__O uint32_t QEICLR;
lynxeyed_atsu	0:e8bfffbb3ab6	685	__O uint32_t QEISET;
lynxeyed_atsu	0:e8bfffbb3ab6	686	} LPC_QEI_TypeDef;
lynxeyed_atsu	0:e8bfffbb3ab6	687
lynxeyed_atsu	0:e8bfffbb3ab6	688	/------------- Controller Area Network (CAN) --------------------------------/
lynxeyed_atsu	0:e8bfffbb3ab6	689	/** @brief Controller Area Network Acceptance Filter RAM (CANAF_RAM)structure definition */
lynxeyed_atsu	0:e8bfffbb3ab6	690	typedef struct
lynxeyed_atsu	0:e8bfffbb3ab6	691	{
lynxeyed_atsu	0:e8bfffbb3ab6	692	__IO uint32_t mask[512]; /* ID Masks */
lynxeyed_atsu	0:e8bfffbb3ab6	693	} LPC_CANAF_RAM_TypeDef;
lynxeyed_atsu	0:e8bfffbb3ab6	694
lynxeyed_atsu	0:e8bfffbb3ab6	695	/** @brief Controller Area Network Acceptance Filter(CANAF) register structure definition */
lynxeyed_atsu	0:e8bfffbb3ab6	696	typedef struct /* Acceptance Filter Registers */
lynxeyed_atsu	0:e8bfffbb3ab6	697	{
lynxeyed_atsu	0:e8bfffbb3ab6	698	__IO uint32_t AFMR;
lynxeyed_atsu	0:e8bfffbb3ab6	699	__IO uint32_t SFF_sa;
lynxeyed_atsu	0:e8bfffbb3ab6	700	__IO uint32_t SFF_GRP_sa;
lynxeyed_atsu	0:e8bfffbb3ab6	701	__IO uint32_t EFF_sa;
lynxeyed_atsu	0:e8bfffbb3ab6	702	__IO uint32_t EFF_GRP_sa;
lynxeyed_atsu	0:e8bfffbb3ab6	703	__IO uint32_t ENDofTable;
lynxeyed_atsu	0:e8bfffbb3ab6	704	__I uint32_t LUTerrAd;
lynxeyed_atsu	0:e8bfffbb3ab6	705	__I uint32_t LUTerr;
lynxeyed_atsu	0:e8bfffbb3ab6	706	__IO uint32_t FCANIE;
lynxeyed_atsu	0:e8bfffbb3ab6	707	__IO uint32_t FCANIC0;
lynxeyed_atsu	0:e8bfffbb3ab6	708	__IO uint32_t FCANIC1;
lynxeyed_atsu	0:e8bfffbb3ab6	709	} LPC_CANAF_TypeDef;
lynxeyed_atsu	0:e8bfffbb3ab6	710
lynxeyed_atsu	0:e8bfffbb3ab6	711	/** @brief Controller Area Network Central (CANCR) register structure definition */
lynxeyed_atsu	0:e8bfffbb3ab6	712	typedef struct /* Central Registers */
lynxeyed_atsu	0:e8bfffbb3ab6	713	{
lynxeyed_atsu	0:e8bfffbb3ab6	714	__I uint32_t CANTxSR;
lynxeyed_atsu	0:e8bfffbb3ab6	715	__I uint32_t CANRxSR;
lynxeyed_atsu	0:e8bfffbb3ab6	716	__I uint32_t CANMSR;
lynxeyed_atsu	0:e8bfffbb3ab6	717	} LPC_CANCR_TypeDef;
lynxeyed_atsu	0:e8bfffbb3ab6	718
lynxeyed_atsu	0:e8bfffbb3ab6	719	/** @brief Controller Area Network Controller (CAN) register structure definition */
lynxeyed_atsu	0:e8bfffbb3ab6	720	typedef struct /* Controller Registers */
lynxeyed_atsu	0:e8bfffbb3ab6	721	{
lynxeyed_atsu	0:e8bfffbb3ab6	722	__IO uint32_t MOD;
lynxeyed_atsu	0:e8bfffbb3ab6	723	__O uint32_t CMR;
lynxeyed_atsu	0:e8bfffbb3ab6	724	__IO uint32_t GSR;
lynxeyed_atsu	0:e8bfffbb3ab6	725	__I uint32_t ICR;
lynxeyed_atsu	0:e8bfffbb3ab6	726	__IO uint32_t IER;
lynxeyed_atsu	0:e8bfffbb3ab6	727	__IO uint32_t BTR;
lynxeyed_atsu	0:e8bfffbb3ab6	728	__IO uint32_t EWL;
lynxeyed_atsu	0:e8bfffbb3ab6	729	__I uint32_t SR;
lynxeyed_atsu	0:e8bfffbb3ab6	730	__IO uint32_t RFS;
lynxeyed_atsu	0:e8bfffbb3ab6	731	__IO uint32_t RID;
lynxeyed_atsu	0:e8bfffbb3ab6	732	__IO uint32_t RDA;
lynxeyed_atsu	0:e8bfffbb3ab6	733	__IO uint32_t RDB;
lynxeyed_atsu	0:e8bfffbb3ab6	734	__IO uint32_t TFI1;
lynxeyed_atsu	0:e8bfffbb3ab6	735	__IO uint32_t TID1;
lynxeyed_atsu	0:e8bfffbb3ab6	736	__IO uint32_t TDA1;
lynxeyed_atsu	0:e8bfffbb3ab6	737	__IO uint32_t TDB1;
lynxeyed_atsu	0:e8bfffbb3ab6	738	__IO uint32_t TFI2;
lynxeyed_atsu	0:e8bfffbb3ab6	739	__IO uint32_t TID2;
lynxeyed_atsu	0:e8bfffbb3ab6	740	__IO uint32_t TDA2;
lynxeyed_atsu	0:e8bfffbb3ab6	741	__IO uint32_t TDB2;
lynxeyed_atsu	0:e8bfffbb3ab6	742	__IO uint32_t TFI3;
lynxeyed_atsu	0:e8bfffbb3ab6	743	__IO uint32_t TID3;
lynxeyed_atsu	0:e8bfffbb3ab6	744	__IO uint32_t TDA3;
lynxeyed_atsu	0:e8bfffbb3ab6	745	__IO uint32_t TDB3;
lynxeyed_atsu	0:e8bfffbb3ab6	746	} LPC_CAN_TypeDef;
lynxeyed_atsu	0:e8bfffbb3ab6	747
lynxeyed_atsu	0:e8bfffbb3ab6	748	/------------- General Purpose Direct Memory Access (GPDMA) -----------------/
lynxeyed_atsu	0:e8bfffbb3ab6	749	/** @brief General Purpose Direct Memory Access (GPDMA) register structure definition */
lynxeyed_atsu	0:e8bfffbb3ab6	750	typedef struct /* Common Registers */
lynxeyed_atsu	0:e8bfffbb3ab6	751	{
lynxeyed_atsu	0:e8bfffbb3ab6	752	__I uint32_t DMACIntStat;
lynxeyed_atsu	0:e8bfffbb3ab6	753	__I uint32_t DMACIntTCStat;
lynxeyed_atsu	0:e8bfffbb3ab6	754	__O uint32_t DMACIntTCClear;
lynxeyed_atsu	0:e8bfffbb3ab6	755	__I uint32_t DMACIntErrStat;
lynxeyed_atsu	0:e8bfffbb3ab6	756	__O uint32_t DMACIntErrClr;
lynxeyed_atsu	0:e8bfffbb3ab6	757	__I uint32_t DMACRawIntTCStat;
lynxeyed_atsu	0:e8bfffbb3ab6	758	__I uint32_t DMACRawIntErrStat;
lynxeyed_atsu	0:e8bfffbb3ab6	759	__I uint32_t DMACEnbldChns;
lynxeyed_atsu	0:e8bfffbb3ab6	760	__IO uint32_t DMACSoftBReq;
lynxeyed_atsu	0:e8bfffbb3ab6	761	__IO uint32_t DMACSoftSReq;
lynxeyed_atsu	0:e8bfffbb3ab6	762	__IO uint32_t DMACSoftLBReq;
lynxeyed_atsu	0:e8bfffbb3ab6	763	__IO uint32_t DMACSoftLSReq;
lynxeyed_atsu	0:e8bfffbb3ab6	764	__IO uint32_t DMACConfig;
lynxeyed_atsu	0:e8bfffbb3ab6	765	__IO uint32_t DMACSync;
lynxeyed_atsu	0:e8bfffbb3ab6	766	} LPC_GPDMA_TypeDef;
lynxeyed_atsu	0:e8bfffbb3ab6	767
lynxeyed_atsu	0:e8bfffbb3ab6	768	/** @brief General Purpose Direct Memory Access Channel (GPDMACH) register structure definition */
lynxeyed_atsu	0:e8bfffbb3ab6	769	typedef struct /* Channel Registers */
lynxeyed_atsu	0:e8bfffbb3ab6	770	{
lynxeyed_atsu	0:e8bfffbb3ab6	771	__IO uint32_t DMACCSrcAddr;
lynxeyed_atsu	0:e8bfffbb3ab6	772	__IO uint32_t DMACCDestAddr;
lynxeyed_atsu	0:e8bfffbb3ab6	773	__IO uint32_t DMACCLLI;
lynxeyed_atsu	0:e8bfffbb3ab6	774	__IO uint32_t DMACCControl;
lynxeyed_atsu	0:e8bfffbb3ab6	775	__IO uint32_t DMACCConfig;
lynxeyed_atsu	0:e8bfffbb3ab6	776	} LPC_GPDMACH_TypeDef;
lynxeyed_atsu	0:e8bfffbb3ab6	777
lynxeyed_atsu	0:e8bfffbb3ab6	778	/------------- Universal Serial Bus (USB) -----------------------------------/
lynxeyed_atsu	0:e8bfffbb3ab6	779	/** @brief Universal Serial Bus (USB) register structure definition */
lynxeyed_atsu	0:e8bfffbb3ab6	780	typedef struct
lynxeyed_atsu	0:e8bfffbb3ab6	781	{
lynxeyed_atsu	0:e8bfffbb3ab6	782	__I uint32_t HcRevision; /* USB Host Registers */
lynxeyed_atsu	0:e8bfffbb3ab6	783	__IO uint32_t HcControl;
lynxeyed_atsu	0:e8bfffbb3ab6	784	__IO uint32_t HcCommandStatus;
lynxeyed_atsu	0:e8bfffbb3ab6	785	__IO uint32_t HcInterruptStatus;
lynxeyed_atsu	0:e8bfffbb3ab6	786	__IO uint32_t HcInterruptEnable;
lynxeyed_atsu	0:e8bfffbb3ab6	787	__IO uint32_t HcInterruptDisable;
lynxeyed_atsu	0:e8bfffbb3ab6	788	__IO uint32_t HcHCCA;
lynxeyed_atsu	0:e8bfffbb3ab6	789	__I uint32_t HcPeriodCurrentED;
lynxeyed_atsu	0:e8bfffbb3ab6	790	__IO uint32_t HcControlHeadED;
lynxeyed_atsu	0:e8bfffbb3ab6	791	__IO uint32_t HcControlCurrentED;
lynxeyed_atsu	0:e8bfffbb3ab6	792	__IO uint32_t HcBulkHeadED;
lynxeyed_atsu	0:e8bfffbb3ab6	793	__IO uint32_t HcBulkCurrentED;
lynxeyed_atsu	0:e8bfffbb3ab6	794	__I uint32_t HcDoneHead;
lynxeyed_atsu	0:e8bfffbb3ab6	795	__IO uint32_t HcFmInterval;
lynxeyed_atsu	0:e8bfffbb3ab6	796	__I uint32_t HcFmRemaining;
lynxeyed_atsu	0:e8bfffbb3ab6	797	__I uint32_t HcFmNumber;
lynxeyed_atsu	0:e8bfffbb3ab6	798	__IO uint32_t HcPeriodicStart;
lynxeyed_atsu	0:e8bfffbb3ab6	799	__IO uint32_t HcLSTreshold;
lynxeyed_atsu	0:e8bfffbb3ab6	800	__IO uint32_t HcRhDescriptorA;
lynxeyed_atsu	0:e8bfffbb3ab6	801	__IO uint32_t HcRhDescriptorB;
lynxeyed_atsu	0:e8bfffbb3ab6	802	__IO uint32_t HcRhStatus;
lynxeyed_atsu	0:e8bfffbb3ab6	803	__IO uint32_t HcRhPortStatus1;
lynxeyed_atsu	0:e8bfffbb3ab6	804	__IO uint32_t HcRhPortStatus2;
lynxeyed_atsu	0:e8bfffbb3ab6	805	uint32_t RESERVED0[40];
lynxeyed_atsu	0:e8bfffbb3ab6	806	__I uint32_t Module_ID;
lynxeyed_atsu	0:e8bfffbb3ab6	807
lynxeyed_atsu	0:e8bfffbb3ab6	808	__I uint32_t OTGIntSt; /* USB On-The-Go Registers */
lynxeyed_atsu	0:e8bfffbb3ab6	809	__IO uint32_t OTGIntEn;
lynxeyed_atsu	0:e8bfffbb3ab6	810	__O uint32_t OTGIntSet;
lynxeyed_atsu	0:e8bfffbb3ab6	811	__O uint32_t OTGIntClr;
lynxeyed_atsu	0:e8bfffbb3ab6	812	__IO uint32_t OTGStCtrl;
lynxeyed_atsu	0:e8bfffbb3ab6	813	__IO uint32_t OTGTmr;
lynxeyed_atsu	0:e8bfffbb3ab6	814	uint32_t RESERVED1[58];
lynxeyed_atsu	0:e8bfffbb3ab6	815
lynxeyed_atsu	0:e8bfffbb3ab6	816	__I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
lynxeyed_atsu	0:e8bfffbb3ab6	817	__IO uint32_t USBDevIntEn;
lynxeyed_atsu	0:e8bfffbb3ab6	818	__O uint32_t USBDevIntClr;
lynxeyed_atsu	0:e8bfffbb3ab6	819	__O uint32_t USBDevIntSet;
lynxeyed_atsu	0:e8bfffbb3ab6	820
lynxeyed_atsu	0:e8bfffbb3ab6	821	__O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
lynxeyed_atsu	0:e8bfffbb3ab6	822	__I uint32_t USBCmdData;
lynxeyed_atsu	0:e8bfffbb3ab6	823
lynxeyed_atsu	0:e8bfffbb3ab6	824	__I uint32_t USBRxData; /* USB Device Transfer Registers */
lynxeyed_atsu	0:e8bfffbb3ab6	825	__O uint32_t USBTxData;
lynxeyed_atsu	0:e8bfffbb3ab6	826	__I uint32_t USBRxPLen;
lynxeyed_atsu	0:e8bfffbb3ab6	827	__O uint32_t USBTxPLen;
lynxeyed_atsu	0:e8bfffbb3ab6	828	__IO uint32_t USBCtrl;
lynxeyed_atsu	0:e8bfffbb3ab6	829	__O uint32_t USBDevIntPri;
lynxeyed_atsu	0:e8bfffbb3ab6	830
lynxeyed_atsu	0:e8bfffbb3ab6	831	__I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
lynxeyed_atsu	0:e8bfffbb3ab6	832	__IO uint32_t USBEpIntEn;
lynxeyed_atsu	0:e8bfffbb3ab6	833	__O uint32_t USBEpIntClr;
lynxeyed_atsu	0:e8bfffbb3ab6	834	__O uint32_t USBEpIntSet;
lynxeyed_atsu	0:e8bfffbb3ab6	835	__O uint32_t USBEpIntPri;
lynxeyed_atsu	0:e8bfffbb3ab6	836
lynxeyed_atsu	0:e8bfffbb3ab6	837	__IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
lynxeyed_atsu	0:e8bfffbb3ab6	838	__O uint32_t USBEpInd;
lynxeyed_atsu	0:e8bfffbb3ab6	839	__IO uint32_t USBMaxPSize;
lynxeyed_atsu	0:e8bfffbb3ab6	840
lynxeyed_atsu	0:e8bfffbb3ab6	841	__I uint32_t USBDMARSt; /* USB Device DMA Registers */
lynxeyed_atsu	0:e8bfffbb3ab6	842	__O uint32_t USBDMARClr;
lynxeyed_atsu	0:e8bfffbb3ab6	843	__O uint32_t USBDMARSet;
lynxeyed_atsu	0:e8bfffbb3ab6	844	uint32_t RESERVED2[9];
lynxeyed_atsu	0:e8bfffbb3ab6	845	__IO uint32_t USBUDCAH;
lynxeyed_atsu	0:e8bfffbb3ab6	846	__I uint32_t USBEpDMASt;
lynxeyed_atsu	0:e8bfffbb3ab6	847	__O uint32_t USBEpDMAEn;
lynxeyed_atsu	0:e8bfffbb3ab6	848	__O uint32_t USBEpDMADis;
lynxeyed_atsu	0:e8bfffbb3ab6	849	__I uint32_t USBDMAIntSt;
lynxeyed_atsu	0:e8bfffbb3ab6	850	__IO uint32_t USBDMAIntEn;
lynxeyed_atsu	0:e8bfffbb3ab6	851	uint32_t RESERVED3[2];
lynxeyed_atsu	0:e8bfffbb3ab6	852	__I uint32_t USBEoTIntSt;
lynxeyed_atsu	0:e8bfffbb3ab6	853	__O uint32_t USBEoTIntClr;
lynxeyed_atsu	0:e8bfffbb3ab6	854	__O uint32_t USBEoTIntSet;
lynxeyed_atsu	0:e8bfffbb3ab6	855	__I uint32_t USBNDDRIntSt;
lynxeyed_atsu	0:e8bfffbb3ab6	856	__O uint32_t USBNDDRIntClr;
lynxeyed_atsu	0:e8bfffbb3ab6	857	__O uint32_t USBNDDRIntSet;
lynxeyed_atsu	0:e8bfffbb3ab6	858	__I uint32_t USBSysErrIntSt;
lynxeyed_atsu	0:e8bfffbb3ab6	859	__O uint32_t USBSysErrIntClr;
lynxeyed_atsu	0:e8bfffbb3ab6	860	__O uint32_t USBSysErrIntSet;
lynxeyed_atsu	0:e8bfffbb3ab6	861	uint32_t RESERVED4[15];
lynxeyed_atsu	0:e8bfffbb3ab6	862
lynxeyed_atsu	0:e8bfffbb3ab6	863	union {
lynxeyed_atsu	0:e8bfffbb3ab6	864	__I uint32_t I2C_RX; /* USB OTG I2C Registers */
lynxeyed_atsu	0:e8bfffbb3ab6	865	__O uint32_t I2C_TX;
lynxeyed_atsu	0:e8bfffbb3ab6	866	};
lynxeyed_atsu	0:e8bfffbb3ab6	867	__I uint32_t I2C_STS;
lynxeyed_atsu	0:e8bfffbb3ab6	868	__IO uint32_t I2C_CTL;
lynxeyed_atsu	0:e8bfffbb3ab6	869	__IO uint32_t I2C_CLKHI;
lynxeyed_atsu	0:e8bfffbb3ab6	870	__O uint32_t I2C_CLKLO;
lynxeyed_atsu	0:e8bfffbb3ab6	871	uint32_t RESERVED5[824];
lynxeyed_atsu	0:e8bfffbb3ab6	872
lynxeyed_atsu	0:e8bfffbb3ab6	873	union {
lynxeyed_atsu	0:e8bfffbb3ab6	874	__IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
lynxeyed_atsu	0:e8bfffbb3ab6	875	__IO uint32_t OTGClkCtrl;
lynxeyed_atsu	0:e8bfffbb3ab6	876	};
lynxeyed_atsu	0:e8bfffbb3ab6	877	union {
lynxeyed_atsu	0:e8bfffbb3ab6	878	__I uint32_t USBClkSt;
lynxeyed_atsu	0:e8bfffbb3ab6	879	__I uint32_t OTGClkSt;
lynxeyed_atsu	0:e8bfffbb3ab6	880	};
lynxeyed_atsu	0:e8bfffbb3ab6	881	} LPC_USB_TypeDef;
lynxeyed_atsu	0:e8bfffbb3ab6	882
lynxeyed_atsu	0:e8bfffbb3ab6	883	/------------- Ethernet Media Access Controller (EMAC) ----------------------/
lynxeyed_atsu	0:e8bfffbb3ab6	884	/** @brief Ethernet Media Access Controller (EMAC) register structure definition */
lynxeyed_atsu	0:e8bfffbb3ab6	885	typedef struct
lynxeyed_atsu	0:e8bfffbb3ab6	886	{
lynxeyed_atsu	0:e8bfffbb3ab6	887	__IO uint32_t MAC1; /* MAC Registers */
lynxeyed_atsu	0:e8bfffbb3ab6	888	__IO uint32_t MAC2;
lynxeyed_atsu	0:e8bfffbb3ab6	889	__IO uint32_t IPGT;
lynxeyed_atsu	0:e8bfffbb3ab6	890	__IO uint32_t IPGR;
lynxeyed_atsu	0:e8bfffbb3ab6	891	__IO uint32_t CLRT;
lynxeyed_atsu	0:e8bfffbb3ab6	892	__IO uint32_t MAXF;
lynxeyed_atsu	0:e8bfffbb3ab6	893	__IO uint32_t SUPP;
lynxeyed_atsu	0:e8bfffbb3ab6	894	__IO uint32_t TEST;
lynxeyed_atsu	0:e8bfffbb3ab6	895	__IO uint32_t MCFG;
lynxeyed_atsu	0:e8bfffbb3ab6	896	__IO uint32_t MCMD;
lynxeyed_atsu	0:e8bfffbb3ab6	897	__IO uint32_t MADR;
lynxeyed_atsu	0:e8bfffbb3ab6	898	__O uint32_t MWTD;
lynxeyed_atsu	0:e8bfffbb3ab6	899	__I uint32_t MRDD;
lynxeyed_atsu	0:e8bfffbb3ab6	900	__I uint32_t MIND;
lynxeyed_atsu	0:e8bfffbb3ab6	901	uint32_t RESERVED0[2];
lynxeyed_atsu	0:e8bfffbb3ab6	902	__IO uint32_t SA0;
lynxeyed_atsu	0:e8bfffbb3ab6	903	__IO uint32_t SA1;
lynxeyed_atsu	0:e8bfffbb3ab6	904	__IO uint32_t SA2;
lynxeyed_atsu	0:e8bfffbb3ab6	905	uint32_t RESERVED1[45];
lynxeyed_atsu	0:e8bfffbb3ab6	906	__IO uint32_t Command; /* Control Registers */
lynxeyed_atsu	0:e8bfffbb3ab6	907	__I uint32_t Status;
lynxeyed_atsu	0:e8bfffbb3ab6	908	__IO uint32_t RxDescriptor;
lynxeyed_atsu	0:e8bfffbb3ab6	909	__IO uint32_t RxStatus;
lynxeyed_atsu	0:e8bfffbb3ab6	910	__IO uint32_t RxDescriptorNumber;
lynxeyed_atsu	0:e8bfffbb3ab6	911	__I uint32_t RxProduceIndex;
lynxeyed_atsu	0:e8bfffbb3ab6	912	__IO uint32_t RxConsumeIndex;
lynxeyed_atsu	0:e8bfffbb3ab6	913	__IO uint32_t TxDescriptor;
lynxeyed_atsu	0:e8bfffbb3ab6	914	__IO uint32_t TxStatus;
lynxeyed_atsu	0:e8bfffbb3ab6	915	__IO uint32_t TxDescriptorNumber;
lynxeyed_atsu	0:e8bfffbb3ab6	916	__IO uint32_t TxProduceIndex;
lynxeyed_atsu	0:e8bfffbb3ab6	917	__I uint32_t TxConsumeIndex;
lynxeyed_atsu	0:e8bfffbb3ab6	918	uint32_t RESERVED2[10];
lynxeyed_atsu	0:e8bfffbb3ab6	919	__I uint32_t TSV0;
lynxeyed_atsu	0:e8bfffbb3ab6	920	__I uint32_t TSV1;
lynxeyed_atsu	0:e8bfffbb3ab6	921	__I uint32_t RSV;
lynxeyed_atsu	0:e8bfffbb3ab6	922	uint32_t RESERVED3[3];
lynxeyed_atsu	0:e8bfffbb3ab6	923	__IO uint32_t FlowControlCounter;
lynxeyed_atsu	0:e8bfffbb3ab6	924	__I uint32_t FlowControlStatus;
lynxeyed_atsu	0:e8bfffbb3ab6	925	uint32_t RESERVED4[34];
lynxeyed_atsu	0:e8bfffbb3ab6	926	__IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
lynxeyed_atsu	0:e8bfffbb3ab6	927	__IO uint32_t RxFilterWoLStatus;
lynxeyed_atsu	0:e8bfffbb3ab6	928	__IO uint32_t RxFilterWoLClear;
lynxeyed_atsu	0:e8bfffbb3ab6	929	uint32_t RESERVED5;
lynxeyed_atsu	0:e8bfffbb3ab6	930	__IO uint32_t HashFilterL;
lynxeyed_atsu	0:e8bfffbb3ab6	931	__IO uint32_t HashFilterH;
lynxeyed_atsu	0:e8bfffbb3ab6	932	uint32_t RESERVED6[882];
lynxeyed_atsu	0:e8bfffbb3ab6	933	__I uint32_t IntStatus; /* Module Control Registers */
lynxeyed_atsu	0:e8bfffbb3ab6	934	__IO uint32_t IntEnable;
lynxeyed_atsu	0:e8bfffbb3ab6	935	__O uint32_t IntClear;
lynxeyed_atsu	0:e8bfffbb3ab6	936	__O uint32_t IntSet;
lynxeyed_atsu	0:e8bfffbb3ab6	937	uint32_t RESERVED7;
lynxeyed_atsu	0:e8bfffbb3ab6	938	__IO uint32_t PowerDown;
lynxeyed_atsu	0:e8bfffbb3ab6	939	uint32_t RESERVED8;
lynxeyed_atsu	0:e8bfffbb3ab6	940	__IO uint32_t Module_ID;
lynxeyed_atsu	0:e8bfffbb3ab6	941	} LPC_EMAC_TypeDef;
lynxeyed_atsu	0:e8bfffbb3ab6	942
lynxeyed_atsu	0:e8bfffbb3ab6	943
lynxeyed_atsu	0:e8bfffbb3ab6	944	#if defined ( __CC_ARM )
lynxeyed_atsu	0:e8bfffbb3ab6	945	#pragma no_anon_unions
lynxeyed_atsu	0:e8bfffbb3ab6	946	#endif
lynxeyed_atsu	0:e8bfffbb3ab6	947
lynxeyed_atsu	0:e8bfffbb3ab6	948
lynxeyed_atsu	0:e8bfffbb3ab6	949	/******************************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	950	/* Peripheral memory map */
lynxeyed_atsu	0:e8bfffbb3ab6	951	/******************************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	952	/* Base addresses */
lynxeyed_atsu	0:e8bfffbb3ab6	953	#define LPC_FLASH_BASE (0x00000000UL)
lynxeyed_atsu	0:e8bfffbb3ab6	954	#define LPC_RAM_BASE (0x10000000UL)
lynxeyed_atsu	0:e8bfffbb3ab6	955	#ifdef __LPC17XX_REV00
lynxeyed_atsu	0:e8bfffbb3ab6	956	#define LPC_AHBRAM0_BASE (0x20000000UL)
lynxeyed_atsu	0:e8bfffbb3ab6	957	#define LPC_AHBRAM1_BASE (0x20004000UL)
lynxeyed_atsu	0:e8bfffbb3ab6	958	#else
lynxeyed_atsu	0:e8bfffbb3ab6	959	#define LPC_AHBRAM0_BASE (0x2007C000UL)
lynxeyed_atsu	0:e8bfffbb3ab6	960	#define LPC_AHBRAM1_BASE (0x20080000UL)
lynxeyed_atsu	0:e8bfffbb3ab6	961	#endif
lynxeyed_atsu	0:e8bfffbb3ab6	962	#define LPC_GPIO_BASE (0x2009C000UL)
lynxeyed_atsu	0:e8bfffbb3ab6	963	#define LPC_APB0_BASE (0x40000000UL)
lynxeyed_atsu	0:e8bfffbb3ab6	964	#define LPC_APB1_BASE (0x40080000UL)
lynxeyed_atsu	0:e8bfffbb3ab6	965	#define LPC_AHB_BASE (0x50000000UL)
lynxeyed_atsu	0:e8bfffbb3ab6	966	#define LPC_CM3_BASE (0xE0000000UL)
lynxeyed_atsu	0:e8bfffbb3ab6	967
lynxeyed_atsu	0:e8bfffbb3ab6	968	/* APB0 peripherals */
lynxeyed_atsu	0:e8bfffbb3ab6	969	#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
lynxeyed_atsu	0:e8bfffbb3ab6	970	#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
lynxeyed_atsu	0:e8bfffbb3ab6	971	#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
lynxeyed_atsu	0:e8bfffbb3ab6	972	#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
lynxeyed_atsu	0:e8bfffbb3ab6	973	#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
lynxeyed_atsu	0:e8bfffbb3ab6	974	#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
lynxeyed_atsu	0:e8bfffbb3ab6	975	#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
lynxeyed_atsu	0:e8bfffbb3ab6	976	#define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
lynxeyed_atsu	0:e8bfffbb3ab6	977	#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
lynxeyed_atsu	0:e8bfffbb3ab6	978	#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
lynxeyed_atsu	0:e8bfffbb3ab6	979	#define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
lynxeyed_atsu	0:e8bfffbb3ab6	980	#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
lynxeyed_atsu	0:e8bfffbb3ab6	981	#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
lynxeyed_atsu	0:e8bfffbb3ab6	982	#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
lynxeyed_atsu	0:e8bfffbb3ab6	983	#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
lynxeyed_atsu	0:e8bfffbb3ab6	984	#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
lynxeyed_atsu	0:e8bfffbb3ab6	985	#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
lynxeyed_atsu	0:e8bfffbb3ab6	986	#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
lynxeyed_atsu	0:e8bfffbb3ab6	987	#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
lynxeyed_atsu	0:e8bfffbb3ab6	988
lynxeyed_atsu	0:e8bfffbb3ab6	989	/* APB1 peripherals */
lynxeyed_atsu	0:e8bfffbb3ab6	990	#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
lynxeyed_atsu	0:e8bfffbb3ab6	991	#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
lynxeyed_atsu	0:e8bfffbb3ab6	992	#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
lynxeyed_atsu	0:e8bfffbb3ab6	993	#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
lynxeyed_atsu	0:e8bfffbb3ab6	994	#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
lynxeyed_atsu	0:e8bfffbb3ab6	995	#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
lynxeyed_atsu	0:e8bfffbb3ab6	996	#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
lynxeyed_atsu	0:e8bfffbb3ab6	997	#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
lynxeyed_atsu	0:e8bfffbb3ab6	998	#define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
lynxeyed_atsu	0:e8bfffbb3ab6	999	#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
lynxeyed_atsu	0:e8bfffbb3ab6	1000	#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
lynxeyed_atsu	0:e8bfffbb3ab6	1001	#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
lynxeyed_atsu	0:e8bfffbb3ab6	1002
lynxeyed_atsu	0:e8bfffbb3ab6	1003	/* AHB peripherals */
lynxeyed_atsu	0:e8bfffbb3ab6	1004	#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
lynxeyed_atsu	0:e8bfffbb3ab6	1005	#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
lynxeyed_atsu	0:e8bfffbb3ab6	1006	#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
lynxeyed_atsu	0:e8bfffbb3ab6	1007	#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
lynxeyed_atsu	0:e8bfffbb3ab6	1008	#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
lynxeyed_atsu	0:e8bfffbb3ab6	1009	#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
lynxeyed_atsu	0:e8bfffbb3ab6	1010	#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
lynxeyed_atsu	0:e8bfffbb3ab6	1011	#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
lynxeyed_atsu	0:e8bfffbb3ab6	1012	#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
lynxeyed_atsu	0:e8bfffbb3ab6	1013	#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
lynxeyed_atsu	0:e8bfffbb3ab6	1014	#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
lynxeyed_atsu	0:e8bfffbb3ab6	1015
lynxeyed_atsu	0:e8bfffbb3ab6	1016	/* GPIOs */
lynxeyed_atsu	0:e8bfffbb3ab6	1017	#define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
lynxeyed_atsu	0:e8bfffbb3ab6	1018	#define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
lynxeyed_atsu	0:e8bfffbb3ab6	1019	#define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
lynxeyed_atsu	0:e8bfffbb3ab6	1020	#define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
lynxeyed_atsu	0:e8bfffbb3ab6	1021	#define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
lynxeyed_atsu	0:e8bfffbb3ab6	1022
lynxeyed_atsu	0:e8bfffbb3ab6	1023	/******************************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	1024	/* Peripheral declaration */
lynxeyed_atsu	0:e8bfffbb3ab6	1025	/******************************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	1026	#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1027	#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1028	#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1029	#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1030	#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1031	#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1032	#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1033	#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1034	#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1035	#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1036	#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1037	#define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1038	#define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1039	#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1040	#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1041	#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1042	#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1043	#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1044	#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1045	#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1046	#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1047	#define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1048	#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1049	#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1050	#define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1051	#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1052	#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1053	#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1054	#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1055	#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
lynxeyed_atsu	0:e8bfffbb3ab6	1056	#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1057	#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1058	#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1059	#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1060	#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1061	#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1062	#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1063	#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1064	#define DMAREQSEL ((__IO uint32_t ) ( 0x4000C1C4))
lynxeyed_atsu	0:e8bfffbb3ab6	1065	#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1066	#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1067	#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1068	#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1069	#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1070	#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1071	#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1072	#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1073	#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
lynxeyed_atsu	0:e8bfffbb3ab6	1074
lynxeyed_atsu	0:e8bfffbb3ab6	1075	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1076	* @}
lynxeyed_atsu	0:e8bfffbb3ab6	1077	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1078
lynxeyed_atsu	0:e8bfffbb3ab6	1079	#endif // __LPC17xx_H__

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	26 Feb 2011
Imports:	12
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	1

I2S_Example/LPC17xx.h@0:e8bfffbb3ab6, 2011-02-26 (annotated)

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