long dao / mbed-src

Mbed for VNG board

Fork of mbed-src by mbed official

targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c@430:d406b7919023, 2014-12-09 (annotated)

Committer:
mbed_official
Date:
Tue Dec 09 14:30:09 2014 +0000
Revision:
430:d406b7919023
Parent:
427:8eeb5157dee4 
Synchronized with git revision 0f2b2cdf092ac0325f6003d3e903308446f2da6f



Full URL: https://github.com/mbedmicro/mbed/commit/0f2b2cdf092ac0325f6003d3e903308446f2da6f/



Targets: RZ_A1H - Fix some bugs about I2C, SPI, Interruptin and add terminal definition of user button.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 390:35c2c1cf29cd 1 /* mbed Microcontroller Library
mbed_official 390:35c2c1cf29cd 2 * Copyright (c) 2006-2013 ARM Limited
mbed_official 390:35c2c1cf29cd 3 *
mbed_official 390:35c2c1cf29cd 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 390:35c2c1cf29cd 5 * you may not use this file except in compliance with the License.
mbed_official 390:35c2c1cf29cd 6 * You may obtain a copy of the License at
mbed_official 390:35c2c1cf29cd 7 *
mbed_official 390:35c2c1cf29cd 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 390:35c2c1cf29cd 9 *
mbed_official 390:35c2c1cf29cd 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 390:35c2c1cf29cd 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 390:35c2c1cf29cd 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 390:35c2c1cf29cd 13 * See the License for the specific language governing permissions and
mbed_official 390:35c2c1cf29cd 14 * limitations under the License.
mbed_official 390:35c2c1cf29cd 15 */
mbed_official 390:35c2c1cf29cd 16 #include "mbed_assert.h"
mbed_official 390:35c2c1cf29cd 17 #include "i2c_api.h"
mbed_official 390:35c2c1cf29cd 18 #include "cmsis.h"
mbed_official 390:35c2c1cf29cd 19 #include "pinmap.h"
mbed_official 390:35c2c1cf29cd 20
mbed_official 390:35c2c1cf29cd 21
mbed_official 390:35c2c1cf29cd 22 #include "riic_iodefine.h"
mbed_official 422:a032ac66f24e 23 #include "RZ_A1_Init.h"
mbed_official 422:a032ac66f24e 24 #include "MBRZA1H.h"
mbed_official 390:35c2c1cf29cd 25
mbed_official 390:35c2c1cf29cd 26 volatile struct st_riic *RIIC[] = RIIC_ADDRESS_LIST;
mbed_official 390:35c2c1cf29cd 27
mbed_official 390:35c2c1cf29cd 28 #define REG(N) \
mbed_official 390:35c2c1cf29cd 29 RIIC[obj->i2c]->RIICn##N
mbed_official 390:35c2c1cf29cd 30
mbed_official 390:35c2c1cf29cd 31 #define NACKF (1 << 4)
mbed_official 390:35c2c1cf29cd 32
mbed_official 390:35c2c1cf29cd 33 static const PinMap PinMap_I2C_SDA[] = {
mbed_official 390:35c2c1cf29cd 34 {P1_1 , I2C_0, 1},
mbed_official 390:35c2c1cf29cd 35 {P1_3 , I2C_1, 1},
mbed_official 390:35c2c1cf29cd 36 {P1_7 , I2C_3, 1},
mbed_official 390:35c2c1cf29cd 37 {NC , NC , 0}
mbed_official 390:35c2c1cf29cd 38 };
mbed_official 390:35c2c1cf29cd 39
mbed_official 390:35c2c1cf29cd 40 static const PinMap PinMap_I2C_SCL[] = {
mbed_official 390:35c2c1cf29cd 41 {P1_0 , I2C_0, 1},
mbed_official 390:35c2c1cf29cd 42 {P1_2 , I2C_1, 1},
mbed_official 390:35c2c1cf29cd 43 {P1_6 , I2C_3, 1},
mbed_official 390:35c2c1cf29cd 44 {NC , NC, 0}
mbed_official 390:35c2c1cf29cd 45 };
mbed_official 390:35c2c1cf29cd 46
mbed_official 390:35c2c1cf29cd 47 // Clear the Transmit data Empty TDRE
mbed_official 390:35c2c1cf29cd 48 static inline int i2c_addressed(i2c_t *obj) {
mbed_official 390:35c2c1cf29cd 49 volatile int sar0 = (REG(SR1.UINT8[0])&1),
mbed_official 390:35c2c1cf29cd 50 trs = (REG(CR2.UINT8[0])&0x20) >> 5;
mbed_official 390:35c2c1cf29cd 51 return sar0 | (trs <<1);
mbed_official 390:35c2c1cf29cd 52 }
mbed_official 390:35c2c1cf29cd 53
mbed_official 390:35c2c1cf29cd 54 static inline int i2c_status(i2c_t *obj) {
mbed_official 390:35c2c1cf29cd 55 return REG(SR2.UINT8[0]);
mbed_official 390:35c2c1cf29cd 56 }
mbed_official 390:35c2c1cf29cd 57
mbed_official 390:35c2c1cf29cd 58 static inline void i2c_clear_TDRE(i2c_t *obj) {
mbed_official 390:35c2c1cf29cd 59 REG(SR2.UINT32) &= ~(1 << 7);
mbed_official 390:35c2c1cf29cd 60 }
mbed_official 390:35c2c1cf29cd 61
mbed_official 390:35c2c1cf29cd 62 static inline void i2c_wait_RDRF(i2c_t *obj) {
mbed_official 390:35c2c1cf29cd 63 while (!(i2c_status(obj) & (1 << 5))) ;
mbed_official 390:35c2c1cf29cd 64 }
mbed_official 390:35c2c1cf29cd 65
mbed_official 409:a95c696104d3 66 static void i2c_reg_reset(i2c_t *obj) {
mbed_official 409:a95c696104d3 67 // full reset
mbed_official 409:a95c696104d3 68 REG(CR1.UINT8[0]) &= ~(1 << 7); // CR1.ICE off
mbed_official 409:a95c696104d3 69 REG(CR1.UINT8[0]) |= (1 << 6); // CR1.IICRST on
mbed_official 409:a95c696104d3 70 REG(CR1.UINT8[0]) |= (1 << 7); // CR1.ICE on
mbed_official 409:a95c696104d3 71
mbed_official 409:a95c696104d3 72 REG(MR1.UINT8[0]) = 0x08; // P_phi /8 9bit (including Ack)
mbed_official 409:a95c696104d3 73 REG(SER.UINT8[0]) = 0x00; // no slave addr enabled
mbed_official 409:a95c696104d3 74
mbed_official 427:8eeb5157dee4 75 // set frequency
mbed_official 427:8eeb5157dee4 76 REG(MR1.UINT8[0]) |= obj->pclk_bit;
mbed_official 427:8eeb5157dee4 77 REG(BRL.UINT32) = obj->width;
mbed_official 427:8eeb5157dee4 78 REG(BRH.UINT32) = obj->width;
mbed_official 409:a95c696104d3 79
mbed_official 409:a95c696104d3 80 REG(MR2.UINT8[0]) = 0x07;
mbed_official 409:a95c696104d3 81 REG(MR3.UINT8[0]) = 0x00;
mbed_official 409:a95c696104d3 82
mbed_official 409:a95c696104d3 83 REG(FER.UINT8[0]) = 0x72; // SCLE, NFE enabled, TMOT
mbed_official 409:a95c696104d3 84 REG(IER.UINT8[0]) = 0x00; // no interrupt
mbed_official 409:a95c696104d3 85
mbed_official 409:a95c696104d3 86 REG(CR1.UINT32) &= ~(1 << 6); // CR1.IICRST negate reset
mbed_official 409:a95c696104d3 87 }
mbed_official 409:a95c696104d3 88
mbed_official 390:35c2c1cf29cd 89 // Wait until the Trans Data Empty (TDRE) is set
mbed_official 390:35c2c1cf29cd 90 static int i2c_wait_TDRE(i2c_t *obj) {
mbed_official 390:35c2c1cf29cd 91 int timeout = 0;
mbed_official 390:35c2c1cf29cd 92
mbed_official 390:35c2c1cf29cd 93 while (!(i2c_status(obj) & (1 << 7))) {
mbed_official 409:a95c696104d3 94 timeout ++;
mbed_official 390:35c2c1cf29cd 95 if (timeout > 100000) return -1;
mbed_official 390:35c2c1cf29cd 96 }
mbed_official 390:35c2c1cf29cd 97
mbed_official 390:35c2c1cf29cd 98 return 0;
mbed_official 390:35c2c1cf29cd 99 }
mbed_official 390:35c2c1cf29cd 100
mbed_official 409:a95c696104d3 101 static inline int i2c_wait_TEND(i2c_t *obj) {
mbed_official 409:a95c696104d3 102 int timeout = 0;
mbed_official 409:a95c696104d3 103
mbed_official 409:a95c696104d3 104 while (!(i2c_status(obj) & (1 << 6))) {
mbed_official 409:a95c696104d3 105 timeout ++;
mbed_official 409:a95c696104d3 106 if (timeout > 100000) return -1;
mbed_official 409:a95c696104d3 107 }
mbed_official 409:a95c696104d3 108
mbed_official 409:a95c696104d3 109 return 0;
mbed_official 409:a95c696104d3 110 }
mbed_official 409:a95c696104d3 111
mbed_official 409:a95c696104d3 112
mbed_official 430:d406b7919023 113 static int i2c_wait_STOP(i2c_t *obj) {
mbed_official 430:d406b7919023 114 volatile uint32_t work_reg;
mbed_official 430:d406b7919023 115
mbed_official 430:d406b7919023 116 /* wait SR2.STOP = 1 */
mbed_official 430:d406b7919023 117 work_reg = REG(SR2.UINT32);
mbed_official 430:d406b7919023 118 while ((work_reg & (1 << 3)) == 0) {
mbed_official 430:d406b7919023 119 work_reg = REG(SR2.UINT32);
mbed_official 430:d406b7919023 120 }
mbed_official 430:d406b7919023 121 /* SR2.NACKF = 0 */
mbed_official 430:d406b7919023 122 REG(SR2.UINT32) &= ~(1 << 4);
mbed_official 430:d406b7919023 123 /* SR2.STOP = 0 */
mbed_official 430:d406b7919023 124 REG(SR2.UINT32) &= ~(1 << 3);
mbed_official 430:d406b7919023 125
mbed_official 430:d406b7919023 126 return 0;
mbed_official 430:d406b7919023 127 }
mbed_official 430:d406b7919023 128
mbed_official 430:d406b7919023 129
mbed_official 390:35c2c1cf29cd 130 static inline void i2c_power_enable(i2c_t *obj) {
mbed_official 390:35c2c1cf29cd 131 volatile uint8_t dummy;
mbed_official 390:35c2c1cf29cd 132 switch ((int)obj->i2c) {
mbed_official 390:35c2c1cf29cd 133 case I2C_0: CPGSTBCR9 &= ~(0x80); break;
mbed_official 390:35c2c1cf29cd 134 case I2C_1: CPGSTBCR9 &= ~(0x40); break;
mbed_official 390:35c2c1cf29cd 135 case I2C_2: CPGSTBCR9 &= ~(0x20); break;
mbed_official 390:35c2c1cf29cd 136 case I2C_3: CPGSTBCR9 &= ~(0x10); break;
mbed_official 390:35c2c1cf29cd 137 }
mbed_official 390:35c2c1cf29cd 138 dummy = CPGSTBCR9;
mbed_official 390:35c2c1cf29cd 139 }
mbed_official 390:35c2c1cf29cd 140
mbed_official 390:35c2c1cf29cd 141 void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
mbed_official 390:35c2c1cf29cd 142 // determine the SPI to use
mbed_official 390:35c2c1cf29cd 143 I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
mbed_official 390:35c2c1cf29cd 144 I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
mbed_official 390:35c2c1cf29cd 145 obj->i2c = pinmap_merge(i2c_sda, i2c_scl);
mbed_official 390:35c2c1cf29cd 146 MBED_ASSERT((int)obj->i2c != NC);
mbed_official 409:a95c696104d3 147
mbed_official 390:35c2c1cf29cd 148 // enable power
mbed_official 390:35c2c1cf29cd 149 i2c_power_enable(obj);
mbed_official 390:35c2c1cf29cd 150
mbed_official 427:8eeb5157dee4 151 // set default frequency at 100k
mbed_official 427:8eeb5157dee4 152 i2c_frequency(obj, 100000);
mbed_official 427:8eeb5157dee4 153
mbed_official 409:a95c696104d3 154 // full reset
mbed_official 409:a95c696104d3 155 i2c_reg_reset(obj);
mbed_official 390:35c2c1cf29cd 156
mbed_official 390:35c2c1cf29cd 157 pinmap_pinout(sda, PinMap_I2C_SDA);
mbed_official 390:35c2c1cf29cd 158 pinmap_pinout(scl, PinMap_I2C_SCL);
mbed_official 390:35c2c1cf29cd 159 }
mbed_official 390:35c2c1cf29cd 160
mbed_official 390:35c2c1cf29cd 161 inline int i2c_start(i2c_t *obj) {
mbed_official 390:35c2c1cf29cd 162 if (REG(CR2.UINT32) & (1 << 7)) { // BBSY check
mbed_official 390:35c2c1cf29cd 163 return 0xff;
mbed_official 390:35c2c1cf29cd 164 }
mbed_official 430:d406b7919023 165 REG(CR2.UINT8[0]) |= 0x02; // start
mbed_official 390:35c2c1cf29cd 166
mbed_official 390:35c2c1cf29cd 167 return 0x10;
mbed_official 390:35c2c1cf29cd 168 }
mbed_official 390:35c2c1cf29cd 169
mbed_official 390:35c2c1cf29cd 170 inline int i2c_stop(i2c_t *obj) {
mbed_official 430:d406b7919023 171 /* SR2.STOP = 0 */
mbed_official 430:d406b7919023 172 REG(SR2.UINT32) &= ~(1 << 3);
mbed_official 390:35c2c1cf29cd 173 // write the stop bit
mbed_official 390:35c2c1cf29cd 174 REG(CR2.UINT32) |= (1 << 3);
mbed_official 409:a95c696104d3 175
mbed_official 390:35c2c1cf29cd 176 return 0;
mbed_official 390:35c2c1cf29cd 177 }
mbed_official 390:35c2c1cf29cd 178
mbed_official 390:35c2c1cf29cd 179 static inline int i2c_do_write(i2c_t *obj, int value) {
mbed_official 390:35c2c1cf29cd 180 // write the data
mbed_official 390:35c2c1cf29cd 181 if (!(i2c_status(obj) & NACKF)) { // NACF=0
mbed_official 390:35c2c1cf29cd 182 i2c_wait_TDRE(obj);
mbed_official 390:35c2c1cf29cd 183 REG(DRT.UINT32) = value;
mbed_official 390:35c2c1cf29cd 184 } else {
mbed_official 390:35c2c1cf29cd 185 return 0xff;
mbed_official 390:35c2c1cf29cd 186 }
mbed_official 390:35c2c1cf29cd 187 return i2c_status(obj);
mbed_official 390:35c2c1cf29cd 188 }
mbed_official 390:35c2c1cf29cd 189
mbed_official 390:35c2c1cf29cd 190 static inline int i2c_do_read(i2c_t *obj, int last) {
mbed_official 390:35c2c1cf29cd 191 if (obj->dummy) {
mbed_official 390:35c2c1cf29cd 192 volatile int dummy = REG(DRR.UINT32);
mbed_official 390:35c2c1cf29cd 193 obj->dummy = 0;
mbed_official 390:35c2c1cf29cd 194 }
mbed_official 409:a95c696104d3 195
mbed_official 409:a95c696104d3 196 // wait for it to arrive
mbed_official 409:a95c696104d3 197 i2c_wait_RDRF(obj);
mbed_official 409:a95c696104d3 198
mbed_official 409:a95c696104d3 199 if (last == 2) {
mbed_official 409:a95c696104d3 200 /* this time is befor last byte read */
mbed_official 409:a95c696104d3 201 /* Set MR3 WATI bit is 1 */;
mbed_official 409:a95c696104d3 202 REG(MR3.UINT32) |= (1 << 6);
mbed_official 409:a95c696104d3 203 } else if (last == 1) {
mbed_official 390:35c2c1cf29cd 204 // send a NOT ACK
mbed_official 430:d406b7919023 205 REG(MR3.UINT32) |= (1 <<4);
mbed_official 409:a95c696104d3 206 REG(MR3.UINT32) |= (1 <<3);
mbed_official 430:d406b7919023 207 REG(MR3.UINT32) &= ~(1 <<4);
mbed_official 390:35c2c1cf29cd 208 } else {
mbed_official 390:35c2c1cf29cd 209 // send a ACK
mbed_official 430:d406b7919023 210 REG(MR3.UINT32) |= (1 <<4);
mbed_official 409:a95c696104d3 211 REG(MR3.UINT32) &= ~(1 <<3);
mbed_official 430:d406b7919023 212 REG(MR3.UINT32) &= ~(1 <<4);
mbed_official 390:35c2c1cf29cd 213 }
mbed_official 409:a95c696104d3 214
mbed_official 390:35c2c1cf29cd 215 // return the data
mbed_official 390:35c2c1cf29cd 216 return (REG(DRR.UINT32) & 0xFF);
mbed_official 390:35c2c1cf29cd 217 }
mbed_official 390:35c2c1cf29cd 218
mbed_official 390:35c2c1cf29cd 219 void i2c_frequency(i2c_t *obj, int hz) {
mbed_official 422:a032ac66f24e 220 int freq;
mbed_official 422:a032ac66f24e 221 int oldfreq = 0;
mbed_official 422:a032ac66f24e 222 int newfreq = 0;
mbed_official 422:a032ac66f24e 223 uint32_t pclk;
mbed_official 422:a032ac66f24e 224 uint32_t pclk_base;
mbed_official 422:a032ac66f24e 225 uint32_t tmp_width;
mbed_official 422:a032ac66f24e 226 uint32_t width = 0;
mbed_official 422:a032ac66f24e 227 uint8_t count;
mbed_official 422:a032ac66f24e 228 uint8_t pclk_bit = 0;
mbed_official 427:8eeb5157dee4 229
mbed_official 422:a032ac66f24e 230 /* set PCLK */
mbed_official 427:8eeb5157dee4 231 if (false == RZ_A1_IsClockMode0()) {
mbed_official 422:a032ac66f24e 232 pclk_base = (uint32_t)CM1_RENESAS_RZ_A1_P0_CLK;
mbed_official 422:a032ac66f24e 233 } else {
mbed_official 422:a032ac66f24e 234 pclk_base = (uint32_t)CM0_RENESAS_RZ_A1_P0_CLK;
mbed_official 422:a032ac66f24e 235 }
mbed_official 427:8eeb5157dee4 236
mbed_official 422:a032ac66f24e 237 /* Min 10kHz, Max 400kHz */
mbed_official 422:a032ac66f24e 238 if (hz < 10000) {
mbed_official 422:a032ac66f24e 239 freq = 10000;
mbed_official 422:a032ac66f24e 240 } else if (hz > 400000) {
mbed_official 422:a032ac66f24e 241 freq = 400000;
mbed_official 422:a032ac66f24e 242 } else {
mbed_official 422:a032ac66f24e 243 freq = hz;
mbed_official 422:a032ac66f24e 244 }
mbed_official 427:8eeb5157dee4 245
mbed_official 422:a032ac66f24e 246 for (count = 0; count < 7; count++) {
mbed_official 422:a032ac66f24e 247 // IIC phi = P0 phi / rate
mbed_official 422:a032ac66f24e 248 pclk = pclk_base / (2 << count);
mbed_official 422:a032ac66f24e 249 // In case of "CLE = 1, NFE = 1, CKS != 000( IIC phi < P0 phi ), nf = 1"
mbed_official 422:a032ac66f24e 250 // freq = 1 / {[( BRH + 2 + 1 ) + ( BRL + 2 + 1 )] / pclk }
mbed_official 422:a032ac66f24e 251 // BRH is regarded as same value with BRL
mbed_official 422:a032ac66f24e 252 // 2( BRH + 3 ) / pclk = 1 / freq
mbed_official 422:a032ac66f24e 253 tmp_width = ((pclk / freq) / 2) - 3;
mbed_official 422:a032ac66f24e 254 // Carry in a decimal point
mbed_official 422:a032ac66f24e 255 tmp_width += 1;
mbed_official 422:a032ac66f24e 256 if ((tmp_width >= 0x00000001) && (tmp_width <= 0x0000001F)) {
mbed_official 422:a032ac66f24e 257 // Calculate theoretical value, and Choose max value of them
mbed_official 422:a032ac66f24e 258 newfreq = pclk / (tmp_width + 3) / 2;
mbed_official 422:a032ac66f24e 259 if (newfreq >= oldfreq) {
mbed_official 422:a032ac66f24e 260 oldfreq = newfreq;
mbed_official 422:a032ac66f24e 261 width = tmp_width;
mbed_official 422:a032ac66f24e 262 pclk_bit = (uint8_t)(0x10 * (count + 1));
mbed_official 422:a032ac66f24e 263 }
mbed_official 422:a032ac66f24e 264 }
mbed_official 422:a032ac66f24e 265 }
mbed_official 409:a95c696104d3 266
mbed_official 422:a032ac66f24e 267 if (width != 0) {
mbed_official 422:a032ac66f24e 268 // I2C Rate
mbed_official 427:8eeb5157dee4 269 obj->pclk_bit = pclk_bit; // P_phi / xx
mbed_official 427:8eeb5157dee4 270 obj->width = (width | 0x000000E0);
mbed_official 422:a032ac66f24e 271 } else {
mbed_official 422:a032ac66f24e 272 // Default
mbed_official 427:8eeb5157dee4 273 obj->pclk_bit = 0x00; // P_phi / 1
mbed_official 427:8eeb5157dee4 274 obj->width = 0x000000FF;
mbed_official 422:a032ac66f24e 275 }
mbed_official 390:35c2c1cf29cd 276 }
mbed_official 390:35c2c1cf29cd 277
mbed_official 390:35c2c1cf29cd 278 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
mbed_official 409:a95c696104d3 279 int count = 0;
mbed_official 409:a95c696104d3 280 int status;
mbed_official 409:a95c696104d3 281 int value;
mbed_official 409:a95c696104d3 282 volatile uint32_t work_reg = 0;
mbed_official 409:a95c696104d3 283
mbed_official 409:a95c696104d3 284 // full reset
mbed_official 409:a95c696104d3 285 i2c_reg_reset(obj);
mbed_official 430:d406b7919023 286 obj->dummy = 1;
mbed_official 430:d406b7919023 287
mbed_official 390:35c2c1cf29cd 288 status = i2c_start(obj);
mbed_official 409:a95c696104d3 289
mbed_official 390:35c2c1cf29cd 290 if (status == 0xff) {
mbed_official 390:35c2c1cf29cd 291 i2c_stop(obj);
mbed_official 430:d406b7919023 292 i2c_wait_STOP(obj);
mbed_official 390:35c2c1cf29cd 293 return I2C_ERROR_BUS_BUSY;
mbed_official 390:35c2c1cf29cd 294 }
mbed_official 409:a95c696104d3 295
mbed_official 390:35c2c1cf29cd 296 status = i2c_do_write(obj, (address | 0x01));
mbed_official 390:35c2c1cf29cd 297 if (status & 0x01) {
mbed_official 390:35c2c1cf29cd 298 i2c_stop(obj);
mbed_official 430:d406b7919023 299 i2c_wait_STOP(obj);
mbed_official 390:35c2c1cf29cd 300 return I2C_ERROR_NO_SLAVE;
mbed_official 390:35c2c1cf29cd 301 }
mbed_official 409:a95c696104d3 302
mbed_official 409:a95c696104d3 303 /* wati RDRF */
mbed_official 409:a95c696104d3 304 i2c_wait_RDRF(obj);
mbed_official 409:a95c696104d3 305 /* check ACK/NACK */
mbed_official 409:a95c696104d3 306 if ((REG(SR2.UINT32) & (1 << 4) == 1)) {
mbed_official 409:a95c696104d3 307 /* Slave sends NACK */
mbed_official 409:a95c696104d3 308 i2c_stop(obj);
mbed_official 430:d406b7919023 309 // dummy read
mbed_official 430:d406b7919023 310 value = REG(DRR.UINT32);
mbed_official 430:d406b7919023 311 i2c_wait_STOP(obj);
mbed_official 409:a95c696104d3 312 return I2C_ERROR_NO_SLAVE;
mbed_official 390:35c2c1cf29cd 313 }
mbed_official 390:35c2c1cf29cd 314
mbed_official 409:a95c696104d3 315 // Read in all except last byte
mbed_official 430:d406b7919023 316 if (length > 2) {
mbed_official 409:a95c696104d3 317 for (count = 0; count < (length - 1); count++) {
mbed_official 409:a95c696104d3 318 if (count == (length - 2)) {
mbed_official 409:a95c696104d3 319 value = i2c_do_read(obj, 1);
mbed_official 409:a95c696104d3 320 } else if ((length >= 3) && (count == (length - 3))) {
mbed_official 409:a95c696104d3 321 value = i2c_do_read(obj, 2);
mbed_official 409:a95c696104d3 322 } else {
mbed_official 409:a95c696104d3 323 value = i2c_do_read(obj, 0);
mbed_official 409:a95c696104d3 324 }
mbed_official 409:a95c696104d3 325 status = i2c_status(obj);
mbed_official 409:a95c696104d3 326 if (status & 0x10) {
mbed_official 409:a95c696104d3 327 i2c_stop(obj);
mbed_official 430:d406b7919023 328 i2c_wait_STOP(obj);
mbed_official 409:a95c696104d3 329 return count;
mbed_official 409:a95c696104d3 330 }
mbed_official 409:a95c696104d3 331 data[count] = (char) value;
mbed_official 409:a95c696104d3 332 }
mbed_official 430:d406b7919023 333 } else if (length == 2) {
mbed_official 430:d406b7919023 334 /* Set MR3 WATI bit is 1 */;
mbed_official 430:d406b7919023 335 REG(MR3.UINT32) |= (1 << 6);
mbed_official 430:d406b7919023 336 // dummy read
mbed_official 430:d406b7919023 337 value = REG(DRR.UINT32);
mbed_official 430:d406b7919023 338 // wait for it to arrive
mbed_official 430:d406b7919023 339 i2c_wait_RDRF(obj);
mbed_official 430:d406b7919023 340 // send a NOT ACK
mbed_official 430:d406b7919023 341 REG(MR3.UINT32) |= (1 <<4);
mbed_official 430:d406b7919023 342 REG(MR3.UINT32) |= (1 <<3);
mbed_official 430:d406b7919023 343 REG(MR3.UINT32) &= ~(1 <<4);
mbed_official 430:d406b7919023 344 data[count] = (char)REG(DRR.UINT32);
mbed_official 430:d406b7919023 345 count++;
mbed_official 430:d406b7919023 346 } else if (length == 1) {
mbed_official 430:d406b7919023 347 /* Set MR3 WATI bit is 1 */;
mbed_official 430:d406b7919023 348 REG(MR3.UINT32) |= (1 << 6);
mbed_official 430:d406b7919023 349 // send a NOT ACK
mbed_official 430:d406b7919023 350 REG(MR3.UINT32) |= (1 <<4);
mbed_official 430:d406b7919023 351 REG(MR3.UINT32) |= (1 <<3);
mbed_official 430:d406b7919023 352 REG(MR3.UINT32) &= ~(1 <<4);
mbed_official 430:d406b7919023 353 // dummy read
mbed_official 430:d406b7919023 354 value = REG(DRR.UINT32);
mbed_official 430:d406b7919023 355 } else {
mbed_official 430:d406b7919023 356 // Do Nothing
mbed_official 409:a95c696104d3 357 }
mbed_official 409:a95c696104d3 358
mbed_official 390:35c2c1cf29cd 359 // read in last byte
mbed_official 409:a95c696104d3 360 i2c_wait_RDRF(obj);
mbed_official 390:35c2c1cf29cd 361 // If not repeated start, send stop.
mbed_official 390:35c2c1cf29cd 362 if (stop) {
mbed_official 430:d406b7919023 363 /* RIICnSR2.STOP = 0 */
mbed_official 430:d406b7919023 364 REG(SR2.UINT32) &= ~(1 << 3);
mbed_official 430:d406b7919023 365 /* RIICnCR2.SP = 1 */
mbed_official 430:d406b7919023 366 REG(CR2.UINT32) |= (1 << 3);
mbed_official 430:d406b7919023 367 /* RIICnDRR read */
mbed_official 430:d406b7919023 368 value = REG(DRR.UINT32) & 0xFF;
mbed_official 430:d406b7919023 369 data[count] = (char) value;
mbed_official 430:d406b7919023 370 /* RIICnMR3.WAIT = 0 */
mbed_official 430:d406b7919023 371 REG(MR3.UINT32) &= ~(1 << 6);
mbed_official 430:d406b7919023 372 i2c_wait_STOP(obj);
mbed_official 430:d406b7919023 373 } else {
mbed_official 430:d406b7919023 374 /* RIICnDRR read */
mbed_official 430:d406b7919023 375 value = REG(DRR.UINT32) & 0xFF;
mbed_official 430:d406b7919023 376 data[count] = (char) value;
mbed_official 390:35c2c1cf29cd 377 }
mbed_official 409:a95c696104d3 378
mbed_official 390:35c2c1cf29cd 379 return length;
mbed_official 390:35c2c1cf29cd 380 }
mbed_official 390:35c2c1cf29cd 381
mbed_official 390:35c2c1cf29cd 382 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
mbed_official 390:35c2c1cf29cd 383 int i, status;
mbed_official 409:a95c696104d3 384
mbed_official 409:a95c696104d3 385 // full reset
mbed_official 409:a95c696104d3 386 i2c_reg_reset(obj);
mbed_official 409:a95c696104d3 387
mbed_official 390:35c2c1cf29cd 388 status = i2c_start(obj);
mbed_official 409:a95c696104d3 389
mbed_official 390:35c2c1cf29cd 390 if ((status == 0xff)) {
mbed_official 390:35c2c1cf29cd 391 i2c_stop(obj);
mbed_official 430:d406b7919023 392 i2c_wait_STOP(obj);
mbed_official 390:35c2c1cf29cd 393 return I2C_ERROR_BUS_BUSY;
mbed_official 390:35c2c1cf29cd 394 }
mbed_official 430:d406b7919023 395
mbed_official 430:d406b7919023 396 /**/
mbed_official 430:d406b7919023 397 status = REG(CR2.UINT32);
mbed_official 430:d406b7919023 398 status = REG(SR2.UINT32);
mbed_official 430:d406b7919023 399 /**/
mbed_official 409:a95c696104d3 400
mbed_official 390:35c2c1cf29cd 401 status = i2c_do_write(obj, address);
mbed_official 390:35c2c1cf29cd 402 if (status & 0x10) {
mbed_official 390:35c2c1cf29cd 403 i2c_stop(obj);
mbed_official 430:d406b7919023 404 i2c_wait_STOP(obj);
mbed_official 390:35c2c1cf29cd 405 return I2C_ERROR_NO_SLAVE;
mbed_official 390:35c2c1cf29cd 406 }
mbed_official 409:a95c696104d3 407
mbed_official 430:d406b7919023 408 /**/
mbed_official 430:d406b7919023 409 status = REG(CR2.UINT32);
mbed_official 430:d406b7919023 410 status = REG(SR2.UINT32);
mbed_official 430:d406b7919023 411 /**/
mbed_official 390:35c2c1cf29cd 412 for (i=0; i<length; i++) {
mbed_official 430:d406b7919023 413 /**/
mbed_official 430:d406b7919023 414 status = REG(CR2.UINT32);
mbed_official 430:d406b7919023 415 status = REG(SR2.UINT32);
mbed_official 430:d406b7919023 416 /**/
mbed_official 390:35c2c1cf29cd 417 status = i2c_do_write(obj, data[i]);
mbed_official 390:35c2c1cf29cd 418 if(status & 0x10) {
mbed_official 390:35c2c1cf29cd 419 i2c_stop(obj);
mbed_official 430:d406b7919023 420 i2c_wait_STOP(obj);
mbed_official 390:35c2c1cf29cd 421 return i;
mbed_official 390:35c2c1cf29cd 422 }
mbed_official 390:35c2c1cf29cd 423 }
mbed_official 409:a95c696104d3 424
mbed_official 409:a95c696104d3 425 i2c_wait_TEND(obj);
mbed_official 409:a95c696104d3 426
mbed_official 390:35c2c1cf29cd 427 // If not repeated start, send stop.
mbed_official 390:35c2c1cf29cd 428 if (stop) {
mbed_official 390:35c2c1cf29cd 429 i2c_stop(obj);
mbed_official 430:d406b7919023 430 i2c_wait_STOP(obj);
mbed_official 390:35c2c1cf29cd 431 }
mbed_official 409:a95c696104d3 432
mbed_official 390:35c2c1cf29cd 433 return length;
mbed_official 390:35c2c1cf29cd 434 }
mbed_official 390:35c2c1cf29cd 435
mbed_official 390:35c2c1cf29cd 436 void i2c_reset(i2c_t *obj) {
mbed_official 390:35c2c1cf29cd 437 i2c_stop(obj);
mbed_official 430:d406b7919023 438 i2c_wait_STOP(obj);
mbed_official 390:35c2c1cf29cd 439 }
mbed_official 390:35c2c1cf29cd 440
mbed_official 390:35c2c1cf29cd 441 int i2c_byte_read(i2c_t *obj, int last) {
mbed_official 430:d406b7919023 442 obj->dummy = 1;
mbed_official 430:d406b7919023 443
mbed_official 390:35c2c1cf29cd 444 return (i2c_do_read(obj, last) & 0xFF);
mbed_official 390:35c2c1cf29cd 445 }
mbed_official 390:35c2c1cf29cd 446
mbed_official 390:35c2c1cf29cd 447 int i2c_byte_write(i2c_t *obj, int data) {
mbed_official 390:35c2c1cf29cd 448 int ack;
mbed_official 390:35c2c1cf29cd 449 int status = i2c_do_write(obj, (data & 0xFF));
mbed_official 390:35c2c1cf29cd 450 if (status & NACKF) {
mbed_official 390:35c2c1cf29cd 451 ack = 0;
mbed_official 390:35c2c1cf29cd 452 } else {
mbed_official 390:35c2c1cf29cd 453 ack = 1;
mbed_official 390:35c2c1cf29cd 454 }
mbed_official 409:a95c696104d3 455
mbed_official 390:35c2c1cf29cd 456 return ack;
mbed_official 390:35c2c1cf29cd 457 }
mbed_official 390:35c2c1cf29cd 458
mbed_official 390:35c2c1cf29cd 459 void i2c_slave_mode(i2c_t *obj, int enable_slave) {
mbed_official 390:35c2c1cf29cd 460 if (enable_slave != 0) {
mbed_official 390:35c2c1cf29cd 461 REG(SER.UINT32) = 0x01; // only slave addr 1 is enabled
mbed_official 390:35c2c1cf29cd 462 } else {
mbed_official 390:35c2c1cf29cd 463 REG(SER.UINT32) = 0x00; // no slave addr enabled
mbed_official 390:35c2c1cf29cd 464 }
mbed_official 390:35c2c1cf29cd 465 }
mbed_official 390:35c2c1cf29cd 466
mbed_official 390:35c2c1cf29cd 467 int i2c_slave_receive(i2c_t *obj) {
mbed_official 390:35c2c1cf29cd 468 int status;
mbed_official 390:35c2c1cf29cd 469 int retval;
mbed_official 409:a95c696104d3 470
mbed_official 390:35c2c1cf29cd 471 status = i2c_addressed(obj);
mbed_official 390:35c2c1cf29cd 472 switch(status) {
mbed_official 390:35c2c1cf29cd 473 case 0x3: retval = 1; break;
mbed_official 390:35c2c1cf29cd 474 case 0x2: retval = 2; break;
mbed_official 390:35c2c1cf29cd 475 case 0x1: retval = 3; break;
mbed_official 390:35c2c1cf29cd 476 default : retval = 1; break;
mbed_official 390:35c2c1cf29cd 477 }
mbed_official 409:a95c696104d3 478
mbed_official 390:35c2c1cf29cd 479 return(retval);
mbed_official 390:35c2c1cf29cd 480 }
mbed_official 390:35c2c1cf29cd 481
mbed_official 390:35c2c1cf29cd 482 int i2c_slave_read(i2c_t *obj, char *data, int length) {
mbed_official 390:35c2c1cf29cd 483 int count = 0;
mbed_official 390:35c2c1cf29cd 484 int status;
mbed_official 390:35c2c1cf29cd 485
mbed_official 430:d406b7919023 486 volatile int dummy = REG(DRR.UINT32) ;
mbed_official 409:a95c696104d3 487
mbed_official 390:35c2c1cf29cd 488 do {
mbed_official 390:35c2c1cf29cd 489 i2c_wait_RDRF(obj);
mbed_official 390:35c2c1cf29cd 490 status = i2c_status(obj);
mbed_official 390:35c2c1cf29cd 491 if(!(status & 0x10)) {
mbed_official 390:35c2c1cf29cd 492 data[count] = REG(DRR.UINT32) & 0xFF;
mbed_official 390:35c2c1cf29cd 493 }
mbed_official 390:35c2c1cf29cd 494 count++;
mbed_official 390:35c2c1cf29cd 495 } while ( !(status & 0x10) && (count < length) );
mbed_official 409:a95c696104d3 496
mbed_official 390:35c2c1cf29cd 497 if(status & 0x10) {
mbed_official 390:35c2c1cf29cd 498 i2c_stop(obj);
mbed_official 430:d406b7919023 499 i2c_wait_STOP(obj);
mbed_official 390:35c2c1cf29cd 500 }
mbed_official 409:a95c696104d3 501
mbed_official 390:35c2c1cf29cd 502 //i2c_clear_TDRE(obj);
mbed_official 409:a95c696104d3 503
mbed_official 390:35c2c1cf29cd 504 return count;
mbed_official 390:35c2c1cf29cd 505 }
mbed_official 390:35c2c1cf29cd 506
mbed_official 390:35c2c1cf29cd 507 int i2c_slave_write(i2c_t *obj, const char *data, int length) {
mbed_official 390:35c2c1cf29cd 508 int count = 0;
mbed_official 390:35c2c1cf29cd 509 int status;
mbed_official 409:a95c696104d3 510
mbed_official 390:35c2c1cf29cd 511 if(length <= 0) {
mbed_official 390:35c2c1cf29cd 512 return(0);
mbed_official 390:35c2c1cf29cd 513 }
mbed_official 409:a95c696104d3 514
mbed_official 390:35c2c1cf29cd 515 do {
mbed_official 390:35c2c1cf29cd 516 status = i2c_do_write(obj, data[count]);
mbed_official 390:35c2c1cf29cd 517 count++;
mbed_official 390:35c2c1cf29cd 518 } while ((count < length) && !(status & 0x10));
mbed_official 409:a95c696104d3 519
mbed_official 390:35c2c1cf29cd 520 if (!(status & 0x10)) {
mbed_official 390:35c2c1cf29cd 521 i2c_stop(obj);
mbed_official 430:d406b7919023 522 i2c_wait_STOP(obj);
mbed_official 390:35c2c1cf29cd 523 }
mbed_official 409:a95c696104d3 524
mbed_official 390:35c2c1cf29cd 525 i2c_clear_TDRE(obj);
mbed_official 409:a95c696104d3 526
mbed_official 390:35c2c1cf29cd 527 return(count);
mbed_official 390:35c2c1cf29cd 528 }
mbed_official 390:35c2c1cf29cd 529
mbed_official 390:35c2c1cf29cd 530 void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
mbed_official 390:35c2c1cf29cd 531 REG(SAR0.UINT32) = address & 0xfe;
mbed_official 390:35c2c1cf29cd 532 }