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targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_ll_sdmmc.h@394:83f921546702, 2014-11-07 (annotated)

Committer:
mbed_official
Date:
Fri Nov 07 15:45:07 2014 +0000
Revision:
394:83f921546702
Parent:
targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_ll_sdmmc.h@354:e67efb2aab0e 
Synchronized with git revision aab52cb7ec5a665869e507dd988bbfd55b7e087e



Full URL: https://github.com/mbedmicro/mbed/commit/aab52cb7ec5a665869e507dd988bbfd55b7e087e/



Tests: Fix cpputest testrunner

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UserRevisionLine numberNew contents of line
mbed_official 354:e67efb2aab0e 1 /**
mbed_official 354:e67efb2aab0e 2 ******************************************************************************
mbed_official 354:e67efb2aab0e 3 * @file stm32l1xx_ll_sdmmc.h
mbed_official 354:e67efb2aab0e 4 * @author MCD Application Team
mbed_official 354:e67efb2aab0e 5 * @version V1.0.0
mbed_official 354:e67efb2aab0e 6 * @date 5-September-2014
mbed_official 354:e67efb2aab0e 7 * @brief Header file of low layer SDMMC HAL module.
mbed_official 354:e67efb2aab0e 8 ******************************************************************************
mbed_official 354:e67efb2aab0e 9 * @attention
mbed_official 354:e67efb2aab0e 10 *
mbed_official 354:e67efb2aab0e 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 354:e67efb2aab0e 12 *
mbed_official 354:e67efb2aab0e 13 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 354:e67efb2aab0e 14 * are permitted provided that the following conditions are met:
mbed_official 354:e67efb2aab0e 15 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 354:e67efb2aab0e 16 * this list of conditions and the following disclaimer.
mbed_official 354:e67efb2aab0e 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 354:e67efb2aab0e 18 * this list of conditions and the following disclaimer in the documentation
mbed_official 354:e67efb2aab0e 19 * and/or other materials provided with the distribution.
mbed_official 354:e67efb2aab0e 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 354:e67efb2aab0e 21 * may be used to endorse or promote products derived from this software
mbed_official 354:e67efb2aab0e 22 * without specific prior written permission.
mbed_official 354:e67efb2aab0e 23 *
mbed_official 354:e67efb2aab0e 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 354:e67efb2aab0e 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 354:e67efb2aab0e 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 354:e67efb2aab0e 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 354:e67efb2aab0e 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 354:e67efb2aab0e 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 354:e67efb2aab0e 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 354:e67efb2aab0e 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 354:e67efb2aab0e 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 354:e67efb2aab0e 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 354:e67efb2aab0e 34 *
mbed_official 354:e67efb2aab0e 35 ******************************************************************************
mbed_official 354:e67efb2aab0e 36 */
mbed_official 354:e67efb2aab0e 37
mbed_official 354:e67efb2aab0e 38 /* Define to prevent recursive inclusion -------------------------------------*/
mbed_official 354:e67efb2aab0e 39 #ifndef __STM32L1xx_LL_SD_H
mbed_official 354:e67efb2aab0e 40 #define __STM32L1xx_LL_SD_H
mbed_official 354:e67efb2aab0e 41
mbed_official 354:e67efb2aab0e 42 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
mbed_official 354:e67efb2aab0e 43
mbed_official 354:e67efb2aab0e 44 #ifdef __cplusplus
mbed_official 354:e67efb2aab0e 45 extern "C" {
mbed_official 354:e67efb2aab0e 46 #endif
mbed_official 354:e67efb2aab0e 47
mbed_official 354:e67efb2aab0e 48 /* Includes ------------------------------------------------------------------*/
mbed_official 354:e67efb2aab0e 49 #include "stm32l1xx_hal_def.h"
mbed_official 354:e67efb2aab0e 50
mbed_official 354:e67efb2aab0e 51 /** @addtogroup STM32L1xx_HAL_Driver
mbed_official 354:e67efb2aab0e 52 * @{
mbed_official 354:e67efb2aab0e 53 */
mbed_official 354:e67efb2aab0e 54
mbed_official 354:e67efb2aab0e 55 /** @addtogroup SDMMC_LL
mbed_official 354:e67efb2aab0e 56 * @{
mbed_official 354:e67efb2aab0e 57 */
mbed_official 354:e67efb2aab0e 58
mbed_official 354:e67efb2aab0e 59 /* Exported types ------------------------------------------------------------*/
mbed_official 354:e67efb2aab0e 60 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
mbed_official 354:e67efb2aab0e 61 * @{
mbed_official 354:e67efb2aab0e 62 */
mbed_official 354:e67efb2aab0e 63
mbed_official 354:e67efb2aab0e 64 /**
mbed_official 354:e67efb2aab0e 65 * @brief SDMMC Configuration Structure definition
mbed_official 354:e67efb2aab0e 66 */
mbed_official 354:e67efb2aab0e 67 typedef struct
mbed_official 354:e67efb2aab0e 68 {
mbed_official 354:e67efb2aab0e 69 uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
mbed_official 354:e67efb2aab0e 70 This parameter can be a value of @ref SDMMC_LL_Clock_Edge */
mbed_official 354:e67efb2aab0e 71
mbed_official 354:e67efb2aab0e 72 uint32_t ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
mbed_official 354:e67efb2aab0e 73 enabled or disabled.
mbed_official 354:e67efb2aab0e 74 This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */
mbed_official 354:e67efb2aab0e 75
mbed_official 354:e67efb2aab0e 76 uint32_t ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
mbed_official 354:e67efb2aab0e 77 disabled when the bus is idle.
mbed_official 354:e67efb2aab0e 78 This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */
mbed_official 354:e67efb2aab0e 79
mbed_official 354:e67efb2aab0e 80 uint32_t BusWide; /*!< Specifies the SDIO bus width.
mbed_official 354:e67efb2aab0e 81 This parameter can be a value of @ref SDMMC_LL_Bus_Wide */
mbed_official 354:e67efb2aab0e 82
mbed_official 354:e67efb2aab0e 83 uint32_t HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
mbed_official 354:e67efb2aab0e 84 This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */
mbed_official 354:e67efb2aab0e 85
mbed_official 354:e67efb2aab0e 86 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
mbed_official 354:e67efb2aab0e 87 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
mbed_official 354:e67efb2aab0e 88
mbed_official 354:e67efb2aab0e 89 }SDIO_InitTypeDef;
mbed_official 354:e67efb2aab0e 90
mbed_official 354:e67efb2aab0e 91
mbed_official 354:e67efb2aab0e 92 /**
mbed_official 354:e67efb2aab0e 93 * @brief SDIO Command Control structure
mbed_official 354:e67efb2aab0e 94 */
mbed_official 354:e67efb2aab0e 95 typedef struct
mbed_official 354:e67efb2aab0e 96 {
mbed_official 354:e67efb2aab0e 97 uint32_t Argument; /*!< Specifies the SDIO command argument which is sent
mbed_official 354:e67efb2aab0e 98 to a card as part of a command message. If a command
mbed_official 354:e67efb2aab0e 99 contains an argument, it must be loaded into this register
mbed_official 354:e67efb2aab0e 100 before writing the command to the command register. */
mbed_official 354:e67efb2aab0e 101
mbed_official 354:e67efb2aab0e 102 uint32_t CmdIndex; /*!< Specifies the SDIO command index. It must be Min_Data = 0 and
mbed_official 354:e67efb2aab0e 103 Max_Data = 64 */
mbed_official 354:e67efb2aab0e 104
mbed_official 354:e67efb2aab0e 105 uint32_t Response; /*!< Specifies the SDIO response type.
mbed_official 354:e67efb2aab0e 106 This parameter can be a value of @ref SDMMC_LL_Response_Type */
mbed_official 354:e67efb2aab0e 107
mbed_official 354:e67efb2aab0e 108 uint32_t WaitForInterrupt; /*!< Specifies whether SDIO wait for interrupt request is
mbed_official 354:e67efb2aab0e 109 enabled or disabled.
mbed_official 354:e67efb2aab0e 110 This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */
mbed_official 354:e67efb2aab0e 111
mbed_official 354:e67efb2aab0e 112 uint32_t CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
mbed_official 354:e67efb2aab0e 113 is enabled or disabled.
mbed_official 354:e67efb2aab0e 114 This parameter can be a value of @ref SDMMC_LL_CPSM_State */
mbed_official 354:e67efb2aab0e 115 }SDIO_CmdInitTypeDef;
mbed_official 354:e67efb2aab0e 116
mbed_official 354:e67efb2aab0e 117
mbed_official 354:e67efb2aab0e 118 /**
mbed_official 354:e67efb2aab0e 119 * @brief SDIO Data Control structure
mbed_official 354:e67efb2aab0e 120 */
mbed_official 354:e67efb2aab0e 121 typedef struct
mbed_official 354:e67efb2aab0e 122 {
mbed_official 354:e67efb2aab0e 123 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
mbed_official 354:e67efb2aab0e 124
mbed_official 354:e67efb2aab0e 125 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */
mbed_official 354:e67efb2aab0e 126
mbed_official 354:e67efb2aab0e 127 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
mbed_official 354:e67efb2aab0e 128 This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */
mbed_official 354:e67efb2aab0e 129
mbed_official 354:e67efb2aab0e 130 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
mbed_official 354:e67efb2aab0e 131 is a read or write.
mbed_official 354:e67efb2aab0e 132 This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
mbed_official 354:e67efb2aab0e 133
mbed_official 354:e67efb2aab0e 134 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
mbed_official 354:e67efb2aab0e 135 This parameter can be a value of @ref SDMMC_LL_Transfer_Type */
mbed_official 354:e67efb2aab0e 136
mbed_official 354:e67efb2aab0e 137 uint32_t DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
mbed_official 354:e67efb2aab0e 138 is enabled or disabled.
mbed_official 354:e67efb2aab0e 139 This parameter can be a value of @ref SDMMC_LL_DPSM_State */
mbed_official 354:e67efb2aab0e 140 }SDIO_DataInitTypeDef;
mbed_official 354:e67efb2aab0e 141
mbed_official 354:e67efb2aab0e 142 /**
mbed_official 354:e67efb2aab0e 143 * @}
mbed_official 354:e67efb2aab0e 144 */
mbed_official 354:e67efb2aab0e 145
mbed_official 354:e67efb2aab0e 146 /* Exported constants --------------------------------------------------------*/
mbed_official 354:e67efb2aab0e 147 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
mbed_official 354:e67efb2aab0e 148 * @{
mbed_official 354:e67efb2aab0e 149 */
mbed_official 354:e67efb2aab0e 150
mbed_official 354:e67efb2aab0e 151 /** @defgroup SDMMC_LL_Clock_Edge Clock Edge
mbed_official 354:e67efb2aab0e 152 * @{
mbed_official 354:e67efb2aab0e 153 */
mbed_official 354:e67efb2aab0e 154 #define SDIO_CLOCK_EDGE_RISING ((uint32_t)0x00000000)
mbed_official 354:e67efb2aab0e 155 #define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE
mbed_official 354:e67efb2aab0e 156
mbed_official 354:e67efb2aab0e 157 #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
mbed_official 354:e67efb2aab0e 158 ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
mbed_official 354:e67efb2aab0e 159 /**
mbed_official 354:e67efb2aab0e 160 * @}
mbed_official 354:e67efb2aab0e 161 */
mbed_official 354:e67efb2aab0e 162
mbed_official 354:e67efb2aab0e 163 /** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass
mbed_official 354:e67efb2aab0e 164 * @{
mbed_official 354:e67efb2aab0e 165 */
mbed_official 354:e67efb2aab0e 166 #define SDIO_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000)
mbed_official 354:e67efb2aab0e 167 #define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS
mbed_official 354:e67efb2aab0e 168
mbed_official 354:e67efb2aab0e 169 #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
mbed_official 354:e67efb2aab0e 170 ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
mbed_official 354:e67efb2aab0e 171 /**
mbed_official 354:e67efb2aab0e 172 * @}
mbed_official 354:e67efb2aab0e 173 */
mbed_official 354:e67efb2aab0e 174
mbed_official 354:e67efb2aab0e 175 /** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving
mbed_official 354:e67efb2aab0e 176 * @{
mbed_official 354:e67efb2aab0e 177 */
mbed_official 354:e67efb2aab0e 178 #define SDIO_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000)
mbed_official 354:e67efb2aab0e 179 #define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV
mbed_official 354:e67efb2aab0e 180
mbed_official 354:e67efb2aab0e 181 #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
mbed_official 354:e67efb2aab0e 182 ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
mbed_official 354:e67efb2aab0e 183 /**
mbed_official 354:e67efb2aab0e 184 * @}
mbed_official 354:e67efb2aab0e 185 */
mbed_official 354:e67efb2aab0e 186
mbed_official 354:e67efb2aab0e 187 /** @defgroup SDMMC_LL_Bus_Wide Bus Width
mbed_official 354:e67efb2aab0e 188 * @{
mbed_official 354:e67efb2aab0e 189 */
mbed_official 354:e67efb2aab0e 190 #define SDIO_BUS_WIDE_1B ((uint32_t)0x00000000)
mbed_official 354:e67efb2aab0e 191 #define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0
mbed_official 354:e67efb2aab0e 192 #define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1
mbed_official 354:e67efb2aab0e 193
mbed_official 354:e67efb2aab0e 194 #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
mbed_official 354:e67efb2aab0e 195 ((WIDE) == SDIO_BUS_WIDE_4B) || \
mbed_official 354:e67efb2aab0e 196 ((WIDE) == SDIO_BUS_WIDE_8B))
mbed_official 354:e67efb2aab0e 197 /**
mbed_official 354:e67efb2aab0e 198 * @}
mbed_official 354:e67efb2aab0e 199 */
mbed_official 354:e67efb2aab0e 200
mbed_official 354:e67efb2aab0e 201 /** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control
mbed_official 354:e67efb2aab0e 202 * @{
mbed_official 354:e67efb2aab0e 203 */
mbed_official 354:e67efb2aab0e 204 #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000)
mbed_official 354:e67efb2aab0e 205 #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN
mbed_official 354:e67efb2aab0e 206
mbed_official 354:e67efb2aab0e 207 #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
mbed_official 354:e67efb2aab0e 208 ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
mbed_official 354:e67efb2aab0e 209 /**
mbed_official 354:e67efb2aab0e 210 * @}
mbed_official 354:e67efb2aab0e 211 */
mbed_official 354:e67efb2aab0e 212
mbed_official 354:e67efb2aab0e 213 /** @defgroup SDMMC_LL_Clock_Division Clock Division
mbed_official 354:e67efb2aab0e 214 * @{
mbed_official 354:e67efb2aab0e 215 */
mbed_official 354:e67efb2aab0e 216 #define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFF)
mbed_official 354:e67efb2aab0e 217 /**
mbed_official 354:e67efb2aab0e 218 * @}
mbed_official 354:e67efb2aab0e 219 */
mbed_official 354:e67efb2aab0e 220
mbed_official 354:e67efb2aab0e 221 /** @defgroup SDMMC_LL_Command_Index Command Index
mbed_official 354:e67efb2aab0e 222 * @{
mbed_official 354:e67efb2aab0e 223 */
mbed_official 354:e67efb2aab0e 224 #define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
mbed_official 354:e67efb2aab0e 225 /**
mbed_official 354:e67efb2aab0e 226 * @}
mbed_official 354:e67efb2aab0e 227 */
mbed_official 354:e67efb2aab0e 228
mbed_official 354:e67efb2aab0e 229 /** @defgroup SDMMC_LL_Response_Type Response Type
mbed_official 354:e67efb2aab0e 230 * @{
mbed_official 354:e67efb2aab0e 231 */
mbed_official 354:e67efb2aab0e 232 #define SDIO_RESPONSE_NO ((uint32_t)0x00000000)
mbed_official 354:e67efb2aab0e 233 #define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0
mbed_official 354:e67efb2aab0e 234 #define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP
mbed_official 354:e67efb2aab0e 235
mbed_official 354:e67efb2aab0e 236 #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \
mbed_official 354:e67efb2aab0e 237 ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
mbed_official 354:e67efb2aab0e 238 ((RESPONSE) == SDIO_RESPONSE_LONG))
mbed_official 354:e67efb2aab0e 239 /**
mbed_official 354:e67efb2aab0e 240 * @}
mbed_official 354:e67efb2aab0e 241 */
mbed_official 354:e67efb2aab0e 242
mbed_official 354:e67efb2aab0e 243 /** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt
mbed_official 354:e67efb2aab0e 244 * @{
mbed_official 354:e67efb2aab0e 245 */
mbed_official 354:e67efb2aab0e 246 #define SDIO_WAIT_NO ((uint32_t)0x00000000)
mbed_official 354:e67efb2aab0e 247 #define SDIO_WAIT_IT SDIO_CMD_WAITINT
mbed_official 354:e67efb2aab0e 248 #define SDIO_WAIT_PEND SDIO_CMD_WAITPEND
mbed_official 354:e67efb2aab0e 249
mbed_official 354:e67efb2aab0e 250 #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
mbed_official 354:e67efb2aab0e 251 ((WAIT) == SDIO_WAIT_IT) || \
mbed_official 354:e67efb2aab0e 252 ((WAIT) == SDIO_WAIT_PEND))
mbed_official 354:e67efb2aab0e 253 /**
mbed_official 354:e67efb2aab0e 254 * @}
mbed_official 354:e67efb2aab0e 255 */
mbed_official 354:e67efb2aab0e 256
mbed_official 354:e67efb2aab0e 257 /** @defgroup SDMMC_LL_CPSM_State CPSM State
mbed_official 354:e67efb2aab0e 258 * @{
mbed_official 354:e67efb2aab0e 259 */
mbed_official 354:e67efb2aab0e 260 #define SDIO_CPSM_DISABLE ((uint32_t)0x00000000)
mbed_official 354:e67efb2aab0e 261 #define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN
mbed_official 354:e67efb2aab0e 262
mbed_official 354:e67efb2aab0e 263 #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
mbed_official 354:e67efb2aab0e 264 ((CPSM) == SDIO_CPSM_ENABLE))
mbed_official 354:e67efb2aab0e 265 /**
mbed_official 354:e67efb2aab0e 266 * @}
mbed_official 354:e67efb2aab0e 267 */
mbed_official 354:e67efb2aab0e 268
mbed_official 354:e67efb2aab0e 269 /** @defgroup SDMMC_LL_Response_Registers Response Register
mbed_official 354:e67efb2aab0e 270 * @{
mbed_official 354:e67efb2aab0e 271 */
mbed_official 354:e67efb2aab0e 272 #define SDIO_RESP1 ((uint32_t)0x00000000)
mbed_official 354:e67efb2aab0e 273 #define SDIO_RESP2 ((uint32_t)0x00000004)
mbed_official 354:e67efb2aab0e 274 #define SDIO_RESP3 ((uint32_t)0x00000008)
mbed_official 354:e67efb2aab0e 275 #define SDIO_RESP4 ((uint32_t)0x0000000C)
mbed_official 354:e67efb2aab0e 276
mbed_official 354:e67efb2aab0e 277 #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
mbed_official 354:e67efb2aab0e 278 ((RESP) == SDIO_RESP2) || \
mbed_official 354:e67efb2aab0e 279 ((RESP) == SDIO_RESP3) || \
mbed_official 354:e67efb2aab0e 280 ((RESP) == SDIO_RESP4))
mbed_official 354:e67efb2aab0e 281 /**
mbed_official 354:e67efb2aab0e 282 * @}
mbed_official 354:e67efb2aab0e 283 */
mbed_official 354:e67efb2aab0e 284
mbed_official 354:e67efb2aab0e 285 /** @defgroup SDMMC_LL_Data_Length Data Lenght
mbed_official 354:e67efb2aab0e 286 * @{
mbed_official 354:e67efb2aab0e 287 */
mbed_official 354:e67efb2aab0e 288 #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
mbed_official 354:e67efb2aab0e 289 /**
mbed_official 354:e67efb2aab0e 290 * @}
mbed_official 354:e67efb2aab0e 291 */
mbed_official 354:e67efb2aab0e 292
mbed_official 354:e67efb2aab0e 293 /** @defgroup SDMMC_LL_Data_Block_Size Data Block Size
mbed_official 354:e67efb2aab0e 294 * @{
mbed_official 354:e67efb2aab0e 295 */
mbed_official 354:e67efb2aab0e 296 #define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000000)
mbed_official 354:e67efb2aab0e 297 #define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0
mbed_official 354:e67efb2aab0e 298 #define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1
mbed_official 354:e67efb2aab0e 299 #define SDIO_DATABLOCK_SIZE_8B ((uint32_t)0x00000030)
mbed_official 354:e67efb2aab0e 300 #define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2
mbed_official 354:e67efb2aab0e 301 #define SDIO_DATABLOCK_SIZE_32B ((uint32_t)0x00000050)
mbed_official 354:e67efb2aab0e 302 #define SDIO_DATABLOCK_SIZE_64B ((uint32_t)0x00000060)
mbed_official 354:e67efb2aab0e 303 #define SDIO_DATABLOCK_SIZE_128B ((uint32_t)0x00000070)
mbed_official 354:e67efb2aab0e 304 #define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3
mbed_official 354:e67efb2aab0e 305 #define SDIO_DATABLOCK_SIZE_512B ((uint32_t)0x00000090)
mbed_official 354:e67efb2aab0e 306 #define SDIO_DATABLOCK_SIZE_1024B ((uint32_t)0x000000A0)
mbed_official 354:e67efb2aab0e 307 #define SDIO_DATABLOCK_SIZE_2048B ((uint32_t)0x000000B0)
mbed_official 354:e67efb2aab0e 308 #define SDIO_DATABLOCK_SIZE_4096B ((uint32_t)0x000000C0)
mbed_official 354:e67efb2aab0e 309 #define SDIO_DATABLOCK_SIZE_8192B ((uint32_t)0x000000D0)
mbed_official 354:e67efb2aab0e 310 #define SDIO_DATABLOCK_SIZE_16384B ((uint32_t)0x000000E0)
mbed_official 354:e67efb2aab0e 311
mbed_official 354:e67efb2aab0e 312 #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \
mbed_official 354:e67efb2aab0e 313 ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \
mbed_official 354:e67efb2aab0e 314 ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \
mbed_official 354:e67efb2aab0e 315 ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \
mbed_official 354:e67efb2aab0e 316 ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \
mbed_official 354:e67efb2aab0e 317 ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \
mbed_official 354:e67efb2aab0e 318 ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \
mbed_official 354:e67efb2aab0e 319 ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \
mbed_official 354:e67efb2aab0e 320 ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \
mbed_official 354:e67efb2aab0e 321 ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \
mbed_official 354:e67efb2aab0e 322 ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
mbed_official 354:e67efb2aab0e 323 ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
mbed_official 354:e67efb2aab0e 324 ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
mbed_official 354:e67efb2aab0e 325 ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
mbed_official 354:e67efb2aab0e 326 ((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
mbed_official 354:e67efb2aab0e 327 /**
mbed_official 354:e67efb2aab0e 328 * @}
mbed_official 354:e67efb2aab0e 329 */
mbed_official 354:e67efb2aab0e 330
mbed_official 354:e67efb2aab0e 331 /** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction
mbed_official 354:e67efb2aab0e 332 * @{
mbed_official 354:e67efb2aab0e 333 */
mbed_official 354:e67efb2aab0e 334 #define SDIO_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000)
mbed_official 354:e67efb2aab0e 335 #define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR
mbed_official 354:e67efb2aab0e 336
mbed_official 354:e67efb2aab0e 337 #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
mbed_official 354:e67efb2aab0e 338 ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
mbed_official 354:e67efb2aab0e 339 /**
mbed_official 354:e67efb2aab0e 340 * @}
mbed_official 354:e67efb2aab0e 341 */
mbed_official 354:e67efb2aab0e 342
mbed_official 354:e67efb2aab0e 343 /** @defgroup SDMMC_LL_Transfer_Type Transfer Type
mbed_official 354:e67efb2aab0e 344 * @{
mbed_official 354:e67efb2aab0e 345 */
mbed_official 354:e67efb2aab0e 346 #define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000)
mbed_official 354:e67efb2aab0e 347 #define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE
mbed_official 354:e67efb2aab0e 348
mbed_official 354:e67efb2aab0e 349 #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
mbed_official 354:e67efb2aab0e 350 ((MODE) == SDIO_TRANSFER_MODE_STREAM))
mbed_official 354:e67efb2aab0e 351 /**
mbed_official 354:e67efb2aab0e 352 * @}
mbed_official 354:e67efb2aab0e 353 */
mbed_official 354:e67efb2aab0e 354
mbed_official 354:e67efb2aab0e 355 /** @defgroup SDMMC_LL_DPSM_State DPSM State
mbed_official 354:e67efb2aab0e 356 * @{
mbed_official 354:e67efb2aab0e 357 */
mbed_official 354:e67efb2aab0e 358 #define SDIO_DPSM_DISABLE ((uint32_t)0x00000000)
mbed_official 354:e67efb2aab0e 359 #define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN
mbed_official 354:e67efb2aab0e 360
mbed_official 354:e67efb2aab0e 361 #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
mbed_official 354:e67efb2aab0e 362 ((DPSM) == SDIO_DPSM_ENABLE))
mbed_official 354:e67efb2aab0e 363 /**
mbed_official 354:e67efb2aab0e 364 * @}
mbed_official 354:e67efb2aab0e 365 */
mbed_official 354:e67efb2aab0e 366
mbed_official 354:e67efb2aab0e 367 /** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode
mbed_official 354:e67efb2aab0e 368 * @{
mbed_official 354:e67efb2aab0e 369 */
mbed_official 354:e67efb2aab0e 370 #define SDIO_READ_WAIT_MODE_CLK ((uint32_t)0x00000000)
mbed_official 354:e67efb2aab0e 371 #define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000001)
mbed_official 354:e67efb2aab0e 372
mbed_official 354:e67efb2aab0e 373 #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
mbed_official 354:e67efb2aab0e 374 ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
mbed_official 354:e67efb2aab0e 375 /**
mbed_official 354:e67efb2aab0e 376 * @}
mbed_official 354:e67efb2aab0e 377 */
mbed_official 354:e67efb2aab0e 378
mbed_official 354:e67efb2aab0e 379 /** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
mbed_official 354:e67efb2aab0e 380 * @{
mbed_official 354:e67efb2aab0e 381 */
mbed_official 354:e67efb2aab0e 382 #define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL
mbed_official 354:e67efb2aab0e 383 #define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL
mbed_official 354:e67efb2aab0e 384 #define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT
mbed_official 354:e67efb2aab0e 385 #define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT
mbed_official 354:e67efb2aab0e 386 #define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR
mbed_official 354:e67efb2aab0e 387 #define SDIO_IT_RXOVERR SDIO_STA_RXOVERR
mbed_official 354:e67efb2aab0e 388 #define SDIO_IT_CMDREND SDIO_STA_CMDREND
mbed_official 354:e67efb2aab0e 389 #define SDIO_IT_CMDSENT SDIO_STA_CMDSENT
mbed_official 354:e67efb2aab0e 390 #define SDIO_IT_DATAEND SDIO_STA_DATAEND
mbed_official 354:e67efb2aab0e 391 #define SDIO_IT_STBITERR SDIO_STA_STBITERR
mbed_official 354:e67efb2aab0e 392 #define SDIO_IT_DBCKEND SDIO_STA_DBCKEND
mbed_official 354:e67efb2aab0e 393 #define SDIO_IT_CMDACT SDIO_STA_CMDACT
mbed_official 354:e67efb2aab0e 394 #define SDIO_IT_TXACT SDIO_STA_TXACT
mbed_official 354:e67efb2aab0e 395 #define SDIO_IT_RXACT SDIO_STA_RXACT
mbed_official 354:e67efb2aab0e 396 #define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE
mbed_official 354:e67efb2aab0e 397 #define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF
mbed_official 354:e67efb2aab0e 398 #define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF
mbed_official 354:e67efb2aab0e 399 #define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF
mbed_official 354:e67efb2aab0e 400 #define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE
mbed_official 354:e67efb2aab0e 401 #define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE
mbed_official 354:e67efb2aab0e 402 #define SDIO_IT_TXDAVL SDIO_STA_TXDAVL
mbed_official 354:e67efb2aab0e 403 #define SDIO_IT_RXDAVL SDIO_STA_RXDAVL
mbed_official 354:e67efb2aab0e 404 #define SDIO_IT_SDIOIT SDIO_STA_SDIOIT
mbed_official 354:e67efb2aab0e 405 #define SDIO_IT_CEATAEND SDIO_STA_CEATAEND
mbed_official 354:e67efb2aab0e 406
mbed_official 354:e67efb2aab0e 407 /**
mbed_official 354:e67efb2aab0e 408 * @}
mbed_official 354:e67efb2aab0e 409 */
mbed_official 354:e67efb2aab0e 410
mbed_official 354:e67efb2aab0e 411 /** @defgroup SDMMC_LL_Flags Flags
mbed_official 354:e67efb2aab0e 412 * @{
mbed_official 354:e67efb2aab0e 413 */
mbed_official 354:e67efb2aab0e 414 #define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL
mbed_official 354:e67efb2aab0e 415 #define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL
mbed_official 354:e67efb2aab0e 416 #define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT
mbed_official 354:e67efb2aab0e 417 #define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT
mbed_official 354:e67efb2aab0e 418 #define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR
mbed_official 354:e67efb2aab0e 419 #define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR
mbed_official 354:e67efb2aab0e 420 #define SDIO_FLAG_CMDREND SDIO_STA_CMDREND
mbed_official 354:e67efb2aab0e 421 #define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT
mbed_official 354:e67efb2aab0e 422 #define SDIO_FLAG_DATAEND SDIO_STA_DATAEND
mbed_official 354:e67efb2aab0e 423 #define SDIO_FLAG_STBITERR SDIO_STA_STBITERR
mbed_official 354:e67efb2aab0e 424 #define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND
mbed_official 354:e67efb2aab0e 425 #define SDIO_FLAG_CMDACT SDIO_STA_CMDACT
mbed_official 354:e67efb2aab0e 426 #define SDIO_FLAG_TXACT SDIO_STA_TXACT
mbed_official 354:e67efb2aab0e 427 #define SDIO_FLAG_RXACT SDIO_STA_RXACT
mbed_official 354:e67efb2aab0e 428 #define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE
mbed_official 354:e67efb2aab0e 429 #define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF
mbed_official 354:e67efb2aab0e 430 #define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF
mbed_official 354:e67efb2aab0e 431 #define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF
mbed_official 354:e67efb2aab0e 432 #define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE
mbed_official 354:e67efb2aab0e 433 #define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE
mbed_official 354:e67efb2aab0e 434 #define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL
mbed_official 354:e67efb2aab0e 435 #define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL
mbed_official 354:e67efb2aab0e 436 #define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT
mbed_official 354:e67efb2aab0e 437 #define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND
mbed_official 354:e67efb2aab0e 438
mbed_official 354:e67efb2aab0e 439 /**
mbed_official 354:e67efb2aab0e 440 * @}
mbed_official 354:e67efb2aab0e 441 */
mbed_official 354:e67efb2aab0e 442
mbed_official 354:e67efb2aab0e 443 /**
mbed_official 354:e67efb2aab0e 444 * @}
mbed_official 354:e67efb2aab0e 445 */
mbed_official 354:e67efb2aab0e 446
mbed_official 354:e67efb2aab0e 447 /* Exported macro ------------------------------------------------------------*/
mbed_official 354:e67efb2aab0e 448 /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
mbed_official 354:e67efb2aab0e 449 * @{
mbed_official 354:e67efb2aab0e 450 */
mbed_official 354:e67efb2aab0e 451
mbed_official 354:e67efb2aab0e 452 /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
mbed_official 354:e67efb2aab0e 453 * @brief SDMMC_LL registers bit address in the alias region
mbed_official 354:e67efb2aab0e 454 * @{
mbed_official 354:e67efb2aab0e 455 */
mbed_official 354:e67efb2aab0e 456
mbed_official 354:e67efb2aab0e 457 /* ------------ SDIO registers bit address in the alias region -------------- */
mbed_official 354:e67efb2aab0e 458 #define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
mbed_official 354:e67efb2aab0e 459
mbed_official 354:e67efb2aab0e 460 /* --- CLKCR Register ---*/
mbed_official 354:e67efb2aab0e 461 /* Alias word address of CLKEN bit */
mbed_official 354:e67efb2aab0e 462 #define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
mbed_official 354:e67efb2aab0e 463 #define CLKEN_BITNUMBER 0x08
mbed_official 354:e67efb2aab0e 464 #define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BITNUMBER * 4))
mbed_official 354:e67efb2aab0e 465
mbed_official 354:e67efb2aab0e 466 /* --- CMD Register ---*/
mbed_official 354:e67efb2aab0e 467 /* Alias word address of SDIOSUSPEND bit */
mbed_official 354:e67efb2aab0e 468 #define CMD_OFFSET (SDIO_OFFSET + 0x0C)
mbed_official 354:e67efb2aab0e 469 #define SDIOSUSPEND_BITNUMBER 0x0B
mbed_official 354:e67efb2aab0e 470 #define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BITNUMBER * 4))
mbed_official 354:e67efb2aab0e 471
mbed_official 354:e67efb2aab0e 472 /* Alias word address of ENCMDCOMPL bit */
mbed_official 354:e67efb2aab0e 473 #define ENCMDCOMPL_BITNUMBER 0x0C
mbed_official 354:e67efb2aab0e 474 #define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BITNUMBER * 4))
mbed_official 354:e67efb2aab0e 475
mbed_official 354:e67efb2aab0e 476 /* Alias word address of NIEN bit */
mbed_official 354:e67efb2aab0e 477 #define NIEN_BITNUMBER 0x0D
mbed_official 354:e67efb2aab0e 478 #define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BITNUMBER * 4))
mbed_official 354:e67efb2aab0e 479
mbed_official 354:e67efb2aab0e 480 /* Alias word address of ATACMD bit */
mbed_official 354:e67efb2aab0e 481 #define ATACMD_BITNUMBER 0x0E
mbed_official 354:e67efb2aab0e 482 #define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BITNUMBER * 4))
mbed_official 354:e67efb2aab0e 483
mbed_official 354:e67efb2aab0e 484 /* --- DCTRL Register ---*/
mbed_official 354:e67efb2aab0e 485 /* Alias word address of DMAEN bit */
mbed_official 354:e67efb2aab0e 486 #define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
mbed_official 354:e67efb2aab0e 487 #define DMAEN_BITNUMBER 0x03
mbed_official 354:e67efb2aab0e 488 #define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BITNUMBER * 4))
mbed_official 354:e67efb2aab0e 489
mbed_official 354:e67efb2aab0e 490 /* Alias word address of RWSTART bit */
mbed_official 354:e67efb2aab0e 491 #define RWSTART_BITNUMBER 0x08
mbed_official 354:e67efb2aab0e 492 #define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BITNUMBER * 4))
mbed_official 354:e67efb2aab0e 493
mbed_official 354:e67efb2aab0e 494 /* Alias word address of RWSTOP bit */
mbed_official 354:e67efb2aab0e 495 #define RWSTOP_BITNUMBER 0x09
mbed_official 354:e67efb2aab0e 496 #define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BITNUMBER * 4))
mbed_official 354:e67efb2aab0e 497
mbed_official 354:e67efb2aab0e 498 /* Alias word address of RWMOD bit */
mbed_official 354:e67efb2aab0e 499 #define RWMOD_BITNUMBER 0x0A
mbed_official 354:e67efb2aab0e 500 #define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BITNUMBER * 4))
mbed_official 354:e67efb2aab0e 501
mbed_official 354:e67efb2aab0e 502 /* Alias word address of SDIOEN bit */
mbed_official 354:e67efb2aab0e 503 #define SDIOEN_BITNUMBER 0x0B
mbed_official 354:e67efb2aab0e 504 #define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BITNUMBER * 4))
mbed_official 354:e67efb2aab0e 505
mbed_official 354:e67efb2aab0e 506 /* ---------------------- SDIO registers bit mask --------------------------- */
mbed_official 354:e67efb2aab0e 507 /* --- CLKCR Register ---*/
mbed_official 354:e67efb2aab0e 508 /* CLKCR register clear mask */
mbed_official 354:e67efb2aab0e 509 #define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV | SDIO_CLKCR_PWRSAV |\
mbed_official 354:e67efb2aab0e 510 SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS |\
mbed_official 354:e67efb2aab0e 511 SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN))
mbed_official 354:e67efb2aab0e 512
mbed_official 354:e67efb2aab0e 513 /* --- DCTRL Register ---*/
mbed_official 354:e67efb2aab0e 514 /* SDIO DCTRL Clear Mask */
mbed_official 354:e67efb2aab0e 515 #define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR |\
mbed_official 354:e67efb2aab0e 516 SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE))
mbed_official 354:e67efb2aab0e 517
mbed_official 354:e67efb2aab0e 518 /* --- CMD Register ---*/
mbed_official 354:e67efb2aab0e 519 /* CMD Register clear mask */
mbed_official 354:e67efb2aab0e 520 #define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\
mbed_official 354:e67efb2aab0e 521 SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND |\
mbed_official 354:e67efb2aab0e 522 SDIO_CMD_CPSMEN | SDIO_CMD_SDIOSUSPEND))
mbed_official 354:e67efb2aab0e 523
mbed_official 354:e67efb2aab0e 524 /* SDIO RESP Registers Address */
mbed_official 354:e67efb2aab0e 525 #define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
mbed_official 354:e67efb2aab0e 526
mbed_official 354:e67efb2aab0e 527 /* SDIO Intialization Frequency (400KHz max) */
mbed_official 354:e67efb2aab0e 528 #define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
mbed_official 354:e67efb2aab0e 529
mbed_official 354:e67efb2aab0e 530 /* SDIO Data Transfer Frequency */
mbed_official 354:e67efb2aab0e 531 #define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x4)
mbed_official 354:e67efb2aab0e 532
mbed_official 354:e67efb2aab0e 533 /**
mbed_official 354:e67efb2aab0e 534 * @}
mbed_official 354:e67efb2aab0e 535 */
mbed_official 354:e67efb2aab0e 536
mbed_official 354:e67efb2aab0e 537 /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
mbed_official 354:e67efb2aab0e 538 * @brief macros to handle interrupts and specific clock configurations
mbed_official 354:e67efb2aab0e 539 * @{
mbed_official 354:e67efb2aab0e 540 */
mbed_official 354:e67efb2aab0e 541
mbed_official 354:e67efb2aab0e 542 /**
mbed_official 354:e67efb2aab0e 543 * @brief Enable the SDIO device.
mbed_official 354:e67efb2aab0e 544 * @retval None
mbed_official 354:e67efb2aab0e 545 */
mbed_official 354:e67efb2aab0e 546 #define __SDIO_ENABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
mbed_official 354:e67efb2aab0e 547
mbed_official 354:e67efb2aab0e 548 /**
mbed_official 354:e67efb2aab0e 549 * @brief Disable the SDIO device.
mbed_official 354:e67efb2aab0e 550 * @retval None
mbed_official 354:e67efb2aab0e 551 */
mbed_official 354:e67efb2aab0e 552 #define __SDIO_DISABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
mbed_official 354:e67efb2aab0e 553
mbed_official 354:e67efb2aab0e 554 /**
mbed_official 354:e67efb2aab0e 555 * @brief Enable the SDIO DMA transfer.
mbed_official 354:e67efb2aab0e 556 * @retval None
mbed_official 354:e67efb2aab0e 557 */
mbed_official 354:e67efb2aab0e 558 #define __SDIO_DMA_ENABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
mbed_official 354:e67efb2aab0e 559
mbed_official 354:e67efb2aab0e 560 /**
mbed_official 354:e67efb2aab0e 561 * @brief Disable the SDIO DMA transfer.
mbed_official 354:e67efb2aab0e 562 * @retval None
mbed_official 354:e67efb2aab0e 563 */
mbed_official 354:e67efb2aab0e 564 #define __SDIO_DMA_DISABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
mbed_official 354:e67efb2aab0e 565
mbed_official 354:e67efb2aab0e 566 /**
mbed_official 354:e67efb2aab0e 567 * @brief Enable the SDIO device interrupt.
mbed_official 354:e67efb2aab0e 568 * @param __INSTANCE__ : Pointer to SDIO register base
mbed_official 354:e67efb2aab0e 569 * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
mbed_official 354:e67efb2aab0e 570 * This parameter can be one or a combination of the following values:
mbed_official 354:e67efb2aab0e 571 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
mbed_official 354:e67efb2aab0e 572 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
mbed_official 354:e67efb2aab0e 573 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
mbed_official 354:e67efb2aab0e 574 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
mbed_official 354:e67efb2aab0e 575 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
mbed_official 354:e67efb2aab0e 576 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
mbed_official 354:e67efb2aab0e 577 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
mbed_official 354:e67efb2aab0e 578 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
mbed_official 354:e67efb2aab0e 579 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
mbed_official 354:e67efb2aab0e 580 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
mbed_official 354:e67efb2aab0e 581 * bus mode interrupt
mbed_official 354:e67efb2aab0e 582 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
mbed_official 354:e67efb2aab0e 583 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
mbed_official 354:e67efb2aab0e 584 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
mbed_official 354:e67efb2aab0e 585 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
mbed_official 354:e67efb2aab0e 586 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
mbed_official 354:e67efb2aab0e 587 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
mbed_official 354:e67efb2aab0e 588 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
mbed_official 354:e67efb2aab0e 589 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
mbed_official 354:e67efb2aab0e 590 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
mbed_official 354:e67efb2aab0e 591 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
mbed_official 354:e67efb2aab0e 592 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
mbed_official 354:e67efb2aab0e 593 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
mbed_official 354:e67efb2aab0e 594 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
mbed_official 354:e67efb2aab0e 595 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
mbed_official 354:e67efb2aab0e 596 * @retval None
mbed_official 354:e67efb2aab0e 597 */
mbed_official 354:e67efb2aab0e 598 #define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
mbed_official 354:e67efb2aab0e 599
mbed_official 354:e67efb2aab0e 600 /**
mbed_official 354:e67efb2aab0e 601 * @brief Disable the SDIO device interrupt.
mbed_official 354:e67efb2aab0e 602 * @param __INSTANCE__ : Pointer to SDIO register base
mbed_official 354:e67efb2aab0e 603 * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
mbed_official 354:e67efb2aab0e 604 * This parameter can be one or a combination of the following values:
mbed_official 354:e67efb2aab0e 605 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
mbed_official 354:e67efb2aab0e 606 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
mbed_official 354:e67efb2aab0e 607 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
mbed_official 354:e67efb2aab0e 608 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
mbed_official 354:e67efb2aab0e 609 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
mbed_official 354:e67efb2aab0e 610 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
mbed_official 354:e67efb2aab0e 611 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
mbed_official 354:e67efb2aab0e 612 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
mbed_official 354:e67efb2aab0e 613 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
mbed_official 354:e67efb2aab0e 614 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
mbed_official 354:e67efb2aab0e 615 * bus mode interrupt
mbed_official 354:e67efb2aab0e 616 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
mbed_official 354:e67efb2aab0e 617 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
mbed_official 354:e67efb2aab0e 618 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
mbed_official 354:e67efb2aab0e 619 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
mbed_official 354:e67efb2aab0e 620 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
mbed_official 354:e67efb2aab0e 621 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
mbed_official 354:e67efb2aab0e 622 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
mbed_official 354:e67efb2aab0e 623 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
mbed_official 354:e67efb2aab0e 624 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
mbed_official 354:e67efb2aab0e 625 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
mbed_official 354:e67efb2aab0e 626 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
mbed_official 354:e67efb2aab0e 627 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
mbed_official 354:e67efb2aab0e 628 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
mbed_official 354:e67efb2aab0e 629 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
mbed_official 354:e67efb2aab0e 630 * @retval None
mbed_official 354:e67efb2aab0e 631 */
mbed_official 354:e67efb2aab0e 632 #define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
mbed_official 354:e67efb2aab0e 633
mbed_official 354:e67efb2aab0e 634 /**
mbed_official 354:e67efb2aab0e 635 * @brief Checks whether the specified SDIO flag is set or not.
mbed_official 354:e67efb2aab0e 636 * @param __INSTANCE__ : Pointer to SDIO register base
mbed_official 354:e67efb2aab0e 637 * @param __FLAG__: specifies the flag to check.
mbed_official 354:e67efb2aab0e 638 * This parameter can be one of the following values:
mbed_official 354:e67efb2aab0e 639 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
mbed_official 354:e67efb2aab0e 640 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
mbed_official 354:e67efb2aab0e 641 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
mbed_official 354:e67efb2aab0e 642 * @arg SDIO_FLAG_DTIMEOUT: Data timeout
mbed_official 354:e67efb2aab0e 643 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
mbed_official 354:e67efb2aab0e 644 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
mbed_official 354:e67efb2aab0e 645 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
mbed_official 354:e67efb2aab0e 646 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
mbed_official 354:e67efb2aab0e 647 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
mbed_official 354:e67efb2aab0e 648 * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
mbed_official 354:e67efb2aab0e 649 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
mbed_official 354:e67efb2aab0e 650 * @arg SDIO_FLAG_CMDACT: Command transfer in progress
mbed_official 354:e67efb2aab0e 651 * @arg SDIO_FLAG_TXACT: Data transmit in progress
mbed_official 354:e67efb2aab0e 652 * @arg SDIO_FLAG_RXACT: Data receive in progress
mbed_official 354:e67efb2aab0e 653 * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
mbed_official 354:e67efb2aab0e 654 * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
mbed_official 354:e67efb2aab0e 655 * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
mbed_official 354:e67efb2aab0e 656 * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
mbed_official 354:e67efb2aab0e 657 * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
mbed_official 354:e67efb2aab0e 658 * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
mbed_official 354:e67efb2aab0e 659 * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
mbed_official 354:e67efb2aab0e 660 * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
mbed_official 354:e67efb2aab0e 661 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
mbed_official 354:e67efb2aab0e 662 * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
mbed_official 354:e67efb2aab0e 663 * @retval The new state of SDIO_FLAG (SET or RESET).
mbed_official 354:e67efb2aab0e 664 */
mbed_official 354:e67efb2aab0e 665 #define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
mbed_official 354:e67efb2aab0e 666
mbed_official 354:e67efb2aab0e 667
mbed_official 354:e67efb2aab0e 668 /**
mbed_official 354:e67efb2aab0e 669 * @brief Clears the SDIO pending flags.
mbed_official 354:e67efb2aab0e 670 * @param __INSTANCE__ : Pointer to SDIO register base
mbed_official 354:e67efb2aab0e 671 * @param __FLAG__: specifies the flag to clear.
mbed_official 354:e67efb2aab0e 672 * This parameter can be one or a combination of the following values:
mbed_official 354:e67efb2aab0e 673 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
mbed_official 354:e67efb2aab0e 674 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
mbed_official 354:e67efb2aab0e 675 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
mbed_official 354:e67efb2aab0e 676 * @arg SDIO_FLAG_DTIMEOUT: Data timeout
mbed_official 354:e67efb2aab0e 677 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
mbed_official 354:e67efb2aab0e 678 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
mbed_official 354:e67efb2aab0e 679 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
mbed_official 354:e67efb2aab0e 680 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
mbed_official 354:e67efb2aab0e 681 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
mbed_official 354:e67efb2aab0e 682 * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
mbed_official 354:e67efb2aab0e 683 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
mbed_official 354:e67efb2aab0e 684 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
mbed_official 354:e67efb2aab0e 685 * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
mbed_official 354:e67efb2aab0e 686 * @retval None
mbed_official 354:e67efb2aab0e 687 */
mbed_official 354:e67efb2aab0e 688 #define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
mbed_official 354:e67efb2aab0e 689
mbed_official 354:e67efb2aab0e 690 /**
mbed_official 354:e67efb2aab0e 691 * @brief Checks whether the specified SDIO interrupt has occurred or not.
mbed_official 354:e67efb2aab0e 692 * @param __INSTANCE__ : Pointer to SDIO register base
mbed_official 354:e67efb2aab0e 693 * @param __INTERRUPT__: specifies the SDIO interrupt source to check.
mbed_official 354:e67efb2aab0e 694 * This parameter can be one of the following values:
mbed_official 354:e67efb2aab0e 695 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
mbed_official 354:e67efb2aab0e 696 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
mbed_official 354:e67efb2aab0e 697 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
mbed_official 354:e67efb2aab0e 698 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
mbed_official 354:e67efb2aab0e 699 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
mbed_official 354:e67efb2aab0e 700 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
mbed_official 354:e67efb2aab0e 701 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
mbed_official 354:e67efb2aab0e 702 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
mbed_official 354:e67efb2aab0e 703 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
mbed_official 354:e67efb2aab0e 704 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
mbed_official 354:e67efb2aab0e 705 * bus mode interrupt
mbed_official 354:e67efb2aab0e 706 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
mbed_official 354:e67efb2aab0e 707 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
mbed_official 354:e67efb2aab0e 708 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
mbed_official 354:e67efb2aab0e 709 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
mbed_official 354:e67efb2aab0e 710 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
mbed_official 354:e67efb2aab0e 711 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
mbed_official 354:e67efb2aab0e 712 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
mbed_official 354:e67efb2aab0e 713 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
mbed_official 354:e67efb2aab0e 714 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
mbed_official 354:e67efb2aab0e 715 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
mbed_official 354:e67efb2aab0e 716 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
mbed_official 354:e67efb2aab0e 717 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
mbed_official 354:e67efb2aab0e 718 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
mbed_official 354:e67efb2aab0e 719 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
mbed_official 354:e67efb2aab0e 720 * @retval The new state of SDIO_IT (SET or RESET).
mbed_official 354:e67efb2aab0e 721 */
mbed_official 354:e67efb2aab0e 722 #define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
mbed_official 354:e67efb2aab0e 723
mbed_official 354:e67efb2aab0e 724 /**
mbed_official 354:e67efb2aab0e 725 * @brief Clears the SDIO's interrupt pending bits.
mbed_official 354:e67efb2aab0e 726 * @param __INSTANCE__ : Pointer to SDIO register base
mbed_official 354:e67efb2aab0e 727 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
mbed_official 354:e67efb2aab0e 728 * This parameter can be one or a combination of the following values:
mbed_official 354:e67efb2aab0e 729 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
mbed_official 354:e67efb2aab0e 730 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
mbed_official 354:e67efb2aab0e 731 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
mbed_official 354:e67efb2aab0e 732 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
mbed_official 354:e67efb2aab0e 733 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
mbed_official 354:e67efb2aab0e 734 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
mbed_official 354:e67efb2aab0e 735 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
mbed_official 354:e67efb2aab0e 736 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
mbed_official 354:e67efb2aab0e 737 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
mbed_official 354:e67efb2aab0e 738 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
mbed_official 354:e67efb2aab0e 739 * bus mode interrupt
mbed_official 354:e67efb2aab0e 740 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
mbed_official 354:e67efb2aab0e 741 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
mbed_official 354:e67efb2aab0e 742 * @retval None
mbed_official 354:e67efb2aab0e 743 */
mbed_official 354:e67efb2aab0e 744 #define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
mbed_official 354:e67efb2aab0e 745
mbed_official 354:e67efb2aab0e 746 /**
mbed_official 354:e67efb2aab0e 747 * @brief Enable Start the SD I/O Read Wait operation.
mbed_official 354:e67efb2aab0e 748 * @retval None
mbed_official 354:e67efb2aab0e 749 */
mbed_official 354:e67efb2aab0e 750 #define __SDIO_START_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
mbed_official 354:e67efb2aab0e 751
mbed_official 354:e67efb2aab0e 752 /**
mbed_official 354:e67efb2aab0e 753 * @brief Disable Start the SD I/O Read Wait operations.
mbed_official 354:e67efb2aab0e 754 * @retval None
mbed_official 354:e67efb2aab0e 755 */
mbed_official 354:e67efb2aab0e 756 #define __SDIO_START_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
mbed_official 354:e67efb2aab0e 757
mbed_official 354:e67efb2aab0e 758 /**
mbed_official 354:e67efb2aab0e 759 * @brief Enable Start the SD I/O Read Wait operation.
mbed_official 354:e67efb2aab0e 760 * @retval None
mbed_official 354:e67efb2aab0e 761 */
mbed_official 354:e67efb2aab0e 762 #define __SDIO_STOP_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
mbed_official 354:e67efb2aab0e 763
mbed_official 354:e67efb2aab0e 764 /**
mbed_official 354:e67efb2aab0e 765 * @brief Disable Stop the SD I/O Read Wait operations.
mbed_official 354:e67efb2aab0e 766 * @retval None
mbed_official 354:e67efb2aab0e 767 */
mbed_official 354:e67efb2aab0e 768 #define __SDIO_STOP_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
mbed_official 354:e67efb2aab0e 769
mbed_official 354:e67efb2aab0e 770 /**
mbed_official 354:e67efb2aab0e 771 * @brief Enable the SD I/O Mode Operation.
mbed_official 354:e67efb2aab0e 772 * @retval None
mbed_official 354:e67efb2aab0e 773 */
mbed_official 354:e67efb2aab0e 774 #define __SDIO_OPERATION_ENABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
mbed_official 354:e67efb2aab0e 775
mbed_official 354:e67efb2aab0e 776 /**
mbed_official 354:e67efb2aab0e 777 * @brief Disable the SD I/O Mode Operation.
mbed_official 354:e67efb2aab0e 778 * @retval None
mbed_official 354:e67efb2aab0e 779 */
mbed_official 354:e67efb2aab0e 780 #define __SDIO_OPERATION_DISABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
mbed_official 354:e67efb2aab0e 781
mbed_official 354:e67efb2aab0e 782 /**
mbed_official 354:e67efb2aab0e 783 * @brief Enable the SD I/O Suspend command sending.
mbed_official 354:e67efb2aab0e 784 * @retval None
mbed_official 354:e67efb2aab0e 785 */
mbed_official 354:e67efb2aab0e 786 #define __SDIO_SUSPEND_CMD_ENABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
mbed_official 354:e67efb2aab0e 787
mbed_official 354:e67efb2aab0e 788 /**
mbed_official 354:e67efb2aab0e 789 * @brief Disable the SD I/O Suspend command sending.
mbed_official 354:e67efb2aab0e 790 * @retval None
mbed_official 354:e67efb2aab0e 791 */
mbed_official 354:e67efb2aab0e 792 #define __SDIO_SUSPEND_CMD_DISABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
mbed_official 354:e67efb2aab0e 793
mbed_official 354:e67efb2aab0e 794 /**
mbed_official 354:e67efb2aab0e 795 * @brief Enable the command completion signal.
mbed_official 354:e67efb2aab0e 796 * @retval None
mbed_official 354:e67efb2aab0e 797 */
mbed_official 354:e67efb2aab0e 798 #define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
mbed_official 354:e67efb2aab0e 799
mbed_official 354:e67efb2aab0e 800 /**
mbed_official 354:e67efb2aab0e 801 * @brief Disable the command completion signal.
mbed_official 354:e67efb2aab0e 802 * @retval None
mbed_official 354:e67efb2aab0e 803 */
mbed_official 354:e67efb2aab0e 804 #define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
mbed_official 354:e67efb2aab0e 805
mbed_official 354:e67efb2aab0e 806 /**
mbed_official 354:e67efb2aab0e 807 * @brief Enable the CE-ATA interrupt.
mbed_official 354:e67efb2aab0e 808 * @retval None
mbed_official 354:e67efb2aab0e 809 */
mbed_official 354:e67efb2aab0e 810 #define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0)
mbed_official 354:e67efb2aab0e 811
mbed_official 354:e67efb2aab0e 812 /**
mbed_official 354:e67efb2aab0e 813 * @brief Disable the CE-ATA interrupt.
mbed_official 354:e67efb2aab0e 814 * @retval None
mbed_official 354:e67efb2aab0e 815 */
mbed_official 354:e67efb2aab0e 816 #define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1)
mbed_official 354:e67efb2aab0e 817
mbed_official 354:e67efb2aab0e 818 /**
mbed_official 354:e67efb2aab0e 819 * @brief Enable send CE-ATA command (CMD61).
mbed_official 354:e67efb2aab0e 820 * @retval None
mbed_official 354:e67efb2aab0e 821 */
mbed_official 354:e67efb2aab0e 822 #define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
mbed_official 354:e67efb2aab0e 823
mbed_official 354:e67efb2aab0e 824 /**
mbed_official 354:e67efb2aab0e 825 * @brief Disable send CE-ATA command (CMD61).
mbed_official 354:e67efb2aab0e 826 * @retval None
mbed_official 354:e67efb2aab0e 827 */
mbed_official 354:e67efb2aab0e 828 #define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
mbed_official 354:e67efb2aab0e 829
mbed_official 354:e67efb2aab0e 830 /**
mbed_official 354:e67efb2aab0e 831 * @}
mbed_official 354:e67efb2aab0e 832 */
mbed_official 354:e67efb2aab0e 833
mbed_official 354:e67efb2aab0e 834 /**
mbed_official 354:e67efb2aab0e 835 * @}
mbed_official 354:e67efb2aab0e 836 */
mbed_official 354:e67efb2aab0e 837
mbed_official 354:e67efb2aab0e 838 /* Exported functions --------------------------------------------------------*/
mbed_official 354:e67efb2aab0e 839 /** @addtogroup SDMMC_LL_Exported_Functions
mbed_official 354:e67efb2aab0e 840 * @{
mbed_official 354:e67efb2aab0e 841 */
mbed_official 354:e67efb2aab0e 842
mbed_official 354:e67efb2aab0e 843 /* Initialization/de-initialization functions **********************************/
mbed_official 354:e67efb2aab0e 844 /** @addtogroup HAL_SDMMC_LL_Group1
mbed_official 354:e67efb2aab0e 845 * @{
mbed_official 354:e67efb2aab0e 846 */
mbed_official 354:e67efb2aab0e 847 HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
mbed_official 354:e67efb2aab0e 848 /**
mbed_official 354:e67efb2aab0e 849 * @}
mbed_official 354:e67efb2aab0e 850 */
mbed_official 354:e67efb2aab0e 851
mbed_official 354:e67efb2aab0e 852 /* I/O operation functions *****************************************************/
mbed_official 354:e67efb2aab0e 853 /** @addtogroup HAL_SDMMC_LL_Group2
mbed_official 354:e67efb2aab0e 854 * @{
mbed_official 354:e67efb2aab0e 855 */
mbed_official 354:e67efb2aab0e 856 /* Blocking mode: Polling */
mbed_official 354:e67efb2aab0e 857 uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
mbed_official 354:e67efb2aab0e 858 HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
mbed_official 354:e67efb2aab0e 859 /**
mbed_official 354:e67efb2aab0e 860 * @}
mbed_official 354:e67efb2aab0e 861 */
mbed_official 354:e67efb2aab0e 862
mbed_official 354:e67efb2aab0e 863 /* Peripheral Control functions ************************************************/
mbed_official 354:e67efb2aab0e 864 /** @addtogroup HAL_SDMMC_LL_Group3
mbed_official 354:e67efb2aab0e 865 * @{
mbed_official 354:e67efb2aab0e 866 */
mbed_official 354:e67efb2aab0e 867 HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
mbed_official 354:e67efb2aab0e 868 HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
mbed_official 354:e67efb2aab0e 869 uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
mbed_official 354:e67efb2aab0e 870
mbed_official 354:e67efb2aab0e 871 /* Command path state machine (CPSM) management functions */
mbed_official 354:e67efb2aab0e 872 HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
mbed_official 354:e67efb2aab0e 873 uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
mbed_official 354:e67efb2aab0e 874 uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
mbed_official 354:e67efb2aab0e 875
mbed_official 354:e67efb2aab0e 876 /* Data path state machine (DPSM) management functions */
mbed_official 354:e67efb2aab0e 877 HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct);
mbed_official 354:e67efb2aab0e 878 uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
mbed_official 354:e67efb2aab0e 879 uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
mbed_official 354:e67efb2aab0e 880
mbed_official 354:e67efb2aab0e 881 /* SDIO IO Cards mode management functions */
mbed_official 354:e67efb2aab0e 882 HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
mbed_official 354:e67efb2aab0e 883 /**
mbed_official 354:e67efb2aab0e 884 * @}
mbed_official 354:e67efb2aab0e 885 */
mbed_official 354:e67efb2aab0e 886
mbed_official 354:e67efb2aab0e 887 /**
mbed_official 354:e67efb2aab0e 888 * @}
mbed_official 354:e67efb2aab0e 889 */
mbed_official 354:e67efb2aab0e 890
mbed_official 354:e67efb2aab0e 891 /**
mbed_official 354:e67efb2aab0e 892 * @}
mbed_official 354:e67efb2aab0e 893 */
mbed_official 354:e67efb2aab0e 894
mbed_official 354:e67efb2aab0e 895 /**
mbed_official 354:e67efb2aab0e 896 * @}
mbed_official 354:e67efb2aab0e 897 */
mbed_official 354:e67efb2aab0e 898
mbed_official 354:e67efb2aab0e 899 #ifdef __cplusplus
mbed_official 354:e67efb2aab0e 900 }
mbed_official 354:e67efb2aab0e 901 #endif
mbed_official 354:e67efb2aab0e 902
mbed_official 354:e67efb2aab0e 903 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
mbed_official 354:e67efb2aab0e 904
mbed_official 354:e67efb2aab0e 905 #endif /* __STM32L1xx_LL_SD_H */
mbed_official 354:e67efb2aab0e 906
mbed_official 354:e67efb2aab0e 907 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/