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targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rcc.h@394:83f921546702, 2014-11-07 (annotated)

Committer:: mbed_official
Date:: Fri Nov 07 15:45:07 2014 +0000
Revision:: 394:83f921546702
Parent:: targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_hal_rcc.h@354:e67efb2aab0e

Synchronized with git revision aab52cb7ec5a665869e507dd988bbfd55b7e087e

Full URL: https://github.com/mbedmicro/mbed/commit/aab52cb7ec5a665869e507dd988bbfd55b7e087e/

Tests: Fix cpputest testrunner

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	354:e67efb2aab0e	1	/**
mbed_official	354:e67efb2aab0e	2	******************************************************************************
mbed_official	354:e67efb2aab0e	3	* @file stm32l1xx_hal_rcc.h
mbed_official	354:e67efb2aab0e	4	* @author MCD Application Team
mbed_official	354:e67efb2aab0e	5	* @version V1.0.0
mbed_official	354:e67efb2aab0e	6	* @date 5-September-2014
mbed_official	354:e67efb2aab0e	7	* @brief Header file of RCC HAL module.
mbed_official	354:e67efb2aab0e	8	******************************************************************************
mbed_official	354:e67efb2aab0e	9	* @attention
mbed_official	354:e67efb2aab0e	10	*
mbed_official	354:e67efb2aab0e	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	354:e67efb2aab0e	12	*
mbed_official	354:e67efb2aab0e	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	354:e67efb2aab0e	14	* are permitted provided that the following conditions are met:
mbed_official	354:e67efb2aab0e	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	354:e67efb2aab0e	16	* this list of conditions and the following disclaimer.
mbed_official	354:e67efb2aab0e	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	354:e67efb2aab0e	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	354:e67efb2aab0e	19	* and/or other materials provided with the distribution.
mbed_official	354:e67efb2aab0e	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	354:e67efb2aab0e	21	* may be used to endorse or promote products derived from this software
mbed_official	354:e67efb2aab0e	22	* without specific prior written permission.
mbed_official	354:e67efb2aab0e	23	*
mbed_official	354:e67efb2aab0e	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	354:e67efb2aab0e	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	354:e67efb2aab0e	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	354:e67efb2aab0e	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	354:e67efb2aab0e	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	354:e67efb2aab0e	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	354:e67efb2aab0e	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	354:e67efb2aab0e	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	354:e67efb2aab0e	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	354:e67efb2aab0e	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	354:e67efb2aab0e	34	*
mbed_official	354:e67efb2aab0e	35	******************************************************************************
mbed_official	354:e67efb2aab0e	36	*/
mbed_official	354:e67efb2aab0e	37
mbed_official	354:e67efb2aab0e	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	354:e67efb2aab0e	39	#ifndef __STM32L1xx_HAL_RCC_H
mbed_official	354:e67efb2aab0e	40	#define __STM32L1xx_HAL_RCC_H
mbed_official	354:e67efb2aab0e	41
mbed_official	354:e67efb2aab0e	42	#ifdef __cplusplus
mbed_official	354:e67efb2aab0e	43	extern "C" {
mbed_official	354:e67efb2aab0e	44	#endif
mbed_official	354:e67efb2aab0e	45
mbed_official	354:e67efb2aab0e	46	/* Includes ------------------------------------------------------------------*/
mbed_official	354:e67efb2aab0e	47	#include "stm32l1xx_hal_def.h"
mbed_official	354:e67efb2aab0e	48
mbed_official	354:e67efb2aab0e	49	/** @addtogroup STM32L1xx_HAL_Driver
mbed_official	354:e67efb2aab0e	50	* @{
mbed_official	354:e67efb2aab0e	51	*/
mbed_official	354:e67efb2aab0e	52
mbed_official	354:e67efb2aab0e	53	/** @addtogroup RCC
mbed_official	354:e67efb2aab0e	54	* @{
mbed_official	354:e67efb2aab0e	55	*/
mbed_official	354:e67efb2aab0e	56
mbed_official	354:e67efb2aab0e	57	/* Exported types ------------------------------------------------------------*/
mbed_official	354:e67efb2aab0e	58
mbed_official	354:e67efb2aab0e	59	/** @defgroup RCC_Exported_Types RCC Exported Types
mbed_official	354:e67efb2aab0e	60	* @{
mbed_official	354:e67efb2aab0e	61	*/
mbed_official	354:e67efb2aab0e	62
mbed_official	354:e67efb2aab0e	63	/**
mbed_official	354:e67efb2aab0e	64	* @brief RCC PLL configuration structure definition
mbed_official	354:e67efb2aab0e	65	*/
mbed_official	354:e67efb2aab0e	66	typedef struct
mbed_official	354:e67efb2aab0e	67	{
mbed_official	354:e67efb2aab0e	68	uint32_t PLLState; /*!< The new state of the PLL.
mbed_official	354:e67efb2aab0e	69	This parameter can be a value of @ref RCC_PLL_Config */
mbed_official	354:e67efb2aab0e	70
mbed_official	354:e67efb2aab0e	71	uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
mbed_official	354:e67efb2aab0e	72	This parameter must be a value of @ref RCC_PLL_Clock_Source */
mbed_official	354:e67efb2aab0e	73
mbed_official	354:e67efb2aab0e	74	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
mbed_official	354:e67efb2aab0e	75	This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
mbed_official	354:e67efb2aab0e	76
mbed_official	354:e67efb2aab0e	77	uint32_t PLLDIV; /*!< PLLDIV: Division factor for PLL VCO input clock
mbed_official	354:e67efb2aab0e	78	This parameter must be a value of @ref RCC_PLL_Division_Factor*/
mbed_official	354:e67efb2aab0e	79	} RCC_PLLInitTypeDef;
mbed_official	354:e67efb2aab0e	80
mbed_official	354:e67efb2aab0e	81	/**
mbed_official	354:e67efb2aab0e	82	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
mbed_official	354:e67efb2aab0e	83	*/
mbed_official	354:e67efb2aab0e	84	typedef struct
mbed_official	354:e67efb2aab0e	85	{
mbed_official	354:e67efb2aab0e	86	uint32_t OscillatorType; /*!< The oscillators to be configured.
mbed_official	354:e67efb2aab0e	87	This parameter can be a value of @ref RCC_Oscillator_Type */
mbed_official	354:e67efb2aab0e	88
mbed_official	354:e67efb2aab0e	89	uint32_t HSEState; /*!< The new state of the HSE.
mbed_official	354:e67efb2aab0e	90	This parameter can be a value of @ref RCC_HSE_Config */
mbed_official	354:e67efb2aab0e	91
mbed_official	354:e67efb2aab0e	92	uint32_t LSEState; /*!< The new state of the LSE.
mbed_official	354:e67efb2aab0e	93	This parameter can be a value of @ref RCC_LSE_Config */
mbed_official	354:e67efb2aab0e	94
mbed_official	354:e67efb2aab0e	95	uint32_t HSIState; /*!< The new state of the HSI.
mbed_official	354:e67efb2aab0e	96	This parameter can be a value of @ref RCC_HSI_Config */
mbed_official	354:e67efb2aab0e	97
mbed_official	354:e67efb2aab0e	98	uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
mbed_official	354:e67efb2aab0e	99	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
mbed_official	354:e67efb2aab0e	100
mbed_official	354:e67efb2aab0e	101	uint32_t LSIState; /*!< The new state of the LSI.
mbed_official	354:e67efb2aab0e	102	This parameter can be a value of @ref RCC_LSI_Config */
mbed_official	354:e67efb2aab0e	103
mbed_official	354:e67efb2aab0e	104	uint32_t MSIState; /*!< The new state of the MSI.
mbed_official	354:e67efb2aab0e	105	This parameter can be a value of @ref RCC_MSI_Config */
mbed_official	354:e67efb2aab0e	106
mbed_official	354:e67efb2aab0e	107	uint32_t MSICalibrationValue; /*!< The MSI calibration trimming value. (default is RCC_MSICALIBRATION_DEFAULT).
mbed_official	354:e67efb2aab0e	108	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
mbed_official	354:e67efb2aab0e	109
mbed_official	354:e67efb2aab0e	110	uint32_t MSIClockRange; /*!< The MSI frequency range.
mbed_official	354:e67efb2aab0e	111	This parameter can be a value of @ref RCC_MSI_Clock_Range */
mbed_official	354:e67efb2aab0e	112
mbed_official	354:e67efb2aab0e	113	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
mbed_official	354:e67efb2aab0e	114
mbed_official	354:e67efb2aab0e	115	} RCC_OscInitTypeDef;
mbed_official	354:e67efb2aab0e	116
mbed_official	354:e67efb2aab0e	117	/**
mbed_official	354:e67efb2aab0e	118	* @brief RCC System, AHB and APB busses clock configuration structure definition
mbed_official	354:e67efb2aab0e	119	*/
mbed_official	354:e67efb2aab0e	120	typedef struct
mbed_official	354:e67efb2aab0e	121	{
mbed_official	354:e67efb2aab0e	122	uint32_t ClockType; /*!< The clock to be configured.
mbed_official	354:e67efb2aab0e	123	This parameter can be a value of @ref RCC_System_Clock_Type */
mbed_official	354:e67efb2aab0e	124
mbed_official	354:e67efb2aab0e	125	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
mbed_official	354:e67efb2aab0e	126	This parameter can be a value of @ref RCC_System_Clock_Source */
mbed_official	354:e67efb2aab0e	127
mbed_official	354:e67efb2aab0e	128	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
mbed_official	354:e67efb2aab0e	129	This parameter can be a value of @ref RCC_AHB_Clock_Source */
mbed_official	354:e67efb2aab0e	130
mbed_official	354:e67efb2aab0e	131	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
mbed_official	354:e67efb2aab0e	132	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
mbed_official	354:e67efb2aab0e	133
mbed_official	354:e67efb2aab0e	134	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
mbed_official	354:e67efb2aab0e	135	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
mbed_official	354:e67efb2aab0e	136
mbed_official	354:e67efb2aab0e	137	} RCC_ClkInitTypeDef;
mbed_official	354:e67efb2aab0e	138
mbed_official	354:e67efb2aab0e	139	/**
mbed_official	354:e67efb2aab0e	140	* @}
mbed_official	354:e67efb2aab0e	141	*/
mbed_official	354:e67efb2aab0e	142
mbed_official	354:e67efb2aab0e	143	/* Exported constants --------------------------------------------------------*/
mbed_official	354:e67efb2aab0e	144	/** @defgroup RCC_Exported_Constants RCC Exported Constants
mbed_official	354:e67efb2aab0e	145	* @{
mbed_official	354:e67efb2aab0e	146	*/
mbed_official	354:e67efb2aab0e	147	#define DBP_TIMEOUT_VALUE ((uint32_t)100)
mbed_official	354:e67efb2aab0e	148	#define LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
mbed_official	354:e67efb2aab0e	149
mbed_official	354:e67efb2aab0e	150	/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
mbed_official	354:e67efb2aab0e	151	* @brief RCC registers bit address in the alias region
mbed_official	354:e67efb2aab0e	152	* @{
mbed_official	354:e67efb2aab0e	153	*/
mbed_official	354:e67efb2aab0e	154	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
mbed_official	354:e67efb2aab0e	155	#define RCC_CR_OFFSET 0x00
mbed_official	354:e67efb2aab0e	156	#define RCC_CFGR_OFFSET 0x08
mbed_official	354:e67efb2aab0e	157	#define RCC_CIR_OFFSET 0x0C
mbed_official	354:e67efb2aab0e	158	#define RCC_CSR_OFFSET 0x34
mbed_official	354:e67efb2aab0e	159	#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
mbed_official	354:e67efb2aab0e	160	#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
mbed_official	354:e67efb2aab0e	161	#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
mbed_official	354:e67efb2aab0e	162	#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
mbed_official	354:e67efb2aab0e	163
mbed_official	354:e67efb2aab0e	164	/* --- CR Register ---*/
mbed_official	354:e67efb2aab0e	165	/* Alias word address of HSION bit */
mbed_official	354:e67efb2aab0e	166	#define HSION_BITNUMBER POSITION_VAL(RCC_CR_HSION)
mbed_official	354:e67efb2aab0e	167	#define CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (HSION_BITNUMBER * 4)))
mbed_official	354:e67efb2aab0e	168	/* Alias word address of MSION bit */
mbed_official	354:e67efb2aab0e	169	#define MSION_BITNUMBER POSITION_VAL(RCC_CR_MSION)
mbed_official	354:e67efb2aab0e	170	#define CR_MSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (MSION_BITNUMBER * 4)))
mbed_official	354:e67efb2aab0e	171	/* Alias word address of HSEON bit */
mbed_official	354:e67efb2aab0e	172	#define HSEON_BITNUMBER POSITION_VAL(RCC_CR_HSEON)
mbed_official	354:e67efb2aab0e	173	#define CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (HSEON_BITNUMBER * 4)))
mbed_official	354:e67efb2aab0e	174	/* Alias word address of CSSON bit */
mbed_official	354:e67efb2aab0e	175	#define CSSON_BITNUMBER POSITION_VAL(RCC_CR_CSSON)
mbed_official	354:e67efb2aab0e	176	#define CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (CSSON_BITNUMBER * 4)))
mbed_official	354:e67efb2aab0e	177	/* Alias word address of PLLON bit */
mbed_official	354:e67efb2aab0e	178	#define PLLON_BITNUMBER POSITION_VAL(RCC_CR_PLLON)
mbed_official	354:e67efb2aab0e	179	#define CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLLON_BITNUMBER * 4)))
mbed_official	354:e67efb2aab0e	180
mbed_official	354:e67efb2aab0e	181	/* --- CSR Register ---*/
mbed_official	354:e67efb2aab0e	182	/* Alias word address of LSION bit */
mbed_official	354:e67efb2aab0e	183	#define LSION_BITNUMBER POSITION_VAL(RCC_CSR_LSION)
mbed_official	354:e67efb2aab0e	184	#define CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSION_BITNUMBER * 4)))
mbed_official	354:e67efb2aab0e	185
mbed_official	354:e67efb2aab0e	186	/* Alias word address of LSEON bit */
mbed_official	354:e67efb2aab0e	187	#define LSEON_BITNUMBER POSITION_VAL(RCC_CSR_LSEON)
mbed_official	354:e67efb2aab0e	188	#define CSR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSEON_BITNUMBER * 4)))
mbed_official	354:e67efb2aab0e	189
mbed_official	354:e67efb2aab0e	190	/* Alias word address of LSEON bit */
mbed_official	354:e67efb2aab0e	191	#define LSEBYP_BITNUMBER POSITION_VAL(RCC_CSR_LSEBYP)
mbed_official	354:e67efb2aab0e	192	#define CSR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSEBYP_BITNUMBER * 4)))
mbed_official	354:e67efb2aab0e	193
mbed_official	354:e67efb2aab0e	194	/* Alias word address of RTCEN bit */
mbed_official	354:e67efb2aab0e	195	#define RTCEN_BITNUMBER POSITION_VAL(RCC_CSR_RTCEN)
mbed_official	354:e67efb2aab0e	196	#define CSR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RTCEN_BITNUMBER * 4)))
mbed_official	354:e67efb2aab0e	197
mbed_official	354:e67efb2aab0e	198	/* Alias word address of RTCRST bit */
mbed_official	354:e67efb2aab0e	199	#define RTCRST_BITNUMBER POSITION_VAL(RCC_CSR_RTCRST)
mbed_official	354:e67efb2aab0e	200	#define CSR_RTCRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RTCRST_BITNUMBER * 4)))
mbed_official	354:e67efb2aab0e	201
mbed_official	354:e67efb2aab0e	202	/* CR register byte 2 (Bits[23:16]) base address */
mbed_official	354:e67efb2aab0e	203	#define CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02))
mbed_official	354:e67efb2aab0e	204
mbed_official	354:e67efb2aab0e	205	/* CIR register byte 1 (Bits[15:8]) base address */
mbed_official	354:e67efb2aab0e	206	#define CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01))
mbed_official	354:e67efb2aab0e	207
mbed_official	354:e67efb2aab0e	208	/* CIR register byte 2 (Bits[23:16]) base address */
mbed_official	354:e67efb2aab0e	209	#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02))
mbed_official	354:e67efb2aab0e	210
mbed_official	354:e67efb2aab0e	211	/**
mbed_official	354:e67efb2aab0e	212	* @}
mbed_official	354:e67efb2aab0e	213	*/
mbed_official	354:e67efb2aab0e	214
mbed_official	354:e67efb2aab0e	215	/** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source
mbed_official	354:e67efb2aab0e	216	* @{
mbed_official	354:e67efb2aab0e	217	*/
mbed_official	354:e67efb2aab0e	218
mbed_official	354:e67efb2aab0e	219	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI
mbed_official	354:e67efb2aab0e	220	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE
mbed_official	354:e67efb2aab0e	221
mbed_official	354:e67efb2aab0e	222	#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) \|\| \
mbed_official	354:e67efb2aab0e	223	((__SOURCE__) == RCC_PLLSOURCE_HSE))
mbed_official	354:e67efb2aab0e	224	/**
mbed_official	354:e67efb2aab0e	225	* @}
mbed_official	354:e67efb2aab0e	226	*/
mbed_official	354:e67efb2aab0e	227
mbed_official	354:e67efb2aab0e	228	/** @defgroup RCC_Oscillator_Type RCC Oscillator Type
mbed_official	354:e67efb2aab0e	229	* @{
mbed_official	354:e67efb2aab0e	230	*/
mbed_official	354:e67efb2aab0e	231	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
mbed_official	354:e67efb2aab0e	232	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
mbed_official	354:e67efb2aab0e	233	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
mbed_official	354:e67efb2aab0e	234	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
mbed_official	354:e67efb2aab0e	235	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
mbed_official	354:e67efb2aab0e	236	#define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010)
mbed_official	354:e67efb2aab0e	237
mbed_official	354:e67efb2aab0e	238	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) \|\| \
mbed_official	354:e67efb2aab0e	239	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
mbed_official	354:e67efb2aab0e	240	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
mbed_official	354:e67efb2aab0e	241	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
mbed_official	354:e67efb2aab0e	242	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) \|\| \
mbed_official	354:e67efb2aab0e	243	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI))
mbed_official	354:e67efb2aab0e	244	/**
mbed_official	354:e67efb2aab0e	245	* @}
mbed_official	354:e67efb2aab0e	246	*/
mbed_official	354:e67efb2aab0e	247
mbed_official	354:e67efb2aab0e	248	/** @defgroup RCC_HSE_Config RCC HSE Config
mbed_official	354:e67efb2aab0e	249	* @{
mbed_official	354:e67efb2aab0e	250	*/
mbed_official	354:e67efb2aab0e	251	#define RCC_HSE_OFF ((uint32_t)0x00000000)
mbed_official	354:e67efb2aab0e	252	#define RCC_HSE_ON ((uint32_t)0x00000001)
mbed_official	354:e67efb2aab0e	253	#define RCC_HSE_BYPASS ((uint32_t)0x00000005)
mbed_official	354:e67efb2aab0e	254
mbed_official	354:e67efb2aab0e	255	#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) \|\| ((__HSE__) == RCC_HSE_ON) \|\| \
mbed_official	354:e67efb2aab0e	256	((__HSE__) == RCC_HSE_BYPASS))
mbed_official	354:e67efb2aab0e	257	/**
mbed_official	354:e67efb2aab0e	258	* @}
mbed_official	354:e67efb2aab0e	259	*/
mbed_official	354:e67efb2aab0e	260
mbed_official	354:e67efb2aab0e	261	/** @defgroup RCC_LSE_Config RCC LSE Config
mbed_official	354:e67efb2aab0e	262	* @{
mbed_official	354:e67efb2aab0e	263	*/
mbed_official	354:e67efb2aab0e	264	#define RCC_LSE_OFF ((uint32_t)0x00000000)
mbed_official	354:e67efb2aab0e	265	#define RCC_LSE_ON ((uint32_t)0x00000001)
mbed_official	354:e67efb2aab0e	266	#define RCC_LSE_BYPASS ((uint32_t)0x00000005)
mbed_official	354:e67efb2aab0e	267
mbed_official	354:e67efb2aab0e	268	#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) \|\| ((__LSE__) == RCC_LSE_ON) \|\| \
mbed_official	354:e67efb2aab0e	269	((__LSE__) == RCC_LSE_BYPASS))
mbed_official	354:e67efb2aab0e	270	/**
mbed_official	354:e67efb2aab0e	271	* @}
mbed_official	354:e67efb2aab0e	272	*/
mbed_official	354:e67efb2aab0e	273
mbed_official	354:e67efb2aab0e	274	/** @defgroup RCC_HSI_Config RCC HSI Config
mbed_official	354:e67efb2aab0e	275	* @{
mbed_official	354:e67efb2aab0e	276	*/
mbed_official	354:e67efb2aab0e	277	#define RCC_HSI_OFF ((uint32_t)0x00000000)
mbed_official	354:e67efb2aab0e	278	#define RCC_HSI_ON ((uint32_t)0x00000001)
mbed_official	354:e67efb2aab0e	279
mbed_official	354:e67efb2aab0e	280	#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON))
mbed_official	354:e67efb2aab0e	281
mbed_official	354:e67efb2aab0e	282	#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
mbed_official	354:e67efb2aab0e	283
mbed_official	354:e67efb2aab0e	284	#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
mbed_official	354:e67efb2aab0e	285	/**
mbed_official	354:e67efb2aab0e	286	* @}
mbed_official	354:e67efb2aab0e	287	*/
mbed_official	354:e67efb2aab0e	288
mbed_official	354:e67efb2aab0e	289	/** @defgroup RCC_MSI_Clock_Range RCC MSI Clock Range
mbed_official	354:e67efb2aab0e	290	* @{
mbed_official	354:e67efb2aab0e	291	*/
mbed_official	354:e67efb2aab0e	292
mbed_official	354:e67efb2aab0e	293	#define RCC_MSIRANGE_0 ((uint32_t)RCC_ICSCR_MSIRANGE_0) /!< MSI = 65.536 KHz /
mbed_official	354:e67efb2aab0e	294	#define RCC_MSIRANGE_1 ((uint32_t)RCC_ICSCR_MSIRANGE_1) /!< MSI = 131.072 KHz /
mbed_official	354:e67efb2aab0e	295	#define RCC_MSIRANGE_2 ((uint32_t)RCC_ICSCR_MSIRANGE_2) /!< MSI = 262.144 KHz /
mbed_official	354:e67efb2aab0e	296	#define RCC_MSIRANGE_3 ((uint32_t)RCC_ICSCR_MSIRANGE_3) /!< MSI = 524.288 KHz /
mbed_official	354:e67efb2aab0e	297	#define RCC_MSIRANGE_4 ((uint32_t)RCC_ICSCR_MSIRANGE_4) /!< MSI = 1.048 MHz /
mbed_official	354:e67efb2aab0e	298	#define RCC_MSIRANGE_5 ((uint32_t)RCC_ICSCR_MSIRANGE_5) /!< MSI = 2.097 MHz /
mbed_official	354:e67efb2aab0e	299	#define RCC_MSIRANGE_6 ((uint32_t)RCC_ICSCR_MSIRANGE_6) /!< MSI = 4.194 MHz /
mbed_official	354:e67efb2aab0e	300
mbed_official	354:e67efb2aab0e	301	#define IS_RCC_MSIRANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) \|\| \
mbed_official	354:e67efb2aab0e	302	((__RANGE__) == RCC_MSIRANGE_1) \|\| \
mbed_official	354:e67efb2aab0e	303	((__RANGE__) == RCC_MSIRANGE_2) \|\| \
mbed_official	354:e67efb2aab0e	304	((__RANGE__) == RCC_MSIRANGE_3) \|\| \
mbed_official	354:e67efb2aab0e	305	((__RANGE__) == RCC_MSIRANGE_4) \|\| \
mbed_official	354:e67efb2aab0e	306	((__RANGE__) == RCC_MSIRANGE_5) \|\| \
mbed_official	354:e67efb2aab0e	307	((__RANGE__) == RCC_MSIRANGE_6))
mbed_official	354:e67efb2aab0e	308	/**
mbed_official	354:e67efb2aab0e	309	* @}
mbed_official	354:e67efb2aab0e	310	*/
mbed_official	354:e67efb2aab0e	311
mbed_official	354:e67efb2aab0e	312	/** @defgroup RCC_LSI_Config RCC LSI Config
mbed_official	354:e67efb2aab0e	313	* @{
mbed_official	354:e67efb2aab0e	314	*/
mbed_official	354:e67efb2aab0e	315	#define RCC_LSI_OFF ((uint32_t)0x00000000)
mbed_official	354:e67efb2aab0e	316	#define RCC_LSI_ON ((uint32_t)0x00000001)
mbed_official	354:e67efb2aab0e	317
mbed_official	354:e67efb2aab0e	318	#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) \|\| ((__LSI__) == RCC_LSI_ON))
mbed_official	354:e67efb2aab0e	319	/**
mbed_official	354:e67efb2aab0e	320	* @}
mbed_official	354:e67efb2aab0e	321	*/
mbed_official	354:e67efb2aab0e	322
mbed_official	354:e67efb2aab0e	323
mbed_official	354:e67efb2aab0e	324	/** @defgroup RCC_MSI_Config RCC MSI Config
mbed_official	354:e67efb2aab0e	325	* @{
mbed_official	354:e67efb2aab0e	326	*/
mbed_official	354:e67efb2aab0e	327	#define RCC_MSI_OFF ((uint32_t)0x00000000)
mbed_official	354:e67efb2aab0e	328	#define RCC_MSI_ON ((uint32_t)0x00000001)
mbed_official	354:e67efb2aab0e	329
mbed_official	354:e67efb2aab0e	330	#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) \|\| ((__MSI__) == RCC_MSI_ON))
mbed_official	354:e67efb2aab0e	331
mbed_official	354:e67efb2aab0e	332	#define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0x00) /* Default MSI calibration trimming value */
mbed_official	354:e67efb2aab0e	333
mbed_official	354:e67efb2aab0e	334	/**
mbed_official	354:e67efb2aab0e	335	* @}
mbed_official	354:e67efb2aab0e	336	*/
mbed_official	354:e67efb2aab0e	337
mbed_official	354:e67efb2aab0e	338	/** @defgroup RCC_PLL_Config RCC PLL Config
mbed_official	354:e67efb2aab0e	339	* @{
mbed_official	354:e67efb2aab0e	340	*/
mbed_official	354:e67efb2aab0e	341	#define RCC_PLL_NONE ((uint32_t)0x00000000)
mbed_official	354:e67efb2aab0e	342	#define RCC_PLL_OFF ((uint32_t)0x00000001)
mbed_official	354:e67efb2aab0e	343	#define RCC_PLL_ON ((uint32_t)0x00000002)
mbed_official	354:e67efb2aab0e	344
mbed_official	354:e67efb2aab0e	345	#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) \|\| ((__PLL__) == RCC_PLL_OFF) \|\| \
mbed_official	354:e67efb2aab0e	346	((__PLL__) == RCC_PLL_ON))
mbed_official	354:e67efb2aab0e	347	/**
mbed_official	354:e67efb2aab0e	348	* @}
mbed_official	354:e67efb2aab0e	349	*/
mbed_official	354:e67efb2aab0e	350
mbed_official	354:e67efb2aab0e	351	/** @defgroup RCC_PLL_Division_Factor RCC PLL Division Factor
mbed_official	354:e67efb2aab0e	352	* @{
mbed_official	354:e67efb2aab0e	353	*/
mbed_official	354:e67efb2aab0e	354
mbed_official	354:e67efb2aab0e	355	#define RCC_PLL_DIV2 RCC_CFGR_PLLDIV2
mbed_official	354:e67efb2aab0e	356	#define RCC_PLL_DIV3 RCC_CFGR_PLLDIV3
mbed_official	354:e67efb2aab0e	357	#define RCC_PLL_DIV4 RCC_CFGR_PLLDIV4
mbed_official	354:e67efb2aab0e	358
mbed_official	354:e67efb2aab0e	359	#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) \|\| \
mbed_official	354:e67efb2aab0e	360	((__DIV__) == RCC_PLL_DIV3) \|\| ((__DIV__) == RCC_PLL_DIV4))
mbed_official	354:e67efb2aab0e	361
mbed_official	354:e67efb2aab0e	362	/**
mbed_official	354:e67efb2aab0e	363	* @}
mbed_official	354:e67efb2aab0e	364	*/
mbed_official	354:e67efb2aab0e	365
mbed_official	354:e67efb2aab0e	366	/** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor
mbed_official	354:e67efb2aab0e	367	* @{
mbed_official	354:e67efb2aab0e	368	*/
mbed_official	354:e67efb2aab0e	369
mbed_official	354:e67efb2aab0e	370	#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
mbed_official	354:e67efb2aab0e	371	#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
mbed_official	354:e67efb2aab0e	372	#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
mbed_official	354:e67efb2aab0e	373	#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
mbed_official	354:e67efb2aab0e	374	#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
mbed_official	354:e67efb2aab0e	375	#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
mbed_official	354:e67efb2aab0e	376	#define RCC_PLL_MUL24 RCC_CFGR_PLLMUL24
mbed_official	354:e67efb2aab0e	377	#define RCC_PLL_MUL32 RCC_CFGR_PLLMUL32
mbed_official	354:e67efb2aab0e	378	#define RCC_PLL_MUL48 RCC_CFGR_PLLMUL48
mbed_official	354:e67efb2aab0e	379
mbed_official	354:e67efb2aab0e	380	#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL3) \|\| ((__MUL__) == RCC_PLL_MUL4) \|\| \
mbed_official	354:e67efb2aab0e	381	((__MUL__) == RCC_PLL_MUL6) \|\| ((__MUL__) == RCC_PLL_MUL8) \|\| \
mbed_official	354:e67efb2aab0e	382	((__MUL__) == RCC_PLL_MUL12) \|\| ((__MUL__) == RCC_PLL_MUL16) \|\| \
mbed_official	354:e67efb2aab0e	383	((__MUL__) == RCC_PLL_MUL24) \|\| ((__MUL__) == RCC_PLL_MUL32) \|\| \
mbed_official	354:e67efb2aab0e	384	((__MUL__) == RCC_PLL_MUL48))
mbed_official	354:e67efb2aab0e	385	/**
mbed_official	354:e67efb2aab0e	386	* @}
mbed_official	354:e67efb2aab0e	387	*/
mbed_official	354:e67efb2aab0e	388
mbed_official	354:e67efb2aab0e	389	/** @defgroup RCC_System_Clock_Type RCC System Clock Type
mbed_official	354:e67efb2aab0e	390	* @{
mbed_official	354:e67efb2aab0e	391	*/
mbed_official	354:e67efb2aab0e	392	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
mbed_official	354:e67efb2aab0e	393	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
mbed_official	354:e67efb2aab0e	394	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
mbed_official	354:e67efb2aab0e	395	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
mbed_official	354:e67efb2aab0e	396
mbed_official	354:e67efb2aab0e	397	#define IS_RCC_CLOCKTYPE(__CLK__) ((1 <= (__CLK__)) && ((__CLK__) <= 15))
mbed_official	354:e67efb2aab0e	398	/**
mbed_official	354:e67efb2aab0e	399	* @}
mbed_official	354:e67efb2aab0e	400	*/
mbed_official	354:e67efb2aab0e	401
mbed_official	354:e67efb2aab0e	402	/** @defgroup RCC_System_Clock_Source RCC System Clock Source
mbed_official	354:e67efb2aab0e	403	* @{
mbed_official	354:e67efb2aab0e	404	*/
mbed_official	354:e67efb2aab0e	405	#define RCC_SYSCLKSOURCE_MSI ((uint32_t)RCC_CFGR_SW_MSI)
mbed_official	354:e67efb2aab0e	406	#define RCC_SYSCLKSOURCE_HSI ((uint32_t)RCC_CFGR_SW_HSI)
mbed_official	354:e67efb2aab0e	407	#define RCC_SYSCLKSOURCE_HSE ((uint32_t)RCC_CFGR_SW_HSE)
mbed_official	354:e67efb2aab0e	408	#define RCC_SYSCLKSOURCE_PLLCLK ((uint32_t)RCC_CFGR_SW_PLL)
mbed_official	354:e67efb2aab0e	409
mbed_official	354:e67efb2aab0e	410	#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) \|\| \
mbed_official	354:e67efb2aab0e	411	((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) \|\| \
mbed_official	354:e67efb2aab0e	412	((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) \|\| \
mbed_official	354:e67efb2aab0e	413	((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
mbed_official	354:e67efb2aab0e	414	/**
mbed_official	354:e67efb2aab0e	415	* @}
mbed_official	354:e67efb2aab0e	416	*/
mbed_official	354:e67efb2aab0e	417
mbed_official	354:e67efb2aab0e	418	/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source
mbed_official	354:e67efb2aab0e	419	* @{
mbed_official	354:e67efb2aab0e	420	*/
mbed_official	354:e67efb2aab0e	421	#define RCC_SYSCLK_DIV1 ((uint32_t)RCC_CFGR_HPRE_DIV1)
mbed_official	354:e67efb2aab0e	422	#define RCC_SYSCLK_DIV2 ((uint32_t)RCC_CFGR_HPRE_DIV2)
mbed_official	354:e67efb2aab0e	423	#define RCC_SYSCLK_DIV4 ((uint32_t)RCC_CFGR_HPRE_DIV4)
mbed_official	354:e67efb2aab0e	424	#define RCC_SYSCLK_DIV8 ((uint32_t)RCC_CFGR_HPRE_DIV8)
mbed_official	354:e67efb2aab0e	425	#define RCC_SYSCLK_DIV16 ((uint32_t)RCC_CFGR_HPRE_DIV16)
mbed_official	354:e67efb2aab0e	426	#define RCC_SYSCLK_DIV64 ((uint32_t)RCC_CFGR_HPRE_DIV64)
mbed_official	354:e67efb2aab0e	427	#define RCC_SYSCLK_DIV128 ((uint32_t)RCC_CFGR_HPRE_DIV128)
mbed_official	354:e67efb2aab0e	428	#define RCC_SYSCLK_DIV256 ((uint32_t)RCC_CFGR_HPRE_DIV256)
mbed_official	354:e67efb2aab0e	429	#define RCC_SYSCLK_DIV512 ((uint32_t)RCC_CFGR_HPRE_DIV512)
mbed_official	354:e67efb2aab0e	430
mbed_official	354:e67efb2aab0e	431	#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|\| \
mbed_official	354:e67efb2aab0e	432	((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \
mbed_official	354:e67efb2aab0e	433	((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \
mbed_official	354:e67efb2aab0e	434	((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \
mbed_official	354:e67efb2aab0e	435	((__HCLK__) == RCC_SYSCLK_DIV512))
mbed_official	354:e67efb2aab0e	436	/**
mbed_official	354:e67efb2aab0e	437	* @}
mbed_official	354:e67efb2aab0e	438	*/
mbed_official	354:e67efb2aab0e	439
mbed_official	354:e67efb2aab0e	440	/** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1 APB2 Clock Source
mbed_official	354:e67efb2aab0e	441	* @{
mbed_official	354:e67efb2aab0e	442	*/
mbed_official	354:e67efb2aab0e	443	#define RCC_HCLK_DIV1 ((uint32_t)RCC_CFGR_PPRE1_DIV1)
mbed_official	354:e67efb2aab0e	444	#define RCC_HCLK_DIV2 ((uint32_t)RCC_CFGR_PPRE1_DIV2)
mbed_official	354:e67efb2aab0e	445	#define RCC_HCLK_DIV4 ((uint32_t)RCC_CFGR_PPRE1_DIV4)
mbed_official	354:e67efb2aab0e	446	#define RCC_HCLK_DIV8 ((uint32_t)RCC_CFGR_PPRE1_DIV8)
mbed_official	354:e67efb2aab0e	447	#define RCC_HCLK_DIV16 ((uint32_t)RCC_CFGR_PPRE1_DIV16)
mbed_official	354:e67efb2aab0e	448
mbed_official	354:e67efb2aab0e	449	#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) \|\| ((__PCLK__) == RCC_HCLK_DIV2) \|\| \
mbed_official	354:e67efb2aab0e	450	((__PCLK__) == RCC_HCLK_DIV4) \|\| ((__PCLK__) == RCC_HCLK_DIV8) \|\| \
mbed_official	354:e67efb2aab0e	451	((__PCLK__) == RCC_HCLK_DIV16))
mbed_official	354:e67efb2aab0e	452	/**
mbed_official	354:e67efb2aab0e	453	* @}
mbed_official	354:e67efb2aab0e	454	*/
mbed_official	354:e67efb2aab0e	455
mbed_official	354:e67efb2aab0e	456	/** @defgroup RCC_RTC_LCD_Clock_Source RCC RTC LCD Clock Source
mbed_official	354:e67efb2aab0e	457	* @{
mbed_official	354:e67efb2aab0e	458	*/
mbed_official	354:e67efb2aab0e	459	#define RCC_RTCCLKSOURCE_LSE ((uint32_t)RCC_CSR_RTCSEL_LSE)
mbed_official	354:e67efb2aab0e	460	#define RCC_RTCCLKSOURCE_LSI ((uint32_t)RCC_CSR_RTCSEL_LSI)
mbed_official	354:e67efb2aab0e	461	#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)RCC_CSR_RTCSEL_HSE)
mbed_official	354:e67efb2aab0e	462	#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)(RCC_CR_RTCPRE_0 \| RCC_CSR_RTCSEL_HSE))
mbed_official	354:e67efb2aab0e	463	#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)(RCC_CR_RTCPRE_1 \| RCC_CSR_RTCSEL_HSE))
mbed_official	354:e67efb2aab0e	464	#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)(RCC_CR_RTCPRE \| RCC_CSR_RTCSEL_HSE))
mbed_official	354:e67efb2aab0e	465	/**
mbed_official	354:e67efb2aab0e	466	* @}
mbed_official	354:e67efb2aab0e	467	*/
mbed_official	354:e67efb2aab0e	468
mbed_official	354:e67efb2aab0e	469	/** @defgroup RCC_MCO_Index RCC MCO Index
mbed_official	354:e67efb2aab0e	470	* @{
mbed_official	354:e67efb2aab0e	471	*/
mbed_official	354:e67efb2aab0e	472	#define RCC_MCO1 ((uint32_t)0x00000000)
mbed_official	354:e67efb2aab0e	473	#define RCC_MCO RCC_MCO1
mbed_official	354:e67efb2aab0e	474
mbed_official	354:e67efb2aab0e	475	#define IS_RCC_MCO(__MCO__) (((__MCO__) == RCC_MCO))
mbed_official	354:e67efb2aab0e	476	/**
mbed_official	354:e67efb2aab0e	477	* @}
mbed_official	354:e67efb2aab0e	478	*/
mbed_official	354:e67efb2aab0e	479
mbed_official	354:e67efb2aab0e	480	/** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler
mbed_official	354:e67efb2aab0e	481	* @{
mbed_official	354:e67efb2aab0e	482	*/
mbed_official	354:e67efb2aab0e	483	#define RCC_MCODIV_1 ((uint32_t)RCC_CFGR_MCO_DIV1)
mbed_official	354:e67efb2aab0e	484	#define RCC_MCODIV_2 ((uint32_t)RCC_CFGR_MCO_DIV2)
mbed_official	354:e67efb2aab0e	485	#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO_DIV4)
mbed_official	354:e67efb2aab0e	486	#define RCC_MCODIV_8 ((uint32_t)RCC_CFGR_MCO_DIV8)
mbed_official	354:e67efb2aab0e	487	#define RCC_MCODIV_16 ((uint32_t)RCC_CFGR_MCO_DIV16)
mbed_official	354:e67efb2aab0e	488
mbed_official	354:e67efb2aab0e	489	#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) \|\| ((__DIV__) == RCC_MCODIV_2) \|\| \
mbed_official	354:e67efb2aab0e	490	((__DIV__) == RCC_MCODIV_4) \|\| ((__DIV__) == RCC_MCODIV_8) \|\| \
mbed_official	354:e67efb2aab0e	491	((__DIV__) == RCC_MCODIV_16))
mbed_official	354:e67efb2aab0e	492	/**
mbed_official	354:e67efb2aab0e	493	* @}
mbed_official	354:e67efb2aab0e	494	*/
mbed_official	354:e67efb2aab0e	495
mbed_official	354:e67efb2aab0e	496	/** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source
mbed_official	354:e67efb2aab0e	497	* @{
mbed_official	354:e67efb2aab0e	498	*/
mbed_official	354:e67efb2aab0e	499	#define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK)
mbed_official	354:e67efb2aab0e	500	#define RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK)
mbed_official	354:e67efb2aab0e	501	#define RCC_MCO1SOURCE_MSI ((uint32_t)RCC_CFGR_MCO_MSI)
mbed_official	354:e67efb2aab0e	502	#define RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI)
mbed_official	354:e67efb2aab0e	503	#define RCC_MCO1SOURCE_LSE ((uint32_t)RCC_CFGR_MCO_LSE)
mbed_official	354:e67efb2aab0e	504	#define RCC_MCO1SOURCE_LSI ((uint32_t)RCC_CFGR_MCO_LSI)
mbed_official	354:e67efb2aab0e	505	#define RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE)
mbed_official	354:e67efb2aab0e	506	#define RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLL)
mbed_official	354:e67efb2aab0e	507
mbed_official	354:e67efb2aab0e	508	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \
mbed_official	354:e67efb2aab0e	509	\|\| ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_LSE) \
mbed_official	354:e67efb2aab0e	510	\|\| ((__SOURCE__) == RCC_MCO1SOURCE_LSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_HSE) \
mbed_official	354:e67efb2aab0e	511	\|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
mbed_official	354:e67efb2aab0e	512	/**
mbed_official	354:e67efb2aab0e	513	* @}
mbed_official	354:e67efb2aab0e	514	*/
mbed_official	354:e67efb2aab0e	515
mbed_official	354:e67efb2aab0e	516	/** @defgroup RCC_Interrupt RCC Interrupt
mbed_official	354:e67efb2aab0e	517	* @{
mbed_official	354:e67efb2aab0e	518	*/
mbed_official	354:e67efb2aab0e	519	#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF)
mbed_official	354:e67efb2aab0e	520	#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF)
mbed_official	354:e67efb2aab0e	521	#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF)
mbed_official	354:e67efb2aab0e	522	#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF)
mbed_official	354:e67efb2aab0e	523	#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF)
mbed_official	354:e67efb2aab0e	524	#define RCC_IT_MSIRDY ((uint8_t)RCC_CIR_MSIRDYF)
mbed_official	354:e67efb2aab0e	525	#define RCC_IT_LSECSS ((uint8_t)RCC_CIR_LSECSS)
mbed_official	354:e67efb2aab0e	526	#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF)
mbed_official	354:e67efb2aab0e	527	/**
mbed_official	354:e67efb2aab0e	528	* @}
mbed_official	354:e67efb2aab0e	529	*/
mbed_official	354:e67efb2aab0e	530
mbed_official	354:e67efb2aab0e	531	/** @defgroup RCC_Flag RCC Flag
mbed_official	354:e67efb2aab0e	532	* Elements values convention: 0XXYYYYYb
mbed_official	354:e67efb2aab0e	533	* - YYYYY : Flag position in the register
mbed_official	354:e67efb2aab0e	534	* - XX : Register index
mbed_official	354:e67efb2aab0e	535	* - 01: CR register
mbed_official	354:e67efb2aab0e	536	* - 11: CSR register
mbed_official	354:e67efb2aab0e	537	* @{
mbed_official	354:e67efb2aab0e	538	*/
mbed_official	354:e67efb2aab0e	539	#define CR_REG_INDEX ((uint8_t)1)
mbed_official	354:e67efb2aab0e	540	#define CSR_REG_INDEX ((uint8_t)3)
mbed_official	354:e67efb2aab0e	541
mbed_official	354:e67efb2aab0e	542	/* Flags in the CR register */
mbed_official	354:e67efb2aab0e	543	#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_HSIRDY)))
mbed_official	354:e67efb2aab0e	544	#define RCC_FLAG_MSIRDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_MSIRDY)))
mbed_official	354:e67efb2aab0e	545	#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_HSERDY)))
mbed_official	354:e67efb2aab0e	546	#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_PLLRDY)))
mbed_official	354:e67efb2aab0e	547
mbed_official	354:e67efb2aab0e	548	/* Flags in the CSR register */
mbed_official	354:e67efb2aab0e	549	#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_LSIRDY)))
mbed_official	354:e67efb2aab0e	550	#define RCC_FLAG_LSERDY ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_LSERDY)))
mbed_official	354:e67efb2aab0e	551	#define RCC_FLAG_LSECSS ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_LSECSSD)))
mbed_official	354:e67efb2aab0e	552	#define RCC_FLAG_RMV ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_RMVF)))
mbed_official	354:e67efb2aab0e	553	#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_OBLRSTF)))
mbed_official	354:e67efb2aab0e	554	#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_PINRSTF)))
mbed_official	354:e67efb2aab0e	555	#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_PORRSTF)))
mbed_official	354:e67efb2aab0e	556	#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_SFTRSTF)))
mbed_official	354:e67efb2aab0e	557	#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_IWDGRSTF)))
mbed_official	354:e67efb2aab0e	558	#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_WWDGRSTF)))
mbed_official	354:e67efb2aab0e	559	#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_LPWRRSTF)))
mbed_official	354:e67efb2aab0e	560
mbed_official	354:e67efb2aab0e	561	#define RCC_FLAG_MASK ((uint8_t)0x1F)
mbed_official	354:e67efb2aab0e	562
mbed_official	354:e67efb2aab0e	563	/**
mbed_official	354:e67efb2aab0e	564	* @}
mbed_official	354:e67efb2aab0e	565	*/
mbed_official	354:e67efb2aab0e	566
mbed_official	354:e67efb2aab0e	567	/**
mbed_official	354:e67efb2aab0e	568	* @}
mbed_official	354:e67efb2aab0e	569	*/
mbed_official	354:e67efb2aab0e	570
mbed_official	354:e67efb2aab0e	571	/* Exported macro ------------------------------------------------------------*/
mbed_official	354:e67efb2aab0e	572
mbed_official	354:e67efb2aab0e	573	/** @defgroup RCC_Exported_Macros RCC Exported Macros
mbed_official	354:e67efb2aab0e	574	* @{
mbed_official	354:e67efb2aab0e	575	*/
mbed_official	354:e67efb2aab0e	576
mbed_official	354:e67efb2aab0e	577	/** @defgroup RCC_Peripheral_Clock_Enable_Disable RCC Peripheral Clock Enable Disable
mbed_official	354:e67efb2aab0e	578	* @brief Enable or disable the AHB1 peripheral clock.
mbed_official	354:e67efb2aab0e	579	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	354:e67efb2aab0e	580	* is disabled and the application software has to enable this clock before
mbed_official	354:e67efb2aab0e	581	* using it.
mbed_official	354:e67efb2aab0e	582	* @{
mbed_official	354:e67efb2aab0e	583	*/
mbed_official	354:e67efb2aab0e	584	#define __GPIOA_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOAEN))
mbed_official	354:e67efb2aab0e	585	#define __GPIOB_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOBEN))
mbed_official	354:e67efb2aab0e	586	#define __GPIOC_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOCEN))
mbed_official	354:e67efb2aab0e	587	#define __GPIOD_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIODEN))
mbed_official	354:e67efb2aab0e	588	#define __GPIOH_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOHEN))
mbed_official	354:e67efb2aab0e	589
mbed_official	354:e67efb2aab0e	590	#define __CRC_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_CRCEN))
mbed_official	354:e67efb2aab0e	591	#define __FLITF_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_FLITFEN))
mbed_official	354:e67efb2aab0e	592	#define __DMA1_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_DMA1EN))
mbed_official	354:e67efb2aab0e	593
mbed_official	354:e67efb2aab0e	594	#define __GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
mbed_official	354:e67efb2aab0e	595	#define __GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
mbed_official	354:e67efb2aab0e	596	#define __GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
mbed_official	354:e67efb2aab0e	597	#define __GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
mbed_official	354:e67efb2aab0e	598	#define __GPIOH_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN))
mbed_official	354:e67efb2aab0e	599
mbed_official	354:e67efb2aab0e	600	#define __CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
mbed_official	354:e67efb2aab0e	601	#define __FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
mbed_official	354:e67efb2aab0e	602	#define __DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
mbed_official	354:e67efb2aab0e	603
mbed_official	354:e67efb2aab0e	604	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
mbed_official	354:e67efb2aab0e	605	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	354:e67efb2aab0e	606	* is disabled and the application software has to enable this clock before
mbed_official	354:e67efb2aab0e	607	* using it.
mbed_official	354:e67efb2aab0e	608	*/
mbed_official	354:e67efb2aab0e	609	#define __TIM2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM2EN))
mbed_official	354:e67efb2aab0e	610	#define __TIM3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM3EN))
mbed_official	354:e67efb2aab0e	611	#define __TIM4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM4EN))
mbed_official	354:e67efb2aab0e	612	#define __TIM6_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM6EN))
mbed_official	354:e67efb2aab0e	613	#define __TIM7_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM7EN))
mbed_official	354:e67efb2aab0e	614	#define __WWDG_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_WWDGEN))
mbed_official	354:e67efb2aab0e	615	#define __SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
mbed_official	354:e67efb2aab0e	616	#define __USART2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART2EN))
mbed_official	354:e67efb2aab0e	617	#define __USART3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART3EN))
mbed_official	354:e67efb2aab0e	618	#define __I2C1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C1EN))
mbed_official	354:e67efb2aab0e	619	#define __I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
mbed_official	354:e67efb2aab0e	620	#define __USB_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USBEN))
mbed_official	354:e67efb2aab0e	621	#define __PWR_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_PWREN))
mbed_official	354:e67efb2aab0e	622	#define __DAC_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_DACEN))
mbed_official	354:e67efb2aab0e	623	#define __COMP_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_COMPEN))
mbed_official	354:e67efb2aab0e	624
mbed_official	354:e67efb2aab0e	625	#define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
mbed_official	354:e67efb2aab0e	626	#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
mbed_official	354:e67efb2aab0e	627	#define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
mbed_official	354:e67efb2aab0e	628	#define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
mbed_official	354:e67efb2aab0e	629	#define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
mbed_official	354:e67efb2aab0e	630	#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
mbed_official	354:e67efb2aab0e	631	#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
mbed_official	354:e67efb2aab0e	632	#define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
mbed_official	354:e67efb2aab0e	633	#define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
mbed_official	354:e67efb2aab0e	634	#define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
mbed_official	354:e67efb2aab0e	635	#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
mbed_official	354:e67efb2aab0e	636	#define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
mbed_official	354:e67efb2aab0e	637	#define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
mbed_official	354:e67efb2aab0e	638	#define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
mbed_official	354:e67efb2aab0e	639	#define __COMP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_COMPEN))
mbed_official	354:e67efb2aab0e	640
mbed_official	354:e67efb2aab0e	641	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
mbed_official	354:e67efb2aab0e	642	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	354:e67efb2aab0e	643	* is disabled and the application software has to enable this clock before
mbed_official	354:e67efb2aab0e	644	* using it.
mbed_official	354:e67efb2aab0e	645	*/
mbed_official	354:e67efb2aab0e	646	#define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SYSCFGEN))
mbed_official	354:e67efb2aab0e	647	#define __TIM9_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM9EN))
mbed_official	354:e67efb2aab0e	648	#define __TIM10_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM10EN))
mbed_official	354:e67efb2aab0e	649	#define __TIM11_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM11EN))
mbed_official	354:e67efb2aab0e	650	#define __ADC1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_ADC1EN))
mbed_official	354:e67efb2aab0e	651	#define __SPI1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI1EN))
mbed_official	354:e67efb2aab0e	652	#define __USART1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART1EN))
mbed_official	354:e67efb2aab0e	653
mbed_official	354:e67efb2aab0e	654	#define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
mbed_official	354:e67efb2aab0e	655	#define __TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
mbed_official	354:e67efb2aab0e	656	#define __TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
mbed_official	354:e67efb2aab0e	657	#define __TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
mbed_official	354:e67efb2aab0e	658	#define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
mbed_official	354:e67efb2aab0e	659	#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
mbed_official	354:e67efb2aab0e	660	#define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
mbed_official	354:e67efb2aab0e	661
mbed_official	354:e67efb2aab0e	662	/**
mbed_official	354:e67efb2aab0e	663	* @}
mbed_official	354:e67efb2aab0e	664	*/
mbed_official	354:e67efb2aab0e	665
mbed_official	354:e67efb2aab0e	666	/** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release
mbed_official	354:e67efb2aab0e	667	* @brief Force or release AHB peripheral reset.
mbed_official	354:e67efb2aab0e	668	* @{
mbed_official	354:e67efb2aab0e	669	*/
mbed_official	354:e67efb2aab0e	670	#define __AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
mbed_official	354:e67efb2aab0e	671	#define __GPIOA_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOARST))
mbed_official	354:e67efb2aab0e	672	#define __GPIOB_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOBRST))
mbed_official	354:e67efb2aab0e	673	#define __GPIOC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOCRST))
mbed_official	354:e67efb2aab0e	674	#define __GPIOD_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIODRST))
mbed_official	354:e67efb2aab0e	675	#define __GPIOH_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOHRST))
mbed_official	354:e67efb2aab0e	676
mbed_official	354:e67efb2aab0e	677	#define __CRC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_CRCRST))
mbed_official	354:e67efb2aab0e	678	#define __FLITF_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_FLITFRST))
mbed_official	354:e67efb2aab0e	679	#define __DMA1_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_DMA1RST))
mbed_official	354:e67efb2aab0e	680
mbed_official	354:e67efb2aab0e	681	#define __AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
mbed_official	354:e67efb2aab0e	682	#define __GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
mbed_official	354:e67efb2aab0e	683	#define __GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
mbed_official	354:e67efb2aab0e	684	#define __GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
mbed_official	354:e67efb2aab0e	685	#define __GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
mbed_official	354:e67efb2aab0e	686	#define __GPIOH_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST))
mbed_official	354:e67efb2aab0e	687
mbed_official	354:e67efb2aab0e	688	#define __CRC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_CRCRST))
mbed_official	354:e67efb2aab0e	689	#define __FLITF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FLITFRST))
mbed_official	354:e67efb2aab0e	690	#define __DMA1_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA1RST))
mbed_official	354:e67efb2aab0e	691
mbed_official	354:e67efb2aab0e	692	/** @brief Force or release APB1 peripheral reset.
mbed_official	354:e67efb2aab0e	693	*/
mbed_official	354:e67efb2aab0e	694	#define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
mbed_official	354:e67efb2aab0e	695	#define __TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
mbed_official	354:e67efb2aab0e	696	#define __TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
mbed_official	354:e67efb2aab0e	697	#define __TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
mbed_official	354:e67efb2aab0e	698	#define __TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
mbed_official	354:e67efb2aab0e	699	#define __TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
mbed_official	354:e67efb2aab0e	700	#define __WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
mbed_official	354:e67efb2aab0e	701	#define __SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
mbed_official	354:e67efb2aab0e	702	#define __USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
mbed_official	354:e67efb2aab0e	703	#define __USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
mbed_official	354:e67efb2aab0e	704	#define __I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
mbed_official	354:e67efb2aab0e	705	#define __I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
mbed_official	354:e67efb2aab0e	706	#define __USB_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USBRST))
mbed_official	354:e67efb2aab0e	707	#define __PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
mbed_official	354:e67efb2aab0e	708	#define __DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
mbed_official	354:e67efb2aab0e	709	#define __COMP_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_COMPRST))
mbed_official	354:e67efb2aab0e	710
mbed_official	354:e67efb2aab0e	711	#define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
mbed_official	354:e67efb2aab0e	712	#define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
mbed_official	354:e67efb2aab0e	713	#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
mbed_official	354:e67efb2aab0e	714	#define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
mbed_official	354:e67efb2aab0e	715	#define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
mbed_official	354:e67efb2aab0e	716	#define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
mbed_official	354:e67efb2aab0e	717	#define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
mbed_official	354:e67efb2aab0e	718	#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
mbed_official	354:e67efb2aab0e	719	#define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
mbed_official	354:e67efb2aab0e	720	#define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
mbed_official	354:e67efb2aab0e	721	#define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
mbed_official	354:e67efb2aab0e	722	#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
mbed_official	354:e67efb2aab0e	723	#define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
mbed_official	354:e67efb2aab0e	724	#define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
mbed_official	354:e67efb2aab0e	725	#define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
mbed_official	354:e67efb2aab0e	726	#define __COMP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_COMPRST))
mbed_official	354:e67efb2aab0e	727
mbed_official	354:e67efb2aab0e	728	/** @brief Force or release APB2 peripheral reset.
mbed_official	354:e67efb2aab0e	729	*/
mbed_official	354:e67efb2aab0e	730	#define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
mbed_official	354:e67efb2aab0e	731	#define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
mbed_official	354:e67efb2aab0e	732	#define __TIM9_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM9RST))
mbed_official	354:e67efb2aab0e	733	#define __TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
mbed_official	354:e67efb2aab0e	734	#define __TIM11_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM11RST))
mbed_official	354:e67efb2aab0e	735	#define __ADC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADC1RST))
mbed_official	354:e67efb2aab0e	736	#define __SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
mbed_official	354:e67efb2aab0e	737	#define __USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
mbed_official	354:e67efb2aab0e	738
mbed_official	354:e67efb2aab0e	739	#define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
mbed_official	354:e67efb2aab0e	740	#define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
mbed_official	354:e67efb2aab0e	741	#define __TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
mbed_official	354:e67efb2aab0e	742	#define __TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
mbed_official	354:e67efb2aab0e	743	#define __TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
mbed_official	354:e67efb2aab0e	744	#define __ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
mbed_official	354:e67efb2aab0e	745	#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
mbed_official	354:e67efb2aab0e	746	#define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
mbed_official	354:e67efb2aab0e	747
mbed_official	354:e67efb2aab0e	748	/**
mbed_official	354:e67efb2aab0e	749	* @}
mbed_official	354:e67efb2aab0e	750	*/
mbed_official	354:e67efb2aab0e	751
mbed_official	354:e67efb2aab0e	752	/** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable
mbed_official	354:e67efb2aab0e	753	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	354:e67efb2aab0e	754	* power consumption.
mbed_official	354:e67efb2aab0e	755	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	354:e67efb2aab0e	756	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	354:e67efb2aab0e	757	* @{
mbed_official	354:e67efb2aab0e	758	*/
mbed_official	354:e67efb2aab0e	759	#define __GPIOA_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_GPIOALPEN))
mbed_official	354:e67efb2aab0e	760	#define __GPIOB_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_GPIOBLPEN))
mbed_official	354:e67efb2aab0e	761	#define __GPIOC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_GPIOCLPEN))
mbed_official	354:e67efb2aab0e	762	#define __GPIOD_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_GPIODLPEN))
mbed_official	354:e67efb2aab0e	763	#define __GPIOH_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_GPIOHLPEN))
mbed_official	354:e67efb2aab0e	764
mbed_official	354:e67efb2aab0e	765	#define __CRC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_CRCLPEN))
mbed_official	354:e67efb2aab0e	766	#define __FLITF_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_FLITFLPEN))
mbed_official	354:e67efb2aab0e	767	#define __DMA1_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_DMA1LPEN))
mbed_official	354:e67efb2aab0e	768
mbed_official	354:e67efb2aab0e	769	#define __GPIOA_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOALPEN))
mbed_official	354:e67efb2aab0e	770	#define __GPIOB_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOBLPEN))
mbed_official	354:e67efb2aab0e	771	#define __GPIOC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOCLPEN))
mbed_official	354:e67efb2aab0e	772	#define __GPIOD_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIODLPEN))
mbed_official	354:e67efb2aab0e	773	#define __GPIOH_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOHLPEN))
mbed_official	354:e67efb2aab0e	774
mbed_official	354:e67efb2aab0e	775	#define __CRC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_CRCLPEN))
mbed_official	354:e67efb2aab0e	776	#define __FLITF_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FLITFLPEN))
mbed_official	354:e67efb2aab0e	777	#define __DMA1_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA1LPEN))
mbed_official	354:e67efb2aab0e	778
mbed_official	354:e67efb2aab0e	779	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
mbed_official	354:e67efb2aab0e	780	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	354:e67efb2aab0e	781	* power consumption.
mbed_official	354:e67efb2aab0e	782	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	354:e67efb2aab0e	783	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	354:e67efb2aab0e	784	*/
mbed_official	354:e67efb2aab0e	785	#define __TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
mbed_official	354:e67efb2aab0e	786	#define __TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
mbed_official	354:e67efb2aab0e	787	#define __TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
mbed_official	354:e67efb2aab0e	788	#define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
mbed_official	354:e67efb2aab0e	789	#define __TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
mbed_official	354:e67efb2aab0e	790	#define __WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_WWDGLPEN))
mbed_official	354:e67efb2aab0e	791	#define __SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI2LPEN))
mbed_official	354:e67efb2aab0e	792	#define __USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART2LPEN))
mbed_official	354:e67efb2aab0e	793	#define __USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
mbed_official	354:e67efb2aab0e	794	#define __I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C1LPEN))
mbed_official	354:e67efb2aab0e	795	#define __I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C2LPEN))
mbed_official	354:e67efb2aab0e	796	#define __USB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USBLPEN))
mbed_official	354:e67efb2aab0e	797	#define __PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_PWRLPEN))
mbed_official	354:e67efb2aab0e	798	#define __DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
mbed_official	354:e67efb2aab0e	799	#define __COMP_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_COMPLPEN))
mbed_official	354:e67efb2aab0e	800
mbed_official	354:e67efb2aab0e	801	#define __TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
mbed_official	354:e67efb2aab0e	802	#define __TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
mbed_official	354:e67efb2aab0e	803	#define __TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
mbed_official	354:e67efb2aab0e	804	#define __TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
mbed_official	354:e67efb2aab0e	805	#define __TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
mbed_official	354:e67efb2aab0e	806	#define __WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
mbed_official	354:e67efb2aab0e	807	#define __SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
mbed_official	354:e67efb2aab0e	808	#define __USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
mbed_official	354:e67efb2aab0e	809	#define __USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
mbed_official	354:e67efb2aab0e	810	#define __I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
mbed_official	354:e67efb2aab0e	811	#define __I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
mbed_official	354:e67efb2aab0e	812	#define __USB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USBLPEN))
mbed_official	354:e67efb2aab0e	813	#define __PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
mbed_official	354:e67efb2aab0e	814	#define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
mbed_official	354:e67efb2aab0e	815	#define __COMP_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_COMPLPEN))
mbed_official	354:e67efb2aab0e	816
mbed_official	354:e67efb2aab0e	817	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
mbed_official	354:e67efb2aab0e	818	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	354:e67efb2aab0e	819	* power consumption.
mbed_official	354:e67efb2aab0e	820	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	354:e67efb2aab0e	821	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	354:e67efb2aab0e	822	*/
mbed_official	354:e67efb2aab0e	823	#define __SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SYSCFGLPEN))
mbed_official	354:e67efb2aab0e	824	#define __TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM9LPEN))
mbed_official	354:e67efb2aab0e	825	#define __TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
mbed_official	354:e67efb2aab0e	826	#define __TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM11LPEN))
mbed_official	354:e67efb2aab0e	827	#define __ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC1LPEN))
mbed_official	354:e67efb2aab0e	828	#define __SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI1LPEN))
mbed_official	354:e67efb2aab0e	829	#define __USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART1LPEN))
mbed_official	354:e67efb2aab0e	830
mbed_official	354:e67efb2aab0e	831	#define __SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
mbed_official	354:e67efb2aab0e	832	#define __TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
mbed_official	354:e67efb2aab0e	833	#define __TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
mbed_official	354:e67efb2aab0e	834	#define __TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
mbed_official	354:e67efb2aab0e	835	#define __ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
mbed_official	354:e67efb2aab0e	836	#define __SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
mbed_official	354:e67efb2aab0e	837	#define __USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
mbed_official	354:e67efb2aab0e	838
mbed_official	354:e67efb2aab0e	839	/**
mbed_official	354:e67efb2aab0e	840	* @}
mbed_official	354:e67efb2aab0e	841	*/
mbed_official	354:e67efb2aab0e	842
mbed_official	354:e67efb2aab0e	843	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
mbed_official	354:e67efb2aab0e	844	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	354:e67efb2aab0e	845	* @note HSI can not be stopped if it is used as system clock source. In this case,
mbed_official	354:e67efb2aab0e	846	* you have to select another source of the system clock then stop the HSI.
mbed_official	354:e67efb2aab0e	847	* @note After enabling the HSI, the application software should wait on HSIRDY
mbed_official	354:e67efb2aab0e	848	* flag to be set indicating that HSI clock is stable and can be used as
mbed_official	354:e67efb2aab0e	849	* system clock source.
mbed_official	354:e67efb2aab0e	850	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
mbed_official	354:e67efb2aab0e	851	* clock cycles.
mbed_official	354:e67efb2aab0e	852	*/
mbed_official	354:e67efb2aab0e	853	#define __HAL_RCC_HSI_ENABLE() ((__IO uint32_t ) CR_HSION_BB = ENABLE)
mbed_official	354:e67efb2aab0e	854	#define __HAL_RCC_HSI_DISABLE() ((__IO uint32_t ) CR_HSION_BB = DISABLE)
mbed_official	354:e67efb2aab0e	855
mbed_official	354:e67efb2aab0e	856	/** @brief Macros to enable or disable the External High Speed oscillator (HSE).
mbed_official	354:e67efb2aab0e	857	* @param __HSE_STATE__: specifies the new state of the HSE.
mbed_official	354:e67efb2aab0e	858	* This parameter can be one of the following values:
mbed_official	354:e67efb2aab0e	859	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
mbed_official	354:e67efb2aab0e	860	* 6 HSE oscillator clock cycles.
mbed_official	354:e67efb2aab0e	861	* @arg RCC_HSE_ON: turn ON the HSE oscillator
mbed_official	354:e67efb2aab0e	862	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock
mbed_official	354:e67efb2aab0e	863	*/
mbed_official	354:e67efb2aab0e	864	#define __HAL_RCC_HSE_CONFIG(__HSE_STATE__) ((__IO uint8_t ) CR_BYTE2_ADDRESS = (__HSE_STATE__))
mbed_official	354:e67efb2aab0e	865
mbed_official	354:e67efb2aab0e	866	/** @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI).
mbed_official	354:e67efb2aab0e	867	* @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	354:e67efb2aab0e	868	* It is used (enabled by hardware) as system clock source after startup
mbed_official	354:e67efb2aab0e	869	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
mbed_official	354:e67efb2aab0e	870	* of the HSE used directly or indirectly as system clock (if the Clock
mbed_official	354:e67efb2aab0e	871	* Security System CSS is enabled).
mbed_official	354:e67efb2aab0e	872	* @note MSI can not be stopped if it is used as system clock source. In this case,
mbed_official	354:e67efb2aab0e	873	* you have to select another source of the system clock then stop the MSI.
mbed_official	354:e67efb2aab0e	874	* @note After enabling the MSI, the application software should wait on MSIRDY
mbed_official	354:e67efb2aab0e	875	* flag to be set indicating that MSI clock is stable and can be used as
mbed_official	354:e67efb2aab0e	876	* system clock source.
mbed_official	354:e67efb2aab0e	877	* @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
mbed_official	354:e67efb2aab0e	878	* clock cycles.
mbed_official	354:e67efb2aab0e	879	*/
mbed_official	354:e67efb2aab0e	880	#define __HAL_RCC_MSI_ENABLE() ((__IO uint32_t ) CR_MSION_BB = ENABLE)
mbed_official	354:e67efb2aab0e	881	#define __HAL_RCC_MSI_DISABLE() ((__IO uint32_t ) CR_MSION_BB = DISABLE)
mbed_official	354:e67efb2aab0e	882
mbed_official	354:e67efb2aab0e	883	/** @brief macro to adjust the Internal High Speed oscillator (HSI) calibration value.
mbed_official	354:e67efb2aab0e	884	* @note The calibration is used to compensate for the variations in voltage
mbed_official	354:e67efb2aab0e	885	* and temperature that influence the frequency of the internal HSI RC.
mbed_official	354:e67efb2aab0e	886	* @param _HSICALIBRATIONVALUE_: specifies the calibration trimming value.
mbed_official	354:e67efb2aab0e	887	* (default is RCC_HSICALIBRATION_DEFAULT).
mbed_official	354:e67efb2aab0e	888	* This parameter must be a number between 0 and 0x1F.
mbed_official	354:e67efb2aab0e	889	*/
mbed_official	354:e67efb2aab0e	890	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
mbed_official	354:e67efb2aab0e	891	(MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_ICSCR_HSITRIM)))
mbed_official	354:e67efb2aab0e	892
mbed_official	354:e67efb2aab0e	893	/** @brief macro to adjust the Internal Multi Speed oscillator (MSI) calibration value.
mbed_official	354:e67efb2aab0e	894	* @note The calibration is used to compensate for the variations in voltage
mbed_official	354:e67efb2aab0e	895	* and temperature that influence the frequency of the internal MSI RC.
mbed_official	354:e67efb2aab0e	896	* @param _MSICALIBRATIONVALUE_: specifies the calibration trimming value.
mbed_official	354:e67efb2aab0e	897	* (default is RCC_MSICALIBRATION_DEFAULT).
mbed_official	354:e67efb2aab0e	898	* This parameter must be a number between 0 and 0x1F.
mbed_official	354:e67efb2aab0e	899	*/
mbed_official	354:e67efb2aab0e	900	#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(_MSICALIBRATIONVALUE_) \
mbed_official	354:e67efb2aab0e	901	(MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(_MSICALIBRATIONVALUE_) << POSITION_VAL(RCC_ICSCR_MSITRIM)))
mbed_official	354:e67efb2aab0e	902
mbed_official	354:e67efb2aab0e	903	/* @brief Macro to configures the Internal Multi Speed oscillator (MSI) clock range.
mbed_official	354:e67efb2aab0e	904	* @note After restart from Reset or wakeup from STANDBY, the MSI clock is
mbed_official	354:e67efb2aab0e	905	* around 2.097 MHz. The MSI clock does not change after wake-up from
mbed_official	354:e67efb2aab0e	906	* STOP mode.
mbed_official	354:e67efb2aab0e	907	* @note The MSI clock range can be modified on the fly.
mbed_official	354:e67efb2aab0e	908	* @param _MSIRANGEVALUE_: specifies the MSI Clock range.
mbed_official	354:e67efb2aab0e	909	* This parameter must be one of the following values:
mbed_official	354:e67efb2aab0e	910	* @arg RCC_MSIRANGE_0: MSI clock is around 65.536 KHz
mbed_official	354:e67efb2aab0e	911	* @arg RCC_MSIRANGE_1: MSI clock is around 131.072 KHz
mbed_official	354:e67efb2aab0e	912	* @arg RCC_MSIRANGE_2: MSI clock is around 262.144 KHz
mbed_official	354:e67efb2aab0e	913	* @arg RCC_MSIRANGE_3: MSI clock is around 524.288 KHz
mbed_official	354:e67efb2aab0e	914	* @arg RCC_MSIRANGE_4: MSI clock is around 1.048 MHz
mbed_official	354:e67efb2aab0e	915	* @arg RCC_MSIRANGE_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
mbed_official	354:e67efb2aab0e	916	* @arg RCC_MSIRANGE_6: MSI clock is around 4.194 MHz
mbed_official	354:e67efb2aab0e	917	*/
mbed_official	354:e67efb2aab0e	918	#define __HAL_RCC_MSI_RANGE_CONFIG(_MSIRANGEVALUE_) (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSIRANGE, (uint32_t)(_MSIRANGEVALUE_)))
mbed_official	354:e67efb2aab0e	919
mbed_official	354:e67efb2aab0e	920
mbed_official	354:e67efb2aab0e	921	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
mbed_official	354:e67efb2aab0e	922	* @note After enabling the LSI, the application software should wait on
mbed_official	354:e67efb2aab0e	923	* LSIRDY flag to be set indicating that LSI clock is stable and can
mbed_official	354:e67efb2aab0e	924	* be used to clock the IWDG and/or the RTC.
mbed_official	354:e67efb2aab0e	925	* @note LSI can not be disabled if the IWDG is running.
mbed_official	354:e67efb2aab0e	926	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
mbed_official	354:e67efb2aab0e	927	* clock cycles.
mbed_official	354:e67efb2aab0e	928	*/
mbed_official	354:e67efb2aab0e	929	#define __HAL_RCC_LSI_ENABLE() ((__IO uint32_t ) CSR_LSION_BB = ENABLE)
mbed_official	354:e67efb2aab0e	930	#define __HAL_RCC_LSI_DISABLE() ((__IO uint32_t ) CSR_LSION_BB = DISABLE)
mbed_official	354:e67efb2aab0e	931
mbed_official	354:e67efb2aab0e	932	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSE).
mbed_official	354:e67efb2aab0e	933	*/
mbed_official	354:e67efb2aab0e	934	#define __HAL_RCC_LSE_CONFIG(__LSE_STATE__) \
mbed_official	354:e67efb2aab0e	935	do{ \
mbed_official	354:e67efb2aab0e	936	if ((__LSE_STATE__) == RCC_LSE_OFF) \
mbed_official	354:e67efb2aab0e	937	{ \
mbed_official	354:e67efb2aab0e	938	(__IO uint32_t ) CSR_LSEON_BB = DISABLE; \
mbed_official	354:e67efb2aab0e	939	(__IO uint32_t ) CSR_LSEBYP_BB = DISABLE; \
mbed_official	354:e67efb2aab0e	940	} \
mbed_official	354:e67efb2aab0e	941	else if ((__LSE_STATE__) == RCC_LSE_ON) \
mbed_official	354:e67efb2aab0e	942	{ \
mbed_official	354:e67efb2aab0e	943	(__IO uint32_t ) CSR_LSEBYP_BB = DISABLE; \
mbed_official	354:e67efb2aab0e	944	(__IO uint32_t ) CSR_LSEON_BB = ENABLE; \
mbed_official	354:e67efb2aab0e	945	} \
mbed_official	354:e67efb2aab0e	946	else \
mbed_official	354:e67efb2aab0e	947	{ \
mbed_official	354:e67efb2aab0e	948	(__IO uint32_t ) CSR_LSEON_BB = DISABLE; \
mbed_official	354:e67efb2aab0e	949	(__IO uint32_t ) CSR_LSEBYP_BB = ENABLE; \
mbed_official	354:e67efb2aab0e	950	} \
mbed_official	354:e67efb2aab0e	951	}while(0)
mbed_official	354:e67efb2aab0e	952
mbed_official	354:e67efb2aab0e	953	/** @brief Macros to enable or disable the the RTC clock.
mbed_official	354:e67efb2aab0e	954	* @note These macros must be used only after the RTC clock source was selected.
mbed_official	354:e67efb2aab0e	955	*/
mbed_official	354:e67efb2aab0e	956	#define __HAL_RCC_RTC_ENABLE() ((__IO uint32_t ) CSR_RTCEN_BB = ENABLE)
mbed_official	354:e67efb2aab0e	957	#define __HAL_RCC_RTC_DISABLE() ((__IO uint32_t ) CSR_RTCEN_BB = DISABLE)
mbed_official	354:e67efb2aab0e	958
mbed_official	354:e67efb2aab0e	959	/** @brief Macros to force or release the Backup domain reset.
mbed_official	354:e67efb2aab0e	960	* @note This function resets the RTC peripheral (including the backup registers)
mbed_official	354:e67efb2aab0e	961	* and the RTC clock source selection in RCC_CSR register.
mbed_official	354:e67efb2aab0e	962	* @note The BKPSRAM is not affected by this reset.
mbed_official	354:e67efb2aab0e	963	*/
mbed_official	354:e67efb2aab0e	964	#define __HAL_RCC_BACKUPRESET_FORCE() ((__IO uint32_t ) CSR_RTCRST_BB = ENABLE)
mbed_official	354:e67efb2aab0e	965	#define __HAL_RCC_BACKUPRESET_RELEASE() ((__IO uint32_t ) CSR_RTCRST_BB = DISABLE)
mbed_official	354:e67efb2aab0e	966
mbed_official	354:e67efb2aab0e	967
mbed_official	354:e67efb2aab0e	968	/** @brief Macro to configures the RTC clock (RTCCLK).
mbed_official	354:e67efb2aab0e	969	* @note As the RTC clock configuration bits are in the Backup domain and write
mbed_official	354:e67efb2aab0e	970	* access is denied to this domain after reset, you have to enable write
mbed_official	354:e67efb2aab0e	971	* access using the Power Backup Access macro before to configure
mbed_official	354:e67efb2aab0e	972	* the RTC clock source (to be done once after reset).
mbed_official	354:e67efb2aab0e	973	* @note Once the RTC clock is configured it can't be changed unless the
mbed_official	354:e67efb2aab0e	974	* Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
mbed_official	354:e67efb2aab0e	975	* a Power On Reset (POR).
mbed_official	354:e67efb2aab0e	976	* @note RTC prescaler cannot be modified if HSE is enabled (HSEON = 1).
mbed_official	354:e67efb2aab0e	977	*
mbed_official	354:e67efb2aab0e	978	* @param __RTC_CLKSOURCE__: specifies the RTC clock source.
mbed_official	354:e67efb2aab0e	979	* This parameter can be one of the following values:
mbed_official	354:e67efb2aab0e	980	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
mbed_official	354:e67efb2aab0e	981	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
mbed_official	354:e67efb2aab0e	982	* @arg RCC_RTCCLKSOURCE_HSE_DIV2: HSE divided by 2 selected as RTC clock
mbed_official	354:e67efb2aab0e	983	* @arg RCC_RTCCLKSOURCE_HSE_DIV4: HSE divided by 4 selected as RTC clock
mbed_official	354:e67efb2aab0e	984	* @arg RCC_RTCCLKSOURCE_HSE_DIV8: HSE divided by 8 selected as RTC clock
mbed_official	354:e67efb2aab0e	985	* @arg RCC_RTCCLKSOURCE_HSE_DIV16: HSE divided by 16 selected as RTC clock
mbed_official	354:e67efb2aab0e	986	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
mbed_official	354:e67efb2aab0e	987	* work in STOP and STANDBY modes, and can be used as wakeup source.
mbed_official	354:e67efb2aab0e	988	* However, when the HSE clock is used as RTC clock source, the RTC
mbed_official	354:e67efb2aab0e	989	* cannot be used in STOP and STANDBY modes.
mbed_official	354:e67efb2aab0e	990	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
mbed_official	354:e67efb2aab0e	991	* RTC clock source).
mbed_official	354:e67efb2aab0e	992	*/
mbed_official	354:e67efb2aab0e	993	#define __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__) do { \
mbed_official	354:e67efb2aab0e	994	if(((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE) \
mbed_official	354:e67efb2aab0e	995	{ \
mbed_official	354:e67efb2aab0e	996	MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTC_CLKSOURCE__) & RCC_CR_RTCPRE)); \
mbed_official	354:e67efb2aab0e	997	} \
mbed_official	354:e67efb2aab0e	998	} while (0)
mbed_official	354:e67efb2aab0e	999
mbed_official	354:e67efb2aab0e	1000	#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) do { \
mbed_official	354:e67efb2aab0e	1001	__HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__); \
mbed_official	354:e67efb2aab0e	1002	RCC->CSR \|= ((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL); \
mbed_official	354:e67efb2aab0e	1003	} while (0)
mbed_official	354:e67efb2aab0e	1004
mbed_official	354:e67efb2aab0e	1005	/** @brief macros to get the RTC clock source.
mbed_official	354:e67efb2aab0e	1006	*/
mbed_official	354:e67efb2aab0e	1007	#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->CSR, RCC_CSR_RTCSEL))
mbed_official	354:e67efb2aab0e	1008
mbed_official	354:e67efb2aab0e	1009	/** @brief Macros to enable or disable the main PLL.
mbed_official	354:e67efb2aab0e	1010	* @note After enabling the main PLL, the application software should wait on
mbed_official	354:e67efb2aab0e	1011	* PLLRDY flag to be set indicating that PLL clock is stable and can
mbed_official	354:e67efb2aab0e	1012	* be used as system clock source.
mbed_official	354:e67efb2aab0e	1013	* @note The main PLL can not be disabled if it is used as system clock source
mbed_official	354:e67efb2aab0e	1014	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
mbed_official	354:e67efb2aab0e	1015	*/
mbed_official	354:e67efb2aab0e	1016	#define __HAL_RCC_PLL_ENABLE() ((__IO uint32_t ) CR_PLLON_BB = ENABLE)
mbed_official	354:e67efb2aab0e	1017	#define __HAL_RCC_PLL_DISABLE() ((__IO uint32_t ) CR_PLLON_BB = DISABLE)
mbed_official	354:e67efb2aab0e	1018
mbed_official	354:e67efb2aab0e	1019	/** @brief macros to configure the main PLL clock source, multiplication and division factors.
mbed_official	354:e67efb2aab0e	1020	* @note This function must be used only when the main PLL is disabled.
mbed_official	354:e67efb2aab0e	1021	*
mbed_official	354:e67efb2aab0e	1022	* @param __RCC_PLLSOURCE__: specifies the PLL entry clock source.
mbed_official	354:e67efb2aab0e	1023	* This parameter can be one of the following values:
mbed_official	354:e67efb2aab0e	1024	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
mbed_official	354:e67efb2aab0e	1025	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
mbed_official	354:e67efb2aab0e	1026	* @param __PLLMUL__: specifies the multiplication factor for PLL VCO output clock
mbed_official	354:e67efb2aab0e	1027	* This parameter can be one of the following values:
mbed_official	354:e67efb2aab0e	1028	* @arg RCC_PLL_MUL3: PLLVCO = PLL clock entry x 3
mbed_official	354:e67efb2aab0e	1029	* @arg RCC_PLL_MUL4: PLLVCO = PLL clock entry x 4
mbed_official	354:e67efb2aab0e	1030	* @arg RCC_PLL_MUL6: PLLVCO = PLL clock entry x 6
mbed_official	354:e67efb2aab0e	1031	* @arg RCC_PLL_MUL8: PLLVCO = PLL clock entry x 8
mbed_official	354:e67efb2aab0e	1032	* @arg RCC_PLL_MUL12: PLLVCO = PLL clock entry x 12
mbed_official	354:e67efb2aab0e	1033	* @arg RCC_PLL_MUL16: PLLVCO = PLL clock entry x 16
mbed_official	354:e67efb2aab0e	1034	* @arg RCC_PLL_MUL24: PLLVCO = PLL clock entry x 24
mbed_official	354:e67efb2aab0e	1035	* @arg RCC_PLL_MUL32: PLLVCO = PLL clock entry x 32
mbed_official	354:e67efb2aab0e	1036	* @arg RCC_PLL_MUL48: PLLVCO = PLL clock entry x 48
mbed_official	354:e67efb2aab0e	1037	* @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in
mbed_official	354:e67efb2aab0e	1038	* Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is
mbed_official	354:e67efb2aab0e	1039	* in Range 3.
mbed_official	354:e67efb2aab0e	1040	*
mbed_official	354:e67efb2aab0e	1041	* @param __PLLDIV__: specifies the division factor for PLL VCO input clock
mbed_official	354:e67efb2aab0e	1042	* This parameter can be one of the following values:
mbed_official	354:e67efb2aab0e	1043	* @arg RCC_PLL_DIV2: PLL clock output = PLLVCO / 2
mbed_official	354:e67efb2aab0e	1044	* @arg RCC_PLL_DIV3: PLL clock output = PLLVCO / 3
mbed_official	354:e67efb2aab0e	1045	* @arg RCC_PLL_DIV4: PLL clock output = PLLVCO / 4
mbed_official	354:e67efb2aab0e	1046	*
mbed_official	354:e67efb2aab0e	1047	*/
mbed_official	354:e67efb2aab0e	1048	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__, __PLLDIV__)\
mbed_official	354:e67efb2aab0e	1049	MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC\|RCC_CFGR_PLLMUL\|RCC_CFGR_PLLDIV),((__RCC_PLLSOURCE__) \| (__PLLMUL__) \| (__PLLDIV__)))
mbed_official	354:e67efb2aab0e	1050
mbed_official	354:e67efb2aab0e	1051	/** @brief Macro to get the clock source used as system clock.
mbed_official	354:e67efb2aab0e	1052	* @retval The clock source used as system clock. The returned value can be one
mbed_official	354:e67efb2aab0e	1053	* of the following:
mbed_official	354:e67efb2aab0e	1054	* @arg RCC_CFGR_SWS_MSI: MSI used as system clock
mbed_official	354:e67efb2aab0e	1055	* @arg RCC_CFGR_SWS_HSI: HSI used as system clock
mbed_official	354:e67efb2aab0e	1056	* @arg RCC_CFGR_SWS_HSE: HSE used as system clock
mbed_official	354:e67efb2aab0e	1057	* @arg RCC_CFGR_SWS_PLL: PLL used as system clock
mbed_official	354:e67efb2aab0e	1058	*/
mbed_official	354:e67efb2aab0e	1059	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
mbed_official	354:e67efb2aab0e	1060
mbed_official	354:e67efb2aab0e	1061	/** @brief macros to manage the specified RCC Flags and interrupts.
mbed_official	354:e67efb2aab0e	1062	*/
mbed_official	354:e67efb2aab0e	1063
mbed_official	354:e67efb2aab0e	1064	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
mbed_official	354:e67efb2aab0e	1065	* the selected interrupts.).
mbed_official	354:e67efb2aab0e	1066	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
mbed_official	354:e67efb2aab0e	1067	* This parameter can be any combination of the following values:
mbed_official	354:e67efb2aab0e	1068	* @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official	354:e67efb2aab0e	1069	* @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official	354:e67efb2aab0e	1070	* @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official	354:e67efb2aab0e	1071	* @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official	354:e67efb2aab0e	1072	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
mbed_official	354:e67efb2aab0e	1073	* @arg RCC_IT_MSIRDY: MSI ready interrupt
mbed_official	354:e67efb2aab0e	1074	* @arg RCC_IT_LSECSS: LSE CSS interrupt (not available for STM32L100xB \|\| STM32L151xB \|\| STM32L152xB device)
mbed_official	354:e67efb2aab0e	1075	*/
mbed_official	354:e67efb2aab0e	1076	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t ) CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
mbed_official	354:e67efb2aab0e	1077
mbed_official	354:e67efb2aab0e	1078	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
mbed_official	354:e67efb2aab0e	1079	* the selected interrupts).
mbed_official	354:e67efb2aab0e	1080	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
mbed_official	354:e67efb2aab0e	1081	* This parameter can be any combination of the following values:
mbed_official	354:e67efb2aab0e	1082	* @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official	354:e67efb2aab0e	1083	* @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official	354:e67efb2aab0e	1084	* @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official	354:e67efb2aab0e	1085	* @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official	354:e67efb2aab0e	1086	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
mbed_official	354:e67efb2aab0e	1087	* @arg RCC_IT_MSIRDY: MSI ready interrupt
mbed_official	354:e67efb2aab0e	1088	* @arg RCC_IT_LSECSS: LSE CSS interrupt (not available for STM32L100xB \|\| STM32L151xB \|\| STM32L152xB device)
mbed_official	354:e67efb2aab0e	1089	*/
mbed_official	354:e67efb2aab0e	1090	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t ) CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
mbed_official	354:e67efb2aab0e	1091
mbed_official	354:e67efb2aab0e	1092	/** @brief Clear the RCC's interrupt pending bits ( Perform Byte access to RCC_CIR[23:16]
mbed_official	354:e67efb2aab0e	1093	* bits to clear the selected interrupt pending bits.
mbed_official	354:e67efb2aab0e	1094	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
mbed_official	354:e67efb2aab0e	1095	* This parameter can be any combination of the following values:
mbed_official	354:e67efb2aab0e	1096	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
mbed_official	354:e67efb2aab0e	1097	* @arg RCC_IT_LSERDY: LSE ready interrupt.
mbed_official	354:e67efb2aab0e	1098	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
mbed_official	354:e67efb2aab0e	1099	* @arg RCC_IT_HSERDY: HSE ready interrupt.
mbed_official	354:e67efb2aab0e	1100	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
mbed_official	354:e67efb2aab0e	1101	* @arg RCC_IT_MSIRDY: MSI ready interrupt.
mbed_official	354:e67efb2aab0e	1102	* @arg RCC_IT_LSECSS: LSE CSS interrupt (not available for STM32L100xB \|\| STM32L151xB \|\| STM32L152xB device)
mbed_official	354:e67efb2aab0e	1103	* @arg RCC_IT_CSS: Clock Security System interrupt
mbed_official	354:e67efb2aab0e	1104	*/
mbed_official	354:e67efb2aab0e	1105	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) ((__IO uint8_t ) CIR_BYTE2_ADDRESS = (__INTERRUPT__))
mbed_official	354:e67efb2aab0e	1106
mbed_official	354:e67efb2aab0e	1107	/** @brief Check the RCC's interrupt has occurred or not.
mbed_official	354:e67efb2aab0e	1108	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
mbed_official	354:e67efb2aab0e	1109	* This parameter can be one of the following values:
mbed_official	354:e67efb2aab0e	1110	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
mbed_official	354:e67efb2aab0e	1111	* @arg RCC_IT_LSERDY: LSE ready interrupt.
mbed_official	354:e67efb2aab0e	1112	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
mbed_official	354:e67efb2aab0e	1113	* @arg RCC_IT_HSERDY: HSE ready interrupt.
mbed_official	354:e67efb2aab0e	1114	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
mbed_official	354:e67efb2aab0e	1115	* @arg RCC_IT_MSIRDY: MSI ready interrupt.
mbed_official	354:e67efb2aab0e	1116	* @arg RCC_IT_LSECSS: LSE CSS interrupt (not available for STM32L100xB \|\| STM32L151xB \|\| STM32L152xB device)
mbed_official	354:e67efb2aab0e	1117	* @arg RCC_IT_CSS: Clock Security System interrupt
mbed_official	354:e67efb2aab0e	1118	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
mbed_official	354:e67efb2aab0e	1119	*/
mbed_official	354:e67efb2aab0e	1120	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
mbed_official	354:e67efb2aab0e	1121
mbed_official	354:e67efb2aab0e	1122	/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
mbed_official	354:e67efb2aab0e	1123	* RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
mbed_official	354:e67efb2aab0e	1124	*/
mbed_official	354:e67efb2aab0e	1125	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
mbed_official	354:e67efb2aab0e	1126
mbed_official	354:e67efb2aab0e	1127	/** @brief Check RCC flag is set or not.
mbed_official	354:e67efb2aab0e	1128	* @param __FLAG__: specifies the flag to check.
mbed_official	354:e67efb2aab0e	1129	* This parameter can be one of the following values:
mbed_official	354:e67efb2aab0e	1130	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
mbed_official	354:e67efb2aab0e	1131	* @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready.
mbed_official	354:e67efb2aab0e	1132	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
mbed_official	354:e67efb2aab0e	1133	* @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
mbed_official	354:e67efb2aab0e	1134	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
mbed_official	354:e67efb2aab0e	1135	* @arg RCC_FLAG_LSECSS: CSS on LSE failure Detection (*)
mbed_official	354:e67efb2aab0e	1136	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
mbed_official	354:e67efb2aab0e	1137	* @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
mbed_official	354:e67efb2aab0e	1138	* @arg RCC_FLAG_PINRST: Pin reset.
mbed_official	354:e67efb2aab0e	1139	* @arg RCC_FLAG_PORRST: POR/PDR reset.
mbed_official	354:e67efb2aab0e	1140	* @arg RCC_FLAG_SFTRST: Software reset.
mbed_official	354:e67efb2aab0e	1141	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
mbed_official	354:e67efb2aab0e	1142	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
mbed_official	354:e67efb2aab0e	1143	* @arg RCC_FLAG_LPWRRST: Low Power reset.
mbed_official	354:e67efb2aab0e	1144	* @note (*) This bit is available in high and medium+ density devices only.
mbed_official	354:e67efb2aab0e	1145	* @retval The new state of __FLAG__ (TRUE or FALSE).
mbed_official	354:e67efb2aab0e	1146	*/
mbed_official	354:e67efb2aab0e	1147	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR :RCC->CSR) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
mbed_official	354:e67efb2aab0e	1148
mbed_official	354:e67efb2aab0e	1149
mbed_official	354:e67efb2aab0e	1150	/** @brief Get oscillator clock selected as PLL input clock
mbed_official	354:e67efb2aab0e	1151	* @retval The clock source used for PLL entry. The returned value can be one
mbed_official	354:e67efb2aab0e	1152	* of the following:
mbed_official	354:e67efb2aab0e	1153	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL input clock
mbed_official	354:e67efb2aab0e	1154	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL input clock
mbed_official	354:e67efb2aab0e	1155	*/
mbed_official	354:e67efb2aab0e	1156	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((RCC->CFGR & RCC_CFGR_PLLSRC))
mbed_official	354:e67efb2aab0e	1157
mbed_official	354:e67efb2aab0e	1158	/**
mbed_official	354:e67efb2aab0e	1159	* @}
mbed_official	354:e67efb2aab0e	1160	*/
mbed_official	354:e67efb2aab0e	1161
mbed_official	354:e67efb2aab0e	1162	/* Include RCC HAL Extension module */
mbed_official	354:e67efb2aab0e	1163	#include "stm32l1xx_hal_rcc_ex.h"
mbed_official	354:e67efb2aab0e	1164
mbed_official	354:e67efb2aab0e	1165	/* Exported functions --------------------------------------------------------*/
mbed_official	354:e67efb2aab0e	1166	/** @addtogroup RCC_Private_Functions
mbed_official	354:e67efb2aab0e	1167	* @{
mbed_official	354:e67efb2aab0e	1168	*/
mbed_official	354:e67efb2aab0e	1169
mbed_official	354:e67efb2aab0e	1170	/** @addtogroup RCC_Exported_Functions_Group1
mbed_official	354:e67efb2aab0e	1171	* @{
mbed_official	354:e67efb2aab0e	1172	*/
mbed_official	354:e67efb2aab0e	1173
mbed_official	354:e67efb2aab0e	1174	/* Initialization and de-initialization functions ******************************/
mbed_official	354:e67efb2aab0e	1175	void HAL_RCC_DeInit(void);
mbed_official	354:e67efb2aab0e	1176	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
mbed_official	354:e67efb2aab0e	1177	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
mbed_official	354:e67efb2aab0e	1178
mbed_official	354:e67efb2aab0e	1179	/**
mbed_official	354:e67efb2aab0e	1180	* @}
mbed_official	354:e67efb2aab0e	1181	*/
mbed_official	354:e67efb2aab0e	1182
mbed_official	354:e67efb2aab0e	1183	/** @addtogroup RCC_Exported_Functions_Group2
mbed_official	354:e67efb2aab0e	1184	* @{
mbed_official	354:e67efb2aab0e	1185	*/
mbed_official	354:e67efb2aab0e	1186
mbed_official	354:e67efb2aab0e	1187	/* Peripheral Control functions ************************************************/
mbed_official	354:e67efb2aab0e	1188	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
mbed_official	354:e67efb2aab0e	1189	void HAL_RCC_EnableCSS(void);
mbed_official	354:e67efb2aab0e	1190	void HAL_RCC_DisableCSS(void);
mbed_official	354:e67efb2aab0e	1191	uint32_t HAL_RCC_GetSysClockFreq(void);
mbed_official	354:e67efb2aab0e	1192	uint32_t HAL_RCC_GetHCLKFreq(void);
mbed_official	354:e67efb2aab0e	1193	uint32_t HAL_RCC_GetPCLK1Freq(void);
mbed_official	354:e67efb2aab0e	1194	uint32_t HAL_RCC_GetPCLK2Freq(void);
mbed_official	354:e67efb2aab0e	1195	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
mbed_official	354:e67efb2aab0e	1196	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
mbed_official	354:e67efb2aab0e	1197
mbed_official	354:e67efb2aab0e	1198	/* CSS NMI IRQ handler */
mbed_official	354:e67efb2aab0e	1199	void HAL_RCC_NMI_IRQHandler(void);
mbed_official	354:e67efb2aab0e	1200
mbed_official	354:e67efb2aab0e	1201	/* User Callbacks in non blocking mode (IT mode) */
mbed_official	354:e67efb2aab0e	1202	void HAL_RCC_CCSCallback(void);
mbed_official	354:e67efb2aab0e	1203
mbed_official	354:e67efb2aab0e	1204	/**
mbed_official	354:e67efb2aab0e	1205	* @}
mbed_official	354:e67efb2aab0e	1206	*/
mbed_official	354:e67efb2aab0e	1207
mbed_official	354:e67efb2aab0e	1208	/**
mbed_official	354:e67efb2aab0e	1209	* @}
mbed_official	354:e67efb2aab0e	1210	*/
mbed_official	354:e67efb2aab0e	1211
mbed_official	354:e67efb2aab0e	1212	/**
mbed_official	354:e67efb2aab0e	1213	* @}
mbed_official	354:e67efb2aab0e	1214	*/
mbed_official	354:e67efb2aab0e	1215
mbed_official	354:e67efb2aab0e	1216	/**
mbed_official	354:e67efb2aab0e	1217	* @}
mbed_official	354:e67efb2aab0e	1218	*/
mbed_official	354:e67efb2aab0e	1219
mbed_official	354:e67efb2aab0e	1220	#ifdef __cplusplus
mbed_official	354:e67efb2aab0e	1221	}
mbed_official	354:e67efb2aab0e	1222	#endif
mbed_official	354:e67efb2aab0e	1223
mbed_official	354:e67efb2aab0e	1224	#endif /* __STM32L1xx_HAL_RCC_H */
mbed_official	354:e67efb2aab0e	1225
mbed_official	354:e67efb2aab0e	1226	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
mbed_official	354:e67efb2aab0e	1227

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Type:	Library
Created:	21 Jan 2016
Imports:	17
Forks:	0
Commits:	441
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targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rcc.h@394:83f921546702, 2014-11-07 (annotated)

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