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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F072RB/stm32f0xx_hal_tim.c@205:c41fc65bcfb4, 2014-05-22 (annotated)

Committer:
mbed_official
Date:
Thu May 22 20:00:09 2014 +0100
Revision:
205:c41fc65bcfb4
Child:
218:44081b78fdc2
Synchronized with git revision ea4b6f76efab17a3f7d7777b0cc1ef05fec6d1cb



Full URL: https://github.com/mbedmicro/mbed/commit/ea4b6f76efab17a3f7d7777b0cc1ef05fec6d1cb/



[NUCLEO_F072RB] cmsis files

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mbed_official 205:c41fc65bcfb4 1 /**
mbed_official 205:c41fc65bcfb4 2 ******************************************************************************
mbed_official 205:c41fc65bcfb4 3 * @file stm32f0xx_hal_tim.c
mbed_official 205:c41fc65bcfb4 4 * @author MCD Application Team
mbed_official 205:c41fc65bcfb4 5 * @version V1.0.0
mbed_official 205:c41fc65bcfb4 6 * @date 20-May-2014
mbed_official 205:c41fc65bcfb4 7 * @brief TIM HAL module driver.
mbed_official 205:c41fc65bcfb4 8 * This file provides firmware functions to manage the following
mbed_official 205:c41fc65bcfb4 9 * functionalities of the Timer (TIM) peripheral:
mbed_official 205:c41fc65bcfb4 10 * + Time Base Initialization
mbed_official 205:c41fc65bcfb4 11 * + Time Base Start
mbed_official 205:c41fc65bcfb4 12 * + Time Base Start Interruption
mbed_official 205:c41fc65bcfb4 13 * + Time Base Start DMA
mbed_official 205:c41fc65bcfb4 14 * + Time Output Compare/PWM Initialization
mbed_official 205:c41fc65bcfb4 15 * + Time Output Compare/PWM Channel Configuration
mbed_official 205:c41fc65bcfb4 16 * + Time Output Compare/PWM Start
mbed_official 205:c41fc65bcfb4 17 * + Time Output Compare/PWM Start Interruption
mbed_official 205:c41fc65bcfb4 18 * + Time Output Compare/PWM Start DMA
mbed_official 205:c41fc65bcfb4 19 * + Time Input Capture Initialization
mbed_official 205:c41fc65bcfb4 20 * + Time Input Capture Channel Configuration
mbed_official 205:c41fc65bcfb4 21 * + Time Input Capture Start
mbed_official 205:c41fc65bcfb4 22 * + Time Input Capture Start Interruption
mbed_official 205:c41fc65bcfb4 23 * + Time Input Capture Start DMA
mbed_official 205:c41fc65bcfb4 24 * + Time One Pulse Initialization
mbed_official 205:c41fc65bcfb4 25 * + Time One Pulse Channel Configuration
mbed_official 205:c41fc65bcfb4 26 * + Time One Pulse Start
mbed_official 205:c41fc65bcfb4 27 * + Time Encoder Interface Initialization
mbed_official 205:c41fc65bcfb4 28 * + Time Encoder Interface Start
mbed_official 205:c41fc65bcfb4 29 * + Time Encoder Interface Start Interruption
mbed_official 205:c41fc65bcfb4 30 * + Time Encoder Interface Start DMA
mbed_official 205:c41fc65bcfb4 31 * + Commutation Event configuration with Interruption and DMA
mbed_official 205:c41fc65bcfb4 32 * + Time OCRef clear configuration
mbed_official 205:c41fc65bcfb4 33 * + Time External Clock configuration
mbed_official 205:c41fc65bcfb4 34 @verbatim
mbed_official 205:c41fc65bcfb4 35 ==============================================================================
mbed_official 205:c41fc65bcfb4 36 ##### TIMER Generic features #####
mbed_official 205:c41fc65bcfb4 37 ==============================================================================
mbed_official 205:c41fc65bcfb4 38 [..] The Timer features include:
mbed_official 205:c41fc65bcfb4 39 (#) 16-bit up, down, up/down auto-reload counter.
mbed_official 205:c41fc65bcfb4 40 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
mbed_official 205:c41fc65bcfb4 41 counter clock frequency either by any factor between 1 and 65536.
mbed_official 205:c41fc65bcfb4 42 (#) Up to 4 independent channels for:
mbed_official 205:c41fc65bcfb4 43 (++) Input Capture
mbed_official 205:c41fc65bcfb4 44 (++) Output Compare
mbed_official 205:c41fc65bcfb4 45 (++) PWM generation (Edge and Center-aligned Mode)
mbed_official 205:c41fc65bcfb4 46 (++) One-pulse mode output
mbed_official 205:c41fc65bcfb4 47
mbed_official 205:c41fc65bcfb4 48 ##### How to use this driver #####
mbed_official 205:c41fc65bcfb4 49 ==============================================================================
mbed_official 205:c41fc65bcfb4 50 [..]
mbed_official 205:c41fc65bcfb4 51 (#) Initialize the TIM low level resources by implementing the following functions
mbed_official 205:c41fc65bcfb4 52 depending from feature used :
mbed_official 205:c41fc65bcfb4 53 (++) Time Base : HAL_TIM_Base_MspInit()
mbed_official 205:c41fc65bcfb4 54 (++) Input Capture : HAL_TIM_IC_MspInit()
mbed_official 205:c41fc65bcfb4 55 (++) Output Compare : HAL_TIM_OC_MspInit()
mbed_official 205:c41fc65bcfb4 56 (++) PWM generation : HAL_TIM_PWM_MspInit()
mbed_official 205:c41fc65bcfb4 57 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
mbed_official 205:c41fc65bcfb4 58 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
mbed_official 205:c41fc65bcfb4 59
mbed_official 205:c41fc65bcfb4 60 (#) Initialize the TIM low level resources :
mbed_official 205:c41fc65bcfb4 61 (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
mbed_official 205:c41fc65bcfb4 62 (##) TIM pins configuration
mbed_official 205:c41fc65bcfb4 63 (+++) Enable the clock for the TIM GPIOs using the following function:
mbed_official 205:c41fc65bcfb4 64 __GPIOx_CLK_ENABLE();
mbed_official 205:c41fc65bcfb4 65 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
mbed_official 205:c41fc65bcfb4 66
mbed_official 205:c41fc65bcfb4 67 (#) The external Clock can be configured, if needed (the default clock is the
mbed_official 205:c41fc65bcfb4 68 internal clock from the APBx), using the following function:
mbed_official 205:c41fc65bcfb4 69 HAL_TIM_ConfigClockSource, the clock configuration should be done before
mbed_official 205:c41fc65bcfb4 70 any start function.
mbed_official 205:c41fc65bcfb4 71
mbed_official 205:c41fc65bcfb4 72 (#) Configure the TIM in the desired functioning mode using one of the
mbed_official 205:c41fc65bcfb4 73 Initialization function of this driver:
mbed_official 205:c41fc65bcfb4 74 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
mbed_official 205:c41fc65bcfb4 75 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
mbed_official 205:c41fc65bcfb4 76 Output Compare signal.
mbed_official 205:c41fc65bcfb4 77 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
mbed_official 205:c41fc65bcfb4 78 PWM signal.
mbed_official 205:c41fc65bcfb4 79 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
mbed_official 205:c41fc65bcfb4 80 external signal.
mbed_official 205:c41fc65bcfb4 81 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
mbed_official 205:c41fc65bcfb4 82 in One Pulse Mode.
mbed_official 205:c41fc65bcfb4 83 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
mbed_official 205:c41fc65bcfb4 84
mbed_official 205:c41fc65bcfb4 85 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
mbed_official 205:c41fc65bcfb4 86 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
mbed_official 205:c41fc65bcfb4 87 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
mbed_official 205:c41fc65bcfb4 88 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
mbed_official 205:c41fc65bcfb4 89 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
mbed_official 205:c41fc65bcfb4 90 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
mbed_official 205:c41fc65bcfb4 91 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
mbed_official 205:c41fc65bcfb4 92
mbed_official 205:c41fc65bcfb4 93 (#) The DMA Burst is managed with the two following functions:
mbed_official 205:c41fc65bcfb4 94 HAL_TIM_DMABurst_WriteStart()
mbed_official 205:c41fc65bcfb4 95 HAL_TIM_DMABurst_ReadStart()
mbed_official 205:c41fc65bcfb4 96
mbed_official 205:c41fc65bcfb4 97 @endverbatim
mbed_official 205:c41fc65bcfb4 98 ******************************************************************************
mbed_official 205:c41fc65bcfb4 99 * @attention
mbed_official 205:c41fc65bcfb4 100 *
mbed_official 205:c41fc65bcfb4 101 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 205:c41fc65bcfb4 102 *
mbed_official 205:c41fc65bcfb4 103 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 205:c41fc65bcfb4 104 * are permitted provided that the following conditions are met:
mbed_official 205:c41fc65bcfb4 105 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 205:c41fc65bcfb4 106 * this list of conditions and the following disclaimer.
mbed_official 205:c41fc65bcfb4 107 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 205:c41fc65bcfb4 108 * this list of conditions and the following disclaimer in the documentation
mbed_official 205:c41fc65bcfb4 109 * and/or other materials provided with the distribution.
mbed_official 205:c41fc65bcfb4 110 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 205:c41fc65bcfb4 111 * may be used to endorse or promote products derived from this software
mbed_official 205:c41fc65bcfb4 112 * without specific prior written permission.
mbed_official 205:c41fc65bcfb4 113 *
mbed_official 205:c41fc65bcfb4 114 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 205:c41fc65bcfb4 115 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 205:c41fc65bcfb4 116 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 205:c41fc65bcfb4 117 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 205:c41fc65bcfb4 118 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 205:c41fc65bcfb4 119 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 205:c41fc65bcfb4 120 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 205:c41fc65bcfb4 121 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 205:c41fc65bcfb4 122 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 205:c41fc65bcfb4 123 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 205:c41fc65bcfb4 124 *
mbed_official 205:c41fc65bcfb4 125 ******************************************************************************
mbed_official 205:c41fc65bcfb4 126 */
mbed_official 205:c41fc65bcfb4 127
mbed_official 205:c41fc65bcfb4 128 /* Includes ------------------------------------------------------------------*/
mbed_official 205:c41fc65bcfb4 129 #include "stm32f0xx_hal.h"
mbed_official 205:c41fc65bcfb4 130
mbed_official 205:c41fc65bcfb4 131 /** @addtogroup STM32F0xx_HAL_Driver
mbed_official 205:c41fc65bcfb4 132 * @{
mbed_official 205:c41fc65bcfb4 133 */
mbed_official 205:c41fc65bcfb4 134
mbed_official 205:c41fc65bcfb4 135 /** @defgroup TIM
mbed_official 205:c41fc65bcfb4 136 * @brief TIM HAL module driver
mbed_official 205:c41fc65bcfb4 137 * @{
mbed_official 205:c41fc65bcfb4 138 */
mbed_official 205:c41fc65bcfb4 139
mbed_official 205:c41fc65bcfb4 140 #ifdef HAL_TIM_MODULE_ENABLED
mbed_official 205:c41fc65bcfb4 141
mbed_official 205:c41fc65bcfb4 142 /* Private typedef -----------------------------------------------------------*/
mbed_official 205:c41fc65bcfb4 143 /* Private define ------------------------------------------------------------*/
mbed_official 205:c41fc65bcfb4 144 /* Private macro -------------------------------------------------------------*/
mbed_official 205:c41fc65bcfb4 145 /* Private variables ---------------------------------------------------------*/
mbed_official 205:c41fc65bcfb4 146 /* Private function prototypes -----------------------------------------------*/
mbed_official 205:c41fc65bcfb4 147 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
mbed_official 205:c41fc65bcfb4 148 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
mbed_official 205:c41fc65bcfb4 149 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
mbed_official 205:c41fc65bcfb4 150
mbed_official 205:c41fc65bcfb4 151 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
mbed_official 205:c41fc65bcfb4 152 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 205:c41fc65bcfb4 153 uint32_t TIM_ICFilter);
mbed_official 205:c41fc65bcfb4 154 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
mbed_official 205:c41fc65bcfb4 155 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 205:c41fc65bcfb4 156 uint32_t TIM_ICFilter);
mbed_official 205:c41fc65bcfb4 157 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 205:c41fc65bcfb4 158 uint32_t TIM_ICFilter);
mbed_official 205:c41fc65bcfb4 159
mbed_official 205:c41fc65bcfb4 160 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
mbed_official 205:c41fc65bcfb4 161 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
mbed_official 205:c41fc65bcfb4 162
mbed_official 205:c41fc65bcfb4 163 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
mbed_official 205:c41fc65bcfb4 164 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
mbed_official 205:c41fc65bcfb4 165 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
mbed_official 205:c41fc65bcfb4 166 /* Private functions ---------------------------------------------------------*/
mbed_official 205:c41fc65bcfb4 167
mbed_official 205:c41fc65bcfb4 168 /** @defgroup TIM_Private_Functions
mbed_official 205:c41fc65bcfb4 169 * @{
mbed_official 205:c41fc65bcfb4 170 */
mbed_official 205:c41fc65bcfb4 171
mbed_official 205:c41fc65bcfb4 172 /** @defgroup TIM_Group1 Time Base functions
mbed_official 205:c41fc65bcfb4 173 * @brief Time Base functions
mbed_official 205:c41fc65bcfb4 174 *
mbed_official 205:c41fc65bcfb4 175 @verbatim
mbed_official 205:c41fc65bcfb4 176 ==============================================================================
mbed_official 205:c41fc65bcfb4 177 ##### Time Base functions #####
mbed_official 205:c41fc65bcfb4 178 ==============================================================================
mbed_official 205:c41fc65bcfb4 179 [..]
mbed_official 205:c41fc65bcfb4 180 This section provides functions allowing to:
mbed_official 205:c41fc65bcfb4 181 (+) Initialize and configure the TIM base.
mbed_official 205:c41fc65bcfb4 182 (+) De-initialize the TIM base.
mbed_official 205:c41fc65bcfb4 183 (+) Start the Time Base.
mbed_official 205:c41fc65bcfb4 184 (+) Stop the Time Base.
mbed_official 205:c41fc65bcfb4 185 (+) Start the Time Base and enable interrupt.
mbed_official 205:c41fc65bcfb4 186 (+) Stop the Time Base and disable interrupt.
mbed_official 205:c41fc65bcfb4 187 (+) Start the Time Base and enable DMA transfer.
mbed_official 205:c41fc65bcfb4 188 (+) Stop the Time Base and disable DMA transfer.
mbed_official 205:c41fc65bcfb4 189
mbed_official 205:c41fc65bcfb4 190 @endverbatim
mbed_official 205:c41fc65bcfb4 191 * @{
mbed_official 205:c41fc65bcfb4 192 */
mbed_official 205:c41fc65bcfb4 193 /**
mbed_official 205:c41fc65bcfb4 194 * @brief Initializes the TIM Time base Unit according to the specified
mbed_official 205:c41fc65bcfb4 195 * parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official 205:c41fc65bcfb4 196 * @param htim: TIM Base handle
mbed_official 205:c41fc65bcfb4 197 * @retval HAL status
mbed_official 205:c41fc65bcfb4 198 */
mbed_official 205:c41fc65bcfb4 199 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 200 {
mbed_official 205:c41fc65bcfb4 201 /* Check the TIM handle allocation */
mbed_official 205:c41fc65bcfb4 202 if(htim == NULL)
mbed_official 205:c41fc65bcfb4 203 {
mbed_official 205:c41fc65bcfb4 204 return HAL_ERROR;
mbed_official 205:c41fc65bcfb4 205 }
mbed_official 205:c41fc65bcfb4 206
mbed_official 205:c41fc65bcfb4 207 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 208 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 209 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official 205:c41fc65bcfb4 210 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official 205:c41fc65bcfb4 211
mbed_official 205:c41fc65bcfb4 212 if(htim->State == HAL_TIM_STATE_RESET)
mbed_official 205:c41fc65bcfb4 213 {
mbed_official 205:c41fc65bcfb4 214 /* Init the low level hardware : GPIO, CLOCK, NVIC */
mbed_official 205:c41fc65bcfb4 215 HAL_TIM_Base_MspInit(htim);
mbed_official 205:c41fc65bcfb4 216 }
mbed_official 205:c41fc65bcfb4 217
mbed_official 205:c41fc65bcfb4 218 /* Set the TIM state */
mbed_official 205:c41fc65bcfb4 219 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 205:c41fc65bcfb4 220
mbed_official 205:c41fc65bcfb4 221 /* Set the Time Base configuration */
mbed_official 205:c41fc65bcfb4 222 TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official 205:c41fc65bcfb4 223
mbed_official 205:c41fc65bcfb4 224 /* Initialize the TIM state*/
mbed_official 205:c41fc65bcfb4 225 htim->State= HAL_TIM_STATE_READY;
mbed_official 205:c41fc65bcfb4 226
mbed_official 205:c41fc65bcfb4 227 return HAL_OK;
mbed_official 205:c41fc65bcfb4 228 }
mbed_official 205:c41fc65bcfb4 229
mbed_official 205:c41fc65bcfb4 230 /**
mbed_official 205:c41fc65bcfb4 231 * @brief DeInitializes the TIM Base peripheral
mbed_official 205:c41fc65bcfb4 232 * @param htim: TIM Base handle
mbed_official 205:c41fc65bcfb4 233 * @retval HAL status
mbed_official 205:c41fc65bcfb4 234 */
mbed_official 205:c41fc65bcfb4 235 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 236 {
mbed_official 205:c41fc65bcfb4 237 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 238 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 239
mbed_official 205:c41fc65bcfb4 240 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 205:c41fc65bcfb4 241
mbed_official 205:c41fc65bcfb4 242 /* Disable the TIM Peripheral Clock */
mbed_official 205:c41fc65bcfb4 243 __HAL_TIM_DISABLE(htim);
mbed_official 205:c41fc65bcfb4 244
mbed_official 205:c41fc65bcfb4 245 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
mbed_official 205:c41fc65bcfb4 246 HAL_TIM_Base_MspDeInit(htim);
mbed_official 205:c41fc65bcfb4 247
mbed_official 205:c41fc65bcfb4 248 /* Change TIM state */
mbed_official 205:c41fc65bcfb4 249 htim->State = HAL_TIM_STATE_RESET;
mbed_official 205:c41fc65bcfb4 250
mbed_official 205:c41fc65bcfb4 251 /* Release Lock */
mbed_official 205:c41fc65bcfb4 252 __HAL_UNLOCK(htim);
mbed_official 205:c41fc65bcfb4 253
mbed_official 205:c41fc65bcfb4 254 return HAL_OK;
mbed_official 205:c41fc65bcfb4 255 }
mbed_official 205:c41fc65bcfb4 256
mbed_official 205:c41fc65bcfb4 257 /**
mbed_official 205:c41fc65bcfb4 258 * @brief Initializes the TIM Base MSP.
mbed_official 205:c41fc65bcfb4 259 * @param htim: TIM handle
mbed_official 205:c41fc65bcfb4 260 * @retval None
mbed_official 205:c41fc65bcfb4 261 */
mbed_official 205:c41fc65bcfb4 262 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 263 {
mbed_official 205:c41fc65bcfb4 264 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 205:c41fc65bcfb4 265 the HAL_TIM_Base_MspInit could be implemented in the user file
mbed_official 205:c41fc65bcfb4 266 */
mbed_official 205:c41fc65bcfb4 267 }
mbed_official 205:c41fc65bcfb4 268
mbed_official 205:c41fc65bcfb4 269 /**
mbed_official 205:c41fc65bcfb4 270 * @brief DeInitializes TIM Base MSP.
mbed_official 205:c41fc65bcfb4 271 * @param htim: TIM handle
mbed_official 205:c41fc65bcfb4 272 * @retval None
mbed_official 205:c41fc65bcfb4 273 */
mbed_official 205:c41fc65bcfb4 274 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 275 {
mbed_official 205:c41fc65bcfb4 276 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 205:c41fc65bcfb4 277 the HAL_TIM_Base_MspDeInit could be implemented in the user file
mbed_official 205:c41fc65bcfb4 278 */
mbed_official 205:c41fc65bcfb4 279 }
mbed_official 205:c41fc65bcfb4 280
mbed_official 205:c41fc65bcfb4 281
mbed_official 205:c41fc65bcfb4 282 /**
mbed_official 205:c41fc65bcfb4 283 * @brief Starts the TIM Base generation.
mbed_official 205:c41fc65bcfb4 284 * @param htim : TIM handle
mbed_official 205:c41fc65bcfb4 285 * @retval HAL status
mbed_official 205:c41fc65bcfb4 286 */
mbed_official 205:c41fc65bcfb4 287 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 288 {
mbed_official 205:c41fc65bcfb4 289 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 290 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 291
mbed_official 205:c41fc65bcfb4 292 /* Set the TIM state */
mbed_official 205:c41fc65bcfb4 293 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 205:c41fc65bcfb4 294
mbed_official 205:c41fc65bcfb4 295 /* Enable the Peripheral */
mbed_official 205:c41fc65bcfb4 296 __HAL_TIM_ENABLE(htim);
mbed_official 205:c41fc65bcfb4 297
mbed_official 205:c41fc65bcfb4 298 /* Change the TIM state*/
mbed_official 205:c41fc65bcfb4 299 htim->State= HAL_TIM_STATE_READY;
mbed_official 205:c41fc65bcfb4 300
mbed_official 205:c41fc65bcfb4 301 /* Return function status */
mbed_official 205:c41fc65bcfb4 302 return HAL_OK;
mbed_official 205:c41fc65bcfb4 303 }
mbed_official 205:c41fc65bcfb4 304
mbed_official 205:c41fc65bcfb4 305 /**
mbed_official 205:c41fc65bcfb4 306 * @brief Stops the TIM Base generation.
mbed_official 205:c41fc65bcfb4 307 * @param htim : TIM handle
mbed_official 205:c41fc65bcfb4 308 * @retval HAL status
mbed_official 205:c41fc65bcfb4 309 */
mbed_official 205:c41fc65bcfb4 310 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 311 {
mbed_official 205:c41fc65bcfb4 312 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 313 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 314
mbed_official 205:c41fc65bcfb4 315 /* Set the TIM state */
mbed_official 205:c41fc65bcfb4 316 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 205:c41fc65bcfb4 317
mbed_official 205:c41fc65bcfb4 318 /* Disable the Peripheral */
mbed_official 205:c41fc65bcfb4 319 __HAL_TIM_DISABLE(htim);
mbed_official 205:c41fc65bcfb4 320
mbed_official 205:c41fc65bcfb4 321 /* Change the TIM state*/
mbed_official 205:c41fc65bcfb4 322 htim->State= HAL_TIM_STATE_READY;
mbed_official 205:c41fc65bcfb4 323
mbed_official 205:c41fc65bcfb4 324 /* Return function status */
mbed_official 205:c41fc65bcfb4 325 return HAL_OK;
mbed_official 205:c41fc65bcfb4 326 }
mbed_official 205:c41fc65bcfb4 327
mbed_official 205:c41fc65bcfb4 328 /**
mbed_official 205:c41fc65bcfb4 329 * @brief Starts the TIM Base generation in interrupt mode.
mbed_official 205:c41fc65bcfb4 330 * @param htim : TIM handle
mbed_official 205:c41fc65bcfb4 331 * @retval HAL status
mbed_official 205:c41fc65bcfb4 332 */
mbed_official 205:c41fc65bcfb4 333 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 334 {
mbed_official 205:c41fc65bcfb4 335 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 336 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 337
mbed_official 205:c41fc65bcfb4 338 /* Enable the TIM Update interrupt */
mbed_official 205:c41fc65bcfb4 339 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
mbed_official 205:c41fc65bcfb4 340
mbed_official 205:c41fc65bcfb4 341 /* Enable the Peripheral */
mbed_official 205:c41fc65bcfb4 342 __HAL_TIM_ENABLE(htim);
mbed_official 205:c41fc65bcfb4 343
mbed_official 205:c41fc65bcfb4 344 /* Return function status */
mbed_official 205:c41fc65bcfb4 345 return HAL_OK;
mbed_official 205:c41fc65bcfb4 346 }
mbed_official 205:c41fc65bcfb4 347
mbed_official 205:c41fc65bcfb4 348 /**
mbed_official 205:c41fc65bcfb4 349 * @brief Stops the TIM Base generation in interrupt mode.
mbed_official 205:c41fc65bcfb4 350 * @param htim : TIM handle
mbed_official 205:c41fc65bcfb4 351 * @retval HAL status
mbed_official 205:c41fc65bcfb4 352 */
mbed_official 205:c41fc65bcfb4 353 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 354 {
mbed_official 205:c41fc65bcfb4 355 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 356 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 357 /* Disable the TIM Update interrupt */
mbed_official 205:c41fc65bcfb4 358 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
mbed_official 205:c41fc65bcfb4 359
mbed_official 205:c41fc65bcfb4 360 /* Disable the Peripheral */
mbed_official 205:c41fc65bcfb4 361 __HAL_TIM_DISABLE(htim);
mbed_official 205:c41fc65bcfb4 362
mbed_official 205:c41fc65bcfb4 363 /* Return function status */
mbed_official 205:c41fc65bcfb4 364 return HAL_OK;
mbed_official 205:c41fc65bcfb4 365 }
mbed_official 205:c41fc65bcfb4 366
mbed_official 205:c41fc65bcfb4 367 /**
mbed_official 205:c41fc65bcfb4 368 * @brief Starts the TIM Base generation in DMA mode.
mbed_official 205:c41fc65bcfb4 369 * @param htim : TIM handle
mbed_official 205:c41fc65bcfb4 370 * @param pData: The source Buffer address.
mbed_official 205:c41fc65bcfb4 371 * @param Length: The length of data to be transferred from memory to peripheral.
mbed_official 205:c41fc65bcfb4 372 * @retval HAL status
mbed_official 205:c41fc65bcfb4 373 */
mbed_official 205:c41fc65bcfb4 374 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
mbed_official 205:c41fc65bcfb4 375 {
mbed_official 205:c41fc65bcfb4 376 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 377 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 378
mbed_official 205:c41fc65bcfb4 379 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 205:c41fc65bcfb4 380 {
mbed_official 205:c41fc65bcfb4 381 return HAL_BUSY;
mbed_official 205:c41fc65bcfb4 382 }
mbed_official 205:c41fc65bcfb4 383 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 205:c41fc65bcfb4 384 {
mbed_official 205:c41fc65bcfb4 385 if((pData == 0 ) && (Length > 0))
mbed_official 205:c41fc65bcfb4 386 {
mbed_official 205:c41fc65bcfb4 387 return HAL_ERROR;
mbed_official 205:c41fc65bcfb4 388 }
mbed_official 205:c41fc65bcfb4 389 else
mbed_official 205:c41fc65bcfb4 390 {
mbed_official 205:c41fc65bcfb4 391 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 205:c41fc65bcfb4 392 }
mbed_official 205:c41fc65bcfb4 393 }
mbed_official 205:c41fc65bcfb4 394 /* Set the DMA Period elapsed callback */
mbed_official 205:c41fc65bcfb4 395 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
mbed_official 205:c41fc65bcfb4 396
mbed_official 205:c41fc65bcfb4 397 /* Set the DMA error callback */
mbed_official 205:c41fc65bcfb4 398 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 205:c41fc65bcfb4 399
mbed_official 205:c41fc65bcfb4 400 /* Enable the DMA channel */
mbed_official 205:c41fc65bcfb4 401 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
mbed_official 205:c41fc65bcfb4 402
mbed_official 205:c41fc65bcfb4 403 /* Enable the TIM Update DMA request */
mbed_official 205:c41fc65bcfb4 404 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
mbed_official 205:c41fc65bcfb4 405
mbed_official 205:c41fc65bcfb4 406 /* Enable the Peripheral */
mbed_official 205:c41fc65bcfb4 407 __HAL_TIM_ENABLE(htim);
mbed_official 205:c41fc65bcfb4 408
mbed_official 205:c41fc65bcfb4 409 /* Return function status */
mbed_official 205:c41fc65bcfb4 410 return HAL_OK;
mbed_official 205:c41fc65bcfb4 411 }
mbed_official 205:c41fc65bcfb4 412
mbed_official 205:c41fc65bcfb4 413 /**
mbed_official 205:c41fc65bcfb4 414 * @brief Stops the TIM Base generation in DMA mode.
mbed_official 205:c41fc65bcfb4 415 * @param htim : TIM handle
mbed_official 205:c41fc65bcfb4 416 * @retval HAL status
mbed_official 205:c41fc65bcfb4 417 */
mbed_official 205:c41fc65bcfb4 418 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 419 {
mbed_official 205:c41fc65bcfb4 420 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 421 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 422
mbed_official 205:c41fc65bcfb4 423 /* Disable the TIM Update DMA request */
mbed_official 205:c41fc65bcfb4 424 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
mbed_official 205:c41fc65bcfb4 425
mbed_official 205:c41fc65bcfb4 426 /* Disable the Peripheral */
mbed_official 205:c41fc65bcfb4 427 __HAL_TIM_DISABLE(htim);
mbed_official 205:c41fc65bcfb4 428
mbed_official 205:c41fc65bcfb4 429 /* Change the htim state */
mbed_official 205:c41fc65bcfb4 430 htim->State = HAL_TIM_STATE_READY;
mbed_official 205:c41fc65bcfb4 431
mbed_official 205:c41fc65bcfb4 432 /* Return function status */
mbed_official 205:c41fc65bcfb4 433 return HAL_OK;
mbed_official 205:c41fc65bcfb4 434 }
mbed_official 205:c41fc65bcfb4 435
mbed_official 205:c41fc65bcfb4 436 /**
mbed_official 205:c41fc65bcfb4 437 * @}
mbed_official 205:c41fc65bcfb4 438 */
mbed_official 205:c41fc65bcfb4 439
mbed_official 205:c41fc65bcfb4 440 /** @defgroup TIM_Group2 Time Output Compare functions
mbed_official 205:c41fc65bcfb4 441 * @brief Time Output Compare functions
mbed_official 205:c41fc65bcfb4 442 *
mbed_official 205:c41fc65bcfb4 443 @verbatim
mbed_official 205:c41fc65bcfb4 444 ==============================================================================
mbed_official 205:c41fc65bcfb4 445 ##### Time Output Compare functions #####
mbed_official 205:c41fc65bcfb4 446 ==============================================================================
mbed_official 205:c41fc65bcfb4 447 [..]
mbed_official 205:c41fc65bcfb4 448 This section provides functions allowing to:
mbed_official 205:c41fc65bcfb4 449 (+) Initialize and configure the TIM Output Compare.
mbed_official 205:c41fc65bcfb4 450 (+) De-initialize the TIM Output Compare.
mbed_official 205:c41fc65bcfb4 451 (+) Start the Time Output Compare.
mbed_official 205:c41fc65bcfb4 452 (+) Stop the Time Output Compare.
mbed_official 205:c41fc65bcfb4 453 (+) Start the Time Output Compare and enable interrupt.
mbed_official 205:c41fc65bcfb4 454 (+) Stop the Time Output Compare and disable interrupt.
mbed_official 205:c41fc65bcfb4 455 (+) Start the Time Output Compare and enable DMA transfer.
mbed_official 205:c41fc65bcfb4 456 (+) Stop the Time Output Compare and disable DMA transfer.
mbed_official 205:c41fc65bcfb4 457
mbed_official 205:c41fc65bcfb4 458 @endverbatim
mbed_official 205:c41fc65bcfb4 459 * @{
mbed_official 205:c41fc65bcfb4 460 */
mbed_official 205:c41fc65bcfb4 461 /**
mbed_official 205:c41fc65bcfb4 462 * @brief Initializes the TIM Output Compare according to the specified
mbed_official 205:c41fc65bcfb4 463 * parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official 205:c41fc65bcfb4 464 * @param htim: TIM Output Compare handle
mbed_official 205:c41fc65bcfb4 465 * @retval HAL status
mbed_official 205:c41fc65bcfb4 466 */
mbed_official 205:c41fc65bcfb4 467 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
mbed_official 205:c41fc65bcfb4 468 {
mbed_official 205:c41fc65bcfb4 469 /* Check the TIM handle allocation */
mbed_official 205:c41fc65bcfb4 470 if(htim == NULL)
mbed_official 205:c41fc65bcfb4 471 {
mbed_official 205:c41fc65bcfb4 472 return HAL_ERROR;
mbed_official 205:c41fc65bcfb4 473 }
mbed_official 205:c41fc65bcfb4 474
mbed_official 205:c41fc65bcfb4 475 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 476 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 477 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official 205:c41fc65bcfb4 478 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official 205:c41fc65bcfb4 479
mbed_official 205:c41fc65bcfb4 480 if(htim->State == HAL_TIM_STATE_RESET)
mbed_official 205:c41fc65bcfb4 481 {
mbed_official 205:c41fc65bcfb4 482 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official 205:c41fc65bcfb4 483 HAL_TIM_OC_MspInit(htim);
mbed_official 205:c41fc65bcfb4 484 }
mbed_official 205:c41fc65bcfb4 485
mbed_official 205:c41fc65bcfb4 486 /* Set the TIM state */
mbed_official 205:c41fc65bcfb4 487 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 205:c41fc65bcfb4 488
mbed_official 205:c41fc65bcfb4 489 /* Init the base time for the Output Compare */
mbed_official 205:c41fc65bcfb4 490 TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official 205:c41fc65bcfb4 491
mbed_official 205:c41fc65bcfb4 492 /* Initialize the TIM state*/
mbed_official 205:c41fc65bcfb4 493 htim->State= HAL_TIM_STATE_READY;
mbed_official 205:c41fc65bcfb4 494
mbed_official 205:c41fc65bcfb4 495 return HAL_OK;
mbed_official 205:c41fc65bcfb4 496 }
mbed_official 205:c41fc65bcfb4 497
mbed_official 205:c41fc65bcfb4 498 /**
mbed_official 205:c41fc65bcfb4 499 * @brief DeInitializes the TIM peripheral
mbed_official 205:c41fc65bcfb4 500 * @param htim: TIM Output Compare handle
mbed_official 205:c41fc65bcfb4 501 * @retval HAL status
mbed_official 205:c41fc65bcfb4 502 */
mbed_official 205:c41fc65bcfb4 503 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 504 {
mbed_official 205:c41fc65bcfb4 505 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 506 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 507
mbed_official 205:c41fc65bcfb4 508 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 205:c41fc65bcfb4 509
mbed_official 205:c41fc65bcfb4 510 /* Disable the TIM Peripheral Clock */
mbed_official 205:c41fc65bcfb4 511 __HAL_TIM_DISABLE(htim);
mbed_official 205:c41fc65bcfb4 512
mbed_official 205:c41fc65bcfb4 513 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
mbed_official 205:c41fc65bcfb4 514 HAL_TIM_OC_MspDeInit(htim);
mbed_official 205:c41fc65bcfb4 515
mbed_official 205:c41fc65bcfb4 516 /* Change TIM state */
mbed_official 205:c41fc65bcfb4 517 htim->State = HAL_TIM_STATE_RESET;
mbed_official 205:c41fc65bcfb4 518
mbed_official 205:c41fc65bcfb4 519 /* Release Lock */
mbed_official 205:c41fc65bcfb4 520 __HAL_UNLOCK(htim);
mbed_official 205:c41fc65bcfb4 521
mbed_official 205:c41fc65bcfb4 522 return HAL_OK;
mbed_official 205:c41fc65bcfb4 523 }
mbed_official 205:c41fc65bcfb4 524
mbed_official 205:c41fc65bcfb4 525 /**
mbed_official 205:c41fc65bcfb4 526 * @brief Initializes the TIM Output Compare MSP.
mbed_official 205:c41fc65bcfb4 527 * @param htim: TIM handle
mbed_official 205:c41fc65bcfb4 528 * @retval None
mbed_official 205:c41fc65bcfb4 529 */
mbed_official 205:c41fc65bcfb4 530 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 531 {
mbed_official 205:c41fc65bcfb4 532 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 205:c41fc65bcfb4 533 the HAL_TIM_OC_MspInit could be implemented in the user file
mbed_official 205:c41fc65bcfb4 534 */
mbed_official 205:c41fc65bcfb4 535 }
mbed_official 205:c41fc65bcfb4 536
mbed_official 205:c41fc65bcfb4 537 /**
mbed_official 205:c41fc65bcfb4 538 * @brief DeInitializes TIM Output Compare MSP.
mbed_official 205:c41fc65bcfb4 539 * @param htim: TIM handle
mbed_official 205:c41fc65bcfb4 540 * @retval None
mbed_official 205:c41fc65bcfb4 541 */
mbed_official 205:c41fc65bcfb4 542 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 543 {
mbed_official 205:c41fc65bcfb4 544 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 205:c41fc65bcfb4 545 the HAL_TIM_OC_MspDeInit could be implemented in the user file
mbed_official 205:c41fc65bcfb4 546 */
mbed_official 205:c41fc65bcfb4 547 }
mbed_official 205:c41fc65bcfb4 548
mbed_official 205:c41fc65bcfb4 549 /**
mbed_official 205:c41fc65bcfb4 550 * @brief Starts the TIM Output Compare signal generation.
mbed_official 205:c41fc65bcfb4 551 * @param htim : TIM Output Compare handle
mbed_official 205:c41fc65bcfb4 552 * @param Channel : TIM Channel to be enabled
mbed_official 205:c41fc65bcfb4 553 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 554 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 205:c41fc65bcfb4 555 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 205:c41fc65bcfb4 556 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 205:c41fc65bcfb4 557 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 205:c41fc65bcfb4 558 * @retval HAL status
mbed_official 205:c41fc65bcfb4 559 */
mbed_official 205:c41fc65bcfb4 560 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 205:c41fc65bcfb4 561 {
mbed_official 205:c41fc65bcfb4 562 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 563 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 205:c41fc65bcfb4 564
mbed_official 205:c41fc65bcfb4 565 /* Enable the Output compare channel */
mbed_official 205:c41fc65bcfb4 566 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 205:c41fc65bcfb4 567
mbed_official 205:c41fc65bcfb4 568 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official 205:c41fc65bcfb4 569 {
mbed_official 205:c41fc65bcfb4 570 /* Enable the main output */
mbed_official 205:c41fc65bcfb4 571 __HAL_TIM_MOE_ENABLE(htim);
mbed_official 205:c41fc65bcfb4 572 }
mbed_official 205:c41fc65bcfb4 573
mbed_official 205:c41fc65bcfb4 574 /* Enable the Peripheral */
mbed_official 205:c41fc65bcfb4 575 __HAL_TIM_ENABLE(htim);
mbed_official 205:c41fc65bcfb4 576
mbed_official 205:c41fc65bcfb4 577 /* Return function status */
mbed_official 205:c41fc65bcfb4 578 return HAL_OK;
mbed_official 205:c41fc65bcfb4 579 }
mbed_official 205:c41fc65bcfb4 580
mbed_official 205:c41fc65bcfb4 581 /**
mbed_official 205:c41fc65bcfb4 582 * @brief Stops the TIM Output Compare signal generation.
mbed_official 205:c41fc65bcfb4 583 * @param htim : TIM handle
mbed_official 205:c41fc65bcfb4 584 * @param Channel : TIM Channel to be disabled
mbed_official 205:c41fc65bcfb4 585 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 586 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 205:c41fc65bcfb4 587 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 205:c41fc65bcfb4 588 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 205:c41fc65bcfb4 589 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 205:c41fc65bcfb4 590 * @retval HAL status
mbed_official 205:c41fc65bcfb4 591 */
mbed_official 205:c41fc65bcfb4 592 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 205:c41fc65bcfb4 593 {
mbed_official 205:c41fc65bcfb4 594 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 595 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 205:c41fc65bcfb4 596
mbed_official 205:c41fc65bcfb4 597 /* Disable the Output compare channel */
mbed_official 205:c41fc65bcfb4 598 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 205:c41fc65bcfb4 599
mbed_official 205:c41fc65bcfb4 600 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official 205:c41fc65bcfb4 601 {
mbed_official 205:c41fc65bcfb4 602 /* Disable the Main Ouput */
mbed_official 205:c41fc65bcfb4 603 __HAL_TIM_MOE_DISABLE(htim);
mbed_official 205:c41fc65bcfb4 604 }
mbed_official 205:c41fc65bcfb4 605
mbed_official 205:c41fc65bcfb4 606 /* Disable the Peripheral */
mbed_official 205:c41fc65bcfb4 607 __HAL_TIM_DISABLE(htim);
mbed_official 205:c41fc65bcfb4 608
mbed_official 205:c41fc65bcfb4 609 /* Return function status */
mbed_official 205:c41fc65bcfb4 610 return HAL_OK;
mbed_official 205:c41fc65bcfb4 611 }
mbed_official 205:c41fc65bcfb4 612
mbed_official 205:c41fc65bcfb4 613 /**
mbed_official 205:c41fc65bcfb4 614 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
mbed_official 205:c41fc65bcfb4 615 * @param htim : TIM OC handle
mbed_official 205:c41fc65bcfb4 616 * @param Channel : TIM Channel to be enabled
mbed_official 205:c41fc65bcfb4 617 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 618 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 205:c41fc65bcfb4 619 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 205:c41fc65bcfb4 620 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 205:c41fc65bcfb4 621 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 205:c41fc65bcfb4 622 * @retval HAL status
mbed_official 205:c41fc65bcfb4 623 */
mbed_official 205:c41fc65bcfb4 624 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 205:c41fc65bcfb4 625 {
mbed_official 205:c41fc65bcfb4 626 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 627 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 205:c41fc65bcfb4 628
mbed_official 205:c41fc65bcfb4 629 switch (Channel)
mbed_official 205:c41fc65bcfb4 630 {
mbed_official 205:c41fc65bcfb4 631 case TIM_CHANNEL_1:
mbed_official 205:c41fc65bcfb4 632 {
mbed_official 205:c41fc65bcfb4 633 /* Enable the TIM Capture/Compare 1 interrupt */
mbed_official 205:c41fc65bcfb4 634 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official 205:c41fc65bcfb4 635 }
mbed_official 205:c41fc65bcfb4 636 break;
mbed_official 205:c41fc65bcfb4 637
mbed_official 205:c41fc65bcfb4 638 case TIM_CHANNEL_2:
mbed_official 205:c41fc65bcfb4 639 {
mbed_official 205:c41fc65bcfb4 640 /* Enable the TIM Capture/Compare 2 interrupt */
mbed_official 205:c41fc65bcfb4 641 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official 205:c41fc65bcfb4 642 }
mbed_official 205:c41fc65bcfb4 643 break;
mbed_official 205:c41fc65bcfb4 644
mbed_official 205:c41fc65bcfb4 645 case TIM_CHANNEL_3:
mbed_official 205:c41fc65bcfb4 646 {
mbed_official 205:c41fc65bcfb4 647 /* Enable the TIM Capture/Compare 3 interrupt */
mbed_official 205:c41fc65bcfb4 648 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
mbed_official 205:c41fc65bcfb4 649 }
mbed_official 205:c41fc65bcfb4 650 break;
mbed_official 205:c41fc65bcfb4 651
mbed_official 205:c41fc65bcfb4 652 case TIM_CHANNEL_4:
mbed_official 205:c41fc65bcfb4 653 {
mbed_official 205:c41fc65bcfb4 654 /* Enable the TIM Capture/Compare 4 interrupt */
mbed_official 205:c41fc65bcfb4 655 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
mbed_official 205:c41fc65bcfb4 656 }
mbed_official 205:c41fc65bcfb4 657 break;
mbed_official 205:c41fc65bcfb4 658
mbed_official 205:c41fc65bcfb4 659 default:
mbed_official 205:c41fc65bcfb4 660 break;
mbed_official 205:c41fc65bcfb4 661 }
mbed_official 205:c41fc65bcfb4 662
mbed_official 205:c41fc65bcfb4 663 /* Enable the Output compare channel */
mbed_official 205:c41fc65bcfb4 664 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 205:c41fc65bcfb4 665
mbed_official 205:c41fc65bcfb4 666 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official 205:c41fc65bcfb4 667 {
mbed_official 205:c41fc65bcfb4 668 /* Enable the main output */
mbed_official 205:c41fc65bcfb4 669 __HAL_TIM_MOE_ENABLE(htim);
mbed_official 205:c41fc65bcfb4 670 }
mbed_official 205:c41fc65bcfb4 671
mbed_official 205:c41fc65bcfb4 672 /* Enable the Peripheral */
mbed_official 205:c41fc65bcfb4 673 __HAL_TIM_ENABLE(htim);
mbed_official 205:c41fc65bcfb4 674
mbed_official 205:c41fc65bcfb4 675 /* Return function status */
mbed_official 205:c41fc65bcfb4 676 return HAL_OK;
mbed_official 205:c41fc65bcfb4 677 }
mbed_official 205:c41fc65bcfb4 678
mbed_official 205:c41fc65bcfb4 679 /**
mbed_official 205:c41fc65bcfb4 680 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
mbed_official 205:c41fc65bcfb4 681 * @param htim : TIM Output Compare handle
mbed_official 205:c41fc65bcfb4 682 * @param Channel : TIM Channel to be disabled
mbed_official 205:c41fc65bcfb4 683 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 684 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 205:c41fc65bcfb4 685 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 205:c41fc65bcfb4 686 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 205:c41fc65bcfb4 687 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 205:c41fc65bcfb4 688 * @retval HAL status
mbed_official 205:c41fc65bcfb4 689 */
mbed_official 205:c41fc65bcfb4 690 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 205:c41fc65bcfb4 691 {
mbed_official 205:c41fc65bcfb4 692 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 693 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 205:c41fc65bcfb4 694
mbed_official 205:c41fc65bcfb4 695 switch (Channel)
mbed_official 205:c41fc65bcfb4 696 {
mbed_official 205:c41fc65bcfb4 697 case TIM_CHANNEL_1:
mbed_official 205:c41fc65bcfb4 698 {
mbed_official 205:c41fc65bcfb4 699 /* Disable the TIM Capture/Compare 1 interrupt */
mbed_official 205:c41fc65bcfb4 700 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official 205:c41fc65bcfb4 701 }
mbed_official 205:c41fc65bcfb4 702 break;
mbed_official 205:c41fc65bcfb4 703
mbed_official 205:c41fc65bcfb4 704 case TIM_CHANNEL_2:
mbed_official 205:c41fc65bcfb4 705 {
mbed_official 205:c41fc65bcfb4 706 /* Disable the TIM Capture/Compare 2 interrupt */
mbed_official 205:c41fc65bcfb4 707 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official 205:c41fc65bcfb4 708 }
mbed_official 205:c41fc65bcfb4 709 break;
mbed_official 205:c41fc65bcfb4 710
mbed_official 205:c41fc65bcfb4 711 case TIM_CHANNEL_3:
mbed_official 205:c41fc65bcfb4 712 {
mbed_official 205:c41fc65bcfb4 713 /* Disable the TIM Capture/Compare 3 interrupt */
mbed_official 205:c41fc65bcfb4 714 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
mbed_official 205:c41fc65bcfb4 715 }
mbed_official 205:c41fc65bcfb4 716 break;
mbed_official 205:c41fc65bcfb4 717
mbed_official 205:c41fc65bcfb4 718 case TIM_CHANNEL_4:
mbed_official 205:c41fc65bcfb4 719 {
mbed_official 205:c41fc65bcfb4 720 /* Disable the TIM Capture/Compare 4 interrupt */
mbed_official 205:c41fc65bcfb4 721 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
mbed_official 205:c41fc65bcfb4 722 }
mbed_official 205:c41fc65bcfb4 723 break;
mbed_official 205:c41fc65bcfb4 724
mbed_official 205:c41fc65bcfb4 725 default:
mbed_official 205:c41fc65bcfb4 726 break;
mbed_official 205:c41fc65bcfb4 727 }
mbed_official 205:c41fc65bcfb4 728
mbed_official 205:c41fc65bcfb4 729 /* Disable the Output compare channel */
mbed_official 205:c41fc65bcfb4 730 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 205:c41fc65bcfb4 731
mbed_official 205:c41fc65bcfb4 732 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official 205:c41fc65bcfb4 733 {
mbed_official 205:c41fc65bcfb4 734 /* Disable the Main Ouput */
mbed_official 205:c41fc65bcfb4 735 __HAL_TIM_MOE_DISABLE(htim);
mbed_official 205:c41fc65bcfb4 736 }
mbed_official 205:c41fc65bcfb4 737
mbed_official 205:c41fc65bcfb4 738 /* Disable the Peripheral */
mbed_official 205:c41fc65bcfb4 739 __HAL_TIM_DISABLE(htim);
mbed_official 205:c41fc65bcfb4 740
mbed_official 205:c41fc65bcfb4 741 /* Return function status */
mbed_official 205:c41fc65bcfb4 742 return HAL_OK;
mbed_official 205:c41fc65bcfb4 743 }
mbed_official 205:c41fc65bcfb4 744
mbed_official 205:c41fc65bcfb4 745 /**
mbed_official 205:c41fc65bcfb4 746 * @brief Starts the TIM Output Compare signal generation in DMA mode.
mbed_official 205:c41fc65bcfb4 747 * @param htim : TIM Output Compare handle
mbed_official 205:c41fc65bcfb4 748 * @param Channel : TIM Channel to be enabled
mbed_official 205:c41fc65bcfb4 749 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 750 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 205:c41fc65bcfb4 751 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 205:c41fc65bcfb4 752 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 205:c41fc65bcfb4 753 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 205:c41fc65bcfb4 754 * @param pData: The source Buffer address.
mbed_official 205:c41fc65bcfb4 755 * @param Length: The length of data to be transferred from memory to TIM peripheral
mbed_official 205:c41fc65bcfb4 756 * @retval HAL status
mbed_official 205:c41fc65bcfb4 757 */
mbed_official 205:c41fc65bcfb4 758 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
mbed_official 205:c41fc65bcfb4 759 {
mbed_official 205:c41fc65bcfb4 760 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 761 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 205:c41fc65bcfb4 762
mbed_official 205:c41fc65bcfb4 763 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 205:c41fc65bcfb4 764 {
mbed_official 205:c41fc65bcfb4 765 return HAL_BUSY;
mbed_official 205:c41fc65bcfb4 766 }
mbed_official 205:c41fc65bcfb4 767 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 205:c41fc65bcfb4 768 {
mbed_official 205:c41fc65bcfb4 769 if(((uint32_t)pData == 0 ) && (Length > 0))
mbed_official 205:c41fc65bcfb4 770 {
mbed_official 205:c41fc65bcfb4 771 return HAL_ERROR;
mbed_official 205:c41fc65bcfb4 772 }
mbed_official 205:c41fc65bcfb4 773 else
mbed_official 205:c41fc65bcfb4 774 {
mbed_official 205:c41fc65bcfb4 775 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 205:c41fc65bcfb4 776 }
mbed_official 205:c41fc65bcfb4 777 }
mbed_official 205:c41fc65bcfb4 778 switch (Channel)
mbed_official 205:c41fc65bcfb4 779 {
mbed_official 205:c41fc65bcfb4 780 case TIM_CHANNEL_1:
mbed_official 205:c41fc65bcfb4 781 {
mbed_official 205:c41fc65bcfb4 782 /* Set the DMA Period elapsed callback */
mbed_official 205:c41fc65bcfb4 783 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official 205:c41fc65bcfb4 784
mbed_official 205:c41fc65bcfb4 785 /* Set the DMA error callback */
mbed_official 205:c41fc65bcfb4 786 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 205:c41fc65bcfb4 787
mbed_official 205:c41fc65bcfb4 788 /* Enable the DMA channel */
mbed_official 205:c41fc65bcfb4 789 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
mbed_official 205:c41fc65bcfb4 790
mbed_official 205:c41fc65bcfb4 791 /* Enable the TIM Capture/Compare 1 DMA request */
mbed_official 205:c41fc65bcfb4 792 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 205:c41fc65bcfb4 793 }
mbed_official 205:c41fc65bcfb4 794 break;
mbed_official 205:c41fc65bcfb4 795
mbed_official 205:c41fc65bcfb4 796 case TIM_CHANNEL_2:
mbed_official 205:c41fc65bcfb4 797 {
mbed_official 205:c41fc65bcfb4 798 /* Set the DMA Period elapsed callback */
mbed_official 205:c41fc65bcfb4 799 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official 205:c41fc65bcfb4 800
mbed_official 205:c41fc65bcfb4 801 /* Set the DMA error callback */
mbed_official 205:c41fc65bcfb4 802 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 205:c41fc65bcfb4 803
mbed_official 205:c41fc65bcfb4 804 /* Enable the DMA channel */
mbed_official 205:c41fc65bcfb4 805 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
mbed_official 205:c41fc65bcfb4 806
mbed_official 205:c41fc65bcfb4 807 /* Enable the TIM Capture/Compare 2 DMA request */
mbed_official 205:c41fc65bcfb4 808 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 205:c41fc65bcfb4 809 }
mbed_official 205:c41fc65bcfb4 810 break;
mbed_official 205:c41fc65bcfb4 811
mbed_official 205:c41fc65bcfb4 812 case TIM_CHANNEL_3:
mbed_official 205:c41fc65bcfb4 813 {
mbed_official 205:c41fc65bcfb4 814 /* Set the DMA Period elapsed callback */
mbed_official 205:c41fc65bcfb4 815 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official 205:c41fc65bcfb4 816
mbed_official 205:c41fc65bcfb4 817 /* Set the DMA error callback */
mbed_official 205:c41fc65bcfb4 818 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 205:c41fc65bcfb4 819
mbed_official 205:c41fc65bcfb4 820 /* Enable the DMA channel */
mbed_official 205:c41fc65bcfb4 821 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
mbed_official 205:c41fc65bcfb4 822
mbed_official 205:c41fc65bcfb4 823 /* Enable the TIM Capture/Compare 3 DMA request */
mbed_official 205:c41fc65bcfb4 824 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
mbed_official 205:c41fc65bcfb4 825 }
mbed_official 205:c41fc65bcfb4 826 break;
mbed_official 205:c41fc65bcfb4 827
mbed_official 205:c41fc65bcfb4 828 case TIM_CHANNEL_4:
mbed_official 205:c41fc65bcfb4 829 {
mbed_official 205:c41fc65bcfb4 830 /* Set the DMA Period elapsed callback */
mbed_official 205:c41fc65bcfb4 831 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official 205:c41fc65bcfb4 832
mbed_official 205:c41fc65bcfb4 833 /* Set the DMA error callback */
mbed_official 205:c41fc65bcfb4 834 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 205:c41fc65bcfb4 835
mbed_official 205:c41fc65bcfb4 836 /* Enable the DMA channel */
mbed_official 205:c41fc65bcfb4 837 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
mbed_official 205:c41fc65bcfb4 838
mbed_official 205:c41fc65bcfb4 839 /* Enable the TIM Capture/Compare 4 DMA request */
mbed_official 205:c41fc65bcfb4 840 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
mbed_official 205:c41fc65bcfb4 841 }
mbed_official 205:c41fc65bcfb4 842 break;
mbed_official 205:c41fc65bcfb4 843
mbed_official 205:c41fc65bcfb4 844 default:
mbed_official 205:c41fc65bcfb4 845 break;
mbed_official 205:c41fc65bcfb4 846 }
mbed_official 205:c41fc65bcfb4 847
mbed_official 205:c41fc65bcfb4 848 /* Enable the Output compare channel */
mbed_official 205:c41fc65bcfb4 849 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 205:c41fc65bcfb4 850
mbed_official 205:c41fc65bcfb4 851 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official 205:c41fc65bcfb4 852 {
mbed_official 205:c41fc65bcfb4 853 /* Enable the main output */
mbed_official 205:c41fc65bcfb4 854 __HAL_TIM_MOE_ENABLE(htim);
mbed_official 205:c41fc65bcfb4 855 }
mbed_official 205:c41fc65bcfb4 856
mbed_official 205:c41fc65bcfb4 857 /* Enable the Peripheral */
mbed_official 205:c41fc65bcfb4 858 __HAL_TIM_ENABLE(htim);
mbed_official 205:c41fc65bcfb4 859
mbed_official 205:c41fc65bcfb4 860 /* Return function status */
mbed_official 205:c41fc65bcfb4 861 return HAL_OK;
mbed_official 205:c41fc65bcfb4 862 }
mbed_official 205:c41fc65bcfb4 863
mbed_official 205:c41fc65bcfb4 864 /**
mbed_official 205:c41fc65bcfb4 865 * @brief Stops the TIM Output Compare signal generation in DMA mode.
mbed_official 205:c41fc65bcfb4 866 * @param htim : TIM Output Compare handle
mbed_official 205:c41fc65bcfb4 867 * @param Channel : TIM Channel to be disabled
mbed_official 205:c41fc65bcfb4 868 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 869 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 205:c41fc65bcfb4 870 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 205:c41fc65bcfb4 871 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 205:c41fc65bcfb4 872 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 205:c41fc65bcfb4 873 * @retval HAL status
mbed_official 205:c41fc65bcfb4 874 */
mbed_official 205:c41fc65bcfb4 875 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 205:c41fc65bcfb4 876 {
mbed_official 205:c41fc65bcfb4 877 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 878 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 205:c41fc65bcfb4 879
mbed_official 205:c41fc65bcfb4 880 switch (Channel)
mbed_official 205:c41fc65bcfb4 881 {
mbed_official 205:c41fc65bcfb4 882 case TIM_CHANNEL_1:
mbed_official 205:c41fc65bcfb4 883 {
mbed_official 205:c41fc65bcfb4 884 /* Disable the TIM Capture/Compare 1 DMA request */
mbed_official 205:c41fc65bcfb4 885 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 205:c41fc65bcfb4 886 }
mbed_official 205:c41fc65bcfb4 887 break;
mbed_official 205:c41fc65bcfb4 888
mbed_official 205:c41fc65bcfb4 889 case TIM_CHANNEL_2:
mbed_official 205:c41fc65bcfb4 890 {
mbed_official 205:c41fc65bcfb4 891 /* Disable the TIM Capture/Compare 2 DMA request */
mbed_official 205:c41fc65bcfb4 892 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 205:c41fc65bcfb4 893 }
mbed_official 205:c41fc65bcfb4 894 break;
mbed_official 205:c41fc65bcfb4 895
mbed_official 205:c41fc65bcfb4 896 case TIM_CHANNEL_3:
mbed_official 205:c41fc65bcfb4 897 {
mbed_official 205:c41fc65bcfb4 898 /* Disable the TIM Capture/Compare 3 DMA request */
mbed_official 205:c41fc65bcfb4 899 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
mbed_official 205:c41fc65bcfb4 900 }
mbed_official 205:c41fc65bcfb4 901 break;
mbed_official 205:c41fc65bcfb4 902
mbed_official 205:c41fc65bcfb4 903 case TIM_CHANNEL_4:
mbed_official 205:c41fc65bcfb4 904 {
mbed_official 205:c41fc65bcfb4 905 /* Disable the TIM Capture/Compare 4 interrupt */
mbed_official 205:c41fc65bcfb4 906 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
mbed_official 205:c41fc65bcfb4 907 }
mbed_official 205:c41fc65bcfb4 908 break;
mbed_official 205:c41fc65bcfb4 909
mbed_official 205:c41fc65bcfb4 910 default:
mbed_official 205:c41fc65bcfb4 911 break;
mbed_official 205:c41fc65bcfb4 912 }
mbed_official 205:c41fc65bcfb4 913
mbed_official 205:c41fc65bcfb4 914 /* Disable the Output compare channel */
mbed_official 205:c41fc65bcfb4 915 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 205:c41fc65bcfb4 916
mbed_official 205:c41fc65bcfb4 917 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official 205:c41fc65bcfb4 918 {
mbed_official 205:c41fc65bcfb4 919 /* Disable the Main Ouput */
mbed_official 205:c41fc65bcfb4 920 __HAL_TIM_MOE_DISABLE(htim);
mbed_official 205:c41fc65bcfb4 921 }
mbed_official 205:c41fc65bcfb4 922
mbed_official 205:c41fc65bcfb4 923 /* Disable the Peripheral */
mbed_official 205:c41fc65bcfb4 924 __HAL_TIM_DISABLE(htim);
mbed_official 205:c41fc65bcfb4 925
mbed_official 205:c41fc65bcfb4 926 /* Change the htim state */
mbed_official 205:c41fc65bcfb4 927 htim->State = HAL_TIM_STATE_READY;
mbed_official 205:c41fc65bcfb4 928
mbed_official 205:c41fc65bcfb4 929 /* Return function status */
mbed_official 205:c41fc65bcfb4 930 return HAL_OK;
mbed_official 205:c41fc65bcfb4 931 }
mbed_official 205:c41fc65bcfb4 932
mbed_official 205:c41fc65bcfb4 933 /**
mbed_official 205:c41fc65bcfb4 934 * @}
mbed_official 205:c41fc65bcfb4 935 */
mbed_official 205:c41fc65bcfb4 936
mbed_official 205:c41fc65bcfb4 937 /** @defgroup TIM_Group3 Time PWM functions
mbed_official 205:c41fc65bcfb4 938 * @brief Time PWM functions
mbed_official 205:c41fc65bcfb4 939 *
mbed_official 205:c41fc65bcfb4 940 @verbatim
mbed_official 205:c41fc65bcfb4 941 ==============================================================================
mbed_official 205:c41fc65bcfb4 942 ##### Time PWM functions #####
mbed_official 205:c41fc65bcfb4 943 ==============================================================================
mbed_official 205:c41fc65bcfb4 944 [..]
mbed_official 205:c41fc65bcfb4 945 This section provides functions allowing to:
mbed_official 205:c41fc65bcfb4 946 (+) Initialize and configure the TIM OPWM.
mbed_official 205:c41fc65bcfb4 947 (+) De-initialize the TIM PWM.
mbed_official 205:c41fc65bcfb4 948 (+) Start the Time PWM.
mbed_official 205:c41fc65bcfb4 949 (+) Stop the Time PWM.
mbed_official 205:c41fc65bcfb4 950 (+) Start the Time PWM and enable interrupt.
mbed_official 205:c41fc65bcfb4 951 (+) Stop the Time PWM and disable interrupt.
mbed_official 205:c41fc65bcfb4 952 (+) Start the Time PWM and enable DMA transfer.
mbed_official 205:c41fc65bcfb4 953 (+) Stop the Time PWM and disable DMA transfer.
mbed_official 205:c41fc65bcfb4 954
mbed_official 205:c41fc65bcfb4 955 @endverbatim
mbed_official 205:c41fc65bcfb4 956 * @{
mbed_official 205:c41fc65bcfb4 957 */
mbed_official 205:c41fc65bcfb4 958 /**
mbed_official 205:c41fc65bcfb4 959 * @brief Initializes the TIM PWM Time Base according to the specified
mbed_official 205:c41fc65bcfb4 960 * parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official 205:c41fc65bcfb4 961 * @param htim: TIM handle
mbed_official 205:c41fc65bcfb4 962 * @retval HAL status
mbed_official 205:c41fc65bcfb4 963 */
mbed_official 205:c41fc65bcfb4 964 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 965 {
mbed_official 205:c41fc65bcfb4 966 /* Check the TIM handle allocation */
mbed_official 205:c41fc65bcfb4 967 if(htim == NULL)
mbed_official 205:c41fc65bcfb4 968 {
mbed_official 205:c41fc65bcfb4 969 return HAL_ERROR;
mbed_official 205:c41fc65bcfb4 970 }
mbed_official 205:c41fc65bcfb4 971
mbed_official 205:c41fc65bcfb4 972 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 973 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 974 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official 205:c41fc65bcfb4 975 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official 205:c41fc65bcfb4 976
mbed_official 205:c41fc65bcfb4 977 if(htim->State == HAL_TIM_STATE_RESET)
mbed_official 205:c41fc65bcfb4 978 {
mbed_official 205:c41fc65bcfb4 979 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official 205:c41fc65bcfb4 980 HAL_TIM_PWM_MspInit(htim);
mbed_official 205:c41fc65bcfb4 981 }
mbed_official 205:c41fc65bcfb4 982
mbed_official 205:c41fc65bcfb4 983 /* Set the TIM state */
mbed_official 205:c41fc65bcfb4 984 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 205:c41fc65bcfb4 985
mbed_official 205:c41fc65bcfb4 986 /* Init the base time for the PWM */
mbed_official 205:c41fc65bcfb4 987 TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official 205:c41fc65bcfb4 988
mbed_official 205:c41fc65bcfb4 989 /* Initialize the TIM state*/
mbed_official 205:c41fc65bcfb4 990 htim->State= HAL_TIM_STATE_READY;
mbed_official 205:c41fc65bcfb4 991
mbed_official 205:c41fc65bcfb4 992 return HAL_OK;
mbed_official 205:c41fc65bcfb4 993 }
mbed_official 205:c41fc65bcfb4 994
mbed_official 205:c41fc65bcfb4 995 /**
mbed_official 205:c41fc65bcfb4 996 * @brief DeInitializes the TIM peripheral
mbed_official 205:c41fc65bcfb4 997 * @param htim: TIM handle
mbed_official 205:c41fc65bcfb4 998 * @retval HAL status
mbed_official 205:c41fc65bcfb4 999 */
mbed_official 205:c41fc65bcfb4 1000 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 1001 {
mbed_official 205:c41fc65bcfb4 1002 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 1003 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 1004
mbed_official 205:c41fc65bcfb4 1005 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 205:c41fc65bcfb4 1006
mbed_official 205:c41fc65bcfb4 1007 /* Disable the TIM Peripheral Clock */
mbed_official 205:c41fc65bcfb4 1008 __HAL_TIM_DISABLE(htim);
mbed_official 205:c41fc65bcfb4 1009
mbed_official 205:c41fc65bcfb4 1010 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
mbed_official 205:c41fc65bcfb4 1011 HAL_TIM_PWM_MspDeInit(htim);
mbed_official 205:c41fc65bcfb4 1012
mbed_official 205:c41fc65bcfb4 1013 /* Change TIM state */
mbed_official 205:c41fc65bcfb4 1014 htim->State = HAL_TIM_STATE_RESET;
mbed_official 205:c41fc65bcfb4 1015
mbed_official 205:c41fc65bcfb4 1016 /* Release Lock */
mbed_official 205:c41fc65bcfb4 1017 __HAL_UNLOCK(htim);
mbed_official 205:c41fc65bcfb4 1018
mbed_official 205:c41fc65bcfb4 1019 return HAL_OK;
mbed_official 205:c41fc65bcfb4 1020 }
mbed_official 205:c41fc65bcfb4 1021
mbed_official 205:c41fc65bcfb4 1022 /**
mbed_official 205:c41fc65bcfb4 1023 * @brief Initializes the TIM PWM MSP.
mbed_official 205:c41fc65bcfb4 1024 * @param htim: TIM handle
mbed_official 205:c41fc65bcfb4 1025 * @retval None
mbed_official 205:c41fc65bcfb4 1026 */
mbed_official 205:c41fc65bcfb4 1027 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 1028 {
mbed_official 205:c41fc65bcfb4 1029 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 205:c41fc65bcfb4 1030 the HAL_TIM_PWM_MspInit could be implemented in the user file
mbed_official 205:c41fc65bcfb4 1031 */
mbed_official 205:c41fc65bcfb4 1032 }
mbed_official 205:c41fc65bcfb4 1033
mbed_official 205:c41fc65bcfb4 1034 /**
mbed_official 205:c41fc65bcfb4 1035 * @brief DeInitializes TIM PWM MSP.
mbed_official 205:c41fc65bcfb4 1036 * @param htim: TIM handle
mbed_official 205:c41fc65bcfb4 1037 * @retval None
mbed_official 205:c41fc65bcfb4 1038 */
mbed_official 205:c41fc65bcfb4 1039 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 1040 {
mbed_official 205:c41fc65bcfb4 1041 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 205:c41fc65bcfb4 1042 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
mbed_official 205:c41fc65bcfb4 1043 */
mbed_official 205:c41fc65bcfb4 1044 }
mbed_official 205:c41fc65bcfb4 1045
mbed_official 205:c41fc65bcfb4 1046 /**
mbed_official 205:c41fc65bcfb4 1047 * @brief Starts the PWM signal generation.
mbed_official 205:c41fc65bcfb4 1048 * @param htim : TIM handle
mbed_official 205:c41fc65bcfb4 1049 * @param Channel : TIM Channels to be enabled
mbed_official 205:c41fc65bcfb4 1050 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 1051 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 205:c41fc65bcfb4 1052 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 205:c41fc65bcfb4 1053 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 205:c41fc65bcfb4 1054 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 205:c41fc65bcfb4 1055 * @retval HAL status
mbed_official 205:c41fc65bcfb4 1056 */
mbed_official 205:c41fc65bcfb4 1057 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 205:c41fc65bcfb4 1058 {
mbed_official 205:c41fc65bcfb4 1059 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 1060 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 205:c41fc65bcfb4 1061
mbed_official 205:c41fc65bcfb4 1062 /* Enable the Capture compare channel */
mbed_official 205:c41fc65bcfb4 1063 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 205:c41fc65bcfb4 1064
mbed_official 205:c41fc65bcfb4 1065 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official 205:c41fc65bcfb4 1066 {
mbed_official 205:c41fc65bcfb4 1067 /* Enable the main output */
mbed_official 205:c41fc65bcfb4 1068 __HAL_TIM_MOE_ENABLE(htim);
mbed_official 205:c41fc65bcfb4 1069 }
mbed_official 205:c41fc65bcfb4 1070
mbed_official 205:c41fc65bcfb4 1071 /* Enable the Peripheral */
mbed_official 205:c41fc65bcfb4 1072 __HAL_TIM_ENABLE(htim);
mbed_official 205:c41fc65bcfb4 1073
mbed_official 205:c41fc65bcfb4 1074 /* Return function status */
mbed_official 205:c41fc65bcfb4 1075 return HAL_OK;
mbed_official 205:c41fc65bcfb4 1076 }
mbed_official 205:c41fc65bcfb4 1077
mbed_official 205:c41fc65bcfb4 1078 /**
mbed_official 205:c41fc65bcfb4 1079 * @brief Stops the PWM signal generation.
mbed_official 205:c41fc65bcfb4 1080 * @param htim : TIM handle
mbed_official 205:c41fc65bcfb4 1081 * @param Channel : TIM Channels to be disabled
mbed_official 205:c41fc65bcfb4 1082 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 1083 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 205:c41fc65bcfb4 1084 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 205:c41fc65bcfb4 1085 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 205:c41fc65bcfb4 1086 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 205:c41fc65bcfb4 1087 * @retval HAL status
mbed_official 205:c41fc65bcfb4 1088 */
mbed_official 205:c41fc65bcfb4 1089 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 205:c41fc65bcfb4 1090 {
mbed_official 205:c41fc65bcfb4 1091 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 1092 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 205:c41fc65bcfb4 1093
mbed_official 205:c41fc65bcfb4 1094 /* Disable the Capture compare channel */
mbed_official 205:c41fc65bcfb4 1095 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 205:c41fc65bcfb4 1096
mbed_official 205:c41fc65bcfb4 1097 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official 205:c41fc65bcfb4 1098 {
mbed_official 205:c41fc65bcfb4 1099 /* Disable the Main Ouput */
mbed_official 205:c41fc65bcfb4 1100 __HAL_TIM_MOE_DISABLE(htim);
mbed_official 205:c41fc65bcfb4 1101 }
mbed_official 205:c41fc65bcfb4 1102
mbed_official 205:c41fc65bcfb4 1103 /* Disable the Peripheral */
mbed_official 205:c41fc65bcfb4 1104 __HAL_TIM_DISABLE(htim);
mbed_official 205:c41fc65bcfb4 1105
mbed_official 205:c41fc65bcfb4 1106 /* Change the htim state */
mbed_official 205:c41fc65bcfb4 1107 htim->State = HAL_TIM_STATE_READY;
mbed_official 205:c41fc65bcfb4 1108
mbed_official 205:c41fc65bcfb4 1109 /* Return function status */
mbed_official 205:c41fc65bcfb4 1110 return HAL_OK;
mbed_official 205:c41fc65bcfb4 1111 }
mbed_official 205:c41fc65bcfb4 1112
mbed_official 205:c41fc65bcfb4 1113 /**
mbed_official 205:c41fc65bcfb4 1114 * @brief Starts the PWM signal generation in interrupt mode.
mbed_official 205:c41fc65bcfb4 1115 * @param htim : TIM handle
mbed_official 205:c41fc65bcfb4 1116 * @param Channel : TIM Channel to be disabled
mbed_official 205:c41fc65bcfb4 1117 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 1118 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 205:c41fc65bcfb4 1119 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 205:c41fc65bcfb4 1120 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 205:c41fc65bcfb4 1121 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 205:c41fc65bcfb4 1122 * @retval HAL status
mbed_official 205:c41fc65bcfb4 1123 */
mbed_official 205:c41fc65bcfb4 1124 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 205:c41fc65bcfb4 1125 {
mbed_official 205:c41fc65bcfb4 1126 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 1127 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 205:c41fc65bcfb4 1128
mbed_official 205:c41fc65bcfb4 1129 switch (Channel)
mbed_official 205:c41fc65bcfb4 1130 {
mbed_official 205:c41fc65bcfb4 1131 case TIM_CHANNEL_1:
mbed_official 205:c41fc65bcfb4 1132 {
mbed_official 205:c41fc65bcfb4 1133 /* Enable the TIM Capture/Compare 1 interrupt */
mbed_official 205:c41fc65bcfb4 1134 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official 205:c41fc65bcfb4 1135 }
mbed_official 205:c41fc65bcfb4 1136 break;
mbed_official 205:c41fc65bcfb4 1137
mbed_official 205:c41fc65bcfb4 1138 case TIM_CHANNEL_2:
mbed_official 205:c41fc65bcfb4 1139 {
mbed_official 205:c41fc65bcfb4 1140 /* Enable the TIM Capture/Compare 2 interrupt */
mbed_official 205:c41fc65bcfb4 1141 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official 205:c41fc65bcfb4 1142 }
mbed_official 205:c41fc65bcfb4 1143 break;
mbed_official 205:c41fc65bcfb4 1144
mbed_official 205:c41fc65bcfb4 1145 case TIM_CHANNEL_3:
mbed_official 205:c41fc65bcfb4 1146 {
mbed_official 205:c41fc65bcfb4 1147 /* Enable the TIM Capture/Compare 3 interrupt */
mbed_official 205:c41fc65bcfb4 1148 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
mbed_official 205:c41fc65bcfb4 1149 }
mbed_official 205:c41fc65bcfb4 1150 break;
mbed_official 205:c41fc65bcfb4 1151
mbed_official 205:c41fc65bcfb4 1152 case TIM_CHANNEL_4:
mbed_official 205:c41fc65bcfb4 1153 {
mbed_official 205:c41fc65bcfb4 1154 /* Enable the TIM Capture/Compare 4 interrupt */
mbed_official 205:c41fc65bcfb4 1155 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
mbed_official 205:c41fc65bcfb4 1156 }
mbed_official 205:c41fc65bcfb4 1157 break;
mbed_official 205:c41fc65bcfb4 1158
mbed_official 205:c41fc65bcfb4 1159 default:
mbed_official 205:c41fc65bcfb4 1160 break;
mbed_official 205:c41fc65bcfb4 1161 }
mbed_official 205:c41fc65bcfb4 1162
mbed_official 205:c41fc65bcfb4 1163 /* Enable the Capture compare channel */
mbed_official 205:c41fc65bcfb4 1164 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 205:c41fc65bcfb4 1165
mbed_official 205:c41fc65bcfb4 1166 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official 205:c41fc65bcfb4 1167 {
mbed_official 205:c41fc65bcfb4 1168 /* Enable the main output */
mbed_official 205:c41fc65bcfb4 1169 __HAL_TIM_MOE_ENABLE(htim);
mbed_official 205:c41fc65bcfb4 1170 }
mbed_official 205:c41fc65bcfb4 1171
mbed_official 205:c41fc65bcfb4 1172 /* Enable the Peripheral */
mbed_official 205:c41fc65bcfb4 1173 __HAL_TIM_ENABLE(htim);
mbed_official 205:c41fc65bcfb4 1174
mbed_official 205:c41fc65bcfb4 1175 /* Return function status */
mbed_official 205:c41fc65bcfb4 1176 return HAL_OK;
mbed_official 205:c41fc65bcfb4 1177 }
mbed_official 205:c41fc65bcfb4 1178
mbed_official 205:c41fc65bcfb4 1179 /**
mbed_official 205:c41fc65bcfb4 1180 * @brief Stops the PWM signal generation in interrupt mode.
mbed_official 205:c41fc65bcfb4 1181 * @param htim : TIM handle
mbed_official 205:c41fc65bcfb4 1182 * @param Channel : TIM Channels to be disabled
mbed_official 205:c41fc65bcfb4 1183 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 1184 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 205:c41fc65bcfb4 1185 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 205:c41fc65bcfb4 1186 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 205:c41fc65bcfb4 1187 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 205:c41fc65bcfb4 1188 * @retval HAL status
mbed_official 205:c41fc65bcfb4 1189 */
mbed_official 205:c41fc65bcfb4 1190 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 205:c41fc65bcfb4 1191 {
mbed_official 205:c41fc65bcfb4 1192 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 1193 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 205:c41fc65bcfb4 1194
mbed_official 205:c41fc65bcfb4 1195 switch (Channel)
mbed_official 205:c41fc65bcfb4 1196 {
mbed_official 205:c41fc65bcfb4 1197 case TIM_CHANNEL_1:
mbed_official 205:c41fc65bcfb4 1198 {
mbed_official 205:c41fc65bcfb4 1199 /* Disable the TIM Capture/Compare 1 interrupt */
mbed_official 205:c41fc65bcfb4 1200 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official 205:c41fc65bcfb4 1201 }
mbed_official 205:c41fc65bcfb4 1202 break;
mbed_official 205:c41fc65bcfb4 1203
mbed_official 205:c41fc65bcfb4 1204 case TIM_CHANNEL_2:
mbed_official 205:c41fc65bcfb4 1205 {
mbed_official 205:c41fc65bcfb4 1206 /* Disable the TIM Capture/Compare 2 interrupt */
mbed_official 205:c41fc65bcfb4 1207 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official 205:c41fc65bcfb4 1208 }
mbed_official 205:c41fc65bcfb4 1209 break;
mbed_official 205:c41fc65bcfb4 1210
mbed_official 205:c41fc65bcfb4 1211 case TIM_CHANNEL_3:
mbed_official 205:c41fc65bcfb4 1212 {
mbed_official 205:c41fc65bcfb4 1213 /* Disable the TIM Capture/Compare 3 interrupt */
mbed_official 205:c41fc65bcfb4 1214 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
mbed_official 205:c41fc65bcfb4 1215 }
mbed_official 205:c41fc65bcfb4 1216 break;
mbed_official 205:c41fc65bcfb4 1217
mbed_official 205:c41fc65bcfb4 1218 case TIM_CHANNEL_4:
mbed_official 205:c41fc65bcfb4 1219 {
mbed_official 205:c41fc65bcfb4 1220 /* Disable the TIM Capture/Compare 4 interrupt */
mbed_official 205:c41fc65bcfb4 1221 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
mbed_official 205:c41fc65bcfb4 1222 }
mbed_official 205:c41fc65bcfb4 1223 break;
mbed_official 205:c41fc65bcfb4 1224
mbed_official 205:c41fc65bcfb4 1225 default:
mbed_official 205:c41fc65bcfb4 1226 break;
mbed_official 205:c41fc65bcfb4 1227 }
mbed_official 205:c41fc65bcfb4 1228
mbed_official 205:c41fc65bcfb4 1229 /* Disable the Capture compare channel */
mbed_official 205:c41fc65bcfb4 1230 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 205:c41fc65bcfb4 1231
mbed_official 205:c41fc65bcfb4 1232 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official 205:c41fc65bcfb4 1233 {
mbed_official 205:c41fc65bcfb4 1234 /* Disable the Main Ouput */
mbed_official 205:c41fc65bcfb4 1235 __HAL_TIM_MOE_DISABLE(htim);
mbed_official 205:c41fc65bcfb4 1236 }
mbed_official 205:c41fc65bcfb4 1237
mbed_official 205:c41fc65bcfb4 1238 /* Disable the Peripheral */
mbed_official 205:c41fc65bcfb4 1239 __HAL_TIM_DISABLE(htim);
mbed_official 205:c41fc65bcfb4 1240
mbed_official 205:c41fc65bcfb4 1241 /* Return function status */
mbed_official 205:c41fc65bcfb4 1242 return HAL_OK;
mbed_official 205:c41fc65bcfb4 1243 }
mbed_official 205:c41fc65bcfb4 1244
mbed_official 205:c41fc65bcfb4 1245 /**
mbed_official 205:c41fc65bcfb4 1246 * @brief Starts the TIM PWM signal generation in DMA mode.
mbed_official 205:c41fc65bcfb4 1247 * @param htim : TIM handle
mbed_official 205:c41fc65bcfb4 1248 * @param Channel : TIM Channels to be enabled
mbed_official 205:c41fc65bcfb4 1249 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 1250 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 205:c41fc65bcfb4 1251 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 205:c41fc65bcfb4 1252 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 205:c41fc65bcfb4 1253 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 205:c41fc65bcfb4 1254 * @param pData: The source Buffer address.
mbed_official 205:c41fc65bcfb4 1255 * @param Length: The length of data to be transferred from memory to TIM peripheral
mbed_official 205:c41fc65bcfb4 1256 * @retval HAL status
mbed_official 205:c41fc65bcfb4 1257 */
mbed_official 205:c41fc65bcfb4 1258 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
mbed_official 205:c41fc65bcfb4 1259 {
mbed_official 205:c41fc65bcfb4 1260 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 1261 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 205:c41fc65bcfb4 1262
mbed_official 205:c41fc65bcfb4 1263 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 205:c41fc65bcfb4 1264 {
mbed_official 205:c41fc65bcfb4 1265 return HAL_BUSY;
mbed_official 205:c41fc65bcfb4 1266 }
mbed_official 205:c41fc65bcfb4 1267 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 205:c41fc65bcfb4 1268 {
mbed_official 205:c41fc65bcfb4 1269 if(((uint32_t)pData == 0 ) && (Length > 0))
mbed_official 205:c41fc65bcfb4 1270 {
mbed_official 205:c41fc65bcfb4 1271 return HAL_ERROR;
mbed_official 205:c41fc65bcfb4 1272 }
mbed_official 205:c41fc65bcfb4 1273 else
mbed_official 205:c41fc65bcfb4 1274 {
mbed_official 205:c41fc65bcfb4 1275 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 205:c41fc65bcfb4 1276 }
mbed_official 205:c41fc65bcfb4 1277 }
mbed_official 205:c41fc65bcfb4 1278 switch (Channel)
mbed_official 205:c41fc65bcfb4 1279 {
mbed_official 205:c41fc65bcfb4 1280 case TIM_CHANNEL_1:
mbed_official 205:c41fc65bcfb4 1281 {
mbed_official 205:c41fc65bcfb4 1282 /* Set the DMA Period elapsed callback */
mbed_official 205:c41fc65bcfb4 1283 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official 205:c41fc65bcfb4 1284
mbed_official 205:c41fc65bcfb4 1285 /* Set the DMA error callback */
mbed_official 205:c41fc65bcfb4 1286 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 205:c41fc65bcfb4 1287
mbed_official 205:c41fc65bcfb4 1288 /* Enable the DMA channel */
mbed_official 205:c41fc65bcfb4 1289 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
mbed_official 205:c41fc65bcfb4 1290
mbed_official 205:c41fc65bcfb4 1291 /* Enable the TIM Capture/Compare 1 DMA request */
mbed_official 205:c41fc65bcfb4 1292 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 205:c41fc65bcfb4 1293 }
mbed_official 205:c41fc65bcfb4 1294 break;
mbed_official 205:c41fc65bcfb4 1295
mbed_official 205:c41fc65bcfb4 1296 case TIM_CHANNEL_2:
mbed_official 205:c41fc65bcfb4 1297 {
mbed_official 205:c41fc65bcfb4 1298 /* Set the DMA Period elapsed callback */
mbed_official 205:c41fc65bcfb4 1299 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official 205:c41fc65bcfb4 1300
mbed_official 205:c41fc65bcfb4 1301 /* Set the DMA error callback */
mbed_official 205:c41fc65bcfb4 1302 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 205:c41fc65bcfb4 1303
mbed_official 205:c41fc65bcfb4 1304 /* Enable the DMA channel */
mbed_official 205:c41fc65bcfb4 1305 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
mbed_official 205:c41fc65bcfb4 1306
mbed_official 205:c41fc65bcfb4 1307 /* Enable the TIM Capture/Compare 2 DMA request */
mbed_official 205:c41fc65bcfb4 1308 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 205:c41fc65bcfb4 1309 }
mbed_official 205:c41fc65bcfb4 1310 break;
mbed_official 205:c41fc65bcfb4 1311
mbed_official 205:c41fc65bcfb4 1312 case TIM_CHANNEL_3:
mbed_official 205:c41fc65bcfb4 1313 {
mbed_official 205:c41fc65bcfb4 1314 /* Set the DMA Period elapsed callback */
mbed_official 205:c41fc65bcfb4 1315 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official 205:c41fc65bcfb4 1316
mbed_official 205:c41fc65bcfb4 1317 /* Set the DMA error callback */
mbed_official 205:c41fc65bcfb4 1318 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 205:c41fc65bcfb4 1319
mbed_official 205:c41fc65bcfb4 1320 /* Enable the DMA channel */
mbed_official 205:c41fc65bcfb4 1321 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
mbed_official 205:c41fc65bcfb4 1322
mbed_official 205:c41fc65bcfb4 1323 /* Enable the TIM Output Capture/Compare 3 request */
mbed_official 205:c41fc65bcfb4 1324 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
mbed_official 205:c41fc65bcfb4 1325 }
mbed_official 205:c41fc65bcfb4 1326 break;
mbed_official 205:c41fc65bcfb4 1327
mbed_official 205:c41fc65bcfb4 1328 case TIM_CHANNEL_4:
mbed_official 205:c41fc65bcfb4 1329 {
mbed_official 205:c41fc65bcfb4 1330 /* Set the DMA Period elapsed callback */
mbed_official 205:c41fc65bcfb4 1331 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official 205:c41fc65bcfb4 1332
mbed_official 205:c41fc65bcfb4 1333 /* Set the DMA error callback */
mbed_official 205:c41fc65bcfb4 1334 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 205:c41fc65bcfb4 1335
mbed_official 205:c41fc65bcfb4 1336 /* Enable the DMA channel */
mbed_official 205:c41fc65bcfb4 1337 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
mbed_official 205:c41fc65bcfb4 1338
mbed_official 205:c41fc65bcfb4 1339 /* Enable the TIM Capture/Compare 4 DMA request */
mbed_official 205:c41fc65bcfb4 1340 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
mbed_official 205:c41fc65bcfb4 1341 }
mbed_official 205:c41fc65bcfb4 1342 break;
mbed_official 205:c41fc65bcfb4 1343
mbed_official 205:c41fc65bcfb4 1344 default:
mbed_official 205:c41fc65bcfb4 1345 break;
mbed_official 205:c41fc65bcfb4 1346 }
mbed_official 205:c41fc65bcfb4 1347
mbed_official 205:c41fc65bcfb4 1348 /* Enable the Capture compare channel */
mbed_official 205:c41fc65bcfb4 1349 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 205:c41fc65bcfb4 1350
mbed_official 205:c41fc65bcfb4 1351 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official 205:c41fc65bcfb4 1352 {
mbed_official 205:c41fc65bcfb4 1353 /* Enable the main output */
mbed_official 205:c41fc65bcfb4 1354 __HAL_TIM_MOE_ENABLE(htim);
mbed_official 205:c41fc65bcfb4 1355 }
mbed_official 205:c41fc65bcfb4 1356
mbed_official 205:c41fc65bcfb4 1357 /* Enable the Peripheral */
mbed_official 205:c41fc65bcfb4 1358 __HAL_TIM_ENABLE(htim);
mbed_official 205:c41fc65bcfb4 1359
mbed_official 205:c41fc65bcfb4 1360 /* Return function status */
mbed_official 205:c41fc65bcfb4 1361 return HAL_OK;
mbed_official 205:c41fc65bcfb4 1362 }
mbed_official 205:c41fc65bcfb4 1363
mbed_official 205:c41fc65bcfb4 1364 /**
mbed_official 205:c41fc65bcfb4 1365 * @brief Stops the TIM PWM signal generation in DMA mode.
mbed_official 205:c41fc65bcfb4 1366 * @param htim : TIM handle
mbed_official 205:c41fc65bcfb4 1367 * @param Channel : TIM Channels to be disabled
mbed_official 205:c41fc65bcfb4 1368 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 1369 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 205:c41fc65bcfb4 1370 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 205:c41fc65bcfb4 1371 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 205:c41fc65bcfb4 1372 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 205:c41fc65bcfb4 1373 * @retval HAL status
mbed_official 205:c41fc65bcfb4 1374 */
mbed_official 205:c41fc65bcfb4 1375 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 205:c41fc65bcfb4 1376 {
mbed_official 205:c41fc65bcfb4 1377 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 1378 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 205:c41fc65bcfb4 1379
mbed_official 205:c41fc65bcfb4 1380 switch (Channel)
mbed_official 205:c41fc65bcfb4 1381 {
mbed_official 205:c41fc65bcfb4 1382 case TIM_CHANNEL_1:
mbed_official 205:c41fc65bcfb4 1383 {
mbed_official 205:c41fc65bcfb4 1384 /* Disable the TIM Capture/Compare 1 DMA request */
mbed_official 205:c41fc65bcfb4 1385 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 205:c41fc65bcfb4 1386 }
mbed_official 205:c41fc65bcfb4 1387 break;
mbed_official 205:c41fc65bcfb4 1388
mbed_official 205:c41fc65bcfb4 1389 case TIM_CHANNEL_2:
mbed_official 205:c41fc65bcfb4 1390 {
mbed_official 205:c41fc65bcfb4 1391 /* Disable the TIM Capture/Compare 2 DMA request */
mbed_official 205:c41fc65bcfb4 1392 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 205:c41fc65bcfb4 1393 }
mbed_official 205:c41fc65bcfb4 1394 break;
mbed_official 205:c41fc65bcfb4 1395
mbed_official 205:c41fc65bcfb4 1396 case TIM_CHANNEL_3:
mbed_official 205:c41fc65bcfb4 1397 {
mbed_official 205:c41fc65bcfb4 1398 /* Disable the TIM Capture/Compare 3 DMA request */
mbed_official 205:c41fc65bcfb4 1399 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
mbed_official 205:c41fc65bcfb4 1400 }
mbed_official 205:c41fc65bcfb4 1401 break;
mbed_official 205:c41fc65bcfb4 1402
mbed_official 205:c41fc65bcfb4 1403 case TIM_CHANNEL_4:
mbed_official 205:c41fc65bcfb4 1404 {
mbed_official 205:c41fc65bcfb4 1405 /* Disable the TIM Capture/Compare 4 interrupt */
mbed_official 205:c41fc65bcfb4 1406 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
mbed_official 205:c41fc65bcfb4 1407 }
mbed_official 205:c41fc65bcfb4 1408 break;
mbed_official 205:c41fc65bcfb4 1409
mbed_official 205:c41fc65bcfb4 1410 default:
mbed_official 205:c41fc65bcfb4 1411 break;
mbed_official 205:c41fc65bcfb4 1412 }
mbed_official 205:c41fc65bcfb4 1413
mbed_official 205:c41fc65bcfb4 1414 /* Disable the Capture compare channel */
mbed_official 205:c41fc65bcfb4 1415 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 205:c41fc65bcfb4 1416
mbed_official 205:c41fc65bcfb4 1417 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official 205:c41fc65bcfb4 1418 {
mbed_official 205:c41fc65bcfb4 1419 /* Disable the Main Ouput */
mbed_official 205:c41fc65bcfb4 1420 __HAL_TIM_MOE_DISABLE(htim);
mbed_official 205:c41fc65bcfb4 1421 }
mbed_official 205:c41fc65bcfb4 1422
mbed_official 205:c41fc65bcfb4 1423 /* Disable the Peripheral */
mbed_official 205:c41fc65bcfb4 1424 __HAL_TIM_DISABLE(htim);
mbed_official 205:c41fc65bcfb4 1425
mbed_official 205:c41fc65bcfb4 1426 /* Change the htim state */
mbed_official 205:c41fc65bcfb4 1427 htim->State = HAL_TIM_STATE_READY;
mbed_official 205:c41fc65bcfb4 1428
mbed_official 205:c41fc65bcfb4 1429 /* Return function status */
mbed_official 205:c41fc65bcfb4 1430 return HAL_OK;
mbed_official 205:c41fc65bcfb4 1431 }
mbed_official 205:c41fc65bcfb4 1432
mbed_official 205:c41fc65bcfb4 1433 /**
mbed_official 205:c41fc65bcfb4 1434 * @}
mbed_official 205:c41fc65bcfb4 1435 */
mbed_official 205:c41fc65bcfb4 1436
mbed_official 205:c41fc65bcfb4 1437 /** @defgroup TIM_Group4 Time Input Capture functions
mbed_official 205:c41fc65bcfb4 1438 * @brief Time Input Capture functions
mbed_official 205:c41fc65bcfb4 1439 *
mbed_official 205:c41fc65bcfb4 1440 @verbatim
mbed_official 205:c41fc65bcfb4 1441 ==============================================================================
mbed_official 205:c41fc65bcfb4 1442 ##### Time Input Capture functions #####
mbed_official 205:c41fc65bcfb4 1443 ==============================================================================
mbed_official 205:c41fc65bcfb4 1444 [..]
mbed_official 205:c41fc65bcfb4 1445 This section provides functions allowing to:
mbed_official 205:c41fc65bcfb4 1446 (+) Initialize and configure the TIM Input Capture.
mbed_official 205:c41fc65bcfb4 1447 (+) De-initialize the TIM Input Capture.
mbed_official 205:c41fc65bcfb4 1448 (+) Start the Time Input Capture.
mbed_official 205:c41fc65bcfb4 1449 (+) Stop the Time Input Capture.
mbed_official 205:c41fc65bcfb4 1450 (+) Start the Time Input Capture and enable interrupt.
mbed_official 205:c41fc65bcfb4 1451 (+) Stop the Time Input Capture and disable interrupt.
mbed_official 205:c41fc65bcfb4 1452 (+) Start the Time Input Capture and enable DMA transfer.
mbed_official 205:c41fc65bcfb4 1453 (+) Stop the Time Input Capture and disable DMA transfer.
mbed_official 205:c41fc65bcfb4 1454
mbed_official 205:c41fc65bcfb4 1455 @endverbatim
mbed_official 205:c41fc65bcfb4 1456 * @{
mbed_official 205:c41fc65bcfb4 1457 */
mbed_official 205:c41fc65bcfb4 1458 /**
mbed_official 205:c41fc65bcfb4 1459 * @brief Initializes the TIM Input Capture Time base according to the specified
mbed_official 205:c41fc65bcfb4 1460 * parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official 205:c41fc65bcfb4 1461 * @param htim: TIM Input Capture handle
mbed_official 205:c41fc65bcfb4 1462 * @retval HAL status
mbed_official 205:c41fc65bcfb4 1463 */
mbed_official 205:c41fc65bcfb4 1464 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 1465 {
mbed_official 205:c41fc65bcfb4 1466 /* Check the TIM handle allocation */
mbed_official 205:c41fc65bcfb4 1467 if(htim == NULL)
mbed_official 205:c41fc65bcfb4 1468 {
mbed_official 205:c41fc65bcfb4 1469 return HAL_ERROR;
mbed_official 205:c41fc65bcfb4 1470 }
mbed_official 205:c41fc65bcfb4 1471
mbed_official 205:c41fc65bcfb4 1472 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 1473 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 1474 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official 205:c41fc65bcfb4 1475 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official 205:c41fc65bcfb4 1476
mbed_official 205:c41fc65bcfb4 1477 if(htim->State == HAL_TIM_STATE_RESET)
mbed_official 205:c41fc65bcfb4 1478 {
mbed_official 205:c41fc65bcfb4 1479 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official 205:c41fc65bcfb4 1480 HAL_TIM_IC_MspInit(htim);
mbed_official 205:c41fc65bcfb4 1481 }
mbed_official 205:c41fc65bcfb4 1482
mbed_official 205:c41fc65bcfb4 1483 /* Set the TIM state */
mbed_official 205:c41fc65bcfb4 1484 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 205:c41fc65bcfb4 1485
mbed_official 205:c41fc65bcfb4 1486 /* Init the base time for the input capture */
mbed_official 205:c41fc65bcfb4 1487 TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official 205:c41fc65bcfb4 1488
mbed_official 205:c41fc65bcfb4 1489 /* Initialize the TIM state*/
mbed_official 205:c41fc65bcfb4 1490 htim->State= HAL_TIM_STATE_READY;
mbed_official 205:c41fc65bcfb4 1491
mbed_official 205:c41fc65bcfb4 1492 return HAL_OK;
mbed_official 205:c41fc65bcfb4 1493 }
mbed_official 205:c41fc65bcfb4 1494
mbed_official 205:c41fc65bcfb4 1495 /**
mbed_official 205:c41fc65bcfb4 1496 * @brief DeInitializes the TIM peripheral
mbed_official 205:c41fc65bcfb4 1497 * @param htim: TIM Input Capture handle
mbed_official 205:c41fc65bcfb4 1498 * @retval HAL status
mbed_official 205:c41fc65bcfb4 1499 */
mbed_official 205:c41fc65bcfb4 1500 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 1501 {
mbed_official 205:c41fc65bcfb4 1502 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 1503 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 1504
mbed_official 205:c41fc65bcfb4 1505 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 205:c41fc65bcfb4 1506
mbed_official 205:c41fc65bcfb4 1507 /* Disable the TIM Peripheral Clock */
mbed_official 205:c41fc65bcfb4 1508 __HAL_TIM_DISABLE(htim);
mbed_official 205:c41fc65bcfb4 1509
mbed_official 205:c41fc65bcfb4 1510 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
mbed_official 205:c41fc65bcfb4 1511 HAL_TIM_IC_MspDeInit(htim);
mbed_official 205:c41fc65bcfb4 1512
mbed_official 205:c41fc65bcfb4 1513 /* Change TIM state */
mbed_official 205:c41fc65bcfb4 1514 htim->State = HAL_TIM_STATE_RESET;
mbed_official 205:c41fc65bcfb4 1515
mbed_official 205:c41fc65bcfb4 1516 /* Release Lock */
mbed_official 205:c41fc65bcfb4 1517 __HAL_UNLOCK(htim);
mbed_official 205:c41fc65bcfb4 1518
mbed_official 205:c41fc65bcfb4 1519 return HAL_OK;
mbed_official 205:c41fc65bcfb4 1520 }
mbed_official 205:c41fc65bcfb4 1521
mbed_official 205:c41fc65bcfb4 1522 /**
mbed_official 205:c41fc65bcfb4 1523 * @brief Initializes the TIM INput Capture MSP.
mbed_official 205:c41fc65bcfb4 1524 * @param htim: TIM handle
mbed_official 205:c41fc65bcfb4 1525 * @retval None
mbed_official 205:c41fc65bcfb4 1526 */
mbed_official 205:c41fc65bcfb4 1527 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 1528 {
mbed_official 205:c41fc65bcfb4 1529 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 205:c41fc65bcfb4 1530 the HAL_TIM_IC_MspInit could be implemented in the user file
mbed_official 205:c41fc65bcfb4 1531 */
mbed_official 205:c41fc65bcfb4 1532 }
mbed_official 205:c41fc65bcfb4 1533
mbed_official 205:c41fc65bcfb4 1534 /**
mbed_official 205:c41fc65bcfb4 1535 * @brief DeInitializes TIM Input Capture MSP.
mbed_official 205:c41fc65bcfb4 1536 * @param htim: TIM handle
mbed_official 205:c41fc65bcfb4 1537 * @retval None
mbed_official 205:c41fc65bcfb4 1538 */
mbed_official 205:c41fc65bcfb4 1539 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 1540 {
mbed_official 205:c41fc65bcfb4 1541 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 205:c41fc65bcfb4 1542 the HAL_TIM_IC_MspDeInit could be implemented in the user file
mbed_official 205:c41fc65bcfb4 1543 */
mbed_official 205:c41fc65bcfb4 1544 }
mbed_official 205:c41fc65bcfb4 1545
mbed_official 205:c41fc65bcfb4 1546 /**
mbed_official 205:c41fc65bcfb4 1547 * @brief Starts the TIM Input Capture measurement.
mbed_official 205:c41fc65bcfb4 1548 * @param htim : TIM Input Capture handle
mbed_official 205:c41fc65bcfb4 1549 * @param Channel : TIM Channels to be enabled
mbed_official 205:c41fc65bcfb4 1550 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 1551 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 205:c41fc65bcfb4 1552 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 205:c41fc65bcfb4 1553 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 205:c41fc65bcfb4 1554 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 205:c41fc65bcfb4 1555 * @retval HAL status
mbed_official 205:c41fc65bcfb4 1556 */
mbed_official 205:c41fc65bcfb4 1557 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 205:c41fc65bcfb4 1558 {
mbed_official 205:c41fc65bcfb4 1559 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 1560 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 205:c41fc65bcfb4 1561
mbed_official 205:c41fc65bcfb4 1562 /* Enable the Input Capture channel */
mbed_official 205:c41fc65bcfb4 1563 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 205:c41fc65bcfb4 1564
mbed_official 205:c41fc65bcfb4 1565 /* Enable the Peripheral */
mbed_official 205:c41fc65bcfb4 1566 __HAL_TIM_ENABLE(htim);
mbed_official 205:c41fc65bcfb4 1567
mbed_official 205:c41fc65bcfb4 1568 /* Return function status */
mbed_official 205:c41fc65bcfb4 1569 return HAL_OK;
mbed_official 205:c41fc65bcfb4 1570 }
mbed_official 205:c41fc65bcfb4 1571
mbed_official 205:c41fc65bcfb4 1572 /**
mbed_official 205:c41fc65bcfb4 1573 * @brief Stops the TIM Input Capture measurement.
mbed_official 205:c41fc65bcfb4 1574 * @param htim : TIM handle
mbed_official 205:c41fc65bcfb4 1575 * @param Channel : TIM Channels to be disabled
mbed_official 205:c41fc65bcfb4 1576 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 1577 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 205:c41fc65bcfb4 1578 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 205:c41fc65bcfb4 1579 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 205:c41fc65bcfb4 1580 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 205:c41fc65bcfb4 1581 * @retval HAL status
mbed_official 205:c41fc65bcfb4 1582 */
mbed_official 205:c41fc65bcfb4 1583 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 205:c41fc65bcfb4 1584 {
mbed_official 205:c41fc65bcfb4 1585 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 1586 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 205:c41fc65bcfb4 1587
mbed_official 205:c41fc65bcfb4 1588 /* Disable the Input Capture channel */
mbed_official 205:c41fc65bcfb4 1589 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 205:c41fc65bcfb4 1590
mbed_official 205:c41fc65bcfb4 1591 /* Disable the Peripheral */
mbed_official 205:c41fc65bcfb4 1592 __HAL_TIM_DISABLE(htim);
mbed_official 205:c41fc65bcfb4 1593
mbed_official 205:c41fc65bcfb4 1594 /* Return function status */
mbed_official 205:c41fc65bcfb4 1595 return HAL_OK;
mbed_official 205:c41fc65bcfb4 1596 }
mbed_official 205:c41fc65bcfb4 1597
mbed_official 205:c41fc65bcfb4 1598 /**
mbed_official 205:c41fc65bcfb4 1599 * @brief Starts the TIM Input Capture measurement in interrupt mode.
mbed_official 205:c41fc65bcfb4 1600 * @param htim : TIM Input Capture handle
mbed_official 205:c41fc65bcfb4 1601 * @param Channel : TIM Channels to be enabled
mbed_official 205:c41fc65bcfb4 1602 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 1603 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 205:c41fc65bcfb4 1604 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 205:c41fc65bcfb4 1605 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 205:c41fc65bcfb4 1606 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 205:c41fc65bcfb4 1607 * @retval HAL status
mbed_official 205:c41fc65bcfb4 1608 */
mbed_official 205:c41fc65bcfb4 1609 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 205:c41fc65bcfb4 1610 {
mbed_official 205:c41fc65bcfb4 1611 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 1612 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 205:c41fc65bcfb4 1613
mbed_official 205:c41fc65bcfb4 1614 switch (Channel)
mbed_official 205:c41fc65bcfb4 1615 {
mbed_official 205:c41fc65bcfb4 1616 case TIM_CHANNEL_1:
mbed_official 205:c41fc65bcfb4 1617 {
mbed_official 205:c41fc65bcfb4 1618 /* Enable the TIM Capture/Compare 1 interrupt */
mbed_official 205:c41fc65bcfb4 1619 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official 205:c41fc65bcfb4 1620 }
mbed_official 205:c41fc65bcfb4 1621 break;
mbed_official 205:c41fc65bcfb4 1622
mbed_official 205:c41fc65bcfb4 1623 case TIM_CHANNEL_2:
mbed_official 205:c41fc65bcfb4 1624 {
mbed_official 205:c41fc65bcfb4 1625 /* Enable the TIM Capture/Compare 2 interrupt */
mbed_official 205:c41fc65bcfb4 1626 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official 205:c41fc65bcfb4 1627 }
mbed_official 205:c41fc65bcfb4 1628 break;
mbed_official 205:c41fc65bcfb4 1629
mbed_official 205:c41fc65bcfb4 1630 case TIM_CHANNEL_3:
mbed_official 205:c41fc65bcfb4 1631 {
mbed_official 205:c41fc65bcfb4 1632 /* Enable the TIM Capture/Compare 3 interrupt */
mbed_official 205:c41fc65bcfb4 1633 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
mbed_official 205:c41fc65bcfb4 1634 }
mbed_official 205:c41fc65bcfb4 1635 break;
mbed_official 205:c41fc65bcfb4 1636
mbed_official 205:c41fc65bcfb4 1637 case TIM_CHANNEL_4:
mbed_official 205:c41fc65bcfb4 1638 {
mbed_official 205:c41fc65bcfb4 1639 /* Enable the TIM Capture/Compare 4 interrupt */
mbed_official 205:c41fc65bcfb4 1640 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
mbed_official 205:c41fc65bcfb4 1641 }
mbed_official 205:c41fc65bcfb4 1642 break;
mbed_official 205:c41fc65bcfb4 1643
mbed_official 205:c41fc65bcfb4 1644 default:
mbed_official 205:c41fc65bcfb4 1645 break;
mbed_official 205:c41fc65bcfb4 1646 }
mbed_official 205:c41fc65bcfb4 1647 /* Enable the Input Capture channel */
mbed_official 205:c41fc65bcfb4 1648 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 205:c41fc65bcfb4 1649
mbed_official 205:c41fc65bcfb4 1650 /* Enable the Peripheral */
mbed_official 205:c41fc65bcfb4 1651 __HAL_TIM_ENABLE(htim);
mbed_official 205:c41fc65bcfb4 1652
mbed_official 205:c41fc65bcfb4 1653 /* Return function status */
mbed_official 205:c41fc65bcfb4 1654 return HAL_OK;
mbed_official 205:c41fc65bcfb4 1655 }
mbed_official 205:c41fc65bcfb4 1656
mbed_official 205:c41fc65bcfb4 1657 /**
mbed_official 205:c41fc65bcfb4 1658 * @brief Stops the TIM Input Capture measurement in interrupt mode.
mbed_official 205:c41fc65bcfb4 1659 * @param htim : TIM handle
mbed_official 205:c41fc65bcfb4 1660 * @param Channel : TIM Channels to be disabled
mbed_official 205:c41fc65bcfb4 1661 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 1662 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 205:c41fc65bcfb4 1663 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 205:c41fc65bcfb4 1664 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 205:c41fc65bcfb4 1665 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 205:c41fc65bcfb4 1666 * @retval HAL status
mbed_official 205:c41fc65bcfb4 1667 */
mbed_official 205:c41fc65bcfb4 1668 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 205:c41fc65bcfb4 1669 {
mbed_official 205:c41fc65bcfb4 1670 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 1671 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 205:c41fc65bcfb4 1672
mbed_official 205:c41fc65bcfb4 1673 switch (Channel)
mbed_official 205:c41fc65bcfb4 1674 {
mbed_official 205:c41fc65bcfb4 1675 case TIM_CHANNEL_1:
mbed_official 205:c41fc65bcfb4 1676 {
mbed_official 205:c41fc65bcfb4 1677 /* Disable the TIM Capture/Compare 1 interrupt */
mbed_official 205:c41fc65bcfb4 1678 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official 205:c41fc65bcfb4 1679 }
mbed_official 205:c41fc65bcfb4 1680 break;
mbed_official 205:c41fc65bcfb4 1681
mbed_official 205:c41fc65bcfb4 1682 case TIM_CHANNEL_2:
mbed_official 205:c41fc65bcfb4 1683 {
mbed_official 205:c41fc65bcfb4 1684 /* Disable the TIM Capture/Compare 2 interrupt */
mbed_official 205:c41fc65bcfb4 1685 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official 205:c41fc65bcfb4 1686 }
mbed_official 205:c41fc65bcfb4 1687 break;
mbed_official 205:c41fc65bcfb4 1688
mbed_official 205:c41fc65bcfb4 1689 case TIM_CHANNEL_3:
mbed_official 205:c41fc65bcfb4 1690 {
mbed_official 205:c41fc65bcfb4 1691 /* Disable the TIM Capture/Compare 3 interrupt */
mbed_official 205:c41fc65bcfb4 1692 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
mbed_official 205:c41fc65bcfb4 1693 }
mbed_official 205:c41fc65bcfb4 1694 break;
mbed_official 205:c41fc65bcfb4 1695
mbed_official 205:c41fc65bcfb4 1696 case TIM_CHANNEL_4:
mbed_official 205:c41fc65bcfb4 1697 {
mbed_official 205:c41fc65bcfb4 1698 /* Disable the TIM Capture/Compare 4 interrupt */
mbed_official 205:c41fc65bcfb4 1699 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
mbed_official 205:c41fc65bcfb4 1700 }
mbed_official 205:c41fc65bcfb4 1701 break;
mbed_official 205:c41fc65bcfb4 1702
mbed_official 205:c41fc65bcfb4 1703 default:
mbed_official 205:c41fc65bcfb4 1704 break;
mbed_official 205:c41fc65bcfb4 1705 }
mbed_official 205:c41fc65bcfb4 1706
mbed_official 205:c41fc65bcfb4 1707 /* Disable the Input Capture channel */
mbed_official 205:c41fc65bcfb4 1708 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 205:c41fc65bcfb4 1709
mbed_official 205:c41fc65bcfb4 1710 /* Disable the Peripheral */
mbed_official 205:c41fc65bcfb4 1711 __HAL_TIM_DISABLE(htim);
mbed_official 205:c41fc65bcfb4 1712
mbed_official 205:c41fc65bcfb4 1713 /* Return function status */
mbed_official 205:c41fc65bcfb4 1714 return HAL_OK;
mbed_official 205:c41fc65bcfb4 1715 }
mbed_official 205:c41fc65bcfb4 1716
mbed_official 205:c41fc65bcfb4 1717 /**
mbed_official 205:c41fc65bcfb4 1718 * @brief Starts the TIM Input Capture measurement on in DMA mode.
mbed_official 205:c41fc65bcfb4 1719 * @param htim : TIM Input Capture handle
mbed_official 205:c41fc65bcfb4 1720 * @param Channel : TIM Channels to be enabled
mbed_official 205:c41fc65bcfb4 1721 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 1722 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 205:c41fc65bcfb4 1723 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 205:c41fc65bcfb4 1724 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 205:c41fc65bcfb4 1725 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 205:c41fc65bcfb4 1726 * @param pData: The destination Buffer address.
mbed_official 205:c41fc65bcfb4 1727 * @param Length: The length of data to be transferred from TIM peripheral to memory.
mbed_official 205:c41fc65bcfb4 1728 * @retval HAL status
mbed_official 205:c41fc65bcfb4 1729 */
mbed_official 205:c41fc65bcfb4 1730 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
mbed_official 205:c41fc65bcfb4 1731 {
mbed_official 205:c41fc65bcfb4 1732 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 1733 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 205:c41fc65bcfb4 1734 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 1735
mbed_official 205:c41fc65bcfb4 1736 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 205:c41fc65bcfb4 1737 {
mbed_official 205:c41fc65bcfb4 1738 return HAL_BUSY;
mbed_official 205:c41fc65bcfb4 1739 }
mbed_official 205:c41fc65bcfb4 1740 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 205:c41fc65bcfb4 1741 {
mbed_official 205:c41fc65bcfb4 1742 if((pData == 0 ) && (Length > 0))
mbed_official 205:c41fc65bcfb4 1743 {
mbed_official 205:c41fc65bcfb4 1744 return HAL_ERROR;
mbed_official 205:c41fc65bcfb4 1745 }
mbed_official 205:c41fc65bcfb4 1746 else
mbed_official 205:c41fc65bcfb4 1747 {
mbed_official 205:c41fc65bcfb4 1748 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 205:c41fc65bcfb4 1749 }
mbed_official 205:c41fc65bcfb4 1750 }
mbed_official 205:c41fc65bcfb4 1751
mbed_official 205:c41fc65bcfb4 1752 switch (Channel)
mbed_official 205:c41fc65bcfb4 1753 {
mbed_official 205:c41fc65bcfb4 1754 case TIM_CHANNEL_1:
mbed_official 205:c41fc65bcfb4 1755 {
mbed_official 205:c41fc65bcfb4 1756 /* Set the DMA Period elapsed callback */
mbed_official 205:c41fc65bcfb4 1757 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official 205:c41fc65bcfb4 1758
mbed_official 205:c41fc65bcfb4 1759 /* Set the DMA error callback */
mbed_official 205:c41fc65bcfb4 1760 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 205:c41fc65bcfb4 1761
mbed_official 205:c41fc65bcfb4 1762 /* Enable the DMA channel */
mbed_official 205:c41fc65bcfb4 1763 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
mbed_official 205:c41fc65bcfb4 1764
mbed_official 205:c41fc65bcfb4 1765 /* Enable the TIM Capture/Compare 1 DMA request */
mbed_official 205:c41fc65bcfb4 1766 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 205:c41fc65bcfb4 1767 }
mbed_official 205:c41fc65bcfb4 1768 break;
mbed_official 205:c41fc65bcfb4 1769
mbed_official 205:c41fc65bcfb4 1770 case TIM_CHANNEL_2:
mbed_official 205:c41fc65bcfb4 1771 {
mbed_official 205:c41fc65bcfb4 1772 /* Set the DMA Period elapsed callback */
mbed_official 205:c41fc65bcfb4 1773 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official 205:c41fc65bcfb4 1774
mbed_official 205:c41fc65bcfb4 1775 /* Set the DMA error callback */
mbed_official 205:c41fc65bcfb4 1776 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 205:c41fc65bcfb4 1777
mbed_official 205:c41fc65bcfb4 1778 /* Enable the DMA channel */
mbed_official 205:c41fc65bcfb4 1779 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
mbed_official 205:c41fc65bcfb4 1780
mbed_official 205:c41fc65bcfb4 1781 /* Enable the TIM Capture/Compare 2 DMA request */
mbed_official 205:c41fc65bcfb4 1782 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 205:c41fc65bcfb4 1783 }
mbed_official 205:c41fc65bcfb4 1784 break;
mbed_official 205:c41fc65bcfb4 1785
mbed_official 205:c41fc65bcfb4 1786 case TIM_CHANNEL_3:
mbed_official 205:c41fc65bcfb4 1787 {
mbed_official 205:c41fc65bcfb4 1788 /* Set the DMA Period elapsed callback */
mbed_official 205:c41fc65bcfb4 1789 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official 205:c41fc65bcfb4 1790
mbed_official 205:c41fc65bcfb4 1791 /* Set the DMA error callback */
mbed_official 205:c41fc65bcfb4 1792 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 205:c41fc65bcfb4 1793
mbed_official 205:c41fc65bcfb4 1794 /* Enable the DMA channel */
mbed_official 205:c41fc65bcfb4 1795 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
mbed_official 205:c41fc65bcfb4 1796
mbed_official 205:c41fc65bcfb4 1797 /* Enable the TIM Capture/Compare 3 DMA request */
mbed_official 205:c41fc65bcfb4 1798 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
mbed_official 205:c41fc65bcfb4 1799 }
mbed_official 205:c41fc65bcfb4 1800 break;
mbed_official 205:c41fc65bcfb4 1801
mbed_official 205:c41fc65bcfb4 1802 case TIM_CHANNEL_4:
mbed_official 205:c41fc65bcfb4 1803 {
mbed_official 205:c41fc65bcfb4 1804 /* Set the DMA Period elapsed callback */
mbed_official 205:c41fc65bcfb4 1805 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official 205:c41fc65bcfb4 1806
mbed_official 205:c41fc65bcfb4 1807 /* Set the DMA error callback */
mbed_official 205:c41fc65bcfb4 1808 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 205:c41fc65bcfb4 1809
mbed_official 205:c41fc65bcfb4 1810 /* Enable the DMA channel */
mbed_official 205:c41fc65bcfb4 1811 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
mbed_official 205:c41fc65bcfb4 1812
mbed_official 205:c41fc65bcfb4 1813 /* Enable the TIM Capture/Compare 4 DMA request */
mbed_official 205:c41fc65bcfb4 1814 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
mbed_official 205:c41fc65bcfb4 1815 }
mbed_official 205:c41fc65bcfb4 1816 break;
mbed_official 205:c41fc65bcfb4 1817
mbed_official 205:c41fc65bcfb4 1818 default:
mbed_official 205:c41fc65bcfb4 1819 break;
mbed_official 205:c41fc65bcfb4 1820 }
mbed_official 205:c41fc65bcfb4 1821
mbed_official 205:c41fc65bcfb4 1822 /* Enable the Input Capture channel */
mbed_official 205:c41fc65bcfb4 1823 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 205:c41fc65bcfb4 1824
mbed_official 205:c41fc65bcfb4 1825 /* Enable the Peripheral */
mbed_official 205:c41fc65bcfb4 1826 __HAL_TIM_ENABLE(htim);
mbed_official 205:c41fc65bcfb4 1827
mbed_official 205:c41fc65bcfb4 1828 /* Return function status */
mbed_official 205:c41fc65bcfb4 1829 return HAL_OK;
mbed_official 205:c41fc65bcfb4 1830 }
mbed_official 205:c41fc65bcfb4 1831
mbed_official 205:c41fc65bcfb4 1832 /**
mbed_official 205:c41fc65bcfb4 1833 * @brief Stops the TIM Input Capture measurement on in DMA mode.
mbed_official 205:c41fc65bcfb4 1834 * @param htim : TIM Input Capture handle
mbed_official 205:c41fc65bcfb4 1835 * @param Channel : TIM Channels to be disabled
mbed_official 205:c41fc65bcfb4 1836 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 1837 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 205:c41fc65bcfb4 1838 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 205:c41fc65bcfb4 1839 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 205:c41fc65bcfb4 1840 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 205:c41fc65bcfb4 1841 * @retval HAL status
mbed_official 205:c41fc65bcfb4 1842 */
mbed_official 205:c41fc65bcfb4 1843 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 205:c41fc65bcfb4 1844 {
mbed_official 205:c41fc65bcfb4 1845 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 1846 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 205:c41fc65bcfb4 1847 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 1848
mbed_official 205:c41fc65bcfb4 1849 switch (Channel)
mbed_official 205:c41fc65bcfb4 1850 {
mbed_official 205:c41fc65bcfb4 1851 case TIM_CHANNEL_1:
mbed_official 205:c41fc65bcfb4 1852 {
mbed_official 205:c41fc65bcfb4 1853 /* Disable the TIM Capture/Compare 1 DMA request */
mbed_official 205:c41fc65bcfb4 1854 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 205:c41fc65bcfb4 1855 }
mbed_official 205:c41fc65bcfb4 1856 break;
mbed_official 205:c41fc65bcfb4 1857
mbed_official 205:c41fc65bcfb4 1858 case TIM_CHANNEL_2:
mbed_official 205:c41fc65bcfb4 1859 {
mbed_official 205:c41fc65bcfb4 1860 /* Disable the TIM Capture/Compare 2 DMA request */
mbed_official 205:c41fc65bcfb4 1861 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 205:c41fc65bcfb4 1862 }
mbed_official 205:c41fc65bcfb4 1863 break;
mbed_official 205:c41fc65bcfb4 1864
mbed_official 205:c41fc65bcfb4 1865 case TIM_CHANNEL_3:
mbed_official 205:c41fc65bcfb4 1866 {
mbed_official 205:c41fc65bcfb4 1867 /* Disable the TIM Capture/Compare 3 DMA request */
mbed_official 205:c41fc65bcfb4 1868 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
mbed_official 205:c41fc65bcfb4 1869 }
mbed_official 205:c41fc65bcfb4 1870 break;
mbed_official 205:c41fc65bcfb4 1871
mbed_official 205:c41fc65bcfb4 1872 case TIM_CHANNEL_4:
mbed_official 205:c41fc65bcfb4 1873 {
mbed_official 205:c41fc65bcfb4 1874 /* Disable the TIM Capture/Compare 4 DMA request */
mbed_official 205:c41fc65bcfb4 1875 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
mbed_official 205:c41fc65bcfb4 1876 }
mbed_official 205:c41fc65bcfb4 1877 break;
mbed_official 205:c41fc65bcfb4 1878
mbed_official 205:c41fc65bcfb4 1879 default:
mbed_official 205:c41fc65bcfb4 1880 break;
mbed_official 205:c41fc65bcfb4 1881 }
mbed_official 205:c41fc65bcfb4 1882
mbed_official 205:c41fc65bcfb4 1883 /* Disable the Input Capture channel */
mbed_official 205:c41fc65bcfb4 1884 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 205:c41fc65bcfb4 1885
mbed_official 205:c41fc65bcfb4 1886 /* Disable the Peripheral */
mbed_official 205:c41fc65bcfb4 1887 __HAL_TIM_DISABLE(htim);
mbed_official 205:c41fc65bcfb4 1888
mbed_official 205:c41fc65bcfb4 1889 /* Change the htim state */
mbed_official 205:c41fc65bcfb4 1890 htim->State = HAL_TIM_STATE_READY;
mbed_official 205:c41fc65bcfb4 1891
mbed_official 205:c41fc65bcfb4 1892 /* Return function status */
mbed_official 205:c41fc65bcfb4 1893 return HAL_OK;
mbed_official 205:c41fc65bcfb4 1894 }
mbed_official 205:c41fc65bcfb4 1895 /**
mbed_official 205:c41fc65bcfb4 1896 * @}
mbed_official 205:c41fc65bcfb4 1897 */
mbed_official 205:c41fc65bcfb4 1898
mbed_official 205:c41fc65bcfb4 1899 /** @defgroup TIM_Group5 Time One Pulse functions
mbed_official 205:c41fc65bcfb4 1900 * @brief Time One Pulse functions
mbed_official 205:c41fc65bcfb4 1901 *
mbed_official 205:c41fc65bcfb4 1902 @verbatim
mbed_official 205:c41fc65bcfb4 1903 ==============================================================================
mbed_official 205:c41fc65bcfb4 1904 ##### Time One Pulse functions #####
mbed_official 205:c41fc65bcfb4 1905 ==============================================================================
mbed_official 205:c41fc65bcfb4 1906 [..]
mbed_official 205:c41fc65bcfb4 1907 This section provides functions allowing to:
mbed_official 205:c41fc65bcfb4 1908 (+) Initialize and configure the TIM One Pulse.
mbed_official 205:c41fc65bcfb4 1909 (+) De-initialize the TIM One Pulse.
mbed_official 205:c41fc65bcfb4 1910 (+) Start the Time One Pulse.
mbed_official 205:c41fc65bcfb4 1911 (+) Stop the Time One Pulse.
mbed_official 205:c41fc65bcfb4 1912 (+) Start the Time One Pulse and enable interrupt.
mbed_official 205:c41fc65bcfb4 1913 (+) Stop the Time One Pulse and disable interrupt.
mbed_official 205:c41fc65bcfb4 1914 (+) Start the Time One Pulse and enable DMA transfer.
mbed_official 205:c41fc65bcfb4 1915 (+) Stop the Time One Pulse and disable DMA transfer.
mbed_official 205:c41fc65bcfb4 1916
mbed_official 205:c41fc65bcfb4 1917 @endverbatim
mbed_official 205:c41fc65bcfb4 1918 * @{
mbed_official 205:c41fc65bcfb4 1919 */
mbed_official 205:c41fc65bcfb4 1920 /**
mbed_official 205:c41fc65bcfb4 1921 * @brief Initializes the TIM One Pulse Time Base according to the specified
mbed_official 205:c41fc65bcfb4 1922 * parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official 205:c41fc65bcfb4 1923 * @param htim: TIM OnePulse handle
mbed_official 205:c41fc65bcfb4 1924 * @param OnePulseMode: Select the One pulse mode.
mbed_official 205:c41fc65bcfb4 1925 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 1926 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
mbed_official 205:c41fc65bcfb4 1927 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
mbed_official 205:c41fc65bcfb4 1928 * @retval HAL status
mbed_official 205:c41fc65bcfb4 1929 */
mbed_official 205:c41fc65bcfb4 1930 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
mbed_official 205:c41fc65bcfb4 1931 {
mbed_official 205:c41fc65bcfb4 1932 /* Check the TIM handle allocation */
mbed_official 205:c41fc65bcfb4 1933 if(htim == NULL)
mbed_official 205:c41fc65bcfb4 1934 {
mbed_official 205:c41fc65bcfb4 1935 return HAL_ERROR;
mbed_official 205:c41fc65bcfb4 1936 }
mbed_official 205:c41fc65bcfb4 1937
mbed_official 205:c41fc65bcfb4 1938 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 1939 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 1940 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official 205:c41fc65bcfb4 1941 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official 205:c41fc65bcfb4 1942 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
mbed_official 205:c41fc65bcfb4 1943
mbed_official 205:c41fc65bcfb4 1944 if(htim->State == HAL_TIM_STATE_RESET)
mbed_official 205:c41fc65bcfb4 1945 {
mbed_official 205:c41fc65bcfb4 1946 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official 205:c41fc65bcfb4 1947 HAL_TIM_OnePulse_MspInit(htim);
mbed_official 205:c41fc65bcfb4 1948 }
mbed_official 205:c41fc65bcfb4 1949
mbed_official 205:c41fc65bcfb4 1950 /* Set the TIM state */
mbed_official 205:c41fc65bcfb4 1951 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 205:c41fc65bcfb4 1952
mbed_official 205:c41fc65bcfb4 1953 /* Configure the Time base in the One Pulse Mode */
mbed_official 205:c41fc65bcfb4 1954 TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official 205:c41fc65bcfb4 1955
mbed_official 205:c41fc65bcfb4 1956 /* Reset the OPM Bit */
mbed_official 205:c41fc65bcfb4 1957 htim->Instance->CR1 &= (uint16_t)(~TIM_CR1_OPM);
mbed_official 205:c41fc65bcfb4 1958
mbed_official 205:c41fc65bcfb4 1959 /* Configure the OPM Mode */
mbed_official 205:c41fc65bcfb4 1960 htim->Instance->CR1 |= OnePulseMode;
mbed_official 205:c41fc65bcfb4 1961
mbed_official 205:c41fc65bcfb4 1962 /* Initialize the TIM state*/
mbed_official 205:c41fc65bcfb4 1963 htim->State= HAL_TIM_STATE_READY;
mbed_official 205:c41fc65bcfb4 1964
mbed_official 205:c41fc65bcfb4 1965 return HAL_OK;
mbed_official 205:c41fc65bcfb4 1966 }
mbed_official 205:c41fc65bcfb4 1967
mbed_official 205:c41fc65bcfb4 1968 /**
mbed_official 205:c41fc65bcfb4 1969 * @brief DeInitializes the TIM One Pulse
mbed_official 205:c41fc65bcfb4 1970 * @param htim: TIM One Pulse handle
mbed_official 205:c41fc65bcfb4 1971 * @retval HAL status
mbed_official 205:c41fc65bcfb4 1972 */
mbed_official 205:c41fc65bcfb4 1973 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 1974 {
mbed_official 205:c41fc65bcfb4 1975 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 1976 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 1977
mbed_official 205:c41fc65bcfb4 1978 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 205:c41fc65bcfb4 1979
mbed_official 205:c41fc65bcfb4 1980 /* Disable the TIM Peripheral Clock */
mbed_official 205:c41fc65bcfb4 1981 __HAL_TIM_DISABLE(htim);
mbed_official 205:c41fc65bcfb4 1982
mbed_official 205:c41fc65bcfb4 1983 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
mbed_official 205:c41fc65bcfb4 1984 HAL_TIM_OnePulse_MspDeInit(htim);
mbed_official 205:c41fc65bcfb4 1985
mbed_official 205:c41fc65bcfb4 1986 /* Change TIM state */
mbed_official 205:c41fc65bcfb4 1987 htim->State = HAL_TIM_STATE_RESET;
mbed_official 205:c41fc65bcfb4 1988
mbed_official 205:c41fc65bcfb4 1989 /* Release Lock */
mbed_official 205:c41fc65bcfb4 1990 __HAL_UNLOCK(htim);
mbed_official 205:c41fc65bcfb4 1991
mbed_official 205:c41fc65bcfb4 1992 return HAL_OK;
mbed_official 205:c41fc65bcfb4 1993 }
mbed_official 205:c41fc65bcfb4 1994
mbed_official 205:c41fc65bcfb4 1995 /**
mbed_official 205:c41fc65bcfb4 1996 * @brief Initializes the TIM One Pulse MSP.
mbed_official 205:c41fc65bcfb4 1997 * @param htim: TIM handle
mbed_official 205:c41fc65bcfb4 1998 * @retval None
mbed_official 205:c41fc65bcfb4 1999 */
mbed_official 205:c41fc65bcfb4 2000 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 2001 {
mbed_official 205:c41fc65bcfb4 2002 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 205:c41fc65bcfb4 2003 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
mbed_official 205:c41fc65bcfb4 2004 */
mbed_official 205:c41fc65bcfb4 2005 }
mbed_official 205:c41fc65bcfb4 2006
mbed_official 205:c41fc65bcfb4 2007 /**
mbed_official 205:c41fc65bcfb4 2008 * @brief DeInitializes TIM One Pulse MSP.
mbed_official 205:c41fc65bcfb4 2009 * @param htim: TIM handle
mbed_official 205:c41fc65bcfb4 2010 * @retval None
mbed_official 205:c41fc65bcfb4 2011 */
mbed_official 205:c41fc65bcfb4 2012 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 2013 {
mbed_official 205:c41fc65bcfb4 2014 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 205:c41fc65bcfb4 2015 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
mbed_official 205:c41fc65bcfb4 2016 */
mbed_official 205:c41fc65bcfb4 2017 }
mbed_official 205:c41fc65bcfb4 2018
mbed_official 205:c41fc65bcfb4 2019 /**
mbed_official 205:c41fc65bcfb4 2020 * @brief Starts the TIM One Pulse signal generation.
mbed_official 205:c41fc65bcfb4 2021 * @param htim : TIM One Pulse handle
mbed_official 205:c41fc65bcfb4 2022 * @param OutputChannel : TIM Channels to be enabled
mbed_official 205:c41fc65bcfb4 2023 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 2024 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 205:c41fc65bcfb4 2025 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 205:c41fc65bcfb4 2026 * @retval HAL status
mbed_official 205:c41fc65bcfb4 2027 */
mbed_official 205:c41fc65bcfb4 2028 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
mbed_official 205:c41fc65bcfb4 2029 {
mbed_official 205:c41fc65bcfb4 2030 /* Enable the Capture compare and the Input Capture channels
mbed_official 205:c41fc65bcfb4 2031 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
mbed_official 205:c41fc65bcfb4 2032 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
mbed_official 205:c41fc65bcfb4 2033 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
mbed_official 205:c41fc65bcfb4 2034 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
mbed_official 205:c41fc65bcfb4 2035
mbed_official 205:c41fc65bcfb4 2036 No need to enable the counter, it's enabled automatically by hardware
mbed_official 205:c41fc65bcfb4 2037 (the counter starts in response to a stimulus and generate a pulse */
mbed_official 205:c41fc65bcfb4 2038
mbed_official 205:c41fc65bcfb4 2039 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 205:c41fc65bcfb4 2040 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 205:c41fc65bcfb4 2041
mbed_official 205:c41fc65bcfb4 2042 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official 205:c41fc65bcfb4 2043 {
mbed_official 205:c41fc65bcfb4 2044 /* Enable the main output */
mbed_official 205:c41fc65bcfb4 2045 __HAL_TIM_MOE_ENABLE(htim);
mbed_official 205:c41fc65bcfb4 2046 }
mbed_official 205:c41fc65bcfb4 2047
mbed_official 205:c41fc65bcfb4 2048 /* Return function status */
mbed_official 205:c41fc65bcfb4 2049 return HAL_OK;
mbed_official 205:c41fc65bcfb4 2050 }
mbed_official 205:c41fc65bcfb4 2051
mbed_official 205:c41fc65bcfb4 2052 /**
mbed_official 205:c41fc65bcfb4 2053 * @brief Stops the TIM One Pulse signal generation.
mbed_official 205:c41fc65bcfb4 2054 * @param htim : TIM One Pulse handle
mbed_official 205:c41fc65bcfb4 2055 * @param OutputChannel : TIM Channels to be disable
mbed_official 205:c41fc65bcfb4 2056 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 2057 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 205:c41fc65bcfb4 2058 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 205:c41fc65bcfb4 2059 * @retval HAL status
mbed_official 205:c41fc65bcfb4 2060 */
mbed_official 205:c41fc65bcfb4 2061 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
mbed_official 205:c41fc65bcfb4 2062 {
mbed_official 205:c41fc65bcfb4 2063 /* Disable the Capture compare and the Input Capture channels
mbed_official 205:c41fc65bcfb4 2064 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
mbed_official 205:c41fc65bcfb4 2065 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
mbed_official 205:c41fc65bcfb4 2066 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
mbed_official 205:c41fc65bcfb4 2067 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
mbed_official 205:c41fc65bcfb4 2068
mbed_official 205:c41fc65bcfb4 2069 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 205:c41fc65bcfb4 2070 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 205:c41fc65bcfb4 2071
mbed_official 205:c41fc65bcfb4 2072 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official 205:c41fc65bcfb4 2073 {
mbed_official 205:c41fc65bcfb4 2074 /* Disable the Main Ouput */
mbed_official 205:c41fc65bcfb4 2075 __HAL_TIM_MOE_DISABLE(htim);
mbed_official 205:c41fc65bcfb4 2076 }
mbed_official 205:c41fc65bcfb4 2077
mbed_official 205:c41fc65bcfb4 2078 /* Disable the Peripheral */
mbed_official 205:c41fc65bcfb4 2079 __HAL_TIM_DISABLE(htim);
mbed_official 205:c41fc65bcfb4 2080
mbed_official 205:c41fc65bcfb4 2081 /* Return function status */
mbed_official 205:c41fc65bcfb4 2082 return HAL_OK;
mbed_official 205:c41fc65bcfb4 2083 }
mbed_official 205:c41fc65bcfb4 2084
mbed_official 205:c41fc65bcfb4 2085 /**
mbed_official 205:c41fc65bcfb4 2086 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
mbed_official 205:c41fc65bcfb4 2087 * @param htim : TIM One Pulse handle
mbed_official 205:c41fc65bcfb4 2088 * @param OutputChannel : TIM Channels to be enabled
mbed_official 205:c41fc65bcfb4 2089 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 2090 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 205:c41fc65bcfb4 2091 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 205:c41fc65bcfb4 2092 * @retval HAL status
mbed_official 205:c41fc65bcfb4 2093 */
mbed_official 205:c41fc65bcfb4 2094 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
mbed_official 205:c41fc65bcfb4 2095 {
mbed_official 205:c41fc65bcfb4 2096 /* Enable the Capture compare and the Input Capture channels
mbed_official 205:c41fc65bcfb4 2097 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
mbed_official 205:c41fc65bcfb4 2098 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
mbed_official 205:c41fc65bcfb4 2099 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
mbed_official 205:c41fc65bcfb4 2100 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
mbed_official 205:c41fc65bcfb4 2101
mbed_official 205:c41fc65bcfb4 2102 No need to enable the counter, it's enabled automatically by hardware
mbed_official 205:c41fc65bcfb4 2103 (the counter starts in response to a stimulus and generate a pulse */
mbed_official 205:c41fc65bcfb4 2104
mbed_official 205:c41fc65bcfb4 2105 /* Enable the TIM Capture/Compare 1 interrupt */
mbed_official 205:c41fc65bcfb4 2106 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official 205:c41fc65bcfb4 2107
mbed_official 205:c41fc65bcfb4 2108 /* Enable the TIM Capture/Compare 2 interrupt */
mbed_official 205:c41fc65bcfb4 2109 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official 205:c41fc65bcfb4 2110
mbed_official 205:c41fc65bcfb4 2111 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 205:c41fc65bcfb4 2112 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 205:c41fc65bcfb4 2113
mbed_official 205:c41fc65bcfb4 2114 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official 205:c41fc65bcfb4 2115 {
mbed_official 205:c41fc65bcfb4 2116 /* Enable the main output */
mbed_official 205:c41fc65bcfb4 2117 __HAL_TIM_MOE_ENABLE(htim);
mbed_official 205:c41fc65bcfb4 2118 }
mbed_official 205:c41fc65bcfb4 2119
mbed_official 205:c41fc65bcfb4 2120 /* Return function status */
mbed_official 205:c41fc65bcfb4 2121 return HAL_OK;
mbed_official 205:c41fc65bcfb4 2122 }
mbed_official 205:c41fc65bcfb4 2123
mbed_official 205:c41fc65bcfb4 2124 /**
mbed_official 205:c41fc65bcfb4 2125 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
mbed_official 205:c41fc65bcfb4 2126 * @param htim : TIM One Pulse handle
mbed_official 205:c41fc65bcfb4 2127 * @param OutputChannel : TIM Channels to be enabled
mbed_official 205:c41fc65bcfb4 2128 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 2129 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 205:c41fc65bcfb4 2130 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 205:c41fc65bcfb4 2131 * @retval HAL status
mbed_official 205:c41fc65bcfb4 2132 */
mbed_official 205:c41fc65bcfb4 2133 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
mbed_official 205:c41fc65bcfb4 2134 {
mbed_official 205:c41fc65bcfb4 2135 /* Disable the TIM Capture/Compare 1 interrupt */
mbed_official 205:c41fc65bcfb4 2136 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official 205:c41fc65bcfb4 2137
mbed_official 205:c41fc65bcfb4 2138 /* Disable the TIM Capture/Compare 2 interrupt */
mbed_official 205:c41fc65bcfb4 2139 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official 205:c41fc65bcfb4 2140
mbed_official 205:c41fc65bcfb4 2141 /* Disable the Capture compare and the Input Capture channels
mbed_official 205:c41fc65bcfb4 2142 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
mbed_official 205:c41fc65bcfb4 2143 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
mbed_official 205:c41fc65bcfb4 2144 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
mbed_official 205:c41fc65bcfb4 2145 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
mbed_official 205:c41fc65bcfb4 2146 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 205:c41fc65bcfb4 2147 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 205:c41fc65bcfb4 2148
mbed_official 205:c41fc65bcfb4 2149 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official 205:c41fc65bcfb4 2150 {
mbed_official 205:c41fc65bcfb4 2151 /* Disable the Main Ouput */
mbed_official 205:c41fc65bcfb4 2152 __HAL_TIM_MOE_DISABLE(htim);
mbed_official 205:c41fc65bcfb4 2153 }
mbed_official 205:c41fc65bcfb4 2154
mbed_official 205:c41fc65bcfb4 2155 /* Disable the Peripheral */
mbed_official 205:c41fc65bcfb4 2156 __HAL_TIM_DISABLE(htim);
mbed_official 205:c41fc65bcfb4 2157
mbed_official 205:c41fc65bcfb4 2158 /* Return function status */
mbed_official 205:c41fc65bcfb4 2159 return HAL_OK;
mbed_official 205:c41fc65bcfb4 2160 }
mbed_official 205:c41fc65bcfb4 2161
mbed_official 205:c41fc65bcfb4 2162 /**
mbed_official 205:c41fc65bcfb4 2163 * @}
mbed_official 205:c41fc65bcfb4 2164 */
mbed_official 205:c41fc65bcfb4 2165
mbed_official 205:c41fc65bcfb4 2166 /** @defgroup TIM_Group6 Time Encoder functions
mbed_official 205:c41fc65bcfb4 2167 * @brief Time Encoder functions
mbed_official 205:c41fc65bcfb4 2168 *
mbed_official 205:c41fc65bcfb4 2169 @verbatim
mbed_official 205:c41fc65bcfb4 2170 ==============================================================================
mbed_official 205:c41fc65bcfb4 2171 ##### Time Encoder functions #####
mbed_official 205:c41fc65bcfb4 2172 ==============================================================================
mbed_official 205:c41fc65bcfb4 2173 [..]
mbed_official 205:c41fc65bcfb4 2174 This section provides functions allowing to:
mbed_official 205:c41fc65bcfb4 2175 (+) Initialize and configure the TIM Encoder.
mbed_official 205:c41fc65bcfb4 2176 (+) De-initialize the TIM Encoder.
mbed_official 205:c41fc65bcfb4 2177 (+) Start the Time Encoder.
mbed_official 205:c41fc65bcfb4 2178 (+) Stop the Time Encoder.
mbed_official 205:c41fc65bcfb4 2179 (+) Start the Time Encoder and enable interrupt.
mbed_official 205:c41fc65bcfb4 2180 (+) Stop the Time Encoder and disable interrupt.
mbed_official 205:c41fc65bcfb4 2181 (+) Start the Time Encoder and enable DMA transfer.
mbed_official 205:c41fc65bcfb4 2182 (+) Stop the Time Encoder and disable DMA transfer.
mbed_official 205:c41fc65bcfb4 2183
mbed_official 205:c41fc65bcfb4 2184 @endverbatim
mbed_official 205:c41fc65bcfb4 2185 * @{
mbed_official 205:c41fc65bcfb4 2186 */
mbed_official 205:c41fc65bcfb4 2187 /**
mbed_official 205:c41fc65bcfb4 2188 * @brief Initializes the TIM Encoder Interface and create the associated handle.
mbed_official 205:c41fc65bcfb4 2189 * @param htim: TIM Encoder Interface handle
mbed_official 205:c41fc65bcfb4 2190 * @param sConfig: TIM Encoder Interface configuration structure
mbed_official 205:c41fc65bcfb4 2191 * @retval HAL status
mbed_official 205:c41fc65bcfb4 2192 */
mbed_official 205:c41fc65bcfb4 2193 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
mbed_official 205:c41fc65bcfb4 2194 {
mbed_official 205:c41fc65bcfb4 2195 uint32_t tmpsmcr = 0;
mbed_official 205:c41fc65bcfb4 2196 uint32_t tmpccmr1 = 0;
mbed_official 205:c41fc65bcfb4 2197 uint32_t tmpccer = 0;
mbed_official 205:c41fc65bcfb4 2198
mbed_official 205:c41fc65bcfb4 2199 /* Check the TIM handle allocation */
mbed_official 205:c41fc65bcfb4 2200 if(htim == NULL)
mbed_official 205:c41fc65bcfb4 2201 {
mbed_official 205:c41fc65bcfb4 2202 return HAL_ERROR;
mbed_official 205:c41fc65bcfb4 2203 }
mbed_official 205:c41fc65bcfb4 2204
mbed_official 205:c41fc65bcfb4 2205 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 2206 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 2207 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
mbed_official 205:c41fc65bcfb4 2208 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
mbed_official 205:c41fc65bcfb4 2209 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
mbed_official 205:c41fc65bcfb4 2210 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
mbed_official 205:c41fc65bcfb4 2211 assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
mbed_official 205:c41fc65bcfb4 2212 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
mbed_official 205:c41fc65bcfb4 2213 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
mbed_official 205:c41fc65bcfb4 2214 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
mbed_official 205:c41fc65bcfb4 2215 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
mbed_official 205:c41fc65bcfb4 2216
mbed_official 205:c41fc65bcfb4 2217 if(htim->State == HAL_TIM_STATE_RESET)
mbed_official 205:c41fc65bcfb4 2218 {
mbed_official 205:c41fc65bcfb4 2219 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official 205:c41fc65bcfb4 2220 HAL_TIM_Encoder_MspInit(htim);
mbed_official 205:c41fc65bcfb4 2221 }
mbed_official 205:c41fc65bcfb4 2222
mbed_official 205:c41fc65bcfb4 2223 /* Set the TIM state */
mbed_official 205:c41fc65bcfb4 2224 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 205:c41fc65bcfb4 2225
mbed_official 205:c41fc65bcfb4 2226 /* Reset the SMS bits */
mbed_official 205:c41fc65bcfb4 2227 htim->Instance->SMCR &= (uint16_t)(~TIM_SMCR_SMS);
mbed_official 205:c41fc65bcfb4 2228
mbed_official 205:c41fc65bcfb4 2229 /* Configure the Time base in the Encoder Mode */
mbed_official 205:c41fc65bcfb4 2230 TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official 205:c41fc65bcfb4 2231
mbed_official 205:c41fc65bcfb4 2232 /* Get the TIMx SMCR register value */
mbed_official 205:c41fc65bcfb4 2233 tmpsmcr = htim->Instance->SMCR;
mbed_official 205:c41fc65bcfb4 2234
mbed_official 205:c41fc65bcfb4 2235 /* Get the TIMx CCMR1 register value */
mbed_official 205:c41fc65bcfb4 2236 tmpccmr1 = htim->Instance->CCMR1;
mbed_official 205:c41fc65bcfb4 2237
mbed_official 205:c41fc65bcfb4 2238 /* Get the TIMx CCER register value */
mbed_official 205:c41fc65bcfb4 2239 tmpccer = htim->Instance->CCER;
mbed_official 205:c41fc65bcfb4 2240
mbed_official 205:c41fc65bcfb4 2241 /* Set the encoder Mode */
mbed_official 205:c41fc65bcfb4 2242 tmpsmcr |= sConfig->EncoderMode;
mbed_official 205:c41fc65bcfb4 2243
mbed_official 205:c41fc65bcfb4 2244 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
mbed_official 205:c41fc65bcfb4 2245 tmpccmr1 &= (uint16_t)(~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S));
mbed_official 205:c41fc65bcfb4 2246 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
mbed_official 205:c41fc65bcfb4 2247
mbed_official 205:c41fc65bcfb4 2248 /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
mbed_official 205:c41fc65bcfb4 2249 tmpccmr1 &= (uint16_t)(~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC));
mbed_official 205:c41fc65bcfb4 2250 tmpccmr1 &= (uint16_t)(~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F));
mbed_official 205:c41fc65bcfb4 2251 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
mbed_official 205:c41fc65bcfb4 2252 tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
mbed_official 205:c41fc65bcfb4 2253
mbed_official 205:c41fc65bcfb4 2254 /* Set the TI1 and the TI2 Polarities */
mbed_official 205:c41fc65bcfb4 2255 tmpccer &= (uint16_t)(~(TIM_CCER_CC1P | TIM_CCER_CC2P));
mbed_official 205:c41fc65bcfb4 2256 tmpccer &= (uint16_t)(~(TIM_CCER_CC1NP | TIM_CCER_CC2NP));
mbed_official 205:c41fc65bcfb4 2257 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
mbed_official 205:c41fc65bcfb4 2258
mbed_official 205:c41fc65bcfb4 2259 /* Write to TIMx SMCR */
mbed_official 205:c41fc65bcfb4 2260 htim->Instance->SMCR = tmpsmcr;
mbed_official 205:c41fc65bcfb4 2261
mbed_official 205:c41fc65bcfb4 2262 /* Write to TIMx CCMR1 */
mbed_official 205:c41fc65bcfb4 2263 htim->Instance->CCMR1 = tmpccmr1;
mbed_official 205:c41fc65bcfb4 2264
mbed_official 205:c41fc65bcfb4 2265 /* Write to TIMx CCER */
mbed_official 205:c41fc65bcfb4 2266 htim->Instance->CCER = tmpccer;
mbed_official 205:c41fc65bcfb4 2267
mbed_official 205:c41fc65bcfb4 2268 /* Initialize the TIM state*/
mbed_official 205:c41fc65bcfb4 2269 htim->State= HAL_TIM_STATE_READY;
mbed_official 205:c41fc65bcfb4 2270
mbed_official 205:c41fc65bcfb4 2271 return HAL_OK;
mbed_official 205:c41fc65bcfb4 2272 }
mbed_official 205:c41fc65bcfb4 2273
mbed_official 205:c41fc65bcfb4 2274
mbed_official 205:c41fc65bcfb4 2275 /**
mbed_official 205:c41fc65bcfb4 2276 * @brief DeInitializes the TIM Encoder interface
mbed_official 205:c41fc65bcfb4 2277 * @param htim: TIM Encoder handle
mbed_official 205:c41fc65bcfb4 2278 * @retval HAL status
mbed_official 205:c41fc65bcfb4 2279 */
mbed_official 205:c41fc65bcfb4 2280 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 2281 {
mbed_official 205:c41fc65bcfb4 2282 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 2283 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 2284
mbed_official 205:c41fc65bcfb4 2285 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 205:c41fc65bcfb4 2286
mbed_official 205:c41fc65bcfb4 2287 /* Disable the TIM Peripheral Clock */
mbed_official 205:c41fc65bcfb4 2288 __HAL_TIM_DISABLE(htim);
mbed_official 205:c41fc65bcfb4 2289
mbed_official 205:c41fc65bcfb4 2290 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
mbed_official 205:c41fc65bcfb4 2291 HAL_TIM_Encoder_MspDeInit(htim);
mbed_official 205:c41fc65bcfb4 2292
mbed_official 205:c41fc65bcfb4 2293 /* Change TIM state */
mbed_official 205:c41fc65bcfb4 2294 htim->State = HAL_TIM_STATE_RESET;
mbed_official 205:c41fc65bcfb4 2295
mbed_official 205:c41fc65bcfb4 2296 /* Release Lock */
mbed_official 205:c41fc65bcfb4 2297 __HAL_UNLOCK(htim);
mbed_official 205:c41fc65bcfb4 2298
mbed_official 205:c41fc65bcfb4 2299 return HAL_OK;
mbed_official 205:c41fc65bcfb4 2300 }
mbed_official 205:c41fc65bcfb4 2301
mbed_official 205:c41fc65bcfb4 2302 /**
mbed_official 205:c41fc65bcfb4 2303 * @brief Initializes the TIM Encoder Interface MSP.
mbed_official 205:c41fc65bcfb4 2304 * @param htim: TIM handle
mbed_official 205:c41fc65bcfb4 2305 * @retval None
mbed_official 205:c41fc65bcfb4 2306 */
mbed_official 205:c41fc65bcfb4 2307 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 2308 {
mbed_official 205:c41fc65bcfb4 2309 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 205:c41fc65bcfb4 2310 the HAL_TIM_Encoder_MspInit could be implemented in the user file
mbed_official 205:c41fc65bcfb4 2311 */
mbed_official 205:c41fc65bcfb4 2312 }
mbed_official 205:c41fc65bcfb4 2313
mbed_official 205:c41fc65bcfb4 2314 /**
mbed_official 205:c41fc65bcfb4 2315 * @brief DeInitializes TIM Encoder Interface MSP.
mbed_official 205:c41fc65bcfb4 2316 * @param htim: TIM handle
mbed_official 205:c41fc65bcfb4 2317 * @retval None
mbed_official 205:c41fc65bcfb4 2318 */
mbed_official 205:c41fc65bcfb4 2319 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 2320 {
mbed_official 205:c41fc65bcfb4 2321 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 205:c41fc65bcfb4 2322 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
mbed_official 205:c41fc65bcfb4 2323 */
mbed_official 205:c41fc65bcfb4 2324 }
mbed_official 205:c41fc65bcfb4 2325
mbed_official 205:c41fc65bcfb4 2326 /**
mbed_official 205:c41fc65bcfb4 2327 * @brief Starts the TIM Encoder Interface.
mbed_official 205:c41fc65bcfb4 2328 * @param htim : TIM Encoder Interface handle
mbed_official 205:c41fc65bcfb4 2329 * @param Channel : TIM Channels to be enabled
mbed_official 205:c41fc65bcfb4 2330 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 2331 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 205:c41fc65bcfb4 2332 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 205:c41fc65bcfb4 2333 * @retval HAL status
mbed_official 205:c41fc65bcfb4 2334 */
mbed_official 205:c41fc65bcfb4 2335 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 205:c41fc65bcfb4 2336 {
mbed_official 205:c41fc65bcfb4 2337 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 2338 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 2339
mbed_official 205:c41fc65bcfb4 2340 /* Enable the encoder interface channels */
mbed_official 205:c41fc65bcfb4 2341 switch (Channel)
mbed_official 205:c41fc65bcfb4 2342 {
mbed_official 205:c41fc65bcfb4 2343 case TIM_CHANNEL_1:
mbed_official 205:c41fc65bcfb4 2344 {
mbed_official 205:c41fc65bcfb4 2345 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 205:c41fc65bcfb4 2346 break;
mbed_official 205:c41fc65bcfb4 2347 }
mbed_official 205:c41fc65bcfb4 2348 case TIM_CHANNEL_2:
mbed_official 205:c41fc65bcfb4 2349 {
mbed_official 205:c41fc65bcfb4 2350 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 205:c41fc65bcfb4 2351 break;
mbed_official 205:c41fc65bcfb4 2352 }
mbed_official 205:c41fc65bcfb4 2353 default :
mbed_official 205:c41fc65bcfb4 2354 {
mbed_official 205:c41fc65bcfb4 2355 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 205:c41fc65bcfb4 2356 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 205:c41fc65bcfb4 2357 break;
mbed_official 205:c41fc65bcfb4 2358 }
mbed_official 205:c41fc65bcfb4 2359 }
mbed_official 205:c41fc65bcfb4 2360 /* Enable the Peripheral */
mbed_official 205:c41fc65bcfb4 2361 __HAL_TIM_ENABLE(htim);
mbed_official 205:c41fc65bcfb4 2362
mbed_official 205:c41fc65bcfb4 2363 /* Return function status */
mbed_official 205:c41fc65bcfb4 2364 return HAL_OK;
mbed_official 205:c41fc65bcfb4 2365 }
mbed_official 205:c41fc65bcfb4 2366
mbed_official 205:c41fc65bcfb4 2367 /**
mbed_official 205:c41fc65bcfb4 2368 * @brief Stops the TIM Encoder Interface.
mbed_official 205:c41fc65bcfb4 2369 * @param htim : TIM Encoder Interface handle
mbed_official 205:c41fc65bcfb4 2370 * @param Channel : TIM Channels to be disabled
mbed_official 205:c41fc65bcfb4 2371 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 2372 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 205:c41fc65bcfb4 2373 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 205:c41fc65bcfb4 2374 * @retval HAL status
mbed_official 205:c41fc65bcfb4 2375 */
mbed_official 205:c41fc65bcfb4 2376 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 205:c41fc65bcfb4 2377 {
mbed_official 205:c41fc65bcfb4 2378 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 2379 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 2380
mbed_official 205:c41fc65bcfb4 2381 /* Disable the Input Capture channels 1 and 2
mbed_official 205:c41fc65bcfb4 2382 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
mbed_official 205:c41fc65bcfb4 2383 switch (Channel)
mbed_official 205:c41fc65bcfb4 2384 {
mbed_official 205:c41fc65bcfb4 2385 case TIM_CHANNEL_1:
mbed_official 205:c41fc65bcfb4 2386 {
mbed_official 205:c41fc65bcfb4 2387 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 205:c41fc65bcfb4 2388 break;
mbed_official 205:c41fc65bcfb4 2389 }
mbed_official 205:c41fc65bcfb4 2390 case TIM_CHANNEL_2:
mbed_official 205:c41fc65bcfb4 2391 {
mbed_official 205:c41fc65bcfb4 2392 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 205:c41fc65bcfb4 2393 break;
mbed_official 205:c41fc65bcfb4 2394 }
mbed_official 205:c41fc65bcfb4 2395 default :
mbed_official 205:c41fc65bcfb4 2396 {
mbed_official 205:c41fc65bcfb4 2397 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 205:c41fc65bcfb4 2398 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 205:c41fc65bcfb4 2399 break;
mbed_official 205:c41fc65bcfb4 2400 }
mbed_official 205:c41fc65bcfb4 2401 }
mbed_official 205:c41fc65bcfb4 2402
mbed_official 205:c41fc65bcfb4 2403 /* Disable the Peripheral */
mbed_official 205:c41fc65bcfb4 2404 __HAL_TIM_DISABLE(htim);
mbed_official 205:c41fc65bcfb4 2405
mbed_official 205:c41fc65bcfb4 2406 /* Return function status */
mbed_official 205:c41fc65bcfb4 2407 return HAL_OK;
mbed_official 205:c41fc65bcfb4 2408 }
mbed_official 205:c41fc65bcfb4 2409
mbed_official 205:c41fc65bcfb4 2410 /**
mbed_official 205:c41fc65bcfb4 2411 * @brief Starts the TIM Encoder Interface in interrupt mode.
mbed_official 205:c41fc65bcfb4 2412 * @param htim : TIM Encoder Interface handle
mbed_official 205:c41fc65bcfb4 2413 * @param Channel : TIM Channels to be enabled
mbed_official 205:c41fc65bcfb4 2414 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 2415 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 205:c41fc65bcfb4 2416 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 205:c41fc65bcfb4 2417 * @retval HAL status
mbed_official 205:c41fc65bcfb4 2418 */
mbed_official 205:c41fc65bcfb4 2419 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 205:c41fc65bcfb4 2420 {
mbed_official 205:c41fc65bcfb4 2421 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 2422 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 2423
mbed_official 205:c41fc65bcfb4 2424 /* Enable the encoder interface channels */
mbed_official 205:c41fc65bcfb4 2425 /* Enable the capture compare Interrupts 1 and/or 2 */
mbed_official 205:c41fc65bcfb4 2426 switch (Channel)
mbed_official 205:c41fc65bcfb4 2427 {
mbed_official 205:c41fc65bcfb4 2428 case TIM_CHANNEL_1:
mbed_official 205:c41fc65bcfb4 2429 {
mbed_official 205:c41fc65bcfb4 2430 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 205:c41fc65bcfb4 2431 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official 205:c41fc65bcfb4 2432 break;
mbed_official 205:c41fc65bcfb4 2433 }
mbed_official 205:c41fc65bcfb4 2434 case TIM_CHANNEL_2:
mbed_official 205:c41fc65bcfb4 2435 {
mbed_official 205:c41fc65bcfb4 2436 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 205:c41fc65bcfb4 2437 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official 205:c41fc65bcfb4 2438 break;
mbed_official 205:c41fc65bcfb4 2439 }
mbed_official 205:c41fc65bcfb4 2440 default :
mbed_official 205:c41fc65bcfb4 2441 {
mbed_official 205:c41fc65bcfb4 2442 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 205:c41fc65bcfb4 2443 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 205:c41fc65bcfb4 2444 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official 205:c41fc65bcfb4 2445 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official 205:c41fc65bcfb4 2446 break;
mbed_official 205:c41fc65bcfb4 2447 }
mbed_official 205:c41fc65bcfb4 2448 }
mbed_official 205:c41fc65bcfb4 2449
mbed_official 205:c41fc65bcfb4 2450 /* Enable the Peripheral */
mbed_official 205:c41fc65bcfb4 2451 __HAL_TIM_ENABLE(htim);
mbed_official 205:c41fc65bcfb4 2452
mbed_official 205:c41fc65bcfb4 2453 /* Return function status */
mbed_official 205:c41fc65bcfb4 2454 return HAL_OK;
mbed_official 205:c41fc65bcfb4 2455 }
mbed_official 205:c41fc65bcfb4 2456
mbed_official 205:c41fc65bcfb4 2457 /**
mbed_official 205:c41fc65bcfb4 2458 * @brief Stops the TIM Encoder Interface in interrupt mode.
mbed_official 205:c41fc65bcfb4 2459 * @param htim : TIM Encoder Interface handle
mbed_official 205:c41fc65bcfb4 2460 * @param Channel : TIM Channels to be disabled
mbed_official 205:c41fc65bcfb4 2461 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 2462 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 205:c41fc65bcfb4 2463 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 205:c41fc65bcfb4 2464 * @retval HAL status
mbed_official 205:c41fc65bcfb4 2465 */
mbed_official 205:c41fc65bcfb4 2466 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 205:c41fc65bcfb4 2467 {
mbed_official 205:c41fc65bcfb4 2468 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 2469 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 2470
mbed_official 205:c41fc65bcfb4 2471 /* Disable the Input Capture channels 1 and 2
mbed_official 205:c41fc65bcfb4 2472 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
mbed_official 205:c41fc65bcfb4 2473 if(Channel == TIM_CHANNEL_1)
mbed_official 205:c41fc65bcfb4 2474 {
mbed_official 205:c41fc65bcfb4 2475 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 205:c41fc65bcfb4 2476
mbed_official 205:c41fc65bcfb4 2477 /* Disable the capture compare Interrupts 1 */
mbed_official 205:c41fc65bcfb4 2478 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official 205:c41fc65bcfb4 2479 }
mbed_official 205:c41fc65bcfb4 2480 else if(Channel == TIM_CHANNEL_2)
mbed_official 205:c41fc65bcfb4 2481 {
mbed_official 205:c41fc65bcfb4 2482 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 205:c41fc65bcfb4 2483
mbed_official 205:c41fc65bcfb4 2484 /* Disable the capture compare Interrupts 2 */
mbed_official 205:c41fc65bcfb4 2485 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official 205:c41fc65bcfb4 2486 }
mbed_official 205:c41fc65bcfb4 2487 else
mbed_official 205:c41fc65bcfb4 2488 {
mbed_official 205:c41fc65bcfb4 2489 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 205:c41fc65bcfb4 2490 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 205:c41fc65bcfb4 2491
mbed_official 205:c41fc65bcfb4 2492 /* Disable the capture compare Interrupts 1 and 2 */
mbed_official 205:c41fc65bcfb4 2493 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official 205:c41fc65bcfb4 2494 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official 205:c41fc65bcfb4 2495 }
mbed_official 205:c41fc65bcfb4 2496
mbed_official 205:c41fc65bcfb4 2497 /* Disable the Peripheral */
mbed_official 205:c41fc65bcfb4 2498 __HAL_TIM_DISABLE(htim);
mbed_official 205:c41fc65bcfb4 2499
mbed_official 205:c41fc65bcfb4 2500 /* Change the htim state */
mbed_official 205:c41fc65bcfb4 2501 htim->State = HAL_TIM_STATE_READY;
mbed_official 205:c41fc65bcfb4 2502
mbed_official 205:c41fc65bcfb4 2503 /* Return function status */
mbed_official 205:c41fc65bcfb4 2504 return HAL_OK;
mbed_official 205:c41fc65bcfb4 2505 }
mbed_official 205:c41fc65bcfb4 2506
mbed_official 205:c41fc65bcfb4 2507 /**
mbed_official 205:c41fc65bcfb4 2508 * @brief Starts the TIM Encoder Interface in DMA mode.
mbed_official 205:c41fc65bcfb4 2509 * @param htim : TIM Encoder Interface handle
mbed_official 205:c41fc65bcfb4 2510 * @param Channel : TIM Channels to be enabled
mbed_official 205:c41fc65bcfb4 2511 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 2512 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 205:c41fc65bcfb4 2513 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 205:c41fc65bcfb4 2514 * @param pData1: The destination Buffer address for IC1.
mbed_official 205:c41fc65bcfb4 2515 * @param pData2: The destination Buffer address for IC2.
mbed_official 205:c41fc65bcfb4 2516 * @param Length: The length of data to be transferred from TIM peripheral to memory.
mbed_official 205:c41fc65bcfb4 2517 * @retval HAL status
mbed_official 205:c41fc65bcfb4 2518 */
mbed_official 205:c41fc65bcfb4 2519 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
mbed_official 205:c41fc65bcfb4 2520 {
mbed_official 205:c41fc65bcfb4 2521 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 2522 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 2523
mbed_official 205:c41fc65bcfb4 2524 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 205:c41fc65bcfb4 2525 {
mbed_official 205:c41fc65bcfb4 2526 return HAL_BUSY;
mbed_official 205:c41fc65bcfb4 2527 }
mbed_official 205:c41fc65bcfb4 2528 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 205:c41fc65bcfb4 2529 {
mbed_official 205:c41fc65bcfb4 2530 if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
mbed_official 205:c41fc65bcfb4 2531 {
mbed_official 205:c41fc65bcfb4 2532 return HAL_ERROR;
mbed_official 205:c41fc65bcfb4 2533 }
mbed_official 205:c41fc65bcfb4 2534 else
mbed_official 205:c41fc65bcfb4 2535 {
mbed_official 205:c41fc65bcfb4 2536 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 205:c41fc65bcfb4 2537 }
mbed_official 205:c41fc65bcfb4 2538 }
mbed_official 205:c41fc65bcfb4 2539
mbed_official 205:c41fc65bcfb4 2540 switch (Channel)
mbed_official 205:c41fc65bcfb4 2541 {
mbed_official 205:c41fc65bcfb4 2542 case TIM_CHANNEL_1:
mbed_official 205:c41fc65bcfb4 2543 {
mbed_official 205:c41fc65bcfb4 2544 /* Set the DMA Period elapsed callback */
mbed_official 205:c41fc65bcfb4 2545 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official 205:c41fc65bcfb4 2546
mbed_official 205:c41fc65bcfb4 2547 /* Set the DMA error callback */
mbed_official 205:c41fc65bcfb4 2548 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 205:c41fc65bcfb4 2549
mbed_official 205:c41fc65bcfb4 2550 /* Enable the DMA channel */
mbed_official 205:c41fc65bcfb4 2551 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
mbed_official 205:c41fc65bcfb4 2552
mbed_official 205:c41fc65bcfb4 2553 /* Enable the TIM Input Capture DMA request */
mbed_official 205:c41fc65bcfb4 2554 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 205:c41fc65bcfb4 2555
mbed_official 205:c41fc65bcfb4 2556 /* Enable the Peripheral */
mbed_official 205:c41fc65bcfb4 2557 __HAL_TIM_ENABLE(htim);
mbed_official 205:c41fc65bcfb4 2558
mbed_official 205:c41fc65bcfb4 2559 /* Enable the Capture compare channel */
mbed_official 205:c41fc65bcfb4 2560 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 205:c41fc65bcfb4 2561 }
mbed_official 205:c41fc65bcfb4 2562 break;
mbed_official 205:c41fc65bcfb4 2563
mbed_official 205:c41fc65bcfb4 2564 case TIM_CHANNEL_2:
mbed_official 205:c41fc65bcfb4 2565 {
mbed_official 205:c41fc65bcfb4 2566 /* Set the DMA Period elapsed callback */
mbed_official 205:c41fc65bcfb4 2567 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official 205:c41fc65bcfb4 2568
mbed_official 205:c41fc65bcfb4 2569 /* Set the DMA error callback */
mbed_official 205:c41fc65bcfb4 2570 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError;
mbed_official 205:c41fc65bcfb4 2571 /* Enable the DMA channel */
mbed_official 205:c41fc65bcfb4 2572 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
mbed_official 205:c41fc65bcfb4 2573
mbed_official 205:c41fc65bcfb4 2574 /* Enable the TIM Input Capture DMA request */
mbed_official 205:c41fc65bcfb4 2575 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 205:c41fc65bcfb4 2576
mbed_official 205:c41fc65bcfb4 2577 /* Enable the Peripheral */
mbed_official 205:c41fc65bcfb4 2578 __HAL_TIM_ENABLE(htim);
mbed_official 205:c41fc65bcfb4 2579
mbed_official 205:c41fc65bcfb4 2580 /* Enable the Capture compare channel */
mbed_official 205:c41fc65bcfb4 2581 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 205:c41fc65bcfb4 2582 }
mbed_official 205:c41fc65bcfb4 2583 break;
mbed_official 205:c41fc65bcfb4 2584
mbed_official 205:c41fc65bcfb4 2585 case TIM_CHANNEL_ALL:
mbed_official 205:c41fc65bcfb4 2586 {
mbed_official 205:c41fc65bcfb4 2587 /* Set the DMA Period elapsed callback */
mbed_official 205:c41fc65bcfb4 2588 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official 205:c41fc65bcfb4 2589
mbed_official 205:c41fc65bcfb4 2590 /* Set the DMA error callback */
mbed_official 205:c41fc65bcfb4 2591 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 205:c41fc65bcfb4 2592
mbed_official 205:c41fc65bcfb4 2593 /* Enable the DMA channel */
mbed_official 205:c41fc65bcfb4 2594 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
mbed_official 205:c41fc65bcfb4 2595
mbed_official 205:c41fc65bcfb4 2596 /* Set the DMA Period elapsed callback */
mbed_official 205:c41fc65bcfb4 2597 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official 205:c41fc65bcfb4 2598
mbed_official 205:c41fc65bcfb4 2599 /* Set the DMA error callback */
mbed_official 205:c41fc65bcfb4 2600 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 205:c41fc65bcfb4 2601
mbed_official 205:c41fc65bcfb4 2602 /* Enable the DMA channel */
mbed_official 205:c41fc65bcfb4 2603 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
mbed_official 205:c41fc65bcfb4 2604
mbed_official 205:c41fc65bcfb4 2605 /* Enable the Peripheral */
mbed_official 205:c41fc65bcfb4 2606 __HAL_TIM_ENABLE(htim);
mbed_official 205:c41fc65bcfb4 2607
mbed_official 205:c41fc65bcfb4 2608 /* Enable the Capture compare channel */
mbed_official 205:c41fc65bcfb4 2609 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 205:c41fc65bcfb4 2610 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 205:c41fc65bcfb4 2611
mbed_official 205:c41fc65bcfb4 2612 /* Enable the TIM Input Capture DMA request */
mbed_official 205:c41fc65bcfb4 2613 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 205:c41fc65bcfb4 2614 /* Enable the TIM Input Capture DMA request */
mbed_official 205:c41fc65bcfb4 2615 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 205:c41fc65bcfb4 2616 }
mbed_official 205:c41fc65bcfb4 2617 break;
mbed_official 205:c41fc65bcfb4 2618
mbed_official 205:c41fc65bcfb4 2619 default:
mbed_official 205:c41fc65bcfb4 2620 break;
mbed_official 205:c41fc65bcfb4 2621 }
mbed_official 205:c41fc65bcfb4 2622 /* Return function status */
mbed_official 205:c41fc65bcfb4 2623 return HAL_OK;
mbed_official 205:c41fc65bcfb4 2624 }
mbed_official 205:c41fc65bcfb4 2625
mbed_official 205:c41fc65bcfb4 2626 /**
mbed_official 205:c41fc65bcfb4 2627 * @brief Stops the TIM Encoder Interface in DMA mode.
mbed_official 205:c41fc65bcfb4 2628 * @param htim : TIM Encoder Interface handle
mbed_official 205:c41fc65bcfb4 2629 * @param Channel : TIM Channels to be enabled
mbed_official 205:c41fc65bcfb4 2630 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 2631 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 205:c41fc65bcfb4 2632 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 205:c41fc65bcfb4 2633 * @retval HAL status
mbed_official 205:c41fc65bcfb4 2634 */
mbed_official 205:c41fc65bcfb4 2635 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 205:c41fc65bcfb4 2636 {
mbed_official 205:c41fc65bcfb4 2637 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 2638 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 2639
mbed_official 205:c41fc65bcfb4 2640 /* Disable the Input Capture channels 1 and 2
mbed_official 205:c41fc65bcfb4 2641 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
mbed_official 205:c41fc65bcfb4 2642 if(Channel == TIM_CHANNEL_1)
mbed_official 205:c41fc65bcfb4 2643 {
mbed_official 205:c41fc65bcfb4 2644 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 205:c41fc65bcfb4 2645
mbed_official 205:c41fc65bcfb4 2646 /* Disable the capture compare DMA Request 1 */
mbed_official 205:c41fc65bcfb4 2647 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 205:c41fc65bcfb4 2648 }
mbed_official 205:c41fc65bcfb4 2649 else if(Channel == TIM_CHANNEL_2)
mbed_official 205:c41fc65bcfb4 2650 {
mbed_official 205:c41fc65bcfb4 2651 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 205:c41fc65bcfb4 2652
mbed_official 205:c41fc65bcfb4 2653 /* Disable the capture compare DMA Request 2 */
mbed_official 205:c41fc65bcfb4 2654 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 205:c41fc65bcfb4 2655 }
mbed_official 205:c41fc65bcfb4 2656 else
mbed_official 205:c41fc65bcfb4 2657 {
mbed_official 205:c41fc65bcfb4 2658 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 205:c41fc65bcfb4 2659 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 205:c41fc65bcfb4 2660
mbed_official 205:c41fc65bcfb4 2661 /* Disable the capture compare DMA Request 1 and 2 */
mbed_official 205:c41fc65bcfb4 2662 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 205:c41fc65bcfb4 2663 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 205:c41fc65bcfb4 2664 }
mbed_official 205:c41fc65bcfb4 2665
mbed_official 205:c41fc65bcfb4 2666 /* Disable the Peripheral */
mbed_official 205:c41fc65bcfb4 2667 __HAL_TIM_DISABLE(htim);
mbed_official 205:c41fc65bcfb4 2668
mbed_official 205:c41fc65bcfb4 2669 /* Change the htim state */
mbed_official 205:c41fc65bcfb4 2670 htim->State = HAL_TIM_STATE_READY;
mbed_official 205:c41fc65bcfb4 2671
mbed_official 205:c41fc65bcfb4 2672 /* Return function status */
mbed_official 205:c41fc65bcfb4 2673 return HAL_OK;
mbed_official 205:c41fc65bcfb4 2674 }
mbed_official 205:c41fc65bcfb4 2675
mbed_official 205:c41fc65bcfb4 2676 /**
mbed_official 205:c41fc65bcfb4 2677 * @}
mbed_official 205:c41fc65bcfb4 2678 */
mbed_official 205:c41fc65bcfb4 2679 /** @defgroup TIM_Group7 TIM IRQ handler management
mbed_official 205:c41fc65bcfb4 2680 * @brief IRQ handler management
mbed_official 205:c41fc65bcfb4 2681 *
mbed_official 205:c41fc65bcfb4 2682 @verbatim
mbed_official 205:c41fc65bcfb4 2683 ==============================================================================
mbed_official 205:c41fc65bcfb4 2684 ##### IRQ handler management #####
mbed_official 205:c41fc65bcfb4 2685 ==============================================================================
mbed_official 205:c41fc65bcfb4 2686 [..]
mbed_official 205:c41fc65bcfb4 2687 This section provides Timer IRQ handler function.
mbed_official 205:c41fc65bcfb4 2688
mbed_official 205:c41fc65bcfb4 2689 @endverbatim
mbed_official 205:c41fc65bcfb4 2690 * @{
mbed_official 205:c41fc65bcfb4 2691 */
mbed_official 205:c41fc65bcfb4 2692 /**
mbed_official 205:c41fc65bcfb4 2693 * @brief This function handles TIM interrupts requests.
mbed_official 205:c41fc65bcfb4 2694 * @param htim: TIM handle
mbed_official 205:c41fc65bcfb4 2695 * @retval None
mbed_official 205:c41fc65bcfb4 2696 */
mbed_official 205:c41fc65bcfb4 2697 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 2698 {
mbed_official 205:c41fc65bcfb4 2699 /* Capture compare 1 event */
mbed_official 205:c41fc65bcfb4 2700 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
mbed_official 205:c41fc65bcfb4 2701 {
mbed_official 205:c41fc65bcfb4 2702 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC1) !=RESET)
mbed_official 205:c41fc65bcfb4 2703 {
mbed_official 205:c41fc65bcfb4 2704 {
mbed_official 205:c41fc65bcfb4 2705 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
mbed_official 205:c41fc65bcfb4 2706 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
mbed_official 205:c41fc65bcfb4 2707
mbed_official 205:c41fc65bcfb4 2708 /* Input capture event */
mbed_official 205:c41fc65bcfb4 2709 if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
mbed_official 205:c41fc65bcfb4 2710 {
mbed_official 205:c41fc65bcfb4 2711 HAL_TIM_IC_CaptureCallback(htim);
mbed_official 205:c41fc65bcfb4 2712 }
mbed_official 205:c41fc65bcfb4 2713 /* Output compare event */
mbed_official 205:c41fc65bcfb4 2714 else
mbed_official 205:c41fc65bcfb4 2715 {
mbed_official 205:c41fc65bcfb4 2716 HAL_TIM_OC_DelayElapsedCallback(htim);
mbed_official 205:c41fc65bcfb4 2717 HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official 205:c41fc65bcfb4 2718 }
mbed_official 205:c41fc65bcfb4 2719 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official 205:c41fc65bcfb4 2720 }
mbed_official 205:c41fc65bcfb4 2721 }
mbed_official 205:c41fc65bcfb4 2722 }
mbed_official 205:c41fc65bcfb4 2723 /* Capture compare 2 event */
mbed_official 205:c41fc65bcfb4 2724 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
mbed_official 205:c41fc65bcfb4 2725 {
mbed_official 205:c41fc65bcfb4 2726 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC2) !=RESET)
mbed_official 205:c41fc65bcfb4 2727 {
mbed_official 205:c41fc65bcfb4 2728 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
mbed_official 205:c41fc65bcfb4 2729 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
mbed_official 205:c41fc65bcfb4 2730 /* Input capture event */
mbed_official 205:c41fc65bcfb4 2731 if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
mbed_official 205:c41fc65bcfb4 2732 {
mbed_official 205:c41fc65bcfb4 2733 HAL_TIM_IC_CaptureCallback(htim);
mbed_official 205:c41fc65bcfb4 2734 }
mbed_official 205:c41fc65bcfb4 2735 /* Output compare event */
mbed_official 205:c41fc65bcfb4 2736 else
mbed_official 205:c41fc65bcfb4 2737 {
mbed_official 205:c41fc65bcfb4 2738 HAL_TIM_OC_DelayElapsedCallback(htim);
mbed_official 205:c41fc65bcfb4 2739 HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official 205:c41fc65bcfb4 2740 }
mbed_official 205:c41fc65bcfb4 2741 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official 205:c41fc65bcfb4 2742 }
mbed_official 205:c41fc65bcfb4 2743 }
mbed_official 205:c41fc65bcfb4 2744 /* Capture compare 3 event */
mbed_official 205:c41fc65bcfb4 2745 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
mbed_official 205:c41fc65bcfb4 2746 {
mbed_official 205:c41fc65bcfb4 2747 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC3) !=RESET)
mbed_official 205:c41fc65bcfb4 2748 {
mbed_official 205:c41fc65bcfb4 2749 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
mbed_official 205:c41fc65bcfb4 2750 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
mbed_official 205:c41fc65bcfb4 2751 /* Input capture event */
mbed_official 205:c41fc65bcfb4 2752 if((htim->Instance->CCMR1 & TIM_CCMR2_CC3S) != 0x00)
mbed_official 205:c41fc65bcfb4 2753 {
mbed_official 205:c41fc65bcfb4 2754 HAL_TIM_IC_CaptureCallback(htim);
mbed_official 205:c41fc65bcfb4 2755 }
mbed_official 205:c41fc65bcfb4 2756 /* Output compare event */
mbed_official 205:c41fc65bcfb4 2757 else
mbed_official 205:c41fc65bcfb4 2758 {
mbed_official 205:c41fc65bcfb4 2759 HAL_TIM_OC_DelayElapsedCallback(htim);
mbed_official 205:c41fc65bcfb4 2760 HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official 205:c41fc65bcfb4 2761 }
mbed_official 205:c41fc65bcfb4 2762 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official 205:c41fc65bcfb4 2763 }
mbed_official 205:c41fc65bcfb4 2764 }
mbed_official 205:c41fc65bcfb4 2765 /* Capture compare 4 event */
mbed_official 205:c41fc65bcfb4 2766 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
mbed_official 205:c41fc65bcfb4 2767 {
mbed_official 205:c41fc65bcfb4 2768 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC4) !=RESET)
mbed_official 205:c41fc65bcfb4 2769 {
mbed_official 205:c41fc65bcfb4 2770 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
mbed_official 205:c41fc65bcfb4 2771 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
mbed_official 205:c41fc65bcfb4 2772 /* Input capture event */
mbed_official 205:c41fc65bcfb4 2773 if((htim->Instance->CCMR1 & TIM_CCMR2_CC4S) != 0x00)
mbed_official 205:c41fc65bcfb4 2774 {
mbed_official 205:c41fc65bcfb4 2775 HAL_TIM_IC_CaptureCallback(htim);
mbed_official 205:c41fc65bcfb4 2776 }
mbed_official 205:c41fc65bcfb4 2777 /* Output compare event */
mbed_official 205:c41fc65bcfb4 2778 else
mbed_official 205:c41fc65bcfb4 2779 {
mbed_official 205:c41fc65bcfb4 2780 HAL_TIM_OC_DelayElapsedCallback(htim);
mbed_official 205:c41fc65bcfb4 2781 HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official 205:c41fc65bcfb4 2782 }
mbed_official 205:c41fc65bcfb4 2783 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official 205:c41fc65bcfb4 2784 }
mbed_official 205:c41fc65bcfb4 2785 }
mbed_official 205:c41fc65bcfb4 2786 /* TIM Update event */
mbed_official 205:c41fc65bcfb4 2787 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
mbed_official 205:c41fc65bcfb4 2788 {
mbed_official 205:c41fc65bcfb4 2789 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_UPDATE) !=RESET)
mbed_official 205:c41fc65bcfb4 2790 {
mbed_official 205:c41fc65bcfb4 2791 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
mbed_official 205:c41fc65bcfb4 2792 HAL_TIM_PeriodElapsedCallback(htim);
mbed_official 205:c41fc65bcfb4 2793 }
mbed_official 205:c41fc65bcfb4 2794 }
mbed_official 205:c41fc65bcfb4 2795 /* TIM Break input event */
mbed_official 205:c41fc65bcfb4 2796 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
mbed_official 205:c41fc65bcfb4 2797 {
mbed_official 205:c41fc65bcfb4 2798 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_BREAK) !=RESET)
mbed_official 205:c41fc65bcfb4 2799 {
mbed_official 205:c41fc65bcfb4 2800 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
mbed_official 205:c41fc65bcfb4 2801 HAL_TIMEx_BreakCallback(htim);
mbed_official 205:c41fc65bcfb4 2802 }
mbed_official 205:c41fc65bcfb4 2803 }
mbed_official 205:c41fc65bcfb4 2804 /* TIM Trigger detection event */
mbed_official 205:c41fc65bcfb4 2805 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
mbed_official 205:c41fc65bcfb4 2806 {
mbed_official 205:c41fc65bcfb4 2807 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_TRIGGER) !=RESET)
mbed_official 205:c41fc65bcfb4 2808 {
mbed_official 205:c41fc65bcfb4 2809 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
mbed_official 205:c41fc65bcfb4 2810 HAL_TIM_TriggerCallback(htim);
mbed_official 205:c41fc65bcfb4 2811 }
mbed_official 205:c41fc65bcfb4 2812 }
mbed_official 205:c41fc65bcfb4 2813 /* TIM commutation event */
mbed_official 205:c41fc65bcfb4 2814 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
mbed_official 205:c41fc65bcfb4 2815 {
mbed_official 205:c41fc65bcfb4 2816 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_COM) !=RESET)
mbed_official 205:c41fc65bcfb4 2817 {
mbed_official 205:c41fc65bcfb4 2818 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
mbed_official 205:c41fc65bcfb4 2819 HAL_TIMEx_CommutationCallback(htim);
mbed_official 205:c41fc65bcfb4 2820 }
mbed_official 205:c41fc65bcfb4 2821 }
mbed_official 205:c41fc65bcfb4 2822 }
mbed_official 205:c41fc65bcfb4 2823
mbed_official 205:c41fc65bcfb4 2824 /**
mbed_official 205:c41fc65bcfb4 2825 * @}
mbed_official 205:c41fc65bcfb4 2826 */
mbed_official 205:c41fc65bcfb4 2827
mbed_official 205:c41fc65bcfb4 2828 /** @defgroup TIM_Group8 Peripheral Control functions
mbed_official 205:c41fc65bcfb4 2829 * @brief Peripheral Control functions
mbed_official 205:c41fc65bcfb4 2830 *
mbed_official 205:c41fc65bcfb4 2831 @verbatim
mbed_official 205:c41fc65bcfb4 2832 ==============================================================================
mbed_official 205:c41fc65bcfb4 2833 ##### Peripheral Control functions #####
mbed_official 205:c41fc65bcfb4 2834 ==============================================================================
mbed_official 205:c41fc65bcfb4 2835 [..]
mbed_official 205:c41fc65bcfb4 2836 This section provides functions allowing to:
mbed_official 205:c41fc65bcfb4 2837 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
mbed_official 205:c41fc65bcfb4 2838 (+) Configure External Clock source.
mbed_official 205:c41fc65bcfb4 2839 (+) Configure Complementary channels, break features and dead time.
mbed_official 205:c41fc65bcfb4 2840 (+) Configure Master and the Slave synchronization.
mbed_official 205:c41fc65bcfb4 2841 (+) Configure the DMA Burst Mode.
mbed_official 205:c41fc65bcfb4 2842
mbed_official 205:c41fc65bcfb4 2843 @endverbatim
mbed_official 205:c41fc65bcfb4 2844 * @{
mbed_official 205:c41fc65bcfb4 2845 */
mbed_official 205:c41fc65bcfb4 2846
mbed_official 205:c41fc65bcfb4 2847 /**
mbed_official 205:c41fc65bcfb4 2848 * @brief Initializes the TIM Output Compare Channels according to the specified
mbed_official 205:c41fc65bcfb4 2849 * parameters in the TIM_OC_InitTypeDef.
mbed_official 205:c41fc65bcfb4 2850 * @param htim: TIM Output Compare handle
mbed_official 205:c41fc65bcfb4 2851 * @param sConfig: TIM Output Compare configuration structure
mbed_official 205:c41fc65bcfb4 2852 * @param Channel : TIM Channels to be enabled
mbed_official 205:c41fc65bcfb4 2853 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 2854 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 205:c41fc65bcfb4 2855 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 205:c41fc65bcfb4 2856 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 205:c41fc65bcfb4 2857 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 205:c41fc65bcfb4 2858 * @retval HAL status
mbed_official 205:c41fc65bcfb4 2859 */
mbed_official 205:c41fc65bcfb4 2860 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
mbed_official 205:c41fc65bcfb4 2861 {
mbed_official 205:c41fc65bcfb4 2862 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 2863 assert_param(IS_TIM_CHANNELS(Channel));
mbed_official 205:c41fc65bcfb4 2864 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
mbed_official 205:c41fc65bcfb4 2865 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
mbed_official 205:c41fc65bcfb4 2866 assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
mbed_official 205:c41fc65bcfb4 2867 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
mbed_official 205:c41fc65bcfb4 2868 assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
mbed_official 205:c41fc65bcfb4 2869 assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
mbed_official 205:c41fc65bcfb4 2870
mbed_official 205:c41fc65bcfb4 2871 /* Check input state */
mbed_official 205:c41fc65bcfb4 2872 __HAL_LOCK(htim);
mbed_official 205:c41fc65bcfb4 2873
mbed_official 205:c41fc65bcfb4 2874 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 205:c41fc65bcfb4 2875
mbed_official 205:c41fc65bcfb4 2876 switch (Channel)
mbed_official 205:c41fc65bcfb4 2877 {
mbed_official 205:c41fc65bcfb4 2878 case TIM_CHANNEL_1:
mbed_official 205:c41fc65bcfb4 2879 {
mbed_official 205:c41fc65bcfb4 2880 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 2881 /* Configure the TIM Channel 1 in Output Compare */
mbed_official 205:c41fc65bcfb4 2882 TIM_OC1_SetConfig(htim->Instance, sConfig);
mbed_official 205:c41fc65bcfb4 2883 }
mbed_official 205:c41fc65bcfb4 2884 break;
mbed_official 205:c41fc65bcfb4 2885
mbed_official 205:c41fc65bcfb4 2886 case TIM_CHANNEL_2:
mbed_official 205:c41fc65bcfb4 2887 {
mbed_official 205:c41fc65bcfb4 2888 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 2889 /* Configure the TIM Channel 2 in Output Compare */
mbed_official 205:c41fc65bcfb4 2890 TIM_OC2_SetConfig(htim->Instance, sConfig);
mbed_official 205:c41fc65bcfb4 2891 }
mbed_official 205:c41fc65bcfb4 2892 break;
mbed_official 205:c41fc65bcfb4 2893
mbed_official 205:c41fc65bcfb4 2894 case TIM_CHANNEL_3:
mbed_official 205:c41fc65bcfb4 2895 {
mbed_official 205:c41fc65bcfb4 2896 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 2897 /* Configure the TIM Channel 3 in Output Compare */
mbed_official 205:c41fc65bcfb4 2898 TIM_OC3_SetConfig(htim->Instance, sConfig);
mbed_official 205:c41fc65bcfb4 2899 }
mbed_official 205:c41fc65bcfb4 2900 break;
mbed_official 205:c41fc65bcfb4 2901
mbed_official 205:c41fc65bcfb4 2902 case TIM_CHANNEL_4:
mbed_official 205:c41fc65bcfb4 2903 {
mbed_official 205:c41fc65bcfb4 2904 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 2905 /* Configure the TIM Channel 4 in Output Compare */
mbed_official 205:c41fc65bcfb4 2906 TIM_OC4_SetConfig(htim->Instance, sConfig);
mbed_official 205:c41fc65bcfb4 2907 }
mbed_official 205:c41fc65bcfb4 2908 break;
mbed_official 205:c41fc65bcfb4 2909
mbed_official 205:c41fc65bcfb4 2910 default:
mbed_official 205:c41fc65bcfb4 2911 break;
mbed_official 205:c41fc65bcfb4 2912 }
mbed_official 205:c41fc65bcfb4 2913 htim->State = HAL_TIM_STATE_READY;
mbed_official 205:c41fc65bcfb4 2914
mbed_official 205:c41fc65bcfb4 2915 __HAL_UNLOCK(htim);
mbed_official 205:c41fc65bcfb4 2916
mbed_official 205:c41fc65bcfb4 2917 return HAL_OK;
mbed_official 205:c41fc65bcfb4 2918 }
mbed_official 205:c41fc65bcfb4 2919
mbed_official 205:c41fc65bcfb4 2920 /**
mbed_official 205:c41fc65bcfb4 2921 * @brief Initializes the TIM Input Capture Channels according to the specified
mbed_official 205:c41fc65bcfb4 2922 * parameters in the TIM_IC_InitTypeDef.
mbed_official 205:c41fc65bcfb4 2923 * @param htim: TIM IC handle
mbed_official 205:c41fc65bcfb4 2924 * @param sConfig: TIM Input Capture configuration structure
mbed_official 205:c41fc65bcfb4 2925 * @param Channel : TIM Channels to be enabled
mbed_official 205:c41fc65bcfb4 2926 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 2927 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 205:c41fc65bcfb4 2928 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 205:c41fc65bcfb4 2929 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 205:c41fc65bcfb4 2930 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 205:c41fc65bcfb4 2931 * @retval HAL status
mbed_official 205:c41fc65bcfb4 2932 */
mbed_official 205:c41fc65bcfb4 2933 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
mbed_official 205:c41fc65bcfb4 2934 {
mbed_official 205:c41fc65bcfb4 2935 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 2936 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 2937 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
mbed_official 205:c41fc65bcfb4 2938 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
mbed_official 205:c41fc65bcfb4 2939 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
mbed_official 205:c41fc65bcfb4 2940 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
mbed_official 205:c41fc65bcfb4 2941
mbed_official 205:c41fc65bcfb4 2942 __HAL_LOCK(htim);
mbed_official 205:c41fc65bcfb4 2943
mbed_official 205:c41fc65bcfb4 2944 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 205:c41fc65bcfb4 2945
mbed_official 205:c41fc65bcfb4 2946 if (Channel == TIM_CHANNEL_1)
mbed_official 205:c41fc65bcfb4 2947 {
mbed_official 205:c41fc65bcfb4 2948 /* TI1 Configuration */
mbed_official 205:c41fc65bcfb4 2949 TIM_TI1_SetConfig(htim->Instance,
mbed_official 205:c41fc65bcfb4 2950 sConfig->ICPolarity,
mbed_official 205:c41fc65bcfb4 2951 sConfig->ICSelection,
mbed_official 205:c41fc65bcfb4 2952 sConfig->ICFilter);
mbed_official 205:c41fc65bcfb4 2953
mbed_official 205:c41fc65bcfb4 2954 /* Reset the IC1PSC Bits */
mbed_official 205:c41fc65bcfb4 2955 htim->Instance->CCMR1 &= (uint16_t)(~TIM_CCMR1_IC1PSC);
mbed_official 205:c41fc65bcfb4 2956
mbed_official 205:c41fc65bcfb4 2957 /* Set the IC1PSC value */
mbed_official 205:c41fc65bcfb4 2958 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
mbed_official 205:c41fc65bcfb4 2959 }
mbed_official 205:c41fc65bcfb4 2960 else if (Channel == TIM_CHANNEL_2)
mbed_official 205:c41fc65bcfb4 2961 {
mbed_official 205:c41fc65bcfb4 2962 /* TI2 Configuration */
mbed_official 205:c41fc65bcfb4 2963 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 2964
mbed_official 205:c41fc65bcfb4 2965 TIM_TI2_SetConfig(htim->Instance,
mbed_official 205:c41fc65bcfb4 2966 sConfig->ICPolarity,
mbed_official 205:c41fc65bcfb4 2967 sConfig->ICSelection,
mbed_official 205:c41fc65bcfb4 2968 sConfig->ICFilter);
mbed_official 205:c41fc65bcfb4 2969
mbed_official 205:c41fc65bcfb4 2970 /* Reset the IC2PSC Bits */
mbed_official 205:c41fc65bcfb4 2971 htim->Instance->CCMR1 &= (uint16_t)(~TIM_CCMR1_IC2PSC);
mbed_official 205:c41fc65bcfb4 2972
mbed_official 205:c41fc65bcfb4 2973 /* Set the IC2PSC value */
mbed_official 205:c41fc65bcfb4 2974 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
mbed_official 205:c41fc65bcfb4 2975 }
mbed_official 205:c41fc65bcfb4 2976 else if (Channel == TIM_CHANNEL_3)
mbed_official 205:c41fc65bcfb4 2977 {
mbed_official 205:c41fc65bcfb4 2978 /* TI3 Configuration */
mbed_official 205:c41fc65bcfb4 2979 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 2980
mbed_official 205:c41fc65bcfb4 2981 TIM_TI3_SetConfig(htim->Instance,
mbed_official 205:c41fc65bcfb4 2982 sConfig->ICPolarity,
mbed_official 205:c41fc65bcfb4 2983 sConfig->ICSelection,
mbed_official 205:c41fc65bcfb4 2984 sConfig->ICFilter);
mbed_official 205:c41fc65bcfb4 2985
mbed_official 205:c41fc65bcfb4 2986 /* Reset the IC3PSC Bits */
mbed_official 205:c41fc65bcfb4 2987 htim->Instance->CCMR2 &= (uint16_t)(~TIM_CCMR2_IC3PSC);
mbed_official 205:c41fc65bcfb4 2988
mbed_official 205:c41fc65bcfb4 2989 /* Set the IC3PSC value */
mbed_official 205:c41fc65bcfb4 2990 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
mbed_official 205:c41fc65bcfb4 2991 }
mbed_official 205:c41fc65bcfb4 2992 else
mbed_official 205:c41fc65bcfb4 2993 {
mbed_official 205:c41fc65bcfb4 2994 /* TI4 Configuration */
mbed_official 205:c41fc65bcfb4 2995 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 2996
mbed_official 205:c41fc65bcfb4 2997 TIM_TI4_SetConfig(htim->Instance,
mbed_official 205:c41fc65bcfb4 2998 sConfig->ICPolarity,
mbed_official 205:c41fc65bcfb4 2999 sConfig->ICSelection,
mbed_official 205:c41fc65bcfb4 3000 sConfig->ICFilter);
mbed_official 205:c41fc65bcfb4 3001
mbed_official 205:c41fc65bcfb4 3002 /* Reset the IC4PSC Bits */
mbed_official 205:c41fc65bcfb4 3003 htim->Instance->CCMR2 &= (uint16_t)(~TIM_CCMR2_IC4PSC);
mbed_official 205:c41fc65bcfb4 3004
mbed_official 205:c41fc65bcfb4 3005 /* Set the IC4PSC value */
mbed_official 205:c41fc65bcfb4 3006 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
mbed_official 205:c41fc65bcfb4 3007 }
mbed_official 205:c41fc65bcfb4 3008
mbed_official 205:c41fc65bcfb4 3009 htim->State = HAL_TIM_STATE_READY;
mbed_official 205:c41fc65bcfb4 3010
mbed_official 205:c41fc65bcfb4 3011 __HAL_UNLOCK(htim);
mbed_official 205:c41fc65bcfb4 3012
mbed_official 205:c41fc65bcfb4 3013 return HAL_OK;
mbed_official 205:c41fc65bcfb4 3014 }
mbed_official 205:c41fc65bcfb4 3015
mbed_official 205:c41fc65bcfb4 3016 /**
mbed_official 205:c41fc65bcfb4 3017 * @brief Initializes the TIM PWM channels according to the specified
mbed_official 205:c41fc65bcfb4 3018 * parameters in the TIM_OC_InitTypeDef.
mbed_official 205:c41fc65bcfb4 3019 * @param htim: TIM handle
mbed_official 205:c41fc65bcfb4 3020 * @param sConfig: TIM PWM configuration structure
mbed_official 205:c41fc65bcfb4 3021 * @param Channel : TIM Channels to be enabled
mbed_official 205:c41fc65bcfb4 3022 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 3023 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 205:c41fc65bcfb4 3024 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 205:c41fc65bcfb4 3025 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 205:c41fc65bcfb4 3026 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 205:c41fc65bcfb4 3027 * @retval HAL status
mbed_official 205:c41fc65bcfb4 3028 */
mbed_official 205:c41fc65bcfb4 3029 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
mbed_official 205:c41fc65bcfb4 3030 {
mbed_official 205:c41fc65bcfb4 3031 __HAL_LOCK(htim);
mbed_official 205:c41fc65bcfb4 3032
mbed_official 205:c41fc65bcfb4 3033 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 3034 assert_param(IS_TIM_CHANNELS(Channel));
mbed_official 205:c41fc65bcfb4 3035 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
mbed_official 205:c41fc65bcfb4 3036 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
mbed_official 205:c41fc65bcfb4 3037 assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
mbed_official 205:c41fc65bcfb4 3038 assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
mbed_official 205:c41fc65bcfb4 3039 assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
mbed_official 205:c41fc65bcfb4 3040
mbed_official 205:c41fc65bcfb4 3041 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 205:c41fc65bcfb4 3042
mbed_official 205:c41fc65bcfb4 3043 switch (Channel)
mbed_official 205:c41fc65bcfb4 3044 {
mbed_official 205:c41fc65bcfb4 3045 case TIM_CHANNEL_1:
mbed_official 205:c41fc65bcfb4 3046 {
mbed_official 205:c41fc65bcfb4 3047 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 3048 /* Configure the Channel 1 in PWM mode */
mbed_official 205:c41fc65bcfb4 3049 TIM_OC1_SetConfig(htim->Instance, sConfig);
mbed_official 205:c41fc65bcfb4 3050
mbed_official 205:c41fc65bcfb4 3051 /* Set the Preload enable bit for channel1 */
mbed_official 205:c41fc65bcfb4 3052 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
mbed_official 205:c41fc65bcfb4 3053
mbed_official 205:c41fc65bcfb4 3054 /* Configure the Output Fast mode */
mbed_official 205:c41fc65bcfb4 3055 htim->Instance->CCMR1 &= (uint16_t)(~TIM_CCMR1_OC1FE);
mbed_official 205:c41fc65bcfb4 3056 htim->Instance->CCMR1 |= sConfig->OCFastMode;
mbed_official 205:c41fc65bcfb4 3057 }
mbed_official 205:c41fc65bcfb4 3058 break;
mbed_official 205:c41fc65bcfb4 3059
mbed_official 205:c41fc65bcfb4 3060 case TIM_CHANNEL_2:
mbed_official 205:c41fc65bcfb4 3061 {
mbed_official 205:c41fc65bcfb4 3062 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 3063 /* Configure the Channel 2 in PWM mode */
mbed_official 205:c41fc65bcfb4 3064 TIM_OC2_SetConfig(htim->Instance, sConfig);
mbed_official 205:c41fc65bcfb4 3065
mbed_official 205:c41fc65bcfb4 3066 /* Set the Preload enable bit for channel2 */
mbed_official 205:c41fc65bcfb4 3067 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
mbed_official 205:c41fc65bcfb4 3068
mbed_official 205:c41fc65bcfb4 3069 /* Configure the Output Fast mode */
mbed_official 205:c41fc65bcfb4 3070 htim->Instance->CCMR1 &= (uint16_t)(~TIM_CCMR1_OC2FE);
mbed_official 205:c41fc65bcfb4 3071 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
mbed_official 205:c41fc65bcfb4 3072 }
mbed_official 205:c41fc65bcfb4 3073 break;
mbed_official 205:c41fc65bcfb4 3074
mbed_official 205:c41fc65bcfb4 3075 case TIM_CHANNEL_3:
mbed_official 205:c41fc65bcfb4 3076 {
mbed_official 205:c41fc65bcfb4 3077 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 3078 /* Configure the Channel 3 in PWM mode */
mbed_official 205:c41fc65bcfb4 3079 TIM_OC3_SetConfig(htim->Instance, sConfig);
mbed_official 205:c41fc65bcfb4 3080
mbed_official 205:c41fc65bcfb4 3081 /* Set the Preload enable bit for channel3 */
mbed_official 205:c41fc65bcfb4 3082 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
mbed_official 205:c41fc65bcfb4 3083
mbed_official 205:c41fc65bcfb4 3084 /* Configure the Output Fast mode */
mbed_official 205:c41fc65bcfb4 3085 htim->Instance->CCMR2 &= (uint16_t)(~TIM_CCMR2_OC3FE);
mbed_official 205:c41fc65bcfb4 3086 htim->Instance->CCMR2 |= sConfig->OCFastMode;
mbed_official 205:c41fc65bcfb4 3087 }
mbed_official 205:c41fc65bcfb4 3088 break;
mbed_official 205:c41fc65bcfb4 3089
mbed_official 205:c41fc65bcfb4 3090 case TIM_CHANNEL_4:
mbed_official 205:c41fc65bcfb4 3091 {
mbed_official 205:c41fc65bcfb4 3092 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 3093 /* Configure the Channel 4 in PWM mode */
mbed_official 205:c41fc65bcfb4 3094 TIM_OC4_SetConfig(htim->Instance, sConfig);
mbed_official 205:c41fc65bcfb4 3095
mbed_official 205:c41fc65bcfb4 3096 /* Set the Preload enable bit for channel4 */
mbed_official 205:c41fc65bcfb4 3097 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
mbed_official 205:c41fc65bcfb4 3098
mbed_official 205:c41fc65bcfb4 3099 /* Configure the Output Fast mode */
mbed_official 205:c41fc65bcfb4 3100 htim->Instance->CCMR2 &= (uint16_t)(~TIM_CCMR2_OC4FE);
mbed_official 205:c41fc65bcfb4 3101 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
mbed_official 205:c41fc65bcfb4 3102 }
mbed_official 205:c41fc65bcfb4 3103 break;
mbed_official 205:c41fc65bcfb4 3104
mbed_official 205:c41fc65bcfb4 3105 default:
mbed_official 205:c41fc65bcfb4 3106 break;
mbed_official 205:c41fc65bcfb4 3107 }
mbed_official 205:c41fc65bcfb4 3108
mbed_official 205:c41fc65bcfb4 3109 htim->State = HAL_TIM_STATE_READY;
mbed_official 205:c41fc65bcfb4 3110
mbed_official 205:c41fc65bcfb4 3111 __HAL_UNLOCK(htim);
mbed_official 205:c41fc65bcfb4 3112
mbed_official 205:c41fc65bcfb4 3113 return HAL_OK;
mbed_official 205:c41fc65bcfb4 3114 }
mbed_official 205:c41fc65bcfb4 3115
mbed_official 205:c41fc65bcfb4 3116 /**
mbed_official 205:c41fc65bcfb4 3117 * @brief Initializes the TIM One Pulse Channels according to the specified
mbed_official 205:c41fc65bcfb4 3118 * parameters in the TIM_OnePulse_InitTypeDef.
mbed_official 205:c41fc65bcfb4 3119 * @param htim: TIM One Pulse handle
mbed_official 205:c41fc65bcfb4 3120 * @param sConfig: TIM One Pulse configuration structure
mbed_official 205:c41fc65bcfb4 3121 * @param OutputChannel : TIM Channels to be enabled
mbed_official 205:c41fc65bcfb4 3122 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 3123 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 205:c41fc65bcfb4 3124 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 205:c41fc65bcfb4 3125 * @param InputChannel : TIM Channels to be enabled
mbed_official 205:c41fc65bcfb4 3126 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 3127 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 205:c41fc65bcfb4 3128 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 205:c41fc65bcfb4 3129 * @retval HAL status
mbed_official 205:c41fc65bcfb4 3130 */
mbed_official 205:c41fc65bcfb4 3131 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
mbed_official 205:c41fc65bcfb4 3132 {
mbed_official 205:c41fc65bcfb4 3133 TIM_OC_InitTypeDef temp1;
mbed_official 205:c41fc65bcfb4 3134
mbed_official 205:c41fc65bcfb4 3135 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 3136 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
mbed_official 205:c41fc65bcfb4 3137 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
mbed_official 205:c41fc65bcfb4 3138
mbed_official 205:c41fc65bcfb4 3139 if(OutputChannel != InputChannel)
mbed_official 205:c41fc65bcfb4 3140 {
mbed_official 205:c41fc65bcfb4 3141 __HAL_LOCK(htim);
mbed_official 205:c41fc65bcfb4 3142
mbed_official 205:c41fc65bcfb4 3143 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 205:c41fc65bcfb4 3144
mbed_official 205:c41fc65bcfb4 3145 /* Extract the Ouput compare configuration from sConfig structure */
mbed_official 205:c41fc65bcfb4 3146 temp1.OCMode = sConfig->OCMode;
mbed_official 205:c41fc65bcfb4 3147 temp1.Pulse = sConfig->Pulse;
mbed_official 205:c41fc65bcfb4 3148 temp1.OCPolarity = sConfig->OCPolarity;
mbed_official 205:c41fc65bcfb4 3149 temp1.OCNPolarity = sConfig->OCNPolarity;
mbed_official 205:c41fc65bcfb4 3150 temp1.OCIdleState = sConfig->OCIdleState;
mbed_official 205:c41fc65bcfb4 3151 temp1.OCNIdleState = sConfig->OCNIdleState;
mbed_official 205:c41fc65bcfb4 3152
mbed_official 205:c41fc65bcfb4 3153 switch (OutputChannel)
mbed_official 205:c41fc65bcfb4 3154 {
mbed_official 205:c41fc65bcfb4 3155 case TIM_CHANNEL_1:
mbed_official 205:c41fc65bcfb4 3156 {
mbed_official 205:c41fc65bcfb4 3157 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 3158
mbed_official 205:c41fc65bcfb4 3159 TIM_OC1_SetConfig(htim->Instance, &temp1);
mbed_official 205:c41fc65bcfb4 3160 }
mbed_official 205:c41fc65bcfb4 3161 break;
mbed_official 205:c41fc65bcfb4 3162 case TIM_CHANNEL_2:
mbed_official 205:c41fc65bcfb4 3163 {
mbed_official 205:c41fc65bcfb4 3164 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 3165
mbed_official 205:c41fc65bcfb4 3166 TIM_OC2_SetConfig(htim->Instance, &temp1);
mbed_official 205:c41fc65bcfb4 3167 }
mbed_official 205:c41fc65bcfb4 3168 break;
mbed_official 205:c41fc65bcfb4 3169 default:
mbed_official 205:c41fc65bcfb4 3170 break;
mbed_official 205:c41fc65bcfb4 3171 }
mbed_official 205:c41fc65bcfb4 3172 switch (InputChannel)
mbed_official 205:c41fc65bcfb4 3173 {
mbed_official 205:c41fc65bcfb4 3174 case TIM_CHANNEL_1:
mbed_official 205:c41fc65bcfb4 3175 {
mbed_official 205:c41fc65bcfb4 3176 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 3177
mbed_official 205:c41fc65bcfb4 3178 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
mbed_official 205:c41fc65bcfb4 3179 sConfig->ICSelection, sConfig->ICFilter);
mbed_official 205:c41fc65bcfb4 3180
mbed_official 205:c41fc65bcfb4 3181 /* Reset the IC1PSC Bits */
mbed_official 205:c41fc65bcfb4 3182 htim->Instance->CCMR1 &= (uint16_t)(~TIM_CCMR1_IC1PSC);
mbed_official 205:c41fc65bcfb4 3183
mbed_official 205:c41fc65bcfb4 3184 /* Select the Trigger source */
mbed_official 205:c41fc65bcfb4 3185 htim->Instance->SMCR &= (uint16_t)(~TIM_SMCR_TS);
mbed_official 205:c41fc65bcfb4 3186 htim->Instance->SMCR |= TIM_TS_TI1FP1;
mbed_official 205:c41fc65bcfb4 3187
mbed_official 205:c41fc65bcfb4 3188 /* Select the Slave Mode */
mbed_official 205:c41fc65bcfb4 3189 htim->Instance->SMCR &= (uint16_t)(~TIM_SMCR_SMS);
mbed_official 205:c41fc65bcfb4 3190 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
mbed_official 205:c41fc65bcfb4 3191 }
mbed_official 205:c41fc65bcfb4 3192 break;
mbed_official 205:c41fc65bcfb4 3193 case TIM_CHANNEL_2:
mbed_official 205:c41fc65bcfb4 3194 {
mbed_official 205:c41fc65bcfb4 3195 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 3196
mbed_official 205:c41fc65bcfb4 3197 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
mbed_official 205:c41fc65bcfb4 3198 sConfig->ICSelection, sConfig->ICFilter);
mbed_official 205:c41fc65bcfb4 3199
mbed_official 205:c41fc65bcfb4 3200 /* Reset the IC2PSC Bits */
mbed_official 205:c41fc65bcfb4 3201 htim->Instance->CCMR1 &= (uint16_t)(~TIM_CCMR1_IC2PSC);
mbed_official 205:c41fc65bcfb4 3202
mbed_official 205:c41fc65bcfb4 3203 /* Select the Trigger source */
mbed_official 205:c41fc65bcfb4 3204 htim->Instance->SMCR &= (uint16_t)(~TIM_SMCR_TS);
mbed_official 205:c41fc65bcfb4 3205 htim->Instance->SMCR |= TIM_TS_TI2FP2;
mbed_official 205:c41fc65bcfb4 3206
mbed_official 205:c41fc65bcfb4 3207 /* Select the Slave Mode */
mbed_official 205:c41fc65bcfb4 3208 htim->Instance->SMCR &= (uint16_t)(~TIM_SMCR_SMS);
mbed_official 205:c41fc65bcfb4 3209 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
mbed_official 205:c41fc65bcfb4 3210 }
mbed_official 205:c41fc65bcfb4 3211 break;
mbed_official 205:c41fc65bcfb4 3212
mbed_official 205:c41fc65bcfb4 3213 default:
mbed_official 205:c41fc65bcfb4 3214 break;
mbed_official 205:c41fc65bcfb4 3215 }
mbed_official 205:c41fc65bcfb4 3216
mbed_official 205:c41fc65bcfb4 3217 htim->State = HAL_TIM_STATE_READY;
mbed_official 205:c41fc65bcfb4 3218
mbed_official 205:c41fc65bcfb4 3219 __HAL_UNLOCK(htim);
mbed_official 205:c41fc65bcfb4 3220
mbed_official 205:c41fc65bcfb4 3221 return HAL_OK;
mbed_official 205:c41fc65bcfb4 3222 }
mbed_official 205:c41fc65bcfb4 3223 else
mbed_official 205:c41fc65bcfb4 3224 {
mbed_official 205:c41fc65bcfb4 3225 return HAL_ERROR;
mbed_official 205:c41fc65bcfb4 3226 }
mbed_official 205:c41fc65bcfb4 3227 }
mbed_official 205:c41fc65bcfb4 3228
mbed_official 205:c41fc65bcfb4 3229 /**
mbed_official 205:c41fc65bcfb4 3230 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
mbed_official 205:c41fc65bcfb4 3231 * @param htim: TIM handle
mbed_official 205:c41fc65bcfb4 3232 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write
mbed_official 205:c41fc65bcfb4 3233 * This parameters can be on of the following values:
mbed_official 205:c41fc65bcfb4 3234 * @arg TIM_DMABase_CR1
mbed_official 205:c41fc65bcfb4 3235 * @arg TIM_DMABase_CR2
mbed_official 205:c41fc65bcfb4 3236 * @arg TIM_DMABase_SMCR
mbed_official 205:c41fc65bcfb4 3237 * @arg TIM_DMABase_DIER
mbed_official 205:c41fc65bcfb4 3238 * @arg TIM_DMABase_SR
mbed_official 205:c41fc65bcfb4 3239 * @arg TIM_DMABase_EGR
mbed_official 205:c41fc65bcfb4 3240 * @arg TIM_DMABase_CCMR1
mbed_official 205:c41fc65bcfb4 3241 * @arg TIM_DMABase_CCMR2
mbed_official 205:c41fc65bcfb4 3242 * @arg TIM_DMABase_CCER
mbed_official 205:c41fc65bcfb4 3243 * @arg TIM_DMABase_CNT
mbed_official 205:c41fc65bcfb4 3244 * @arg TIM_DMABase_PSC
mbed_official 205:c41fc65bcfb4 3245 * @arg TIM_DMABase_ARR
mbed_official 205:c41fc65bcfb4 3246 * @arg TIM_DMABase_RCR
mbed_official 205:c41fc65bcfb4 3247 * @arg TIM_DMABase_CCR1
mbed_official 205:c41fc65bcfb4 3248 * @arg TIM_DMABase_CCR2
mbed_official 205:c41fc65bcfb4 3249 * @arg TIM_DMABase_CCR3
mbed_official 205:c41fc65bcfb4 3250 * @arg TIM_DMABase_CCR4
mbed_official 205:c41fc65bcfb4 3251 * @arg TIM_DMABase_BDTR
mbed_official 205:c41fc65bcfb4 3252 * @arg TIM_DMABase_DCR
mbed_official 205:c41fc65bcfb4 3253 * @param BurstRequestSrc: TIM DMA Request sources
mbed_official 205:c41fc65bcfb4 3254 * This parameters can be on of the following values:
mbed_official 205:c41fc65bcfb4 3255 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
mbed_official 205:c41fc65bcfb4 3256 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
mbed_official 205:c41fc65bcfb4 3257 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
mbed_official 205:c41fc65bcfb4 3258 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
mbed_official 205:c41fc65bcfb4 3259 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
mbed_official 205:c41fc65bcfb4 3260 * @arg TIM_DMA_COM: TIM Commutation DMA source
mbed_official 205:c41fc65bcfb4 3261 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
mbed_official 205:c41fc65bcfb4 3262 * @param BurstBuffer: The Buffer address.
mbed_official 205:c41fc65bcfb4 3263 * @param BurstLength: DMA Burst length. This parameter can be one value
mbed_official 205:c41fc65bcfb4 3264 * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
mbed_official 205:c41fc65bcfb4 3265 * @retval HAL status
mbed_official 205:c41fc65bcfb4 3266 */
mbed_official 205:c41fc65bcfb4 3267 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
mbed_official 205:c41fc65bcfb4 3268 uint32_t* BurstBuffer, uint32_t BurstLength)
mbed_official 205:c41fc65bcfb4 3269 {
mbed_official 205:c41fc65bcfb4 3270 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 3271 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 3272 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
mbed_official 205:c41fc65bcfb4 3273 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
mbed_official 205:c41fc65bcfb4 3274 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
mbed_official 205:c41fc65bcfb4 3275
mbed_official 205:c41fc65bcfb4 3276 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 205:c41fc65bcfb4 3277 {
mbed_official 205:c41fc65bcfb4 3278 return HAL_BUSY;
mbed_official 205:c41fc65bcfb4 3279 }
mbed_official 205:c41fc65bcfb4 3280 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 205:c41fc65bcfb4 3281 {
mbed_official 205:c41fc65bcfb4 3282 if((BurstBuffer == 0 ) && (BurstLength > 0))
mbed_official 205:c41fc65bcfb4 3283 {
mbed_official 205:c41fc65bcfb4 3284 return HAL_ERROR;
mbed_official 205:c41fc65bcfb4 3285 }
mbed_official 205:c41fc65bcfb4 3286 else
mbed_official 205:c41fc65bcfb4 3287 {
mbed_official 205:c41fc65bcfb4 3288 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 205:c41fc65bcfb4 3289 }
mbed_official 205:c41fc65bcfb4 3290 }
mbed_official 205:c41fc65bcfb4 3291 switch(BurstRequestSrc)
mbed_official 205:c41fc65bcfb4 3292 {
mbed_official 205:c41fc65bcfb4 3293 case TIM_DMA_UPDATE:
mbed_official 205:c41fc65bcfb4 3294 {
mbed_official 205:c41fc65bcfb4 3295 /* Set the DMA Period elapsed callback */
mbed_official 205:c41fc65bcfb4 3296 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
mbed_official 205:c41fc65bcfb4 3297
mbed_official 205:c41fc65bcfb4 3298 /* Set the DMA error callback */
mbed_official 205:c41fc65bcfb4 3299 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 205:c41fc65bcfb4 3300
mbed_official 205:c41fc65bcfb4 3301 /* Enable the DMA channel */
mbed_official 205:c41fc65bcfb4 3302 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 205:c41fc65bcfb4 3303 }
mbed_official 205:c41fc65bcfb4 3304 break;
mbed_official 205:c41fc65bcfb4 3305 case TIM_DMA_CC1:
mbed_official 205:c41fc65bcfb4 3306 {
mbed_official 205:c41fc65bcfb4 3307 /* Set the DMA Period elapsed callback */
mbed_official 205:c41fc65bcfb4 3308 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official 205:c41fc65bcfb4 3309
mbed_official 205:c41fc65bcfb4 3310 /* Set the DMA error callback */
mbed_official 205:c41fc65bcfb4 3311 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 205:c41fc65bcfb4 3312
mbed_official 205:c41fc65bcfb4 3313 /* Enable the DMA channel */
mbed_official 205:c41fc65bcfb4 3314 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 205:c41fc65bcfb4 3315 }
mbed_official 205:c41fc65bcfb4 3316 break;
mbed_official 205:c41fc65bcfb4 3317 case TIM_DMA_CC2:
mbed_official 205:c41fc65bcfb4 3318 {
mbed_official 205:c41fc65bcfb4 3319 /* Set the DMA Period elapsed callback */
mbed_official 205:c41fc65bcfb4 3320 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official 205:c41fc65bcfb4 3321
mbed_official 205:c41fc65bcfb4 3322 /* Set the DMA error callback */
mbed_official 205:c41fc65bcfb4 3323 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 205:c41fc65bcfb4 3324
mbed_official 205:c41fc65bcfb4 3325 /* Enable the DMA channel */
mbed_official 205:c41fc65bcfb4 3326 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 205:c41fc65bcfb4 3327 }
mbed_official 205:c41fc65bcfb4 3328 break;
mbed_official 205:c41fc65bcfb4 3329 case TIM_DMA_CC3:
mbed_official 205:c41fc65bcfb4 3330 {
mbed_official 205:c41fc65bcfb4 3331 /* Set the DMA Period elapsed callback */
mbed_official 205:c41fc65bcfb4 3332 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official 205:c41fc65bcfb4 3333
mbed_official 205:c41fc65bcfb4 3334 /* Set the DMA error callback */
mbed_official 205:c41fc65bcfb4 3335 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 205:c41fc65bcfb4 3336
mbed_official 205:c41fc65bcfb4 3337 /* Enable the DMA channel */
mbed_official 205:c41fc65bcfb4 3338 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 205:c41fc65bcfb4 3339 }
mbed_official 205:c41fc65bcfb4 3340 break;
mbed_official 205:c41fc65bcfb4 3341 case TIM_DMA_CC4:
mbed_official 205:c41fc65bcfb4 3342 {
mbed_official 205:c41fc65bcfb4 3343 /* Set the DMA Period elapsed callback */
mbed_official 205:c41fc65bcfb4 3344 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official 205:c41fc65bcfb4 3345
mbed_official 205:c41fc65bcfb4 3346 /* Set the DMA error callback */
mbed_official 205:c41fc65bcfb4 3347 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 205:c41fc65bcfb4 3348
mbed_official 205:c41fc65bcfb4 3349 /* Enable the DMA channel */
mbed_official 205:c41fc65bcfb4 3350 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 205:c41fc65bcfb4 3351 }
mbed_official 205:c41fc65bcfb4 3352 break;
mbed_official 205:c41fc65bcfb4 3353 case TIM_DMA_COM:
mbed_official 205:c41fc65bcfb4 3354 {
mbed_official 205:c41fc65bcfb4 3355 /* Set the DMA Period elapsed callback */
mbed_official 205:c41fc65bcfb4 3356 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
mbed_official 205:c41fc65bcfb4 3357
mbed_official 205:c41fc65bcfb4 3358 /* Set the DMA error callback */
mbed_official 205:c41fc65bcfb4 3359 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 205:c41fc65bcfb4 3360
mbed_official 205:c41fc65bcfb4 3361 /* Enable the DMA channel */
mbed_official 205:c41fc65bcfb4 3362 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 205:c41fc65bcfb4 3363 }
mbed_official 205:c41fc65bcfb4 3364 break;
mbed_official 205:c41fc65bcfb4 3365 case TIM_DMA_TRIGGER:
mbed_official 205:c41fc65bcfb4 3366 {
mbed_official 205:c41fc65bcfb4 3367 /* Set the DMA Period elapsed callback */
mbed_official 205:c41fc65bcfb4 3368 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
mbed_official 205:c41fc65bcfb4 3369
mbed_official 205:c41fc65bcfb4 3370 /* Set the DMA error callback */
mbed_official 205:c41fc65bcfb4 3371 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 205:c41fc65bcfb4 3372
mbed_official 205:c41fc65bcfb4 3373 /* Enable the DMA channel */
mbed_official 205:c41fc65bcfb4 3374 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 205:c41fc65bcfb4 3375 }
mbed_official 205:c41fc65bcfb4 3376 break;
mbed_official 205:c41fc65bcfb4 3377 default:
mbed_official 205:c41fc65bcfb4 3378 break;
mbed_official 205:c41fc65bcfb4 3379 }
mbed_official 205:c41fc65bcfb4 3380 /* configure the DMA Burst Mode */
mbed_official 205:c41fc65bcfb4 3381 htim->Instance->DCR = BurstBaseAddress | BurstLength;
mbed_official 205:c41fc65bcfb4 3382
mbed_official 205:c41fc65bcfb4 3383 /* Enable the TIM DMA Request */
mbed_official 205:c41fc65bcfb4 3384 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
mbed_official 205:c41fc65bcfb4 3385
mbed_official 205:c41fc65bcfb4 3386 htim->State = HAL_TIM_STATE_READY;
mbed_official 205:c41fc65bcfb4 3387
mbed_official 205:c41fc65bcfb4 3388 /* Return function status */
mbed_official 205:c41fc65bcfb4 3389 return HAL_OK;
mbed_official 205:c41fc65bcfb4 3390 }
mbed_official 205:c41fc65bcfb4 3391
mbed_official 205:c41fc65bcfb4 3392 /**
mbed_official 205:c41fc65bcfb4 3393 * @brief Stops the TIM DMA Burst mode
mbed_official 205:c41fc65bcfb4 3394 * @param htim: TIM handle
mbed_official 205:c41fc65bcfb4 3395 * @param BurstRequestSrc: TIM DMA Request sources to disable
mbed_official 205:c41fc65bcfb4 3396 * @retval HAL status
mbed_official 205:c41fc65bcfb4 3397 */
mbed_official 205:c41fc65bcfb4 3398 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
mbed_official 205:c41fc65bcfb4 3399 {
mbed_official 205:c41fc65bcfb4 3400 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 3401 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
mbed_official 205:c41fc65bcfb4 3402
mbed_official 205:c41fc65bcfb4 3403 /* Abort the DMA transfer (at least disable the DMA channel) */
mbed_official 205:c41fc65bcfb4 3404 switch(BurstRequestSrc)
mbed_official 205:c41fc65bcfb4 3405 {
mbed_official 205:c41fc65bcfb4 3406 case TIM_DMA_UPDATE:
mbed_official 205:c41fc65bcfb4 3407 {
mbed_official 205:c41fc65bcfb4 3408 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
mbed_official 205:c41fc65bcfb4 3409 }
mbed_official 205:c41fc65bcfb4 3410 break;
mbed_official 205:c41fc65bcfb4 3411 case TIM_DMA_CC1:
mbed_official 205:c41fc65bcfb4 3412 {
mbed_official 205:c41fc65bcfb4 3413 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
mbed_official 205:c41fc65bcfb4 3414 }
mbed_official 205:c41fc65bcfb4 3415 break;
mbed_official 205:c41fc65bcfb4 3416 case TIM_DMA_CC2:
mbed_official 205:c41fc65bcfb4 3417 {
mbed_official 205:c41fc65bcfb4 3418 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
mbed_official 205:c41fc65bcfb4 3419 }
mbed_official 205:c41fc65bcfb4 3420 break;
mbed_official 205:c41fc65bcfb4 3421 case TIM_DMA_CC3:
mbed_official 205:c41fc65bcfb4 3422 {
mbed_official 205:c41fc65bcfb4 3423 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
mbed_official 205:c41fc65bcfb4 3424 }
mbed_official 205:c41fc65bcfb4 3425 break;
mbed_official 205:c41fc65bcfb4 3426 case TIM_DMA_CC4:
mbed_official 205:c41fc65bcfb4 3427 {
mbed_official 205:c41fc65bcfb4 3428 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
mbed_official 205:c41fc65bcfb4 3429 }
mbed_official 205:c41fc65bcfb4 3430 break;
mbed_official 205:c41fc65bcfb4 3431 case TIM_DMA_COM:
mbed_official 205:c41fc65bcfb4 3432 {
mbed_official 205:c41fc65bcfb4 3433 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
mbed_official 205:c41fc65bcfb4 3434 }
mbed_official 205:c41fc65bcfb4 3435 break;
mbed_official 205:c41fc65bcfb4 3436 case TIM_DMA_TRIGGER:
mbed_official 205:c41fc65bcfb4 3437 {
mbed_official 205:c41fc65bcfb4 3438 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
mbed_official 205:c41fc65bcfb4 3439 }
mbed_official 205:c41fc65bcfb4 3440 break;
mbed_official 205:c41fc65bcfb4 3441 default:
mbed_official 205:c41fc65bcfb4 3442 break;
mbed_official 205:c41fc65bcfb4 3443 }
mbed_official 205:c41fc65bcfb4 3444
mbed_official 205:c41fc65bcfb4 3445 /* Disable the TIM Update DMA request */
mbed_official 205:c41fc65bcfb4 3446 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
mbed_official 205:c41fc65bcfb4 3447
mbed_official 205:c41fc65bcfb4 3448 /* Return function status */
mbed_official 205:c41fc65bcfb4 3449 return HAL_OK;
mbed_official 205:c41fc65bcfb4 3450 }
mbed_official 205:c41fc65bcfb4 3451
mbed_official 205:c41fc65bcfb4 3452 /**
mbed_official 205:c41fc65bcfb4 3453 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
mbed_official 205:c41fc65bcfb4 3454 * @param htim: TIM handle
mbed_official 205:c41fc65bcfb4 3455 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read
mbed_official 205:c41fc65bcfb4 3456 * This parameters can be on of the following values:
mbed_official 205:c41fc65bcfb4 3457 * @arg TIM_DMABase_CR1
mbed_official 205:c41fc65bcfb4 3458 * @arg TIM_DMABase_CR2
mbed_official 205:c41fc65bcfb4 3459 * @arg TIM_DMABase_SMCR
mbed_official 205:c41fc65bcfb4 3460 * @arg TIM_DMABase_DIER
mbed_official 205:c41fc65bcfb4 3461 * @arg TIM_DMABase_SR
mbed_official 205:c41fc65bcfb4 3462 * @arg TIM_DMABase_EGR
mbed_official 205:c41fc65bcfb4 3463 * @arg TIM_DMABase_CCMR1
mbed_official 205:c41fc65bcfb4 3464 * @arg TIM_DMABase_CCMR2
mbed_official 205:c41fc65bcfb4 3465 * @arg TIM_DMABase_CCER
mbed_official 205:c41fc65bcfb4 3466 * @arg TIM_DMABase_CNT
mbed_official 205:c41fc65bcfb4 3467 * @arg TIM_DMABase_PSC
mbed_official 205:c41fc65bcfb4 3468 * @arg TIM_DMABase_ARR
mbed_official 205:c41fc65bcfb4 3469 * @arg TIM_DMABase_RCR
mbed_official 205:c41fc65bcfb4 3470 * @arg TIM_DMABase_CCR1
mbed_official 205:c41fc65bcfb4 3471 * @arg TIM_DMABase_CCR2
mbed_official 205:c41fc65bcfb4 3472 * @arg TIM_DMABase_CCR3
mbed_official 205:c41fc65bcfb4 3473 * @arg TIM_DMABase_CCR4
mbed_official 205:c41fc65bcfb4 3474 * @arg TIM_DMABase_BDTR
mbed_official 205:c41fc65bcfb4 3475 * @arg TIM_DMABase_DCR
mbed_official 205:c41fc65bcfb4 3476 * @param BurstRequestSrc: TIM DMA Request sources
mbed_official 205:c41fc65bcfb4 3477 * This parameters can be on of the following values:
mbed_official 205:c41fc65bcfb4 3478 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
mbed_official 205:c41fc65bcfb4 3479 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
mbed_official 205:c41fc65bcfb4 3480 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
mbed_official 205:c41fc65bcfb4 3481 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
mbed_official 205:c41fc65bcfb4 3482 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
mbed_official 205:c41fc65bcfb4 3483 * @arg TIM_DMA_COM: TIM Commutation DMA source
mbed_official 205:c41fc65bcfb4 3484 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
mbed_official 205:c41fc65bcfb4 3485 * @param BurstBuffer: The Buffer address.
mbed_official 205:c41fc65bcfb4 3486 * @param BurstLength: DMA Burst length. This parameter can be one value
mbed_official 205:c41fc65bcfb4 3487 * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
mbed_official 205:c41fc65bcfb4 3488 * @retval HAL status
mbed_official 205:c41fc65bcfb4 3489 */
mbed_official 205:c41fc65bcfb4 3490 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
mbed_official 205:c41fc65bcfb4 3491 uint32_t *BurstBuffer, uint32_t BurstLength)
mbed_official 205:c41fc65bcfb4 3492 {
mbed_official 205:c41fc65bcfb4 3493 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 3494 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 3495 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
mbed_official 205:c41fc65bcfb4 3496 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
mbed_official 205:c41fc65bcfb4 3497 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
mbed_official 205:c41fc65bcfb4 3498
mbed_official 205:c41fc65bcfb4 3499 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 205:c41fc65bcfb4 3500 {
mbed_official 205:c41fc65bcfb4 3501 return HAL_BUSY;
mbed_official 205:c41fc65bcfb4 3502 }
mbed_official 205:c41fc65bcfb4 3503 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 205:c41fc65bcfb4 3504 {
mbed_official 205:c41fc65bcfb4 3505 if((BurstBuffer == 0 ) && (BurstLength > 0))
mbed_official 205:c41fc65bcfb4 3506 {
mbed_official 205:c41fc65bcfb4 3507 return HAL_ERROR;
mbed_official 205:c41fc65bcfb4 3508 }
mbed_official 205:c41fc65bcfb4 3509 else
mbed_official 205:c41fc65bcfb4 3510 {
mbed_official 205:c41fc65bcfb4 3511 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 205:c41fc65bcfb4 3512 }
mbed_official 205:c41fc65bcfb4 3513 }
mbed_official 205:c41fc65bcfb4 3514 switch(BurstRequestSrc)
mbed_official 205:c41fc65bcfb4 3515 {
mbed_official 205:c41fc65bcfb4 3516 case TIM_DMA_UPDATE:
mbed_official 205:c41fc65bcfb4 3517 {
mbed_official 205:c41fc65bcfb4 3518 /* Set the DMA Period elapsed callback */
mbed_official 205:c41fc65bcfb4 3519 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
mbed_official 205:c41fc65bcfb4 3520
mbed_official 205:c41fc65bcfb4 3521 /* Set the DMA error callback */
mbed_official 205:c41fc65bcfb4 3522 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 205:c41fc65bcfb4 3523
mbed_official 205:c41fc65bcfb4 3524 /* Enable the DMA channel */
mbed_official 205:c41fc65bcfb4 3525 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 205:c41fc65bcfb4 3526 }
mbed_official 205:c41fc65bcfb4 3527 break;
mbed_official 205:c41fc65bcfb4 3528 case TIM_DMA_CC1:
mbed_official 205:c41fc65bcfb4 3529 {
mbed_official 205:c41fc65bcfb4 3530 /* Set the DMA Period elapsed callback */
mbed_official 205:c41fc65bcfb4 3531 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official 205:c41fc65bcfb4 3532
mbed_official 205:c41fc65bcfb4 3533 /* Set the DMA error callback */
mbed_official 205:c41fc65bcfb4 3534 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 205:c41fc65bcfb4 3535
mbed_official 205:c41fc65bcfb4 3536 /* Enable the DMA channel */
mbed_official 205:c41fc65bcfb4 3537 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 205:c41fc65bcfb4 3538 }
mbed_official 205:c41fc65bcfb4 3539 break;
mbed_official 205:c41fc65bcfb4 3540 case TIM_DMA_CC2:
mbed_official 205:c41fc65bcfb4 3541 {
mbed_official 205:c41fc65bcfb4 3542 /* Set the DMA Period elapsed callback */
mbed_official 205:c41fc65bcfb4 3543 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official 205:c41fc65bcfb4 3544
mbed_official 205:c41fc65bcfb4 3545 /* Set the DMA error callback */
mbed_official 205:c41fc65bcfb4 3546 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 205:c41fc65bcfb4 3547
mbed_official 205:c41fc65bcfb4 3548 /* Enable the DMA channel */
mbed_official 205:c41fc65bcfb4 3549 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 205:c41fc65bcfb4 3550 }
mbed_official 205:c41fc65bcfb4 3551 break;
mbed_official 205:c41fc65bcfb4 3552 case TIM_DMA_CC3:
mbed_official 205:c41fc65bcfb4 3553 {
mbed_official 205:c41fc65bcfb4 3554 /* Set the DMA Period elapsed callback */
mbed_official 205:c41fc65bcfb4 3555 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official 205:c41fc65bcfb4 3556
mbed_official 205:c41fc65bcfb4 3557 /* Set the DMA error callback */
mbed_official 205:c41fc65bcfb4 3558 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 205:c41fc65bcfb4 3559
mbed_official 205:c41fc65bcfb4 3560 /* Enable the DMA channel */
mbed_official 205:c41fc65bcfb4 3561 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 205:c41fc65bcfb4 3562 }
mbed_official 205:c41fc65bcfb4 3563 break;
mbed_official 205:c41fc65bcfb4 3564 case TIM_DMA_CC4:
mbed_official 205:c41fc65bcfb4 3565 {
mbed_official 205:c41fc65bcfb4 3566 /* Set the DMA Period elapsed callback */
mbed_official 205:c41fc65bcfb4 3567 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official 205:c41fc65bcfb4 3568
mbed_official 205:c41fc65bcfb4 3569 /* Set the DMA error callback */
mbed_official 205:c41fc65bcfb4 3570 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 205:c41fc65bcfb4 3571
mbed_official 205:c41fc65bcfb4 3572 /* Enable the DMA channel */
mbed_official 205:c41fc65bcfb4 3573 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 205:c41fc65bcfb4 3574 }
mbed_official 205:c41fc65bcfb4 3575 break;
mbed_official 205:c41fc65bcfb4 3576 case TIM_DMA_COM:
mbed_official 205:c41fc65bcfb4 3577 {
mbed_official 205:c41fc65bcfb4 3578 /* Set the DMA Period elapsed callback */
mbed_official 205:c41fc65bcfb4 3579 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
mbed_official 205:c41fc65bcfb4 3580
mbed_official 205:c41fc65bcfb4 3581 /* Set the DMA error callback */
mbed_official 205:c41fc65bcfb4 3582 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 205:c41fc65bcfb4 3583
mbed_official 205:c41fc65bcfb4 3584 /* Enable the DMA channel */
mbed_official 205:c41fc65bcfb4 3585 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 205:c41fc65bcfb4 3586 }
mbed_official 205:c41fc65bcfb4 3587 break;
mbed_official 205:c41fc65bcfb4 3588 case TIM_DMA_TRIGGER:
mbed_official 205:c41fc65bcfb4 3589 {
mbed_official 205:c41fc65bcfb4 3590 /* Set the DMA Period elapsed callback */
mbed_official 205:c41fc65bcfb4 3591 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
mbed_official 205:c41fc65bcfb4 3592
mbed_official 205:c41fc65bcfb4 3593 /* Set the DMA error callback */
mbed_official 205:c41fc65bcfb4 3594 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 205:c41fc65bcfb4 3595
mbed_official 205:c41fc65bcfb4 3596 /* Enable the DMA channel */
mbed_official 205:c41fc65bcfb4 3597 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 205:c41fc65bcfb4 3598 }
mbed_official 205:c41fc65bcfb4 3599 break;
mbed_official 205:c41fc65bcfb4 3600 default:
mbed_official 205:c41fc65bcfb4 3601 break;
mbed_official 205:c41fc65bcfb4 3602 }
mbed_official 205:c41fc65bcfb4 3603
mbed_official 205:c41fc65bcfb4 3604 /* configure the DMA Burst Mode */
mbed_official 205:c41fc65bcfb4 3605 htim->Instance->DCR = BurstBaseAddress | BurstLength;
mbed_official 205:c41fc65bcfb4 3606
mbed_official 205:c41fc65bcfb4 3607 /* Enable the TIM DMA Request */
mbed_official 205:c41fc65bcfb4 3608 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
mbed_official 205:c41fc65bcfb4 3609
mbed_official 205:c41fc65bcfb4 3610 htim->State = HAL_TIM_STATE_READY;
mbed_official 205:c41fc65bcfb4 3611
mbed_official 205:c41fc65bcfb4 3612 /* Return function status */
mbed_official 205:c41fc65bcfb4 3613 return HAL_OK;
mbed_official 205:c41fc65bcfb4 3614 }
mbed_official 205:c41fc65bcfb4 3615
mbed_official 205:c41fc65bcfb4 3616 /**
mbed_official 205:c41fc65bcfb4 3617 * @brief Stop the DMA burst reading
mbed_official 205:c41fc65bcfb4 3618 * @param htim: TIM handle
mbed_official 205:c41fc65bcfb4 3619 * @param BurstRequestSrc: TIM DMA Request sources to disable.
mbed_official 205:c41fc65bcfb4 3620 * @retval HAL status
mbed_official 205:c41fc65bcfb4 3621 */
mbed_official 205:c41fc65bcfb4 3622 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
mbed_official 205:c41fc65bcfb4 3623 {
mbed_official 205:c41fc65bcfb4 3624 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 3625 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
mbed_official 205:c41fc65bcfb4 3626
mbed_official 205:c41fc65bcfb4 3627 /* Abort the DMA transfer (at least disable the DMA channel) */
mbed_official 205:c41fc65bcfb4 3628 switch(BurstRequestSrc)
mbed_official 205:c41fc65bcfb4 3629 {
mbed_official 205:c41fc65bcfb4 3630 case TIM_DMA_UPDATE:
mbed_official 205:c41fc65bcfb4 3631 {
mbed_official 205:c41fc65bcfb4 3632 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
mbed_official 205:c41fc65bcfb4 3633 }
mbed_official 205:c41fc65bcfb4 3634 break;
mbed_official 205:c41fc65bcfb4 3635 case TIM_DMA_CC1:
mbed_official 205:c41fc65bcfb4 3636 {
mbed_official 205:c41fc65bcfb4 3637 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
mbed_official 205:c41fc65bcfb4 3638 }
mbed_official 205:c41fc65bcfb4 3639 break;
mbed_official 205:c41fc65bcfb4 3640 case TIM_DMA_CC2:
mbed_official 205:c41fc65bcfb4 3641 {
mbed_official 205:c41fc65bcfb4 3642 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
mbed_official 205:c41fc65bcfb4 3643 }
mbed_official 205:c41fc65bcfb4 3644 break;
mbed_official 205:c41fc65bcfb4 3645 case TIM_DMA_CC3:
mbed_official 205:c41fc65bcfb4 3646 {
mbed_official 205:c41fc65bcfb4 3647 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
mbed_official 205:c41fc65bcfb4 3648 }
mbed_official 205:c41fc65bcfb4 3649 break;
mbed_official 205:c41fc65bcfb4 3650 case TIM_DMA_CC4:
mbed_official 205:c41fc65bcfb4 3651 {
mbed_official 205:c41fc65bcfb4 3652 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
mbed_official 205:c41fc65bcfb4 3653 }
mbed_official 205:c41fc65bcfb4 3654 break;
mbed_official 205:c41fc65bcfb4 3655 case TIM_DMA_COM:
mbed_official 205:c41fc65bcfb4 3656 {
mbed_official 205:c41fc65bcfb4 3657 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
mbed_official 205:c41fc65bcfb4 3658 }
mbed_official 205:c41fc65bcfb4 3659 break;
mbed_official 205:c41fc65bcfb4 3660 case TIM_DMA_TRIGGER:
mbed_official 205:c41fc65bcfb4 3661 {
mbed_official 205:c41fc65bcfb4 3662 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
mbed_official 205:c41fc65bcfb4 3663 }
mbed_official 205:c41fc65bcfb4 3664 break;
mbed_official 205:c41fc65bcfb4 3665 default:
mbed_official 205:c41fc65bcfb4 3666 break;
mbed_official 205:c41fc65bcfb4 3667 }
mbed_official 205:c41fc65bcfb4 3668
mbed_official 205:c41fc65bcfb4 3669 /* Disable the TIM Update DMA request */
mbed_official 205:c41fc65bcfb4 3670 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
mbed_official 205:c41fc65bcfb4 3671
mbed_official 205:c41fc65bcfb4 3672 /* Return function status */
mbed_official 205:c41fc65bcfb4 3673 return HAL_OK;
mbed_official 205:c41fc65bcfb4 3674 }
mbed_official 205:c41fc65bcfb4 3675
mbed_official 205:c41fc65bcfb4 3676 /**
mbed_official 205:c41fc65bcfb4 3677 * @brief Generate a software event
mbed_official 205:c41fc65bcfb4 3678 * @param htim: TIM handle
mbed_official 205:c41fc65bcfb4 3679 * @param EventSource: specifies the event source.
mbed_official 205:c41fc65bcfb4 3680 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 3681 * @arg TIM_EventSource_Update: Timer update Event source
mbed_official 205:c41fc65bcfb4 3682 * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
mbed_official 205:c41fc65bcfb4 3683 * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
mbed_official 205:c41fc65bcfb4 3684 * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
mbed_official 205:c41fc65bcfb4 3685 * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
mbed_official 205:c41fc65bcfb4 3686 * @arg TIM_EventSource_COM: Timer COM event source
mbed_official 205:c41fc65bcfb4 3687 * @arg TIM_EventSource_Trigger: Timer Trigger Event source
mbed_official 205:c41fc65bcfb4 3688 * @arg TIM_EventSource_Break: Timer Break event source
mbed_official 205:c41fc65bcfb4 3689 * @note TBC can only generate an update event.
mbed_official 205:c41fc65bcfb4 3690 * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TBC.
mbed_official 205:c41fc65bcfb4 3691 * @retval HAL status
mbed_official 205:c41fc65bcfb4 3692 */
mbed_official 205:c41fc65bcfb4 3693
mbed_official 205:c41fc65bcfb4 3694 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
mbed_official 205:c41fc65bcfb4 3695 {
mbed_official 205:c41fc65bcfb4 3696 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 3697 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 3698 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
mbed_official 205:c41fc65bcfb4 3699
mbed_official 205:c41fc65bcfb4 3700 /* Process Locked */
mbed_official 205:c41fc65bcfb4 3701 __HAL_LOCK(htim);
mbed_official 205:c41fc65bcfb4 3702
mbed_official 205:c41fc65bcfb4 3703 /* Change the TIM state */
mbed_official 205:c41fc65bcfb4 3704 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 205:c41fc65bcfb4 3705
mbed_official 205:c41fc65bcfb4 3706 /* Set the event sources */
mbed_official 205:c41fc65bcfb4 3707 htim->Instance->EGR = EventSource;
mbed_official 205:c41fc65bcfb4 3708
mbed_official 205:c41fc65bcfb4 3709 /* Change the TIM state */
mbed_official 205:c41fc65bcfb4 3710 htim->State = HAL_TIM_STATE_READY;
mbed_official 205:c41fc65bcfb4 3711
mbed_official 205:c41fc65bcfb4 3712 __HAL_UNLOCK(htim);
mbed_official 205:c41fc65bcfb4 3713
mbed_official 205:c41fc65bcfb4 3714 /* Return function status */
mbed_official 205:c41fc65bcfb4 3715 return HAL_OK;
mbed_official 205:c41fc65bcfb4 3716 }
mbed_official 205:c41fc65bcfb4 3717
mbed_official 205:c41fc65bcfb4 3718 /**
mbed_official 205:c41fc65bcfb4 3719 * @brief Configures the OCRef clear feature
mbed_official 205:c41fc65bcfb4 3720 * @param htim: TIM handle
mbed_official 205:c41fc65bcfb4 3721 * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
mbed_official 205:c41fc65bcfb4 3722 * contains the OCREF clear feature and parameters for the TIM peripheral.
mbed_official 205:c41fc65bcfb4 3723 * @param Channel: specifies the TIM Channel
mbed_official 205:c41fc65bcfb4 3724 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 3725 * @arg TIM_Channel_1: TIM Channel 1
mbed_official 205:c41fc65bcfb4 3726 * @arg TIM_Channel_2: TIM Channel 2
mbed_official 205:c41fc65bcfb4 3727 * @arg TIM_Channel_3: TIM Channel 3
mbed_official 205:c41fc65bcfb4 3728 * @arg TIM_Channel_4: TIM Channel 4
mbed_official 205:c41fc65bcfb4 3729 * @retval HAL status
mbed_official 205:c41fc65bcfb4 3730 */
mbed_official 205:c41fc65bcfb4 3731 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
mbed_official 205:c41fc65bcfb4 3732 {
mbed_official 205:c41fc65bcfb4 3733 uint32_t tmpsmcr = 0;
mbed_official 205:c41fc65bcfb4 3734
mbed_official 205:c41fc65bcfb4 3735 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 3736 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 3737 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
mbed_official 205:c41fc65bcfb4 3738 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
mbed_official 205:c41fc65bcfb4 3739 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
mbed_official 205:c41fc65bcfb4 3740 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
mbed_official 205:c41fc65bcfb4 3741
mbed_official 205:c41fc65bcfb4 3742 /* Process Locked */
mbed_official 205:c41fc65bcfb4 3743 __HAL_LOCK(htim);
mbed_official 205:c41fc65bcfb4 3744
mbed_official 205:c41fc65bcfb4 3745 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 205:c41fc65bcfb4 3746
mbed_official 205:c41fc65bcfb4 3747 switch (sClearInputConfig->ClearInputSource)
mbed_official 205:c41fc65bcfb4 3748 {
mbed_official 205:c41fc65bcfb4 3749 case TIM_CLEARINPUTSOURCE_NONE:
mbed_official 205:c41fc65bcfb4 3750 {
mbed_official 205:c41fc65bcfb4 3751 /* Clear the OCREF clear selection bit */
mbed_official 205:c41fc65bcfb4 3752 tmpsmcr &= (uint16_t)(~TIM_SMCR_OCCS);
mbed_official 205:c41fc65bcfb4 3753
mbed_official 205:c41fc65bcfb4 3754 /* Clear the ETR Bits */
mbed_official 205:c41fc65bcfb4 3755 tmpsmcr &= (uint16_t)(~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
mbed_official 205:c41fc65bcfb4 3756
mbed_official 205:c41fc65bcfb4 3757 /* Set TIMx_SMCR */
mbed_official 205:c41fc65bcfb4 3758 htim->Instance->SMCR = tmpsmcr;
mbed_official 205:c41fc65bcfb4 3759 }
mbed_official 205:c41fc65bcfb4 3760 break;
mbed_official 205:c41fc65bcfb4 3761
mbed_official 205:c41fc65bcfb4 3762 case TIM_CLEARINPUTSOURCE_ETR:
mbed_official 205:c41fc65bcfb4 3763 {
mbed_official 205:c41fc65bcfb4 3764 TIM_ETR_SetConfig(htim->Instance,
mbed_official 205:c41fc65bcfb4 3765 sClearInputConfig->ClearInputPrescaler,
mbed_official 205:c41fc65bcfb4 3766 sClearInputConfig->ClearInputPolarity,
mbed_official 205:c41fc65bcfb4 3767 sClearInputConfig->ClearInputFilter);
mbed_official 205:c41fc65bcfb4 3768
mbed_official 205:c41fc65bcfb4 3769 /* Set the OCREF clear selection bit */
mbed_official 205:c41fc65bcfb4 3770 htim->Instance->SMCR |= TIM_SMCR_OCCS;
mbed_official 205:c41fc65bcfb4 3771 }
mbed_official 205:c41fc65bcfb4 3772 break;
mbed_official 205:c41fc65bcfb4 3773 }
mbed_official 205:c41fc65bcfb4 3774
mbed_official 205:c41fc65bcfb4 3775 switch (Channel)
mbed_official 205:c41fc65bcfb4 3776 {
mbed_official 205:c41fc65bcfb4 3777 case TIM_CHANNEL_1:
mbed_official 205:c41fc65bcfb4 3778 {
mbed_official 205:c41fc65bcfb4 3779 if(sClearInputConfig->ClearInputState != RESET)
mbed_official 205:c41fc65bcfb4 3780 {
mbed_official 205:c41fc65bcfb4 3781 /* Enable the Ocref clear feature for Channel 1 */
mbed_official 205:c41fc65bcfb4 3782 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
mbed_official 205:c41fc65bcfb4 3783 }
mbed_official 205:c41fc65bcfb4 3784 else
mbed_official 205:c41fc65bcfb4 3785 {
mbed_official 205:c41fc65bcfb4 3786 /* Disable the Ocref clear feature for Channel 1 */
mbed_official 205:c41fc65bcfb4 3787 htim->Instance->CCMR1 &= (uint16_t)(~TIM_CCMR1_OC1CE);
mbed_official 205:c41fc65bcfb4 3788 }
mbed_official 205:c41fc65bcfb4 3789 }
mbed_official 205:c41fc65bcfb4 3790 break;
mbed_official 205:c41fc65bcfb4 3791 case TIM_CHANNEL_2:
mbed_official 205:c41fc65bcfb4 3792 {
mbed_official 205:c41fc65bcfb4 3793 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 3794 if(sClearInputConfig->ClearInputState != RESET)
mbed_official 205:c41fc65bcfb4 3795 {
mbed_official 205:c41fc65bcfb4 3796 /* Enable the Ocref clear feature for Channel 1 */
mbed_official 205:c41fc65bcfb4 3797 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
mbed_official 205:c41fc65bcfb4 3798 }
mbed_official 205:c41fc65bcfb4 3799 else
mbed_official 205:c41fc65bcfb4 3800 {
mbed_official 205:c41fc65bcfb4 3801 /* Disable the Ocref clear feature for Channel 1 */
mbed_official 205:c41fc65bcfb4 3802 htim->Instance->CCMR1 &= (uint16_t)(~TIM_CCMR1_OC2CE);
mbed_official 205:c41fc65bcfb4 3803 }
mbed_official 205:c41fc65bcfb4 3804 }
mbed_official 205:c41fc65bcfb4 3805 break;
mbed_official 205:c41fc65bcfb4 3806 case TIM_CHANNEL_3:
mbed_official 205:c41fc65bcfb4 3807 {
mbed_official 205:c41fc65bcfb4 3808 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 3809 if(sClearInputConfig->ClearInputState != RESET)
mbed_official 205:c41fc65bcfb4 3810 {
mbed_official 205:c41fc65bcfb4 3811 /* Enable the Ocref clear feature for Channel 1 */
mbed_official 205:c41fc65bcfb4 3812 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
mbed_official 205:c41fc65bcfb4 3813 }
mbed_official 205:c41fc65bcfb4 3814 else
mbed_official 205:c41fc65bcfb4 3815 {
mbed_official 205:c41fc65bcfb4 3816 /* Disable the Ocref clear feature for Channel 1 */
mbed_official 205:c41fc65bcfb4 3817 htim->Instance->CCMR2 &= (uint16_t)(~TIM_CCMR2_OC3CE);
mbed_official 205:c41fc65bcfb4 3818 }
mbed_official 205:c41fc65bcfb4 3819 }
mbed_official 205:c41fc65bcfb4 3820 break;
mbed_official 205:c41fc65bcfb4 3821 case TIM_CHANNEL_4:
mbed_official 205:c41fc65bcfb4 3822 {
mbed_official 205:c41fc65bcfb4 3823 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 3824 if(sClearInputConfig->ClearInputState != RESET)
mbed_official 205:c41fc65bcfb4 3825 {
mbed_official 205:c41fc65bcfb4 3826 /* Enable the Ocref clear feature for Channel 1 */
mbed_official 205:c41fc65bcfb4 3827 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
mbed_official 205:c41fc65bcfb4 3828 }
mbed_official 205:c41fc65bcfb4 3829 else
mbed_official 205:c41fc65bcfb4 3830 {
mbed_official 205:c41fc65bcfb4 3831 /* Disable the Ocref clear feature for Channel 1 */
mbed_official 205:c41fc65bcfb4 3832 htim->Instance->CCMR2 &= (uint16_t)(~TIM_CCMR2_OC4CE);
mbed_official 205:c41fc65bcfb4 3833 }
mbed_official 205:c41fc65bcfb4 3834 }
mbed_official 205:c41fc65bcfb4 3835 break;
mbed_official 205:c41fc65bcfb4 3836 default:
mbed_official 205:c41fc65bcfb4 3837 break;
mbed_official 205:c41fc65bcfb4 3838 }
mbed_official 205:c41fc65bcfb4 3839
mbed_official 205:c41fc65bcfb4 3840 htim->State = HAL_TIM_STATE_READY;
mbed_official 205:c41fc65bcfb4 3841
mbed_official 205:c41fc65bcfb4 3842 __HAL_UNLOCK(htim);
mbed_official 205:c41fc65bcfb4 3843
mbed_official 205:c41fc65bcfb4 3844 return HAL_OK;
mbed_official 205:c41fc65bcfb4 3845 }
mbed_official 205:c41fc65bcfb4 3846
mbed_official 205:c41fc65bcfb4 3847 /**
mbed_official 205:c41fc65bcfb4 3848 * @brief Configures the clock source to be used
mbed_official 205:c41fc65bcfb4 3849 * @param htim: TIM handle
mbed_official 205:c41fc65bcfb4 3850 * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
mbed_official 205:c41fc65bcfb4 3851 * contains the clock source information for the TIM peripheral.
mbed_official 205:c41fc65bcfb4 3852 * @retval HAL status
mbed_official 205:c41fc65bcfb4 3853 */
mbed_official 205:c41fc65bcfb4 3854 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
mbed_official 205:c41fc65bcfb4 3855 {
mbed_official 205:c41fc65bcfb4 3856 uint32_t tmpsmcr = 0;
mbed_official 205:c41fc65bcfb4 3857
mbed_official 205:c41fc65bcfb4 3858 /* Process Locked */
mbed_official 205:c41fc65bcfb4 3859 __HAL_LOCK(htim);
mbed_official 205:c41fc65bcfb4 3860
mbed_official 205:c41fc65bcfb4 3861 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 205:c41fc65bcfb4 3862
mbed_official 205:c41fc65bcfb4 3863 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 3864 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
mbed_official 205:c41fc65bcfb4 3865 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
mbed_official 205:c41fc65bcfb4 3866 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
mbed_official 205:c41fc65bcfb4 3867 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
mbed_official 205:c41fc65bcfb4 3868
mbed_official 205:c41fc65bcfb4 3869 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
mbed_official 205:c41fc65bcfb4 3870 tmpsmcr = htim->Instance->SMCR;
mbed_official 205:c41fc65bcfb4 3871 tmpsmcr &= (uint16_t)(~(TIM_SMCR_SMS | TIM_SMCR_TS));
mbed_official 205:c41fc65bcfb4 3872 tmpsmcr &= (uint16_t)(~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
mbed_official 205:c41fc65bcfb4 3873 htim->Instance->SMCR = tmpsmcr;
mbed_official 205:c41fc65bcfb4 3874
mbed_official 205:c41fc65bcfb4 3875 switch (sClockSourceConfig->ClockSource)
mbed_official 205:c41fc65bcfb4 3876 {
mbed_official 205:c41fc65bcfb4 3877 case TIM_CLOCKSOURCE_INTERNAL:
mbed_official 205:c41fc65bcfb4 3878 {
mbed_official 205:c41fc65bcfb4 3879 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 3880 /* Disable slave mode to clock the prescaler directly with the internal clock */
mbed_official 205:c41fc65bcfb4 3881 htim->Instance->SMCR &= (uint16_t)(~TIM_SMCR_SMS);
mbed_official 205:c41fc65bcfb4 3882 }
mbed_official 205:c41fc65bcfb4 3883 break;
mbed_official 205:c41fc65bcfb4 3884
mbed_official 205:c41fc65bcfb4 3885 case TIM_CLOCKSOURCE_ETRMODE1:
mbed_official 205:c41fc65bcfb4 3886 {
mbed_official 205:c41fc65bcfb4 3887 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
mbed_official 205:c41fc65bcfb4 3888 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 3889
mbed_official 205:c41fc65bcfb4 3890 /* Configure the ETR Clock source */
mbed_official 205:c41fc65bcfb4 3891 TIM_ETR_SetConfig(htim->Instance,
mbed_official 205:c41fc65bcfb4 3892 sClockSourceConfig->ClockPrescaler,
mbed_official 205:c41fc65bcfb4 3893 sClockSourceConfig->ClockPolarity,
mbed_official 205:c41fc65bcfb4 3894 sClockSourceConfig->ClockFilter);
mbed_official 205:c41fc65bcfb4 3895 /* Get the TIMx SMCR register value */
mbed_official 205:c41fc65bcfb4 3896 tmpsmcr = htim->Instance->SMCR;
mbed_official 205:c41fc65bcfb4 3897 /* Reset the SMS and TS Bits */
mbed_official 205:c41fc65bcfb4 3898 tmpsmcr &= (uint16_t)(~(TIM_SMCR_SMS | TIM_SMCR_TS));
mbed_official 205:c41fc65bcfb4 3899 /* Select the External clock mode1 and the ETRF trigger */
mbed_official 205:c41fc65bcfb4 3900 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
mbed_official 205:c41fc65bcfb4 3901 /* Write to TIMx SMCR */
mbed_official 205:c41fc65bcfb4 3902 htim->Instance->SMCR = tmpsmcr;
mbed_official 205:c41fc65bcfb4 3903 }
mbed_official 205:c41fc65bcfb4 3904 break;
mbed_official 205:c41fc65bcfb4 3905
mbed_official 205:c41fc65bcfb4 3906 case TIM_CLOCKSOURCE_ETRMODE2:
mbed_official 205:c41fc65bcfb4 3907 {
mbed_official 205:c41fc65bcfb4 3908 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
mbed_official 205:c41fc65bcfb4 3909 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 3910
mbed_official 205:c41fc65bcfb4 3911 /* Configure the ETR Clock source */
mbed_official 205:c41fc65bcfb4 3912 TIM_ETR_SetConfig(htim->Instance,
mbed_official 205:c41fc65bcfb4 3913 sClockSourceConfig->ClockPrescaler,
mbed_official 205:c41fc65bcfb4 3914 sClockSourceConfig->ClockPolarity,
mbed_official 205:c41fc65bcfb4 3915 sClockSourceConfig->ClockFilter);
mbed_official 205:c41fc65bcfb4 3916 /* Enable the External clock mode2 */
mbed_official 205:c41fc65bcfb4 3917 htim->Instance->SMCR |= TIM_SMCR_ECE;
mbed_official 205:c41fc65bcfb4 3918 }
mbed_official 205:c41fc65bcfb4 3919 break;
mbed_official 205:c41fc65bcfb4 3920
mbed_official 205:c41fc65bcfb4 3921 case TIM_CLOCKSOURCE_TI1:
mbed_official 205:c41fc65bcfb4 3922 {
mbed_official 205:c41fc65bcfb4 3923 /* Check whether or not the timer instance supports external clock mode 1 */
mbed_official 205:c41fc65bcfb4 3924 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 3925
mbed_official 205:c41fc65bcfb4 3926 TIM_TI1_ConfigInputStage(htim->Instance,
mbed_official 205:c41fc65bcfb4 3927 sClockSourceConfig->ClockPolarity,
mbed_official 205:c41fc65bcfb4 3928 sClockSourceConfig->ClockFilter);
mbed_official 205:c41fc65bcfb4 3929 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
mbed_official 205:c41fc65bcfb4 3930 }
mbed_official 205:c41fc65bcfb4 3931 break;
mbed_official 205:c41fc65bcfb4 3932 case TIM_CLOCKSOURCE_TI2:
mbed_official 205:c41fc65bcfb4 3933 {
mbed_official 205:c41fc65bcfb4 3934 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
mbed_official 205:c41fc65bcfb4 3935 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 3936
mbed_official 205:c41fc65bcfb4 3937 TIM_TI2_ConfigInputStage(htim->Instance,
mbed_official 205:c41fc65bcfb4 3938 sClockSourceConfig->ClockPolarity,
mbed_official 205:c41fc65bcfb4 3939 sClockSourceConfig->ClockFilter);
mbed_official 205:c41fc65bcfb4 3940 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
mbed_official 205:c41fc65bcfb4 3941 }
mbed_official 205:c41fc65bcfb4 3942 break;
mbed_official 205:c41fc65bcfb4 3943 case TIM_CLOCKSOURCE_TI1ED:
mbed_official 205:c41fc65bcfb4 3944 {
mbed_official 205:c41fc65bcfb4 3945 /* Check whether or not the timer instance supports external clock mode 1 */
mbed_official 205:c41fc65bcfb4 3946 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 3947
mbed_official 205:c41fc65bcfb4 3948 TIM_TI1_ConfigInputStage(htim->Instance,
mbed_official 205:c41fc65bcfb4 3949 sClockSourceConfig->ClockPolarity,
mbed_official 205:c41fc65bcfb4 3950 sClockSourceConfig->ClockFilter);
mbed_official 205:c41fc65bcfb4 3951 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
mbed_official 205:c41fc65bcfb4 3952 }
mbed_official 205:c41fc65bcfb4 3953 break;
mbed_official 205:c41fc65bcfb4 3954 case TIM_CLOCKSOURCE_ITR0:
mbed_official 205:c41fc65bcfb4 3955 {
mbed_official 205:c41fc65bcfb4 3956 /* Check whether or not the timer instance supports external clock mode 1 */
mbed_official 205:c41fc65bcfb4 3957 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 3958
mbed_official 205:c41fc65bcfb4 3959 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
mbed_official 205:c41fc65bcfb4 3960 }
mbed_official 205:c41fc65bcfb4 3961 break;
mbed_official 205:c41fc65bcfb4 3962 case TIM_CLOCKSOURCE_ITR1:
mbed_official 205:c41fc65bcfb4 3963 {
mbed_official 205:c41fc65bcfb4 3964 /* Check whether or not the timer instance supports external clock mode 1 */
mbed_official 205:c41fc65bcfb4 3965 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 3966
mbed_official 205:c41fc65bcfb4 3967 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
mbed_official 205:c41fc65bcfb4 3968 }
mbed_official 205:c41fc65bcfb4 3969 break;
mbed_official 205:c41fc65bcfb4 3970 case TIM_CLOCKSOURCE_ITR2:
mbed_official 205:c41fc65bcfb4 3971 {
mbed_official 205:c41fc65bcfb4 3972 /* Check whether or not the timer instance supports external clock mode 1 */
mbed_official 205:c41fc65bcfb4 3973 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 3974
mbed_official 205:c41fc65bcfb4 3975 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
mbed_official 205:c41fc65bcfb4 3976 }
mbed_official 205:c41fc65bcfb4 3977 break;
mbed_official 205:c41fc65bcfb4 3978 case TIM_CLOCKSOURCE_ITR3:
mbed_official 205:c41fc65bcfb4 3979 {
mbed_official 205:c41fc65bcfb4 3980 /* Check whether or not the timer instance supports external clock mode 1 */
mbed_official 205:c41fc65bcfb4 3981 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 3982
mbed_official 205:c41fc65bcfb4 3983 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
mbed_official 205:c41fc65bcfb4 3984 }
mbed_official 205:c41fc65bcfb4 3985 break;
mbed_official 205:c41fc65bcfb4 3986
mbed_official 205:c41fc65bcfb4 3987 default:
mbed_official 205:c41fc65bcfb4 3988 break;
mbed_official 205:c41fc65bcfb4 3989 }
mbed_official 205:c41fc65bcfb4 3990 htim->State = HAL_TIM_STATE_READY;
mbed_official 205:c41fc65bcfb4 3991
mbed_official 205:c41fc65bcfb4 3992 __HAL_UNLOCK(htim);
mbed_official 205:c41fc65bcfb4 3993
mbed_official 205:c41fc65bcfb4 3994 return HAL_OK;
mbed_official 205:c41fc65bcfb4 3995 }
mbed_official 205:c41fc65bcfb4 3996
mbed_official 205:c41fc65bcfb4 3997 /**
mbed_official 205:c41fc65bcfb4 3998 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
mbed_official 205:c41fc65bcfb4 3999 * or a XOR combination between CH1_input, CH2_input & CH3_input
mbed_official 205:c41fc65bcfb4 4000 * @param htim: TIM handle.
mbed_official 205:c41fc65bcfb4 4001 * @param TI1_Selection: Indicate whether or not channel 1 is connected to the
mbed_official 205:c41fc65bcfb4 4002 * output of a XOR gate.
mbed_official 205:c41fc65bcfb4 4003 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 4004 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
mbed_official 205:c41fc65bcfb4 4005 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
mbed_official 205:c41fc65bcfb4 4006 * pins are connected to the TI1 input (XOR combination)
mbed_official 205:c41fc65bcfb4 4007 * @retval HAL status
mbed_official 205:c41fc65bcfb4 4008 */
mbed_official 205:c41fc65bcfb4 4009 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
mbed_official 205:c41fc65bcfb4 4010 {
mbed_official 205:c41fc65bcfb4 4011 uint32_t tmpcr2 = 0;
mbed_official 205:c41fc65bcfb4 4012
mbed_official 205:c41fc65bcfb4 4013 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 4014 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 4015 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
mbed_official 205:c41fc65bcfb4 4016
mbed_official 205:c41fc65bcfb4 4017 /* Get the TIMx CR2 register value */
mbed_official 205:c41fc65bcfb4 4018 tmpcr2 = htim->Instance->CR2;
mbed_official 205:c41fc65bcfb4 4019
mbed_official 205:c41fc65bcfb4 4020 /* Reset the TI1 selection */
mbed_official 205:c41fc65bcfb4 4021 tmpcr2 &= (uint16_t)(~TIM_CR2_TI1S);
mbed_official 205:c41fc65bcfb4 4022
mbed_official 205:c41fc65bcfb4 4023 /* Set the the TI1 selection */
mbed_official 205:c41fc65bcfb4 4024 tmpcr2 |= TI1_Selection;
mbed_official 205:c41fc65bcfb4 4025
mbed_official 205:c41fc65bcfb4 4026 /* Write to TIMxCR2 */
mbed_official 205:c41fc65bcfb4 4027 htim->Instance->CR2 = tmpcr2;
mbed_official 205:c41fc65bcfb4 4028
mbed_official 205:c41fc65bcfb4 4029 return HAL_OK;
mbed_official 205:c41fc65bcfb4 4030 }
mbed_official 205:c41fc65bcfb4 4031
mbed_official 205:c41fc65bcfb4 4032 /**
mbed_official 205:c41fc65bcfb4 4033 * @brief Configures the TIM in Slave mode
mbed_official 205:c41fc65bcfb4 4034 * @param htim: TIM handle.
mbed_official 205:c41fc65bcfb4 4035 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
mbed_official 205:c41fc65bcfb4 4036 * contains the selected trigger (internal trigger input, filtered
mbed_official 205:c41fc65bcfb4 4037 * timer input or external trigger input) and the ) and the Slave
mbed_official 205:c41fc65bcfb4 4038 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
mbed_official 205:c41fc65bcfb4 4039 * @retval HAL status
mbed_official 205:c41fc65bcfb4 4040 */
mbed_official 205:c41fc65bcfb4 4041 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
mbed_official 205:c41fc65bcfb4 4042 {
mbed_official 205:c41fc65bcfb4 4043 uint32_t tmpsmcr = 0;
mbed_official 205:c41fc65bcfb4 4044 uint32_t tmpccmr1 = 0;
mbed_official 205:c41fc65bcfb4 4045 uint32_t tmpccer = 0;
mbed_official 205:c41fc65bcfb4 4046
mbed_official 205:c41fc65bcfb4 4047 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 4048 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 4049 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
mbed_official 205:c41fc65bcfb4 4050 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
mbed_official 205:c41fc65bcfb4 4051
mbed_official 205:c41fc65bcfb4 4052 __HAL_LOCK(htim);
mbed_official 205:c41fc65bcfb4 4053
mbed_official 205:c41fc65bcfb4 4054 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 205:c41fc65bcfb4 4055
mbed_official 205:c41fc65bcfb4 4056 /* Get the TIMx SMCR register value */
mbed_official 205:c41fc65bcfb4 4057 tmpsmcr = htim->Instance->SMCR;
mbed_official 205:c41fc65bcfb4 4058
mbed_official 205:c41fc65bcfb4 4059 /* Reset the Trigger Selection Bits */
mbed_official 205:c41fc65bcfb4 4060 tmpsmcr &= (uint16_t)(~TIM_SMCR_TS);
mbed_official 205:c41fc65bcfb4 4061 /* Set the Input Trigger source */
mbed_official 205:c41fc65bcfb4 4062 tmpsmcr |= sSlaveConfig->InputTrigger;
mbed_official 205:c41fc65bcfb4 4063
mbed_official 205:c41fc65bcfb4 4064 /* Reset the slave mode Bits */
mbed_official 205:c41fc65bcfb4 4065 tmpsmcr &= (uint16_t)(~TIM_SMCR_SMS);
mbed_official 205:c41fc65bcfb4 4066 /* Set the slave mode */
mbed_official 205:c41fc65bcfb4 4067 tmpsmcr |= sSlaveConfig->SlaveMode;
mbed_official 205:c41fc65bcfb4 4068
mbed_official 205:c41fc65bcfb4 4069 /* Write to TIMx SMCR */
mbed_official 205:c41fc65bcfb4 4070 htim->Instance->SMCR = tmpsmcr;
mbed_official 205:c41fc65bcfb4 4071
mbed_official 205:c41fc65bcfb4 4072 /* Configure the trigger prescaler, filter, and polarity */
mbed_official 205:c41fc65bcfb4 4073 switch (sSlaveConfig->InputTrigger)
mbed_official 205:c41fc65bcfb4 4074 {
mbed_official 205:c41fc65bcfb4 4075 case TIM_TS_ETRF:
mbed_official 205:c41fc65bcfb4 4076 {
mbed_official 205:c41fc65bcfb4 4077 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 4078 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 4079 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
mbed_official 205:c41fc65bcfb4 4080 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
mbed_official 205:c41fc65bcfb4 4081 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
mbed_official 205:c41fc65bcfb4 4082 /* Configure the ETR Trigger source */
mbed_official 205:c41fc65bcfb4 4083 TIM_ETR_SetConfig(htim->Instance,
mbed_official 205:c41fc65bcfb4 4084 sSlaveConfig->TriggerPrescaler,
mbed_official 205:c41fc65bcfb4 4085 sSlaveConfig->TriggerPolarity,
mbed_official 205:c41fc65bcfb4 4086 sSlaveConfig->TriggerFilter);
mbed_official 205:c41fc65bcfb4 4087 }
mbed_official 205:c41fc65bcfb4 4088 break;
mbed_official 205:c41fc65bcfb4 4089
mbed_official 205:c41fc65bcfb4 4090 case TIM_TS_TI1F_ED:
mbed_official 205:c41fc65bcfb4 4091 {
mbed_official 205:c41fc65bcfb4 4092 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 4093 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 4094 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
mbed_official 205:c41fc65bcfb4 4095 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
mbed_official 205:c41fc65bcfb4 4096
mbed_official 205:c41fc65bcfb4 4097 /* Disable the Channel 1: Reset the CC1E Bit */
mbed_official 205:c41fc65bcfb4 4098 tmpccer = htim->Instance->CCER;
mbed_official 205:c41fc65bcfb4 4099 htim->Instance->CCER &= (uint16_t)(~TIM_CCER_CC1E);
mbed_official 205:c41fc65bcfb4 4100 tmpccmr1 = htim->Instance->CCMR1;
mbed_official 205:c41fc65bcfb4 4101
mbed_official 205:c41fc65bcfb4 4102 /* Set the filter */
mbed_official 205:c41fc65bcfb4 4103 tmpccmr1 &= (uint16_t)(~TIM_CCMR1_IC1F);
mbed_official 205:c41fc65bcfb4 4104 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
mbed_official 205:c41fc65bcfb4 4105
mbed_official 205:c41fc65bcfb4 4106 /* Write to TIMx CCMR1 and CCER registers */
mbed_official 205:c41fc65bcfb4 4107 htim->Instance->CCMR1 = tmpccmr1;
mbed_official 205:c41fc65bcfb4 4108 htim->Instance->CCER = tmpccer;
mbed_official 205:c41fc65bcfb4 4109
mbed_official 205:c41fc65bcfb4 4110 }
mbed_official 205:c41fc65bcfb4 4111 break;
mbed_official 205:c41fc65bcfb4 4112
mbed_official 205:c41fc65bcfb4 4113 case TIM_TS_TI1FP1:
mbed_official 205:c41fc65bcfb4 4114 {
mbed_official 205:c41fc65bcfb4 4115 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 4116 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 4117 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
mbed_official 205:c41fc65bcfb4 4118 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
mbed_official 205:c41fc65bcfb4 4119
mbed_official 205:c41fc65bcfb4 4120 /* Configure TI1 Filter and Polarity */
mbed_official 205:c41fc65bcfb4 4121 TIM_TI1_ConfigInputStage(htim->Instance,
mbed_official 205:c41fc65bcfb4 4122 sSlaveConfig->TriggerPolarity,
mbed_official 205:c41fc65bcfb4 4123 sSlaveConfig->TriggerFilter);
mbed_official 205:c41fc65bcfb4 4124 }
mbed_official 205:c41fc65bcfb4 4125 break;
mbed_official 205:c41fc65bcfb4 4126
mbed_official 205:c41fc65bcfb4 4127 case TIM_TS_TI2FP2:
mbed_official 205:c41fc65bcfb4 4128 {
mbed_official 205:c41fc65bcfb4 4129 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 4130 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 4131 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
mbed_official 205:c41fc65bcfb4 4132 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
mbed_official 205:c41fc65bcfb4 4133
mbed_official 205:c41fc65bcfb4 4134 /* Configure TI2 Filter and Polarity */
mbed_official 205:c41fc65bcfb4 4135 TIM_TI2_ConfigInputStage(htim->Instance,
mbed_official 205:c41fc65bcfb4 4136 sSlaveConfig->TriggerPolarity,
mbed_official 205:c41fc65bcfb4 4137 sSlaveConfig->TriggerFilter);
mbed_official 205:c41fc65bcfb4 4138 }
mbed_official 205:c41fc65bcfb4 4139 break;
mbed_official 205:c41fc65bcfb4 4140
mbed_official 205:c41fc65bcfb4 4141 case TIM_TS_ITR0:
mbed_official 205:c41fc65bcfb4 4142 {
mbed_official 205:c41fc65bcfb4 4143 /* Check the parameter */
mbed_official 205:c41fc65bcfb4 4144 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 4145 }
mbed_official 205:c41fc65bcfb4 4146 break;
mbed_official 205:c41fc65bcfb4 4147
mbed_official 205:c41fc65bcfb4 4148 case TIM_TS_ITR1:
mbed_official 205:c41fc65bcfb4 4149 {
mbed_official 205:c41fc65bcfb4 4150 /* Check the parameter */
mbed_official 205:c41fc65bcfb4 4151 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 4152 }
mbed_official 205:c41fc65bcfb4 4153 break;
mbed_official 205:c41fc65bcfb4 4154
mbed_official 205:c41fc65bcfb4 4155 case TIM_TS_ITR2:
mbed_official 205:c41fc65bcfb4 4156 {
mbed_official 205:c41fc65bcfb4 4157 /* Check the parameter */
mbed_official 205:c41fc65bcfb4 4158 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 4159 }
mbed_official 205:c41fc65bcfb4 4160 break;
mbed_official 205:c41fc65bcfb4 4161
mbed_official 205:c41fc65bcfb4 4162 case TIM_TS_ITR3:
mbed_official 205:c41fc65bcfb4 4163 {
mbed_official 205:c41fc65bcfb4 4164 /* Check the parameter */
mbed_official 205:c41fc65bcfb4 4165 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 4166 }
mbed_official 205:c41fc65bcfb4 4167 break;
mbed_official 205:c41fc65bcfb4 4168
mbed_official 205:c41fc65bcfb4 4169 default:
mbed_official 205:c41fc65bcfb4 4170 break;
mbed_official 205:c41fc65bcfb4 4171 }
mbed_official 205:c41fc65bcfb4 4172
mbed_official 205:c41fc65bcfb4 4173 htim->State = HAL_TIM_STATE_READY;
mbed_official 205:c41fc65bcfb4 4174
mbed_official 205:c41fc65bcfb4 4175 __HAL_UNLOCK(htim);
mbed_official 205:c41fc65bcfb4 4176
mbed_official 205:c41fc65bcfb4 4177 return HAL_OK;
mbed_official 205:c41fc65bcfb4 4178 }
mbed_official 205:c41fc65bcfb4 4179
mbed_official 205:c41fc65bcfb4 4180 /**
mbed_official 205:c41fc65bcfb4 4181 * @brief Read the captured value from Capture Compare unit
mbed_official 205:c41fc65bcfb4 4182 * @param htim: TIM handle.
mbed_official 205:c41fc65bcfb4 4183 * @param Channel : TIM Channels to be enabled
mbed_official 205:c41fc65bcfb4 4184 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 4185 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 205:c41fc65bcfb4 4186 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 205:c41fc65bcfb4 4187 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 205:c41fc65bcfb4 4188 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 205:c41fc65bcfb4 4189 * @retval Captured value
mbed_official 205:c41fc65bcfb4 4190 */
mbed_official 205:c41fc65bcfb4 4191 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 205:c41fc65bcfb4 4192 {
mbed_official 205:c41fc65bcfb4 4193 uint32_t tmpreg = 0;
mbed_official 205:c41fc65bcfb4 4194
mbed_official 205:c41fc65bcfb4 4195 __HAL_LOCK(htim);
mbed_official 205:c41fc65bcfb4 4196
mbed_official 205:c41fc65bcfb4 4197 switch (Channel)
mbed_official 205:c41fc65bcfb4 4198 {
mbed_official 205:c41fc65bcfb4 4199 case TIM_CHANNEL_1:
mbed_official 205:c41fc65bcfb4 4200 {
mbed_official 205:c41fc65bcfb4 4201 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 4202 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 4203
mbed_official 205:c41fc65bcfb4 4204 /* Return the capture 1 value */
mbed_official 205:c41fc65bcfb4 4205 tmpreg = htim->Instance->CCR1;
mbed_official 205:c41fc65bcfb4 4206
mbed_official 205:c41fc65bcfb4 4207 break;
mbed_official 205:c41fc65bcfb4 4208 }
mbed_official 205:c41fc65bcfb4 4209 case TIM_CHANNEL_2:
mbed_official 205:c41fc65bcfb4 4210 {
mbed_official 205:c41fc65bcfb4 4211 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 4212 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 4213
mbed_official 205:c41fc65bcfb4 4214 /* Return the capture 2 value */
mbed_official 205:c41fc65bcfb4 4215 tmpreg = htim->Instance->CCR2;
mbed_official 205:c41fc65bcfb4 4216
mbed_official 205:c41fc65bcfb4 4217 break;
mbed_official 205:c41fc65bcfb4 4218 }
mbed_official 205:c41fc65bcfb4 4219
mbed_official 205:c41fc65bcfb4 4220 case TIM_CHANNEL_3:
mbed_official 205:c41fc65bcfb4 4221 {
mbed_official 205:c41fc65bcfb4 4222 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 4223 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 4224
mbed_official 205:c41fc65bcfb4 4225 /* Return the capture 3 value */
mbed_official 205:c41fc65bcfb4 4226 tmpreg = htim->Instance->CCR3;
mbed_official 205:c41fc65bcfb4 4227
mbed_official 205:c41fc65bcfb4 4228 break;
mbed_official 205:c41fc65bcfb4 4229 }
mbed_official 205:c41fc65bcfb4 4230
mbed_official 205:c41fc65bcfb4 4231 case TIM_CHANNEL_4:
mbed_official 205:c41fc65bcfb4 4232 {
mbed_official 205:c41fc65bcfb4 4233 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 4234 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official 205:c41fc65bcfb4 4235
mbed_official 205:c41fc65bcfb4 4236 /* Return the capture 4 value */
mbed_official 205:c41fc65bcfb4 4237 tmpreg = htim->Instance->CCR4;
mbed_official 205:c41fc65bcfb4 4238
mbed_official 205:c41fc65bcfb4 4239 break;
mbed_official 205:c41fc65bcfb4 4240 }
mbed_official 205:c41fc65bcfb4 4241
mbed_official 205:c41fc65bcfb4 4242 default:
mbed_official 205:c41fc65bcfb4 4243 break;
mbed_official 205:c41fc65bcfb4 4244 }
mbed_official 205:c41fc65bcfb4 4245
mbed_official 205:c41fc65bcfb4 4246 __HAL_UNLOCK(htim);
mbed_official 205:c41fc65bcfb4 4247 return tmpreg;
mbed_official 205:c41fc65bcfb4 4248 }
mbed_official 205:c41fc65bcfb4 4249
mbed_official 205:c41fc65bcfb4 4250 /**
mbed_official 205:c41fc65bcfb4 4251 * @}
mbed_official 205:c41fc65bcfb4 4252 */
mbed_official 205:c41fc65bcfb4 4253
mbed_official 205:c41fc65bcfb4 4254 /** @defgroup TIM_Group9 TIM Callbacks functions
mbed_official 205:c41fc65bcfb4 4255 * @brief TIM Callbacks functions
mbed_official 205:c41fc65bcfb4 4256 *
mbed_official 205:c41fc65bcfb4 4257 @verbatim
mbed_official 205:c41fc65bcfb4 4258 ==============================================================================
mbed_official 205:c41fc65bcfb4 4259 ##### TIM Callbacks functions #####
mbed_official 205:c41fc65bcfb4 4260 ==============================================================================
mbed_official 205:c41fc65bcfb4 4261 [..]
mbed_official 205:c41fc65bcfb4 4262 This section provides TIM callback functions:
mbed_official 205:c41fc65bcfb4 4263 (+) Timer Period elapsed callback
mbed_official 205:c41fc65bcfb4 4264 (+) Timer Output Compare callback
mbed_official 205:c41fc65bcfb4 4265 (+) Timer Input capture callback
mbed_official 205:c41fc65bcfb4 4266 (+) Timer Trigger callback
mbed_official 205:c41fc65bcfb4 4267 (+) Timer Error callback
mbed_official 205:c41fc65bcfb4 4268
mbed_official 205:c41fc65bcfb4 4269 @endverbatim
mbed_official 205:c41fc65bcfb4 4270 * @{
mbed_official 205:c41fc65bcfb4 4271 */
mbed_official 205:c41fc65bcfb4 4272
mbed_official 205:c41fc65bcfb4 4273 /**
mbed_official 205:c41fc65bcfb4 4274 * @brief Period elapsed callback in non blocking mode
mbed_official 205:c41fc65bcfb4 4275 * @param htim : TIM handle
mbed_official 205:c41fc65bcfb4 4276 * @retval None
mbed_official 205:c41fc65bcfb4 4277 */
mbed_official 205:c41fc65bcfb4 4278 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 4279 {
mbed_official 205:c41fc65bcfb4 4280 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 205:c41fc65bcfb4 4281 the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
mbed_official 205:c41fc65bcfb4 4282 */
mbed_official 205:c41fc65bcfb4 4283
mbed_official 205:c41fc65bcfb4 4284 }
mbed_official 205:c41fc65bcfb4 4285 /**
mbed_official 205:c41fc65bcfb4 4286 * @brief Output Compare callback in non blocking mode
mbed_official 205:c41fc65bcfb4 4287 * @param htim : TIM OC handle
mbed_official 205:c41fc65bcfb4 4288 * @retval None
mbed_official 205:c41fc65bcfb4 4289 */
mbed_official 205:c41fc65bcfb4 4290 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 4291 {
mbed_official 205:c41fc65bcfb4 4292 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 205:c41fc65bcfb4 4293 the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
mbed_official 205:c41fc65bcfb4 4294 */
mbed_official 205:c41fc65bcfb4 4295 }
mbed_official 205:c41fc65bcfb4 4296 /**
mbed_official 205:c41fc65bcfb4 4297 * @brief Input Capture callback in non blocking mode
mbed_official 205:c41fc65bcfb4 4298 * @param htim : TIM IC handle
mbed_official 205:c41fc65bcfb4 4299 * @retval None
mbed_official 205:c41fc65bcfb4 4300 */
mbed_official 205:c41fc65bcfb4 4301 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 4302 {
mbed_official 205:c41fc65bcfb4 4303 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 205:c41fc65bcfb4 4304 the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
mbed_official 205:c41fc65bcfb4 4305 */
mbed_official 205:c41fc65bcfb4 4306 }
mbed_official 205:c41fc65bcfb4 4307
mbed_official 205:c41fc65bcfb4 4308 /**
mbed_official 205:c41fc65bcfb4 4309 * @brief PWM Pulse finished callback in non blocking mode
mbed_official 205:c41fc65bcfb4 4310 * @param htim : TIM handle
mbed_official 205:c41fc65bcfb4 4311 * @retval None
mbed_official 205:c41fc65bcfb4 4312 */
mbed_official 205:c41fc65bcfb4 4313 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 4314 {
mbed_official 205:c41fc65bcfb4 4315 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 205:c41fc65bcfb4 4316 the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
mbed_official 205:c41fc65bcfb4 4317 */
mbed_official 205:c41fc65bcfb4 4318 }
mbed_official 205:c41fc65bcfb4 4319
mbed_official 205:c41fc65bcfb4 4320 /**
mbed_official 205:c41fc65bcfb4 4321 * @brief Hall Trigger detection callback in non blocking mode
mbed_official 205:c41fc65bcfb4 4322 * @param htim : TIM handle
mbed_official 205:c41fc65bcfb4 4323 * @retval None
mbed_official 205:c41fc65bcfb4 4324 */
mbed_official 205:c41fc65bcfb4 4325 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 4326 {
mbed_official 205:c41fc65bcfb4 4327 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 205:c41fc65bcfb4 4328 the HAL_TIM_TriggerCallback could be implemented in the user file
mbed_official 205:c41fc65bcfb4 4329 */
mbed_official 205:c41fc65bcfb4 4330 }
mbed_official 205:c41fc65bcfb4 4331
mbed_official 205:c41fc65bcfb4 4332 /**
mbed_official 205:c41fc65bcfb4 4333 * @brief Timer error callback in non blocking mode
mbed_official 205:c41fc65bcfb4 4334 * @param htim : TIM handle
mbed_official 205:c41fc65bcfb4 4335 * @retval None
mbed_official 205:c41fc65bcfb4 4336 */
mbed_official 205:c41fc65bcfb4 4337 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 4338 {
mbed_official 205:c41fc65bcfb4 4339 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 205:c41fc65bcfb4 4340 the HAL_TIM_ErrorCallback could be implemented in the user file
mbed_official 205:c41fc65bcfb4 4341 */
mbed_official 205:c41fc65bcfb4 4342 }
mbed_official 205:c41fc65bcfb4 4343
mbed_official 205:c41fc65bcfb4 4344 /**
mbed_official 205:c41fc65bcfb4 4345 * @}
mbed_official 205:c41fc65bcfb4 4346 */
mbed_official 205:c41fc65bcfb4 4347
mbed_official 205:c41fc65bcfb4 4348 /** @defgroup TIM_Group10 Peripheral State functions
mbed_official 205:c41fc65bcfb4 4349 * @brief Peripheral State functions
mbed_official 205:c41fc65bcfb4 4350 *
mbed_official 205:c41fc65bcfb4 4351 @verbatim
mbed_official 205:c41fc65bcfb4 4352 ==============================================================================
mbed_official 205:c41fc65bcfb4 4353 ##### Peripheral State functions #####
mbed_official 205:c41fc65bcfb4 4354 ==============================================================================
mbed_official 205:c41fc65bcfb4 4355 [..]
mbed_official 205:c41fc65bcfb4 4356 This subsection permit to get in run-time the status of the peripheral
mbed_official 205:c41fc65bcfb4 4357 and the data flow.
mbed_official 205:c41fc65bcfb4 4358
mbed_official 205:c41fc65bcfb4 4359 @endverbatim
mbed_official 205:c41fc65bcfb4 4360 * @{
mbed_official 205:c41fc65bcfb4 4361 */
mbed_official 205:c41fc65bcfb4 4362
mbed_official 205:c41fc65bcfb4 4363 /**
mbed_official 205:c41fc65bcfb4 4364 * @brief Return the TIM Base state
mbed_official 205:c41fc65bcfb4 4365 * @param htim: TIM Base handle
mbed_official 205:c41fc65bcfb4 4366 * @retval HAL state
mbed_official 205:c41fc65bcfb4 4367 */
mbed_official 205:c41fc65bcfb4 4368 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 4369 {
mbed_official 205:c41fc65bcfb4 4370 return htim->State;
mbed_official 205:c41fc65bcfb4 4371 }
mbed_official 205:c41fc65bcfb4 4372
mbed_official 205:c41fc65bcfb4 4373 /**
mbed_official 205:c41fc65bcfb4 4374 * @brief Return the TIM OC state
mbed_official 205:c41fc65bcfb4 4375 * @param htim: TIM Ouput Compare handle
mbed_official 205:c41fc65bcfb4 4376 * @retval HAL state
mbed_official 205:c41fc65bcfb4 4377 */
mbed_official 205:c41fc65bcfb4 4378 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 4379 {
mbed_official 205:c41fc65bcfb4 4380 return htim->State;
mbed_official 205:c41fc65bcfb4 4381 }
mbed_official 205:c41fc65bcfb4 4382
mbed_official 205:c41fc65bcfb4 4383 /**
mbed_official 205:c41fc65bcfb4 4384 * @brief Return the TIM PWM state
mbed_official 205:c41fc65bcfb4 4385 * @param htim: TIM handle
mbed_official 205:c41fc65bcfb4 4386 * @retval HAL state
mbed_official 205:c41fc65bcfb4 4387 */
mbed_official 205:c41fc65bcfb4 4388 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 4389 {
mbed_official 205:c41fc65bcfb4 4390 return htim->State;
mbed_official 205:c41fc65bcfb4 4391 }
mbed_official 205:c41fc65bcfb4 4392
mbed_official 205:c41fc65bcfb4 4393 /**
mbed_official 205:c41fc65bcfb4 4394 * @brief Return the TIM Input Capture state
mbed_official 205:c41fc65bcfb4 4395 * @param htim: TIM IC handle
mbed_official 205:c41fc65bcfb4 4396 * @retval HAL state
mbed_official 205:c41fc65bcfb4 4397 */
mbed_official 205:c41fc65bcfb4 4398 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 4399 {
mbed_official 205:c41fc65bcfb4 4400 return htim->State;
mbed_official 205:c41fc65bcfb4 4401 }
mbed_official 205:c41fc65bcfb4 4402
mbed_official 205:c41fc65bcfb4 4403 /**
mbed_official 205:c41fc65bcfb4 4404 * @brief Return the TIM One Pulse Mode state
mbed_official 205:c41fc65bcfb4 4405 * @param htim: TIM OPM handle
mbed_official 205:c41fc65bcfb4 4406 * @retval HAL state
mbed_official 205:c41fc65bcfb4 4407 */
mbed_official 205:c41fc65bcfb4 4408 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 4409 {
mbed_official 205:c41fc65bcfb4 4410 return htim->State;
mbed_official 205:c41fc65bcfb4 4411 }
mbed_official 205:c41fc65bcfb4 4412
mbed_official 205:c41fc65bcfb4 4413 /**
mbed_official 205:c41fc65bcfb4 4414 * @brief Return the TIM Encoder Mode state
mbed_official 205:c41fc65bcfb4 4415 * @param htim: TIM Encoder handle
mbed_official 205:c41fc65bcfb4 4416 * @retval HAL state
mbed_official 205:c41fc65bcfb4 4417 */
mbed_official 205:c41fc65bcfb4 4418 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
mbed_official 205:c41fc65bcfb4 4419 {
mbed_official 205:c41fc65bcfb4 4420 return htim->State;
mbed_official 205:c41fc65bcfb4 4421 }
mbed_official 205:c41fc65bcfb4 4422
mbed_official 205:c41fc65bcfb4 4423 /**
mbed_official 205:c41fc65bcfb4 4424 * @}
mbed_official 205:c41fc65bcfb4 4425 */
mbed_official 205:c41fc65bcfb4 4426
mbed_official 205:c41fc65bcfb4 4427 /**
mbed_official 205:c41fc65bcfb4 4428 * @brief TIM DMA error callback
mbed_official 205:c41fc65bcfb4 4429 * @param hdma : pointer to DMA handle.
mbed_official 205:c41fc65bcfb4 4430 * @retval None
mbed_official 205:c41fc65bcfb4 4431 */
mbed_official 205:c41fc65bcfb4 4432 void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma)
mbed_official 205:c41fc65bcfb4 4433 {
mbed_official 205:c41fc65bcfb4 4434 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 205:c41fc65bcfb4 4435
mbed_official 205:c41fc65bcfb4 4436 htim->State= HAL_TIM_STATE_READY;
mbed_official 205:c41fc65bcfb4 4437
mbed_official 205:c41fc65bcfb4 4438 HAL_TIM_ErrorCallback(htim);
mbed_official 205:c41fc65bcfb4 4439 }
mbed_official 205:c41fc65bcfb4 4440
mbed_official 205:c41fc65bcfb4 4441 /**
mbed_official 205:c41fc65bcfb4 4442 * @brief TIM DMA Delay Pulse complete callback.
mbed_official 205:c41fc65bcfb4 4443 * @param hdma : pointer to DMA handle.
mbed_official 205:c41fc65bcfb4 4444 * @retval None
mbed_official 205:c41fc65bcfb4 4445 */
mbed_official 205:c41fc65bcfb4 4446 void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
mbed_official 205:c41fc65bcfb4 4447 {
mbed_official 205:c41fc65bcfb4 4448 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 205:c41fc65bcfb4 4449
mbed_official 205:c41fc65bcfb4 4450 htim->State= HAL_TIM_STATE_READY;
mbed_official 205:c41fc65bcfb4 4451
mbed_official 205:c41fc65bcfb4 4452 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
mbed_official 205:c41fc65bcfb4 4453 {
mbed_official 205:c41fc65bcfb4 4454 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
mbed_official 205:c41fc65bcfb4 4455 }
mbed_official 205:c41fc65bcfb4 4456 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
mbed_official 205:c41fc65bcfb4 4457 {
mbed_official 205:c41fc65bcfb4 4458 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
mbed_official 205:c41fc65bcfb4 4459 }
mbed_official 205:c41fc65bcfb4 4460 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
mbed_official 205:c41fc65bcfb4 4461 {
mbed_official 205:c41fc65bcfb4 4462 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
mbed_official 205:c41fc65bcfb4 4463 }
mbed_official 205:c41fc65bcfb4 4464 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
mbed_official 205:c41fc65bcfb4 4465 {
mbed_official 205:c41fc65bcfb4 4466 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
mbed_official 205:c41fc65bcfb4 4467 }
mbed_official 205:c41fc65bcfb4 4468
mbed_official 205:c41fc65bcfb4 4469 HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official 205:c41fc65bcfb4 4470
mbed_official 205:c41fc65bcfb4 4471 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official 205:c41fc65bcfb4 4472 }
mbed_official 205:c41fc65bcfb4 4473 /**
mbed_official 205:c41fc65bcfb4 4474 * @brief TIM DMA Capture complete callback.
mbed_official 205:c41fc65bcfb4 4475 * @param hdma : pointer to DMA handle.
mbed_official 205:c41fc65bcfb4 4476 * @retval None
mbed_official 205:c41fc65bcfb4 4477 */
mbed_official 205:c41fc65bcfb4 4478 void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
mbed_official 205:c41fc65bcfb4 4479 {
mbed_official 205:c41fc65bcfb4 4480 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 205:c41fc65bcfb4 4481
mbed_official 205:c41fc65bcfb4 4482 htim->State= HAL_TIM_STATE_READY;
mbed_official 205:c41fc65bcfb4 4483
mbed_official 205:c41fc65bcfb4 4484 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
mbed_official 205:c41fc65bcfb4 4485 {
mbed_official 205:c41fc65bcfb4 4486 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
mbed_official 205:c41fc65bcfb4 4487 }
mbed_official 205:c41fc65bcfb4 4488 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
mbed_official 205:c41fc65bcfb4 4489 {
mbed_official 205:c41fc65bcfb4 4490 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
mbed_official 205:c41fc65bcfb4 4491 }
mbed_official 205:c41fc65bcfb4 4492 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
mbed_official 205:c41fc65bcfb4 4493 {
mbed_official 205:c41fc65bcfb4 4494 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
mbed_official 205:c41fc65bcfb4 4495 }
mbed_official 205:c41fc65bcfb4 4496 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
mbed_official 205:c41fc65bcfb4 4497 {
mbed_official 205:c41fc65bcfb4 4498 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
mbed_official 205:c41fc65bcfb4 4499 }
mbed_official 205:c41fc65bcfb4 4500
mbed_official 205:c41fc65bcfb4 4501 HAL_TIM_IC_CaptureCallback(htim);
mbed_official 205:c41fc65bcfb4 4502
mbed_official 205:c41fc65bcfb4 4503 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official 205:c41fc65bcfb4 4504 }
mbed_official 205:c41fc65bcfb4 4505
mbed_official 205:c41fc65bcfb4 4506 /**
mbed_official 205:c41fc65bcfb4 4507 * @brief TIM DMA Period Elapse complete callback.
mbed_official 205:c41fc65bcfb4 4508 * @param hdma : pointer to DMA handle.
mbed_official 205:c41fc65bcfb4 4509 * @retval None
mbed_official 205:c41fc65bcfb4 4510 */
mbed_official 205:c41fc65bcfb4 4511 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
mbed_official 205:c41fc65bcfb4 4512 {
mbed_official 205:c41fc65bcfb4 4513 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 205:c41fc65bcfb4 4514
mbed_official 205:c41fc65bcfb4 4515 htim->State= HAL_TIM_STATE_READY;
mbed_official 205:c41fc65bcfb4 4516
mbed_official 205:c41fc65bcfb4 4517 HAL_TIM_PeriodElapsedCallback(htim);
mbed_official 205:c41fc65bcfb4 4518 }
mbed_official 205:c41fc65bcfb4 4519
mbed_official 205:c41fc65bcfb4 4520 /**
mbed_official 205:c41fc65bcfb4 4521 * @brief TIM DMA Trigger callback.
mbed_official 205:c41fc65bcfb4 4522 * @param hdma : pointer to DMA handle.
mbed_official 205:c41fc65bcfb4 4523 * @retval None
mbed_official 205:c41fc65bcfb4 4524 */
mbed_official 205:c41fc65bcfb4 4525 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
mbed_official 205:c41fc65bcfb4 4526 {
mbed_official 205:c41fc65bcfb4 4527 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 205:c41fc65bcfb4 4528
mbed_official 205:c41fc65bcfb4 4529 htim->State= HAL_TIM_STATE_READY;
mbed_official 205:c41fc65bcfb4 4530
mbed_official 205:c41fc65bcfb4 4531 HAL_TIM_TriggerCallback(htim);
mbed_official 205:c41fc65bcfb4 4532 }
mbed_official 205:c41fc65bcfb4 4533
mbed_official 205:c41fc65bcfb4 4534 /**
mbed_official 205:c41fc65bcfb4 4535 * @brief Time Base configuration
mbed_official 205:c41fc65bcfb4 4536 * @param TIMx: TIM periheral
mbed_official 205:c41fc65bcfb4 4537 * @param Structure: TIM Base configuration structure
mbed_official 205:c41fc65bcfb4 4538 * @retval None
mbed_official 205:c41fc65bcfb4 4539 */
mbed_official 205:c41fc65bcfb4 4540 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
mbed_official 205:c41fc65bcfb4 4541 {
mbed_official 205:c41fc65bcfb4 4542 uint32_t tmpcr1 = 0;
mbed_official 205:c41fc65bcfb4 4543 tmpcr1 = TIMx->CR1;
mbed_official 205:c41fc65bcfb4 4544
mbed_official 205:c41fc65bcfb4 4545 /* Set TIM Time Base Unit parameters ---------------------------------------*/
mbed_official 205:c41fc65bcfb4 4546 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
mbed_official 205:c41fc65bcfb4 4547 {
mbed_official 205:c41fc65bcfb4 4548 /* Select the Counter Mode */
mbed_official 205:c41fc65bcfb4 4549 tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS));
mbed_official 205:c41fc65bcfb4 4550 tmpcr1 |= Structure->CounterMode;
mbed_official 205:c41fc65bcfb4 4551 }
mbed_official 205:c41fc65bcfb4 4552
mbed_official 205:c41fc65bcfb4 4553 if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
mbed_official 205:c41fc65bcfb4 4554 {
mbed_official 205:c41fc65bcfb4 4555 /* Set the clock division */
mbed_official 205:c41fc65bcfb4 4556 tmpcr1 &= (uint16_t)(~TIM_CR1_CKD);
mbed_official 205:c41fc65bcfb4 4557 tmpcr1 |= (uint32_t)Structure->ClockDivision;
mbed_official 205:c41fc65bcfb4 4558 }
mbed_official 205:c41fc65bcfb4 4559
mbed_official 205:c41fc65bcfb4 4560 TIMx->CR1 = tmpcr1;
mbed_official 205:c41fc65bcfb4 4561
mbed_official 205:c41fc65bcfb4 4562 /* Set the Autoreload value */
mbed_official 205:c41fc65bcfb4 4563 TIMx->ARR = (uint32_t)Structure->Period ;
mbed_official 205:c41fc65bcfb4 4564
mbed_official 205:c41fc65bcfb4 4565 /* Set the Prescaler value */
mbed_official 205:c41fc65bcfb4 4566 TIMx->PSC = (uint32_t)Structure->Prescaler;
mbed_official 205:c41fc65bcfb4 4567
mbed_official 205:c41fc65bcfb4 4568 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
mbed_official 205:c41fc65bcfb4 4569 {
mbed_official 205:c41fc65bcfb4 4570 /* Set the Repetition Counter value */
mbed_official 205:c41fc65bcfb4 4571 TIMx->RCR = Structure->RepetitionCounter;
mbed_official 205:c41fc65bcfb4 4572 }
mbed_official 205:c41fc65bcfb4 4573
mbed_official 205:c41fc65bcfb4 4574 /* Generate an update event to reload the Prescaler
mbed_official 205:c41fc65bcfb4 4575 and the repetition counter(only for TIM1 and TIM8) value immediatly */
mbed_official 205:c41fc65bcfb4 4576 TIMx->EGR = TIM_EGR_UG;
mbed_official 205:c41fc65bcfb4 4577 }
mbed_official 205:c41fc65bcfb4 4578
mbed_official 205:c41fc65bcfb4 4579 /**
mbed_official 205:c41fc65bcfb4 4580 * @brief Time Ouput Compare 1 configuration
mbed_official 205:c41fc65bcfb4 4581 * @param TIMx to select the TIM peripheral
mbed_official 205:c41fc65bcfb4 4582 * @param OC_Config: The ouput configuration structure
mbed_official 205:c41fc65bcfb4 4583 * @retval None
mbed_official 205:c41fc65bcfb4 4584 */
mbed_official 205:c41fc65bcfb4 4585 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
mbed_official 205:c41fc65bcfb4 4586 {
mbed_official 205:c41fc65bcfb4 4587 uint32_t tmpccmrx = 0;
mbed_official 205:c41fc65bcfb4 4588 uint32_t tmpccer = 0;
mbed_official 205:c41fc65bcfb4 4589 uint32_t tmpcr2 = 0;
mbed_official 205:c41fc65bcfb4 4590
mbed_official 205:c41fc65bcfb4 4591 /* Disable the Channel 1: Reset the CC1E Bit */
mbed_official 205:c41fc65bcfb4 4592 TIMx->CCER &= (uint16_t)(~TIM_CCER_CC1E);
mbed_official 205:c41fc65bcfb4 4593
mbed_official 205:c41fc65bcfb4 4594 /* Get the TIMx CCER register value */
mbed_official 205:c41fc65bcfb4 4595 tmpccer = TIMx->CCER;
mbed_official 205:c41fc65bcfb4 4596 /* Get the TIMx CR2 register value */
mbed_official 205:c41fc65bcfb4 4597 tmpcr2 = TIMx->CR2;
mbed_official 205:c41fc65bcfb4 4598
mbed_official 205:c41fc65bcfb4 4599 /* Get the TIMx CCMR1 register value */
mbed_official 205:c41fc65bcfb4 4600 tmpccmrx = TIMx->CCMR1;
mbed_official 205:c41fc65bcfb4 4601
mbed_official 205:c41fc65bcfb4 4602 /* Reset the Output Compare Mode Bits */
mbed_official 205:c41fc65bcfb4 4603 tmpccmrx &= (uint16_t)(~TIM_CCMR1_OC1M);
mbed_official 205:c41fc65bcfb4 4604 tmpccmrx &= (uint16_t)(~TIM_CCMR1_CC1S);
mbed_official 205:c41fc65bcfb4 4605 /* Select the Output Compare Mode */
mbed_official 205:c41fc65bcfb4 4606 tmpccmrx |= OC_Config->OCMode;
mbed_official 205:c41fc65bcfb4 4607
mbed_official 205:c41fc65bcfb4 4608 /* Reset the Output Polarity level */
mbed_official 205:c41fc65bcfb4 4609 tmpccer &= (uint16_t)(~TIM_CCER_CC1P);
mbed_official 205:c41fc65bcfb4 4610 /* Set the Output Compare Polarity */
mbed_official 205:c41fc65bcfb4 4611 tmpccer |= OC_Config->OCPolarity;
mbed_official 205:c41fc65bcfb4 4612
mbed_official 205:c41fc65bcfb4 4613 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
mbed_official 205:c41fc65bcfb4 4614 {
mbed_official 205:c41fc65bcfb4 4615 /* Check parameters */
mbed_official 205:c41fc65bcfb4 4616 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
mbed_official 205:c41fc65bcfb4 4617
mbed_official 205:c41fc65bcfb4 4618 /* Reset the Output N Polarity level */
mbed_official 205:c41fc65bcfb4 4619 tmpccer &= (uint16_t)(~TIM_CCER_CC1NP);
mbed_official 205:c41fc65bcfb4 4620 /* Set the Output N Polarity */
mbed_official 205:c41fc65bcfb4 4621 tmpccer |= OC_Config->OCNPolarity;
mbed_official 205:c41fc65bcfb4 4622 /* Reset the Output N State */
mbed_official 205:c41fc65bcfb4 4623 tmpccer &= (uint16_t)(~TIM_CCER_CC1NE);
mbed_official 205:c41fc65bcfb4 4624 }
mbed_official 205:c41fc65bcfb4 4625
mbed_official 205:c41fc65bcfb4 4626 if(IS_TIM_BREAK_INSTANCE(TIMx))
mbed_official 205:c41fc65bcfb4 4627 {
mbed_official 205:c41fc65bcfb4 4628 /* Check parameters */
mbed_official 205:c41fc65bcfb4 4629 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
mbed_official 205:c41fc65bcfb4 4630 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
mbed_official 205:c41fc65bcfb4 4631
mbed_official 205:c41fc65bcfb4 4632 /* Reset the Output Compare and Output Compare N IDLE State */
mbed_official 205:c41fc65bcfb4 4633 tmpcr2 &= (uint16_t)(~TIM_CR2_OIS1);
mbed_official 205:c41fc65bcfb4 4634 tmpcr2 &= (uint16_t)(~TIM_CR2_OIS1N);
mbed_official 205:c41fc65bcfb4 4635 /* Set the Output Idle state */
mbed_official 205:c41fc65bcfb4 4636 tmpcr2 |= OC_Config->OCIdleState;
mbed_official 205:c41fc65bcfb4 4637 /* Set the Output N Idle state */
mbed_official 205:c41fc65bcfb4 4638 tmpcr2 |= OC_Config->OCNIdleState;
mbed_official 205:c41fc65bcfb4 4639 }
mbed_official 205:c41fc65bcfb4 4640 /* Write to TIMx CR2 */
mbed_official 205:c41fc65bcfb4 4641 TIMx->CR2 = tmpcr2;
mbed_official 205:c41fc65bcfb4 4642
mbed_official 205:c41fc65bcfb4 4643 /* Write to TIMx CCMR1 */
mbed_official 205:c41fc65bcfb4 4644 TIMx->CCMR1 = tmpccmrx;
mbed_official 205:c41fc65bcfb4 4645
mbed_official 205:c41fc65bcfb4 4646 /* Set the Capture Compare Register value */
mbed_official 205:c41fc65bcfb4 4647 TIMx->CCR1 = OC_Config->Pulse;
mbed_official 205:c41fc65bcfb4 4648
mbed_official 205:c41fc65bcfb4 4649 /* Write to TIMx CCER */
mbed_official 205:c41fc65bcfb4 4650 TIMx->CCER = tmpccer;
mbed_official 205:c41fc65bcfb4 4651 }
mbed_official 205:c41fc65bcfb4 4652
mbed_official 205:c41fc65bcfb4 4653 /**
mbed_official 205:c41fc65bcfb4 4654 * @brief Time Ouput Compare 2 configuration
mbed_official 205:c41fc65bcfb4 4655 * @param TIMx to select the TIM peripheral
mbed_official 205:c41fc65bcfb4 4656 * @param OC_Config: The ouput configuration structure
mbed_official 205:c41fc65bcfb4 4657 * @retval None
mbed_official 205:c41fc65bcfb4 4658 */
mbed_official 205:c41fc65bcfb4 4659 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
mbed_official 205:c41fc65bcfb4 4660 {
mbed_official 205:c41fc65bcfb4 4661 uint32_t tmpccmrx = 0;
mbed_official 205:c41fc65bcfb4 4662 uint32_t tmpccer = 0;
mbed_official 205:c41fc65bcfb4 4663 uint32_t tmpcr2 = 0;
mbed_official 205:c41fc65bcfb4 4664
mbed_official 205:c41fc65bcfb4 4665 /* Disable the Channel 2: Reset the CC2E Bit */
mbed_official 205:c41fc65bcfb4 4666 TIMx->CCER &= (uint16_t)(~TIM_CCER_CC2E);
mbed_official 205:c41fc65bcfb4 4667
mbed_official 205:c41fc65bcfb4 4668 /* Get the TIMx CCER register value */
mbed_official 205:c41fc65bcfb4 4669 tmpccer = TIMx->CCER;
mbed_official 205:c41fc65bcfb4 4670 /* Get the TIMx CR2 register value */
mbed_official 205:c41fc65bcfb4 4671 tmpcr2 = TIMx->CR2;
mbed_official 205:c41fc65bcfb4 4672
mbed_official 205:c41fc65bcfb4 4673 /* Get the TIMx CCMR1 register value */
mbed_official 205:c41fc65bcfb4 4674 tmpccmrx = TIMx->CCMR1;
mbed_official 205:c41fc65bcfb4 4675
mbed_official 205:c41fc65bcfb4 4676 /* Reset the Output Compare mode and Capture/Compare selection Bits */
mbed_official 205:c41fc65bcfb4 4677 tmpccmrx &= (uint16_t)(~TIM_CCMR1_OC2M);
mbed_official 205:c41fc65bcfb4 4678 tmpccmrx &= (uint16_t)(~TIM_CCMR1_CC2S);
mbed_official 205:c41fc65bcfb4 4679
mbed_official 205:c41fc65bcfb4 4680 /* Select the Output Compare Mode */
mbed_official 205:c41fc65bcfb4 4681 tmpccmrx |= (OC_Config->OCMode << 8);
mbed_official 205:c41fc65bcfb4 4682
mbed_official 205:c41fc65bcfb4 4683 /* Reset the Output Polarity level */
mbed_official 205:c41fc65bcfb4 4684 tmpccer &= (uint16_t)(~TIM_CCER_CC2P);
mbed_official 205:c41fc65bcfb4 4685 /* Set the Output Compare Polarity */
mbed_official 205:c41fc65bcfb4 4686 tmpccer |= (OC_Config->OCPolarity << 4);
mbed_official 205:c41fc65bcfb4 4687
mbed_official 205:c41fc65bcfb4 4688 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
mbed_official 205:c41fc65bcfb4 4689 {
mbed_official 205:c41fc65bcfb4 4690 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
mbed_official 205:c41fc65bcfb4 4691 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
mbed_official 205:c41fc65bcfb4 4692 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
mbed_official 205:c41fc65bcfb4 4693
mbed_official 205:c41fc65bcfb4 4694 /* Reset the Output N Polarity level */
mbed_official 205:c41fc65bcfb4 4695 tmpccer &= (uint16_t)(~TIM_CCER_CC2NP);
mbed_official 205:c41fc65bcfb4 4696 /* Set the Output N Polarity */
mbed_official 205:c41fc65bcfb4 4697 tmpccer |= (OC_Config->OCNPolarity << 4);
mbed_official 205:c41fc65bcfb4 4698 /* Reset the Output N State */
mbed_official 205:c41fc65bcfb4 4699 tmpccer &= (uint16_t)(~TIM_CCER_CC2NE);
mbed_official 205:c41fc65bcfb4 4700
mbed_official 205:c41fc65bcfb4 4701 }
mbed_official 205:c41fc65bcfb4 4702
mbed_official 205:c41fc65bcfb4 4703 if(IS_TIM_BREAK_INSTANCE(TIMx))
mbed_official 205:c41fc65bcfb4 4704 {
mbed_official 205:c41fc65bcfb4 4705 /* Check parameters */
mbed_official 205:c41fc65bcfb4 4706 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
mbed_official 205:c41fc65bcfb4 4707 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
mbed_official 205:c41fc65bcfb4 4708
mbed_official 205:c41fc65bcfb4 4709 /* Reset the Output Compare and Output Compare N IDLE State */
mbed_official 205:c41fc65bcfb4 4710 tmpcr2 &= (uint16_t)(~TIM_CR2_OIS2);
mbed_official 205:c41fc65bcfb4 4711 tmpcr2 &= (uint16_t)(~TIM_CR2_OIS2N);
mbed_official 205:c41fc65bcfb4 4712 /* Set the Output Idle state */
mbed_official 205:c41fc65bcfb4 4713 tmpcr2 |= (OC_Config->OCIdleState << 2);
mbed_official 205:c41fc65bcfb4 4714 /* Set the Output N Idle state */
mbed_official 205:c41fc65bcfb4 4715 tmpcr2 |= (OC_Config->OCNIdleState << 2);
mbed_official 205:c41fc65bcfb4 4716 }
mbed_official 205:c41fc65bcfb4 4717
mbed_official 205:c41fc65bcfb4 4718 /* Write to TIMx CR2 */
mbed_official 205:c41fc65bcfb4 4719 TIMx->CR2 = tmpcr2;
mbed_official 205:c41fc65bcfb4 4720
mbed_official 205:c41fc65bcfb4 4721 /* Write to TIMx CCMR1 */
mbed_official 205:c41fc65bcfb4 4722 TIMx->CCMR1 = tmpccmrx;
mbed_official 205:c41fc65bcfb4 4723
mbed_official 205:c41fc65bcfb4 4724 /* Set the Capture Compare Register value */
mbed_official 205:c41fc65bcfb4 4725 TIMx->CCR2 = OC_Config->Pulse;
mbed_official 205:c41fc65bcfb4 4726
mbed_official 205:c41fc65bcfb4 4727 /* Write to TIMx CCER */
mbed_official 205:c41fc65bcfb4 4728 TIMx->CCER = tmpccer;
mbed_official 205:c41fc65bcfb4 4729 }
mbed_official 205:c41fc65bcfb4 4730
mbed_official 205:c41fc65bcfb4 4731 /**
mbed_official 205:c41fc65bcfb4 4732 * @brief Time Ouput Compare 3 configuration
mbed_official 205:c41fc65bcfb4 4733 * @param TIMx to select the TIM peripheral
mbed_official 205:c41fc65bcfb4 4734 * @param OC_Config: The ouput configuration structure
mbed_official 205:c41fc65bcfb4 4735 * @retval None
mbed_official 205:c41fc65bcfb4 4736 */
mbed_official 205:c41fc65bcfb4 4737 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
mbed_official 205:c41fc65bcfb4 4738 {
mbed_official 205:c41fc65bcfb4 4739 uint32_t tmpccmrx = 0;
mbed_official 205:c41fc65bcfb4 4740 uint32_t tmpccer = 0;
mbed_official 205:c41fc65bcfb4 4741 uint32_t tmpcr2 = 0;
mbed_official 205:c41fc65bcfb4 4742
mbed_official 205:c41fc65bcfb4 4743 /* Disable the Channel 3: Reset the CC2E Bit */
mbed_official 205:c41fc65bcfb4 4744 TIMx->CCER &= (uint16_t)(~TIM_CCER_CC3E);
mbed_official 205:c41fc65bcfb4 4745
mbed_official 205:c41fc65bcfb4 4746 /* Get the TIMx CCER register value */
mbed_official 205:c41fc65bcfb4 4747 tmpccer = TIMx->CCER;
mbed_official 205:c41fc65bcfb4 4748 /* Get the TIMx CR2 register value */
mbed_official 205:c41fc65bcfb4 4749 tmpcr2 = TIMx->CR2;
mbed_official 205:c41fc65bcfb4 4750
mbed_official 205:c41fc65bcfb4 4751 /* Get the TIMx CCMR2 register value */
mbed_official 205:c41fc65bcfb4 4752 tmpccmrx = TIMx->CCMR2;
mbed_official 205:c41fc65bcfb4 4753
mbed_official 205:c41fc65bcfb4 4754 /* Reset the Output Compare mode and Capture/Compare selection Bits */
mbed_official 205:c41fc65bcfb4 4755 tmpccmrx &= (uint16_t)(~TIM_CCMR2_OC3M);
mbed_official 205:c41fc65bcfb4 4756 tmpccmrx &= (uint16_t)(~TIM_CCMR2_CC3S);
mbed_official 205:c41fc65bcfb4 4757 /* Select the Output Compare Mode */
mbed_official 205:c41fc65bcfb4 4758 tmpccmrx |= OC_Config->OCMode;
mbed_official 205:c41fc65bcfb4 4759
mbed_official 205:c41fc65bcfb4 4760 /* Reset the Output Polarity level */
mbed_official 205:c41fc65bcfb4 4761 tmpccer &= (uint16_t)(~TIM_CCER_CC3P);
mbed_official 205:c41fc65bcfb4 4762 /* Set the Output Compare Polarity */
mbed_official 205:c41fc65bcfb4 4763 tmpccer |= (OC_Config->OCPolarity << 8);
mbed_official 205:c41fc65bcfb4 4764
mbed_official 205:c41fc65bcfb4 4765 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
mbed_official 205:c41fc65bcfb4 4766 {
mbed_official 205:c41fc65bcfb4 4767 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
mbed_official 205:c41fc65bcfb4 4768 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
mbed_official 205:c41fc65bcfb4 4769 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
mbed_official 205:c41fc65bcfb4 4770
mbed_official 205:c41fc65bcfb4 4771 /* Reset the Output N Polarity level */
mbed_official 205:c41fc65bcfb4 4772 tmpccer &= (uint16_t)(~TIM_CCER_CC3NP);
mbed_official 205:c41fc65bcfb4 4773 /* Set the Output N Polarity */
mbed_official 205:c41fc65bcfb4 4774 tmpccer |= (OC_Config->OCNPolarity << 8);
mbed_official 205:c41fc65bcfb4 4775 /* Reset the Output N State */
mbed_official 205:c41fc65bcfb4 4776 tmpccer &= (uint16_t)(~TIM_CCER_CC3NE);
mbed_official 205:c41fc65bcfb4 4777 }
mbed_official 205:c41fc65bcfb4 4778
mbed_official 205:c41fc65bcfb4 4779 if(IS_TIM_BREAK_INSTANCE(TIMx))
mbed_official 205:c41fc65bcfb4 4780 {
mbed_official 205:c41fc65bcfb4 4781 /* Check parameters */
mbed_official 205:c41fc65bcfb4 4782 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
mbed_official 205:c41fc65bcfb4 4783 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
mbed_official 205:c41fc65bcfb4 4784
mbed_official 205:c41fc65bcfb4 4785 /* Reset the Output Compare and Output Compare N IDLE State */
mbed_official 205:c41fc65bcfb4 4786 tmpcr2 &= (uint16_t)(~TIM_CR2_OIS3);
mbed_official 205:c41fc65bcfb4 4787 tmpcr2 &= (uint16_t)(~TIM_CR2_OIS3N);
mbed_official 205:c41fc65bcfb4 4788 /* Set the Output Idle state */
mbed_official 205:c41fc65bcfb4 4789 tmpcr2 |= (OC_Config->OCIdleState << 4);
mbed_official 205:c41fc65bcfb4 4790 /* Set the Output N Idle state */
mbed_official 205:c41fc65bcfb4 4791 tmpcr2 |= (OC_Config->OCNIdleState << 4);
mbed_official 205:c41fc65bcfb4 4792 }
mbed_official 205:c41fc65bcfb4 4793
mbed_official 205:c41fc65bcfb4 4794 /* Write to TIMx CR2 */
mbed_official 205:c41fc65bcfb4 4795 TIMx->CR2 = tmpcr2;
mbed_official 205:c41fc65bcfb4 4796
mbed_official 205:c41fc65bcfb4 4797 /* Write to TIMx CCMR2 */
mbed_official 205:c41fc65bcfb4 4798 TIMx->CCMR2 = tmpccmrx;
mbed_official 205:c41fc65bcfb4 4799
mbed_official 205:c41fc65bcfb4 4800 /* Set the Capture Compare Register value */
mbed_official 205:c41fc65bcfb4 4801 TIMx->CCR3 = OC_Config->Pulse;
mbed_official 205:c41fc65bcfb4 4802
mbed_official 205:c41fc65bcfb4 4803 /* Write to TIMx CCER */
mbed_official 205:c41fc65bcfb4 4804 TIMx->CCER = tmpccer;
mbed_official 205:c41fc65bcfb4 4805 }
mbed_official 205:c41fc65bcfb4 4806
mbed_official 205:c41fc65bcfb4 4807 /**
mbed_official 205:c41fc65bcfb4 4808 * @brief Time Ouput Compare 4 configuration
mbed_official 205:c41fc65bcfb4 4809 * @param TIMx to select the TIM peripheral
mbed_official 205:c41fc65bcfb4 4810 * @param OC_Config: The ouput configuration structure
mbed_official 205:c41fc65bcfb4 4811 * @retval None
mbed_official 205:c41fc65bcfb4 4812 */
mbed_official 205:c41fc65bcfb4 4813 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
mbed_official 205:c41fc65bcfb4 4814 {
mbed_official 205:c41fc65bcfb4 4815 uint32_t tmpccmrx = 0;
mbed_official 205:c41fc65bcfb4 4816 uint32_t tmpccer = 0;
mbed_official 205:c41fc65bcfb4 4817 uint32_t tmpcr2 = 0;
mbed_official 205:c41fc65bcfb4 4818
mbed_official 205:c41fc65bcfb4 4819 /* Disable the Channel 4: Reset the CC4E Bit */
mbed_official 205:c41fc65bcfb4 4820 TIMx->CCER &= (uint16_t)(~TIM_CCER_CC4E);
mbed_official 205:c41fc65bcfb4 4821
mbed_official 205:c41fc65bcfb4 4822 /* Get the TIMx CCER register value */
mbed_official 205:c41fc65bcfb4 4823 tmpccer = TIMx->CCER;
mbed_official 205:c41fc65bcfb4 4824 /* Get the TIMx CR2 register value */
mbed_official 205:c41fc65bcfb4 4825 tmpcr2 = TIMx->CR2;
mbed_official 205:c41fc65bcfb4 4826
mbed_official 205:c41fc65bcfb4 4827 /* Get the TIMx CCMR2 register value */
mbed_official 205:c41fc65bcfb4 4828 tmpccmrx = TIMx->CCMR2;
mbed_official 205:c41fc65bcfb4 4829
mbed_official 205:c41fc65bcfb4 4830 /* Reset the Output Compare mode and Capture/Compare selection Bits */
mbed_official 205:c41fc65bcfb4 4831 tmpccmrx &= (uint16_t)(~TIM_CCMR2_OC4M);
mbed_official 205:c41fc65bcfb4 4832 tmpccmrx &= (uint16_t)(~TIM_CCMR2_CC4S);
mbed_official 205:c41fc65bcfb4 4833
mbed_official 205:c41fc65bcfb4 4834 /* Select the Output Compare Mode */
mbed_official 205:c41fc65bcfb4 4835 tmpccmrx |= (OC_Config->OCMode << 8);
mbed_official 205:c41fc65bcfb4 4836
mbed_official 205:c41fc65bcfb4 4837 /* Reset the Output Polarity level */
mbed_official 205:c41fc65bcfb4 4838 tmpccer &= (uint16_t)(~TIM_CCER_CC4P);
mbed_official 205:c41fc65bcfb4 4839 /* Set the Output Compare Polarity */
mbed_official 205:c41fc65bcfb4 4840 tmpccer |= (OC_Config->OCPolarity << 12);
mbed_official 205:c41fc65bcfb4 4841
mbed_official 205:c41fc65bcfb4 4842 if(IS_TIM_BREAK_INSTANCE(TIMx))
mbed_official 205:c41fc65bcfb4 4843 {
mbed_official 205:c41fc65bcfb4 4844 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
mbed_official 205:c41fc65bcfb4 4845
mbed_official 205:c41fc65bcfb4 4846 /* Reset the Output Compare IDLE State */
mbed_official 205:c41fc65bcfb4 4847 tmpcr2 &= (uint16_t)(~TIM_CR2_OIS4);
mbed_official 205:c41fc65bcfb4 4848 /* Set the Output Idle state */
mbed_official 205:c41fc65bcfb4 4849 tmpcr2 |= (OC_Config->OCIdleState << 6);
mbed_official 205:c41fc65bcfb4 4850 }
mbed_official 205:c41fc65bcfb4 4851
mbed_official 205:c41fc65bcfb4 4852 /* Write to TIMx CR2 */
mbed_official 205:c41fc65bcfb4 4853 TIMx->CR2 = tmpcr2;
mbed_official 205:c41fc65bcfb4 4854
mbed_official 205:c41fc65bcfb4 4855 /* Write to TIMx CCMR2 */
mbed_official 205:c41fc65bcfb4 4856 TIMx->CCMR2 = tmpccmrx;
mbed_official 205:c41fc65bcfb4 4857
mbed_official 205:c41fc65bcfb4 4858 /* Set the Capture Compare Register value */
mbed_official 205:c41fc65bcfb4 4859 TIMx->CCR4 = OC_Config->Pulse;
mbed_official 205:c41fc65bcfb4 4860
mbed_official 205:c41fc65bcfb4 4861 /* Write to TIMx CCER */
mbed_official 205:c41fc65bcfb4 4862 TIMx->CCER = tmpccer;
mbed_official 205:c41fc65bcfb4 4863 }
mbed_official 205:c41fc65bcfb4 4864
mbed_official 205:c41fc65bcfb4 4865 /**
mbed_official 205:c41fc65bcfb4 4866 * @brief Configure the TI1 as Input.
mbed_official 205:c41fc65bcfb4 4867 * @param TIMx to select the TIM peripheral.
mbed_official 205:c41fc65bcfb4 4868 * @param TIM_ICPolarity : The Input Polarity.
mbed_official 205:c41fc65bcfb4 4869 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 4870 * @arg TIM_ICPolarity_Rising
mbed_official 205:c41fc65bcfb4 4871 * @arg TIM_ICPolarity_Falling
mbed_official 205:c41fc65bcfb4 4872 * @arg TIM_ICPolarity_BothEdge
mbed_official 205:c41fc65bcfb4 4873 * @param TIM_ICSelection: specifies the input to be used.
mbed_official 205:c41fc65bcfb4 4874 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 4875 * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
mbed_official 205:c41fc65bcfb4 4876 * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
mbed_official 205:c41fc65bcfb4 4877 * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
mbed_official 205:c41fc65bcfb4 4878 * @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official 205:c41fc65bcfb4 4879 * This parameter must be a value between 0x00 and 0x0F.
mbed_official 205:c41fc65bcfb4 4880 * @retval None
mbed_official 205:c41fc65bcfb4 4881 */
mbed_official 205:c41fc65bcfb4 4882 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 205:c41fc65bcfb4 4883 uint32_t TIM_ICFilter)
mbed_official 205:c41fc65bcfb4 4884 {
mbed_official 205:c41fc65bcfb4 4885 uint32_t tmpccmr1 = 0;
mbed_official 205:c41fc65bcfb4 4886 uint32_t tmpccer = 0;
mbed_official 205:c41fc65bcfb4 4887
mbed_official 205:c41fc65bcfb4 4888 /* Disable the Channel 1: Reset the CC1E Bit */
mbed_official 205:c41fc65bcfb4 4889 TIMx->CCER &= (uint16_t)(~TIM_CCER_CC1E);
mbed_official 205:c41fc65bcfb4 4890 tmpccmr1 = TIMx->CCMR1;
mbed_official 205:c41fc65bcfb4 4891 tmpccer = TIMx->CCER;
mbed_official 205:c41fc65bcfb4 4892
mbed_official 205:c41fc65bcfb4 4893 /* Select the Input */
mbed_official 205:c41fc65bcfb4 4894 if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
mbed_official 205:c41fc65bcfb4 4895 {
mbed_official 205:c41fc65bcfb4 4896 tmpccmr1 &= (uint16_t)(~TIM_CCMR1_CC1S);
mbed_official 205:c41fc65bcfb4 4897 tmpccmr1 |= TIM_ICSelection;
mbed_official 205:c41fc65bcfb4 4898 }
mbed_official 205:c41fc65bcfb4 4899 else
mbed_official 205:c41fc65bcfb4 4900 {
mbed_official 205:c41fc65bcfb4 4901 tmpccmr1 |= TIM_CCMR1_CC1S_0;
mbed_official 205:c41fc65bcfb4 4902 }
mbed_official 205:c41fc65bcfb4 4903
mbed_official 205:c41fc65bcfb4 4904 /* Set the filter */
mbed_official 205:c41fc65bcfb4 4905 tmpccmr1 &= (uint16_t)(~TIM_CCMR1_IC1F);
mbed_official 205:c41fc65bcfb4 4906 tmpccmr1 |= (TIM_ICFilter << 4);
mbed_official 205:c41fc65bcfb4 4907
mbed_official 205:c41fc65bcfb4 4908 /* Select the Polarity and set the CC1E Bit */
mbed_official 205:c41fc65bcfb4 4909 tmpccer &= (uint16_t)(~(TIM_CCER_CC1P | TIM_CCER_CC1NP));
mbed_official 205:c41fc65bcfb4 4910 tmpccer |= TIM_ICPolarity;
mbed_official 205:c41fc65bcfb4 4911
mbed_official 205:c41fc65bcfb4 4912 /* Write to TIMx CCMR1 and CCER registers */
mbed_official 205:c41fc65bcfb4 4913 TIMx->CCMR1 = tmpccmr1;
mbed_official 205:c41fc65bcfb4 4914 TIMx->CCER = tmpccer;
mbed_official 205:c41fc65bcfb4 4915 }
mbed_official 205:c41fc65bcfb4 4916
mbed_official 205:c41fc65bcfb4 4917 /**
mbed_official 205:c41fc65bcfb4 4918 * @brief Configure the Polarity and Filter for TI1.
mbed_official 205:c41fc65bcfb4 4919 * @param TIMx to select the TIM peripheral.
mbed_official 205:c41fc65bcfb4 4920 * @param TIM_ICPolarity : The Input Polarity.
mbed_official 205:c41fc65bcfb4 4921 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 4922 * @arg TIM_ICPolarity_Rising
mbed_official 205:c41fc65bcfb4 4923 * @arg TIM_ICPolarity_Falling
mbed_official 205:c41fc65bcfb4 4924 * @arg TIM_ICPolarity_BothEdge
mbed_official 205:c41fc65bcfb4 4925 * @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official 205:c41fc65bcfb4 4926 * This parameter must be a value between 0x00 and 0x0F.
mbed_official 205:c41fc65bcfb4 4927 * @retval None
mbed_official 205:c41fc65bcfb4 4928 */
mbed_official 205:c41fc65bcfb4 4929 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
mbed_official 205:c41fc65bcfb4 4930 {
mbed_official 205:c41fc65bcfb4 4931 uint32_t tmpccmr1 = 0;
mbed_official 205:c41fc65bcfb4 4932 uint32_t tmpccer = 0;
mbed_official 205:c41fc65bcfb4 4933
mbed_official 205:c41fc65bcfb4 4934 /* Disable the Channel 1: Reset the CC1E Bit */
mbed_official 205:c41fc65bcfb4 4935 tmpccer = TIMx->CCER;
mbed_official 205:c41fc65bcfb4 4936 TIMx->CCER &= (uint16_t)(~TIM_CCER_CC1E);
mbed_official 205:c41fc65bcfb4 4937 tmpccmr1 = TIMx->CCMR1;
mbed_official 205:c41fc65bcfb4 4938
mbed_official 205:c41fc65bcfb4 4939 /* Set the filter */
mbed_official 205:c41fc65bcfb4 4940 tmpccmr1 &= (uint16_t)(~TIM_CCMR1_IC1F);
mbed_official 205:c41fc65bcfb4 4941 tmpccmr1 |= (TIM_ICFilter << 4);
mbed_official 205:c41fc65bcfb4 4942
mbed_official 205:c41fc65bcfb4 4943 /* Select the Polarity and set the CC1E Bit */
mbed_official 205:c41fc65bcfb4 4944 tmpccer &= (uint16_t)(~(TIM_CCER_CC1P | TIM_CCER_CC1NP));
mbed_official 205:c41fc65bcfb4 4945 tmpccer |= TIM_ICPolarity;
mbed_official 205:c41fc65bcfb4 4946
mbed_official 205:c41fc65bcfb4 4947 /* Write to TIMx CCMR1 and CCER registers */
mbed_official 205:c41fc65bcfb4 4948 TIMx->CCMR1 = tmpccmr1;
mbed_official 205:c41fc65bcfb4 4949 TIMx->CCER = tmpccer;
mbed_official 205:c41fc65bcfb4 4950 }
mbed_official 205:c41fc65bcfb4 4951
mbed_official 205:c41fc65bcfb4 4952 /**
mbed_official 205:c41fc65bcfb4 4953 * @brief Configure the TI2 as Input.
mbed_official 205:c41fc65bcfb4 4954 * @param TIMx to select the TIM peripheral
mbed_official 205:c41fc65bcfb4 4955 * @param TIM_ICPolarity : The Input Polarity.
mbed_official 205:c41fc65bcfb4 4956 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 4957 * @arg TIM_ICPolarity_Rising
mbed_official 205:c41fc65bcfb4 4958 * @arg TIM_ICPolarity_Falling
mbed_official 205:c41fc65bcfb4 4959 * @arg TIM_ICPolarity_BothEdge
mbed_official 205:c41fc65bcfb4 4960 * @param TIM_ICSelection: specifies the input to be used.
mbed_official 205:c41fc65bcfb4 4961 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 4962 * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
mbed_official 205:c41fc65bcfb4 4963 * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
mbed_official 205:c41fc65bcfb4 4964 * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
mbed_official 205:c41fc65bcfb4 4965 * @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official 205:c41fc65bcfb4 4966 * This parameter must be a value between 0x00 and 0x0F.
mbed_official 205:c41fc65bcfb4 4967 * @retval None
mbed_official 205:c41fc65bcfb4 4968 */
mbed_official 205:c41fc65bcfb4 4969 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 205:c41fc65bcfb4 4970 uint32_t TIM_ICFilter)
mbed_official 205:c41fc65bcfb4 4971 {
mbed_official 205:c41fc65bcfb4 4972 uint32_t tmpccmr1 = 0;
mbed_official 205:c41fc65bcfb4 4973 uint32_t tmpccer = 0;
mbed_official 205:c41fc65bcfb4 4974
mbed_official 205:c41fc65bcfb4 4975 /* Disable the Channel 2: Reset the CC2E Bit */
mbed_official 205:c41fc65bcfb4 4976 TIMx->CCER &= (uint16_t)(~TIM_CCER_CC2E);
mbed_official 205:c41fc65bcfb4 4977 tmpccmr1 = TIMx->CCMR1;
mbed_official 205:c41fc65bcfb4 4978 tmpccer = TIMx->CCER;
mbed_official 205:c41fc65bcfb4 4979
mbed_official 205:c41fc65bcfb4 4980 /* Select the Input */
mbed_official 205:c41fc65bcfb4 4981 tmpccmr1 &= (uint16_t)(~TIM_CCMR1_CC2S);
mbed_official 205:c41fc65bcfb4 4982 tmpccmr1 |= (TIM_ICSelection << 8);
mbed_official 205:c41fc65bcfb4 4983
mbed_official 205:c41fc65bcfb4 4984 /* Set the filter */
mbed_official 205:c41fc65bcfb4 4985 tmpccmr1 &= (uint16_t)(~TIM_CCMR1_IC2F);
mbed_official 205:c41fc65bcfb4 4986 tmpccmr1 |= (TIM_ICFilter << 12);
mbed_official 205:c41fc65bcfb4 4987
mbed_official 205:c41fc65bcfb4 4988 /* Select the Polarity and set the CC2E Bit */
mbed_official 205:c41fc65bcfb4 4989 tmpccer &= (uint16_t)(~(TIM_CCER_CC2P | TIM_CCER_CC2NP));
mbed_official 205:c41fc65bcfb4 4990 tmpccer |= (TIM_ICPolarity << 4);
mbed_official 205:c41fc65bcfb4 4991
mbed_official 205:c41fc65bcfb4 4992 /* Write to TIMx CCMR1 and CCER registers */
mbed_official 205:c41fc65bcfb4 4993 TIMx->CCMR1 = tmpccmr1 ;
mbed_official 205:c41fc65bcfb4 4994 TIMx->CCER = tmpccer;
mbed_official 205:c41fc65bcfb4 4995 }
mbed_official 205:c41fc65bcfb4 4996
mbed_official 205:c41fc65bcfb4 4997 /**
mbed_official 205:c41fc65bcfb4 4998 * @brief Configure the Polarity and Filter for TI2.
mbed_official 205:c41fc65bcfb4 4999 * @param TIMx to select the TIM peripheral.
mbed_official 205:c41fc65bcfb4 5000 * @param TIM_ICPolarity : The Input Polarity.
mbed_official 205:c41fc65bcfb4 5001 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 5002 * @arg TIM_ICPolarity_Rising
mbed_official 205:c41fc65bcfb4 5003 * @arg TIM_ICPolarity_Falling
mbed_official 205:c41fc65bcfb4 5004 * @arg TIM_ICPolarity_BothEdge
mbed_official 205:c41fc65bcfb4 5005 * @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official 205:c41fc65bcfb4 5006 * This parameter must be a value between 0x00 and 0x0F.
mbed_official 205:c41fc65bcfb4 5007 * @retval None
mbed_official 205:c41fc65bcfb4 5008 */
mbed_official 205:c41fc65bcfb4 5009 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
mbed_official 205:c41fc65bcfb4 5010 {
mbed_official 205:c41fc65bcfb4 5011 uint32_t tmpccmr1 = 0;
mbed_official 205:c41fc65bcfb4 5012 uint32_t tmpccer = 0;
mbed_official 205:c41fc65bcfb4 5013
mbed_official 205:c41fc65bcfb4 5014 /* Disable the Channel 2: Reset the CC2E Bit */
mbed_official 205:c41fc65bcfb4 5015 TIMx->CCER &= (uint16_t)(~TIM_CCER_CC2E);
mbed_official 205:c41fc65bcfb4 5016 tmpccmr1 = TIMx->CCMR1;
mbed_official 205:c41fc65bcfb4 5017 tmpccer = TIMx->CCER;
mbed_official 205:c41fc65bcfb4 5018
mbed_official 205:c41fc65bcfb4 5019 /* Set the filter */
mbed_official 205:c41fc65bcfb4 5020 tmpccmr1 &= (uint16_t)(~TIM_CCMR1_IC2F);
mbed_official 205:c41fc65bcfb4 5021 tmpccmr1 |= (TIM_ICFilter << 12);
mbed_official 205:c41fc65bcfb4 5022
mbed_official 205:c41fc65bcfb4 5023 /* Select the Polarity and set the CC2E Bit */
mbed_official 205:c41fc65bcfb4 5024 tmpccer &= (uint16_t)(~(TIM_CCER_CC2P | TIM_CCER_CC2NP));
mbed_official 205:c41fc65bcfb4 5025 tmpccer |= (TIM_ICPolarity << 4);
mbed_official 205:c41fc65bcfb4 5026
mbed_official 205:c41fc65bcfb4 5027 /* Write to TIMx CCMR1 and CCER registers */
mbed_official 205:c41fc65bcfb4 5028 TIMx->CCMR1 = tmpccmr1 ;
mbed_official 205:c41fc65bcfb4 5029 TIMx->CCER = tmpccer;
mbed_official 205:c41fc65bcfb4 5030 }
mbed_official 205:c41fc65bcfb4 5031
mbed_official 205:c41fc65bcfb4 5032 /**
mbed_official 205:c41fc65bcfb4 5033 * @brief Configure the TI3 as Input.
mbed_official 205:c41fc65bcfb4 5034 * @param TIMx to select the TIM peripheral
mbed_official 205:c41fc65bcfb4 5035 * @param TIM_ICPolarity : The Input Polarity.
mbed_official 205:c41fc65bcfb4 5036 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 5037 * @arg TIM_ICPolarity_Rising
mbed_official 205:c41fc65bcfb4 5038 * @arg TIM_ICPolarity_Falling
mbed_official 205:c41fc65bcfb4 5039 * @arg TIM_ICPolarity_BothEdge
mbed_official 205:c41fc65bcfb4 5040 * @param TIM_ICSelection: specifies the input to be used.
mbed_official 205:c41fc65bcfb4 5041 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 5042 * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
mbed_official 205:c41fc65bcfb4 5043 * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
mbed_official 205:c41fc65bcfb4 5044 * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
mbed_official 205:c41fc65bcfb4 5045 * @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official 205:c41fc65bcfb4 5046 * This parameter must be a value between 0x00 and 0x0F.
mbed_official 205:c41fc65bcfb4 5047 * @retval None
mbed_official 205:c41fc65bcfb4 5048 */
mbed_official 205:c41fc65bcfb4 5049 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 205:c41fc65bcfb4 5050 uint32_t TIM_ICFilter)
mbed_official 205:c41fc65bcfb4 5051 {
mbed_official 205:c41fc65bcfb4 5052 uint32_t tmpccmr2 = 0;
mbed_official 205:c41fc65bcfb4 5053 uint32_t tmpccer = 0;
mbed_official 205:c41fc65bcfb4 5054
mbed_official 205:c41fc65bcfb4 5055 /* Disable the Channel 3: Reset the CC3E Bit */
mbed_official 205:c41fc65bcfb4 5056 TIMx->CCER &= (uint16_t)(~TIM_CCER_CC3E);
mbed_official 205:c41fc65bcfb4 5057 tmpccmr2 = TIMx->CCMR2;
mbed_official 205:c41fc65bcfb4 5058 tmpccer = TIMx->CCER;
mbed_official 205:c41fc65bcfb4 5059
mbed_official 205:c41fc65bcfb4 5060 /* Select the Input */
mbed_official 205:c41fc65bcfb4 5061 tmpccmr2 &= (uint16_t)(~TIM_CCMR2_CC3S);
mbed_official 205:c41fc65bcfb4 5062 tmpccmr2 |= TIM_ICSelection;
mbed_official 205:c41fc65bcfb4 5063
mbed_official 205:c41fc65bcfb4 5064 /* Set the filter */
mbed_official 205:c41fc65bcfb4 5065 tmpccmr2 &= (uint16_t)(~TIM_CCMR2_IC3F);
mbed_official 205:c41fc65bcfb4 5066 tmpccmr2 |= (TIM_ICFilter << 4);
mbed_official 205:c41fc65bcfb4 5067
mbed_official 205:c41fc65bcfb4 5068 /* Select the Polarity and set the CC3E Bit */
mbed_official 205:c41fc65bcfb4 5069 tmpccer &= (uint16_t)(~(TIM_CCER_CC3P | TIM_CCER_CC3NP));
mbed_official 205:c41fc65bcfb4 5070 tmpccer |= (TIM_ICPolarity << 8);
mbed_official 205:c41fc65bcfb4 5071
mbed_official 205:c41fc65bcfb4 5072 /* Write to TIMx CCMR2 and CCER registers */
mbed_official 205:c41fc65bcfb4 5073 TIMx->CCMR2 = tmpccmr2;
mbed_official 205:c41fc65bcfb4 5074 TIMx->CCER = tmpccer;
mbed_official 205:c41fc65bcfb4 5075 }
mbed_official 205:c41fc65bcfb4 5076
mbed_official 205:c41fc65bcfb4 5077 /**
mbed_official 205:c41fc65bcfb4 5078 * @brief Configure the TI4 as Input.
mbed_official 205:c41fc65bcfb4 5079 * @param TIMx to select the TIM peripheral
mbed_official 205:c41fc65bcfb4 5080 * @param TIM_ICPolarity : The Input Polarity.
mbed_official 205:c41fc65bcfb4 5081 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 5082 * @arg TIM_ICPolarity_Rising
mbed_official 205:c41fc65bcfb4 5083 * @arg TIM_ICPolarity_Falling
mbed_official 205:c41fc65bcfb4 5084 * @arg TIM_ICPolarity_BothEdge
mbed_official 205:c41fc65bcfb4 5085 * @param TIM_ICSelection: specifies the input to be used.
mbed_official 205:c41fc65bcfb4 5086 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 5087 * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
mbed_official 205:c41fc65bcfb4 5088 * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
mbed_official 205:c41fc65bcfb4 5089 * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
mbed_official 205:c41fc65bcfb4 5090 * @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official 205:c41fc65bcfb4 5091 * This parameter must be a value between 0x00 and 0x0F.
mbed_official 205:c41fc65bcfb4 5092 * @retval None
mbed_official 205:c41fc65bcfb4 5093 */
mbed_official 205:c41fc65bcfb4 5094 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 205:c41fc65bcfb4 5095 uint32_t TIM_ICFilter)
mbed_official 205:c41fc65bcfb4 5096 {
mbed_official 205:c41fc65bcfb4 5097 uint32_t tmpccmr2 = 0;
mbed_official 205:c41fc65bcfb4 5098 uint32_t tmpccer = 0;
mbed_official 205:c41fc65bcfb4 5099
mbed_official 205:c41fc65bcfb4 5100 /* Disable the Channel 4: Reset the CC4E Bit */
mbed_official 205:c41fc65bcfb4 5101 TIMx->CCER &= (uint16_t)(~TIM_CCER_CC4E);
mbed_official 205:c41fc65bcfb4 5102 tmpccmr2 = TIMx->CCMR2;
mbed_official 205:c41fc65bcfb4 5103 tmpccer = TIMx->CCER;
mbed_official 205:c41fc65bcfb4 5104
mbed_official 205:c41fc65bcfb4 5105 /* Select the Input */
mbed_official 205:c41fc65bcfb4 5106 tmpccmr2 &= (uint16_t)(~TIM_CCMR2_CC4S);
mbed_official 205:c41fc65bcfb4 5107 tmpccmr2 |= (TIM_ICSelection << 8);
mbed_official 205:c41fc65bcfb4 5108
mbed_official 205:c41fc65bcfb4 5109 /* Set the filter */
mbed_official 205:c41fc65bcfb4 5110 tmpccmr2 &= (uint16_t)(~TIM_CCMR2_IC4F);
mbed_official 205:c41fc65bcfb4 5111 tmpccmr2 |= (TIM_ICFilter << 12);
mbed_official 205:c41fc65bcfb4 5112
mbed_official 205:c41fc65bcfb4 5113 /* Select the Polarity and set the CC4E Bit */
mbed_official 205:c41fc65bcfb4 5114 tmpccer &= (uint16_t)(~(TIM_CCER_CC4P | TIM_CCER_CC4NP));
mbed_official 205:c41fc65bcfb4 5115 tmpccer |= (TIM_ICPolarity << 12);
mbed_official 205:c41fc65bcfb4 5116
mbed_official 205:c41fc65bcfb4 5117 /* Write to TIMx CCMR2 and CCER registers */
mbed_official 205:c41fc65bcfb4 5118 TIMx->CCMR2 = tmpccmr2;
mbed_official 205:c41fc65bcfb4 5119 TIMx->CCER = tmpccer ;
mbed_official 205:c41fc65bcfb4 5120 }
mbed_official 205:c41fc65bcfb4 5121
mbed_official 205:c41fc65bcfb4 5122 /**
mbed_official 205:c41fc65bcfb4 5123 * @brief Selects the Input Trigger source
mbed_official 205:c41fc65bcfb4 5124 * @param TIMx to select the TIM peripheral
mbed_official 205:c41fc65bcfb4 5125 * @param InputTriggerSource: The Input Trigger source.
mbed_official 205:c41fc65bcfb4 5126 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 5127 * @arg TIM_TS_ITR0: Internal Trigger 0
mbed_official 205:c41fc65bcfb4 5128 * @arg TIM_TS_ITR1: Internal Trigger 1
mbed_official 205:c41fc65bcfb4 5129 * @arg TIM_TS_ITR2: Internal Trigger 2
mbed_official 205:c41fc65bcfb4 5130 * @arg TIM_TS_ITR3: Internal Trigger 3
mbed_official 205:c41fc65bcfb4 5131 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
mbed_official 205:c41fc65bcfb4 5132 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
mbed_official 205:c41fc65bcfb4 5133 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
mbed_official 205:c41fc65bcfb4 5134 * @arg TIM_TS_ETRF: External Trigger input
mbed_official 205:c41fc65bcfb4 5135 * @retval None
mbed_official 205:c41fc65bcfb4 5136 */
mbed_official 205:c41fc65bcfb4 5137 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
mbed_official 205:c41fc65bcfb4 5138 {
mbed_official 205:c41fc65bcfb4 5139 uint32_t tmpsmcr = 0;
mbed_official 205:c41fc65bcfb4 5140
mbed_official 205:c41fc65bcfb4 5141 /* Get the TIMx SMCR register value */
mbed_official 205:c41fc65bcfb4 5142 tmpsmcr = TIMx->SMCR;
mbed_official 205:c41fc65bcfb4 5143 /* Reset the TS Bits */
mbed_official 205:c41fc65bcfb4 5144 tmpsmcr &= (uint16_t)(~TIM_SMCR_TS);
mbed_official 205:c41fc65bcfb4 5145 /* Set the Input Trigger source and the slave mode*/
mbed_official 205:c41fc65bcfb4 5146 tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1;
mbed_official 205:c41fc65bcfb4 5147 /* Write to TIMx SMCR */
mbed_official 205:c41fc65bcfb4 5148 TIMx->SMCR = tmpsmcr;
mbed_official 205:c41fc65bcfb4 5149 }
mbed_official 205:c41fc65bcfb4 5150 /**
mbed_official 205:c41fc65bcfb4 5151 * @brief Configures the TIMx External Trigger (ETR).
mbed_official 205:c41fc65bcfb4 5152 * @param TIMx to select the TIM peripheral
mbed_official 205:c41fc65bcfb4 5153 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
mbed_official 205:c41fc65bcfb4 5154 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 5155 * @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.
mbed_official 205:c41fc65bcfb4 5156 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
mbed_official 205:c41fc65bcfb4 5157 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
mbed_official 205:c41fc65bcfb4 5158 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
mbed_official 205:c41fc65bcfb4 5159 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
mbed_official 205:c41fc65bcfb4 5160 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 5161 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
mbed_official 205:c41fc65bcfb4 5162 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
mbed_official 205:c41fc65bcfb4 5163 * @param ExtTRGFilter: External Trigger Filter.
mbed_official 205:c41fc65bcfb4 5164 * This parameter must be a value between 0x00 and 0x0F
mbed_official 205:c41fc65bcfb4 5165 * @retval None
mbed_official 205:c41fc65bcfb4 5166 */
mbed_official 205:c41fc65bcfb4 5167 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
mbed_official 205:c41fc65bcfb4 5168 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
mbed_official 205:c41fc65bcfb4 5169 {
mbed_official 205:c41fc65bcfb4 5170 uint32_t tmpsmcr = 0;
mbed_official 205:c41fc65bcfb4 5171
mbed_official 205:c41fc65bcfb4 5172 tmpsmcr = TIMx->SMCR;
mbed_official 205:c41fc65bcfb4 5173
mbed_official 205:c41fc65bcfb4 5174 /* Reset the ETR Bits */
mbed_official 205:c41fc65bcfb4 5175 tmpsmcr &= (uint32_t)(~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
mbed_official 205:c41fc65bcfb4 5176
mbed_official 205:c41fc65bcfb4 5177 /* Set the Prescaler, the Filter value and the Polarity */
mbed_official 205:c41fc65bcfb4 5178 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
mbed_official 205:c41fc65bcfb4 5179
mbed_official 205:c41fc65bcfb4 5180 /* Write to TIMx SMCR */
mbed_official 205:c41fc65bcfb4 5181 TIMx->SMCR = tmpsmcr;
mbed_official 205:c41fc65bcfb4 5182 }
mbed_official 205:c41fc65bcfb4 5183
mbed_official 205:c41fc65bcfb4 5184 /**
mbed_official 205:c41fc65bcfb4 5185 * @brief Enables or disables the TIM Capture Compare Channel x.
mbed_official 205:c41fc65bcfb4 5186 * @param TIMx to select the TIM peripheral
mbed_official 205:c41fc65bcfb4 5187 * @param Channel: specifies the TIM Channel
mbed_official 205:c41fc65bcfb4 5188 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 5189 * @arg TIM_Channel_1: TIM Channel 1
mbed_official 205:c41fc65bcfb4 5190 * @arg TIM_Channel_2: TIM Channel 2
mbed_official 205:c41fc65bcfb4 5191 * @arg TIM_Channel_3: TIM Channel 3
mbed_official 205:c41fc65bcfb4 5192 * @arg TIM_Channel_4: TIM Channel 4
mbed_official 205:c41fc65bcfb4 5193 * @param ChannelState: specifies the TIM Channel CCxE bit new state.
mbed_official 205:c41fc65bcfb4 5194 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
mbed_official 205:c41fc65bcfb4 5195 * @retval None
mbed_official 205:c41fc65bcfb4 5196 */
mbed_official 205:c41fc65bcfb4 5197 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
mbed_official 205:c41fc65bcfb4 5198 {
mbed_official 205:c41fc65bcfb4 5199 uint32_t tmp = 0;
mbed_official 205:c41fc65bcfb4 5200
mbed_official 205:c41fc65bcfb4 5201 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 5202 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
mbed_official 205:c41fc65bcfb4 5203 assert_param(IS_TIM_CHANNELS(Channel));
mbed_official 205:c41fc65bcfb4 5204
mbed_official 205:c41fc65bcfb4 5205 tmp = (uint16_t)(TIM_CCER_CC1E << Channel);
mbed_official 205:c41fc65bcfb4 5206
mbed_official 205:c41fc65bcfb4 5207 /* Reset the CCxE Bit */
mbed_official 205:c41fc65bcfb4 5208 TIMx->CCER &= ~tmp;
mbed_official 205:c41fc65bcfb4 5209
mbed_official 205:c41fc65bcfb4 5210 /* Set or reset the CCxE Bit */
mbed_official 205:c41fc65bcfb4 5211 TIMx->CCER |= (uint32_t)(ChannelState << Channel);
mbed_official 205:c41fc65bcfb4 5212 }
mbed_official 205:c41fc65bcfb4 5213
mbed_official 205:c41fc65bcfb4 5214
mbed_official 205:c41fc65bcfb4 5215 /**
mbed_official 205:c41fc65bcfb4 5216 * @}
mbed_official 205:c41fc65bcfb4 5217 */
mbed_official 205:c41fc65bcfb4 5218
mbed_official 205:c41fc65bcfb4 5219 #endif /* HAL_TIM_MODULE_ENABLED */
mbed_official 205:c41fc65bcfb4 5220 /**
mbed_official 205:c41fc65bcfb4 5221 * @}
mbed_official 205:c41fc65bcfb4 5222 */
mbed_official 205:c41fc65bcfb4 5223
mbed_official 205:c41fc65bcfb4 5224 /**
mbed_official 205:c41fc65bcfb4 5225 * @}
mbed_official 205:c41fc65bcfb4 5226 */
mbed_official 205:c41fc65bcfb4 5227 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/