Kenji Arai / CheckRTC

Checking program for RTC module inside CPU.

Dependents:   RTC_w_COM Frequency_Counter_w_GPS_1PPS debug_tools Nucleo_RTC_Clock_setting ... more

Please refer below link.
http://developer.mbed.org/users/kenjiArai/notebook/nucleo-series-clock-structure-and-xtal-oscillation/

CheckRTC.cpp@3:babcde30190d, 2015-05-16 (annotated)

Committer:
kenjiArai
Date:
Sat May 16 23:34:53 2015 +0000
Revision:
3:babcde30190d
Parent:
2:2ee7a7260cbf 
small modification

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kenjiArai 0:01ddb8e35845 1 /*
kenjiArai 0:01ddb8e35845 2 * mbed Library program
kenjiArai 0:01ddb8e35845 3 * Check RTC function and set proper clock if we can set
kenjiArai 0:01ddb8e35845 4 * ONLY FOR "Nucleo Board"
kenjiArai 0:01ddb8e35845 5 *
kenjiArai 3:babcde30190d 6 * Copyright (c) 2010-2015 Kenji Arai / JH1PJL
kenjiArai 0:01ddb8e35845 7 * http://www.page.sannet.ne.jp/kenjia/index.html
kenjiArai 0:01ddb8e35845 8 * http://mbed.org/users/kenjiArai/
kenjiArai 0:01ddb8e35845 9 * Created: October 24th, 2014
kenjiArai 3:babcde30190d 10 * Revised: May 16th, 2015
kenjiArai 0:01ddb8e35845 11 *
kenjiArai 0:01ddb8e35845 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
kenjiArai 0:01ddb8e35845 13 * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
kenjiArai 0:01ddb8e35845 14 * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
kenjiArai 0:01ddb8e35845 15 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
kenjiArai 0:01ddb8e35845 16 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
kenjiArai 0:01ddb8e35845 17 */
kenjiArai 0:01ddb8e35845 18
kenjiArai 0:01ddb8e35845 19 //#define DEBUG // use Communication with PC(UART)
kenjiArai 0:01ddb8e35845 20
kenjiArai 0:01ddb8e35845 21 // Include ---------------------------------------------------------------------------------------
kenjiArai 0:01ddb8e35845 22 #include "mbed.h"
kenjiArai 0:01ddb8e35845 23 #include "CheckRTC.h"
kenjiArai 0:01ddb8e35845 24
kenjiArai 0:01ddb8e35845 25 // Definition ------------------------------------------------------------------------------------
kenjiArai 0:01ddb8e35845 26 #ifdef DEBUG
kenjiArai 3:babcde30190d 27 #define PUTS(x) pcm.puts(x)
kenjiArai 0:01ddb8e35845 28 #define PRINTF(...) pcm.printf(__VA_ARGS__)
kenjiArai 0:01ddb8e35845 29 #else
kenjiArai 3:babcde30190d 30 #define PUTS(x) {;}
kenjiArai 0:01ddb8e35845 31 #define PRINTF(...) {;}
kenjiArai 0:01ddb8e35845 32 #endif
kenjiArai 0:01ddb8e35845 33
kenjiArai 0:01ddb8e35845 34 // Object ----------------------------------------------------------------------------------------
kenjiArai 0:01ddb8e35845 35 #ifdef DEBUG
kenjiArai 0:01ddb8e35845 36 Serial pcm(USBTX, USBRX);
kenjiArai 0:01ddb8e35845 37 #endif
kenjiArai 0:01ddb8e35845 38
kenjiArai 0:01ddb8e35845 39 // RAM -------------------------------------------------------------------------------------------
kenjiArai 0:01ddb8e35845 40
kenjiArai 0:01ddb8e35845 41 // ROM / Constant data ---------------------------------------------------------------------------
kenjiArai 0:01ddb8e35845 42
kenjiArai 0:01ddb8e35845 43 // Function prototypes ---------------------------------------------------------------------------
kenjiArai 0:01ddb8e35845 44 #if defined(TARGET_NUCLEO_F401RE) || defined(TARGET_NUCLEO_F411RE) || defined(TARGET_NUCLEO_L152RE)
kenjiArai 0:01ddb8e35845 45 static int32_t Set_RTC_LSI(void);
kenjiArai 0:01ddb8e35845 46 static int32_t rtc_external_osc_init(void);
kenjiArai 0:01ddb8e35845 47 static int32_t Set_RTC_LSE(void);
kenjiArai 0:01ddb8e35845 48 #endif
kenjiArai 0:01ddb8e35845 49
kenjiArai 0:01ddb8e35845 50 //-------------------------------------------------------------------------------------------------
kenjiArai 0:01ddb8e35845 51 // Control Program
kenjiArai 0:01ddb8e35845 52 //-------------------------------------------------------------------------------------------------
kenjiArai 3:babcde30190d 53 int32_t CheckRTC(void)
kenjiArai 0:01ddb8e35845 54 {
kenjiArai 0:01ddb8e35845 55 #if defined(TARGET_NUCLEO_F401RE) || defined(TARGET_NUCLEO_F411RE) || defined(TARGET_NUCLEO_L152RE)
kenjiArai 0:01ddb8e35845 56 if (rtc_external_osc_init() == OK) {
kenjiArai 0:01ddb8e35845 57 return OK;
kenjiArai 0:01ddb8e35845 58 } else {
kenjiArai 0:01ddb8e35845 59 return NG;
kenjiArai 0:01ddb8e35845 60 }
kenjiArai 0:01ddb8e35845 61 #elif defined(TARGET_LPC1768) || defined(TARGET_K64F)
kenjiArai 0:01ddb8e35845 62 return OK;
kenjiArai 0:01ddb8e35845 63 #else
kenjiArai 0:01ddb8e35845 64 return UNKNOWN;
kenjiArai 0:01ddb8e35845 65 #endif
kenjiArai 0:01ddb8e35845 66 }
kenjiArai 0:01ddb8e35845 67
kenjiArai 2:2ee7a7260cbf 68 uint32_t get_RTCSEL(void)
kenjiArai 2:2ee7a7260cbf 69 {
kenjiArai 1:921a188e61c0 70 #if defined(TARGET_NUCLEO_F401RE) || defined(TARGET_NUCLEO_F411RE)
kenjiArai 1:921a188e61c0 71 return ((RCC->BDCR >> 8) & 0x03);
kenjiArai 1:921a188e61c0 72 #elif defined(TARGET_NUCLEO_L152RE)
kenjiArai 1:921a188e61c0 73 return ((RCC->CSR >> 16) & 0x03);
kenjiArai 1:921a188e61c0 74 #else
kenjiArai 1:921a188e61c0 75 return 0;
kenjiArai 1:921a188e61c0 76 #endif
kenjiArai 1:921a188e61c0 77 }
kenjiArai 1:921a188e61c0 78
kenjiArai 0:01ddb8e35845 79 #if defined(TARGET_NUCLEO_F401RE) || defined(TARGET_NUCLEO_F411RE) || defined(TARGET_NUCLEO_L152RE)
kenjiArai 0:01ddb8e35845 80 int32_t Set_RTC_LSE(void)
kenjiArai 0:01ddb8e35845 81 {
kenjiArai 0:01ddb8e35845 82 uint32_t timeout = 0;
kenjiArai 0:01ddb8e35845 83
kenjiArai 0:01ddb8e35845 84 //---------------------------- LSE Configuration -------------------------
kenjiArai 0:01ddb8e35845 85 // Enable Power Clock
kenjiArai 0:01ddb8e35845 86 __PWR_CLK_ENABLE();
kenjiArai 0:01ddb8e35845 87 // Enable write access to Backup domain
kenjiArai 0:01ddb8e35845 88 PWR->CR |= PWR_CR_DBP;
kenjiArai 0:01ddb8e35845 89 // Wait for Backup domain Write protection disable
kenjiArai 0:01ddb8e35845 90 timeout = HAL_GetTick() + DBP_TIMEOUT_VALUE;
kenjiArai 0:01ddb8e35845 91 while((PWR->CR & PWR_CR_DBP) == RESET) {
kenjiArai 0:01ddb8e35845 92 if(HAL_GetTick() >= timeout) {
kenjiArai 0:01ddb8e35845 93 PRINTF("Time-Out 1\r\n");
kenjiArai 0:01ddb8e35845 94 return NG;
kenjiArai 0:01ddb8e35845 95 }
kenjiArai 0:01ddb8e35845 96 }
kenjiArai 0:01ddb8e35845 97 // Reset LSEON and LSEBYP bits before configuring the LSE ----------------
kenjiArai 0:01ddb8e35845 98 __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
kenjiArai 0:01ddb8e35845 99 // Get timeout
kenjiArai 0:01ddb8e35845 100 timeout = HAL_GetTick() + TIMEOUT;
kenjiArai 0:01ddb8e35845 101 // Wait till LSE is ready
kenjiArai 0:01ddb8e35845 102 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) {
kenjiArai 0:01ddb8e35845 103 if(HAL_GetTick() >= timeout) {
kenjiArai 0:01ddb8e35845 104 PRINTF("Time-Out 2\r\n");
kenjiArai 0:01ddb8e35845 105 return NG;
kenjiArai 0:01ddb8e35845 106 }
kenjiArai 0:01ddb8e35845 107 }
kenjiArai 0:01ddb8e35845 108 // Set the new LSE configuration -----------------------------------------
kenjiArai 0:01ddb8e35845 109 __HAL_RCC_LSE_CONFIG(RCC_LSE_ON);
kenjiArai 0:01ddb8e35845 110 // Get timeout
kenjiArai 0:01ddb8e35845 111 timeout = HAL_GetTick() + TIMEOUT;
kenjiArai 0:01ddb8e35845 112 // Wait till LSE is ready
kenjiArai 0:01ddb8e35845 113 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) {
kenjiArai 0:01ddb8e35845 114 if(HAL_GetTick() >= timeout) {
kenjiArai 0:01ddb8e35845 115 PRINTF("Time-Out 3\r\n");
kenjiArai 0:01ddb8e35845 116 return NG;
kenjiArai 0:01ddb8e35845 117 }
kenjiArai 0:01ddb8e35845 118 }
kenjiArai 0:01ddb8e35845 119 PRINTF("OK");
kenjiArai 0:01ddb8e35845 120 return OK;
kenjiArai 0:01ddb8e35845 121 }
kenjiArai 0:01ddb8e35845 122
kenjiArai 0:01ddb8e35845 123 int32_t Set_RTC_LSI(void)
kenjiArai 0:01ddb8e35845 124 {
kenjiArai 0:01ddb8e35845 125 uint32_t timeout = 0;
kenjiArai 0:01ddb8e35845 126
kenjiArai 0:01ddb8e35845 127 // Enable Power clock
kenjiArai 0:01ddb8e35845 128 __PWR_CLK_ENABLE();
kenjiArai 0:01ddb8e35845 129 // Enable access to Backup domain
kenjiArai 0:01ddb8e35845 130 HAL_PWR_EnableBkUpAccess();
kenjiArai 0:01ddb8e35845 131 // Reset Backup domain
kenjiArai 0:01ddb8e35845 132 __HAL_RCC_BACKUPRESET_FORCE();
kenjiArai 0:01ddb8e35845 133 __HAL_RCC_BACKUPRESET_RELEASE();
kenjiArai 0:01ddb8e35845 134 // Enable Power Clock
kenjiArai 0:01ddb8e35845 135 __PWR_CLK_ENABLE();
kenjiArai 0:01ddb8e35845 136 // Enable write access to Backup domain
kenjiArai 0:01ddb8e35845 137 PWR->CR |= PWR_CR_DBP;
kenjiArai 0:01ddb8e35845 138 // Wait for Backup domain Write protection disable
kenjiArai 0:01ddb8e35845 139 timeout = HAL_GetTick() + DBP_TIMEOUT_VALUE;
kenjiArai 0:01ddb8e35845 140 while((PWR->CR & PWR_CR_DBP) == RESET) {
kenjiArai 0:01ddb8e35845 141 if(HAL_GetTick() >= timeout) {
kenjiArai 0:01ddb8e35845 142 return NG;
kenjiArai 0:01ddb8e35845 143 }
kenjiArai 0:01ddb8e35845 144 }
kenjiArai 0:01ddb8e35845 145 __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
kenjiArai 0:01ddb8e35845 146 // Enable LSI
kenjiArai 0:01ddb8e35845 147 __HAL_RCC_LSI_ENABLE();
kenjiArai 0:01ddb8e35845 148 timeout = HAL_GetTick() + TIMEOUT;
kenjiArai 0:01ddb8e35845 149 // Wait till LSI is ready
kenjiArai 0:01ddb8e35845 150 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) {
kenjiArai 0:01ddb8e35845 151 if(HAL_GetTick() >= timeout) {
kenjiArai 0:01ddb8e35845 152 return NG;
kenjiArai 0:01ddb8e35845 153 }
kenjiArai 0:01ddb8e35845 154 }
kenjiArai 0:01ddb8e35845 155 // Connect LSI to RTC
kenjiArai 0:01ddb8e35845 156 __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSI);
kenjiArai 0:01ddb8e35845 157 __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI);
kenjiArai 0:01ddb8e35845 158 return OK;
kenjiArai 0:01ddb8e35845 159 }
kenjiArai 0:01ddb8e35845 160
kenjiArai 0:01ddb8e35845 161 int32_t rtc_external_osc_init(void)
kenjiArai 0:01ddb8e35845 162 {
kenjiArai 0:01ddb8e35845 163 // Enable Power clock
kenjiArai 0:01ddb8e35845 164 __PWR_CLK_ENABLE();
kenjiArai 0:01ddb8e35845 165 // Enable access to Backup domain
kenjiArai 0:01ddb8e35845 166 HAL_PWR_EnableBkUpAccess();
kenjiArai 0:01ddb8e35845 167 // Reset Backup domain
kenjiArai 0:01ddb8e35845 168 __HAL_RCC_BACKUPRESET_FORCE();
kenjiArai 0:01ddb8e35845 169 __HAL_RCC_BACKUPRESET_RELEASE();
kenjiArai 0:01ddb8e35845 170 // Enable LSE Oscillator
kenjiArai 0:01ddb8e35845 171 if (Set_RTC_LSE() == OK) {
kenjiArai 0:01ddb8e35845 172 // Connect LSE to RTC
kenjiArai 0:01ddb8e35845 173 __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSE);
kenjiArai 0:01ddb8e35845 174 __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE);
kenjiArai 0:01ddb8e35845 175 return OK;
kenjiArai 0:01ddb8e35845 176 } else {
kenjiArai 0:01ddb8e35845 177 Set_RTC_LSI();
kenjiArai 0:01ddb8e35845 178 return NG;
kenjiArai 0:01ddb8e35845 179 }
kenjiArai 0:01ddb8e35845 180 }
kenjiArai 0:01ddb8e35845 181 #endif