Diff: targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_ARM_MICRO/startup_efm32hg.S

Revision:

577:15494b56c2f3

Parent:

525:c320967f86b9

Child:

593:78ee8643776a

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_ARM_MICRO/startup_efm32hg.S	Wed Jul 01 08:15:11 2015 +0100
@@ -0,0 +1,202 @@
+;/**************************************************************************//**
+; * @file startup_efm32hg.s
+; * @brief    CMSIS Core Device Startup File for
+; *           Silicon Labs EFM32HG Device Series
+; * @version 3.20.12
+; * @date     03. February 2012
+; *
+; * @note
+; * Copyright (C) 2012 ARM Limited. All rights reserved.
+; *
+; * @par
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M
+; * processor based microcontrollers.  This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * @par
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x0
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY, ALIGN=8
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+
+                DCD     DMA_IRQHandler        ; 0: DMA Interrupt
+                DCD     GPIO_EVEN_IRQHandler        ; 1: GPIO_EVEN Interrupt
+                DCD     TIMER0_IRQHandler        ; 2: TIMER0 Interrupt
+                DCD     ACMP0_IRQHandler        ; 3: ACMP0 Interrupt
+                DCD     ADC0_IRQHandler        ; 4: ADC0 Interrupt
+                DCD     I2C0_IRQHandler        ; 5: I2C0 Interrupt
+                DCD     GPIO_ODD_IRQHandler        ; 6: GPIO_ODD Interrupt
+                DCD     TIMER1_IRQHandler        ; 7: TIMER1 Interrupt
+                DCD     USART1_RX_IRQHandler        ; 8: USART1_RX Interrupt
+                DCD     USART1_TX_IRQHandler        ; 9: USART1_TX Interrupt
+                DCD     LEUART0_IRQHandler        ; 10: LEUART0 Interrupt
+                DCD     PCNT0_IRQHandler        ; 11: PCNT0 Interrupt
+                DCD     RTC_IRQHandler        ; 12: RTC Interrupt
+                DCD     CMU_IRQHandler        ; 13: CMU Interrupt
+                DCD     VCMP_IRQHandler        ; 14: VCMP Interrupt
+                DCD     MSC_IRQHandler        ; 15: MSC Interrupt
+                DCD     AES_IRQHandler        ; 16: AES Interrupt
+                DCD     USART0_RX_IRQHandler        ; 17: USART0_RX Interrupt
+                DCD     USART0_TX_IRQHandler        ; 18: USART0_TX Interrupt
+                DCD     USB_IRQHandler        ; 19: USB Interrupt
+                DCD     TIMER2_IRQHandler        ; 20: TIMER2 Interrupt
+
+__Vectors_End
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DMA_IRQHandler        [WEAK]
+                EXPORT  GPIO_EVEN_IRQHandler        [WEAK]
+                EXPORT  TIMER0_IRQHandler        [WEAK]
+                EXPORT  ACMP0_IRQHandler        [WEAK]
+                EXPORT  ADC0_IRQHandler        [WEAK]
+                EXPORT  I2C0_IRQHandler        [WEAK]
+                EXPORT  GPIO_ODD_IRQHandler        [WEAK]
+                EXPORT  TIMER1_IRQHandler        [WEAK]
+                EXPORT  USART1_RX_IRQHandler        [WEAK]
+                EXPORT  USART1_TX_IRQHandler        [WEAK]
+                EXPORT  LEUART0_IRQHandler        [WEAK]
+                EXPORT  PCNT0_IRQHandler        [WEAK]
+                EXPORT  RTC_IRQHandler        [WEAK]
+                EXPORT  CMU_IRQHandler        [WEAK]
+                EXPORT  VCMP_IRQHandler        [WEAK]
+                EXPORT  MSC_IRQHandler        [WEAK]
+                EXPORT  AES_IRQHandler        [WEAK]
+                EXPORT  USART0_RX_IRQHandler        [WEAK]
+                EXPORT  USART0_TX_IRQHandler        [WEAK]
+                EXPORT  USB_IRQHandler        [WEAK]
+                EXPORT  TIMER2_IRQHandler        [WEAK]
+
+
+DMA_IRQHandler
+GPIO_EVEN_IRQHandler
+TIMER0_IRQHandler
+ACMP0_IRQHandler
+ADC0_IRQHandler
+I2C0_IRQHandler
+GPIO_ODD_IRQHandler
+TIMER1_IRQHandler
+USART1_RX_IRQHandler
+USART1_TX_IRQHandler
+LEUART0_IRQHandler
+PCNT0_IRQHandler
+RTC_IRQHandler
+CMU_IRQHandler
+VCMP_IRQHandler
+MSC_IRQHandler
+AES_IRQHandler
+USART0_RX_IRQHandler
+USART0_TX_IRQHandler
+USB_IRQHandler
+TIMER2_IRQHandler
+                B       .
+                ENDP
+
+                ALIGN
+
+; User Initial Stack & Heap
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                END