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targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/CMSDK_CM4.h@580:3c14cb9b87c5, 2015-07-02 (annotated)

Committer:
mbed_official
Date:
Thu Jul 02 16:15:09 2015 +0100
Revision:
580:3c14cb9b87c5
Synchronized with git revision 213caf296f26963a7bea129b8ec4f33bbd1e6588



Full URL: https://github.com/mbedmicro/mbed/commit/213caf296f26963a7bea129b8ec4f33bbd1e6588/



commit of mps2

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UserRevisionLine numberNew contents of line
mbed_official 580:3c14cb9b87c5 1 /* MPS2 CMSIS Library
mbed_official 580:3c14cb9b87c5 2 *
mbed_official 580:3c14cb9b87c5 3 * Copyright (c) 2006-2015 ARM Limited
mbed_official 580:3c14cb9b87c5 4 * All rights reserved.
mbed_official 580:3c14cb9b87c5 5 *
mbed_official 580:3c14cb9b87c5 6 * Redistribution and use in source and binary forms, with or without
mbed_official 580:3c14cb9b87c5 7 * modification, are permitted provided that the following conditions are met:
mbed_official 580:3c14cb9b87c5 8 *
mbed_official 580:3c14cb9b87c5 9 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 580:3c14cb9b87c5 10 * this list of conditions and the following disclaimer.
mbed_official 580:3c14cb9b87c5 11 *
mbed_official 580:3c14cb9b87c5 12 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 580:3c14cb9b87c5 13 * this list of conditions and the following disclaimer in the documentation
mbed_official 580:3c14cb9b87c5 14 * and/or other materials provided with the distribution.
mbed_official 580:3c14cb9b87c5 15 *
mbed_official 580:3c14cb9b87c5 16 * 3. Neither the name of the copyright holder nor the names of its contributors
mbed_official 580:3c14cb9b87c5 17 * may be used to endorse or promote products derived from this software without
mbed_official 580:3c14cb9b87c5 18 * specific prior written permission.
mbed_official 580:3c14cb9b87c5 19 *
mbed_official 580:3c14cb9b87c5 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 580:3c14cb9b87c5 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 580:3c14cb9b87c5 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mbed_official 580:3c14cb9b87c5 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
mbed_official 580:3c14cb9b87c5 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mbed_official 580:3c14cb9b87c5 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mbed_official 580:3c14cb9b87c5 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 580:3c14cb9b87c5 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 580:3c14cb9b87c5 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mbed_official 580:3c14cb9b87c5 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 580:3c14cb9b87c5 30 * POSSIBILITY OF SUCH DAMAGE.
mbed_official 580:3c14cb9b87c5 31 *******************************************************************************
mbed_official 580:3c14cb9b87c5 32 * @file CMSDK_CM4.h
mbed_official 580:3c14cb9b87c5 33 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for
mbed_official 580:3c14cb9b87c5 34 * Device CMSDK_CM4
mbed_official 580:3c14cb9b87c5 35 * @version V3.01
mbed_official 580:3c14cb9b87c5 36 * @date 06. March 2012
mbed_official 580:3c14cb9b87c5 37 *
mbed_official 580:3c14cb9b87c5 38 * @note configured for CM7 without FPU
mbed_official 580:3c14cb9b87c5 39 *
mbed_official 580:3c14cb9b87c5 40 *******************************************************************************/
mbed_official 580:3c14cb9b87c5 41
mbed_official 580:3c14cb9b87c5 42
mbed_official 580:3c14cb9b87c5 43 #ifndef CMSDK_CM4_H
mbed_official 580:3c14cb9b87c5 44 #define CMSDK_CM4_H
mbed_official 580:3c14cb9b87c5 45
mbed_official 580:3c14cb9b87c5 46 #ifdef __cplusplus
mbed_official 580:3c14cb9b87c5 47 extern "C" {
mbed_official 580:3c14cb9b87c5 48 #endif
mbed_official 580:3c14cb9b87c5 49
mbed_official 580:3c14cb9b87c5 50 /** @addtogroup CMSDK_CM4_Definitions CMSDK_CM4 Definitions
mbed_official 580:3c14cb9b87c5 51 This file defines all structures and symbols for CMSDK_CM4:
mbed_official 580:3c14cb9b87c5 52 - registers and bitfields
mbed_official 580:3c14cb9b87c5 53 - peripheral base address
mbed_official 580:3c14cb9b87c5 54 - peripheral ID
mbed_official 580:3c14cb9b87c5 55 - Peripheral definitions
mbed_official 580:3c14cb9b87c5 56 @{
mbed_official 580:3c14cb9b87c5 57 */
mbed_official 580:3c14cb9b87c5 58
mbed_official 580:3c14cb9b87c5 59
mbed_official 580:3c14cb9b87c5 60 /******************************************************************************/
mbed_official 580:3c14cb9b87c5 61 /* Processor and Core Peripherals */
mbed_official 580:3c14cb9b87c5 62 /******************************************************************************/
mbed_official 580:3c14cb9b87c5 63 /** @addtogroup CMSDK_CM4_CMSIS Device CMSIS Definitions
mbed_official 580:3c14cb9b87c5 64 Configuration of the Cortex-M4 Processor and Core Peripherals
mbed_official 580:3c14cb9b87c5 65 @{
mbed_official 580:3c14cb9b87c5 66 */
mbed_official 580:3c14cb9b87c5 67
mbed_official 580:3c14cb9b87c5 68 /*
mbed_official 580:3c14cb9b87c5 69 * ==========================================================================
mbed_official 580:3c14cb9b87c5 70 * ---------- Interrupt Number Definition -----------------------------------
mbed_official 580:3c14cb9b87c5 71 * ==========================================================================
mbed_official 580:3c14cb9b87c5 72 */
mbed_official 580:3c14cb9b87c5 73
mbed_official 580:3c14cb9b87c5 74 typedef enum IRQn
mbed_official 580:3c14cb9b87c5 75 {
mbed_official 580:3c14cb9b87c5 76 /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/
mbed_official 580:3c14cb9b87c5 77 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
mbed_official 580:3c14cb9b87c5 78 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
mbed_official 580:3c14cb9b87c5 79 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
mbed_official 580:3c14cb9b87c5 80 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
mbed_official 580:3c14cb9b87c5 81 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
mbed_official 580:3c14cb9b87c5 82 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
mbed_official 580:3c14cb9b87c5 83 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
mbed_official 580:3c14cb9b87c5 84 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
mbed_official 580:3c14cb9b87c5 85
mbed_official 580:3c14cb9b87c5 86 /****** CMSDK Specific Interrupt Numbers *******************************************************/
mbed_official 580:3c14cb9b87c5 87 UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */
mbed_official 580:3c14cb9b87c5 88 UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */
mbed_official 580:3c14cb9b87c5 89 UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */
mbed_official 580:3c14cb9b87c5 90 UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */
mbed_official 580:3c14cb9b87c5 91 UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */
mbed_official 580:3c14cb9b87c5 92 UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */
mbed_official 580:3c14cb9b87c5 93 // UARTRX3_IRQn = 6, /*!< UART 2 RX Interrupt //only used in extended version */
mbed_official 580:3c14cb9b87c5 94 // UARTTX3_IRQn = 7, /*!< UART 2 TX Interrupt //only used in extended version */
mbed_official 580:3c14cb9b87c5 95 PORT0_ALL_IRQn = 6, /*!< Port 1 combined Interrupt */
mbed_official 580:3c14cb9b87c5 96 PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */
mbed_official 580:3c14cb9b87c5 97 TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */
mbed_official 580:3c14cb9b87c5 98 TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */
mbed_official 580:3c14cb9b87c5 99 DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */
mbed_official 580:3c14cb9b87c5 100 SPI_IRQn = 11, /*!< SPI Interrupt */
mbed_official 580:3c14cb9b87c5 101 UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */
mbed_official 580:3c14cb9b87c5 102 ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */
mbed_official 580:3c14cb9b87c5 103 I2S_IRQn = 14, /*!< I2S Interrupt */
mbed_official 580:3c14cb9b87c5 104 TSC_IRQn = 15, /* Touch Screen Interrupt */
mbed_official 580:3c14cb9b87c5 105 // DMA_IRQn = 15, /* PL230 DMA Done + Error Interrupt */
mbed_official 580:3c14cb9b87c5 106 PORT0_0_IRQn = 16, /*!< All P0 I/O pins can be used as interrupt source. */
mbed_official 580:3c14cb9b87c5 107 PORT0_1_IRQn = 17, /*!< There are 16 pins in total */
mbed_official 580:3c14cb9b87c5 108 PORT0_2_IRQn = 18,
mbed_official 580:3c14cb9b87c5 109 PORT0_3_IRQn = 19,
mbed_official 580:3c14cb9b87c5 110 PORT0_4_IRQn = 20,
mbed_official 580:3c14cb9b87c5 111 PORT0_5_IRQn = 21,
mbed_official 580:3c14cb9b87c5 112 PORT0_6_IRQn = 22,
mbed_official 580:3c14cb9b87c5 113 PORT0_7_IRQn = 23,
mbed_official 580:3c14cb9b87c5 114 PORT0_8_IRQn = 24,
mbed_official 580:3c14cb9b87c5 115 PORT0_9_IRQn = 25,
mbed_official 580:3c14cb9b87c5 116 PORT0_10_IRQn = 26,
mbed_official 580:3c14cb9b87c5 117 PORT0_11_IRQn = 27,
mbed_official 580:3c14cb9b87c5 118 PORT0_12_IRQn = 28,
mbed_official 580:3c14cb9b87c5 119 PORT0_13_IRQn = 29,
mbed_official 580:3c14cb9b87c5 120 PORT0_14_IRQn = 30,
mbed_official 580:3c14cb9b87c5 121 PORT0_15_IRQn = 31,
mbed_official 580:3c14cb9b87c5 122 } IRQn_Type;
mbed_official 580:3c14cb9b87c5 123
mbed_official 580:3c14cb9b87c5 124
mbed_official 580:3c14cb9b87c5 125 /*
mbed_official 580:3c14cb9b87c5 126 * ==========================================================================
mbed_official 580:3c14cb9b87c5 127 * ----------- Processor and Core Peripheral Section ------------------------
mbed_official 580:3c14cb9b87c5 128 * ==========================================================================
mbed_official 580:3c14cb9b87c5 129 */
mbed_official 580:3c14cb9b87c5 130
mbed_official 580:3c14cb9b87c5 131 /* Configuration of the Cortex-M4 Processor and Core Peripherals */
mbed_official 580:3c14cb9b87c5 132 #define __CM4_REV 0x0001 /*!< Core Revision r0p1 */
mbed_official 580:3c14cb9b87c5 133 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
mbed_official 580:3c14cb9b87c5 134 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
mbed_official 580:3c14cb9b87c5 135 #define __MPU_PRESENT 1 /*!< MPU present or not */
mbed_official 580:3c14cb9b87c5 136 #define __FPU_PRESENT 1 /*!< FPU present or not */
mbed_official 580:3c14cb9b87c5 137
mbed_official 580:3c14cb9b87c5 138 /*@}*/ /* end of group CMSDK_CM4_CMSIS */
mbed_official 580:3c14cb9b87c5 139
mbed_official 580:3c14cb9b87c5 140
mbed_official 580:3c14cb9b87c5 141 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
mbed_official 580:3c14cb9b87c5 142 #include "system_CMSDK_CM4.h" /* CMSDK_CM4 System include file */
mbed_official 580:3c14cb9b87c5 143
mbed_official 580:3c14cb9b87c5 144
mbed_official 580:3c14cb9b87c5 145 /******************************************************************************/
mbed_official 580:3c14cb9b87c5 146 /* Device Specific Peripheral registers structures */
mbed_official 580:3c14cb9b87c5 147 /******************************************************************************/
mbed_official 580:3c14cb9b87c5 148 /** @addtogroup CMSDK_CM4_Peripherals CMSDK_CM4 Peripherals
mbed_official 580:3c14cb9b87c5 149 CMSDK_CM4 Device Specific Peripheral registers structures
mbed_official 580:3c14cb9b87c5 150 @{
mbed_official 580:3c14cb9b87c5 151 */
mbed_official 580:3c14cb9b87c5 152
mbed_official 580:3c14cb9b87c5 153 #if defined ( __CC_ARM )
mbed_official 580:3c14cb9b87c5 154 #pragma anon_unions
mbed_official 580:3c14cb9b87c5 155 #endif
mbed_official 580:3c14cb9b87c5 156
mbed_official 580:3c14cb9b87c5 157 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
mbed_official 580:3c14cb9b87c5 158 /** @addtogroup CMSDK_UART CMSDK Universal Asynchronous Receiver/Transmitter
mbed_official 580:3c14cb9b87c5 159 memory mapped structure for CMSDK_UART
mbed_official 580:3c14cb9b87c5 160 @{
mbed_official 580:3c14cb9b87c5 161 */
mbed_official 580:3c14cb9b87c5 162 typedef struct
mbed_official 580:3c14cb9b87c5 163 {
mbed_official 580:3c14cb9b87c5 164 __IO uint32_t DATA; /*!< Offset: 0x000 Data Register (R/W) */
mbed_official 580:3c14cb9b87c5 165 __IO uint32_t STATE; /*!< Offset: 0x004 Status Register (R/W) */
mbed_official 580:3c14cb9b87c5 166 __IO uint32_t CTRL; /*!< Offset: 0x008 Control Register (R/W) */
mbed_official 580:3c14cb9b87c5 167 union {
mbed_official 580:3c14cb9b87c5 168 __I uint32_t INTSTATUS; /*!< Offset: 0x00C Interrupt Status Register (R/ ) */
mbed_official 580:3c14cb9b87c5 169 __O uint32_t INTCLEAR; /*!< Offset: 0x00C Interrupt Clear Register ( /W) */
mbed_official 580:3c14cb9b87c5 170 };
mbed_official 580:3c14cb9b87c5 171 __IO uint32_t BAUDDIV; /*!< Offset: 0x010 Baudrate Divider Register (R/W) */
mbed_official 580:3c14cb9b87c5 172
mbed_official 580:3c14cb9b87c5 173 } CMSDK_UART_TypeDef;
mbed_official 580:3c14cb9b87c5 174
mbed_official 580:3c14cb9b87c5 175 /* CMSDK_UART DATA Register Definitions */
mbed_official 580:3c14cb9b87c5 176
mbed_official 580:3c14cb9b87c5 177 #define CMSDK_UART_DATA_Pos 0 /*!< CMSDK_UART_DATA_Pos: DATA Position */
mbed_official 580:3c14cb9b87c5 178 #define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /*!< CMSDK_UART DATA: DATA Mask */
mbed_official 580:3c14cb9b87c5 179
mbed_official 580:3c14cb9b87c5 180 #define CMSDK_UART_STATE_RXOR_Pos 3 /*!< CMSDK_UART STATE: RXOR Position */
mbed_official 580:3c14cb9b87c5 181 #define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /*!< CMSDK_UART STATE: RXOR Mask */
mbed_official 580:3c14cb9b87c5 182
mbed_official 580:3c14cb9b87c5 183 #define CMSDK_UART_STATE_TXOR_Pos 2 /*!< CMSDK_UART STATE: TXOR Position */
mbed_official 580:3c14cb9b87c5 184 #define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /*!< CMSDK_UART STATE: TXOR Mask */
mbed_official 580:3c14cb9b87c5 185
mbed_official 580:3c14cb9b87c5 186 #define CMSDK_UART_STATE_RXBF_Pos 1 /*!< CMSDK_UART STATE: RXBF Position */
mbed_official 580:3c14cb9b87c5 187 #define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /*!< CMSDK_UART STATE: RXBF Mask */
mbed_official 580:3c14cb9b87c5 188
mbed_official 580:3c14cb9b87c5 189 #define CMSDK_UART_STATE_TXBF_Pos 0 /*!< CMSDK_UART STATE: TXBF Position */
mbed_official 580:3c14cb9b87c5 190 #define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /*!< CMSDK_UART STATE: TXBF Mask */
mbed_official 580:3c14cb9b87c5 191
mbed_official 580:3c14cb9b87c5 192 #define CMSDK_UART_CTRL_HSTM_Pos 6 /*!< CMSDK_UART CTRL: HSTM Position */
mbed_official 580:3c14cb9b87c5 193 #define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /*!< CMSDK_UART CTRL: HSTM Mask */
mbed_official 580:3c14cb9b87c5 194
mbed_official 580:3c14cb9b87c5 195 #define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /*!< CMSDK_UART CTRL: RXORIRQEN Position */
mbed_official 580:3c14cb9b87c5 196 #define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /*!< CMSDK_UART CTRL: RXORIRQEN Mask */
mbed_official 580:3c14cb9b87c5 197
mbed_official 580:3c14cb9b87c5 198 #define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /*!< CMSDK_UART CTRL: TXORIRQEN Position */
mbed_official 580:3c14cb9b87c5 199 #define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /*!< CMSDK_UART CTRL: TXORIRQEN Mask */
mbed_official 580:3c14cb9b87c5 200
mbed_official 580:3c14cb9b87c5 201 #define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /*!< CMSDK_UART CTRL: RXIRQEN Position */
mbed_official 580:3c14cb9b87c5 202 #define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /*!< CMSDK_UART CTRL: RXIRQEN Mask */
mbed_official 580:3c14cb9b87c5 203
mbed_official 580:3c14cb9b87c5 204 #define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /*!< CMSDK_UART CTRL: TXIRQEN Position */
mbed_official 580:3c14cb9b87c5 205 #define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /*!< CMSDK_UART CTRL: TXIRQEN Mask */
mbed_official 580:3c14cb9b87c5 206
mbed_official 580:3c14cb9b87c5 207 #define CMSDK_UART_CTRL_RXEN_Pos 1 /*!< CMSDK_UART CTRL: RXEN Position */
mbed_official 580:3c14cb9b87c5 208 #define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /*!< CMSDK_UART CTRL: RXEN Mask */
mbed_official 580:3c14cb9b87c5 209
mbed_official 580:3c14cb9b87c5 210 #define CMSDK_UART_CTRL_TXEN_Pos 0 /*!< CMSDK_UART CTRL: TXEN Position */
mbed_official 580:3c14cb9b87c5 211 #define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /*!< CMSDK_UART CTRL: TXEN Mask */
mbed_official 580:3c14cb9b87c5 212
mbed_official 580:3c14cb9b87c5 213 #define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /*!< CMSDK_UART CTRL: RXORIRQ Position */
mbed_official 580:3c14cb9b87c5 214 #define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /*!< CMSDK_UART CTRL: RXORIRQ Mask */
mbed_official 580:3c14cb9b87c5 215
mbed_official 580:3c14cb9b87c5 216 #define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /*!< CMSDK_UART CTRL: TXORIRQ Position */
mbed_official 580:3c14cb9b87c5 217 #define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQ_Pos) /*!< CMSDK_UART CTRL: TXORIRQ Mask */
mbed_official 580:3c14cb9b87c5 218
mbed_official 580:3c14cb9b87c5 219 #define CMSDK_UART_CTRL_RXIRQ_Pos 1 /*!< CMSDK_UART CTRL: RXIRQ Position */
mbed_official 580:3c14cb9b87c5 220 #define CMSDK_UART_CTRL_RXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQ_Pos) /*!< CMSDK_UART CTRL: RXIRQ Mask */
mbed_official 580:3c14cb9b87c5 221
mbed_official 580:3c14cb9b87c5 222 #define CMSDK_UART_CTRL_TXIRQ_Pos 0 /*!< CMSDK_UART CTRL: TXIRQ Position */
mbed_official 580:3c14cb9b87c5 223 #define CMSDK_UART_CTRL_TXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQ_Pos) /*!< CMSDK_UART CTRL: TXIRQ Mask */
mbed_official 580:3c14cb9b87c5 224
mbed_official 580:3c14cb9b87c5 225 #define CMSDK_UART_BAUDDIV_Pos 0 /*!< CMSDK_UART BAUDDIV: BAUDDIV Position */
mbed_official 580:3c14cb9b87c5 226 #define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /*!< CMSDK_UART BAUDDIV: BAUDDIV Mask */
mbed_official 580:3c14cb9b87c5 227
mbed_official 580:3c14cb9b87c5 228 /*@}*/ /* end of group CMSDK_UART */
mbed_official 580:3c14cb9b87c5 229
mbed_official 580:3c14cb9b87c5 230
mbed_official 580:3c14cb9b87c5 231 /*----------------------------- Timer (TIMER) -------------------------------*/
mbed_official 580:3c14cb9b87c5 232 /** @addtogroup CMSDK_TIMER CMSDK Timer
mbed_official 580:3c14cb9b87c5 233 @{
mbed_official 580:3c14cb9b87c5 234 */
mbed_official 580:3c14cb9b87c5 235 typedef struct
mbed_official 580:3c14cb9b87c5 236 {
mbed_official 580:3c14cb9b87c5 237 __IO uint32_t CTRL; /*!< Offset: 0x000 Control Register (R/W) */
mbed_official 580:3c14cb9b87c5 238 __IO uint32_t VALUE; /*!< Offset: 0x004 Current Value Register (R/W) */
mbed_official 580:3c14cb9b87c5 239 __IO uint32_t RELOAD; /*!< Offset: 0x008 Reload Value Register (R/W) */
mbed_official 580:3c14cb9b87c5 240 union {
mbed_official 580:3c14cb9b87c5 241 __I uint32_t INTSTATUS; /*!< Offset: 0x00C Interrupt Status Register (R/ ) */
mbed_official 580:3c14cb9b87c5 242 __O uint32_t INTCLEAR; /*!< Offset: 0x00C Interrupt Clear Register ( /W) */
mbed_official 580:3c14cb9b87c5 243 };
mbed_official 580:3c14cb9b87c5 244
mbed_official 580:3c14cb9b87c5 245 } CMSDK_TIMER_TypeDef;
mbed_official 580:3c14cb9b87c5 246
mbed_official 580:3c14cb9b87c5 247 /* CMSDK_TIMER CTRL Register Definitions */
mbed_official 580:3c14cb9b87c5 248
mbed_official 580:3c14cb9b87c5 249 #define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /*!< CMSDK_TIMER CTRL: IRQEN Position */
mbed_official 580:3c14cb9b87c5 250 #define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /*!< CMSDK_TIMER CTRL: IRQEN Mask */
mbed_official 580:3c14cb9b87c5 251
mbed_official 580:3c14cb9b87c5 252 #define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /*!< CMSDK_TIMER CTRL: SELEXTCLK Position */
mbed_official 580:3c14cb9b87c5 253 #define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /*!< CMSDK_TIMER CTRL: SELEXTCLK Mask */
mbed_official 580:3c14cb9b87c5 254
mbed_official 580:3c14cb9b87c5 255 #define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /*!< CMSDK_TIMER CTRL: SELEXTEN Position */
mbed_official 580:3c14cb9b87c5 256 #define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /*!< CMSDK_TIMER CTRL: SELEXTEN Mask */
mbed_official 580:3c14cb9b87c5 257
mbed_official 580:3c14cb9b87c5 258 #define CMSDK_TIMER_CTRL_EN_Pos 0 /*!< CMSDK_TIMER CTRL: EN Position */
mbed_official 580:3c14cb9b87c5 259 #define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /*!< CMSDK_TIMER CTRL: EN Mask */
mbed_official 580:3c14cb9b87c5 260
mbed_official 580:3c14cb9b87c5 261 #define CMSDK_TIMER_VAL_CURRENT_Pos 0 /*!< CMSDK_TIMER VALUE: CURRENT Position */
mbed_official 580:3c14cb9b87c5 262 #define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /*!< CMSDK_TIMER VALUE: CURRENT Mask */
mbed_official 580:3c14cb9b87c5 263
mbed_official 580:3c14cb9b87c5 264 #define CMSDK_TIMER_RELOAD_VAL_Pos 0 /*!< CMSDK_TIMER RELOAD: RELOAD Position */
mbed_official 580:3c14cb9b87c5 265 #define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /*!< CMSDK_TIMER RELOAD: RELOAD Mask */
mbed_official 580:3c14cb9b87c5 266
mbed_official 580:3c14cb9b87c5 267 #define CMSDK_TIMER_INTSTATUS_Pos 0 /*!< CMSDK_TIMER INTSTATUS: INTSTATUSPosition */
mbed_official 580:3c14cb9b87c5 268 #define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /*!< CMSDK_TIMER INTSTATUS: INTSTATUSMask */
mbed_official 580:3c14cb9b87c5 269
mbed_official 580:3c14cb9b87c5 270 #define CMSDK_TIMER_INTCLEAR_Pos 0 /*!< CMSDK_TIMER INTCLEAR: INTCLEAR Position */
mbed_official 580:3c14cb9b87c5 271 #define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /*!< CMSDK_TIMER INTCLEAR: INTCLEAR Mask */
mbed_official 580:3c14cb9b87c5 272
mbed_official 580:3c14cb9b87c5 273 /*@}*/ /* end of group CMSDK_TIMER */
mbed_official 580:3c14cb9b87c5 274
mbed_official 580:3c14cb9b87c5 275
mbed_official 580:3c14cb9b87c5 276 /*------------- Timer (TIM) --------------------------------------------------*/
mbed_official 580:3c14cb9b87c5 277 // <g> Timer (TIM)
mbed_official 580:3c14cb9b87c5 278
mbed_official 580:3c14cb9b87c5 279 /** @addtogroup CMSDK_DualTIMER CMSDK Dual Timer
mbed_official 580:3c14cb9b87c5 280 @{
mbed_official 580:3c14cb9b87c5 281 */
mbed_official 580:3c14cb9b87c5 282
mbed_official 580:3c14cb9b87c5 283 typedef struct
mbed_official 580:3c14cb9b87c5 284 {
mbed_official 580:3c14cb9b87c5 285 __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
mbed_official 580:3c14cb9b87c5 286 __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
mbed_official 580:3c14cb9b87c5 287 __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
mbed_official 580:3c14cb9b87c5 288 // <o.7> TimerEn: Timer Enable
mbed_official 580:3c14cb9b87c5 289 // <o.6> TimerMode: Timer Mode
mbed_official 580:3c14cb9b87c5 290 // <0=> Freerunning-mode
mbed_official 580:3c14cb9b87c5 291 // <1=> Periodic mode
mbed_official 580:3c14cb9b87c5 292 // <o.5> IntEnable: Interrupt Enable
mbed_official 580:3c14cb9b87c5 293 // <o.2..3> TimerPre: Timer Prescale
mbed_official 580:3c14cb9b87c5 294 // <0=> / 1
mbed_official 580:3c14cb9b87c5 295 // <1=> / 16
mbed_official 580:3c14cb9b87c5 296 // <2=> / 256
mbed_official 580:3c14cb9b87c5 297 // <3=> Undefined!
mbed_official 580:3c14cb9b87c5 298 // <o.1> TimerSize: Timer Size
mbed_official 580:3c14cb9b87c5 299 // <0=> 16-bit counter
mbed_official 580:3c14cb9b87c5 300 // <1=> 32-bit counter
mbed_official 580:3c14cb9b87c5 301 // <o.0> OneShot: One-shoot mode
mbed_official 580:3c14cb9b87c5 302 // <0=> Wrapping mode
mbed_official 580:3c14cb9b87c5 303 // <1=> One-shot mode
mbed_official 580:3c14cb9b87c5 304 // </h>
mbed_official 580:3c14cb9b87c5 305 __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
mbed_official 580:3c14cb9b87c5 306 __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
mbed_official 580:3c14cb9b87c5 307 __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
mbed_official 580:3c14cb9b87c5 308 __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
mbed_official 580:3c14cb9b87c5 309 uint32_t RESERVED0;
mbed_official 580:3c14cb9b87c5 310 __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
mbed_official 580:3c14cb9b87c5 311 __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
mbed_official 580:3c14cb9b87c5 312 __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
mbed_official 580:3c14cb9b87c5 313 // <o.7> TimerEn: Timer Enable
mbed_official 580:3c14cb9b87c5 314 // <o.6> TimerMode: Timer Mode
mbed_official 580:3c14cb9b87c5 315 // <0=> Freerunning-mode
mbed_official 580:3c14cb9b87c5 316 // <1=> Periodic mode
mbed_official 580:3c14cb9b87c5 317 // <o.5> IntEnable: Interrupt Enable
mbed_official 580:3c14cb9b87c5 318 // <o.2..3> TimerPre: Timer Prescale
mbed_official 580:3c14cb9b87c5 319 // <0=> / 1
mbed_official 580:3c14cb9b87c5 320 // <1=> / 16
mbed_official 580:3c14cb9b87c5 321 // <2=> / 256
mbed_official 580:3c14cb9b87c5 322 // <3=> Undefined!
mbed_official 580:3c14cb9b87c5 323 // <o.1> TimerSize: Timer Size
mbed_official 580:3c14cb9b87c5 324 // <0=> 16-bit counter
mbed_official 580:3c14cb9b87c5 325 // <1=> 32-bit counter
mbed_official 580:3c14cb9b87c5 326 // <o.0> OneShot: One-shoot mode
mbed_official 580:3c14cb9b87c5 327 // <0=> Wrapping mode
mbed_official 580:3c14cb9b87c5 328 // <1=> One-shot mode
mbed_official 580:3c14cb9b87c5 329 // </h>
mbed_official 580:3c14cb9b87c5 330 __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
mbed_official 580:3c14cb9b87c5 331 __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
mbed_official 580:3c14cb9b87c5 332 __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
mbed_official 580:3c14cb9b87c5 333 __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
mbed_official 580:3c14cb9b87c5 334 uint32_t RESERVED1[945];
mbed_official 580:3c14cb9b87c5 335 __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */
mbed_official 580:3c14cb9b87c5 336 __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
mbed_official 580:3c14cb9b87c5 337 } CMSDK_DUALTIMER_BOTH_TypeDef;
mbed_official 580:3c14cb9b87c5 338
mbed_official 580:3c14cb9b87c5 339 #define CMSDK_DUALTIMER1_LOAD_Pos 0 /*!< CMSDK_DUALTIMER1 LOAD: LOAD Position */
mbed_official 580:3c14cb9b87c5 340 #define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /*!< CMSDK_DUALTIMER1 LOAD: LOAD Mask */
mbed_official 580:3c14cb9b87c5 341
mbed_official 580:3c14cb9b87c5 342 #define CMSDK_DUALTIMER1_VALUE_Pos 0 /*!< CMSDK_DUALTIMER1 VALUE: VALUE Position */
mbed_official 580:3c14cb9b87c5 343 #define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /*!< CMSDK_DUALTIMER1 VALUE: VALUE Mask */
mbed_official 580:3c14cb9b87c5 344
mbed_official 580:3c14cb9b87c5 345 #define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /*!< CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */
mbed_official 580:3c14cb9b87c5 346 #define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /*!< CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */
mbed_official 580:3c14cb9b87c5 347
mbed_official 580:3c14cb9b87c5 348 #define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /*!< CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */
mbed_official 580:3c14cb9b87c5 349 #define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /*!< CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */
mbed_official 580:3c14cb9b87c5 350
mbed_official 580:3c14cb9b87c5 351 #define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /*!< CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */
mbed_official 580:3c14cb9b87c5 352 #define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /*!< CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */
mbed_official 580:3c14cb9b87c5 353
mbed_official 580:3c14cb9b87c5 354 #define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /*!< CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */
mbed_official 580:3c14cb9b87c5 355 #define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /*!< CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */
mbed_official 580:3c14cb9b87c5 356
mbed_official 580:3c14cb9b87c5 357 #define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /*!< CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */
mbed_official 580:3c14cb9b87c5 358 #define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /*!< CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */
mbed_official 580:3c14cb9b87c5 359
mbed_official 580:3c14cb9b87c5 360 #define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /*!< CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */
mbed_official 580:3c14cb9b87c5 361 #define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /*!< CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
mbed_official 580:3c14cb9b87c5 362
mbed_official 580:3c14cb9b87c5 363 #define CMSDK_DUALTIMER1_INTCLR_Pos 0 /*!< CMSDK_DUALTIMER1 INTCLR: INT Clear Position */
mbed_official 580:3c14cb9b87c5 364 #define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /*!< CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */
mbed_official 580:3c14cb9b87c5 365
mbed_official 580:3c14cb9b87c5 366 #define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /*!< CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */
mbed_official 580:3c14cb9b87c5 367 #define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /*!< CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */
mbed_official 580:3c14cb9b87c5 368
mbed_official 580:3c14cb9b87c5 369 #define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /*!< CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */
mbed_official 580:3c14cb9b87c5 370 #define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /*!< CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */
mbed_official 580:3c14cb9b87c5 371
mbed_official 580:3c14cb9b87c5 372 #define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /*!< CMSDK_DUALTIMER1 BGLOAD: Background Load Position */
mbed_official 580:3c14cb9b87c5 373 #define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /*!< CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */
mbed_official 580:3c14cb9b87c5 374
mbed_official 580:3c14cb9b87c5 375 #define CMSDK_DUALTIMER2_LOAD_Pos 0 /*!< CMSDK_DUALTIMER2 LOAD: LOAD Position */
mbed_official 580:3c14cb9b87c5 376 #define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /*!< CMSDK_DUALTIMER2 LOAD: LOAD Mask */
mbed_official 580:3c14cb9b87c5 377
mbed_official 580:3c14cb9b87c5 378 #define CMSDK_DUALTIMER2_VALUE_Pos 0 /*!< CMSDK_DUALTIMER2 VALUE: VALUE Position */
mbed_official 580:3c14cb9b87c5 379 #define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /*!< CMSDK_DUALTIMER2 VALUE: VALUE Mask */
mbed_official 580:3c14cb9b87c5 380
mbed_official 580:3c14cb9b87c5 381 #define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /*!< CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */
mbed_official 580:3c14cb9b87c5 382 #define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /*!< CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */
mbed_official 580:3c14cb9b87c5 383
mbed_official 580:3c14cb9b87c5 384 #define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /*!< CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */
mbed_official 580:3c14cb9b87c5 385 #define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /*!< CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */
mbed_official 580:3c14cb9b87c5 386
mbed_official 580:3c14cb9b87c5 387 #define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /*!< CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */
mbed_official 580:3c14cb9b87c5 388 #define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /*!< CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */
mbed_official 580:3c14cb9b87c5 389
mbed_official 580:3c14cb9b87c5 390 #define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /*!< CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */
mbed_official 580:3c14cb9b87c5 391 #define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /*!< CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */
mbed_official 580:3c14cb9b87c5 392
mbed_official 580:3c14cb9b87c5 393 #define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /*!< CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */
mbed_official 580:3c14cb9b87c5 394 #define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /*!< CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */
mbed_official 580:3c14cb9b87c5 395
mbed_official 580:3c14cb9b87c5 396 #define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /*!< CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */
mbed_official 580:3c14cb9b87c5 397 #define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /*!< CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
mbed_official 580:3c14cb9b87c5 398
mbed_official 580:3c14cb9b87c5 399 #define CMSDK_DUALTIMER2_INTCLR_Pos 0 /*!< CMSDK_DUALTIMER2 INTCLR: INT Clear Position */
mbed_official 580:3c14cb9b87c5 400 #define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /*!< CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */
mbed_official 580:3c14cb9b87c5 401
mbed_official 580:3c14cb9b87c5 402 #define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /*!< CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */
mbed_official 580:3c14cb9b87c5 403 #define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /*!< CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */
mbed_official 580:3c14cb9b87c5 404
mbed_official 580:3c14cb9b87c5 405 #define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /*!< CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */
mbed_official 580:3c14cb9b87c5 406 #define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /*!< CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */
mbed_official 580:3c14cb9b87c5 407
mbed_official 580:3c14cb9b87c5 408 #define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /*!< CMSDK_DUALTIMER2 BGLOAD: Background Load Position */
mbed_official 580:3c14cb9b87c5 409 #define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /*!< CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
mbed_official 580:3c14cb9b87c5 410
mbed_official 580:3c14cb9b87c5 411 typedef struct
mbed_official 580:3c14cb9b87c5 412 {
mbed_official 580:3c14cb9b87c5 413 __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
mbed_official 580:3c14cb9b87c5 414 __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
mbed_official 580:3c14cb9b87c5 415 __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
mbed_official 580:3c14cb9b87c5 416 // <o.7> TimerEn: Timer Enable
mbed_official 580:3c14cb9b87c5 417 // <o.6> TimerMode: Timer Mode
mbed_official 580:3c14cb9b87c5 418 // <0=> Freerunning-mode
mbed_official 580:3c14cb9b87c5 419 // <1=> Periodic mode
mbed_official 580:3c14cb9b87c5 420 // <o.5> IntEnable: Interrupt Enable
mbed_official 580:3c14cb9b87c5 421 // <o.2..3> TimerPre: Timer Prescale
mbed_official 580:3c14cb9b87c5 422 // <0=> / 1
mbed_official 580:3c14cb9b87c5 423 // <1=> / 16
mbed_official 580:3c14cb9b87c5 424 // <2=> / 256
mbed_official 580:3c14cb9b87c5 425 // <3=> Undefined!
mbed_official 580:3c14cb9b87c5 426 // <o.1> TimerSize: Timer Size
mbed_official 580:3c14cb9b87c5 427 // <0=> 16-bit counter
mbed_official 580:3c14cb9b87c5 428 // <1=> 32-bit counter
mbed_official 580:3c14cb9b87c5 429 // <o.0> OneShot: One-shoot mode
mbed_official 580:3c14cb9b87c5 430 // <0=> Wrapping mode
mbed_official 580:3c14cb9b87c5 431 // <1=> One-shot mode
mbed_official 580:3c14cb9b87c5 432 // </h>
mbed_official 580:3c14cb9b87c5 433 __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */
mbed_official 580:3c14cb9b87c5 434 __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */
mbed_official 580:3c14cb9b87c5 435 __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */
mbed_official 580:3c14cb9b87c5 436 __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */
mbed_official 580:3c14cb9b87c5 437 } CMSDK_DUALTIMER_SINGLE_TypeDef;
mbed_official 580:3c14cb9b87c5 438
mbed_official 580:3c14cb9b87c5 439 #define CMSDK_DUALTIMER_LOAD_Pos 0 /*!< CMSDK_DUALTIMER LOAD: LOAD Position */
mbed_official 580:3c14cb9b87c5 440 #define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /*!< CMSDK_DUALTIMER LOAD: LOAD Mask */
mbed_official 580:3c14cb9b87c5 441
mbed_official 580:3c14cb9b87c5 442 #define CMSDK_DUALTIMER_VALUE_Pos 0 /*!< CMSDK_DUALTIMER VALUE: VALUE Position */
mbed_official 580:3c14cb9b87c5 443 #define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /*!< CMSDK_DUALTIMER VALUE: VALUE Mask */
mbed_official 580:3c14cb9b87c5 444
mbed_official 580:3c14cb9b87c5 445 #define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /*!< CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */
mbed_official 580:3c14cb9b87c5 446 #define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /*!< CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */
mbed_official 580:3c14cb9b87c5 447
mbed_official 580:3c14cb9b87c5 448 #define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /*!< CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */
mbed_official 580:3c14cb9b87c5 449 #define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /*!< CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */
mbed_official 580:3c14cb9b87c5 450
mbed_official 580:3c14cb9b87c5 451 #define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /*!< CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */
mbed_official 580:3c14cb9b87c5 452 #define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /*!< CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */
mbed_official 580:3c14cb9b87c5 453
mbed_official 580:3c14cb9b87c5 454 #define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /*!< CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */
mbed_official 580:3c14cb9b87c5 455 #define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /*!< CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */
mbed_official 580:3c14cb9b87c5 456
mbed_official 580:3c14cb9b87c5 457 #define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /*!< CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */
mbed_official 580:3c14cb9b87c5 458 #define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /*!< CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */
mbed_official 580:3c14cb9b87c5 459
mbed_official 580:3c14cb9b87c5 460 #define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /*!< CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */
mbed_official 580:3c14cb9b87c5 461 #define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /*!< CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */
mbed_official 580:3c14cb9b87c5 462
mbed_official 580:3c14cb9b87c5 463 #define CMSDK_DUALTIMER_INTCLR_Pos 0 /*!< CMSDK_DUALTIMER INTCLR: INT Clear Position */
mbed_official 580:3c14cb9b87c5 464 #define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /*!< CMSDK_DUALTIMER INTCLR: INT Clear Mask */
mbed_official 580:3c14cb9b87c5 465
mbed_official 580:3c14cb9b87c5 466 #define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /*!< CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */
mbed_official 580:3c14cb9b87c5 467 #define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /*!< CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */
mbed_official 580:3c14cb9b87c5 468
mbed_official 580:3c14cb9b87c5 469 #define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /*!< CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */
mbed_official 580:3c14cb9b87c5 470 #define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /*!< CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */
mbed_official 580:3c14cb9b87c5 471
mbed_official 580:3c14cb9b87c5 472 #define CMSDK_DUALTIMER_BGLOAD_Pos 0 /*!< CMSDK_DUALTIMER BGLOAD: Background Load Position */
mbed_official 580:3c14cb9b87c5 473 #define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /*!< CMSDK_DUALTIMER BGLOAD: Background Load Mask */
mbed_official 580:3c14cb9b87c5 474
mbed_official 580:3c14cb9b87c5 475 /*@}*/ /* end of group CMSDK_DualTIMER */
mbed_official 580:3c14cb9b87c5 476
mbed_official 580:3c14cb9b87c5 477
mbed_official 580:3c14cb9b87c5 478 /*-------------------- General Purpose Input Output (GPIO) -------------------*/
mbed_official 580:3c14cb9b87c5 479 /** @addtogroup CMSDK_GPIO CMSDK GPIO
mbed_official 580:3c14cb9b87c5 480 @{
mbed_official 580:3c14cb9b87c5 481 */
mbed_official 580:3c14cb9b87c5 482 typedef struct
mbed_official 580:3c14cb9b87c5 483 {
mbed_official 580:3c14cb9b87c5 484 __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
mbed_official 580:3c14cb9b87c5 485 __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
mbed_official 580:3c14cb9b87c5 486 uint32_t RESERVED0[2];
mbed_official 580:3c14cb9b87c5 487 __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */
mbed_official 580:3c14cb9b87c5 488 __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */
mbed_official 580:3c14cb9b87c5 489 __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */
mbed_official 580:3c14cb9b87c5 490 __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */
mbed_official 580:3c14cb9b87c5 491 __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */
mbed_official 580:3c14cb9b87c5 492 __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */
mbed_official 580:3c14cb9b87c5 493 __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */
mbed_official 580:3c14cb9b87c5 494 __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */
mbed_official 580:3c14cb9b87c5 495 __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */
mbed_official 580:3c14cb9b87c5 496 __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */
mbed_official 580:3c14cb9b87c5 497 union {
mbed_official 580:3c14cb9b87c5 498 __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */
mbed_official 580:3c14cb9b87c5 499 __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
mbed_official 580:3c14cb9b87c5 500 };
mbed_official 580:3c14cb9b87c5 501 uint32_t RESERVED1[241];
mbed_official 580:3c14cb9b87c5 502 __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */
mbed_official 580:3c14cb9b87c5 503 __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */
mbed_official 580:3c14cb9b87c5 504 } CMSDK_GPIO_TypeDef;
mbed_official 580:3c14cb9b87c5 505
mbed_official 580:3c14cb9b87c5 506 #define CMSDK_GPIO_DATA_Pos 0 /*!< CMSDK_GPIO DATA: DATA Position */
mbed_official 580:3c14cb9b87c5 507 #define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /*!< CMSDK_GPIO DATA: DATA Mask */
mbed_official 580:3c14cb9b87c5 508
mbed_official 580:3c14cb9b87c5 509 #define CMSDK_GPIO_DATAOUT_Pos 0 /*!< CMSDK_GPIO DATAOUT: DATAOUT Position */
mbed_official 580:3c14cb9b87c5 510 #define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /*!< CMSDK_GPIO DATAOUT: DATAOUT Mask */
mbed_official 580:3c14cb9b87c5 511
mbed_official 580:3c14cb9b87c5 512 #define CMSDK_GPIO_OUTENSET_Pos 0 /*!< CMSDK_GPIO OUTEN: OUTEN Position */
mbed_official 580:3c14cb9b87c5 513 #define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /*!< CMSDK_GPIO OUTEN: OUTEN Mask */
mbed_official 580:3c14cb9b87c5 514
mbed_official 580:3c14cb9b87c5 515 #define CMSDK_GPIO_OUTENCLR_Pos 0 /*!< CMSDK_GPIO OUTEN: OUTEN Position */
mbed_official 580:3c14cb9b87c5 516 #define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /*!< CMSDK_GPIO OUTEN: OUTEN Mask */
mbed_official 580:3c14cb9b87c5 517
mbed_official 580:3c14cb9b87c5 518 #define CMSDK_GPIO_ALTFUNCSET_Pos 0 /*!< CMSDK_GPIO ALTFUNC: ALTFUNC Position */
mbed_official 580:3c14cb9b87c5 519 #define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /*!< CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
mbed_official 580:3c14cb9b87c5 520
mbed_official 580:3c14cb9b87c5 521 #define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /*!< CMSDK_GPIO ALTFUNC: ALTFUNC Position */
mbed_official 580:3c14cb9b87c5 522 #define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /*!< CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
mbed_official 580:3c14cb9b87c5 523
mbed_official 580:3c14cb9b87c5 524 #define CMSDK_GPIO_INTENSET_Pos 0 /*!< CMSDK_GPIO INTEN: INTEN Position */
mbed_official 580:3c14cb9b87c5 525 #define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /*!< CMSDK_GPIO INTEN: INTEN Mask */
mbed_official 580:3c14cb9b87c5 526
mbed_official 580:3c14cb9b87c5 527 #define CMSDK_GPIO_INTENCLR_Pos 0 /*!< CMSDK_GPIO INTEN: INTEN Position */
mbed_official 580:3c14cb9b87c5 528 #define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /*!< CMSDK_GPIO INTEN: INTEN Mask */
mbed_official 580:3c14cb9b87c5 529
mbed_official 580:3c14cb9b87c5 530 #define CMSDK_GPIO_INTTYPESET_Pos 0 /*!< CMSDK_GPIO INTTYPE: INTTYPE Position */
mbed_official 580:3c14cb9b87c5 531 #define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /*!< CMSDK_GPIO INTTYPE: INTTYPE Mask */
mbed_official 580:3c14cb9b87c5 532
mbed_official 580:3c14cb9b87c5 533 #define CMSDK_GPIO_INTTYPECLR_Pos 0 /*!< CMSDK_GPIO INTTYPE: INTTYPE Position */
mbed_official 580:3c14cb9b87c5 534 #define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /*!< CMSDK_GPIO INTTYPE: INTTYPE Mask */
mbed_official 580:3c14cb9b87c5 535
mbed_official 580:3c14cb9b87c5 536 #define CMSDK_GPIO_INTPOLSET_Pos 0 /*!< CMSDK_GPIO INTPOL: INTPOL Position */
mbed_official 580:3c14cb9b87c5 537 #define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /*!< CMSDK_GPIO INTPOL: INTPOL Mask */
mbed_official 580:3c14cb9b87c5 538
mbed_official 580:3c14cb9b87c5 539 #define CMSDK_GPIO_INTPOLCLR_Pos 0 /*!< CMSDK_GPIO INTPOL: INTPOL Position */
mbed_official 580:3c14cb9b87c5 540 #define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /*!< CMSDK_GPIO INTPOL: INTPOL Mask */
mbed_official 580:3c14cb9b87c5 541
mbed_official 580:3c14cb9b87c5 542 #define CMSDK_GPIO_INTSTATUS_Pos 0 /*!< CMSDK_GPIO INTSTATUS: INTSTATUS Position */
mbed_official 580:3c14cb9b87c5 543 #define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /*!< CMSDK_GPIO INTSTATUS: INTSTATUS Mask */
mbed_official 580:3c14cb9b87c5 544
mbed_official 580:3c14cb9b87c5 545 #define CMSDK_GPIO_INTCLEAR_Pos 0 /*!< CMSDK_GPIO INTCLEAR: INTCLEAR Position */
mbed_official 580:3c14cb9b87c5 546 #define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /*!< CMSDK_GPIO INTCLEAR: INTCLEAR Mask */
mbed_official 580:3c14cb9b87c5 547
mbed_official 580:3c14cb9b87c5 548 #define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /*!< CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */
mbed_official 580:3c14cb9b87c5 549 #define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /*!< CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */
mbed_official 580:3c14cb9b87c5 550
mbed_official 580:3c14cb9b87c5 551 #define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /*!< CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */
mbed_official 580:3c14cb9b87c5 552 #define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /*!< CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */
mbed_official 580:3c14cb9b87c5 553
mbed_official 580:3c14cb9b87c5 554 /*@}*/ /* end of group CMSDK_GPIO */
mbed_official 580:3c14cb9b87c5 555
mbed_official 580:3c14cb9b87c5 556
mbed_official 580:3c14cb9b87c5 557 /*------------- System Control (SYSCON) --------------------------------------*/
mbed_official 580:3c14cb9b87c5 558 /** @addtogroup CMSDK_SYSCON CMSDK System Control
mbed_official 580:3c14cb9b87c5 559 @{
mbed_official 580:3c14cb9b87c5 560 */
mbed_official 580:3c14cb9b87c5 561 typedef struct
mbed_official 580:3c14cb9b87c5 562 {
mbed_official 580:3c14cb9b87c5 563 __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
mbed_official 580:3c14cb9b87c5 564 __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
mbed_official 580:3c14cb9b87c5 565 __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
mbed_official 580:3c14cb9b87c5 566 __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */
mbed_official 580:3c14cb9b87c5 567 __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
mbed_official 580:3c14cb9b87c5 568 } CMSDK_SYSCON_TypeDef;
mbed_official 580:3c14cb9b87c5 569
mbed_official 580:3c14cb9b87c5 570 #define CMSDK_SYSCON_REMAP_Pos 0
mbed_official 580:3c14cb9b87c5 571 #define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /*!< CMSDK_SYSCON MEME_CTRL: REMAP Mask */
mbed_official 580:3c14cb9b87c5 572
mbed_official 580:3c14cb9b87c5 573 #define CMSDK_SYSCON_PMUCTRL_EN_Pos 0
mbed_official 580:3c14cb9b87c5 574 #define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /*!< CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */
mbed_official 580:3c14cb9b87c5 575
mbed_official 580:3c14cb9b87c5 576 #define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0
mbed_official 580:3c14cb9b87c5 577 #define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /*!< CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */
mbed_official 580:3c14cb9b87c5 578
mbed_official 580:3c14cb9b87c5 579 #define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24
mbed_official 580:3c14cb9b87c5 580 #define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /*!< CMSDK_SYSCON EMICTRL: SIZE Mask */
mbed_official 580:3c14cb9b87c5 581
mbed_official 580:3c14cb9b87c5 582 #define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16
mbed_official 580:3c14cb9b87c5 583 #define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /*!< CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */
mbed_official 580:3c14cb9b87c5 584
mbed_official 580:3c14cb9b87c5 585 #define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8
mbed_official 580:3c14cb9b87c5 586 #define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /*!< CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */
mbed_official 580:3c14cb9b87c5 587
mbed_official 580:3c14cb9b87c5 588 #define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0
mbed_official 580:3c14cb9b87c5 589 #define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /*!< CMSDK_SYSCON EMICTRL: READCYCLE Mask */
mbed_official 580:3c14cb9b87c5 590
mbed_official 580:3c14cb9b87c5 591 #define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0
mbed_official 580:3c14cb9b87c5 592 #define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /*!< CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */
mbed_official 580:3c14cb9b87c5 593
mbed_official 580:3c14cb9b87c5 594 #define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1
mbed_official 580:3c14cb9b87c5 595 #define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /*!< CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */
mbed_official 580:3c14cb9b87c5 596
mbed_official 580:3c14cb9b87c5 597 #define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2
mbed_official 580:3c14cb9b87c5 598 #define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /*!< CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */
mbed_official 580:3c14cb9b87c5 599
mbed_official 580:3c14cb9b87c5 600 /*@}*/ /* end of group CMSDK_SYSCON */
mbed_official 580:3c14cb9b87c5 601
mbed_official 580:3c14cb9b87c5 602 /*------------- PL230 uDMA (PL230) --------------------------------------*/
mbed_official 580:3c14cb9b87c5 603 /** @addtogroup CMSDK_PL230 CMSDK uDMA controller
mbed_official 580:3c14cb9b87c5 604 @{
mbed_official 580:3c14cb9b87c5 605 */
mbed_official 580:3c14cb9b87c5 606 typedef struct
mbed_official 580:3c14cb9b87c5 607 {
mbed_official 580:3c14cb9b87c5 608 __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
mbed_official 580:3c14cb9b87c5 609 __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
mbed_official 580:3c14cb9b87c5 610 __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
mbed_official 580:3c14cb9b87c5 611 __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */
mbed_official 580:3c14cb9b87c5 612 __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */
mbed_official 580:3c14cb9b87c5 613 __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */
mbed_official 580:3c14cb9b87c5 614 __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */
mbed_official 580:3c14cb9b87c5 615 __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */
mbed_official 580:3c14cb9b87c5 616 __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */
mbed_official 580:3c14cb9b87c5 617 __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */
mbed_official 580:3c14cb9b87c5 618 __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */
mbed_official 580:3c14cb9b87c5 619 __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */
mbed_official 580:3c14cb9b87c5 620 __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */
mbed_official 580:3c14cb9b87c5 621 __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */
mbed_official 580:3c14cb9b87c5 622 __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */
mbed_official 580:3c14cb9b87c5 623 __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */
mbed_official 580:3c14cb9b87c5 624 uint32_t RESERVED0[3];
mbed_official 580:3c14cb9b87c5 625 __IO uint32_t ERR_CLR; /* Offset: 0x04C (R/W) Bus Error Clear Register */
mbed_official 580:3c14cb9b87c5 626
mbed_official 580:3c14cb9b87c5 627 } CMSDK_PL230_TypeDef;
mbed_official 580:3c14cb9b87c5 628
mbed_official 580:3c14cb9b87c5 629 #define PL230_DMA_CHNL_BITS 0
mbed_official 580:3c14cb9b87c5 630
mbed_official 580:3c14cb9b87c5 631 #define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /*!< CMSDK_PL230 DMA STATUS: MSTREN Position */
mbed_official 580:3c14cb9b87c5 632 #define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /*!< CMSDK_PL230 DMA STATUS: MSTREN Mask */
mbed_official 580:3c14cb9b87c5 633
mbed_official 580:3c14cb9b87c5 634 #define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /*!< CMSDK_PL230 DMA STATUS: STATE Position */
mbed_official 580:3c14cb9b87c5 635 #define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /*!< CMSDK_PL230 DMA STATUS: STATE Mask */
mbed_official 580:3c14cb9b87c5 636
mbed_official 580:3c14cb9b87c5 637 #define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /*!< CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */
mbed_official 580:3c14cb9b87c5 638 #define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /*!< CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */
mbed_official 580:3c14cb9b87c5 639
mbed_official 580:3c14cb9b87c5 640 #define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /*!< CMSDK_PL230 DMA STATUS: TEST_STATUS Position */
mbed_official 580:3c14cb9b87c5 641 #define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /*!< CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */
mbed_official 580:3c14cb9b87c5 642
mbed_official 580:3c14cb9b87c5 643 #define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /*!< CMSDK_PL230 DMA CFG: MSTREN Position */
mbed_official 580:3c14cb9b87c5 644 #define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /*!< CMSDK_PL230 DMA CFG: MSTREN Mask */
mbed_official 580:3c14cb9b87c5 645
mbed_official 580:3c14cb9b87c5 646 #define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /*!< CMSDK_PL230 DMA CFG: CPCCACHE Position */
mbed_official 580:3c14cb9b87c5 647 #define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /*!< CMSDK_PL230 DMA CFG: CPCCACHE Mask */
mbed_official 580:3c14cb9b87c5 648
mbed_official 580:3c14cb9b87c5 649 #define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /*!< CMSDK_PL230 DMA CFG: CPCBUF Position */
mbed_official 580:3c14cb9b87c5 650 #define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /*!< CMSDK_PL230 DMA CFG: CPCBUF Mask */
mbed_official 580:3c14cb9b87c5 651
mbed_official 580:3c14cb9b87c5 652 #define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /*!< CMSDK_PL230 DMA CFG: CPCPRIV Position */
mbed_official 580:3c14cb9b87c5 653 #define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /*!< CMSDK_PL230 DMA CFG: CPCPRIV Mask */
mbed_official 580:3c14cb9b87c5 654
mbed_official 580:3c14cb9b87c5 655 #define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /*!< CMSDK_PL230 STATUS: BASE_PTR Position */
mbed_official 580:3c14cb9b87c5 656 #define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /*!< CMSDK_PL230 STATUS: BASE_PTR Mask */
mbed_official 580:3c14cb9b87c5 657
mbed_official 580:3c14cb9b87c5 658 #define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /*!< CMSDK_PL230 STATUS: MSTREN Position */
mbed_official 580:3c14cb9b87c5 659 #define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /*!< CMSDK_PL230 STATUS: MSTREN Mask */
mbed_official 580:3c14cb9b87c5 660
mbed_official 580:3c14cb9b87c5 661 #define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /*!< CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */
mbed_official 580:3c14cb9b87c5 662 #define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /*!< CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */
mbed_official 580:3c14cb9b87c5 663
mbed_official 580:3c14cb9b87c5 664 #define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /*!< CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */
mbed_official 580:3c14cb9b87c5 665 #define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /*!< CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */
mbed_official 580:3c14cb9b87c5 666
mbed_official 580:3c14cb9b87c5 667 #define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /*!< CMSDK_PL230 CHNL_USEBURST: SET Position */
mbed_official 580:3c14cb9b87c5 668 #define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /*!< CMSDK_PL230 CHNL_USEBURST: SET Mask */
mbed_official 580:3c14cb9b87c5 669
mbed_official 580:3c14cb9b87c5 670 #define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /*!< CMSDK_PL230 CHNL_USEBURST: CLR Position */
mbed_official 580:3c14cb9b87c5 671 #define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /*!< CMSDK_PL230 CHNL_USEBURST: CLR Mask */
mbed_official 580:3c14cb9b87c5 672
mbed_official 580:3c14cb9b87c5 673 #define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /*!< CMSDK_PL230 CHNL_REQ_MASK: SET Position */
mbed_official 580:3c14cb9b87c5 674 #define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /*!< CMSDK_PL230 CHNL_REQ_MASK: SET Mask */
mbed_official 580:3c14cb9b87c5 675
mbed_official 580:3c14cb9b87c5 676 #define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /*!< CMSDK_PL230 CHNL_REQ_MASK: CLR Position */
mbed_official 580:3c14cb9b87c5 677 #define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /*!< CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */
mbed_official 580:3c14cb9b87c5 678
mbed_official 580:3c14cb9b87c5 679 #define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /*!< CMSDK_PL230 CHNL_ENABLE: SET Position */
mbed_official 580:3c14cb9b87c5 680 #define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /*!< CMSDK_PL230 CHNL_ENABLE: SET Mask */
mbed_official 580:3c14cb9b87c5 681
mbed_official 580:3c14cb9b87c5 682 #define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /*!< CMSDK_PL230 CHNL_ENABLE: CLR Position */
mbed_official 580:3c14cb9b87c5 683 #define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /*!< CMSDK_PL230 CHNL_ENABLE: CLR Mask */
mbed_official 580:3c14cb9b87c5 684
mbed_official 580:3c14cb9b87c5 685 #define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /*!< CMSDK_PL230 CHNL_PRI_ALT: SET Position */
mbed_official 580:3c14cb9b87c5 686 #define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /*!< CMSDK_PL230 CHNL_PRI_ALT: SET Mask */
mbed_official 580:3c14cb9b87c5 687
mbed_official 580:3c14cb9b87c5 688 #define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /*!< CMSDK_PL230 CHNL_PRI_ALT: CLR Position */
mbed_official 580:3c14cb9b87c5 689 #define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /*!< CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */
mbed_official 580:3c14cb9b87c5 690
mbed_official 580:3c14cb9b87c5 691 #define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /*!< CMSDK_PL230 CHNL_PRIORITY: SET Position */
mbed_official 580:3c14cb9b87c5 692 #define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /*!< CMSDK_PL230 CHNL_PRIORITY: SET Mask */
mbed_official 580:3c14cb9b87c5 693
mbed_official 580:3c14cb9b87c5 694 #define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /*!< CMSDK_PL230 CHNL_PRIORITY: CLR Position */
mbed_official 580:3c14cb9b87c5 695 #define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /*!< CMSDK_PL230 CHNL_PRIORITY: CLR Mask */
mbed_official 580:3c14cb9b87c5 696
mbed_official 580:3c14cb9b87c5 697 #define CMSDK_PL230_ERR_CLR_Pos 0 /*!< CMSDK_PL230 ERR: CLR Position */
mbed_official 580:3c14cb9b87c5 698 #define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /*!< CMSDK_PL230 ERR: CLR Mask */
mbed_official 580:3c14cb9b87c5 699
mbed_official 580:3c14cb9b87c5 700
mbed_official 580:3c14cb9b87c5 701 /*@}*/ /* end of group CMSDK_PL230 */
mbed_official 580:3c14cb9b87c5 702
mbed_official 580:3c14cb9b87c5 703
mbed_official 580:3c14cb9b87c5 704 /*------------- PrimeCell UART (PL110) --------------------------------------*/
mbed_official 580:3c14cb9b87c5 705 /** @addtogroup CMSDK_PL110 CMSDK PrimeCell UART
mbed_official 580:3c14cb9b87c5 706 @{
mbed_official 580:3c14cb9b87c5 707 */
mbed_official 580:3c14cb9b87c5 708
mbed_official 580:3c14cb9b87c5 709 typedef struct
mbed_official 580:3c14cb9b87c5 710 {
mbed_official 580:3c14cb9b87c5 711 __IO uint32_t UARTDR; // <h> Data
mbed_official 580:3c14cb9b87c5 712 // <o.11> OE: Overrun error <r>
mbed_official 580:3c14cb9b87c5 713 // <o.10> BE: Break error <r>
mbed_official 580:3c14cb9b87c5 714 // <o.9> PE: Parity error <r>
mbed_official 580:3c14cb9b87c5 715 // <o.8> FE: Framing error <r>
mbed_official 580:3c14cb9b87c5 716 // <o.0..7> DATA: Received or Transmitting data (0..255)
mbed_official 580:3c14cb9b87c5 717 // </h>
mbed_official 580:3c14cb9b87c5 718 union {
mbed_official 580:3c14cb9b87c5 719 __I uint32_t UARTRSR; // <h> Receive Status <r>
mbed_official 580:3c14cb9b87c5 720 // <o.3> OE: Overrun error <r>
mbed_official 580:3c14cb9b87c5 721 // <o.2> BE: Break error <r>
mbed_official 580:3c14cb9b87c5 722 // <o.1> PE: Parity error <r>
mbed_official 580:3c14cb9b87c5 723 // <o.0> FE: Framing error <r>
mbed_official 580:3c14cb9b87c5 724 // </h>
mbed_official 580:3c14cb9b87c5 725 __O uint32_t UARTECR; // <h> Error Clear <w>
mbed_official 580:3c14cb9b87c5 726 // <o.3> OE: Overrun error <w>
mbed_official 580:3c14cb9b87c5 727 // <o.2> BE: Break error <w>
mbed_official 580:3c14cb9b87c5 728 // <o.1> PE: Parity error <w>
mbed_official 580:3c14cb9b87c5 729 // <o.0> FE: Framing error <w>
mbed_official 580:3c14cb9b87c5 730 // </h>
mbed_official 580:3c14cb9b87c5 731 };
mbed_official 580:3c14cb9b87c5 732 uint32_t RESERVED0[4];
mbed_official 580:3c14cb9b87c5 733 __IO uint32_t UARTFR; // <h> Flags <r>
mbed_official 580:3c14cb9b87c5 734 // <o.8> RI: Ring indicator <r>
mbed_official 580:3c14cb9b87c5 735 // <o.7> TXFE: Transmit FIFO empty <r>
mbed_official 580:3c14cb9b87c5 736 // <o.6> RXFF: Receive FIFO full <r>
mbed_official 580:3c14cb9b87c5 737 // <o.5> TXFF: Transmit FIFO full <r>
mbed_official 580:3c14cb9b87c5 738 // <o.4> RXFE: Receive FIFO empty <r>
mbed_official 580:3c14cb9b87c5 739 // <o.3> BUSY: UART busy <r>
mbed_official 580:3c14cb9b87c5 740 // <o.2> DCD: Data carrier detect <r>
mbed_official 580:3c14cb9b87c5 741 // <o.1> DSR: Data set ready <r>
mbed_official 580:3c14cb9b87c5 742 // <o.0> CTS: Clear to send <r>
mbed_official 580:3c14cb9b87c5 743 // </h>
mbed_official 580:3c14cb9b87c5 744 uint32_t RESERVED1;
mbed_official 580:3c14cb9b87c5 745 __IO uint32_t UARTILPR; // <h> IrDA Low-power Counter
mbed_official 580:3c14cb9b87c5 746 // <o.0..7> ILPDVSR: 8-bit low-power divisor value (0..255)
mbed_official 580:3c14cb9b87c5 747 // </h>
mbed_official 580:3c14cb9b87c5 748 __IO uint32_t UARTIBRD; // <h> Integer Baud Rate
mbed_official 580:3c14cb9b87c5 749 // <o.0..15> BAUD DIVINT: Integer baud rate divisor (0..65535)
mbed_official 580:3c14cb9b87c5 750 // </h>
mbed_official 580:3c14cb9b87c5 751 __IO uint32_t UARTFBRD; // <h> Fractional Baud Rate
mbed_official 580:3c14cb9b87c5 752 // <o.0..5> BAUD DIVFRAC: Fractional baud rate divisor (0..63)
mbed_official 580:3c14cb9b87c5 753 // </h>
mbed_official 580:3c14cb9b87c5 754 __IO uint32_t UARTLCR_H; // <h> Line Control
mbed_official 580:3c14cb9b87c5 755 // <o.8> SPS: Stick parity select
mbed_official 580:3c14cb9b87c5 756 // <o.5..6> WLEN: Word length
mbed_official 580:3c14cb9b87c5 757 // <0=> 5 bits
mbed_official 580:3c14cb9b87c5 758 // <1=> 6 bits
mbed_official 580:3c14cb9b87c5 759 // <2=> 7 bits
mbed_official 580:3c14cb9b87c5 760 // <3=> 8 bits
mbed_official 580:3c14cb9b87c5 761 // <o.4> FEN: Enable FIFOs
mbed_official 580:3c14cb9b87c5 762 // <o.3> STP2: Two stop bits select
mbed_official 580:3c14cb9b87c5 763 // <o.2> EPS: Even parity select
mbed_official 580:3c14cb9b87c5 764 // <o.1> PEN: Parity enable
mbed_official 580:3c14cb9b87c5 765 // <o.0> BRK: Send break
mbed_official 580:3c14cb9b87c5 766 // </h>
mbed_official 580:3c14cb9b87c5 767 __IO uint32_t UARTCR; // <h> Control
mbed_official 580:3c14cb9b87c5 768 // <o.15> CTSEn: CTS hardware flow control enable
mbed_official 580:3c14cb9b87c5 769 // <o.14> RTSEn: RTS hardware flow control enable
mbed_official 580:3c14cb9b87c5 770 // <o.13> Out2: Complement of Out2 modem status output
mbed_official 580:3c14cb9b87c5 771 // <o.12> Out1: Complement of Out1 modem status output
mbed_official 580:3c14cb9b87c5 772 // <o.11> RTS: Request to send
mbed_official 580:3c14cb9b87c5 773 // <o.10> DTR: Data transmit ready
mbed_official 580:3c14cb9b87c5 774 // <o.9> RXE: Receive enable
mbed_official 580:3c14cb9b87c5 775 // <o.8> TXE: Transmit enable
mbed_official 580:3c14cb9b87c5 776 // <o.7> LBE: Loop-back enable
mbed_official 580:3c14cb9b87c5 777 // <o.2> SIRLP: IrDA SIR low power mode
mbed_official 580:3c14cb9b87c5 778 // <o.1> SIREN: SIR enable
mbed_official 580:3c14cb9b87c5 779 // <o.0> UARTEN: UART enable
mbed_official 580:3c14cb9b87c5 780 // </h>
mbed_official 580:3c14cb9b87c5 781 __IO uint32_t UARTIFLS; // <h> Interrupt FIFO Level Select
mbed_official 580:3c14cb9b87c5 782 // <o.3..5> RXIFLSEL: Receive interrupt FIFO level select
mbed_official 580:3c14cb9b87c5 783 // <0=> >= 1/8 full
mbed_official 580:3c14cb9b87c5 784 // <1=> >= 1/4 full
mbed_official 580:3c14cb9b87c5 785 // <2=> >= 1/2 full
mbed_official 580:3c14cb9b87c5 786 // <3=> >= 3/4 full
mbed_official 580:3c14cb9b87c5 787 // <4=> >= 7/8 full
mbed_official 580:3c14cb9b87c5 788 // <5=> reserved
mbed_official 580:3c14cb9b87c5 789 // <6=> reserved
mbed_official 580:3c14cb9b87c5 790 // <7=> reserved
mbed_official 580:3c14cb9b87c5 791 // <o.0..2> TXIFLSEL: Transmit interrupt FIFO level select
mbed_official 580:3c14cb9b87c5 792 // <0=> <= 1/8 full
mbed_official 580:3c14cb9b87c5 793 // <1=> <= 1/4 full
mbed_official 580:3c14cb9b87c5 794 // <2=> <= 1/2 full
mbed_official 580:3c14cb9b87c5 795 // <3=> <= 3/4 full
mbed_official 580:3c14cb9b87c5 796 // <4=> <= 7/8 full
mbed_official 580:3c14cb9b87c5 797 // <5=> reserved
mbed_official 580:3c14cb9b87c5 798 // <6=> reserved
mbed_official 580:3c14cb9b87c5 799 // <7=> reserved
mbed_official 580:3c14cb9b87c5 800 // </h>
mbed_official 580:3c14cb9b87c5 801 __IO uint32_t UARTIMSC; // <h> Interrupt Mask Set / Clear
mbed_official 580:3c14cb9b87c5 802 // <o.10> OEIM: Overrun error interrupt mask
mbed_official 580:3c14cb9b87c5 803 // <o.9> BEIM: Break error interrupt mask
mbed_official 580:3c14cb9b87c5 804 // <o.8> PEIM: Parity error interrupt mask
mbed_official 580:3c14cb9b87c5 805 // <o.7> FEIM: Framing error interrupt mask
mbed_official 580:3c14cb9b87c5 806 // <o.6> RTIM: Receive interrupt mask
mbed_official 580:3c14cb9b87c5 807 // <o.5> TXIM: Transmit interrupt mask
mbed_official 580:3c14cb9b87c5 808 // <o.4> RXIM: Receive interrupt mask
mbed_official 580:3c14cb9b87c5 809 // <o.3> DSRMIM: nUARTDSR modem interrupt mask
mbed_official 580:3c14cb9b87c5 810 // <o.2> DCDMIM: nUARTDCD modem interrupt mask
mbed_official 580:3c14cb9b87c5 811 // <o.1> CTSMIM: nUARTCTS modem interrupt mask
mbed_official 580:3c14cb9b87c5 812 // <o.0> RIMIM: nUARTRI modem interrupt mask
mbed_official 580:3c14cb9b87c5 813 // </h>
mbed_official 580:3c14cb9b87c5 814 __IO uint32_t UARTRIS; // <h> Raw Interrupt Status <r>
mbed_official 580:3c14cb9b87c5 815 // <o.10> OERIS: Overrun error interrupt status <r>
mbed_official 580:3c14cb9b87c5 816 // <o.9> BERIS: Break error interrupt status <r>
mbed_official 580:3c14cb9b87c5 817 // <o.8> PERIS: Parity error interrupt status <r>
mbed_official 580:3c14cb9b87c5 818 // <o.7> FERIS: Framing error interrupt status <r>
mbed_official 580:3c14cb9b87c5 819 // <o.6> RTRIS: Receive timeout interrupt status <r>
mbed_official 580:3c14cb9b87c5 820 // <o.5> TXRIS: Transmit interrupt status <r>
mbed_official 580:3c14cb9b87c5 821 // <o.4> RXRIS: Receive interrupt status <r>
mbed_official 580:3c14cb9b87c5 822 // <o.3> DSRRMIS: nUARTDSR modem interrupt status <r>
mbed_official 580:3c14cb9b87c5 823 // <o.2> DCDRMIS: nUARTDCD modem interrupt status <r>
mbed_official 580:3c14cb9b87c5 824 // <o.1> CTSRMIS: nUARTCTS modem interrupt status <r>
mbed_official 580:3c14cb9b87c5 825 // <o.0> RIRMIS: nUARTRI modem interrupt status <r>
mbed_official 580:3c14cb9b87c5 826 // </h>
mbed_official 580:3c14cb9b87c5 827 __IO uint32_t UARTMIS; // <h> Masked Interrupt Status <r>
mbed_official 580:3c14cb9b87c5 828 // <o.10> OEMIS: Overrun error masked interrupt status <r>
mbed_official 580:3c14cb9b87c5 829 // <o.9> BEMIS: Break error masked interrupt status <r>
mbed_official 580:3c14cb9b87c5 830 // <o.8> PEMIS: Parity error masked interrupt status <r>
mbed_official 580:3c14cb9b87c5 831 // <o.7> FEMIS: Framing error masked interrupt status <r>
mbed_official 580:3c14cb9b87c5 832 // <o.6> RTMIS: Receive timeout masked interrupt status <r>
mbed_official 580:3c14cb9b87c5 833 // <o.5> TXMIS: Transmit masked interrupt status <r>
mbed_official 580:3c14cb9b87c5 834 // <o.4> RXMIS: Receive masked interrupt status <r>
mbed_official 580:3c14cb9b87c5 835 // <o.3> DSRMMIS: nUARTDSR modem masked interrupt status <r>
mbed_official 580:3c14cb9b87c5 836 // <o.2> DCDMMIS: nUARTDCD modem masked interrupt status <r>
mbed_official 580:3c14cb9b87c5 837 // <o.1> CTSMMIS: nUARTCTS modem masked interrupt status <r>
mbed_official 580:3c14cb9b87c5 838 // <o.0> RIMMIS: nUARTRI modem masked interrupt status <r>
mbed_official 580:3c14cb9b87c5 839 // </h>
mbed_official 580:3c14cb9b87c5 840 __O uint32_t UARTICR; // <h> Interrupt Clear <w>
mbed_official 580:3c14cb9b87c5 841 // <o.10> OEIC: Overrun error interrupt clear <w>
mbed_official 580:3c14cb9b87c5 842 // <o.9> BEIC: Break error interrupt clear <w>
mbed_official 580:3c14cb9b87c5 843 // <o.8> PEIC: Parity error interrupt clear <w>
mbed_official 580:3c14cb9b87c5 844 // <o.7> FEIC: Framing error interrupt clear <w>
mbed_official 580:3c14cb9b87c5 845 // <o.6> RTIC: Receive timeout interrupt clear <w>
mbed_official 580:3c14cb9b87c5 846 // <o.5> TXIC: Transmit interrupt clear <w>
mbed_official 580:3c14cb9b87c5 847 // <o.4> RXIC: Receive interrupt clear <w>
mbed_official 580:3c14cb9b87c5 848 // <o.3> DSRMIC: nUARTDSR modem interrupt clear <w>
mbed_official 580:3c14cb9b87c5 849 // <o.2> DCDMIC: nUARTDCD modem interrupt clear <w>
mbed_official 580:3c14cb9b87c5 850 // <o.1> CTSMIC: nUARTCTS modem interrupt clear <w>
mbed_official 580:3c14cb9b87c5 851 // <o.0> RIMIC: nUARTRI modem interrupt clear <w>
mbed_official 580:3c14cb9b87c5 852 // </h>
mbed_official 580:3c14cb9b87c5 853 __IO uint32_t UARTDMACR; // <h> DMA Control
mbed_official 580:3c14cb9b87c5 854 // <o.2> DMAONERR: DMA on error
mbed_official 580:3c14cb9b87c5 855 // <o.1> TXDMAE: Transmit DMA enable
mbed_official 580:3c14cb9b87c5 856 // <o.0> RXDMAE: Receive DMA enable
mbed_official 580:3c14cb9b87c5 857 // </h>
mbed_official 580:3c14cb9b87c5 858 } PL110_UART_TypeDef;
mbed_official 580:3c14cb9b87c5 859
mbed_official 580:3c14cb9b87c5 860 #define CMSDK_PL110_DATAOVRRUN_Pos 11 /*!< CMSDK_PL110 DATAOVRRUN: Data Overrun Position */
mbed_official 580:3c14cb9b87c5 861 #define CMSDK_PL110_DATAOVRRUN_Msk (0x1ul << CMSDK_PL110_DATAOVRRUN_Pos) /*!< CMSDK_PL110 DATAOVRRUN: Data Overrun Mask */
mbed_official 580:3c14cb9b87c5 862
mbed_official 580:3c14cb9b87c5 863 #define CMSDK_PL110_DATABREAKERR_Pos 10 /*!< CMSDK_PL110 DATABREAKERR: Data Break Error Position */
mbed_official 580:3c14cb9b87c5 864 #define CMSDK_PL110_DATABREAKERR_Msk (0x1ul << CMSDK_PL110_DATABREAKERR_Pos) /*!< CMSDK_PL110 DATABREAKERR: Data Break Error Mask */
mbed_official 580:3c14cb9b87c5 865
mbed_official 580:3c14cb9b87c5 866 #define CMSDK_PL110_DATAPARITYERR_Pos 9 /*!< CMSDK_PL110 DATAPARITYERR: Data Parity Error Position */
mbed_official 580:3c14cb9b87c5 867 #define CMSDK_PL110_DATAPARITYERR_Msk (0x1ul << CMSDK_PL110_DATAPARITYERR_Pos) /*!< CMSDK_PL110 DATAPARITYERR: Data Parity Error Mask */
mbed_official 580:3c14cb9b87c5 868
mbed_official 580:3c14cb9b87c5 869 #define CMSDK_PL110_DATAFRAMEERR_Pos 8 /*!< CMSDK_PL110 DATAFRAMEERR: Data Frame Error Position */
mbed_official 580:3c14cb9b87c5 870 #define CMSDK_PL110_DATAFRAMEERR_Msk (0x1ul << CMSDK_PL110_DATAFRAMEERR_Pos) /*!< CMSDK_PL110 DATAFRAMEERR: Data Frame Error Mask */
mbed_official 580:3c14cb9b87c5 871
mbed_official 580:3c14cb9b87c5 872 #define CMSDK_PL110_RECOVRRUN_Pos 3 /*!< CMSDK_PL110 RECOVRRUN: Receive Overrun Position */
mbed_official 580:3c14cb9b87c5 873 #define CMSDK_PL110_RECOVRRUN_Msk (0x1ul << CMSDK_PL110_RECOVRRUN_Pos) /*!< CMSDK_PL110 RECOVRRUN: Receive Overrun Mask */
mbed_official 580:3c14cb9b87c5 874
mbed_official 580:3c14cb9b87c5 875 #define CMSDK_PL110_RECBREAKERR_Pos 2 /*!< CMSDK_PL110 RECBREAKERR: Receive Break Error Position */
mbed_official 580:3c14cb9b87c5 876 #define CMSDK_PL110_RECBREAKERR_Msk (0x1ul << CMSDK_PL110_RECBREAKERR_Pos) /*!< CMSDK_PL110 RECBREAKERR: Receive Break Error Mask */
mbed_official 580:3c14cb9b87c5 877
mbed_official 580:3c14cb9b87c5 878 #define CMSDK_PL110_RECPARITYERR_Pos 1 /*!< CMSDK_PL110 RECPARITYERR: Receive Parity Error Position */
mbed_official 580:3c14cb9b87c5 879 #define CMSDK_PL110_RECPARITYERR_Msk (0x1ul << CMSDK_PL110_RECPARITYERR_Pos) /*!< CMSDK_PL110 RECPARITYERR: Receive Parity Error Mask */
mbed_official 580:3c14cb9b87c5 880
mbed_official 580:3c14cb9b87c5 881 #define CMSDK_PL110_RECFRAMEERR_Pos 0 /*!< CMSDK_PL110 RECFRAMEERR: Receive Frame Error Position */
mbed_official 580:3c14cb9b87c5 882 #define CMSDK_PL110_RECFRAMEERR_Msk (0x1ul << CMSDK_PL110_RECFRAMEERR_Pos) /*!< CMSDK_PL110 RECFRAMEERR: Receive Frame Error Mask */
mbed_official 580:3c14cb9b87c5 883
mbed_official 580:3c14cb9b87c5 884 #define CMSDK_PL110_ERRCLROVRRUN_Pos 3 /*!< CMSDK_PL110 ERRCLROVRRUN: Clear Overrun Position */
mbed_official 580:3c14cb9b87c5 885 #define CMSDK_PL110_ERRCLROVRRUN_Msk (0x1ul << CMSDK_PL110_ERRCLROVRRUN_Pos) /*!< CMSDK_PL110 ERRCLROVRRUN: Clear Overrun Mask */
mbed_official 580:3c14cb9b87c5 886
mbed_official 580:3c14cb9b87c5 887 #define CMSDK_PL110_ERRCLRBREAKERR_Pos 2 /*!< CMSDK_PL110 ERRCLRBREAKERR: Clear Break Error Position */
mbed_official 580:3c14cb9b87c5 888 #define CMSDK_PL110_ERRCLRBREAKERR_Msk (0x1ul << CMSDK_PL110_ERRCLRBREAKERR_Pos) /*!< CMSDK_PL110 ERRCLRBREAKERR: Clear Break Error Mask */
mbed_official 580:3c14cb9b87c5 889
mbed_official 580:3c14cb9b87c5 890 #define CMSDK_PL110_ERRCLRPARITYERR_Pos 1 /*!< CMSDK_PL110 ERRCLRPARITYERR: Clear Parity Error Position */
mbed_official 580:3c14cb9b87c5 891 #define CMSDK_PL110_ERRCLRPARITYERR_Msk (0x1ul << CMSDK_PL110_ERRCLRPARITYERR_Pos) /*!< CMSDK_PL110 ERRCLRPARITYERR: Clear Parity Error Mask */
mbed_official 580:3c14cb9b87c5 892
mbed_official 580:3c14cb9b87c5 893 #define CMSDK_PL110_ERRCLRFRAMEERR_Pos 0 /*!< CMSDK_PL110 ERRCLRFRAMEERR: Clear Frame Error Position */
mbed_official 580:3c14cb9b87c5 894 #define CMSDK_PL110_ERRCLRFRAMEERR_Msk (0x1ul << CMSDK_PL110_ERRCLRFRAMEERR_Pos) /*!< CMSDK_PL110 ERRCLRFRAMEERR: Clear Frame Error Mask */
mbed_official 580:3c14cb9b87c5 895
mbed_official 580:3c14cb9b87c5 896 #define CMSDK_PL110_FLAG_RINGIND_Pos 8 /*!< CMSDK_PL110 FLAG_RINGIND: Ring Indicator Position */
mbed_official 580:3c14cb9b87c5 897 #define CMSDK_PL110_FLAG_RINGIND_Msk (0x1ul << CMSDK_PL110_FLAG_RINGIND_Pos) /*!< CMSDK_PL110 FLAG_RINGIND: Ring Indicator Mask */
mbed_official 580:3c14cb9b87c5 898
mbed_official 580:3c14cb9b87c5 899 #define CMSDK_PL110_FLAG_TXFEMPTY_Pos 7 /*!< CMSDK_PL110 FLAG_TXFEMPTY: Transmit FIFO Empty Position */
mbed_official 580:3c14cb9b87c5 900 #define CMSDK_PL110_FLAG_TXFEMPTY_Msk (0x1ul << CMSDK_PL110_FLAG_TXFEMPTY_Pos) /*!< CMSDK_PL110 FLAG_TXFEMPTY: Transmit FIFO Empty Mask */
mbed_official 580:3c14cb9b87c5 901
mbed_official 580:3c14cb9b87c5 902 #define CMSDK_PL110_FLAG_RXFFULL_Pos 6 /*!< CMSDK_PL110 FLAG_RXFFULL: Receive FIFO Full Position */
mbed_official 580:3c14cb9b87c5 903 #define CMSDK_PL110_FLAG_RXFFULL_Msk (0x1ul << CMSDK_PL110_FLAG_RXFFULL_Pos) /*!< CMSDK_PL110 FLAG_RXFFULL: Receive FIFO Full Mask */
mbed_official 580:3c14cb9b87c5 904
mbed_official 580:3c14cb9b87c5 905 #define CMSDK_PL110_FLAG_TXFFULL_Pos 5 /*!< CMSDK_PL110 FLAG_TXFFULL: Transmit FIFO Full Position */
mbed_official 580:3c14cb9b87c5 906 #define CMSDK_PL110_FLAG_TXFFULL_Msk (0x1ul << CMSDK_PL110_FLAG_TXFFULL_Pos) /*!< CMSDK_PL110 FLAG_TXFFULL: Transmit FIFO Full Mask */
mbed_official 580:3c14cb9b87c5 907
mbed_official 580:3c14cb9b87c5 908 #define CMSDK_PL110_FLAG_RXFEMPTY_Pos 4 /*!< CMSDK_PL110 FLAG_RXFEMPTY: Receive FIFO Empty Position */
mbed_official 580:3c14cb9b87c5 909 #define CMSDK_PL110_FLAG_RXFEMPTY_Msk (0x1ul << CMSDK_PL110_FLAG_RXFEMPTY_Pos) /*!< CMSDK_PL110 FLAG_RXFEMPTY: Receive FIFO Empty Mask */
mbed_official 580:3c14cb9b87c5 910
mbed_official 580:3c14cb9b87c5 911 #define CMSDK_PL110_FLAG_UARTBUSY_Pos 3 /*!< CMSDK_PL110 FLAG_UARTBUSY: UART Busy Position */
mbed_official 580:3c14cb9b87c5 912 #define CMSDK_PL110_FLAG_UARTBUSY_Msk (0x1ul << CMSDK_PL110_FLAG_UARTBUSY_Pos) /*!< CMSDK_PL110 FLAG_UARTBUSY: UART Busy Mask */
mbed_official 580:3c14cb9b87c5 913
mbed_official 580:3c14cb9b87c5 914 #define CMSDK_PL110_FLAG_CARRIERDETECT_Pos 2 /*!< CMSDK_PL110 FLAG_CARRIERDETECT: Carrier Detect Position */
mbed_official 580:3c14cb9b87c5 915 #define CMSDK_PL110_FLAG_CARRIERDETECT_Msk (0x1ul << CMSDK_PL110_FLAG_CARRIERDETECT_Pos) /*!< CMSDK_PL110 FLAG_CARRIERDETECT: Carrier Detect Mask */
mbed_official 580:3c14cb9b87c5 916
mbed_official 580:3c14cb9b87c5 917 #define CMSDK_PL110_FLAG_DATASETREADY_Pos 1 /*!< CMSDK_PL110 FLAG_DATASETREADY: Data Set Ready Position */
mbed_official 580:3c14cb9b87c5 918 #define CMSDK_PL110_FLAG_DATASETREADY_Msk (0x1ul << CMSDK_PL110_FLAG_DATASETREADY_Pos) /*!< CMSDK_PL110 FLAG_DATASETREADY: Data Set Ready Mask */
mbed_official 580:3c14cb9b87c5 919
mbed_official 580:3c14cb9b87c5 920 #define CMSDK_PL110_FLAG_CLR2SEND_Pos 0 /*!< CMSDK_PL110 FLAG_CLR2SEND: Clear To Send Position */
mbed_official 580:3c14cb9b87c5 921 #define CMSDK_PL110_FLAG_CLR2SEND_Msk (0x1ul << CMSDK_PL110_FLAG_CLR2SEND_Pos) /*!< CMSDK_PL110 FLAG_CLR2SEND: Clear To Send Mask */
mbed_official 580:3c14cb9b87c5 922
mbed_official 580:3c14cb9b87c5 923 #define CMSDK_PL110_IRDALOWPOWERCOUNT_Pos 0 /*!< CMSDK_PL110 IRDALOWPOWERCOUNT: IrDA 8-bit low-power divisor value Position */
mbed_official 580:3c14cb9b87c5 924 #define CMSDK_PL110_IRDALOWPOWERCOUNT_Msk (0xFFul << CMSDK_PL110_IRDALOWPOWERCOUNT_Pos) /*!< CMSDK_PL110 IRDALOWPOWERCOUNT: IrDA 8-bit low-power divisor value Mask */
mbed_official 580:3c14cb9b87c5 925
mbed_official 580:3c14cb9b87c5 926 #define CMSDK_PL110_INTDIVIDER_Pos 0 /*!< CMSDK_PL110 INTDIVIDER: Integer Divider Position */
mbed_official 580:3c14cb9b87c5 927 #define CMSDK_PL110_INTDIVIDER_Msk (0xFFFFul << CMSDK_PL110_INTDIVIDER_Pos) /*!< CMSDK_PL110 INTDIVIDER: Integer Divider Mask */
mbed_official 580:3c14cb9b87c5 928
mbed_official 580:3c14cb9b87c5 929 #define CMSDK_PL110_FRACTDIVIDER_Pos 0 /*!< CMSDK_PL110 FRACTDIVIDER: Fractional Divider Position */
mbed_official 580:3c14cb9b87c5 930 #define CMSDK_PL110_FRACTDIVIDER_Msk (0x3Ful << CMSDK_PL110_FRACTDIVIDER_Pos) /*!< CMSDK_PL110 FRACTDIVIDER: Fractional Divider Mask */
mbed_official 580:3c14cb9b87c5 931
mbed_official 580:3c14cb9b87c5 932 #define CMSDK_PL110_STICKPARITYSEL_Pos 8 /*!< CMSDK_PL110 STICKPARITYSEL: Stick parity select Position */
mbed_official 580:3c14cb9b87c5 933 #define CMSDK_PL110_STICKPARITYSEL_Msk (0x1ul << CMSDK_PL110_STICKPARITYSEL_Pos) /*!< CMSDK_PL110 STICKPARITYSEL: Stick parity select Mask */
mbed_official 580:3c14cb9b87c5 934
mbed_official 580:3c14cb9b87c5 935 #define CMSDK_PL110_WORDLEN_Pos 5 /*!< CMSDK_PL110 WORDLEN: Word Length Select Position */
mbed_official 580:3c14cb9b87c5 936 #define CMSDK_PL110_WORDLEN_Msk (0x3ul << CMSDK_PL110_WORDLEN_Pos) /*!< CMSDK_PL110 WORDLEN: Word Length Select Mask */
mbed_official 580:3c14cb9b87c5 937
mbed_official 580:3c14cb9b87c5 938 #define CMSDK_PL110_ENFIFOS_Pos 4 /*!< CMSDK_PL110 ENFIFOS: Enable FIFOs Position */
mbed_official 580:3c14cb9b87c5 939 #define CMSDK_PL110_ENFIFOS_Msk (0x1ul << CMSDK_PL110_ENFIFOS_Pos) /*!< CMSDK_PL110 ENFIFOS: Enable FIFOs Mask */
mbed_official 580:3c14cb9b87c5 940
mbed_official 580:3c14cb9b87c5 941 #define CMSDK_PL110_2STOPBITS_Pos 3 /*!< CMSDK_PL110 2STOPBITS: Two Stop Bits Select Position */
mbed_official 580:3c14cb9b87c5 942 #define CMSDK_PL110_2STOPBITS_Msk (0x1ul << CMSDK_PL110_2STOPBITS_Pos) /*!< CMSDK_PL110 2STOPBITS: Two Stop Bits Select Mask */
mbed_official 580:3c14cb9b87c5 943
mbed_official 580:3c14cb9b87c5 944 #define CMSDK_PL110_EVENPARITY_Pos 2 /*!< CMSDK_PL110 EVENPARITY: Even Parity Select Position */
mbed_official 580:3c14cb9b87c5 945 #define CMSDK_PL110_EVENPARITY_Msk (0x1ul << CMSDK_PL110_EVENPARITY_Pos) /*!< CMSDK_PL110 EVENPARITY: Even Parity Select Mask */
mbed_official 580:3c14cb9b87c5 946
mbed_official 580:3c14cb9b87c5 947 #define CMSDK_PL110_PARITYEN_Pos 1 /*!< CMSDK_PL110 PARITYEN: Parity Enable Position */
mbed_official 580:3c14cb9b87c5 948 #define CMSDK_PL110_PARITYEN_Msk (0x1ul << CMSDK_PL110_PARITYEN_Pos) /*!< CMSDK_PL110 PARITYEN: Parity Enable Mask */
mbed_official 580:3c14cb9b87c5 949
mbed_official 580:3c14cb9b87c5 950 #define CMSDK_PL110_SENDBREAK_Pos 0 /*!< CMSDK_PL110 SENDBREAK: Send Break Position */
mbed_official 580:3c14cb9b87c5 951 #define CMSDK_PL110_SENDBREAK_Msk (0x1ul << CMSDK_PL110_SENDBREAK_Pos) /*!< CMSDK_PL110 SENDBREAK: Send Break Mask */
mbed_official 580:3c14cb9b87c5 952
mbed_official 580:3c14cb9b87c5 953 #define CMSDK_PL110_CTS_FLOWCTRL_Pos 15 /*!< CMSDK_PL110 CTS_FLOWCTRL: Enable CTS Flow Control Position */
mbed_official 580:3c14cb9b87c5 954 #define CMSDK_PL110_CTS_FLOWCTRL_Msk (0x1ul << CMSDK_PL110_CTS_FLOWCTRL_Pos) /*!< CMSDK_PL110 CTS_FLOWCTRL: Enable CTS Flow Control Mask */
mbed_official 580:3c14cb9b87c5 955
mbed_official 580:3c14cb9b87c5 956 #define CMSDK_PL110_RTS_FLOWCTRL_Pos 14 /*!< CMSDK_PL110 RTS_FLOWCTRL: Enable RTS Flow Control Position */
mbed_official 580:3c14cb9b87c5 957 #define CMSDK_PL110_RTS_FLOWCTRL_Msk (0x1ul << CMSDK_PL110_RTS_FLOWCTRL_Pos) /*!< CMSDK_PL110 RTS_FLOWCTRL: Enable RTS Flow Control Mask */
mbed_official 580:3c14cb9b87c5 958
mbed_official 580:3c14cb9b87c5 959 #define CMSDK_PL110_OUT2_Pos 13 /*!< CMSDK_PL110 OUT2: Complement of Out2 modem status output Position */
mbed_official 580:3c14cb9b87c5 960 #define CMSDK_PL110_OUT2_Msk (0x1ul << CMSDK_PL110_OUT2_Pos) /*!< CMSDK_PL110 OUT2: Complement of Out2 modem status output Mask */
mbed_official 580:3c14cb9b87c5 961
mbed_official 580:3c14cb9b87c5 962 #define CMSDK_PL110_OUT1_Pos 12 /*!< CMSDK_PL110 OUT1: Complement of Out1 modem status output Position */
mbed_official 580:3c14cb9b87c5 963 #define CMSDK_PL110_OUT1_Msk (0x1ul << CMSDK_PL110_OUT1_Pos) /*!< CMSDK_PL110 OUT1: Complement of Out1 modem status output Mask */
mbed_official 580:3c14cb9b87c5 964
mbed_official 580:3c14cb9b87c5 965 #define CMSDK_PL110_REQ2SEND_Pos 11 /*!< CMSDK_PL110 REQ2SEND: Request To Send Position */
mbed_official 580:3c14cb9b87c5 966 #define CMSDK_PL110_REQ2SEND_Msk (0x1ul << CMSDK_PL110_REQ2SEND_Pos) /*!< CMSDK_PL110 REQ2SEND: Request To Send Mask */
mbed_official 580:3c14cb9b87c5 967
mbed_official 580:3c14cb9b87c5 968 #define CMSDK_PL110_DATATRANSREADY_Pos 10 /*!< CMSDK_PL110 DATATRANSREADY: Transmit Ready Position */
mbed_official 580:3c14cb9b87c5 969 #define CMSDK_PL110_DATATRANSREADY_Msk (0x1ul << CMSDK_PL110_DATATRANSREADY_Pos) /*!< CMSDK_PL110 DATATRANSREADY: Transmit Ready Mask */
mbed_official 580:3c14cb9b87c5 970
mbed_official 580:3c14cb9b87c5 971 #define CMSDK_PL110_RXEN_Pos 9 /*!< CMSDK_PL110 RXEN: Receive Enable Position */
mbed_official 580:3c14cb9b87c5 972 #define CMSDK_PL110_RXEN_Msk (0x1ul << CMSDK_PL110_RXEN_Pos) /*!< CMSDK_PL110 RXEN: Receive Enable Mask */
mbed_official 580:3c14cb9b87c5 973
mbed_official 580:3c14cb9b87c5 974 #define CMSDK_PL110_TXEN_Pos 8 /*!< CMSDK_PL110 TXEN: Transmit Enable Position */
mbed_official 580:3c14cb9b87c5 975 #define CMSDK_PL110_TXEN_Msk (0x1ul << CMSDK_PL110_TXEN_Pos) /*!< CMSDK_PL110 TXEN: Transmit Enable Mask */
mbed_official 580:3c14cb9b87c5 976
mbed_official 580:3c14cb9b87c5 977 #define CMSDK_PL110_LOOPBACKEN_Pos 7 /*!< CMSDK_PL110 LOOPBACKEN: Loopback Enable Position */
mbed_official 580:3c14cb9b87c5 978 #define CMSDK_PL110_LOOPBACKEN_Msk (0x1ul << CMSDK_PL110_LOOPBACKEN_Pos) /*!< CMSDK_PL110 LOOPBACKEN: Loopback Enable Mask */
mbed_official 580:3c14cb9b87c5 979
mbed_official 580:3c14cb9b87c5 980 #define CMSDK_PL110_IRDASIRLPM_Pos 2 /*!< CMSDK_PL110 IRDASIRLPM: IRDA SIR Low Power Position */
mbed_official 580:3c14cb9b87c5 981 #define CMSDK_PL110_IRDASIRLPM_Msk (0x1ul << CMSDK_PL110_IRDASIRLPM_Pos) /*!< CMSDK_PL110 IRDASIRLPM: IRDA SIR Low Power Mask */
mbed_official 580:3c14cb9b87c5 982
mbed_official 580:3c14cb9b87c5 983 #define CMSDK_PL110_SIREN_Pos 1 /*!< CMSDK_PL110 SIREN: SIR Enable Position */
mbed_official 580:3c14cb9b87c5 984 #define CMSDK_PL110_SIREN_Msk (0x1ul << CMSDK_PL110_SIREN_Pos) /*!< CMSDK_PL110 SIREN: SIR Enable Mask */
mbed_official 580:3c14cb9b87c5 985
mbed_official 580:3c14cb9b87c5 986 #define CMSDK_PL110_UARTEN_Pos 0 /*!< CMSDK_PL110 UARTEN: UART Enable Position */
mbed_official 580:3c14cb9b87c5 987 #define CMSDK_PL110_UARTEN_Msk (0x1ul << CMSDK_PL110_UARTEN_Pos) /*!< CMSDK_PL110 UARTEN: UART Enable Mask */
mbed_official 580:3c14cb9b87c5 988
mbed_official 580:3c14cb9b87c5 989 #define CMSDK_PL110_RECINTFIFOLEVEL_Pos 3 /*!< CMSDK_PL110 RECINTFIFOLEVEL: Set Receive Int FIFO Level Position */
mbed_official 580:3c14cb9b87c5 990 #define CMSDK_PL110_RECINTFIFOLEVEL_Msk (0x7ul << CMSDK_PL110_RECINTFIFOLEVEL_Pos) /*!< CMSDK_PL110 RECINTFIFOLEVEL: Set Receive Int FIFO Level Mask */
mbed_official 580:3c14cb9b87c5 991
mbed_official 580:3c14cb9b87c5 992 #define CMSDK_PL110_TRANSINTFIFOLEVEL_Pos 0 /*!< CMSDK_PL110 TRANSINTFIFOLEVEL: Set Transmit Int FIFO Level Position */
mbed_official 580:3c14cb9b87c5 993 #define CMSDK_PL110_TRANSINTFIFOLEVEL_Msk (0x7ul << CMSDK_PL110_TRANSINTFIFOLEVEL_Pos) /*!< CMSDK_PL110 TRANSINTFIFOLEVEL: Set Transmit Int FIFO Level Mask */
mbed_official 580:3c14cb9b87c5 994
mbed_official 580:3c14cb9b87c5 995 #define CMSDK_PL110_SETMASK_OVRRUNERRINT_Pos 10 /*!< CMSDK_PL110 SETMASK_OVRRUNERRINT: Set Overrun Error Int Mask Position */
mbed_official 580:3c14cb9b87c5 996 #define CMSDK_PL110_SETMASK_OVRRUNERRINT_Msk (0x1ul << CMSDK_PL110_SETMASK_OVRRUNERRINT_Pos) /*!< CMSDK_PL110 SETMASK_OVRRUNERRINT: Set Overrun Error Int Mask Mask */
mbed_official 580:3c14cb9b87c5 997
mbed_official 580:3c14cb9b87c5 998 #define CMSDK_PL110_SETMASK_BREAKERRINT_Pos 9 /*!< CMSDK_PL110 SETMASK_BREAKERRINT: Set Break Error Int Mask Position */
mbed_official 580:3c14cb9b87c5 999 #define CMSDK_PL110_SETMASK_BREAKERRINT_Msk (0x1ul << CMSDK_PL110_SETMASK_BREAKERRINT_Pos) /*!< CMSDK_PL110 SETMASK_BREAKERRINT: Set Break Error Int Mask Mask */
mbed_official 580:3c14cb9b87c5 1000
mbed_official 580:3c14cb9b87c5 1001 #define CMSDK_PL110_SETMASK_PARITYERRINT_Pos 8 /*!< CMSDK_PL110 SETMASK_PARITYERRINT: Set Parity Error Int Mask Position */
mbed_official 580:3c14cb9b87c5 1002 #define CMSDK_PL110_SETMASK_PARITYERRINT_Msk (0x1ul << CMSDK_PL110_SETMASK_PARITYERRINT_Pos) /*!< CMSDK_PL110 SETMASK_PARITYERRINT: Set Parity Error Int Mask Mask */
mbed_official 580:3c14cb9b87c5 1003
mbed_official 580:3c14cb9b87c5 1004 #define CMSDK_PL110_SETMASK_FRAMEERRINT_Pos 7 /*!< CMSDK_PL110 SETMASK_FRAMEERRINT: Set Frame Error Int Mask Position */
mbed_official 580:3c14cb9b87c5 1005 #define CMSDK_PL110_SETMASK_FRAMEERRINT_Msk (0x1ul << CMSDK_PL110_SETMASK_FRAMEERRINT_Pos) /*!< CMSDK_PL110 SETMASK_FRAMEERRINT: Set Frame Error Int Mask Mask */
mbed_official 580:3c14cb9b87c5 1006
mbed_official 580:3c14cb9b87c5 1007 #define CMSDK_PL110_SETMASK_RECTRANSINT_Pos 6 /*!< CMSDK_PL110 SETMASK_RECTRANSINT: Set Transmit Receive Comb Int Mask Position */
mbed_official 580:3c14cb9b87c5 1008 #define CMSDK_PL110_SETMASK_RECTRANSINT_Msk (0x1ul << CMSDK_PL110_SETMASK_RECTRANSINT_Pos) /*!< CMSDK_PL110 SETMASK_RECTRANSINT: Set Transmit Receive Comb Int Mask Mask */
mbed_official 580:3c14cb9b87c5 1009
mbed_official 580:3c14cb9b87c5 1010 #define CMSDK_PL110_SETMASK_TRANSINT_Pos 5 /*!< CMSDK_PL110 SETMASK_TRANSINT: Set Transmit Int Mask Position */
mbed_official 580:3c14cb9b87c5 1011 #define CMSDK_PL110_SETMASK_TRANSINT_Msk (0x1ul << CMSDK_PL110_SETMASK_TRANSINT_Pos) /*!< CMSDK_PL110 SETMASK_TRANSINT: Set Transmit Int Mask Mask */
mbed_official 580:3c14cb9b87c5 1012
mbed_official 580:3c14cb9b87c5 1013 #define CMSDK_PL110_SETMASK_RECINT_Pos 4 /*!< CMSDK_PL110 SETMASK_RECINT: Set Receive Int Mask Position */
mbed_official 580:3c14cb9b87c5 1014 #define CMSDK_PL110_SETMASK_RECINT_Msk (0x1ul << CMSDK_PL110_SETMASK_RECINT_Pos) /*!< CMSDK_PL110 SETMASK_RECINT: Set Receive Int Mask Mask */
mbed_official 580:3c14cb9b87c5 1015
mbed_official 580:3c14cb9b87c5 1016 #define CMSDK_PL110_SETMASK_UART_DSRMODINT_Pos 3 /*!< CMSDK_PL110 SETMASK_UART_DSRMODINT: Set Data Set Ready Modem Int Mask Position */
mbed_official 580:3c14cb9b87c5 1017 #define CMSDK_PL110_SETMASK_UART_DSRMODINT_Msk (0x1ul << CMSDK_PL110_SETMASK_UARTD_SRMODINT_Pos) /*!< CMSDK_PL110 SETMASK_UART_DSRMODINT: Set Data Set Ready Modem Int Mask Mask */
mbed_official 580:3c14cb9b87c5 1018
mbed_official 580:3c14cb9b87c5 1019 #define CMSDK_PL110_SETMASK_UART_DCDMODINT_Pos 2 /*!< CMSDK_PL110 SETMASK_UART_DCDMODINT: Set Data Carrier Detect Modem Int Mask Position */
mbed_official 580:3c14cb9b87c5 1020 #define CMSDK_PL110_SETMASK_UART_DCDMODINT_Msk (0x1ul << CMSDK_PL110_SETMASK_UART_DCDMODINT_Pos) /*!< CMSDK_PL110 SETMASK_UART_DCDMODINT: Set Data Carrier Detect Modem Int Mask Mask */
mbed_official 580:3c14cb9b87c5 1021
mbed_official 580:3c14cb9b87c5 1022 #define CMSDK_PL110_SETMASK_UART_CTSMODINT_Pos 1 /*!< CMSDK_PL110 SETMASK_UART_CTSMODINT: Set Clear To Send Modem Int Mask Position */
mbed_official 580:3c14cb9b87c5 1023 #define CMSDK_PL110_SETMASK_UART_CTSMODINT_Msk (0x1ul << CMSDK_PL110_SETMASK_UART_CTSMODINT_Pos) /*!< CMSDK_PL110 SETMASK_UART_CTSMODINT: Set Clear To Send Modem Int Mask Mask */
mbed_official 580:3c14cb9b87c5 1024
mbed_official 580:3c14cb9b87c5 1025 #define CMSDK_PL110_SETMASK_UART_RIMODINT_Pos 0 /*!< CMSDK_PL110 SETMASK_UART_RIMODINT: Set nUARTRI Modem Int Mask Position */
mbed_official 580:3c14cb9b87c5 1026 #define CMSDK_PL110_SETMASK_UART_RIMODINT_Msk (0x1ul << CMSDK_PL110_SETMASK_UART_RIMODINT_Pos) /*!< CMSDK_PL110 SETMASK_UART_RIMODINT: Set nUARTRI Modem Int Mask Mask */
mbed_official 580:3c14cb9b87c5 1027
mbed_official 580:3c14cb9b87c5 1028 #define CMSDK_PL110_RAWINTSTAT_OVRRUNERRINT_Pos 10 /*!< CMSDK_PL110 RAWINTSTAT_OVRRUNERRINT: Raw Overrun Error Int Status Mask Position */
mbed_official 580:3c14cb9b87c5 1029 #define CMSDK_PL110_RAWINTSTAT_OVRRUNERRINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_OVRRUNERRINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_OVRRUNERRINT: Raw Overrun Error Int Status Mask */
mbed_official 580:3c14cb9b87c5 1030
mbed_official 580:3c14cb9b87c5 1031 #define CMSDK_PL110_RAWINTSTAT_BREAKERRINT_Pos 9 /*!< CMSDK_PL110 RAWINTSTAT_BREAKERRINT: Raw Break Error Int Status Mask Position */
mbed_official 580:3c14cb9b87c5 1032 #define CMSDK_PL110_RAWINTSTAT_BREAKERRINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_BREAKERRINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_BREAKERRINT: Raw Break Error Int Status Mask */
mbed_official 580:3c14cb9b87c5 1033
mbed_official 580:3c14cb9b87c5 1034 #define CMSDK_PL110_RAWINTSTAT_PARITYERRINT_Pos 8 /*!< CMSDK_PL110 RAWINTSTAT_PARITYERRINT: Raw Parity Error Int Status Mask Position */
mbed_official 580:3c14cb9b87c5 1035 #define CMSDK_PL110_RAWINTSTAT_PARITYERRINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_PARITYERRINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_PARITYERRINT: Raw Parity Error Int Status Mask */
mbed_official 580:3c14cb9b87c5 1036
mbed_official 580:3c14cb9b87c5 1037 #define CMSDK_PL110_RAWINTSTAT_FRAMEERRINT_Pos 7 /*!< CMSDK_PL110 RAWINTSTAT_FRAMEERRINT: Raw Frame Error Int Status Mask Position */
mbed_official 580:3c14cb9b87c5 1038 #define CMSDK_PL110_RAWINTSTAT_FRAMEERRINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_FRAMEERRINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_FRAMEERRINT: Raw Frame Error Int Status Mask */
mbed_official 580:3c14cb9b87c5 1039
mbed_official 580:3c14cb9b87c5 1040 #define CMSDK_PL110_RAWINTSTAT_RECTRANSINT_Pos 6 /*!< CMSDK_PL110 RAWINTSTAT_RECTRANSINT: Raw Transmit Receive Comb Int Status Position */
mbed_official 580:3c14cb9b87c5 1041 #define CMSDK_PL110_RAWINTSTAT_RECTRANSINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_RECTRANSINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_RECTRANSINT: Raw Transmit Receive Comb Int Status Mask */
mbed_official 580:3c14cb9b87c5 1042
mbed_official 580:3c14cb9b87c5 1043 #define CMSDK_PL110_RAWINTSTAT_TRANSINT_Pos 5 /*!< CMSDK_PL110 RAWINTSTAT_TRANSINT: Raw Transmit Int Status Position */
mbed_official 580:3c14cb9b87c5 1044 #define CMSDK_PL110_RAWINTSTAT_TRANSINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_TRANSINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_TRANSINT: Raw Transmit Int Status Mask */
mbed_official 580:3c14cb9b87c5 1045
mbed_official 580:3c14cb9b87c5 1046 #define CMSDK_PL110_RAWINTSTAT_RECINT_Pos 4 /*!< CMSDK_PL110 RAWINTSTAT_RECINT: Raw Receive Int Status Position */
mbed_official 580:3c14cb9b87c5 1047 #define CMSDK_PL110_RAWINTSTAT_RECINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_RECINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_RECINT: Raw Receive Int Status Mask */
mbed_official 580:3c14cb9b87c5 1048
mbed_official 580:3c14cb9b87c5 1049 #define CMSDK_PL110_RAWINTSTAT_UART_DSRMODINT_Pos 3 /*!< CMSDK_PL110 RAWINTSTAT_UART_DSRMODINT: Raw Data Set Ready Int Status Position */
mbed_official 580:3c14cb9b87c5 1050 #define CMSDK_PL110_RAWINTSTAT_UART_DSRMODINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_UARTD_SRMODINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_UARTD_SRMODINT: Raw Data Set Ready Int Status Mask */
mbed_official 580:3c14cb9b87c5 1051
mbed_official 580:3c14cb9b87c5 1052 #define CMSDK_PL110_RAWINTSTAT_UART_DCDMODINT_Pos 2 /*!< CMSDK_PL110 RAWINTSTAT_UART_DCDMODINT: Raw Data Carrier Detect Int Status Position */
mbed_official 580:3c14cb9b87c5 1053 #define CMSDK_PL110_RAWINTSTAT_UART_DCDMODINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_UART_DCDMODINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_UART_DCDMODINT: Raw Data Carrier Detect Int Status Mask */
mbed_official 580:3c14cb9b87c5 1054
mbed_official 580:3c14cb9b87c5 1055 #define CMSDK_PL110_RAWINTSTAT_UART_CTSMODINT_Pos 1 /*!< CMSDK_PL110 RAWINTSTAT_UART_CTSMODINT: Raw Clear To Send Int Status Position */
mbed_official 580:3c14cb9b87c5 1056 #define CMSDK_PL110_RAWINTSTAT_UART_CTSMODINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_UART_CTSMODINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_UART_CTSMODINT: Raw Clear To Send Int Status Mask */
mbed_official 580:3c14cb9b87c5 1057
mbed_official 580:3c14cb9b87c5 1058 #define CMSDK_PL110_RAWINTSTAT_UART_RIMODINT_Pos 0 /*!< CMSDK_PL110 RAWINTSTAT_UART_RIMODINT: Raw nUARTRI Modem Int Status Position */
mbed_official 580:3c14cb9b87c5 1059 #define CMSDK_PL110_RAWINTSTAT_UART_RIMODINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_UART_RIMODINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_UART_RIMODINT: Raw nUARTRI Modem Int Status Mask */
mbed_official 580:3c14cb9b87c5 1060
mbed_official 580:3c14cb9b87c5 1061 #define CMSDK_PL110_MSKINTSTAT_OVRRUNERRINT_Pos 10 /*!< CMSDK_PL110 MSKINTSTAT_OVRRUNERRINT: Masked Overrun Error Int Status Position */
mbed_official 580:3c14cb9b87c5 1062 #define CMSDK_PL110_MSKINTSTAT_OVRRUNERRINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_OVRRUNERRINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_OVRRUNERRINT: Masked Overrun Error Int Status Mask */
mbed_official 580:3c14cb9b87c5 1063
mbed_official 580:3c14cb9b87c5 1064 #define CMSDK_PL110_MSKINTSTAT_BREAKERRINT_Pos 9 /*!< CMSDK_PL110 MSKINTSTAT_BREAKERRINT: Masked Break Error Int Status Position */
mbed_official 580:3c14cb9b87c5 1065 #define CMSDK_PL110_MSKINTSTAT_BREAKERRINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_BREAKERRINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_BREAKERRINT: Masked Break Error Int Status Mask */
mbed_official 580:3c14cb9b87c5 1066
mbed_official 580:3c14cb9b87c5 1067 #define CMSDK_PL110_MSKINTSTAT_PARITYERRINT_Pos 8 /*!< CMSDK_PL110 MSKINTSTAT_PARITYERRINT: Masked Parity Error Int Status Position */
mbed_official 580:3c14cb9b87c5 1068 #define CMSDK_PL110_MSKINTSTAT_PARITYERRINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_PARITYERRINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_PARITYERRINT: Masked Parity Error Int Status Mask */
mbed_official 580:3c14cb9b87c5 1069
mbed_official 580:3c14cb9b87c5 1070 #define CMSDK_PL110_MSKINTSTAT_FRAMEERRINT_Pos 7 /*!< CMSDK_PL110 MSKINTSTAT_FRAMEERRINT: Masked Frame Error Int Status Position */
mbed_official 580:3c14cb9b87c5 1071 #define CMSDK_PL110_MSKINTSTAT_FRAMEERRINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_FRAMEERRINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_FRAMEERRINT: Masked Frame Error Int Status Mask */
mbed_official 580:3c14cb9b87c5 1072
mbed_official 580:3c14cb9b87c5 1073 #define CMSDK_PL110_MSKINTSTAT_RECTRANSINT_Pos 6 /*!< CMSDK_PL110 MSKINTSTAT_RECTRANSINT: Masked Transmit Receive Comb Int Status Position */
mbed_official 580:3c14cb9b87c5 1074 #define CMSDK_PL110_MSKINTSTAT_RECTRANSINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_RECTRANSINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_RECTRANSINT: Masked Transmit Receive Comb Int Status Mask */
mbed_official 580:3c14cb9b87c5 1075
mbed_official 580:3c14cb9b87c5 1076 #define CMSDK_PL110_MSKINTSTAT_TRANSINT_Pos 5 /*!< CMSDK_PL110 MSKINTSTAT_TRANSINT: Masked Transmit Int Status Position */
mbed_official 580:3c14cb9b87c5 1077 #define CMSDK_PL110_MSKINTSTAT_TRANSINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_TRANSINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_TRANSINT: Masked Transmit Int Status Mask */
mbed_official 580:3c14cb9b87c5 1078
mbed_official 580:3c14cb9b87c5 1079 #define CMSDK_PL110_MSKINTSTAT_RECINT_Pos 4 /*!< CMSDK_PL110 MSKINTSTAT_RECINT: Masked Receive Int Status Position */
mbed_official 580:3c14cb9b87c5 1080 #define CMSDK_PL110_MSKINTSTAT_RECINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_RECINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_RECINT: Masked Receive Int Status Mask */
mbed_official 580:3c14cb9b87c5 1081
mbed_official 580:3c14cb9b87c5 1082 #define CMSDK_PL110_MSKINTSTAT_UART_DSRMODINT_Pos 3 /*!< CMSDK_PL110 MSKINTSTAT_UART_DSRMODINT: Masked Data Set Ready Int Status Position */
mbed_official 580:3c14cb9b87c5 1083 #define CMSDK_PL110_MSKINTSTAT_UART_DSRMODINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_UARTD_SRMODINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_UART_DSRMODINT: Masked Data Set Ready Int Status Mask */
mbed_official 580:3c14cb9b87c5 1084
mbed_official 580:3c14cb9b87c5 1085 #define CMSDK_PL110_MSKINTSTAT_UART_DCDMODINT_Pos 2 /*!< CMSDK_PL110 MSKINTSTAT_UART_DCDMODINT: Masked Data Carrier Detect Int Status Position */
mbed_official 580:3c14cb9b87c5 1086 #define CMSDK_PL110_MSKINTSTAT_UART_DCDMODINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_UART_DCDMODINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_UART_DCDMODINT: Masked Data Carrier Detect Int Status Mask */
mbed_official 580:3c14cb9b87c5 1087
mbed_official 580:3c14cb9b87c5 1088 #define CMSDK_PL110_MSKINTSTAT_UART_CTSMODINT_Pos 1 /*!< CMSDK_PL110 MSKINTSTAT_UART_CTSMODINT: Masked Clear To Send Int Status Position */
mbed_official 580:3c14cb9b87c5 1089 #define CMSDK_PL110_MSKINTSTAT_UART_CTSMODINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_UART_CTSMODINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_UART_CTSMODINT: Masked Clear To Send Int Status Mask */
mbed_official 580:3c14cb9b87c5 1090
mbed_official 580:3c14cb9b87c5 1091 #define CMSDK_PL110_MSKINTSTAT_UART_RIMODINT_Pos 0 /*!< CMSDK_PL110 MSKINTSTAT_UART_RIMODINT: Masked nUARTRI Modem Int Status Position */
mbed_official 580:3c14cb9b87c5 1092 #define CMSDK_PL110_MSKINTSTAT_UART_RIMODINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_UART_RIMODINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_UART_RIMODINT: Masked nUARTRI Modem Int Status Mask */
mbed_official 580:3c14cb9b87c5 1093
mbed_official 580:3c14cb9b87c5 1094 #define CMSDK_PL110_INTCLR_OVRRUNERRINT_Pos 10 /*!< CMSDK_PL110 INTCLR_OVRRUNERRINT: Clear Overrun Error Int Position */
mbed_official 580:3c14cb9b87c5 1095 #define CMSDK_PL110_INTCLR_OVRRUNERRINT_Msk (0x1ul << CMSDK_PL110_INTCLR_OVRRUNERRINT_Pos) /*!< CMSDK_PL110 INTCLR_OVRRUNERRINT: Clear Overrun Error Int Mask */
mbed_official 580:3c14cb9b87c5 1096
mbed_official 580:3c14cb9b87c5 1097 #define CMSDK_PL110_INTCLR_BREAKERRINT_Pos 9 /*!< CMSDK_PL110 INTCLR_BREAKERRINT: Clear Break Error Int Position */
mbed_official 580:3c14cb9b87c5 1098 #define CMSDK_PL110_INTCLR_BREAKERRINT_Msk (0x1ul << CMSDK_PL110_INTCLR_BREAKERRINT_Pos) /*!< CMSDK_PL110 INTCLR_BREAKERRINT: Clear Break Error Int Mask */
mbed_official 580:3c14cb9b87c5 1099
mbed_official 580:3c14cb9b87c5 1100 #define CMSDK_PL110_INTCLR_PARITYERRINT_Pos 8 /*!< CMSDK_PL110 INTCLR_PARITYERRINT: Clear Parity Error Int Position */
mbed_official 580:3c14cb9b87c5 1101 #define CMSDK_PL110_INTCLR_PARITYERRINT_Msk (0x1ul << CMSDK_PL110_INTCLR_PARITYERRINT_Pos) /*!< CMSDK_PL110 INTCLR_PARITYERRINT: Clear Parity Error Int Mask */
mbed_official 580:3c14cb9b87c5 1102
mbed_official 580:3c14cb9b87c5 1103 #define CMSDK_PL110_INTCLR_FRAMEERRINT_Pos 7 /*!< CMSDK_PL110 INTCLR_FRAMEERRINT: Clear Frame Error Int Position */
mbed_official 580:3c14cb9b87c5 1104 #define CMSDK_PL110_INTCLR_FRAMEERRINT_Msk (0x1ul << CMSDK_PL110_INTCLR_FRAMEERRINT_Pos) /*!< CMSDK_PL110 INTCLR_FRAMEERRINT: Clear Frame Error Int Mask */
mbed_official 580:3c14cb9b87c5 1105
mbed_official 580:3c14cb9b87c5 1106 #define CMSDK_PL110_INTCLR_RECTRANSINT_Pos 6 /*!< CMSDK_PL110 INTCLR_RECTRANSINT: Clear Receive Transmit Comb Int Position */
mbed_official 580:3c14cb9b87c5 1107 #define CMSDK_PL110_INTCLR_RECTRANSINT_Msk (0x1ul << CMSDK_PL110_INTCLR_RECTRANSINT_Pos) /*!< CMSDK_PL110 INTCLR_RECTRANSINT: Clear Receive Transmit Comb Int Mask */
mbed_official 580:3c14cb9b87c5 1108
mbed_official 580:3c14cb9b87c5 1109 #define CMSDK_PL110_INTCLR_TRANSINT_Pos 5 /*!< CMSDK_PL110 INTCLR_TRANSINT: Clear Transmit Int Position */
mbed_official 580:3c14cb9b87c5 1110 #define CMSDK_PL110_INTCLR_TRANSINT_Msk (0x1ul << CMSDK_PL110_INTCLR_TRANSINT_Pos) /*!< CMSDK_PL110 INTCLR_TRANSINT: Clear Transmit Int Mask */
mbed_official 580:3c14cb9b87c5 1111
mbed_official 580:3c14cb9b87c5 1112 #define CMSDK_PL110_INTCLR_RECINT_Pos 4 /*!< CMSDK_PL110 INTCLR_RECINT: Clear Receive Int Position */
mbed_official 580:3c14cb9b87c5 1113 #define CMSDK_PL110_INTCLR_RECINT_Msk (0x1ul << CMSDK_PL110_INTCLR_RECINT_Pos) /*!< CMSDK_PL110 INTCLR_RECINT: Clear Receive Int Mask */
mbed_official 580:3c14cb9b87c5 1114
mbed_official 580:3c14cb9b87c5 1115 #define CMSDK_PL110_INTCLR_UART_DSRMODINT_Pos 3 /*!< CMSDK_PL110 INTCLR_UART_DSRMODINT: Clear Data Carrier Detect Int Position */
mbed_official 580:3c14cb9b87c5 1116 #define CMSDK_PL110_INTCLR_UART_DSRMODINT_Msk (0x1ul << CMSDK_PL110_INTCLR_UARTD_SRMODINT_Pos) /*!< CMSDK_PL110 INTCLR_UARTD_SRMODINT: Clear Data Carrier Detect Int Mask */
mbed_official 580:3c14cb9b87c5 1117
mbed_official 580:3c14cb9b87c5 1118 #define CMSDK_PL110_INTCLR_UART_DCDMODINT_Pos 2 /*!< CMSDK_PL110 INTCLR_UART_DCDMODINT: Clear Data Set Ready Int Position */
mbed_official 580:3c14cb9b87c5 1119 #define CMSDK_PL110_INTCLR_UART_DCDMODINT_Msk (0x1ul << CMSDK_PL110_INTCLR_UART_DCDMODINT_Pos) /*!< CMSDK_PL110 INTCLR_UART_DCDMODINT: Clear Data Set Ready Int Mask */
mbed_official 580:3c14cb9b87c5 1120
mbed_official 580:3c14cb9b87c5 1121 #define CMSDK_PL110_INTCLR_UART_CTSMODINT_Pos 1 /*!< CMSDK_PL110 INTCLR_UART_CTSMODINT: Clear Clear To Sent Int Position */
mbed_official 580:3c14cb9b87c5 1122 #define CMSDK_PL110_INTCLR_UART_CTSMODINT_Msk (0x1ul << CMSDK_PL110_INTCLR_UART_CTSMODINT_Pos) /*!< CMSDK_PL110 INTCLR_UART_CTSMODINT: Clear Clear To Sent Int Mask */
mbed_official 580:3c14cb9b87c5 1123
mbed_official 580:3c14cb9b87c5 1124 #define CMSDK_PL110_INTCLR_UART_RIMODINT_Pos 0 /*!< CMSDK_PL110 INTCLR_UART_RIMODINT: Clear nUARTRI Modem Int Position */
mbed_official 580:3c14cb9b87c5 1125 #define CMSDK_PL110_INTCLR_UART_RIMODINT_Msk (0x1ul << CMSDK_PL110_INTCLR_UART_RIMODINT_Pos) /*!< CMSDK_PL110 INTCLR_UART_RIMODINT: Clear nUARTRI Modem Int Mask */
mbed_official 580:3c14cb9b87c5 1126
mbed_official 580:3c14cb9b87c5 1127 #define CMSDK_PL110_DMA_ERR_Pos 2 /*!< CMSDK_PL110 DMA_ERR: DMA Error Position */
mbed_official 580:3c14cb9b87c5 1128 #define CMSDK_PL110_DMA_ERR_Msk (0x1ul << CMSDK_PL110_DMA_ERR_Pos) /*!< CMSDK_PL110 DMA_ERR: DMA Error Mask */
mbed_official 580:3c14cb9b87c5 1129
mbed_official 580:3c14cb9b87c5 1130 #define CMSDK_PL110_DMA_TRANS_EN_Pos 1 /*!< CMSDK_PL110 DMA_TRANS_EN: DMA Transmit Error Position */
mbed_official 580:3c14cb9b87c5 1131 #define CMSDK_PL110_DMA_TRANS_EN_Msk (0x1ul << CMSDK_PL110_DMA_TRANS_EN_Pos) /*!< CMSDK_PL110 DMA_TRANS_EN: DMA Transmit Error Mask */
mbed_official 580:3c14cb9b87c5 1132
mbed_official 580:3c14cb9b87c5 1133 #define CMSDK_PL110_DMA_REC_EN_Pos 0 /*!< CMSDK_PL110 DMA_REC_EN: DMA Receive Error Position */
mbed_official 580:3c14cb9b87c5 1134 #define CMSDK_PL110_DMA_REC_EN_Msk (0x1ul << CMSDK_PL110_DMA_REC_EN_Pos) /*!< CMSDK_PL110 DMA_REC_EN: DMA Receive Error Mask */
mbed_official 580:3c14cb9b87c5 1135
mbed_official 580:3c14cb9b87c5 1136
mbed_official 580:3c14cb9b87c5 1137 /*@}*/ /* end of group CMSDK_PL110 */
mbed_official 580:3c14cb9b87c5 1138
mbed_official 580:3c14cb9b87c5 1139 /*------------------- Watchdog ----------------------------------------------*/
mbed_official 580:3c14cb9b87c5 1140 /** @addtogroup CMSDK_Watchdog CMSDK Watchdog
mbed_official 580:3c14cb9b87c5 1141 @{
mbed_official 580:3c14cb9b87c5 1142 */
mbed_official 580:3c14cb9b87c5 1143 typedef struct
mbed_official 580:3c14cb9b87c5 1144 {
mbed_official 580:3c14cb9b87c5 1145
mbed_official 580:3c14cb9b87c5 1146 __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
mbed_official 580:3c14cb9b87c5 1147 __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
mbed_official 580:3c14cb9b87c5 1148 __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */
mbed_official 580:3c14cb9b87c5 1149 // <o.1> RESEN: Reset enable
mbed_official 580:3c14cb9b87c5 1150 // <o.0> INTEN: Interrupt enable
mbed_official 580:3c14cb9b87c5 1151 // </h>
mbed_official 580:3c14cb9b87c5 1152 __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */
mbed_official 580:3c14cb9b87c5 1153 __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */
mbed_official 580:3c14cb9b87c5 1154 __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */
mbed_official 580:3c14cb9b87c5 1155 uint32_t RESERVED0[762];
mbed_official 580:3c14cb9b87c5 1156 __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */
mbed_official 580:3c14cb9b87c5 1157 uint32_t RESERVED1[191];
mbed_official 580:3c14cb9b87c5 1158 __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
mbed_official 580:3c14cb9b87c5 1159 __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
mbed_official 580:3c14cb9b87c5 1160 }CMSDK_WATCHDOG_TypeDef;
mbed_official 580:3c14cb9b87c5 1161
mbed_official 580:3c14cb9b87c5 1162 #define CMSDK_Watchdog_LOAD_Pos 0 /*!< CMSDK_Watchdog LOAD: LOAD Position */
mbed_official 580:3c14cb9b87c5 1163 #define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /*!< CMSDK_Watchdog LOAD: LOAD Mask */
mbed_official 580:3c14cb9b87c5 1164
mbed_official 580:3c14cb9b87c5 1165 #define CMSDK_Watchdog_VALUE_Pos 0 /*!< CMSDK_Watchdog VALUE: VALUE Position */
mbed_official 580:3c14cb9b87c5 1166 #define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /*!< CMSDK_Watchdog VALUE: VALUE Mask */
mbed_official 580:3c14cb9b87c5 1167
mbed_official 580:3c14cb9b87c5 1168 #define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /*!< CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */
mbed_official 580:3c14cb9b87c5 1169 #define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /*!< CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */
mbed_official 580:3c14cb9b87c5 1170
mbed_official 580:3c14cb9b87c5 1171 #define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /*!< CMSDK_Watchdog CTRL_INTEN: Int Enable Position */
mbed_official 580:3c14cb9b87c5 1172 #define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /*!< CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */
mbed_official 580:3c14cb9b87c5 1173
mbed_official 580:3c14cb9b87c5 1174 #define CMSDK_Watchdog_INTCLR_Pos 0 /*!< CMSDK_Watchdog INTCLR: Int Clear Position */
mbed_official 580:3c14cb9b87c5 1175 #define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /*!< CMSDK_Watchdog INTCLR: Int Clear Mask */
mbed_official 580:3c14cb9b87c5 1176
mbed_official 580:3c14cb9b87c5 1177 #define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /*!< CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */
mbed_official 580:3c14cb9b87c5 1178 #define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /*!< CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */
mbed_official 580:3c14cb9b87c5 1179
mbed_official 580:3c14cb9b87c5 1180 #define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /*!< CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */
mbed_official 580:3c14cb9b87c5 1181 #define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /*!< CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */
mbed_official 580:3c14cb9b87c5 1182
mbed_official 580:3c14cb9b87c5 1183 #define CMSDK_Watchdog_LOCK_Pos 0 /*!< CMSDK_Watchdog LOCK: LOCK Position */
mbed_official 580:3c14cb9b87c5 1184 #define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /*!< CMSDK_Watchdog LOCK: LOCK Mask */
mbed_official 580:3c14cb9b87c5 1185
mbed_official 580:3c14cb9b87c5 1186 #define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /*!< CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */
mbed_official 580:3c14cb9b87c5 1187 #define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /*!< CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */
mbed_official 580:3c14cb9b87c5 1188
mbed_official 580:3c14cb9b87c5 1189 #define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /*!< CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */
mbed_official 580:3c14cb9b87c5 1190 #define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /*!< CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */
mbed_official 580:3c14cb9b87c5 1191
mbed_official 580:3c14cb9b87c5 1192 /*@}*/ /* end of group CMSDK_Watchdog */
mbed_official 580:3c14cb9b87c5 1193
mbed_official 580:3c14cb9b87c5 1194 /*------------------- PrimeCell APB GPIO --------------------------------------*/
mbed_official 580:3c14cb9b87c5 1195 /** @addtogroup CMSDK_PL061 CMSDK APB GPIO
mbed_official 580:3c14cb9b87c5 1196 @{
mbed_official 580:3c14cb9b87c5 1197 */
mbed_official 580:3c14cb9b87c5 1198 typedef struct
mbed_official 580:3c14cb9b87c5 1199 {
mbed_official 580:3c14cb9b87c5 1200
mbed_official 580:3c14cb9b87c5 1201 __IO uint32_t DATA[256];
mbed_official 580:3c14cb9b87c5 1202 __IO uint32_t DIR;
mbed_official 580:3c14cb9b87c5 1203 __IO uint32_t INTSENSE;
mbed_official 580:3c14cb9b87c5 1204 __IO uint32_t INTBOTHEDGE;
mbed_official 580:3c14cb9b87c5 1205 __IO uint32_t INTEVENT;
mbed_official 580:3c14cb9b87c5 1206 __IO uint32_t INTMASK;
mbed_official 580:3c14cb9b87c5 1207 __O uint32_t RAWINTSTAT;
mbed_official 580:3c14cb9b87c5 1208 __O uint32_t MASKINTSTAT;
mbed_official 580:3c14cb9b87c5 1209 __I uint32_t INTCLR;
mbed_official 580:3c14cb9b87c5 1210 __IO uint32_t MODECTRL;
mbed_official 580:3c14cb9b87c5 1211
mbed_official 580:3c14cb9b87c5 1212 }APBGPIO_TypeDef;
mbed_official 580:3c14cb9b87c5 1213
mbed_official 580:3c14cb9b87c5 1214 #define CMSDK_PL061_DATA_Pos 0 /*!< CMSDK_PL061 DATA: DATA Position */
mbed_official 580:3c14cb9b87c5 1215 #define CMSDK_PL061_DATA_Msk (0xFFFFFFFFul << CMSDK_PL061_LOAD_Pos) /*!< CMSDK_PL061 DATA: DATA Mask */
mbed_official 580:3c14cb9b87c5 1216
mbed_official 580:3c14cb9b87c5 1217 #define CMSDK_PL061_DIR_Pos 0 /*!< CMSDK_PL061 DIR: Data Direction Position */
mbed_official 580:3c14cb9b87c5 1218 #define CMSDK_PL061_DIR_Msk (0x1ul << CMSDK_PL061_DIR_Pos) /*!< CMSDK_PL061 DIR: Data Direction Mask */
mbed_official 580:3c14cb9b87c5 1219
mbed_official 580:3c14cb9b87c5 1220 #define CMSDK_PL061_INTSENSE_Pos 0 /*!< CMSDK_PL061 INTSENSE: INT SENSE Position */
mbed_official 580:3c14cb9b87c5 1221 #define CMSDK_PL061_INTSENSE_Msk (0x1ul << CMSDK_PL061_INTSENSE_Pos) /*!< CMSDK_PL061 INTSENSE: INT SENSE Mask */
mbed_official 580:3c14cb9b87c5 1222
mbed_official 580:3c14cb9b87c5 1223 #define CMSDK_PL061_INTBOTHEDGE_Pos 0 /*!< CMSDK_PL061 INTBOTHEDGE: INT BOTH EDGE Position */
mbed_official 580:3c14cb9b87c5 1224 #define CMSDK_PL061_INTBOTHEDGE_Msk (0x1ul << CMSDK_PL061_INTBOTHEDGE_Pos) /*!< CMSDK_PL061 INTBOTHEDGE: INT BOTH EDGE Mask */
mbed_official 580:3c14cb9b87c5 1225
mbed_official 580:3c14cb9b87c5 1226 #define CMSDK_PL061_INTEVENT_Pos 0 /*!< CMSDK_PL061 INTEVENT: INT EVENT Position */
mbed_official 580:3c14cb9b87c5 1227 #define CMSDK_PL061_INTEVENT_Msk (0x1ul << CMSDK_PL061_INTEVENT_Pos) /*!< CMSDK_PL061 INTEVENT: INT EVENT Mask */
mbed_official 580:3c14cb9b87c5 1228
mbed_official 580:3c14cb9b87c5 1229 #define CMSDK_PL061_INTMASK_Pos 0 /*!< CMSDK_PL061 INTMASK: INT MASK Position */
mbed_official 580:3c14cb9b87c5 1230 #define CMSDK_PL061_INTMASK_Msk (0x1ul << CMSDK_PL061_INTMASK_Pos) /*!< CMSDK_PL061 INTMASK: INT MASK Mask */
mbed_official 580:3c14cb9b87c5 1231
mbed_official 580:3c14cb9b87c5 1232 #define CMSDK_PL061_RAWINTSTAT_Pos 0 /*!< CMSDK_PL061 RAWINTSTAT: Raw Int Status Position */
mbed_official 580:3c14cb9b87c5 1233 #define CMSDK_PL061_RAWINTSTAT_Msk (0x1ul << CMSDK_PL061_RAWINTSTAT_Pos) /*!< CMSDK_PL061 RAWINTSTAT: Raw Int Status Mask */
mbed_official 580:3c14cb9b87c5 1234
mbed_official 580:3c14cb9b87c5 1235 #define CMSDK_PL061_MASKINTSTAT_Pos 0 /*!< CMSDK_PL061 MASKINTSTAT: Mask Int Status Position */
mbed_official 580:3c14cb9b87c5 1236 #define CMSDK_PL061_MASKINTSTAT_Msk (0x1ul << CMSDK_PL061_MASKINTSTAT_Pos) /*!< CMSDK_PL061 MASKINTSTAT: Mask Int Status Mask */
mbed_official 580:3c14cb9b87c5 1237
mbed_official 580:3c14cb9b87c5 1238 #define CMSDK_PL061_INTCLR_Pos 0 /*!< CMSDK_PL061 INTCLR: Int Clear Position */
mbed_official 580:3c14cb9b87c5 1239 #define CMSDK_PL061_INTCLR_Msk (0x1ul << CMSDK_PL061_INTCLR_Pos) /*!< CMSDK_PL061 INTCLR: Int Clear Mask */
mbed_official 580:3c14cb9b87c5 1240
mbed_official 580:3c14cb9b87c5 1241 #define CMSDK_PL061_MODECTRL_HWEN_Pos 0 /*!< CMSDK_PL061 MODECTRL_HWEN: Mode Control Hardware Enable Position */
mbed_official 580:3c14cb9b87c5 1242 #define CMSDK_PL061_MODECTRL_HWEN_Msk (0x1ul << CMSDK_PL061_MODECTRL_HWEN_Pos) /*!< CMSDK_PL061 MODECTRL_HWEN: Mode Control Hardware Enable Mask */
mbed_official 580:3c14cb9b87c5 1243
mbed_official 580:3c14cb9b87c5 1244
mbed_official 580:3c14cb9b87c5 1245 /*@}*/ /* end of group CMSDK_PL061 */
mbed_official 580:3c14cb9b87c5 1246
mbed_official 580:3c14cb9b87c5 1247
mbed_official 580:3c14cb9b87c5 1248 #if defined ( __CC_ARM )
mbed_official 580:3c14cb9b87c5 1249 #pragma no_anon_unions
mbed_official 580:3c14cb9b87c5 1250 #endif
mbed_official 580:3c14cb9b87c5 1251
mbed_official 580:3c14cb9b87c5 1252 /*@}*/ /* end of group CMSDK_CM4_Peripherals */
mbed_official 580:3c14cb9b87c5 1253
mbed_official 580:3c14cb9b87c5 1254
mbed_official 580:3c14cb9b87c5 1255 /******************************************************************************/
mbed_official 580:3c14cb9b87c5 1256 /* Peripheral memory map */
mbed_official 580:3c14cb9b87c5 1257 /******************************************************************************/
mbed_official 580:3c14cb9b87c5 1258 /** @addtogroup CMSDK_CM4_MemoryMap CMSDK_CM4 Memory Mapping
mbed_official 580:3c14cb9b87c5 1259 @{
mbed_official 580:3c14cb9b87c5 1260 */
mbed_official 580:3c14cb9b87c5 1261
mbed_official 580:3c14cb9b87c5 1262 /* Peripheral and SRAM base address */
mbed_official 580:3c14cb9b87c5 1263 #define CMSDK_FLASH_BASE (0x00000000UL) /*!< (FLASH ) Base Address */
mbed_official 580:3c14cb9b87c5 1264 #define CMSDK_SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */
mbed_official 580:3c14cb9b87c5 1265 #define CMSDK_PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */
mbed_official 580:3c14cb9b87c5 1266
mbed_official 580:3c14cb9b87c5 1267 /* Base addresses */
mbed_official 580:3c14cb9b87c5 1268 #define CMSDK_RAM_BASE (0x20000000UL)
mbed_official 580:3c14cb9b87c5 1269 #define CMSDK_APB_BASE (0x40000000UL)
mbed_official 580:3c14cb9b87c5 1270 #define CMSDK_AHB_BASE (0x40010000UL)
mbed_official 580:3c14cb9b87c5 1271
mbed_official 580:3c14cb9b87c5 1272 /* APB peripherals */
mbed_official 580:3c14cb9b87c5 1273 #define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL)
mbed_official 580:3c14cb9b87c5 1274 #define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL)
mbed_official 580:3c14cb9b87c5 1275 #define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL)
mbed_official 580:3c14cb9b87c5 1276 #define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE)
mbed_official 580:3c14cb9b87c5 1277 #define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL)
mbed_official 580:3c14cb9b87c5 1278 #define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL)
mbed_official 580:3c14cb9b87c5 1279 #define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL)
mbed_official 580:3c14cb9b87c5 1280 #define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL)
mbed_official 580:3c14cb9b87c5 1281 //#define CMSDK_UART3_BASE (CMSDK_APB_BASE + 0x7000UL) //only used in extended version
mbed_official 580:3c14cb9b87c5 1282 #define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL)
mbed_official 580:3c14cb9b87c5 1283 #define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL)
mbed_official 580:3c14cb9b87c5 1284
mbed_official 580:3c14cb9b87c5 1285 /* AHB peripherals */
mbed_official 580:3c14cb9b87c5 1286 #define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL)
mbed_official 580:3c14cb9b87c5 1287 #define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL)
mbed_official 580:3c14cb9b87c5 1288 #define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL)
mbed_official 580:3c14cb9b87c5 1289 #define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL)
mbed_official 580:3c14cb9b87c5 1290 #define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL)
mbed_official 580:3c14cb9b87c5 1291 /*@}*/ /* end of group CMSDK_CM4_MemoryMap */
mbed_official 580:3c14cb9b87c5 1292
mbed_official 580:3c14cb9b87c5 1293
mbed_official 580:3c14cb9b87c5 1294 /******************************************************************************/
mbed_official 580:3c14cb9b87c5 1295 /* Peripheral declaration */
mbed_official 580:3c14cb9b87c5 1296 /******************************************************************************/
mbed_official 580:3c14cb9b87c5 1297 /** @addtogroup CMSDK_CM4_PeripheralDecl CMSDK_CM4 Peripheral Declaration
mbed_official 580:3c14cb9b87c5 1298 @{
mbed_official 580:3c14cb9b87c5 1299 */
mbed_official 580:3c14cb9b87c5 1300
mbed_official 580:3c14cb9b87c5 1301 #define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
mbed_official 580:3c14cb9b87c5 1302 #define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
mbed_official 580:3c14cb9b87c5 1303 #define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )
mbed_official 580:3c14cb9b87c5 1304 //#define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE ) //only used in extended version
mbed_official 580:3c14cb9b87c5 1305 #define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
mbed_official 580:3c14cb9b87c5 1306 #define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
mbed_official 580:3c14cb9b87c5 1307 #define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )
mbed_official 580:3c14cb9b87c5 1308 #define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE )
mbed_official 580:3c14cb9b87c5 1309 #define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE )
mbed_official 580:3c14cb9b87c5 1310 #define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE )
mbed_official 580:3c14cb9b87c5 1311 #define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE )
mbed_official 580:3c14cb9b87c5 1312 #define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE )
mbed_official 580:3c14cb9b87c5 1313 #define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE )
mbed_official 580:3c14cb9b87c5 1314 #define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE )
mbed_official 580:3c14cb9b87c5 1315 #define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE )
mbed_official 580:3c14cb9b87c5 1316 #define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE )
mbed_official 580:3c14cb9b87c5 1317 /*@}*/ /* end of group CMSDK_CM4_PeripheralDecl */
mbed_official 580:3c14cb9b87c5 1318
mbed_official 580:3c14cb9b87c5 1319 /*@}*/ /* end of group CMSDK_CM4_Definitions */
mbed_official 580:3c14cb9b87c5 1320
mbed_official 580:3c14cb9b87c5 1321 #ifdef __cplusplus
mbed_official 580:3c14cb9b87c5 1322 }
mbed_official 580:3c14cb9b87c5 1323 #endif
mbed_official 580:3c14cb9b87c5 1324
mbed_official 580:3c14cb9b87c5 1325 #endif /* CMSDK_CM4_H */