Kazuki Yamamoto / mbeDshield

The official mbed C/C SDK provides the software platform and libraries to build your applications.

Dependents:   SeeedTouchLCD

Fork of mbed by mbed official

(01.May.2014) started sales! http://www.switch-science.com/catalog/1717/

(13.March.2014) updated to 0.5.0

This is a pin conversion PCB from mbed 1768/11U24 to arduino UNO.

  • So if you have both mbed and arduino shields, I guess you would be happy with such a conversion board :)

Photos

  • Board photo vvv /media/uploads/k4zuki/mbedshield050.brd.png
  • Schematic photo vvv /media/uploads/k4zuki/mbedshield050.sch.png
  • Functionality photo vvv /media/uploads/k4zuki/mbedshieldfunc.jpg

Latest eagle files

PCB >> /media/uploads/k4zuki/mbedshield050.brd
SCH >> /media/uploads/k4zuki/mbedshield050.sch

BIG changes from previous version

  1. Ethernet RJ45 connector is removed.
    1. http://mbed.org/components/Seeed-Ethernet-Shield-V20/ is the biggest hint to use Ethernet!
  2. Most ALL of components can be bought at Akizuki http://akizukidenshi.com/
    1. But sorry, they do not send parts to abroad
  3. Pinout is changed!
arduino0.4.00.5.0
D4p12p21
D5p11p22
MOSI_nonep11
MISO_nonep12
SCK_nonep13

This design has bug(s)

  1. I2C functional pin differs between 1768 and 11U24.

Fixed bugs here

  1. MiniUSB cable cannot be connected on mbed if you solder high-height electrolytic capacitor on C3.
    1. http://akizukidenshi.com/catalog/g/gP-05002/ is the solution to make this 100% AKIZUKI parts!
  2. the 6-pin ISP port is not inprimented in version 0.4.0
    1. it will be fixed in later version 0.4.1/0.4.2/0.5.0 This has beenfixed

I am doing some porting to use existing arduino shields but it may faster if you do it by yourself...

you can use arduino PinName "A0-A5,D0-D13" plus backside SPI port for easier porting.

To do this you have to edit PinName enum in

  • "mbed/TARGET_LPC1768/PinNames.h" or
  • "mbed/TARGET_LPC11U24/PinNames.h" as per your target mbed.

here is the actual list: This list includes define switch to switch pin assignment

part_of_PinNames.h

        USBTX = P0_2,
        USBRX = P0_3,

//from here mbeDshield mod
        D0=p27,
        D1=p28,
        D2=p14,
        D3=p13,
#ifdef MBEDSHIELD_050
        MOSI_=p11,
        MISO_=p12,
        SCK_=p13,
        D4=p21,
        D5=p22,
#else
        D4=p12,
        D5=p11,
#endif
        D6=p23,
        D7=p24,
        D8=p25,
        D9=p26,
        D10=p8,
        D11=p5,
        D12=p6,
        D13=p7,
        A0=p15,
        A1=p16,
        A2=p17,
        A3=p18,
        A4=p19,
        A5=p20,
        SDA=p9,
        SCL=p10,
//mbeDshield mod ends here
        // Not connected
        NC = (int)0xFFFFFFFF

LPC11U24/ARM/core_cm0.h@31:a7ef757f598c, 2012-01-06 (annotated)

Committer:
emilmont
Date:
Fri Jan 06 12:02:19 2012 +0000
Revision:
31:a7ef757f598c
Parent:
27:7110ebee3484 
[06 January 2012] Minor fixes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 27:7110ebee3484 1 /**************************************************************************//**
emilmont 27:7110ebee3484 2 * @file core_cm0.h
emilmont 27:7110ebee3484 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
emilmont 31:a7ef757f598c 4 * @version V3.00
emilmont 31:a7ef757f598c 5 * @date 09. December 2011
emilmont 27:7110ebee3484 6 *
emilmont 27:7110ebee3484 7 * @note
emilmont 27:7110ebee3484 8 * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
emilmont 27:7110ebee3484 9 *
emilmont 27:7110ebee3484 10 * @par
emilmont 31:a7ef757f598c 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
emilmont 31:a7ef757f598c 12 * processor based microcontrollers. This file can be freely distributed
emilmont 31:a7ef757f598c 13 * within development tools that are supporting such ARM based processors.
emilmont 27:7110ebee3484 14 *
emilmont 27:7110ebee3484 15 * @par
emilmont 27:7110ebee3484 16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
emilmont 27:7110ebee3484 17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
emilmont 27:7110ebee3484 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
emilmont 27:7110ebee3484 19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
emilmont 27:7110ebee3484 20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
emilmont 27:7110ebee3484 21 *
emilmont 27:7110ebee3484 22 ******************************************************************************/
emilmont 31:a7ef757f598c 23 #if defined ( __ICCARM__ )
emilmont 27:7110ebee3484 24 #pragma system_include /* treat file as system include file for MISRA check */
emilmont 27:7110ebee3484 25 #endif
emilmont 27:7110ebee3484 26
emilmont 27:7110ebee3484 27 #ifdef __cplusplus
emilmont 27:7110ebee3484 28 extern "C" {
emilmont 31:a7ef757f598c 29 #endif
emilmont 27:7110ebee3484 30
emilmont 27:7110ebee3484 31 #ifndef __CORE_CM0_H_GENERIC
emilmont 27:7110ebee3484 32 #define __CORE_CM0_H_GENERIC
emilmont 27:7110ebee3484 33
emilmont 31:a7ef757f598c 34 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
emilmont 31:a7ef757f598c 35 CMSIS violates the following MISRA-C:2004 rules:
emilmont 31:a7ef757f598c 36
emilmont 31:a7ef757f598c 37 \li Required Rule 8.5, object/function definition in header file.<br>
emilmont 31:a7ef757f598c 38 Function definitions in header files are used to allow 'inlining'.
emilmont 27:7110ebee3484 39
emilmont 31:a7ef757f598c 40 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
emilmont 31:a7ef757f598c 41 Unions are used for effective representation of core registers.
emilmont 27:7110ebee3484 42
emilmont 31:a7ef757f598c 43 \li Advisory Rule 19.7, Function-like macro defined.<br>
emilmont 31:a7ef757f598c 44 Function-like macros are used to allow more efficient code.
emilmont 27:7110ebee3484 45 */
emilmont 27:7110ebee3484 46
emilmont 27:7110ebee3484 47
emilmont 27:7110ebee3484 48 /*******************************************************************************
emilmont 27:7110ebee3484 49 * CMSIS definitions
emilmont 27:7110ebee3484 50 ******************************************************************************/
emilmont 31:a7ef757f598c 51 /** \ingroup Cortex_M0
emilmont 27:7110ebee3484 52 @{
emilmont 27:7110ebee3484 53 */
emilmont 27:7110ebee3484 54
emilmont 27:7110ebee3484 55 /* CMSIS CM0 definitions */
emilmont 31:a7ef757f598c 56 #define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
emilmont 31:a7ef757f598c 57 #define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
emilmont 31:a7ef757f598c 58 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
emilmont 31:a7ef757f598c 59 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
emilmont 27:7110ebee3484 60
emilmont 31:a7ef757f598c 61 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
emilmont 27:7110ebee3484 62
emilmont 27:7110ebee3484 63
emilmont 31:a7ef757f598c 64 #if defined ( __CC_ARM )
emilmont 27:7110ebee3484 65 #define __ASM __asm /*!< asm keyword for ARM Compiler */
emilmont 27:7110ebee3484 66 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
emilmont 27:7110ebee3484 67
emilmont 27:7110ebee3484 68 #elif defined ( __ICCARM__ )
emilmont 27:7110ebee3484 69 #define __ASM __asm /*!< asm keyword for IAR Compiler */
emilmont 27:7110ebee3484 70 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
emilmont 27:7110ebee3484 71
emilmont 31:a7ef757f598c 72 #elif defined ( __GNUC__ )
emilmont 27:7110ebee3484 73 #define __ASM __asm /*!< asm keyword for GNU Compiler */
emilmont 27:7110ebee3484 74 #define __INLINE inline /*!< inline keyword for GNU Compiler */
emilmont 27:7110ebee3484 75
emilmont 31:a7ef757f598c 76 #elif defined ( __TASKING__ )
emilmont 27:7110ebee3484 77 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
emilmont 27:7110ebee3484 78 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
emilmont 27:7110ebee3484 79
emilmont 27:7110ebee3484 80 #endif
emilmont 27:7110ebee3484 81
emilmont 31:a7ef757f598c 82 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
emilmont 31:a7ef757f598c 83 */
emilmont 31:a7ef757f598c 84 #define __FPU_USED 0
emilmont 31:a7ef757f598c 85
emilmont 31:a7ef757f598c 86 #if defined ( __CC_ARM )
emilmont 31:a7ef757f598c 87 #if defined __TARGET_FPU_VFP
emilmont 31:a7ef757f598c 88 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 31:a7ef757f598c 89 #endif
emilmont 31:a7ef757f598c 90
emilmont 31:a7ef757f598c 91 #elif defined ( __ICCARM__ )
emilmont 31:a7ef757f598c 92 #if defined __ARMVFP__
emilmont 31:a7ef757f598c 93 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 31:a7ef757f598c 94 #endif
emilmont 31:a7ef757f598c 95
emilmont 31:a7ef757f598c 96 #elif defined ( __GNUC__ )
emilmont 31:a7ef757f598c 97 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
emilmont 31:a7ef757f598c 98 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 31:a7ef757f598c 99 #endif
emilmont 31:a7ef757f598c 100
emilmont 31:a7ef757f598c 101 #elif defined ( __TASKING__ )
emilmont 31:a7ef757f598c 102 /* add preprocessor checks */
emilmont 31:a7ef757f598c 103 #endif
emilmont 31:a7ef757f598c 104
emilmont 31:a7ef757f598c 105 #include <stdint.h> /* standard types definitions */
emilmont 31:a7ef757f598c 106 #include <core_cmInstr.h> /* Core Instruction Access */
emilmont 31:a7ef757f598c 107 #include <core_cmFunc.h> /* Core Function Access */
emilmont 27:7110ebee3484 108
emilmont 27:7110ebee3484 109 #endif /* __CORE_CM0_H_GENERIC */
emilmont 27:7110ebee3484 110
emilmont 27:7110ebee3484 111 #ifndef __CMSIS_GENERIC
emilmont 27:7110ebee3484 112
emilmont 27:7110ebee3484 113 #ifndef __CORE_CM0_H_DEPENDANT
emilmont 27:7110ebee3484 114 #define __CORE_CM0_H_DEPENDANT
emilmont 27:7110ebee3484 115
emilmont 31:a7ef757f598c 116 /* check device defines and use defaults */
emilmont 31:a7ef757f598c 117 #if defined __CHECK_DEVICE_DEFINES
emilmont 31:a7ef757f598c 118 #ifndef __CM0_REV
emilmont 31:a7ef757f598c 119 #define __CM0_REV 0x0000
emilmont 31:a7ef757f598c 120 #warning "__CM0_REV not defined in device header file; using default!"
emilmont 31:a7ef757f598c 121 #endif
emilmont 31:a7ef757f598c 122
emilmont 31:a7ef757f598c 123 #ifndef __NVIC_PRIO_BITS
emilmont 31:a7ef757f598c 124 #define __NVIC_PRIO_BITS 2
emilmont 31:a7ef757f598c 125 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
emilmont 31:a7ef757f598c 126 #endif
emilmont 31:a7ef757f598c 127
emilmont 31:a7ef757f598c 128 #ifndef __Vendor_SysTickConfig
emilmont 31:a7ef757f598c 129 #define __Vendor_SysTickConfig 0
emilmont 31:a7ef757f598c 130 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
emilmont 31:a7ef757f598c 131 #endif
emilmont 31:a7ef757f598c 132 #endif
emilmont 31:a7ef757f598c 133
emilmont 27:7110ebee3484 134 /* IO definitions (access restrictions to peripheral registers) */
emilmont 31:a7ef757f598c 135 /**
emilmont 31:a7ef757f598c 136 \defgroup CMSIS_glob_defs CMSIS Global Defines
emilmont 31:a7ef757f598c 137
emilmont 31:a7ef757f598c 138 <strong>IO Type Qualifiers</strong> are used
emilmont 31:a7ef757f598c 139 \li to specify the access to peripheral variables.
emilmont 31:a7ef757f598c 140 \li for automatic generation of peripheral register debug information.
emilmont 31:a7ef757f598c 141 */
emilmont 27:7110ebee3484 142 #ifdef __cplusplus
emilmont 31:a7ef757f598c 143 #define __I volatile /*!< Defines 'read only' permissions */
emilmont 27:7110ebee3484 144 #else
emilmont 31:a7ef757f598c 145 #define __I volatile const /*!< Defines 'read only' permissions */
emilmont 27:7110ebee3484 146 #endif
emilmont 31:a7ef757f598c 147 #define __O volatile /*!< Defines 'write only' permissions */
emilmont 31:a7ef757f598c 148 #define __IO volatile /*!< Defines 'read / write' permissions */
emilmont 27:7110ebee3484 149
emilmont 31:a7ef757f598c 150 /*@} end of group Cortex_M0 */
emilmont 27:7110ebee3484 151
emilmont 27:7110ebee3484 152
emilmont 27:7110ebee3484 153
emilmont 27:7110ebee3484 154 /*******************************************************************************
emilmont 27:7110ebee3484 155 * Register Abstraction
emilmont 27:7110ebee3484 156 Core Register contain:
emilmont 27:7110ebee3484 157 - Core Register
emilmont 27:7110ebee3484 158 - Core NVIC Register
emilmont 27:7110ebee3484 159 - Core SCB Register
emilmont 27:7110ebee3484 160 - Core SysTick Register
emilmont 31:a7ef757f598c 161 ******************************************************************************/
emilmont 31:a7ef757f598c 162 /** \defgroup CMSIS_core_register Defines and Type Definitions
emilmont 31:a7ef757f598c 163 \brief Type definitions and defines for Cortex-M processor based devices.
emilmont 27:7110ebee3484 164 */
emilmont 27:7110ebee3484 165
emilmont 31:a7ef757f598c 166 /** \ingroup CMSIS_core_register
emilmont 31:a7ef757f598c 167 \defgroup CMSIS_CORE Status and Control Registers
emilmont 31:a7ef757f598c 168 \brief Core Register type definitions.
emilmont 27:7110ebee3484 169 @{
emilmont 27:7110ebee3484 170 */
emilmont 27:7110ebee3484 171
emilmont 27:7110ebee3484 172 /** \brief Union type to access the Application Program Status Register (APSR).
emilmont 27:7110ebee3484 173 */
emilmont 27:7110ebee3484 174 typedef union
emilmont 27:7110ebee3484 175 {
emilmont 27:7110ebee3484 176 struct
emilmont 27:7110ebee3484 177 {
emilmont 27:7110ebee3484 178 #if (__CORTEX_M != 0x04)
emilmont 27:7110ebee3484 179 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
emilmont 27:7110ebee3484 180 #else
emilmont 27:7110ebee3484 181 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
emilmont 27:7110ebee3484 182 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
emilmont 27:7110ebee3484 183 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
emilmont 27:7110ebee3484 184 #endif
emilmont 27:7110ebee3484 185 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
emilmont 27:7110ebee3484 186 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
emilmont 27:7110ebee3484 187 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
emilmont 27:7110ebee3484 188 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
emilmont 27:7110ebee3484 189 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
emilmont 27:7110ebee3484 190 } b; /*!< Structure used for bit access */
emilmont 31:a7ef757f598c 191 uint32_t w; /*!< Type used for word access */
emilmont 27:7110ebee3484 192 } APSR_Type;
emilmont 27:7110ebee3484 193
emilmont 27:7110ebee3484 194
emilmont 27:7110ebee3484 195 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
emilmont 27:7110ebee3484 196 */
emilmont 27:7110ebee3484 197 typedef union
emilmont 27:7110ebee3484 198 {
emilmont 27:7110ebee3484 199 struct
emilmont 27:7110ebee3484 200 {
emilmont 27:7110ebee3484 201 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
emilmont 27:7110ebee3484 202 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
emilmont 27:7110ebee3484 203 } b; /*!< Structure used for bit access */
emilmont 27:7110ebee3484 204 uint32_t w; /*!< Type used for word access */
emilmont 27:7110ebee3484 205 } IPSR_Type;
emilmont 27:7110ebee3484 206
emilmont 27:7110ebee3484 207
emilmont 27:7110ebee3484 208 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
emilmont 27:7110ebee3484 209 */
emilmont 27:7110ebee3484 210 typedef union
emilmont 27:7110ebee3484 211 {
emilmont 27:7110ebee3484 212 struct
emilmont 27:7110ebee3484 213 {
emilmont 27:7110ebee3484 214 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
emilmont 27:7110ebee3484 215 #if (__CORTEX_M != 0x04)
emilmont 27:7110ebee3484 216 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
emilmont 27:7110ebee3484 217 #else
emilmont 27:7110ebee3484 218 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
emilmont 27:7110ebee3484 219 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
emilmont 27:7110ebee3484 220 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
emilmont 27:7110ebee3484 221 #endif
emilmont 27:7110ebee3484 222 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
emilmont 27:7110ebee3484 223 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
emilmont 27:7110ebee3484 224 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
emilmont 27:7110ebee3484 225 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
emilmont 27:7110ebee3484 226 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
emilmont 27:7110ebee3484 227 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
emilmont 27:7110ebee3484 228 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
emilmont 27:7110ebee3484 229 } b; /*!< Structure used for bit access */
emilmont 27:7110ebee3484 230 uint32_t w; /*!< Type used for word access */
emilmont 27:7110ebee3484 231 } xPSR_Type;
emilmont 27:7110ebee3484 232
emilmont 27:7110ebee3484 233
emilmont 27:7110ebee3484 234 /** \brief Union type to access the Control Registers (CONTROL).
emilmont 27:7110ebee3484 235 */
emilmont 27:7110ebee3484 236 typedef union
emilmont 27:7110ebee3484 237 {
emilmont 27:7110ebee3484 238 struct
emilmont 27:7110ebee3484 239 {
emilmont 27:7110ebee3484 240 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
emilmont 27:7110ebee3484 241 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
emilmont 27:7110ebee3484 242 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
emilmont 27:7110ebee3484 243 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
emilmont 27:7110ebee3484 244 } b; /*!< Structure used for bit access */
emilmont 27:7110ebee3484 245 uint32_t w; /*!< Type used for word access */
emilmont 27:7110ebee3484 246 } CONTROL_Type;
emilmont 27:7110ebee3484 247
emilmont 27:7110ebee3484 248 /*@} end of group CMSIS_CORE */
emilmont 27:7110ebee3484 249
emilmont 27:7110ebee3484 250
emilmont 31:a7ef757f598c 251 /** \ingroup CMSIS_core_register
emilmont 31:a7ef757f598c 252 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
emilmont 31:a7ef757f598c 253 \brief Type definitions for the NVIC Registers
emilmont 27:7110ebee3484 254 @{
emilmont 27:7110ebee3484 255 */
emilmont 27:7110ebee3484 256
emilmont 27:7110ebee3484 257 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
emilmont 27:7110ebee3484 258 */
emilmont 27:7110ebee3484 259 typedef struct
emilmont 27:7110ebee3484 260 {
emilmont 27:7110ebee3484 261 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
emilmont 27:7110ebee3484 262 uint32_t RESERVED0[31];
emilmont 27:7110ebee3484 263 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
emilmont 27:7110ebee3484 264 uint32_t RSERVED1[31];
emilmont 27:7110ebee3484 265 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
emilmont 27:7110ebee3484 266 uint32_t RESERVED2[31];
emilmont 27:7110ebee3484 267 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
emilmont 27:7110ebee3484 268 uint32_t RESERVED3[31];
emilmont 27:7110ebee3484 269 uint32_t RESERVED4[64];
emilmont 31:a7ef757f598c 270 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
emilmont 27:7110ebee3484 271 } NVIC_Type;
emilmont 27:7110ebee3484 272
emilmont 27:7110ebee3484 273 /*@} end of group CMSIS_NVIC */
emilmont 27:7110ebee3484 274
emilmont 27:7110ebee3484 275
emilmont 31:a7ef757f598c 276 /** \ingroup CMSIS_core_register
emilmont 31:a7ef757f598c 277 \defgroup CMSIS_SCB System Control Block (SCB)
emilmont 31:a7ef757f598c 278 \brief Type definitions for the System Control Block Registers
emilmont 27:7110ebee3484 279 @{
emilmont 27:7110ebee3484 280 */
emilmont 27:7110ebee3484 281
emilmont 27:7110ebee3484 282 /** \brief Structure type to access the System Control Block (SCB).
emilmont 27:7110ebee3484 283 */
emilmont 27:7110ebee3484 284 typedef struct
emilmont 27:7110ebee3484 285 {
emilmont 31:a7ef757f598c 286 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
emilmont 31:a7ef757f598c 287 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
emilmont 31:a7ef757f598c 288 uint32_t RESERVED0;
emilmont 31:a7ef757f598c 289 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
emilmont 27:7110ebee3484 290 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
emilmont 27:7110ebee3484 291 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
emilmont 31:a7ef757f598c 292 uint32_t RESERVED1;
emilmont 27:7110ebee3484 293 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
emilmont 31:a7ef757f598c 294 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
emilmont 31:a7ef757f598c 295 } SCB_Type;
emilmont 27:7110ebee3484 296
emilmont 27:7110ebee3484 297 /* SCB CPUID Register Definitions */
emilmont 27:7110ebee3484 298 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
emilmont 27:7110ebee3484 299 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
emilmont 27:7110ebee3484 300
emilmont 27:7110ebee3484 301 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
emilmont 27:7110ebee3484 302 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
emilmont 27:7110ebee3484 303
emilmont 27:7110ebee3484 304 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
emilmont 27:7110ebee3484 305 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
emilmont 27:7110ebee3484 306
emilmont 27:7110ebee3484 307 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
emilmont 27:7110ebee3484 308 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
emilmont 27:7110ebee3484 309
emilmont 27:7110ebee3484 310 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
emilmont 27:7110ebee3484 311 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
emilmont 27:7110ebee3484 312
emilmont 27:7110ebee3484 313 /* SCB Interrupt Control State Register Definitions */
emilmont 27:7110ebee3484 314 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
emilmont 27:7110ebee3484 315 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
emilmont 27:7110ebee3484 316
emilmont 27:7110ebee3484 317 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
emilmont 27:7110ebee3484 318 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
emilmont 27:7110ebee3484 319
emilmont 27:7110ebee3484 320 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
emilmont 27:7110ebee3484 321 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
emilmont 27:7110ebee3484 322
emilmont 27:7110ebee3484 323 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
emilmont 27:7110ebee3484 324 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
emilmont 27:7110ebee3484 325
emilmont 27:7110ebee3484 326 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
emilmont 27:7110ebee3484 327 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
emilmont 27:7110ebee3484 328
emilmont 27:7110ebee3484 329 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
emilmont 27:7110ebee3484 330 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
emilmont 27:7110ebee3484 331
emilmont 27:7110ebee3484 332 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
emilmont 27:7110ebee3484 333 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
emilmont 27:7110ebee3484 334
emilmont 27:7110ebee3484 335 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
emilmont 27:7110ebee3484 336 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
emilmont 27:7110ebee3484 337
emilmont 27:7110ebee3484 338 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
emilmont 27:7110ebee3484 339 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
emilmont 27:7110ebee3484 340
emilmont 27:7110ebee3484 341 /* SCB Application Interrupt and Reset Control Register Definitions */
emilmont 27:7110ebee3484 342 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
emilmont 27:7110ebee3484 343 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
emilmont 27:7110ebee3484 344
emilmont 27:7110ebee3484 345 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
emilmont 27:7110ebee3484 346 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
emilmont 27:7110ebee3484 347
emilmont 27:7110ebee3484 348 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
emilmont 27:7110ebee3484 349 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
emilmont 27:7110ebee3484 350
emilmont 27:7110ebee3484 351 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
emilmont 27:7110ebee3484 352 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
emilmont 27:7110ebee3484 353
emilmont 27:7110ebee3484 354 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
emilmont 27:7110ebee3484 355 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
emilmont 27:7110ebee3484 356
emilmont 27:7110ebee3484 357 /* SCB System Control Register Definitions */
emilmont 27:7110ebee3484 358 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
emilmont 27:7110ebee3484 359 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
emilmont 27:7110ebee3484 360
emilmont 27:7110ebee3484 361 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
emilmont 27:7110ebee3484 362 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
emilmont 27:7110ebee3484 363
emilmont 27:7110ebee3484 364 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
emilmont 27:7110ebee3484 365 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
emilmont 27:7110ebee3484 366
emilmont 27:7110ebee3484 367 /* SCB Configuration Control Register Definitions */
emilmont 27:7110ebee3484 368 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
emilmont 27:7110ebee3484 369 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
emilmont 27:7110ebee3484 370
emilmont 27:7110ebee3484 371 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
emilmont 27:7110ebee3484 372 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
emilmont 27:7110ebee3484 373
emilmont 31:a7ef757f598c 374 /* SCB System Handler Control and State Register Definitions */
emilmont 31:a7ef757f598c 375 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
emilmont 31:a7ef757f598c 376 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
emilmont 31:a7ef757f598c 377
emilmont 27:7110ebee3484 378 /*@} end of group CMSIS_SCB */
emilmont 27:7110ebee3484 379
emilmont 27:7110ebee3484 380
emilmont 31:a7ef757f598c 381 /** \ingroup CMSIS_core_register
emilmont 31:a7ef757f598c 382 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
emilmont 31:a7ef757f598c 383 \brief Type definitions for the System Timer Registers.
emilmont 27:7110ebee3484 384 @{
emilmont 27:7110ebee3484 385 */
emilmont 27:7110ebee3484 386
emilmont 27:7110ebee3484 387 /** \brief Structure type to access the System Timer (SysTick).
emilmont 27:7110ebee3484 388 */
emilmont 27:7110ebee3484 389 typedef struct
emilmont 27:7110ebee3484 390 {
emilmont 27:7110ebee3484 391 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
emilmont 27:7110ebee3484 392 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
emilmont 27:7110ebee3484 393 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
emilmont 27:7110ebee3484 394 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
emilmont 27:7110ebee3484 395 } SysTick_Type;
emilmont 27:7110ebee3484 396
emilmont 27:7110ebee3484 397 /* SysTick Control / Status Register Definitions */
emilmont 27:7110ebee3484 398 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
emilmont 27:7110ebee3484 399 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
emilmont 27:7110ebee3484 400
emilmont 27:7110ebee3484 401 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
emilmont 27:7110ebee3484 402 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
emilmont 27:7110ebee3484 403
emilmont 27:7110ebee3484 404 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
emilmont 27:7110ebee3484 405 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
emilmont 27:7110ebee3484 406
emilmont 27:7110ebee3484 407 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
emilmont 27:7110ebee3484 408 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
emilmont 27:7110ebee3484 409
emilmont 27:7110ebee3484 410 /* SysTick Reload Register Definitions */
emilmont 27:7110ebee3484 411 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
emilmont 27:7110ebee3484 412 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
emilmont 27:7110ebee3484 413
emilmont 27:7110ebee3484 414 /* SysTick Current Register Definitions */
emilmont 27:7110ebee3484 415 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
emilmont 27:7110ebee3484 416 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
emilmont 27:7110ebee3484 417
emilmont 27:7110ebee3484 418 /* SysTick Calibration Register Definitions */
emilmont 27:7110ebee3484 419 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
emilmont 27:7110ebee3484 420 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
emilmont 27:7110ebee3484 421
emilmont 27:7110ebee3484 422 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
emilmont 27:7110ebee3484 423 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
emilmont 27:7110ebee3484 424
emilmont 27:7110ebee3484 425 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
emilmont 27:7110ebee3484 426 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
emilmont 27:7110ebee3484 427
emilmont 27:7110ebee3484 428 /*@} end of group CMSIS_SysTick */
emilmont 27:7110ebee3484 429
emilmont 27:7110ebee3484 430
emilmont 31:a7ef757f598c 431 /** \ingroup CMSIS_core_register
emilmont 31:a7ef757f598c 432 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
emilmont 31:a7ef757f598c 433 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
emilmont 31:a7ef757f598c 434 are only accessible over DAP and not via processor. Therefore
emilmont 31:a7ef757f598c 435 they are not covered by the Cortex-M0 header file.
emilmont 31:a7ef757f598c 436 @{
emilmont 31:a7ef757f598c 437 */
emilmont 31:a7ef757f598c 438 /*@} end of group CMSIS_CoreDebug */
emilmont 31:a7ef757f598c 439
emilmont 31:a7ef757f598c 440
emilmont 31:a7ef757f598c 441 /** \ingroup CMSIS_core_register
emilmont 31:a7ef757f598c 442 \defgroup CMSIS_core_base Core Definitions
emilmont 31:a7ef757f598c 443 \brief Definitions for base addresses, unions, and structures.
emilmont 27:7110ebee3484 444 @{
emilmont 27:7110ebee3484 445 */
emilmont 27:7110ebee3484 446
emilmont 27:7110ebee3484 447 /* Memory mapping of Cortex-M0 Hardware */
emilmont 27:7110ebee3484 448 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
emilmont 27:7110ebee3484 449 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
emilmont 27:7110ebee3484 450 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
emilmont 27:7110ebee3484 451 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
emilmont 27:7110ebee3484 452
emilmont 31:a7ef757f598c 453 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
emilmont 31:a7ef757f598c 454 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
emilmont 31:a7ef757f598c 455 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
emilmont 31:a7ef757f598c 456
emilmont 27:7110ebee3484 457
emilmont 27:7110ebee3484 458 /*@} */
emilmont 27:7110ebee3484 459
emilmont 27:7110ebee3484 460
emilmont 27:7110ebee3484 461
emilmont 27:7110ebee3484 462 /*******************************************************************************
emilmont 27:7110ebee3484 463 * Hardware Abstraction Layer
emilmont 27:7110ebee3484 464 Core Function Interface contains:
emilmont 27:7110ebee3484 465 - Core NVIC Functions
emilmont 27:7110ebee3484 466 - Core SysTick Functions
emilmont 27:7110ebee3484 467 - Core Register Access Functions
emilmont 31:a7ef757f598c 468 ******************************************************************************/
emilmont 31:a7ef757f598c 469 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
emilmont 27:7110ebee3484 470 */
emilmont 27:7110ebee3484 471
emilmont 27:7110ebee3484 472
emilmont 27:7110ebee3484 473
emilmont 27:7110ebee3484 474 /* ########################## NVIC functions #################################### */
emilmont 31:a7ef757f598c 475 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 31:a7ef757f598c 476 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
emilmont 31:a7ef757f598c 477 \brief Functions that manage interrupts and exceptions via the NVIC.
emilmont 31:a7ef757f598c 478 @{
emilmont 27:7110ebee3484 479 */
emilmont 27:7110ebee3484 480
emilmont 27:7110ebee3484 481 /* Interrupt Priorities are WORD accessible only under ARMv6M */
emilmont 27:7110ebee3484 482 /* The following MACROS handle generation of the register offset and byte masks */
emilmont 27:7110ebee3484 483 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
emilmont 27:7110ebee3484 484 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
emilmont 27:7110ebee3484 485 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
emilmont 27:7110ebee3484 486
emilmont 27:7110ebee3484 487
emilmont 27:7110ebee3484 488 /** \brief Enable External Interrupt
emilmont 27:7110ebee3484 489
emilmont 31:a7ef757f598c 490 The function enables a device-specific interrupt in the NVIC interrupt controller.
emilmont 27:7110ebee3484 491
emilmont 31:a7ef757f598c 492 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 27:7110ebee3484 493 */
emilmont 27:7110ebee3484 494 static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
emilmont 27:7110ebee3484 495 {
emilmont 27:7110ebee3484 496 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
emilmont 27:7110ebee3484 497 }
emilmont 27:7110ebee3484 498
emilmont 27:7110ebee3484 499
emilmont 27:7110ebee3484 500 /** \brief Disable External Interrupt
emilmont 27:7110ebee3484 501
emilmont 31:a7ef757f598c 502 The function disables a device-specific interrupt in the NVIC interrupt controller.
emilmont 27:7110ebee3484 503
emilmont 31:a7ef757f598c 504 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 27:7110ebee3484 505 */
emilmont 27:7110ebee3484 506 static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
emilmont 27:7110ebee3484 507 {
emilmont 27:7110ebee3484 508 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
emilmont 27:7110ebee3484 509 }
emilmont 27:7110ebee3484 510
emilmont 27:7110ebee3484 511
emilmont 27:7110ebee3484 512 /** \brief Get Pending Interrupt
emilmont 27:7110ebee3484 513
emilmont 31:a7ef757f598c 514 The function reads the pending register in the NVIC and returns the pending bit
emilmont 31:a7ef757f598c 515 for the specified interrupt.
emilmont 27:7110ebee3484 516
emilmont 31:a7ef757f598c 517 \param [in] IRQn Interrupt number.
emilmont 31:a7ef757f598c 518
emilmont 31:a7ef757f598c 519 \return 0 Interrupt status is not pending.
emilmont 31:a7ef757f598c 520 \return 1 Interrupt status is pending.
emilmont 27:7110ebee3484 521 */
emilmont 27:7110ebee3484 522 static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
emilmont 27:7110ebee3484 523 {
emilmont 27:7110ebee3484 524 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
emilmont 27:7110ebee3484 525 }
emilmont 27:7110ebee3484 526
emilmont 27:7110ebee3484 527
emilmont 27:7110ebee3484 528 /** \brief Set Pending Interrupt
emilmont 27:7110ebee3484 529
emilmont 31:a7ef757f598c 530 The function sets the pending bit of an external interrupt.
emilmont 27:7110ebee3484 531
emilmont 31:a7ef757f598c 532 \param [in] IRQn Interrupt number. Value cannot be negative.
emilmont 27:7110ebee3484 533 */
emilmont 27:7110ebee3484 534 static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
emilmont 27:7110ebee3484 535 {
emilmont 27:7110ebee3484 536 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
emilmont 27:7110ebee3484 537 }
emilmont 27:7110ebee3484 538
emilmont 27:7110ebee3484 539
emilmont 27:7110ebee3484 540 /** \brief Clear Pending Interrupt
emilmont 27:7110ebee3484 541
emilmont 31:a7ef757f598c 542 The function clears the pending bit of an external interrupt.
emilmont 27:7110ebee3484 543
emilmont 31:a7ef757f598c 544 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 27:7110ebee3484 545 */
emilmont 27:7110ebee3484 546 static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
emilmont 27:7110ebee3484 547 {
emilmont 27:7110ebee3484 548 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
emilmont 27:7110ebee3484 549 }
emilmont 27:7110ebee3484 550
emilmont 27:7110ebee3484 551
emilmont 27:7110ebee3484 552 /** \brief Set Interrupt Priority
emilmont 27:7110ebee3484 553
emilmont 31:a7ef757f598c 554 The function sets the priority of an interrupt.
emilmont 27:7110ebee3484 555
emilmont 31:a7ef757f598c 556 \note The priority cannot be set for every core interrupt.
emilmont 27:7110ebee3484 557
emilmont 31:a7ef757f598c 558 \param [in] IRQn Interrupt number.
emilmont 31:a7ef757f598c 559 \param [in] priority Priority to set.
emilmont 27:7110ebee3484 560 */
emilmont 27:7110ebee3484 561 static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
emilmont 27:7110ebee3484 562 {
emilmont 27:7110ebee3484 563 if(IRQn < 0) {
emilmont 31:a7ef757f598c 564 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
emilmont 27:7110ebee3484 565 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
emilmont 27:7110ebee3484 566 else {
emilmont 31:a7ef757f598c 567 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
emilmont 27:7110ebee3484 568 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
emilmont 27:7110ebee3484 569 }
emilmont 27:7110ebee3484 570
emilmont 27:7110ebee3484 571
emilmont 27:7110ebee3484 572 /** \brief Get Interrupt Priority
emilmont 27:7110ebee3484 573
emilmont 31:a7ef757f598c 574 The function reads the priority of an interrupt. The interrupt
emilmont 31:a7ef757f598c 575 number can be positive to specify an external (device specific)
emilmont 27:7110ebee3484 576 interrupt, or negative to specify an internal (core) interrupt.
emilmont 27:7110ebee3484 577
emilmont 27:7110ebee3484 578
emilmont 31:a7ef757f598c 579 \param [in] IRQn Interrupt number.
emilmont 31:a7ef757f598c 580 \return Interrupt Priority. Value is aligned automatically to the implemented
emilmont 31:a7ef757f598c 581 priority bits of the microcontroller.
emilmont 27:7110ebee3484 582 */
emilmont 27:7110ebee3484 583 static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
emilmont 27:7110ebee3484 584 {
emilmont 27:7110ebee3484 585
emilmont 27:7110ebee3484 586 if(IRQn < 0) {
emilmont 27:7110ebee3484 587 return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
emilmont 27:7110ebee3484 588 else {
emilmont 31:a7ef757f598c 589 return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
emilmont 27:7110ebee3484 590 }
emilmont 27:7110ebee3484 591
emilmont 27:7110ebee3484 592
emilmont 27:7110ebee3484 593 /** \brief System Reset
emilmont 27:7110ebee3484 594
emilmont 31:a7ef757f598c 595 The function initiates a system reset request to reset the MCU.
emilmont 27:7110ebee3484 596 */
emilmont 27:7110ebee3484 597 static __INLINE void NVIC_SystemReset(void)
emilmont 27:7110ebee3484 598 {
emilmont 27:7110ebee3484 599 __DSB(); /* Ensure all outstanding memory accesses included
emilmont 31:a7ef757f598c 600 buffered write are completed before reset */
emilmont 31:a7ef757f598c 601 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
emilmont 27:7110ebee3484 602 SCB_AIRCR_SYSRESETREQ_Msk);
emilmont 31:a7ef757f598c 603 __DSB(); /* Ensure completion of memory access */
emilmont 27:7110ebee3484 604 while(1); /* wait until reset */
emilmont 27:7110ebee3484 605 }
emilmont 27:7110ebee3484 606
emilmont 27:7110ebee3484 607 /*@} end of CMSIS_Core_NVICFunctions */
emilmont 27:7110ebee3484 608
emilmont 27:7110ebee3484 609
emilmont 27:7110ebee3484 610
emilmont 27:7110ebee3484 611 /* ################################## SysTick function ############################################ */
emilmont 31:a7ef757f598c 612 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 31:a7ef757f598c 613 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
emilmont 31:a7ef757f598c 614 \brief Functions that configure the System.
emilmont 27:7110ebee3484 615 @{
emilmont 27:7110ebee3484 616 */
emilmont 27:7110ebee3484 617
emilmont 27:7110ebee3484 618 #if (__Vendor_SysTickConfig == 0)
emilmont 27:7110ebee3484 619
emilmont 27:7110ebee3484 620 /** \brief System Tick Configuration
emilmont 27:7110ebee3484 621
emilmont 31:a7ef757f598c 622 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
emilmont 31:a7ef757f598c 623 Counter is in free running mode to generate periodic interrupts.
emilmont 27:7110ebee3484 624
emilmont 31:a7ef757f598c 625 \param [in] ticks Number of ticks between two interrupts.
emilmont 31:a7ef757f598c 626
emilmont 31:a7ef757f598c 627 \return 0 Function succeeded.
emilmont 31:a7ef757f598c 628 \return 1 Function failed.
emilmont 31:a7ef757f598c 629
emilmont 31:a7ef757f598c 630 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
emilmont 31:a7ef757f598c 631 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
emilmont 31:a7ef757f598c 632 must contain a vendor-specific implementation of this function.
emilmont 31:a7ef757f598c 633
emilmont 27:7110ebee3484 634 */
emilmont 27:7110ebee3484 635 static __INLINE uint32_t SysTick_Config(uint32_t ticks)
emilmont 31:a7ef757f598c 636 {
emilmont 27:7110ebee3484 637 if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
emilmont 31:a7ef757f598c 638
emilmont 27:7110ebee3484 639 SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
emilmont 31:a7ef757f598c 640 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
emilmont 27:7110ebee3484 641 SysTick->VAL = 0; /* Load the SysTick Counter Value */
emilmont 31:a7ef757f598c 642 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
emilmont 31:a7ef757f598c 643 SysTick_CTRL_TICKINT_Msk |
emilmont 27:7110ebee3484 644 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
emilmont 27:7110ebee3484 645 return (0); /* Function successful */
emilmont 27:7110ebee3484 646 }
emilmont 27:7110ebee3484 647
emilmont 27:7110ebee3484 648 #endif
emilmont 27:7110ebee3484 649
emilmont 27:7110ebee3484 650 /*@} end of CMSIS_Core_SysTickFunctions */
emilmont 27:7110ebee3484 651
emilmont 27:7110ebee3484 652
emilmont 27:7110ebee3484 653
emilmont 27:7110ebee3484 654
emilmont 27:7110ebee3484 655 #endif /* __CORE_CM0_H_DEPENDANT */
emilmont 27:7110ebee3484 656
emilmont 27:7110ebee3484 657 #endif /* __CMSIS_GENERIC */
emilmont 27:7110ebee3484 658
emilmont 27:7110ebee3484 659 #ifdef __cplusplus
emilmont 27:7110ebee3484 660 }
emilmont 27:7110ebee3484 661 #endif