Revision 562:f0e4febb6ec5, committed 2015-06-09

Comitter:

jpiat

Date:

Tue Jun 09 12:33:35 2015 +0000

Parent:

561:f26bb522183d

Commit message:

Changed system clock to internal with PLL to 120MHz

Changed in this revision

--- a/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.h	Mon Jun 08 16:15:09 2015 +0100
+++ b/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.h	Tue Jun 09 12:33:35 2015 +0000
@@ -96,7 +96,7 @@
 #define DISABLE_WDOG                   1
 
 #ifndef CLOCK_SETUP
-  #define CLOCK_SETUP                  4
+  #define CLOCK_SETUP                  0
 #endif
 
 /* MCG mode constants */
@@ -166,32 +166,32 @@
 /* #undef FAST_FINE_TRIM_ADDRESS */                        /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
 
 #if (CLOCK_SETUP == 0)
-  #define DEFAULT_SYSTEM_CLOCK         20971520u           /* Default System clock value */
-  #define MCG_MODE                     MCG_MODE_FEI /* Clock generator mode */
-  /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
-  #define SYSTEM_MCG_C1_VALUE          0x06U               /* MCG_C1 */
+ #define DEFAULT_SYSTEM_CLOCK         120000000U          /* Default System clock value */
+  #define MCG_MODE                     MCG_MODE_PEE /* Clock generator mode */
+  /* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+  #define SYSTEM_MCG_C1_VALUE          0x22U               /* MCG_C1 */
   /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
   #define SYSTEM_MCG_C2_VALUE          0x24U               /* MCG_C2 */
   /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
   #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
   /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
   #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
-/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
-  #define SYSTEM_MCG_C5_VALUE          0x00U               /* MCG_C5 */
-/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
-  #define SYSTEM_MCG_C6_VALUE          0x00U               /* MCG_C6 */
-/* MCG_C7: OSCSEL=0 */
+  /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=3 */
+  #define SYSTEM_MCG_C5_VALUE          0x03U               /* MCG_C5 */
+  /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=6 */
+  #define SYSTEM_MCG_C6_VALUE          0x46U               /* MCG_C6 */
+  /* MCG_C7: OSCSEL=0 */
   #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
-/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
-  #define SYSTEM_OSC_CR_VALUE          0x00U               /* OSC_CR */
-/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
-  #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
-/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1 */
-  #define SYSTEM_SIM_CLKDIV1_VALUE     0x00110000U         /* SIM_CLKDIV1 */
-/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
-  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
-/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
-  #define SYSTEM_SIM_SOPT2_VALUE       0x00U               /* SIM_SOPT2 */
+  /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define SYSTEM_OSC_CR_VALUE          0x80U               /* OSC_CR */
+  /* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
+  #define SYSTEM_SMC_PMCTRL_VALUE      0x60U               /* SMC_PMCTRL */
+  /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x01140000U         /* SIM_CLKDIV1 */
+  /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3,OSC32KOUT=0,RAMSIZE=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x000C0000U         /* SIM_SOPT1 */
+  /* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x00010000U         /* SIM_SOPT2 */
 #elif (CLOCK_SETUP == 1)
   #define DEFAULT_SYSTEM_CLOCK         120000000u          /* Default System clock value */
   #define MCG_MODE                     MCG_MODE_PEE /* Clock generator mode */