Jonathan Piat / mbed-src

mbed library sources

Fork of mbed-src by mbed official

targets/hal/TARGET_NXP/TARGET_LPC11UXX/spi_api.c@552:a1b9575155a3, 2015-05-27 (annotated)

Committer:
mbed_official
Date:
Wed May 27 13:30:08 2015 +0100
Revision:
552:a1b9575155a3
Parent:
285:31249416b6f9 
Synchronized with git revision a74a8f14fd8c4bf3dc09980c4bf9498ebcf4c207



Full URL: https://github.com/mbedmicro/mbed/commit/a74a8f14fd8c4bf3dc09980c4bf9498ebcf4c207/

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /* mbed Microcontroller Library
emilmont 10:3bc89ef62ce7 2 * Copyright (c) 2006-2013 ARM Limited
emilmont 10:3bc89ef62ce7 3 *
emilmont 10:3bc89ef62ce7 4 * Licensed under the Apache License, Version 2.0 (the "License");
emilmont 10:3bc89ef62ce7 5 * you may not use this file except in compliance with the License.
emilmont 10:3bc89ef62ce7 6 * You may obtain a copy of the License at
emilmont 10:3bc89ef62ce7 7 *
emilmont 10:3bc89ef62ce7 8 * http://www.apache.org/licenses/LICENSE-2.0
emilmont 10:3bc89ef62ce7 9 *
emilmont 10:3bc89ef62ce7 10 * Unless required by applicable law or agreed to in writing, software
emilmont 10:3bc89ef62ce7 11 * distributed under the License is distributed on an "AS IS" BASIS,
emilmont 10:3bc89ef62ce7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
emilmont 10:3bc89ef62ce7 13 * See the License for the specific language governing permissions and
emilmont 10:3bc89ef62ce7 14 * limitations under the License.
emilmont 10:3bc89ef62ce7 15 */
mbed_official 227:7bd0639b8911 16 #include "mbed_assert.h"
emilmont 10:3bc89ef62ce7 17 #include <math.h>
emilmont 10:3bc89ef62ce7 18 #include "spi_api.h"
emilmont 10:3bc89ef62ce7 19 #include "cmsis.h"
emilmont 10:3bc89ef62ce7 20 #include "pinmap.h"
mbed_official 285:31249416b6f9 21 #include "mbed_error.h"
mbed_official 274:6937b19af361 22 #include "PeripheralPins.h" // For the Peripheral to Pin Definitions found in the individual Target's Platform
emilmont 10:3bc89ef62ce7 23
emilmont 10:3bc89ef62ce7 24 static inline int ssp_disable(spi_t *obj);
emilmont 10:3bc89ef62ce7 25 static inline int ssp_enable(spi_t *obj);
emilmont 10:3bc89ef62ce7 26
emilmont 10:3bc89ef62ce7 27 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
emilmont 10:3bc89ef62ce7 28 // determine the SPI to use
emilmont 10:3bc89ef62ce7 29 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
emilmont 10:3bc89ef62ce7 30 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
emilmont 10:3bc89ef62ce7 31 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
emilmont 10:3bc89ef62ce7 32 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
emilmont 10:3bc89ef62ce7 33 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
emilmont 10:3bc89ef62ce7 34 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
emilmont 10:3bc89ef62ce7 35
emilmont 10:3bc89ef62ce7 36 obj->spi = (LPC_SSPx_Type*)pinmap_merge(spi_data, spi_cntl);
mbed_official 227:7bd0639b8911 37 MBED_ASSERT((int)obj->spi != NC);
emilmont 10:3bc89ef62ce7 38
emilmont 10:3bc89ef62ce7 39 // enable power and clocking
emilmont 10:3bc89ef62ce7 40 switch ((int)obj->spi) {
emilmont 10:3bc89ef62ce7 41 case SPI_0:
emilmont 10:3bc89ef62ce7 42 LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 11;
emilmont 10:3bc89ef62ce7 43 LPC_SYSCON->SSP0CLKDIV = 0x01;
emilmont 10:3bc89ef62ce7 44 LPC_SYSCON->PRESETCTRL |= 1 << 0;
emilmont 10:3bc89ef62ce7 45 break;
emilmont 10:3bc89ef62ce7 46 case SPI_1:
emilmont 10:3bc89ef62ce7 47 LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 18;
emilmont 10:3bc89ef62ce7 48 LPC_SYSCON->SSP1CLKDIV = 0x01;
emilmont 10:3bc89ef62ce7 49 LPC_SYSCON->PRESETCTRL |= 1 << 2;
emilmont 10:3bc89ef62ce7 50 break;
emilmont 10:3bc89ef62ce7 51 }
emilmont 10:3bc89ef62ce7 52
emilmont 10:3bc89ef62ce7 53 // pin out the spi pins
emilmont 10:3bc89ef62ce7 54 pinmap_pinout(mosi, PinMap_SPI_MOSI);
emilmont 10:3bc89ef62ce7 55 pinmap_pinout(miso, PinMap_SPI_MISO);
emilmont 10:3bc89ef62ce7 56 pinmap_pinout(sclk, PinMap_SPI_SCLK);
emilmont 10:3bc89ef62ce7 57 if (ssel != NC) {
emilmont 10:3bc89ef62ce7 58 pinmap_pinout(ssel, PinMap_SPI_SSEL);
emilmont 10:3bc89ef62ce7 59 }
emilmont 10:3bc89ef62ce7 60 }
emilmont 10:3bc89ef62ce7 61
emilmont 10:3bc89ef62ce7 62 void spi_free(spi_t *obj) {}
emilmont 10:3bc89ef62ce7 63
emilmont 10:3bc89ef62ce7 64 void spi_format(spi_t *obj, int bits, int mode, int slave) {
mbed_official 227:7bd0639b8911 65 MBED_ASSERT((bits >= 4 && bits <= 16) || (mode >= 0 && mode <= 3));
mbed_official 227:7bd0639b8911 66
emilmont 10:3bc89ef62ce7 67 ssp_disable(obj);
emilmont 10:3bc89ef62ce7 68
emilmont 10:3bc89ef62ce7 69 int polarity = (mode & 0x2) ? 1 : 0;
emilmont 10:3bc89ef62ce7 70 int phase = (mode & 0x1) ? 1 : 0;
emilmont 10:3bc89ef62ce7 71
emilmont 10:3bc89ef62ce7 72 // set it up
emilmont 10:3bc89ef62ce7 73 int DSS = bits - 1; // DSS (data select size)
emilmont 10:3bc89ef62ce7 74 int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
emilmont 10:3bc89ef62ce7 75 int SPH = (phase) ? 1 : 0; // SPH - clock out phase
emilmont 10:3bc89ef62ce7 76
emilmont 10:3bc89ef62ce7 77 int FRF = 0; // FRF (frame format) = SPI
emilmont 10:3bc89ef62ce7 78 uint32_t tmp = obj->spi->CR0;
emilmont 10:3bc89ef62ce7 79 tmp &= ~(0xFFFF);
emilmont 10:3bc89ef62ce7 80 tmp |= DSS << 0
emilmont 10:3bc89ef62ce7 81 | FRF << 4
emilmont 10:3bc89ef62ce7 82 | SPO << 6
emilmont 10:3bc89ef62ce7 83 | SPH << 7;
emilmont 10:3bc89ef62ce7 84 obj->spi->CR0 = tmp;
emilmont 10:3bc89ef62ce7 85
emilmont 10:3bc89ef62ce7 86 tmp = obj->spi->CR1;
emilmont 10:3bc89ef62ce7 87 tmp &= ~(0xD);
emilmont 10:3bc89ef62ce7 88 tmp |= 0 << 0 // LBM - loop back mode - off
emilmont 10:3bc89ef62ce7 89 | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave
emilmont 10:3bc89ef62ce7 90 | 0 << 3; // SOD - slave output disable - na
emilmont 10:3bc89ef62ce7 91 obj->spi->CR1 = tmp;
emilmont 10:3bc89ef62ce7 92
emilmont 10:3bc89ef62ce7 93 ssp_enable(obj);
emilmont 10:3bc89ef62ce7 94 }
emilmont 10:3bc89ef62ce7 95
emilmont 10:3bc89ef62ce7 96 void spi_frequency(spi_t *obj, int hz) {
emilmont 10:3bc89ef62ce7 97 ssp_disable(obj);
emilmont 10:3bc89ef62ce7 98
emilmont 10:3bc89ef62ce7 99 uint32_t PCLK = SystemCoreClock;
emilmont 10:3bc89ef62ce7 100
emilmont 10:3bc89ef62ce7 101 int prescaler;
emilmont 10:3bc89ef62ce7 102
emilmont 10:3bc89ef62ce7 103 for (prescaler = 2; prescaler <= 254; prescaler += 2) {
emilmont 10:3bc89ef62ce7 104 int prescale_hz = PCLK / prescaler;
emilmont 10:3bc89ef62ce7 105
emilmont 10:3bc89ef62ce7 106 // calculate the divider
emilmont 10:3bc89ef62ce7 107 int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
emilmont 10:3bc89ef62ce7 108
emilmont 10:3bc89ef62ce7 109 // check we can support the divider
emilmont 10:3bc89ef62ce7 110 if (divider < 256) {
emilmont 10:3bc89ef62ce7 111 // prescaler
emilmont 10:3bc89ef62ce7 112 obj->spi->CPSR = prescaler;
emilmont 10:3bc89ef62ce7 113
emilmont 10:3bc89ef62ce7 114 // divider
emilmont 10:3bc89ef62ce7 115 obj->spi->CR0 &= ~(0xFFFF << 8);
emilmont 10:3bc89ef62ce7 116 obj->spi->CR0 |= (divider - 1) << 8;
emilmont 10:3bc89ef62ce7 117 ssp_enable(obj);
emilmont 10:3bc89ef62ce7 118 return;
emilmont 10:3bc89ef62ce7 119 }
emilmont 10:3bc89ef62ce7 120 }
emilmont 10:3bc89ef62ce7 121 error("Couldn't setup requested SPI frequency");
emilmont 10:3bc89ef62ce7 122 }
emilmont 10:3bc89ef62ce7 123
emilmont 10:3bc89ef62ce7 124 static inline int ssp_disable(spi_t *obj) {
emilmont 10:3bc89ef62ce7 125 return obj->spi->CR1 &= ~(1 << 1);
emilmont 10:3bc89ef62ce7 126 }
emilmont 10:3bc89ef62ce7 127
emilmont 10:3bc89ef62ce7 128 static inline int ssp_enable(spi_t *obj) {
emilmont 10:3bc89ef62ce7 129 return obj->spi->CR1 |= (1 << 1);
emilmont 10:3bc89ef62ce7 130 }
emilmont 10:3bc89ef62ce7 131
emilmont 10:3bc89ef62ce7 132 static inline int ssp_readable(spi_t *obj) {
emilmont 10:3bc89ef62ce7 133 return obj->spi->SR & (1 << 2);
emilmont 10:3bc89ef62ce7 134 }
emilmont 10:3bc89ef62ce7 135
emilmont 10:3bc89ef62ce7 136 static inline int ssp_writeable(spi_t *obj) {
emilmont 10:3bc89ef62ce7 137 return obj->spi->SR & (1 << 1);
emilmont 10:3bc89ef62ce7 138 }
emilmont 10:3bc89ef62ce7 139
emilmont 10:3bc89ef62ce7 140 static inline void ssp_write(spi_t *obj, int value) {
emilmont 10:3bc89ef62ce7 141 while (!ssp_writeable(obj));
emilmont 10:3bc89ef62ce7 142 obj->spi->DR = value;
emilmont 10:3bc89ef62ce7 143 }
emilmont 10:3bc89ef62ce7 144
emilmont 10:3bc89ef62ce7 145 static inline int ssp_read(spi_t *obj) {
emilmont 10:3bc89ef62ce7 146 while (!ssp_readable(obj));
emilmont 10:3bc89ef62ce7 147 return obj->spi->DR;
emilmont 10:3bc89ef62ce7 148 }
emilmont 10:3bc89ef62ce7 149
emilmont 10:3bc89ef62ce7 150 static inline int ssp_busy(spi_t *obj) {
emilmont 10:3bc89ef62ce7 151 return (obj->spi->SR & (1 << 4)) ? (1) : (0);
emilmont 10:3bc89ef62ce7 152 }
emilmont 10:3bc89ef62ce7 153
emilmont 10:3bc89ef62ce7 154 int spi_master_write(spi_t *obj, int value) {
emilmont 10:3bc89ef62ce7 155 ssp_write(obj, value);
emilmont 10:3bc89ef62ce7 156 return ssp_read(obj);
emilmont 10:3bc89ef62ce7 157 }
emilmont 10:3bc89ef62ce7 158
emilmont 10:3bc89ef62ce7 159 int spi_slave_receive(spi_t *obj) {
emilmont 10:3bc89ef62ce7 160 return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
mbed_official 81:a9456fdf72fa 161 }
emilmont 10:3bc89ef62ce7 162
emilmont 10:3bc89ef62ce7 163 int spi_slave_read(spi_t *obj) {
emilmont 10:3bc89ef62ce7 164 return obj->spi->DR;
emilmont 10:3bc89ef62ce7 165 }
emilmont 10:3bc89ef62ce7 166
emilmont 10:3bc89ef62ce7 167 void spi_slave_write(spi_t *obj, int value) {
emilmont 10:3bc89ef62ce7 168 while (ssp_writeable(obj) == 0) ;
emilmont 10:3bc89ef62ce7 169 obj->spi->DR = value;
emilmont 10:3bc89ef62ce7 170 }
emilmont 10:3bc89ef62ce7 171
emilmont 10:3bc89ef62ce7 172 int spi_busy(spi_t *obj) {
emilmont 10:3bc89ef62ce7 173 return ssp_busy(obj);
emilmont 10:3bc89ef62ce7 174 }