Committer:
jp
Date:
Sun Feb 13 02:18:50 2011 +0000
Revision:
3:d0fc1ce5e516
Parent:
2:98b11b7dd7b2

        

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jp 0:cf255d2aa92f 1 /*
jp 2:98b11b7dd7b2 2 * Copyright or � or Copr. 2010, Thomas SOETE
jp 0:cf255d2aa92f 3 *
jp 0:cf255d2aa92f 4 * Author e-mail: thomas@soete.org
jp 0:cf255d2aa92f 5 * Library website : http://mbed.org/users/Alkorin/libraries/SimpleLib/
jp 0:cf255d2aa92f 6 *
jp 0:cf255d2aa92f 7 * This software is governed by the CeCILL license under French law and
jp 0:cf255d2aa92f 8 * abiding by the rules of distribution of free software. You can use,
jp 0:cf255d2aa92f 9 * modify and/ or redistribute the software under the terms of the CeCILL
jp 0:cf255d2aa92f 10 * license as circulated by CEA, CNRS and INRIA at the following URL
jp 0:cf255d2aa92f 11 * "http://www.cecill.info".
jp 0:cf255d2aa92f 12 *
jp 0:cf255d2aa92f 13 * As a counterpart to the access to the source code and rights to copy,
jp 0:cf255d2aa92f 14 * modify and redistribute granted by the license, users are provided only
jp 0:cf255d2aa92f 15 * with a limited warranty and the software's author, the holder of the
jp 0:cf255d2aa92f 16 * economic rights, and the successive licensors have only limited
jp 0:cf255d2aa92f 17 * liability.
jp 0:cf255d2aa92f 18 *
jp 0:cf255d2aa92f 19 * In this respect, the user's attention is drawn to the risks associated
jp 0:cf255d2aa92f 20 * with loading, using, modifying and/or developing or reproducing the
jp 0:cf255d2aa92f 21 * software by the user in light of its specific status of free software,
jp 0:cf255d2aa92f 22 * that may mean that it is complicated to manipulate, and that also
jp 0:cf255d2aa92f 23 * therefore means that it is reserved for developers and experienced
jp 0:cf255d2aa92f 24 * professionals having in-depth computer knowledge. Users are therefore
jp 0:cf255d2aa92f 25 * encouraged to load and test the software's suitability as regards their
jp 0:cf255d2aa92f 26 * requirements in conditions enabling the security of their systems and/or
jp 0:cf255d2aa92f 27 * data to be ensured and, more generally, to use and operate it in the
jp 0:cf255d2aa92f 28 * same conditions as regards security.
jp 0:cf255d2aa92f 29 *
jp 0:cf255d2aa92f 30 * The fact that you are presently reading this means that you have had
jp 0:cf255d2aa92f 31 * knowledge of the CeCILL license and that you accept its terms.
jp 0:cf255d2aa92f 32 */
jp 0:cf255d2aa92f 33
jp 0:cf255d2aa92f 34 #ifndef __SIMPLELIB_MBED_GLOBALS_H__
jp 0:cf255d2aa92f 35 #define __SIMPLELIB_MBED_GLOBALS_H__
jp 0:cf255d2aa92f 36
jp 0:cf255d2aa92f 37 #include <LPC17xx.h>
jp 0:cf255d2aa92f 38
jp 0:cf255d2aa92f 39 /* GLOBALS MACRO */
jp 0:cf255d2aa92f 40 #define GET_REGISTER8(reg) *(volatile uint8_t *)(reg)
jp 0:cf255d2aa92f 41 #define GET_REGISTER16(reg) *(volatile uint16_t *)(reg)
jp 0:cf255d2aa92f 42 #define GET_REGISTER32(reg) *(volatile uint32_t *)(reg)
jp 0:cf255d2aa92f 43
jp 0:cf255d2aa92f 44 #define SET_REGISTER8(reg, val) *(uint8_t *)(reg)=(val)
jp 0:cf255d2aa92f 45 #define SET_REGISTER16(reg, val) *(uint16_t *)(reg)=(val)
jp 0:cf255d2aa92f 46 #define SET_REGISTER32(reg, val) *(uint32_t *)(reg)=(val)
jp 0:cf255d2aa92f 47
jp 0:cf255d2aa92f 48 // See 34.3.2.5 p740
jp 0:cf255d2aa92f 49 #define BIT_BANDING_ADDRESS(reg, bit) (((reg) & 0xF0000000) | (0x02000000) | (((reg) & 0x000FFFFF) << 5) | ((bit) << 2))
jp 0:cf255d2aa92f 50 #define GET_BIT_ADDRESS(reg, bit) BIT_BANDING_ADDRESS(((uint32_t)&(reg)), (bit))
jp 0:cf255d2aa92f 51 #define GET_BIT_VALUE(reg, bit) GET_REGISTER32(GET_BIT_ADDRESS((reg), (bit)))
jp 0:cf255d2aa92f 52 #define SET_BIT_VALUE(reg, bit, value) SET_REGISTER32(GET_BIT_ADDRESS((reg), (bit)), (value))
jp 0:cf255d2aa92f 53
jp 0:cf255d2aa92f 54 // Macro tools
jp 0:cf255d2aa92f 55 #define TOKENPASTE(x, y) x ## y
jp 0:cf255d2aa92f 56 #define TOKENPASTE2(x, y) TOKENPASTE(x, y)
jp 0:cf255d2aa92f 57
jp 0:cf255d2aa92f 58 // Extern C
jp 0:cf255d2aa92f 59 #ifdef __cplusplus
jp 0:cf255d2aa92f 60 #define EXTERN_C extern "C"
jp 0:cf255d2aa92f 61 #else
jp 0:cf255d2aa92f 62 #define EXTERN_C
jp 0:cf255d2aa92f 63 #endif
jp 0:cf255d2aa92f 64
jp 0:cf255d2aa92f 65 // Byte swap macros
jp 0:cf255d2aa92f 66 #define HTONS(x) (((((unsigned short)(x))>>8) & 0xff) | ((((unsigned short)(x)) & 0xff)<<8))
jp 0:cf255d2aa92f 67 #define NTOHS(x) (((((unsigned short)(x))>>8) & 0xff) | ((((unsigned short)(x)) & 0xff)<<8))
jp 0:cf255d2aa92f 68 #define HTONL(x) ((((x)>>24) & 0xffL) | (((x)>>8) & 0xff00L) | (((x)<<8) & 0xff0000L) | (((x)<<24) & 0xff000000L))
jp 0:cf255d2aa92f 69 #define NTOHL(x) ((((x)>>24) & 0xffL) | (((x)>>8) & 0xff00L) | (((x)<<8) & 0xff0000L) | (((x)<<24) & 0xff000000L))
jp 0:cf255d2aa92f 70
jp 0:cf255d2aa92f 71
jp 0:cf255d2aa92f 72 /** Constants **/
jp 0:cf255d2aa92f 73 // Peripheral Clock Selection register bit values (Table 42, p57)
jp 0:cf255d2aa92f 74 #define CCLK4 0U
jp 0:cf255d2aa92f 75 #define CCLK 1U
jp 0:cf255d2aa92f 76 #define CCLK2 2U
jp 0:cf255d2aa92f 77 #define CCLK8 3U
jp 0:cf255d2aa92f 78
jp 0:cf255d2aa92f 79 #endif