João Sousa
Maniacbug's nRF24L01 arduino library ported to mbed. Functional with minor issues.
Fork of
nRF24L01P_Maniacbug
by 
Christiaan M
rf24_config.h@7:5ddd7a2fcb70, 2014-10-25 (annotated)
- Committer:
- jotaemesousa
- Date:
- Sat Oct 25 17:09:50 2014 +0000
- Revision:
- 7:5ddd7a2fcb70
FIX: redefenition of #define STATUS 0x07 (using a mkl05); ADD: configuration where the macros are defined (file included only in nRF24L01P_Maniacbug)
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| jotaemesousa | 7:5ddd7a2fcb70 | 1 | /* Memory Map */ |
| jotaemesousa | 7:5ddd7a2fcb70 | 2 | #define CONFIG 0x00 |
| jotaemesousa | 7:5ddd7a2fcb70 | 3 | #define EN_AA 0x01 |
| jotaemesousa | 7:5ddd7a2fcb70 | 4 | #define EN_RXADDR 0x02 |
| jotaemesousa | 7:5ddd7a2fcb70 | 5 | #define SETUP_AW 0x03 |
| jotaemesousa | 7:5ddd7a2fcb70 | 6 | #define SETUP_RETR 0x04 |
| jotaemesousa | 7:5ddd7a2fcb70 | 7 | #define RF_CH 0x05 |
| jotaemesousa | 7:5ddd7a2fcb70 | 8 | #define RF_SETUP 0x06 |
| jotaemesousa | 7:5ddd7a2fcb70 | 9 | #define STATUS 0x07 |
| jotaemesousa | 7:5ddd7a2fcb70 | 10 | #define OBSERVE_TX 0x08 |
| jotaemesousa | 7:5ddd7a2fcb70 | 11 | #define CD 0x09 |
| jotaemesousa | 7:5ddd7a2fcb70 | 12 | #define RX_ADDR_P0 0x0A |
| jotaemesousa | 7:5ddd7a2fcb70 | 13 | #define RX_ADDR_P1 0x0B |
| jotaemesousa | 7:5ddd7a2fcb70 | 14 | #define RX_ADDR_P2 0x0C |
| jotaemesousa | 7:5ddd7a2fcb70 | 15 | #define RX_ADDR_P3 0x0D |
| jotaemesousa | 7:5ddd7a2fcb70 | 16 | #define RX_ADDR_P4 0x0E |
| jotaemesousa | 7:5ddd7a2fcb70 | 17 | #define RX_ADDR_P5 0x0F |
| jotaemesousa | 7:5ddd7a2fcb70 | 18 | #define TX_ADDR 0x10 |
| jotaemesousa | 7:5ddd7a2fcb70 | 19 | #define RX_PW_P0 0x11 |
| jotaemesousa | 7:5ddd7a2fcb70 | 20 | #define RX_PW_P1 0x12 |
| jotaemesousa | 7:5ddd7a2fcb70 | 21 | #define RX_PW_P2 0x13 |
| jotaemesousa | 7:5ddd7a2fcb70 | 22 | #define RX_PW_P3 0x14 |
| jotaemesousa | 7:5ddd7a2fcb70 | 23 | #define RX_PW_P4 0x15 |
| jotaemesousa | 7:5ddd7a2fcb70 | 24 | #define RX_PW_P5 0x16 |
| jotaemesousa | 7:5ddd7a2fcb70 | 25 | #define FIFO_STATUS 0x17 |
| jotaemesousa | 7:5ddd7a2fcb70 | 26 | #define DYNPD 0x1C |
| jotaemesousa | 7:5ddd7a2fcb70 | 27 | #define FEATURE 0x1D |
| jotaemesousa | 7:5ddd7a2fcb70 | 28 | |
| jotaemesousa | 7:5ddd7a2fcb70 | 29 | /* Bit Mnemonics */ |
| jotaemesousa | 7:5ddd7a2fcb70 | 30 | #define MASK_RX_DR 6 |
| jotaemesousa | 7:5ddd7a2fcb70 | 31 | #define MASK_TX_DS 5 |
| jotaemesousa | 7:5ddd7a2fcb70 | 32 | #define MASK_MAX_RT 4 |
| jotaemesousa | 7:5ddd7a2fcb70 | 33 | #define EN_CRC 3 |
| jotaemesousa | 7:5ddd7a2fcb70 | 34 | #define CRCO 2 |
| jotaemesousa | 7:5ddd7a2fcb70 | 35 | #define PWR_UP 1 |
| jotaemesousa | 7:5ddd7a2fcb70 | 36 | #define PRIM_RX 0 |
| jotaemesousa | 7:5ddd7a2fcb70 | 37 | #define ENAA_P5 5 |
| jotaemesousa | 7:5ddd7a2fcb70 | 38 | #define ENAA_P4 4 |
| jotaemesousa | 7:5ddd7a2fcb70 | 39 | #define ENAA_P3 3 |
| jotaemesousa | 7:5ddd7a2fcb70 | 40 | #define ENAA_P2 2 |
| jotaemesousa | 7:5ddd7a2fcb70 | 41 | #define ENAA_P1 1 |
| jotaemesousa | 7:5ddd7a2fcb70 | 42 | #define ENAA_P0 0 |
| jotaemesousa | 7:5ddd7a2fcb70 | 43 | #define ERX_P5 5 |
| jotaemesousa | 7:5ddd7a2fcb70 | 44 | #define ERX_P4 4 |
| jotaemesousa | 7:5ddd7a2fcb70 | 45 | #define ERX_P3 3 |
| jotaemesousa | 7:5ddd7a2fcb70 | 46 | #define ERX_P2 2 |
| jotaemesousa | 7:5ddd7a2fcb70 | 47 | #define ERX_P1 1 |
| jotaemesousa | 7:5ddd7a2fcb70 | 48 | #define ERX_P0 0 |
| jotaemesousa | 7:5ddd7a2fcb70 | 49 | #define AW 0 |
| jotaemesousa | 7:5ddd7a2fcb70 | 50 | #define ARD 4 |
| jotaemesousa | 7:5ddd7a2fcb70 | 51 | #define ARC 0 |
| jotaemesousa | 7:5ddd7a2fcb70 | 52 | #define PLL_LOCK 4 |
| jotaemesousa | 7:5ddd7a2fcb70 | 53 | #define RF_DR 3 |
| jotaemesousa | 7:5ddd7a2fcb70 | 54 | #define RF_PWR 6 |
| jotaemesousa | 7:5ddd7a2fcb70 | 55 | #define RX_DR 6 |
| jotaemesousa | 7:5ddd7a2fcb70 | 56 | #define TX_DS 5 |
| jotaemesousa | 7:5ddd7a2fcb70 | 57 | #define MAX_RT 4 |
| jotaemesousa | 7:5ddd7a2fcb70 | 58 | #define RX_P_NO 1 |
| jotaemesousa | 7:5ddd7a2fcb70 | 59 | #define TX_FULL 0 |
| jotaemesousa | 7:5ddd7a2fcb70 | 60 | #define PLOS_CNT 4 |
| jotaemesousa | 7:5ddd7a2fcb70 | 61 | #define ARC_CNT 0 |
| jotaemesousa | 7:5ddd7a2fcb70 | 62 | #define TX_REUSE 6 |
| jotaemesousa | 7:5ddd7a2fcb70 | 63 | #define FIFO_FULL 5 |
| jotaemesousa | 7:5ddd7a2fcb70 | 64 | #define TX_EMPTY 4 |
| jotaemesousa | 7:5ddd7a2fcb70 | 65 | #define RX_FULL 1 |
| jotaemesousa | 7:5ddd7a2fcb70 | 66 | #define RX_EMPTY 0 |
| jotaemesousa | 7:5ddd7a2fcb70 | 67 | #define DPL_P5 5 |
| jotaemesousa | 7:5ddd7a2fcb70 | 68 | #define DPL_P4 4 |
| jotaemesousa | 7:5ddd7a2fcb70 | 69 | #define DPL_P3 3 |
| jotaemesousa | 7:5ddd7a2fcb70 | 70 | #define DPL_P2 2 |
| jotaemesousa | 7:5ddd7a2fcb70 | 71 | #define DPL_P1 1 |
| jotaemesousa | 7:5ddd7a2fcb70 | 72 | #define DPL_P0 0 |
| jotaemesousa | 7:5ddd7a2fcb70 | 73 | #define EN_DPL 2 |
| jotaemesousa | 7:5ddd7a2fcb70 | 74 | #define EN_ACK_PAY 1 |
| jotaemesousa | 7:5ddd7a2fcb70 | 75 | #define EN_DYN_ACK 0 |
| jotaemesousa | 7:5ddd7a2fcb70 | 76 | |
| jotaemesousa | 7:5ddd7a2fcb70 | 77 | /* Instruction Mnemonics */ |
| jotaemesousa | 7:5ddd7a2fcb70 | 78 | #define R_REGISTER 0x00 |
| jotaemesousa | 7:5ddd7a2fcb70 | 79 | #define W_REGISTER 0x20 |
| jotaemesousa | 7:5ddd7a2fcb70 | 80 | #define REGISTER_MASK 0x1F |
| jotaemesousa | 7:5ddd7a2fcb70 | 81 | #define ACTIVATE 0x50 |
| jotaemesousa | 7:5ddd7a2fcb70 | 82 | #define R_RX_PL_WID 0x60 |
| jotaemesousa | 7:5ddd7a2fcb70 | 83 | #define R_RX_PAYLOAD 0x61 |
| jotaemesousa | 7:5ddd7a2fcb70 | 84 | #define W_TX_PAYLOAD 0xA0 |
| jotaemesousa | 7:5ddd7a2fcb70 | 85 | #define W_ACK_PAYLOAD 0xA8 |
| jotaemesousa | 7:5ddd7a2fcb70 | 86 | #define FLUSH_TX 0xE1 |
| jotaemesousa | 7:5ddd7a2fcb70 | 87 | #define FLUSH_RX 0xE2 |
| jotaemesousa | 7:5ddd7a2fcb70 | 88 | #define REUSE_TX_PL 0xE3 |
| jotaemesousa | 7:5ddd7a2fcb70 | 89 | #define NOP 0xFF |
| jotaemesousa | 7:5ddd7a2fcb70 | 90 | |
| jotaemesousa | 7:5ddd7a2fcb70 | 91 | /* Non-P omissions */ |
| jotaemesousa | 7:5ddd7a2fcb70 | 92 | #define LNA_HCURR 0 |
| jotaemesousa | 7:5ddd7a2fcb70 | 93 | |
| jotaemesousa | 7:5ddd7a2fcb70 | 94 | /* P model memory Map */ |
| jotaemesousa | 7:5ddd7a2fcb70 | 95 | #define RPD 0x09 |
| jotaemesousa | 7:5ddd7a2fcb70 | 96 | |
| jotaemesousa | 7:5ddd7a2fcb70 | 97 | /* P model bit Mnemonics */ |
| jotaemesousa | 7:5ddd7a2fcb70 | 98 | #define RF_DR_LOW 5 |
| jotaemesousa | 7:5ddd7a2fcb70 | 99 | #define RF_DR_HIGH 3 |
| jotaemesousa | 7:5ddd7a2fcb70 | 100 | #define RF_PWR_LOW 1 |
| jotaemesousa | 7:5ddd7a2fcb70 | 101 | #define RF_PWR_HIGH 2 |
| jotaemesousa | 7:5ddd7a2fcb70 | 102 | |
| jotaemesousa | 7:5ddd7a2fcb70 | 103 | #define HIGH 1 |
| jotaemesousa | 7:5ddd7a2fcb70 | 104 | #define LOW 0 |
| jotaemesousa | 7:5ddd7a2fcb70 | 105 | #define _BV(n) (1 << n) |