Seunghee Jeong / Mbed 2 deprecated controller_real

,

Dependencies:   mbed

nRF24L01.h@0:9d06cdd73bc7, 18 months ago (annotated)

Committer:
jjeong
Date:
Sat Dec 03 08:21:37 2022 +0000
Revision:
0:9d06cdd73bc7
controller for quadrotor with RF24 driver;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jjeong 0:9d06cdd73bc7 1 /*
jjeong 0:9d06cdd73bc7 2 Copyright (c) 2007 Stefan Engelke <mbox@stefanengelke.de>
jjeong 0:9d06cdd73bc7 3 Portions Copyright (C) 2011 Greg Copeland
jjeong 0:9d06cdd73bc7 4
jjeong 0:9d06cdd73bc7 5 Permission is hereby granted, free of charge, to any person
jjeong 0:9d06cdd73bc7 6 obtaining a copy of this software and associated documentation
jjeong 0:9d06cdd73bc7 7 files (the "Software"), to deal in the Software without
jjeong 0:9d06cdd73bc7 8 restriction, including without limitation the rights to use, copy,
jjeong 0:9d06cdd73bc7 9 modify, merge, publish, distribute, sublicense, and/or sell copies
jjeong 0:9d06cdd73bc7 10 of the Software, and to permit persons to whom the Software is
jjeong 0:9d06cdd73bc7 11 furnished to do so, subject to the following conditions:
jjeong 0:9d06cdd73bc7 12
jjeong 0:9d06cdd73bc7 13 The above copyright notice and this permission notice shall be
jjeong 0:9d06cdd73bc7 14 included in all copies or substantial portions of the Software.
jjeong 0:9d06cdd73bc7 15
jjeong 0:9d06cdd73bc7 16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
jjeong 0:9d06cdd73bc7 17 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
jjeong 0:9d06cdd73bc7 18 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
jjeong 0:9d06cdd73bc7 19 NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
jjeong 0:9d06cdd73bc7 20 HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
jjeong 0:9d06cdd73bc7 21 WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
jjeong 0:9d06cdd73bc7 22 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
jjeong 0:9d06cdd73bc7 23 DEALINGS IN THE SOFTWARE.
jjeong 0:9d06cdd73bc7 24 */
jjeong 0:9d06cdd73bc7 25
jjeong 0:9d06cdd73bc7 26 /*
jjeong 0:9d06cdd73bc7 27 * Mbed support added by Akash Vibhute <akash.roboticist@gmail.com>
jjeong 0:9d06cdd73bc7 28 * Porting completed on Nov/05/2015
jjeong 0:9d06cdd73bc7 29 *
jjeong 0:9d06cdd73bc7 30 * Updated 1: Synced with TMRh20's RF24 library on Nov/04/2015 from https://github.com/TMRh20
jjeong 0:9d06cdd73bc7 31 * Updated 2: Synced with TMRh20's RF24 library on Apr/18/2015 from https://github.com/TMRh20
jjeong 0:9d06cdd73bc7 32 *
jjeong 0:9d06cdd73bc7 33 */
jjeong 0:9d06cdd73bc7 34
jjeong 0:9d06cdd73bc7 35 /* Memory Map */
jjeong 0:9d06cdd73bc7 36 #define NRF_CONFIG 0x00
jjeong 0:9d06cdd73bc7 37 #define EN_AA 0x01
jjeong 0:9d06cdd73bc7 38 #define EN_RXADDR 0x02
jjeong 0:9d06cdd73bc7 39 #define SETUP_AW 0x03
jjeong 0:9d06cdd73bc7 40 #define SETUP_RETR 0x04
jjeong 0:9d06cdd73bc7 41 #define RF_CH 0x05
jjeong 0:9d06cdd73bc7 42 #define RF_SETUP 0x06
jjeong 0:9d06cdd73bc7 43 #define NRF_STATUS 0x07
jjeong 0:9d06cdd73bc7 44 #define OBSERVE_TX 0x08
jjeong 0:9d06cdd73bc7 45 #define CD 0x09
jjeong 0:9d06cdd73bc7 46 #define RX_ADDR_P0 0x0A
jjeong 0:9d06cdd73bc7 47 #define RX_ADDR_P1 0x0B
jjeong 0:9d06cdd73bc7 48 #define RX_ADDR_P2 0x0C
jjeong 0:9d06cdd73bc7 49 #define RX_ADDR_P3 0x0D
jjeong 0:9d06cdd73bc7 50 #define RX_ADDR_P4 0x0E
jjeong 0:9d06cdd73bc7 51 #define RX_ADDR_P5 0x0F
jjeong 0:9d06cdd73bc7 52 #define TX_ADDR 0x10
jjeong 0:9d06cdd73bc7 53 #define RX_PW_P0 0x11
jjeong 0:9d06cdd73bc7 54 #define RX_PW_P1 0x12
jjeong 0:9d06cdd73bc7 55 #define RX_PW_P2 0x13
jjeong 0:9d06cdd73bc7 56 #define RX_PW_P3 0x14
jjeong 0:9d06cdd73bc7 57 #define RX_PW_P4 0x15
jjeong 0:9d06cdd73bc7 58 #define RX_PW_P5 0x16
jjeong 0:9d06cdd73bc7 59 #define FIFO_STATUS 0x17
jjeong 0:9d06cdd73bc7 60 #define DYNPD 0x1C
jjeong 0:9d06cdd73bc7 61 #define FEATURE 0x1D
jjeong 0:9d06cdd73bc7 62
jjeong 0:9d06cdd73bc7 63 /* Bit Mnemonics */
jjeong 0:9d06cdd73bc7 64 #define MASK_RX_DR 6
jjeong 0:9d06cdd73bc7 65 #define MASK_TX_DS 5
jjeong 0:9d06cdd73bc7 66 #define MASK_MAX_RT 4
jjeong 0:9d06cdd73bc7 67 #define EN_CRC 3
jjeong 0:9d06cdd73bc7 68 #define CRCO 2
jjeong 0:9d06cdd73bc7 69 #define PWR_UP 1
jjeong 0:9d06cdd73bc7 70 #define PRIM_RX 0
jjeong 0:9d06cdd73bc7 71 #define ENAA_P5 5
jjeong 0:9d06cdd73bc7 72 #define ENAA_P4 4
jjeong 0:9d06cdd73bc7 73 #define ENAA_P3 3
jjeong 0:9d06cdd73bc7 74 #define ENAA_P2 2
jjeong 0:9d06cdd73bc7 75 #define ENAA_P1 1
jjeong 0:9d06cdd73bc7 76 #define ENAA_P0 0
jjeong 0:9d06cdd73bc7 77 #define ERX_P5 5
jjeong 0:9d06cdd73bc7 78 #define ERX_P4 4
jjeong 0:9d06cdd73bc7 79 #define ERX_P3 3
jjeong 0:9d06cdd73bc7 80 #define ERX_P2 2
jjeong 0:9d06cdd73bc7 81 #define ERX_P1 1
jjeong 0:9d06cdd73bc7 82 #define ERX_P0 0
jjeong 0:9d06cdd73bc7 83 #define AW 0
jjeong 0:9d06cdd73bc7 84 #define ARD 4
jjeong 0:9d06cdd73bc7 85 #define ARC 0
jjeong 0:9d06cdd73bc7 86 #define PLL_LOCK 4
jjeong 0:9d06cdd73bc7 87 #define RF_DR 3
jjeong 0:9d06cdd73bc7 88 #define RF_PWR 6
jjeong 0:9d06cdd73bc7 89 #define RX_DR 6
jjeong 0:9d06cdd73bc7 90 #define TX_DS 5
jjeong 0:9d06cdd73bc7 91 #define MAX_RT 4
jjeong 0:9d06cdd73bc7 92 #define RX_P_NO 1
jjeong 0:9d06cdd73bc7 93 #define TX_FULL 0
jjeong 0:9d06cdd73bc7 94 #define PLOS_CNT 4
jjeong 0:9d06cdd73bc7 95 #define ARC_CNT 0
jjeong 0:9d06cdd73bc7 96 #define TX_REUSE 6
jjeong 0:9d06cdd73bc7 97 #define FIFO_FULL 5
jjeong 0:9d06cdd73bc7 98 #define TX_EMPTY 4
jjeong 0:9d06cdd73bc7 99 #define RX_FULL 1
jjeong 0:9d06cdd73bc7 100 #define RX_EMPTY 0
jjeong 0:9d06cdd73bc7 101 #define DPL_P5 5
jjeong 0:9d06cdd73bc7 102 #define DPL_P4 4
jjeong 0:9d06cdd73bc7 103 #define DPL_P3 3
jjeong 0:9d06cdd73bc7 104 #define DPL_P2 2
jjeong 0:9d06cdd73bc7 105 #define DPL_P1 1
jjeong 0:9d06cdd73bc7 106 #define DPL_P0 0
jjeong 0:9d06cdd73bc7 107 #define EN_DPL 2
jjeong 0:9d06cdd73bc7 108 #define EN_ACK_PAY 1
jjeong 0:9d06cdd73bc7 109 #define EN_DYN_ACK 0
jjeong 0:9d06cdd73bc7 110
jjeong 0:9d06cdd73bc7 111 /* Instruction Mnemonics */
jjeong 0:9d06cdd73bc7 112 #define R_REGISTER 0x00
jjeong 0:9d06cdd73bc7 113 #define W_REGISTER 0x20
jjeong 0:9d06cdd73bc7 114 #define REGISTER_MASK 0x1F
jjeong 0:9d06cdd73bc7 115 #define ACTIVATE 0x50
jjeong 0:9d06cdd73bc7 116 #define R_RX_PL_WID 0x60
jjeong 0:9d06cdd73bc7 117 #define R_RX_PAYLOAD 0x61
jjeong 0:9d06cdd73bc7 118 #define W_TX_PAYLOAD 0xA0
jjeong 0:9d06cdd73bc7 119 #define W_ACK_PAYLOAD 0xA8
jjeong 0:9d06cdd73bc7 120 #define FLUSH_TX 0xE1
jjeong 0:9d06cdd73bc7 121 #define FLUSH_RX 0xE2
jjeong 0:9d06cdd73bc7 122 #define REUSE_TX_PL 0xE3
jjeong 0:9d06cdd73bc7 123 #define NOP 0xFF
jjeong 0:9d06cdd73bc7 124
jjeong 0:9d06cdd73bc7 125 /* Non-P omissions */
jjeong 0:9d06cdd73bc7 126 #define LNA_HCURR 0
jjeong 0:9d06cdd73bc7 127
jjeong 0:9d06cdd73bc7 128 /* P model memory Map */
jjeong 0:9d06cdd73bc7 129 #define RPD 0x09
jjeong 0:9d06cdd73bc7 130 #define W_TX_PAYLOAD_NO_ACK 0xB0
jjeong 0:9d06cdd73bc7 131
jjeong 0:9d06cdd73bc7 132 /* P model bit Mnemonics */
jjeong 0:9d06cdd73bc7 133 #define RF_DR_LOW 5
jjeong 0:9d06cdd73bc7 134 #define RF_DR_HIGH 3
jjeong 0:9d06cdd73bc7 135 #define RF_PWR_LOW 1
jjeong 0:9d06cdd73bc7 136 #define RF_PWR_HIGH 2
jjeong 0:9d06cdd73bc7 137