Seunghee Jeong / Mbed 2 deprecated controller_real

,

Dependencies:   mbed

RF24.cpp@0:9d06cdd73bc7, 18 months ago (annotated)

Committer:
jjeong
Date:
Sat Dec 03 08:21:37 2022 +0000
Revision:
0:9d06cdd73bc7
controller for quadrotor with RF24 driver;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jjeong 0:9d06cdd73bc7 1 /*
jjeong 0:9d06cdd73bc7 2 Copyright (C) 2011 J. Coliz <maniacbug@ymail.com>
jjeong 0:9d06cdd73bc7 3
jjeong 0:9d06cdd73bc7 4 This program is free software; you can redistribute it and/or
jjeong 0:9d06cdd73bc7 5 modify it under the terms of the GNU General Public License
jjeong 0:9d06cdd73bc7 6 version 2 as published by the Free Software Foundation.
jjeong 0:9d06cdd73bc7 7 */
jjeong 0:9d06cdd73bc7 8
jjeong 0:9d06cdd73bc7 9 /*
jjeong 0:9d06cdd73bc7 10 * Mbed support added by Akash Vibhute <akash.roboticist@gmail.com>
jjeong 0:9d06cdd73bc7 11 * Porting completed on Nov/05/2015
jjeong 0:9d06cdd73bc7 12 *
jjeong 0:9d06cdd73bc7 13 * Updated 1: Synced with TMRh20's RF24 library on Nov/04/2015 from https://github.com/TMRh20
jjeong 0:9d06cdd73bc7 14 * Updated 2: Synced with TMRh20's RF24 library on Apr/18/2015 from https://github.com/TMRh20
jjeong 0:9d06cdd73bc7 15 *
jjeong 0:9d06cdd73bc7 16 */
jjeong 0:9d06cdd73bc7 17
jjeong 0:9d06cdd73bc7 18 #include "nRF24L01.h"
jjeong 0:9d06cdd73bc7 19 #include "RF24_config.h"
jjeong 0:9d06cdd73bc7 20 #include "RF24.h"
jjeong 0:9d06cdd73bc7 21
jjeong 0:9d06cdd73bc7 22 /****************************************************************************/
jjeong 0:9d06cdd73bc7 23
jjeong 0:9d06cdd73bc7 24 void RF24::csn(bool mode)
jjeong 0:9d06cdd73bc7 25 {
jjeong 0:9d06cdd73bc7 26
jjeong 0:9d06cdd73bc7 27 csn_pin = mode;
jjeong 0:9d06cdd73bc7 28
jjeong 0:9d06cdd73bc7 29
jjeong 0:9d06cdd73bc7 30 }
jjeong 0:9d06cdd73bc7 31
jjeong 0:9d06cdd73bc7 32 /****************************************************************************/
jjeong 0:9d06cdd73bc7 33
jjeong 0:9d06cdd73bc7 34 void RF24::ce(bool level)
jjeong 0:9d06cdd73bc7 35 {
jjeong 0:9d06cdd73bc7 36 ce_pin = level;
jjeong 0:9d06cdd73bc7 37
jjeong 0:9d06cdd73bc7 38 }
jjeong 0:9d06cdd73bc7 39
jjeong 0:9d06cdd73bc7 40 /****************************************************************************/
jjeong 0:9d06cdd73bc7 41
jjeong 0:9d06cdd73bc7 42 inline void RF24::beginTransaction() {
jjeong 0:9d06cdd73bc7 43
jjeong 0:9d06cdd73bc7 44
jjeong 0:9d06cdd73bc7 45 csn(LOW);
jjeong 0:9d06cdd73bc7 46 }
jjeong 0:9d06cdd73bc7 47
jjeong 0:9d06cdd73bc7 48 /****************************************************************************/
jjeong 0:9d06cdd73bc7 49
jjeong 0:9d06cdd73bc7 50 inline void RF24::endTransaction() {
jjeong 0:9d06cdd73bc7 51 csn(HIGH);
jjeong 0:9d06cdd73bc7 52
jjeong 0:9d06cdd73bc7 53
jjeong 0:9d06cdd73bc7 54
jjeong 0:9d06cdd73bc7 55 }
jjeong 0:9d06cdd73bc7 56
jjeong 0:9d06cdd73bc7 57 /****************************************************************************/
jjeong 0:9d06cdd73bc7 58
jjeong 0:9d06cdd73bc7 59 uint8_t RF24::read_register(uint8_t reg, uint8_t* buf, uint8_t len)
jjeong 0:9d06cdd73bc7 60 {
jjeong 0:9d06cdd73bc7 61 uint8_t status;
jjeong 0:9d06cdd73bc7 62
jjeong 0:9d06cdd73bc7 63
jjeong 0:9d06cdd73bc7 64
jjeong 0:9d06cdd73bc7 65 beginTransaction();
jjeong 0:9d06cdd73bc7 66 status = spi.write( R_REGISTER | ( REGISTER_MASK & reg ) );
jjeong 0:9d06cdd73bc7 67 while ( len-- ){
jjeong 0:9d06cdd73bc7 68 *buf++ = spi.write(0xff);
jjeong 0:9d06cdd73bc7 69 }
jjeong 0:9d06cdd73bc7 70 endTransaction();
jjeong 0:9d06cdd73bc7 71
jjeong 0:9d06cdd73bc7 72
jjeong 0:9d06cdd73bc7 73
jjeong 0:9d06cdd73bc7 74 return status;
jjeong 0:9d06cdd73bc7 75 }
jjeong 0:9d06cdd73bc7 76
jjeong 0:9d06cdd73bc7 77 /****************************************************************************/
jjeong 0:9d06cdd73bc7 78
jjeong 0:9d06cdd73bc7 79 uint8_t RF24::read_register(uint8_t reg)
jjeong 0:9d06cdd73bc7 80 {
jjeong 0:9d06cdd73bc7 81 uint8_t result;
jjeong 0:9d06cdd73bc7 82
jjeong 0:9d06cdd73bc7 83
jjeong 0:9d06cdd73bc7 84 beginTransaction();
jjeong 0:9d06cdd73bc7 85 spi.write( R_REGISTER | ( REGISTER_MASK & reg ) );
jjeong 0:9d06cdd73bc7 86 result = spi.write(0xff);
jjeong 0:9d06cdd73bc7 87 endTransaction();
jjeong 0:9d06cdd73bc7 88
jjeong 0:9d06cdd73bc7 89
jjeong 0:9d06cdd73bc7 90
jjeong 0:9d06cdd73bc7 91 return result;
jjeong 0:9d06cdd73bc7 92 }
jjeong 0:9d06cdd73bc7 93
jjeong 0:9d06cdd73bc7 94 /****************************************************************************/
jjeong 0:9d06cdd73bc7 95
jjeong 0:9d06cdd73bc7 96 uint8_t RF24::write_register(uint8_t reg, const uint8_t* buf, uint8_t len)
jjeong 0:9d06cdd73bc7 97 {
jjeong 0:9d06cdd73bc7 98 uint8_t status;
jjeong 0:9d06cdd73bc7 99
jjeong 0:9d06cdd73bc7 100
jjeong 0:9d06cdd73bc7 101 beginTransaction();
jjeong 0:9d06cdd73bc7 102 status = spi.write( W_REGISTER | ( REGISTER_MASK & reg ) );
jjeong 0:9d06cdd73bc7 103 while ( len-- )
jjeong 0:9d06cdd73bc7 104 spi.write(*buf++);
jjeong 0:9d06cdd73bc7 105 endTransaction();
jjeong 0:9d06cdd73bc7 106
jjeong 0:9d06cdd73bc7 107
jjeong 0:9d06cdd73bc7 108
jjeong 0:9d06cdd73bc7 109 return status;
jjeong 0:9d06cdd73bc7 110 }
jjeong 0:9d06cdd73bc7 111
jjeong 0:9d06cdd73bc7 112 /****************************************************************************/
jjeong 0:9d06cdd73bc7 113
jjeong 0:9d06cdd73bc7 114 uint8_t RF24::write_register(uint8_t reg, uint8_t value)
jjeong 0:9d06cdd73bc7 115 {
jjeong 0:9d06cdd73bc7 116 uint8_t status;
jjeong 0:9d06cdd73bc7 117
jjeong 0:9d06cdd73bc7 118 IF_SERIAL_DEBUG(printf_P(PSTR("write_register(%02x,%02x)\r\n"),reg,value));
jjeong 0:9d06cdd73bc7 119
jjeong 0:9d06cdd73bc7 120
jjeong 0:9d06cdd73bc7 121 beginTransaction();
jjeong 0:9d06cdd73bc7 122 status = spi.write( W_REGISTER | ( REGISTER_MASK & reg ) );
jjeong 0:9d06cdd73bc7 123 spi.write(value);
jjeong 0:9d06cdd73bc7 124 endTransaction();
jjeong 0:9d06cdd73bc7 125
jjeong 0:9d06cdd73bc7 126
jjeong 0:9d06cdd73bc7 127
jjeong 0:9d06cdd73bc7 128 return status;
jjeong 0:9d06cdd73bc7 129 }
jjeong 0:9d06cdd73bc7 130
jjeong 0:9d06cdd73bc7 131 /****************************************************************************/
jjeong 0:9d06cdd73bc7 132
jjeong 0:9d06cdd73bc7 133 uint8_t RF24::write_payload(const void* buf, uint8_t data_len, const uint8_t writeType)
jjeong 0:9d06cdd73bc7 134 {
jjeong 0:9d06cdd73bc7 135 uint8_t status;
jjeong 0:9d06cdd73bc7 136 const uint8_t* current = reinterpret_cast<const uint8_t*>(buf);
jjeong 0:9d06cdd73bc7 137
jjeong 0:9d06cdd73bc7 138 data_len = rf24_min(data_len, payload_size);
jjeong 0:9d06cdd73bc7 139 uint8_t blank_len = dynamic_payloads_enabled ? 0 : payload_size - data_len;
jjeong 0:9d06cdd73bc7 140
jjeong 0:9d06cdd73bc7 141 //printf("[Writing %u bytes %u blanks]",data_len,blank_len);
jjeong 0:9d06cdd73bc7 142 IF_SERIAL_DEBUG( printf("[Writing %u bytes %u blanks]\n",data_len,blank_len); );
jjeong 0:9d06cdd73bc7 143
jjeong 0:9d06cdd73bc7 144
jjeong 0:9d06cdd73bc7 145 beginTransaction();
jjeong 0:9d06cdd73bc7 146 status = spi.write( writeType );
jjeong 0:9d06cdd73bc7 147 while ( data_len-- ) {
jjeong 0:9d06cdd73bc7 148 spi.write(*current++);
jjeong 0:9d06cdd73bc7 149 }
jjeong 0:9d06cdd73bc7 150 while ( blank_len-- ) {
jjeong 0:9d06cdd73bc7 151 spi.write(0);
jjeong 0:9d06cdd73bc7 152 }
jjeong 0:9d06cdd73bc7 153 endTransaction();
jjeong 0:9d06cdd73bc7 154
jjeong 0:9d06cdd73bc7 155
jjeong 0:9d06cdd73bc7 156
jjeong 0:9d06cdd73bc7 157 return status;
jjeong 0:9d06cdd73bc7 158 }
jjeong 0:9d06cdd73bc7 159
jjeong 0:9d06cdd73bc7 160 /****************************************************************************/
jjeong 0:9d06cdd73bc7 161
jjeong 0:9d06cdd73bc7 162 uint8_t RF24::read_payload(void* buf, uint8_t data_len)
jjeong 0:9d06cdd73bc7 163 {
jjeong 0:9d06cdd73bc7 164 uint8_t status;
jjeong 0:9d06cdd73bc7 165 uint8_t* current = reinterpret_cast<uint8_t*>(buf);
jjeong 0:9d06cdd73bc7 166
jjeong 0:9d06cdd73bc7 167 if(data_len > payload_size) data_len = payload_size;
jjeong 0:9d06cdd73bc7 168 uint8_t blank_len = dynamic_payloads_enabled ? 0 : payload_size - data_len;
jjeong 0:9d06cdd73bc7 169
jjeong 0:9d06cdd73bc7 170 //printf("[Reading %u bytes %u blanks]",data_len,blank_len);
jjeong 0:9d06cdd73bc7 171
jjeong 0:9d06cdd73bc7 172 IF_SERIAL_DEBUG( printf("[Reading %u bytes %u blanks]\n",data_len,blank_len); );
jjeong 0:9d06cdd73bc7 173
jjeong 0:9d06cdd73bc7 174
jjeong 0:9d06cdd73bc7 175
jjeong 0:9d06cdd73bc7 176 beginTransaction();
jjeong 0:9d06cdd73bc7 177 status = spi.write( R_RX_PAYLOAD );
jjeong 0:9d06cdd73bc7 178 while ( data_len-- ) {
jjeong 0:9d06cdd73bc7 179 *current++ = spi.write(0xFF);
jjeong 0:9d06cdd73bc7 180 }
jjeong 0:9d06cdd73bc7 181 while ( blank_len-- ) {
jjeong 0:9d06cdd73bc7 182 spi.write(0xff);
jjeong 0:9d06cdd73bc7 183 }
jjeong 0:9d06cdd73bc7 184 endTransaction();
jjeong 0:9d06cdd73bc7 185
jjeong 0:9d06cdd73bc7 186
jjeong 0:9d06cdd73bc7 187
jjeong 0:9d06cdd73bc7 188 return status;
jjeong 0:9d06cdd73bc7 189 }
jjeong 0:9d06cdd73bc7 190
jjeong 0:9d06cdd73bc7 191 /****************************************************************************/
jjeong 0:9d06cdd73bc7 192
jjeong 0:9d06cdd73bc7 193 uint8_t RF24::flush_rx(void)
jjeong 0:9d06cdd73bc7 194 {
jjeong 0:9d06cdd73bc7 195 return spiTrans( FLUSH_RX );
jjeong 0:9d06cdd73bc7 196 }
jjeong 0:9d06cdd73bc7 197
jjeong 0:9d06cdd73bc7 198 /****************************************************************************/
jjeong 0:9d06cdd73bc7 199
jjeong 0:9d06cdd73bc7 200 uint8_t RF24::flush_tx(void)
jjeong 0:9d06cdd73bc7 201 {
jjeong 0:9d06cdd73bc7 202 return spiTrans( FLUSH_TX );
jjeong 0:9d06cdd73bc7 203 }
jjeong 0:9d06cdd73bc7 204
jjeong 0:9d06cdd73bc7 205 /****************************************************************************/
jjeong 0:9d06cdd73bc7 206
jjeong 0:9d06cdd73bc7 207 uint8_t RF24::spiTrans(uint8_t cmd){
jjeong 0:9d06cdd73bc7 208
jjeong 0:9d06cdd73bc7 209 uint8_t status;
jjeong 0:9d06cdd73bc7 210
jjeong 0:9d06cdd73bc7 211 beginTransaction();
jjeong 0:9d06cdd73bc7 212 status = spi.write( cmd );
jjeong 0:9d06cdd73bc7 213 endTransaction();
jjeong 0:9d06cdd73bc7 214
jjeong 0:9d06cdd73bc7 215 return status;
jjeong 0:9d06cdd73bc7 216 }
jjeong 0:9d06cdd73bc7 217
jjeong 0:9d06cdd73bc7 218 /****************************************************************************/
jjeong 0:9d06cdd73bc7 219
jjeong 0:9d06cdd73bc7 220 uint8_t RF24::get_status(void)
jjeong 0:9d06cdd73bc7 221 {
jjeong 0:9d06cdd73bc7 222 return spiTrans(NOP);
jjeong 0:9d06cdd73bc7 223 }
jjeong 0:9d06cdd73bc7 224
jjeong 0:9d06cdd73bc7 225 /****************************************************************************/
jjeong 0:9d06cdd73bc7 226 #if !defined (MINIMAL)
jjeong 0:9d06cdd73bc7 227 void RF24::print_status(uint8_t status)
jjeong 0:9d06cdd73bc7 228 {
jjeong 0:9d06cdd73bc7 229 printf_P(PSTR("STATUS\t\t = 0x%02x RX_DR=%x TX_DS=%x MAX_RT=%x RX_P_NO=%x TX_FULL=%x\r\n"),
jjeong 0:9d06cdd73bc7 230 status,
jjeong 0:9d06cdd73bc7 231 (status & _BV(RX_DR))?1:0,
jjeong 0:9d06cdd73bc7 232 (status & _BV(TX_DS))?1:0,
jjeong 0:9d06cdd73bc7 233 (status & _BV(MAX_RT))?1:0,
jjeong 0:9d06cdd73bc7 234 ((status >> RX_P_NO) & 0b111),
jjeong 0:9d06cdd73bc7 235 (status & _BV(TX_FULL))?1:0
jjeong 0:9d06cdd73bc7 236 );
jjeong 0:9d06cdd73bc7 237 }
jjeong 0:9d06cdd73bc7 238
jjeong 0:9d06cdd73bc7 239 /****************************************************************************/
jjeong 0:9d06cdd73bc7 240
jjeong 0:9d06cdd73bc7 241 void RF24::print_observe_tx(uint8_t value)
jjeong 0:9d06cdd73bc7 242 {
jjeong 0:9d06cdd73bc7 243 printf_P(PSTR("OBSERVE_TX=%02x: POLS_CNT=%x ARC_CNT=%x\r\n"),
jjeong 0:9d06cdd73bc7 244 value,
jjeong 0:9d06cdd73bc7 245 (value >> PLOS_CNT) & 0b1111,
jjeong 0:9d06cdd73bc7 246 (value >> ARC_CNT) & 0b1111
jjeong 0:9d06cdd73bc7 247 );
jjeong 0:9d06cdd73bc7 248 }
jjeong 0:9d06cdd73bc7 249
jjeong 0:9d06cdd73bc7 250 /****************************************************************************/
jjeong 0:9d06cdd73bc7 251
jjeong 0:9d06cdd73bc7 252 void RF24::print_byte_register(const char* name, uint8_t reg, uint8_t qty)
jjeong 0:9d06cdd73bc7 253 {
jjeong 0:9d06cdd73bc7 254 //char extra_tab = strlen_P(name) < 8 ? '\t' : 0;
jjeong 0:9d06cdd73bc7 255 //printf_P(PSTR(PRIPSTR"\t%c ="),name,extra_tab);
jjeong 0:9d06cdd73bc7 256
jjeong 0:9d06cdd73bc7 257
jjeong 0:9d06cdd73bc7 258
jjeong 0:9d06cdd73bc7 259 printf_P(PSTR(PRIPSTR"\t ="),name);
jjeong 0:9d06cdd73bc7 260
jjeong 0:9d06cdd73bc7 261 while (qty--)
jjeong 0:9d06cdd73bc7 262 printf_P(PSTR(" 0x%02x"),read_register(reg++));
jjeong 0:9d06cdd73bc7 263 printf_P(PSTR("\r\n"));
jjeong 0:9d06cdd73bc7 264 }
jjeong 0:9d06cdd73bc7 265
jjeong 0:9d06cdd73bc7 266 /****************************************************************************/
jjeong 0:9d06cdd73bc7 267
jjeong 0:9d06cdd73bc7 268 void RF24::print_address_register(const char* name, uint8_t reg, uint8_t qty)
jjeong 0:9d06cdd73bc7 269 {
jjeong 0:9d06cdd73bc7 270
jjeong 0:9d06cdd73bc7 271
jjeong 0:9d06cdd73bc7 272
jjeong 0:9d06cdd73bc7 273
jjeong 0:9d06cdd73bc7 274 printf_P(PSTR(PRIPSTR"\t ="),name);
jjeong 0:9d06cdd73bc7 275
jjeong 0:9d06cdd73bc7 276 while (qty--)
jjeong 0:9d06cdd73bc7 277 {
jjeong 0:9d06cdd73bc7 278 uint8_t buffer[addr_width];
jjeong 0:9d06cdd73bc7 279 read_register(reg++,buffer,sizeof buffer);
jjeong 0:9d06cdd73bc7 280
jjeong 0:9d06cdd73bc7 281 printf_P(PSTR(" 0x"));
jjeong 0:9d06cdd73bc7 282 uint8_t* bufptr = buffer + sizeof buffer;
jjeong 0:9d06cdd73bc7 283 while( --bufptr >= buffer )
jjeong 0:9d06cdd73bc7 284 printf_P(PSTR("%02x"),*bufptr);
jjeong 0:9d06cdd73bc7 285 }
jjeong 0:9d06cdd73bc7 286
jjeong 0:9d06cdd73bc7 287 printf_P(PSTR("\r\n"));
jjeong 0:9d06cdd73bc7 288 }
jjeong 0:9d06cdd73bc7 289 #endif
jjeong 0:9d06cdd73bc7 290 /****************************************************************************/
jjeong 0:9d06cdd73bc7 291 RF24::RF24(PinName mosi, PinName miso, PinName sck, PinName _cepin, PinName _csnpin):
jjeong 0:9d06cdd73bc7 292 spi(mosi, miso, sck), ce_pin(_cepin), csn_pin(_csnpin), p_variant(true),
jjeong 0:9d06cdd73bc7 293 payload_size(32), dynamic_payloads_enabled(false), addr_width(5)
jjeong 0:9d06cdd73bc7 294 {
jjeong 0:9d06cdd73bc7 295 pipe0_reading_address[0]=0;
jjeong 0:9d06cdd73bc7 296
jjeong 0:9d06cdd73bc7 297 //spi.frequency(10000000/5); // 2Mbit, 1/5th the maximum transfer rate for the spi bus
jjeong 0:9d06cdd73bc7 298 spi.frequency(10000000/5);
jjeong 0:9d06cdd73bc7 299 //spi.format(8,0); // 8-bit, ClockPhase = 0, ClockPolarity = 0
jjeong 0:9d06cdd73bc7 300 spi.format(8,0);
jjeong 0:9d06cdd73bc7 301 wait_ms(10);
jjeong 0:9d06cdd73bc7 302 }
jjeong 0:9d06cdd73bc7 303
jjeong 0:9d06cdd73bc7 304
jjeong 0:9d06cdd73bc7 305
jjeong 0:9d06cdd73bc7 306
jjeong 0:9d06cdd73bc7 307
jjeong 0:9d06cdd73bc7 308
jjeong 0:9d06cdd73bc7 309
jjeong 0:9d06cdd73bc7 310
jjeong 0:9d06cdd73bc7 311 /****************************************************************************/
jjeong 0:9d06cdd73bc7 312
jjeong 0:9d06cdd73bc7 313 void RF24::setChannel(uint8_t channel)
jjeong 0:9d06cdd73bc7 314 {
jjeong 0:9d06cdd73bc7 315 const uint8_t max_channel = 125;
jjeong 0:9d06cdd73bc7 316 write_register(RF_CH,rf24_min(channel,max_channel));
jjeong 0:9d06cdd73bc7 317 }
jjeong 0:9d06cdd73bc7 318
jjeong 0:9d06cdd73bc7 319 uint8_t RF24::getChannel()
jjeong 0:9d06cdd73bc7 320 {
jjeong 0:9d06cdd73bc7 321
jjeong 0:9d06cdd73bc7 322 return read_register(RF_CH);
jjeong 0:9d06cdd73bc7 323 }
jjeong 0:9d06cdd73bc7 324 /****************************************************************************/
jjeong 0:9d06cdd73bc7 325
jjeong 0:9d06cdd73bc7 326 void RF24::setPayloadSize(uint8_t size)
jjeong 0:9d06cdd73bc7 327 {
jjeong 0:9d06cdd73bc7 328 payload_size = rf24_min(size,32);
jjeong 0:9d06cdd73bc7 329 }
jjeong 0:9d06cdd73bc7 330
jjeong 0:9d06cdd73bc7 331 /****************************************************************************/
jjeong 0:9d06cdd73bc7 332
jjeong 0:9d06cdd73bc7 333 uint8_t RF24::getPayloadSize(void)
jjeong 0:9d06cdd73bc7 334 {
jjeong 0:9d06cdd73bc7 335 return payload_size;
jjeong 0:9d06cdd73bc7 336 }
jjeong 0:9d06cdd73bc7 337
jjeong 0:9d06cdd73bc7 338 /****************************************************************************/
jjeong 0:9d06cdd73bc7 339
jjeong 0:9d06cdd73bc7 340 #if !defined (MINIMAL)
jjeong 0:9d06cdd73bc7 341
jjeong 0:9d06cdd73bc7 342 static const char rf24_datarate_e_str_0[] PROGMEM = "1MBPS";
jjeong 0:9d06cdd73bc7 343 static const char rf24_datarate_e_str_1[] PROGMEM = "2MBPS";
jjeong 0:9d06cdd73bc7 344 static const char rf24_datarate_e_str_2[] PROGMEM = "250KBPS";
jjeong 0:9d06cdd73bc7 345 static const char * const rf24_datarate_e_str_P[] PROGMEM = {
jjeong 0:9d06cdd73bc7 346 rf24_datarate_e_str_0,
jjeong 0:9d06cdd73bc7 347 rf24_datarate_e_str_1,
jjeong 0:9d06cdd73bc7 348 rf24_datarate_e_str_2,
jjeong 0:9d06cdd73bc7 349 };
jjeong 0:9d06cdd73bc7 350 static const char rf24_model_e_str_0[] PROGMEM = "nRF24L01";
jjeong 0:9d06cdd73bc7 351 static const char rf24_model_e_str_1[] PROGMEM = "nRF24L01+";
jjeong 0:9d06cdd73bc7 352 static const char * const rf24_model_e_str_P[] PROGMEM = {
jjeong 0:9d06cdd73bc7 353 rf24_model_e_str_0,
jjeong 0:9d06cdd73bc7 354 rf24_model_e_str_1,
jjeong 0:9d06cdd73bc7 355 };
jjeong 0:9d06cdd73bc7 356 static const char rf24_crclength_e_str_0[] PROGMEM = "Disabled";
jjeong 0:9d06cdd73bc7 357 static const char rf24_crclength_e_str_1[] PROGMEM = "8 bits";
jjeong 0:9d06cdd73bc7 358 static const char rf24_crclength_e_str_2[] PROGMEM = "16 bits" ;
jjeong 0:9d06cdd73bc7 359 static const char * const rf24_crclength_e_str_P[] PROGMEM = {
jjeong 0:9d06cdd73bc7 360 rf24_crclength_e_str_0,
jjeong 0:9d06cdd73bc7 361 rf24_crclength_e_str_1,
jjeong 0:9d06cdd73bc7 362 rf24_crclength_e_str_2,
jjeong 0:9d06cdd73bc7 363 };
jjeong 0:9d06cdd73bc7 364 static const char rf24_pa_dbm_e_str_0[] PROGMEM = "PA_MIN";
jjeong 0:9d06cdd73bc7 365 static const char rf24_pa_dbm_e_str_1[] PROGMEM = "PA_LOW";
jjeong 0:9d06cdd73bc7 366 static const char rf24_pa_dbm_e_str_2[] PROGMEM = "PA_HIGH";
jjeong 0:9d06cdd73bc7 367 static const char rf24_pa_dbm_e_str_3[] PROGMEM = "PA_MAX";
jjeong 0:9d06cdd73bc7 368 static const char * const rf24_pa_dbm_e_str_P[] PROGMEM = {
jjeong 0:9d06cdd73bc7 369 rf24_pa_dbm_e_str_0,
jjeong 0:9d06cdd73bc7 370 rf24_pa_dbm_e_str_1,
jjeong 0:9d06cdd73bc7 371 rf24_pa_dbm_e_str_2,
jjeong 0:9d06cdd73bc7 372 rf24_pa_dbm_e_str_3,
jjeong 0:9d06cdd73bc7 373 };
jjeong 0:9d06cdd73bc7 374
jjeong 0:9d06cdd73bc7 375
jjeong 0:9d06cdd73bc7 376
jjeong 0:9d06cdd73bc7 377
jjeong 0:9d06cdd73bc7 378
jjeong 0:9d06cdd73bc7 379
jjeong 0:9d06cdd73bc7 380
jjeong 0:9d06cdd73bc7 381
jjeong 0:9d06cdd73bc7 382
jjeong 0:9d06cdd73bc7 383
jjeong 0:9d06cdd73bc7 384
jjeong 0:9d06cdd73bc7 385
jjeong 0:9d06cdd73bc7 386
jjeong 0:9d06cdd73bc7 387
jjeong 0:9d06cdd73bc7 388 void RF24::printDetails(void)
jjeong 0:9d06cdd73bc7 389 {
jjeong 0:9d06cdd73bc7 390
jjeong 0:9d06cdd73bc7 391
jjeong 0:9d06cdd73bc7 392 print_status(get_status());
jjeong 0:9d06cdd73bc7 393
jjeong 0:9d06cdd73bc7 394 print_address_register(PSTR("RX_ADDR_P0-1"),RX_ADDR_P0,2);
jjeong 0:9d06cdd73bc7 395 print_byte_register(PSTR("RX_ADDR_P2-5"),RX_ADDR_P2,4);
jjeong 0:9d06cdd73bc7 396 print_address_register(PSTR("TX_ADDR\t"),TX_ADDR);
jjeong 0:9d06cdd73bc7 397
jjeong 0:9d06cdd73bc7 398 print_byte_register(PSTR("RX_PW_P0-6"),RX_PW_P0,6);
jjeong 0:9d06cdd73bc7 399 print_byte_register(PSTR("EN_AA\t"),EN_AA);
jjeong 0:9d06cdd73bc7 400 print_byte_register(PSTR("EN_RXADDR"),EN_RXADDR);
jjeong 0:9d06cdd73bc7 401 print_byte_register(PSTR("RF_CH\t"),RF_CH);
jjeong 0:9d06cdd73bc7 402 print_byte_register(PSTR("RF_SETUP"),RF_SETUP);
jjeong 0:9d06cdd73bc7 403 print_byte_register(PSTR("CONFIG\t"),NRF_CONFIG);
jjeong 0:9d06cdd73bc7 404 print_byte_register(PSTR("DYNPD/FEATURE"),DYNPD,2);
jjeong 0:9d06cdd73bc7 405
jjeong 0:9d06cdd73bc7 406 printf_P(PSTR("Data Rate\t = " PRIPSTR "\r\n"),pgm_read_word(&rf24_datarate_e_str_P[getDataRate()]));
jjeong 0:9d06cdd73bc7 407 printf_P(PSTR("Model\t\t = " PRIPSTR "\r\n"),pgm_read_word(&rf24_model_e_str_P[isPVariant()]));
jjeong 0:9d06cdd73bc7 408 printf_P(PSTR("CRC Length\t = " PRIPSTR "\r\n"),pgm_read_word(&rf24_crclength_e_str_P[getCRCLength()]));
jjeong 0:9d06cdd73bc7 409 printf_P(PSTR("PA Power\t = " PRIPSTR "\r\n"), pgm_read_word(&rf24_pa_dbm_e_str_P[getPALevel()]));
jjeong 0:9d06cdd73bc7 410
jjeong 0:9d06cdd73bc7 411 }
jjeong 0:9d06cdd73bc7 412
jjeong 0:9d06cdd73bc7 413 #endif
jjeong 0:9d06cdd73bc7 414 /****************************************************************************/
jjeong 0:9d06cdd73bc7 415
jjeong 0:9d06cdd73bc7 416 bool RF24::begin(void)
jjeong 0:9d06cdd73bc7 417 {
jjeong 0:9d06cdd73bc7 418
jjeong 0:9d06cdd73bc7 419 uint8_t setup=0;
jjeong 0:9d06cdd73bc7 420
jjeong 0:9d06cdd73bc7 421 mainTimer.start();
jjeong 0:9d06cdd73bc7 422
jjeong 0:9d06cdd73bc7 423 ce(LOW);
jjeong 0:9d06cdd73bc7 424 csn(HIGH);
jjeong 0:9d06cdd73bc7 425
jjeong 0:9d06cdd73bc7 426 wait_ms(100);
jjeong 0:9d06cdd73bc7 427
jjeong 0:9d06cdd73bc7 428
jjeong 0:9d06cdd73bc7 429
jjeong 0:9d06cdd73bc7 430
jjeong 0:9d06cdd73bc7 431 // Must allow the radio time to settle else configuration bits will not necessarily stick.
jjeong 0:9d06cdd73bc7 432 // This is actually only required following power up but some settling time also appears to
jjeong 0:9d06cdd73bc7 433 // be required after resets too. For full coverage, we'll always assume the worst.
jjeong 0:9d06cdd73bc7 434 // Enabling 16b CRC is by far the most obvious case if the wrong timing is used - or skipped.
jjeong 0:9d06cdd73bc7 435 // Technically we require 4.5ms + 14us as a worst case. We'll just call it 5ms for good measure.
jjeong 0:9d06cdd73bc7 436 // WARNING: Delay is based on P-variant whereby non-P *may* require different timing.
jjeong 0:9d06cdd73bc7 437 wait_ms( 5 ) ;
jjeong 0:9d06cdd73bc7 438
jjeong 0:9d06cdd73bc7 439 // Reset NRF_CONFIG and enable 16-bit CRC.
jjeong 0:9d06cdd73bc7 440 write_register( NRF_CONFIG, 0b00001100 ) ;
jjeong 0:9d06cdd73bc7 441
jjeong 0:9d06cdd73bc7 442 // Set 1500uS (minimum for 32B payload in ESB@250KBPS) timeouts, to make testing a little easier
jjeong 0:9d06cdd73bc7 443 // WARNING: If this is ever lowered, either 250KBS mode with AA is broken or maximum packet
jjeong 0:9d06cdd73bc7 444 // sizes must never be used. See documentation for a more complete explanation.
jjeong 0:9d06cdd73bc7 445 setRetries(5,15);
jjeong 0:9d06cdd73bc7 446
jjeong 0:9d06cdd73bc7 447 // Reset value is MAX
jjeong 0:9d06cdd73bc7 448 //setPALevel( RF24_PA_MAX ) ;
jjeong 0:9d06cdd73bc7 449
jjeong 0:9d06cdd73bc7 450 // check for connected module and if this is a p nRF24l01 variant
jjeong 0:9d06cdd73bc7 451 //
jjeong 0:9d06cdd73bc7 452 if( setDataRate( RF24_250KBPS ) )
jjeong 0:9d06cdd73bc7 453 {
jjeong 0:9d06cdd73bc7 454 p_variant = true ;
jjeong 0:9d06cdd73bc7 455 }
jjeong 0:9d06cdd73bc7 456 setup = read_register(RF_SETUP);
jjeong 0:9d06cdd73bc7 457 /*if( setup == 0b00001110 ) // register default for nRF24L01P
jjeong 0:9d06cdd73bc7 458 {
jjeong 0:9d06cdd73bc7 459 p_variant = true ;
jjeong 0:9d06cdd73bc7 460 }*/
jjeong 0:9d06cdd73bc7 461
jjeong 0:9d06cdd73bc7 462 // Then set the data rate to the slowest (and most reliable) speed supported by all
jjeong 0:9d06cdd73bc7 463 // hardware.
jjeong 0:9d06cdd73bc7 464 //setDataRate( RF24_1MBPS ) ;
jjeong 0:9d06cdd73bc7 465 setDataRate( RF24_1MBPS ) ;
jjeong 0:9d06cdd73bc7 466
jjeong 0:9d06cdd73bc7 467 // Initialize CRC and request 2-byte (16bit) CRC
jjeong 0:9d06cdd73bc7 468 setCRCLength( RF24_CRC_16 ) ;
jjeong 0:9d06cdd73bc7 469
jjeong 0:9d06cdd73bc7 470 // Disable dynamic payloads, to match dynamic_payloads_enabled setting - Reset value is 0
jjeong 0:9d06cdd73bc7 471 toggle_features();
jjeong 0:9d06cdd73bc7 472 write_register(FEATURE,0 );
jjeong 0:9d06cdd73bc7 473 write_register(DYNPD,0);
jjeong 0:9d06cdd73bc7 474
jjeong 0:9d06cdd73bc7 475 // Reset current status
jjeong 0:9d06cdd73bc7 476 // Notice reset and flush is the last thing we do
jjeong 0:9d06cdd73bc7 477 write_register(NRF_STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
jjeong 0:9d06cdd73bc7 478
jjeong 0:9d06cdd73bc7 479 // Set up default configuration. Callers can always change it later.
jjeong 0:9d06cdd73bc7 480 // This channel should be universally safe and not bleed over into adjacent
jjeong 0:9d06cdd73bc7 481 // spectrum.
jjeong 0:9d06cdd73bc7 482 setChannel(76);
jjeong 0:9d06cdd73bc7 483
jjeong 0:9d06cdd73bc7 484 // Flush buffers
jjeong 0:9d06cdd73bc7 485 flush_rx();
jjeong 0:9d06cdd73bc7 486 flush_tx();
jjeong 0:9d06cdd73bc7 487
jjeong 0:9d06cdd73bc7 488 powerUp(); //Power up by default when begin() is called
jjeong 0:9d06cdd73bc7 489
jjeong 0:9d06cdd73bc7 490 // Enable PTX, do not write CE high so radio will remain in standby I mode ( 130us max to transition to RX or TX instead of 1500us from powerUp )
jjeong 0:9d06cdd73bc7 491 // PTX should use only 22uA of power
jjeong 0:9d06cdd73bc7 492 write_register(NRF_CONFIG, ( read_register(NRF_CONFIG) ) & ~_BV(PRIM_RX) );
jjeong 0:9d06cdd73bc7 493 printDetails();
jjeong 0:9d06cdd73bc7 494 // if setup is 0 or ff then there was no response from module
jjeong 0:9d06cdd73bc7 495 return ( setup != 0 && setup != 0xff );
jjeong 0:9d06cdd73bc7 496 }
jjeong 0:9d06cdd73bc7 497
jjeong 0:9d06cdd73bc7 498 /****************************************************************************/
jjeong 0:9d06cdd73bc7 499
jjeong 0:9d06cdd73bc7 500 void RF24::startListening(void)
jjeong 0:9d06cdd73bc7 501 {
jjeong 0:9d06cdd73bc7 502
jjeong 0:9d06cdd73bc7 503
jjeong 0:9d06cdd73bc7 504
jjeong 0:9d06cdd73bc7 505 write_register(NRF_CONFIG, read_register(NRF_CONFIG) | _BV(PRIM_RX));
jjeong 0:9d06cdd73bc7 506 write_register(NRF_STATUS, _BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
jjeong 0:9d06cdd73bc7 507 ce(HIGH);
jjeong 0:9d06cdd73bc7 508 // Restore the pipe0 adddress, if exists
jjeong 0:9d06cdd73bc7 509 if (pipe0_reading_address[0] > 0){
jjeong 0:9d06cdd73bc7 510 write_register(RX_ADDR_P0, pipe0_reading_address, addr_width);
jjeong 0:9d06cdd73bc7 511 }else{
jjeong 0:9d06cdd73bc7 512 closeReadingPipe(0);
jjeong 0:9d06cdd73bc7 513 }
jjeong 0:9d06cdd73bc7 514
jjeong 0:9d06cdd73bc7 515 // Flush buffers
jjeong 0:9d06cdd73bc7 516 //flush_rx();
jjeong 0:9d06cdd73bc7 517 if(read_register(FEATURE) & _BV(EN_ACK_PAY)){
jjeong 0:9d06cdd73bc7 518 flush_tx();
jjeong 0:9d06cdd73bc7 519 }
jjeong 0:9d06cdd73bc7 520
jjeong 0:9d06cdd73bc7 521 // Go!
jjeong 0:9d06cdd73bc7 522 //delayMicroseconds(100);
jjeong 0:9d06cdd73bc7 523 }
jjeong 0:9d06cdd73bc7 524
jjeong 0:9d06cdd73bc7 525 /****************************************************************************/
jjeong 0:9d06cdd73bc7 526 static const uint8_t child_pipe_enable[] PROGMEM =
jjeong 0:9d06cdd73bc7 527 {
jjeong 0:9d06cdd73bc7 528 ERX_P0, ERX_P1, ERX_P2, ERX_P3, ERX_P4, ERX_P5
jjeong 0:9d06cdd73bc7 529 };
jjeong 0:9d06cdd73bc7 530
jjeong 0:9d06cdd73bc7 531 void RF24::stopListening(void)
jjeong 0:9d06cdd73bc7 532 {
jjeong 0:9d06cdd73bc7 533 ce(LOW);
jjeong 0:9d06cdd73bc7 534
jjeong 0:9d06cdd73bc7 535 wait_us(txRxDelay);
jjeong 0:9d06cdd73bc7 536
jjeong 0:9d06cdd73bc7 537 if(read_register(FEATURE) & _BV(EN_ACK_PAY)){
jjeong 0:9d06cdd73bc7 538 wait_us(txRxDelay); //200
jjeong 0:9d06cdd73bc7 539 flush_tx();
jjeong 0:9d06cdd73bc7 540 }
jjeong 0:9d06cdd73bc7 541 //flush_rx();
jjeong 0:9d06cdd73bc7 542 write_register(NRF_CONFIG, ( read_register(NRF_CONFIG) ) & ~_BV(PRIM_RX) );
jjeong 0:9d06cdd73bc7 543
jjeong 0:9d06cdd73bc7 544
jjeong 0:9d06cdd73bc7 545 write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[0]))); // Enable RX on pipe0
jjeong 0:9d06cdd73bc7 546
jjeong 0:9d06cdd73bc7 547 //delayMicroseconds(100);
jjeong 0:9d06cdd73bc7 548
jjeong 0:9d06cdd73bc7 549 }
jjeong 0:9d06cdd73bc7 550
jjeong 0:9d06cdd73bc7 551 /****************************************************************************/
jjeong 0:9d06cdd73bc7 552
jjeong 0:9d06cdd73bc7 553 void RF24::powerDown(void)
jjeong 0:9d06cdd73bc7 554 {
jjeong 0:9d06cdd73bc7 555 ce(LOW); // Guarantee CE is low on powerDown
jjeong 0:9d06cdd73bc7 556 write_register(NRF_CONFIG,read_register(NRF_CONFIG) & ~_BV(PWR_UP));
jjeong 0:9d06cdd73bc7 557 }
jjeong 0:9d06cdd73bc7 558
jjeong 0:9d06cdd73bc7 559 /****************************************************************************/
jjeong 0:9d06cdd73bc7 560
jjeong 0:9d06cdd73bc7 561 //Power up now. Radio will not power down unless instructed by MCU for config changes etc.
jjeong 0:9d06cdd73bc7 562 void RF24::powerUp(void)
jjeong 0:9d06cdd73bc7 563 {
jjeong 0:9d06cdd73bc7 564 uint8_t cfg = read_register(NRF_CONFIG);
jjeong 0:9d06cdd73bc7 565
jjeong 0:9d06cdd73bc7 566 // if not powered up then power up and wait for the radio to initialize
jjeong 0:9d06cdd73bc7 567 if (!(cfg & _BV(PWR_UP))){
jjeong 0:9d06cdd73bc7 568 write_register(NRF_CONFIG, cfg | _BV(PWR_UP));
jjeong 0:9d06cdd73bc7 569
jjeong 0:9d06cdd73bc7 570 // For nRF24L01+ to go from power down mode to TX or RX mode it must first pass through stand-by mode.
jjeong 0:9d06cdd73bc7 571 // There must be a delay of Tpd2stby (see Table 16.) after the nRF24L01+ leaves power down mode before
jjeong 0:9d06cdd73bc7 572 // the CEis set high. - Tpd2stby can be up to 5ms per the 1.0 datasheet
jjeong 0:9d06cdd73bc7 573 wait_ms(5);
jjeong 0:9d06cdd73bc7 574 }
jjeong 0:9d06cdd73bc7 575 }
jjeong 0:9d06cdd73bc7 576
jjeong 0:9d06cdd73bc7 577 /******************************************************************/
jjeong 0:9d06cdd73bc7 578 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
jjeong 0:9d06cdd73bc7 579 void RF24::errNotify(){
jjeong 0:9d06cdd73bc7 580 #if defined (SERIAL_DEBUG) || defined (RF24_LINUX)
jjeong 0:9d06cdd73bc7 581 printf_P(PSTR("RF24 HARDWARE FAIL: Radio not responding, verify pin connections, wiring, etc.\r\n"));
jjeong 0:9d06cdd73bc7 582 #endif
jjeong 0:9d06cdd73bc7 583 #if defined (FAILURE_HANDLING)
jjeong 0:9d06cdd73bc7 584 failureDetected = 1;
jjeong 0:9d06cdd73bc7 585 #else
jjeong 0:9d06cdd73bc7 586 wait_ms(5000);
jjeong 0:9d06cdd73bc7 587 #endif
jjeong 0:9d06cdd73bc7 588 }
jjeong 0:9d06cdd73bc7 589 #endif
jjeong 0:9d06cdd73bc7 590 /******************************************************************/
jjeong 0:9d06cdd73bc7 591
jjeong 0:9d06cdd73bc7 592 //Similar to the previous write, clears the interrupt flags
jjeong 0:9d06cdd73bc7 593 bool RF24::write( const void* buf, uint8_t len, const bool multicast )
jjeong 0:9d06cdd73bc7 594 {
jjeong 0:9d06cdd73bc7 595 //Start Writing
jjeong 0:9d06cdd73bc7 596 startFastWrite(buf,len,multicast);
jjeong 0:9d06cdd73bc7 597
jjeong 0:9d06cdd73bc7 598 //Wait until complete or failed
jjeong 0:9d06cdd73bc7 599 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
jjeong 0:9d06cdd73bc7 600 uint32_t timer = mainTimer.read_ms();
jjeong 0:9d06cdd73bc7 601 #endif
jjeong 0:9d06cdd73bc7 602
jjeong 0:9d06cdd73bc7 603 while( ! ( get_status() & ( _BV(TX_DS) | _BV(MAX_RT) ))) {
jjeong 0:9d06cdd73bc7 604 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
jjeong 0:9d06cdd73bc7 605 if(mainTimer.read_ms() - timer > 95){
jjeong 0:9d06cdd73bc7 606 errNotify();
jjeong 0:9d06cdd73bc7 607 #if defined (FAILURE_HANDLING)
jjeong 0:9d06cdd73bc7 608 return 0;
jjeong 0:9d06cdd73bc7 609 #else
jjeong 0:9d06cdd73bc7 610 wait_ms(100);
jjeong 0:9d06cdd73bc7 611 #endif
jjeong 0:9d06cdd73bc7 612 }
jjeong 0:9d06cdd73bc7 613 #endif
jjeong 0:9d06cdd73bc7 614 }
jjeong 0:9d06cdd73bc7 615
jjeong 0:9d06cdd73bc7 616 ce(LOW);
jjeong 0:9d06cdd73bc7 617
jjeong 0:9d06cdd73bc7 618 uint8_t status = write_register(NRF_STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
jjeong 0:9d06cdd73bc7 619
jjeong 0:9d06cdd73bc7 620 //Max retries exceeded
jjeong 0:9d06cdd73bc7 621 if( status & _BV(MAX_RT)){
jjeong 0:9d06cdd73bc7 622 flush_tx(); //Only going to be 1 packet int the FIFO at a time using this method, so just flush
jjeong 0:9d06cdd73bc7 623 return 0;
jjeong 0:9d06cdd73bc7 624 }
jjeong 0:9d06cdd73bc7 625 //TX OK 1 or 0
jjeong 0:9d06cdd73bc7 626 return 1;
jjeong 0:9d06cdd73bc7 627 }
jjeong 0:9d06cdd73bc7 628
jjeong 0:9d06cdd73bc7 629 bool RF24::write( const void* buf, uint8_t len ){
jjeong 0:9d06cdd73bc7 630 return write(buf,len,0);
jjeong 0:9d06cdd73bc7 631 }
jjeong 0:9d06cdd73bc7 632 /****************************************************************************/
jjeong 0:9d06cdd73bc7 633
jjeong 0:9d06cdd73bc7 634 //For general use, the interrupt flags are not important to clear
jjeong 0:9d06cdd73bc7 635 bool RF24::writeBlocking( const void* buf, uint8_t len, uint32_t timeout )
jjeong 0:9d06cdd73bc7 636 {
jjeong 0:9d06cdd73bc7 637 //Block until the FIFO is NOT full.
jjeong 0:9d06cdd73bc7 638 //Keep track of the MAX retries and set auto-retry if seeing failures
jjeong 0:9d06cdd73bc7 639 //This way the FIFO will fill up and allow blocking until packets go through
jjeong 0:9d06cdd73bc7 640 //The radio will auto-clear everything in the FIFO as long as CE remains high
jjeong 0:9d06cdd73bc7 641
jjeong 0:9d06cdd73bc7 642 uint32_t timer = mainTimer.read_ms(); //Get the time that the payload transmission started
jjeong 0:9d06cdd73bc7 643
jjeong 0:9d06cdd73bc7 644 while( ( get_status() & ( _BV(TX_FULL) ))) { //Blocking only if FIFO is full. This will loop and block until TX is successful or timeout
jjeong 0:9d06cdd73bc7 645
jjeong 0:9d06cdd73bc7 646 if( get_status() & _BV(MAX_RT)){ //If MAX Retries have been reached
jjeong 0:9d06cdd73bc7 647 reUseTX(); //Set re-transmit and clear the MAX_RT interrupt flag
jjeong 0:9d06cdd73bc7 648 if(mainTimer.read_ms() - timer > timeout){ return 0; } //If this payload has exceeded the user-defined timeout, exit and return 0
jjeong 0:9d06cdd73bc7 649 }
jjeong 0:9d06cdd73bc7 650 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
jjeong 0:9d06cdd73bc7 651 if(mainTimer.read_ms() - timer > (timeout+95) ){
jjeong 0:9d06cdd73bc7 652 errNotify();
jjeong 0:9d06cdd73bc7 653 #if defined (FAILURE_HANDLING)
jjeong 0:9d06cdd73bc7 654 return 0;
jjeong 0:9d06cdd73bc7 655 #endif
jjeong 0:9d06cdd73bc7 656 }
jjeong 0:9d06cdd73bc7 657 #endif
jjeong 0:9d06cdd73bc7 658
jjeong 0:9d06cdd73bc7 659 }
jjeong 0:9d06cdd73bc7 660
jjeong 0:9d06cdd73bc7 661 //Start Writing
jjeong 0:9d06cdd73bc7 662 startFastWrite(buf,len,0); //Write the payload if a buffer is clear
jjeong 0:9d06cdd73bc7 663
jjeong 0:9d06cdd73bc7 664 return 1; //Return 1 to indicate successful transmission
jjeong 0:9d06cdd73bc7 665 }
jjeong 0:9d06cdd73bc7 666
jjeong 0:9d06cdd73bc7 667 /****************************************************************************/
jjeong 0:9d06cdd73bc7 668
jjeong 0:9d06cdd73bc7 669 void RF24::reUseTX(){
jjeong 0:9d06cdd73bc7 670 write_register(NRF_STATUS,_BV(MAX_RT) ); //Clear max retry flag
jjeong 0:9d06cdd73bc7 671 spiTrans( REUSE_TX_PL );
jjeong 0:9d06cdd73bc7 672 ce(LOW); //Re-Transfer packet
jjeong 0:9d06cdd73bc7 673 ce(HIGH);
jjeong 0:9d06cdd73bc7 674 }
jjeong 0:9d06cdd73bc7 675
jjeong 0:9d06cdd73bc7 676 /****************************************************************************/
jjeong 0:9d06cdd73bc7 677
jjeong 0:9d06cdd73bc7 678 bool RF24::writeFast( const void* buf, uint8_t len, const bool multicast )
jjeong 0:9d06cdd73bc7 679 {
jjeong 0:9d06cdd73bc7 680 //Block until the FIFO is NOT full.
jjeong 0:9d06cdd73bc7 681 //Keep track of the MAX retries and set auto-retry if seeing failures
jjeong 0:9d06cdd73bc7 682 //Return 0 so the user can control the retrys and set a timer or failure counter if required
jjeong 0:9d06cdd73bc7 683 //The radio will auto-clear everything in the FIFO as long as CE remains high
jjeong 0:9d06cdd73bc7 684
jjeong 0:9d06cdd73bc7 685 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
jjeong 0:9d06cdd73bc7 686 uint32_t timer = mainTimer.read_ms();
jjeong 0:9d06cdd73bc7 687 #endif
jjeong 0:9d06cdd73bc7 688
jjeong 0:9d06cdd73bc7 689 while( ( get_status() & ( _BV(TX_FULL) ))) { //Blocking only if FIFO is full. This will loop and block until TX is successful or fail
jjeong 0:9d06cdd73bc7 690
jjeong 0:9d06cdd73bc7 691 if( get_status() & _BV(MAX_RT)){
jjeong 0:9d06cdd73bc7 692 //reUseTX(); //Set re-transmit
jjeong 0:9d06cdd73bc7 693 write_register(NRF_STATUS,_BV(MAX_RT) ); //Clear max retry flag
jjeong 0:9d06cdd73bc7 694 return 0; //Return 0. The previous payload has been retransmitted
jjeong 0:9d06cdd73bc7 695 //From the user perspective, if you get a 0, just keep trying to send the same payload
jjeong 0:9d06cdd73bc7 696 }
jjeong 0:9d06cdd73bc7 697 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
jjeong 0:9d06cdd73bc7 698 if(mainTimer.read_ms() - timer > 95 ){
jjeong 0:9d06cdd73bc7 699 errNotify();
jjeong 0:9d06cdd73bc7 700 #if defined (FAILURE_HANDLING)
jjeong 0:9d06cdd73bc7 701 return 0;
jjeong 0:9d06cdd73bc7 702 #endif
jjeong 0:9d06cdd73bc7 703 }
jjeong 0:9d06cdd73bc7 704 #endif
jjeong 0:9d06cdd73bc7 705 }
jjeong 0:9d06cdd73bc7 706 //Start Writing
jjeong 0:9d06cdd73bc7 707 startFastWrite(buf,len,multicast);
jjeong 0:9d06cdd73bc7 708
jjeong 0:9d06cdd73bc7 709 return 1;
jjeong 0:9d06cdd73bc7 710 }
jjeong 0:9d06cdd73bc7 711
jjeong 0:9d06cdd73bc7 712 bool RF24::writeFast( const void* buf, uint8_t len ){
jjeong 0:9d06cdd73bc7 713 return writeFast(buf,len,0);
jjeong 0:9d06cdd73bc7 714 }
jjeong 0:9d06cdd73bc7 715
jjeong 0:9d06cdd73bc7 716 /****************************************************************************/
jjeong 0:9d06cdd73bc7 717
jjeong 0:9d06cdd73bc7 718 //Per the documentation, we want to set PTX Mode when not listening. Then all we do is write data and set CE high
jjeong 0:9d06cdd73bc7 719 //In this mode, if we can keep the FIFO buffers loaded, packets will transmit immediately (no 130us delay)
jjeong 0:9d06cdd73bc7 720 //Otherwise we enter Standby-II mode, which is still faster than standby mode
jjeong 0:9d06cdd73bc7 721 //Also, we remove the need to keep writing the config register over and over and delaying for 150 us each time if sending a stream of data
jjeong 0:9d06cdd73bc7 722
jjeong 0:9d06cdd73bc7 723 void RF24::startFastWrite( const void* buf, uint8_t len, const bool multicast, bool startTx){ //TMRh20
jjeong 0:9d06cdd73bc7 724
jjeong 0:9d06cdd73bc7 725 //write_payload( buf,len);
jjeong 0:9d06cdd73bc7 726 write_payload( buf, len,multicast ? W_TX_PAYLOAD_NO_ACK : W_TX_PAYLOAD ) ;
jjeong 0:9d06cdd73bc7 727 if(startTx){
jjeong 0:9d06cdd73bc7 728 ce(HIGH);
jjeong 0:9d06cdd73bc7 729 }
jjeong 0:9d06cdd73bc7 730
jjeong 0:9d06cdd73bc7 731 }
jjeong 0:9d06cdd73bc7 732
jjeong 0:9d06cdd73bc7 733 /****************************************************************************/
jjeong 0:9d06cdd73bc7 734
jjeong 0:9d06cdd73bc7 735 //Added the original startWrite back in so users can still use interrupts, ack payloads, etc
jjeong 0:9d06cdd73bc7 736 //Allows the library to pass all tests
jjeong 0:9d06cdd73bc7 737 void RF24::startWrite( const void* buf, uint8_t len, const bool multicast ){
jjeong 0:9d06cdd73bc7 738
jjeong 0:9d06cdd73bc7 739 // Send the payload
jjeong 0:9d06cdd73bc7 740
jjeong 0:9d06cdd73bc7 741 //write_payload( buf, len );
jjeong 0:9d06cdd73bc7 742 write_payload( buf, len,multicast? W_TX_PAYLOAD_NO_ACK : W_TX_PAYLOAD ) ;
jjeong 0:9d06cdd73bc7 743 ce(HIGH);
jjeong 0:9d06cdd73bc7 744
jjeong 0:9d06cdd73bc7 745 wait_us(10);
jjeong 0:9d06cdd73bc7 746
jjeong 0:9d06cdd73bc7 747 ce(LOW);
jjeong 0:9d06cdd73bc7 748
jjeong 0:9d06cdd73bc7 749
jjeong 0:9d06cdd73bc7 750 }
jjeong 0:9d06cdd73bc7 751
jjeong 0:9d06cdd73bc7 752 /****************************************************************************/
jjeong 0:9d06cdd73bc7 753
jjeong 0:9d06cdd73bc7 754 bool RF24::rxFifoFull(){
jjeong 0:9d06cdd73bc7 755 return read_register(FIFO_STATUS) & _BV(RX_FULL);
jjeong 0:9d06cdd73bc7 756 }
jjeong 0:9d06cdd73bc7 757 /****************************************************************************/
jjeong 0:9d06cdd73bc7 758
jjeong 0:9d06cdd73bc7 759 bool RF24::txStandBy(){
jjeong 0:9d06cdd73bc7 760
jjeong 0:9d06cdd73bc7 761 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
jjeong 0:9d06cdd73bc7 762 uint32_t timeout = mainTimer.read_ms();
jjeong 0:9d06cdd73bc7 763 #endif
jjeong 0:9d06cdd73bc7 764 while( ! (read_register(FIFO_STATUS) & _BV(TX_EMPTY)) ){
jjeong 0:9d06cdd73bc7 765 if( get_status() & _BV(MAX_RT)){
jjeong 0:9d06cdd73bc7 766 write_register(NRF_STATUS,_BV(MAX_RT) );
jjeong 0:9d06cdd73bc7 767 ce(LOW);
jjeong 0:9d06cdd73bc7 768 flush_tx(); //Non blocking, flush the data
jjeong 0:9d06cdd73bc7 769 return 0;
jjeong 0:9d06cdd73bc7 770 }
jjeong 0:9d06cdd73bc7 771 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
jjeong 0:9d06cdd73bc7 772 if( mainTimer.read_ms() - timeout > 95){
jjeong 0:9d06cdd73bc7 773 errNotify();
jjeong 0:9d06cdd73bc7 774 #if defined (FAILURE_HANDLING)
jjeong 0:9d06cdd73bc7 775 return 0;
jjeong 0:9d06cdd73bc7 776 #endif
jjeong 0:9d06cdd73bc7 777 }
jjeong 0:9d06cdd73bc7 778 #endif
jjeong 0:9d06cdd73bc7 779 }
jjeong 0:9d06cdd73bc7 780
jjeong 0:9d06cdd73bc7 781 ce(LOW); //Set STANDBY-I mode
jjeong 0:9d06cdd73bc7 782 return 1;
jjeong 0:9d06cdd73bc7 783 }
jjeong 0:9d06cdd73bc7 784
jjeong 0:9d06cdd73bc7 785 /****************************************************************************/
jjeong 0:9d06cdd73bc7 786
jjeong 0:9d06cdd73bc7 787 bool RF24::txStandBy(uint32_t timeout, bool startTx){
jjeong 0:9d06cdd73bc7 788
jjeong 0:9d06cdd73bc7 789 if(startTx){
jjeong 0:9d06cdd73bc7 790 stopListening();
jjeong 0:9d06cdd73bc7 791 ce(HIGH);
jjeong 0:9d06cdd73bc7 792 }
jjeong 0:9d06cdd73bc7 793 uint32_t start = mainTimer.read_ms();
jjeong 0:9d06cdd73bc7 794
jjeong 0:9d06cdd73bc7 795 while( ! (read_register(FIFO_STATUS) & _BV(TX_EMPTY)) ){
jjeong 0:9d06cdd73bc7 796 if( get_status() & _BV(MAX_RT)){
jjeong 0:9d06cdd73bc7 797 write_register(NRF_STATUS,_BV(MAX_RT) );
jjeong 0:9d06cdd73bc7 798 ce(LOW); //Set re-transmit
jjeong 0:9d06cdd73bc7 799 ce(HIGH);
jjeong 0:9d06cdd73bc7 800 if(mainTimer.read_ms() - start >= timeout){
jjeong 0:9d06cdd73bc7 801 ce(LOW); flush_tx(); return 0;
jjeong 0:9d06cdd73bc7 802 }
jjeong 0:9d06cdd73bc7 803 }
jjeong 0:9d06cdd73bc7 804 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
jjeong 0:9d06cdd73bc7 805 if( mainTimer.read_ms() - start > (timeout+95)){
jjeong 0:9d06cdd73bc7 806 errNotify();
jjeong 0:9d06cdd73bc7 807 #if defined (FAILURE_HANDLING)
jjeong 0:9d06cdd73bc7 808 return 0;
jjeong 0:9d06cdd73bc7 809 #endif
jjeong 0:9d06cdd73bc7 810 }
jjeong 0:9d06cdd73bc7 811 #endif
jjeong 0:9d06cdd73bc7 812 }
jjeong 0:9d06cdd73bc7 813
jjeong 0:9d06cdd73bc7 814
jjeong 0:9d06cdd73bc7 815 ce(LOW); //Set STANDBY-I mode
jjeong 0:9d06cdd73bc7 816 return 1;
jjeong 0:9d06cdd73bc7 817
jjeong 0:9d06cdd73bc7 818 }
jjeong 0:9d06cdd73bc7 819
jjeong 0:9d06cdd73bc7 820 /****************************************************************************/
jjeong 0:9d06cdd73bc7 821
jjeong 0:9d06cdd73bc7 822 void RF24::maskIRQ(bool tx, bool fail, bool rx){
jjeong 0:9d06cdd73bc7 823
jjeong 0:9d06cdd73bc7 824 uint8_t config = read_register(NRF_CONFIG);
jjeong 0:9d06cdd73bc7 825 /* clear the interrupt flags */
jjeong 0:9d06cdd73bc7 826 config &= ~(1 << MASK_MAX_RT | 1 << MASK_TX_DS | 1 << MASK_RX_DR);
jjeong 0:9d06cdd73bc7 827 /* set the specified interrupt flags */
jjeong 0:9d06cdd73bc7 828 config |= fail << MASK_MAX_RT | tx << MASK_TX_DS | rx << MASK_RX_DR;
jjeong 0:9d06cdd73bc7 829 write_register(NRF_CONFIG, config);
jjeong 0:9d06cdd73bc7 830 }
jjeong 0:9d06cdd73bc7 831
jjeong 0:9d06cdd73bc7 832 /****************************************************************************/
jjeong 0:9d06cdd73bc7 833
jjeong 0:9d06cdd73bc7 834 uint8_t RF24::getDynamicPayloadSize(void)
jjeong 0:9d06cdd73bc7 835 {
jjeong 0:9d06cdd73bc7 836 uint8_t result = 0;
jjeong 0:9d06cdd73bc7 837
jjeong 0:9d06cdd73bc7 838
jjeong 0:9d06cdd73bc7 839 beginTransaction();
jjeong 0:9d06cdd73bc7 840 spi.write( R_RX_PL_WID );
jjeong 0:9d06cdd73bc7 841 result = spi.write(0xff);
jjeong 0:9d06cdd73bc7 842 endTransaction();
jjeong 0:9d06cdd73bc7 843
jjeong 0:9d06cdd73bc7 844
jjeong 0:9d06cdd73bc7 845 if(result > 32) { flush_rx(); wait_ms(2); return 0; }
jjeong 0:9d06cdd73bc7 846 return result;
jjeong 0:9d06cdd73bc7 847 }
jjeong 0:9d06cdd73bc7 848
jjeong 0:9d06cdd73bc7 849 /****************************************************************************/
jjeong 0:9d06cdd73bc7 850
jjeong 0:9d06cdd73bc7 851 bool RF24::available(void)
jjeong 0:9d06cdd73bc7 852 {
jjeong 0:9d06cdd73bc7 853 return available(NULL);
jjeong 0:9d06cdd73bc7 854 }
jjeong 0:9d06cdd73bc7 855
jjeong 0:9d06cdd73bc7 856 /****************************************************************************/
jjeong 0:9d06cdd73bc7 857
jjeong 0:9d06cdd73bc7 858 bool RF24::available(uint8_t* pipe_num)
jjeong 0:9d06cdd73bc7 859 {
jjeong 0:9d06cdd73bc7 860 if (!( read_register(FIFO_STATUS) & _BV(RX_EMPTY) )){
jjeong 0:9d06cdd73bc7 861
jjeong 0:9d06cdd73bc7 862 // If the caller wants the pipe number, include that
jjeong 0:9d06cdd73bc7 863 if ( pipe_num ){
jjeong 0:9d06cdd73bc7 864 uint8_t status = get_status();
jjeong 0:9d06cdd73bc7 865 *pipe_num = ( status >> RX_P_NO ) & 0b111;
jjeong 0:9d06cdd73bc7 866 }
jjeong 0:9d06cdd73bc7 867 return 1;
jjeong 0:9d06cdd73bc7 868 }
jjeong 0:9d06cdd73bc7 869
jjeong 0:9d06cdd73bc7 870
jjeong 0:9d06cdd73bc7 871 return 0;
jjeong 0:9d06cdd73bc7 872
jjeong 0:9d06cdd73bc7 873
jjeong 0:9d06cdd73bc7 874 }
jjeong 0:9d06cdd73bc7 875
jjeong 0:9d06cdd73bc7 876 /****************************************************************************/
jjeong 0:9d06cdd73bc7 877
jjeong 0:9d06cdd73bc7 878 void RF24::read( void* buf, uint8_t len ){
jjeong 0:9d06cdd73bc7 879
jjeong 0:9d06cdd73bc7 880 // Fetch the payload
jjeong 0:9d06cdd73bc7 881 read_payload( buf, len );
jjeong 0:9d06cdd73bc7 882
jjeong 0:9d06cdd73bc7 883 //Clear the two possible interrupt flags with one command
jjeong 0:9d06cdd73bc7 884 write_register(NRF_STATUS,_BV(RX_DR) | _BV(MAX_RT) | _BV(TX_DS) );
jjeong 0:9d06cdd73bc7 885
jjeong 0:9d06cdd73bc7 886 }
jjeong 0:9d06cdd73bc7 887
jjeong 0:9d06cdd73bc7 888 /****************************************************************************/
jjeong 0:9d06cdd73bc7 889
jjeong 0:9d06cdd73bc7 890 void RF24::whatHappened(bool& tx_ok,bool& tx_fail,bool& rx_ready)
jjeong 0:9d06cdd73bc7 891 {
jjeong 0:9d06cdd73bc7 892 // Read the status & reset the status in one easy call
jjeong 0:9d06cdd73bc7 893 // Or is that such a good idea?
jjeong 0:9d06cdd73bc7 894 uint8_t status = write_register(NRF_STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
jjeong 0:9d06cdd73bc7 895
jjeong 0:9d06cdd73bc7 896 // Report to the user what happened
jjeong 0:9d06cdd73bc7 897 tx_ok = status & _BV(TX_DS);
jjeong 0:9d06cdd73bc7 898 tx_fail = status & _BV(MAX_RT);
jjeong 0:9d06cdd73bc7 899 rx_ready = status & _BV(RX_DR);
jjeong 0:9d06cdd73bc7 900 }
jjeong 0:9d06cdd73bc7 901
jjeong 0:9d06cdd73bc7 902 /****************************************************************************/
jjeong 0:9d06cdd73bc7 903
jjeong 0:9d06cdd73bc7 904 void RF24::openWritingPipe(uint64_t value)
jjeong 0:9d06cdd73bc7 905 {
jjeong 0:9d06cdd73bc7 906 // Note that AVR 8-bit uC's store this LSB first, and the NRF24L01(+)
jjeong 0:9d06cdd73bc7 907 // expects it LSB first too, so we're good.
jjeong 0:9d06cdd73bc7 908
jjeong 0:9d06cdd73bc7 909 write_register(RX_ADDR_P0, reinterpret_cast<uint8_t*>(&value), addr_width);
jjeong 0:9d06cdd73bc7 910 write_register(TX_ADDR, reinterpret_cast<uint8_t*>(&value), addr_width);
jjeong 0:9d06cdd73bc7 911
jjeong 0:9d06cdd73bc7 912
jjeong 0:9d06cdd73bc7 913 //const uint8_t max_payload_size = 32;
jjeong 0:9d06cdd73bc7 914 //write_register(RX_PW_P0,rf24_min(payload_size,max_payload_size));
jjeong 0:9d06cdd73bc7 915 write_register(RX_PW_P0,payload_size);
jjeong 0:9d06cdd73bc7 916 }
jjeong 0:9d06cdd73bc7 917
jjeong 0:9d06cdd73bc7 918 /****************************************************************************/
jjeong 0:9d06cdd73bc7 919 void RF24::openWritingPipe(const uint8_t *address)
jjeong 0:9d06cdd73bc7 920 {
jjeong 0:9d06cdd73bc7 921 // Note that AVR 8-bit uC's store this LSB first, and the NRF24L01(+)
jjeong 0:9d06cdd73bc7 922 // expects it LSB first too, so we're good.
jjeong 0:9d06cdd73bc7 923
jjeong 0:9d06cdd73bc7 924 write_register(RX_ADDR_P0,address, addr_width);
jjeong 0:9d06cdd73bc7 925 write_register(TX_ADDR, address, addr_width);
jjeong 0:9d06cdd73bc7 926
jjeong 0:9d06cdd73bc7 927 //const uint8_t max_payload_size = 32;
jjeong 0:9d06cdd73bc7 928 //write_register(RX_PW_P0,rf24_min(payload_size,max_payload_size));
jjeong 0:9d06cdd73bc7 929 write_register(RX_PW_P0,payload_size);
jjeong 0:9d06cdd73bc7 930 }
jjeong 0:9d06cdd73bc7 931
jjeong 0:9d06cdd73bc7 932 /****************************************************************************/
jjeong 0:9d06cdd73bc7 933 static const uint8_t child_pipe[] PROGMEM =
jjeong 0:9d06cdd73bc7 934 {
jjeong 0:9d06cdd73bc7 935 RX_ADDR_P0, RX_ADDR_P1, RX_ADDR_P2, RX_ADDR_P3, RX_ADDR_P4, RX_ADDR_P5
jjeong 0:9d06cdd73bc7 936 };
jjeong 0:9d06cdd73bc7 937 static const uint8_t child_payload_size[] PROGMEM =
jjeong 0:9d06cdd73bc7 938 {
jjeong 0:9d06cdd73bc7 939 RX_PW_P0, RX_PW_P1, RX_PW_P2, RX_PW_P3, RX_PW_P4, RX_PW_P5
jjeong 0:9d06cdd73bc7 940 };
jjeong 0:9d06cdd73bc7 941
jjeong 0:9d06cdd73bc7 942
jjeong 0:9d06cdd73bc7 943 void RF24::openReadingPipe(uint8_t child, uint64_t address)
jjeong 0:9d06cdd73bc7 944 {
jjeong 0:9d06cdd73bc7 945 // If this is pipe 0, cache the address. This is needed because
jjeong 0:9d06cdd73bc7 946 // openWritingPipe() will overwrite the pipe 0 address, so
jjeong 0:9d06cdd73bc7 947 // startListening() will have to restore it.
jjeong 0:9d06cdd73bc7 948 if (child == 0){
jjeong 0:9d06cdd73bc7 949 memcpy(pipe0_reading_address,&address,addr_width);
jjeong 0:9d06cdd73bc7 950 }
jjeong 0:9d06cdd73bc7 951
jjeong 0:9d06cdd73bc7 952 if (child <= 6)
jjeong 0:9d06cdd73bc7 953 {
jjeong 0:9d06cdd73bc7 954 // For pipes 2-5, only write the LSB
jjeong 0:9d06cdd73bc7 955 if ( child < 2 )
jjeong 0:9d06cdd73bc7 956 write_register(pgm_read_byte(&child_pipe[child]), reinterpret_cast<const uint8_t*>(&address), addr_width);
jjeong 0:9d06cdd73bc7 957 else
jjeong 0:9d06cdd73bc7 958 write_register(pgm_read_byte(&child_pipe[child]), reinterpret_cast<const uint8_t*>(&address), 1);
jjeong 0:9d06cdd73bc7 959
jjeong 0:9d06cdd73bc7 960 write_register(pgm_read_byte(&child_payload_size[child]),payload_size);
jjeong 0:9d06cdd73bc7 961
jjeong 0:9d06cdd73bc7 962 // Note it would be more efficient to set all of the bits for all open
jjeong 0:9d06cdd73bc7 963 // pipes at once. However, I thought it would make the calling code
jjeong 0:9d06cdd73bc7 964 // more simple to do it this way.
jjeong 0:9d06cdd73bc7 965 write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[child])));
jjeong 0:9d06cdd73bc7 966 }
jjeong 0:9d06cdd73bc7 967 }
jjeong 0:9d06cdd73bc7 968
jjeong 0:9d06cdd73bc7 969 /****************************************************************************/
jjeong 0:9d06cdd73bc7 970 void RF24::setAddressWidth(uint8_t a_width){
jjeong 0:9d06cdd73bc7 971
jjeong 0:9d06cdd73bc7 972 if(a_width -= 2){
jjeong 0:9d06cdd73bc7 973 write_register(SETUP_AW,a_width%4);
jjeong 0:9d06cdd73bc7 974 addr_width = (a_width%4) + 2;
jjeong 0:9d06cdd73bc7 975 }
jjeong 0:9d06cdd73bc7 976
jjeong 0:9d06cdd73bc7 977 }
jjeong 0:9d06cdd73bc7 978
jjeong 0:9d06cdd73bc7 979 /****************************************************************************/
jjeong 0:9d06cdd73bc7 980
jjeong 0:9d06cdd73bc7 981 void RF24::openReadingPipe(uint8_t child, const uint8_t *address)
jjeong 0:9d06cdd73bc7 982 {
jjeong 0:9d06cdd73bc7 983 // If this is pipe 0, cache the address. This is needed because
jjeong 0:9d06cdd73bc7 984 // openWritingPipe() will overwrite the pipe 0 address, so
jjeong 0:9d06cdd73bc7 985 // startListening() will have to restore it.
jjeong 0:9d06cdd73bc7 986 if (child == 0){
jjeong 0:9d06cdd73bc7 987 memcpy(pipe0_reading_address,address,addr_width);
jjeong 0:9d06cdd73bc7 988 }
jjeong 0:9d06cdd73bc7 989 if (child <= 6)
jjeong 0:9d06cdd73bc7 990 {
jjeong 0:9d06cdd73bc7 991 // For pipes 2-5, only write the LSB
jjeong 0:9d06cdd73bc7 992 if ( child < 2 ){
jjeong 0:9d06cdd73bc7 993 write_register(pgm_read_byte(&child_pipe[child]), address, addr_width);
jjeong 0:9d06cdd73bc7 994 }else{
jjeong 0:9d06cdd73bc7 995 write_register(pgm_read_byte(&child_pipe[child]), address, 1);
jjeong 0:9d06cdd73bc7 996 }
jjeong 0:9d06cdd73bc7 997 write_register(pgm_read_byte(&child_payload_size[child]),payload_size);
jjeong 0:9d06cdd73bc7 998
jjeong 0:9d06cdd73bc7 999 // Note it would be more efficient to set all of the bits for all open
jjeong 0:9d06cdd73bc7 1000 // pipes at once. However, I thought it would make the calling code
jjeong 0:9d06cdd73bc7 1001 // more simple to do it this way.
jjeong 0:9d06cdd73bc7 1002 write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[child])));
jjeong 0:9d06cdd73bc7 1003
jjeong 0:9d06cdd73bc7 1004 }
jjeong 0:9d06cdd73bc7 1005 }
jjeong 0:9d06cdd73bc7 1006
jjeong 0:9d06cdd73bc7 1007 /****************************************************************************/
jjeong 0:9d06cdd73bc7 1008
jjeong 0:9d06cdd73bc7 1009 void RF24::closeReadingPipe( uint8_t pipe )
jjeong 0:9d06cdd73bc7 1010 {
jjeong 0:9d06cdd73bc7 1011 write_register(EN_RXADDR,read_register(EN_RXADDR) & ~_BV(pgm_read_byte(&child_pipe_enable[pipe])));
jjeong 0:9d06cdd73bc7 1012 }
jjeong 0:9d06cdd73bc7 1013
jjeong 0:9d06cdd73bc7 1014 /****************************************************************************/
jjeong 0:9d06cdd73bc7 1015
jjeong 0:9d06cdd73bc7 1016 void RF24::toggle_features(void)
jjeong 0:9d06cdd73bc7 1017 {
jjeong 0:9d06cdd73bc7 1018 beginTransaction();
jjeong 0:9d06cdd73bc7 1019 spi.write( ACTIVATE );
jjeong 0:9d06cdd73bc7 1020 spi.write( 0x73 );
jjeong 0:9d06cdd73bc7 1021 endTransaction();
jjeong 0:9d06cdd73bc7 1022 }
jjeong 0:9d06cdd73bc7 1023
jjeong 0:9d06cdd73bc7 1024 /****************************************************************************/
jjeong 0:9d06cdd73bc7 1025
jjeong 0:9d06cdd73bc7 1026 void RF24::enableDynamicPayloads(void)
jjeong 0:9d06cdd73bc7 1027 {
jjeong 0:9d06cdd73bc7 1028 // Enable dynamic payload throughout the system
jjeong 0:9d06cdd73bc7 1029
jjeong 0:9d06cdd73bc7 1030 //toggle_features();
jjeong 0:9d06cdd73bc7 1031 write_register(FEATURE,read_register(FEATURE) | _BV(EN_DPL) );
jjeong 0:9d06cdd73bc7 1032
jjeong 0:9d06cdd73bc7 1033
jjeong 0:9d06cdd73bc7 1034 IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE)));
jjeong 0:9d06cdd73bc7 1035
jjeong 0:9d06cdd73bc7 1036 // Enable dynamic payload on all pipes
jjeong 0:9d06cdd73bc7 1037 //
jjeong 0:9d06cdd73bc7 1038 // Not sure the use case of only having dynamic payload on certain
jjeong 0:9d06cdd73bc7 1039 // pipes, so the library does not support it.
jjeong 0:9d06cdd73bc7 1040 write_register(DYNPD,read_register(DYNPD) | _BV(DPL_P5) | _BV(DPL_P4) | _BV(DPL_P3) | _BV(DPL_P2) | _BV(DPL_P1) | _BV(DPL_P0));
jjeong 0:9d06cdd73bc7 1041
jjeong 0:9d06cdd73bc7 1042 dynamic_payloads_enabled = true;
jjeong 0:9d06cdd73bc7 1043 }
jjeong 0:9d06cdd73bc7 1044
jjeong 0:9d06cdd73bc7 1045 /****************************************************************************/
jjeong 0:9d06cdd73bc7 1046
jjeong 0:9d06cdd73bc7 1047 void RF24::enableAckPayload(void)
jjeong 0:9d06cdd73bc7 1048 {
jjeong 0:9d06cdd73bc7 1049 //
jjeong 0:9d06cdd73bc7 1050 // enable ack payload and dynamic payload features
jjeong 0:9d06cdd73bc7 1051 //
jjeong 0:9d06cdd73bc7 1052
jjeong 0:9d06cdd73bc7 1053 //toggle_features();
jjeong 0:9d06cdd73bc7 1054 write_register(FEATURE,read_register(FEATURE) | _BV(EN_ACK_PAY) | _BV(EN_DPL) );
jjeong 0:9d06cdd73bc7 1055
jjeong 0:9d06cdd73bc7 1056 IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE)));
jjeong 0:9d06cdd73bc7 1057
jjeong 0:9d06cdd73bc7 1058 //
jjeong 0:9d06cdd73bc7 1059 // Enable dynamic payload on pipes 0 & 1
jjeong 0:9d06cdd73bc7 1060 //
jjeong 0:9d06cdd73bc7 1061
jjeong 0:9d06cdd73bc7 1062 write_register(DYNPD,read_register(DYNPD) | _BV(DPL_P1) | _BV(DPL_P0));
jjeong 0:9d06cdd73bc7 1063 dynamic_payloads_enabled = true;
jjeong 0:9d06cdd73bc7 1064 }
jjeong 0:9d06cdd73bc7 1065
jjeong 0:9d06cdd73bc7 1066 /****************************************************************************/
jjeong 0:9d06cdd73bc7 1067
jjeong 0:9d06cdd73bc7 1068 void RF24::enableDynamicAck(void){
jjeong 0:9d06cdd73bc7 1069 //
jjeong 0:9d06cdd73bc7 1070 // enable dynamic ack features
jjeong 0:9d06cdd73bc7 1071 //
jjeong 0:9d06cdd73bc7 1072 //toggle_features();
jjeong 0:9d06cdd73bc7 1073 write_register(FEATURE,read_register(FEATURE) | _BV(EN_DYN_ACK) );
jjeong 0:9d06cdd73bc7 1074
jjeong 0:9d06cdd73bc7 1075 IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE)));
jjeong 0:9d06cdd73bc7 1076
jjeong 0:9d06cdd73bc7 1077
jjeong 0:9d06cdd73bc7 1078 }
jjeong 0:9d06cdd73bc7 1079
jjeong 0:9d06cdd73bc7 1080 /****************************************************************************/
jjeong 0:9d06cdd73bc7 1081
jjeong 0:9d06cdd73bc7 1082 void RF24::writeAckPayload(uint8_t pipe, const void* buf, uint8_t len)
jjeong 0:9d06cdd73bc7 1083 {
jjeong 0:9d06cdd73bc7 1084 const uint8_t* current = reinterpret_cast<const uint8_t*>(buf);
jjeong 0:9d06cdd73bc7 1085
jjeong 0:9d06cdd73bc7 1086 uint8_t data_len = rf24_min(len,32);
jjeong 0:9d06cdd73bc7 1087
jjeong 0:9d06cdd73bc7 1088
jjeong 0:9d06cdd73bc7 1089
jjeong 0:9d06cdd73bc7 1090 beginTransaction();
jjeong 0:9d06cdd73bc7 1091 spi.write(W_ACK_PAYLOAD | ( pipe & 0b111 ) );
jjeong 0:9d06cdd73bc7 1092
jjeong 0:9d06cdd73bc7 1093 while ( data_len-- )
jjeong 0:9d06cdd73bc7 1094 spi.write(*current++);
jjeong 0:9d06cdd73bc7 1095 endTransaction();
jjeong 0:9d06cdd73bc7 1096
jjeong 0:9d06cdd73bc7 1097
jjeong 0:9d06cdd73bc7 1098
jjeong 0:9d06cdd73bc7 1099 }
jjeong 0:9d06cdd73bc7 1100
jjeong 0:9d06cdd73bc7 1101 /****************************************************************************/
jjeong 0:9d06cdd73bc7 1102
jjeong 0:9d06cdd73bc7 1103 bool RF24::isAckPayloadAvailable(void)
jjeong 0:9d06cdd73bc7 1104 {
jjeong 0:9d06cdd73bc7 1105 return ! (read_register(FIFO_STATUS) & _BV(RX_EMPTY));
jjeong 0:9d06cdd73bc7 1106 }
jjeong 0:9d06cdd73bc7 1107
jjeong 0:9d06cdd73bc7 1108 /****************************************************************************/
jjeong 0:9d06cdd73bc7 1109
jjeong 0:9d06cdd73bc7 1110 bool RF24::isPVariant(void)
jjeong 0:9d06cdd73bc7 1111 {
jjeong 0:9d06cdd73bc7 1112 return p_variant ;
jjeong 0:9d06cdd73bc7 1113 }
jjeong 0:9d06cdd73bc7 1114
jjeong 0:9d06cdd73bc7 1115 /****************************************************************************/
jjeong 0:9d06cdd73bc7 1116
jjeong 0:9d06cdd73bc7 1117 void RF24::setAutoAck(bool enable)
jjeong 0:9d06cdd73bc7 1118 {
jjeong 0:9d06cdd73bc7 1119 if ( enable )
jjeong 0:9d06cdd73bc7 1120 write_register(EN_AA, 0b111111);
jjeong 0:9d06cdd73bc7 1121 else
jjeong 0:9d06cdd73bc7 1122 write_register(EN_AA, 0);
jjeong 0:9d06cdd73bc7 1123 }
jjeong 0:9d06cdd73bc7 1124
jjeong 0:9d06cdd73bc7 1125 /****************************************************************************/
jjeong 0:9d06cdd73bc7 1126
jjeong 0:9d06cdd73bc7 1127 void RF24::setAutoAck( uint8_t pipe, bool enable )
jjeong 0:9d06cdd73bc7 1128 {
jjeong 0:9d06cdd73bc7 1129 if ( pipe <= 6 )
jjeong 0:9d06cdd73bc7 1130 {
jjeong 0:9d06cdd73bc7 1131 uint8_t en_aa = read_register( EN_AA ) ;
jjeong 0:9d06cdd73bc7 1132 if( enable )
jjeong 0:9d06cdd73bc7 1133 {
jjeong 0:9d06cdd73bc7 1134 en_aa |= _BV(pipe) ;
jjeong 0:9d06cdd73bc7 1135 }
jjeong 0:9d06cdd73bc7 1136 else
jjeong 0:9d06cdd73bc7 1137 {
jjeong 0:9d06cdd73bc7 1138 en_aa &= ~_BV(pipe) ;
jjeong 0:9d06cdd73bc7 1139 }
jjeong 0:9d06cdd73bc7 1140 write_register( EN_AA, en_aa ) ;
jjeong 0:9d06cdd73bc7 1141 }
jjeong 0:9d06cdd73bc7 1142 }
jjeong 0:9d06cdd73bc7 1143
jjeong 0:9d06cdd73bc7 1144 /****************************************************************************/
jjeong 0:9d06cdd73bc7 1145
jjeong 0:9d06cdd73bc7 1146 bool RF24::testCarrier(void)
jjeong 0:9d06cdd73bc7 1147 {
jjeong 0:9d06cdd73bc7 1148 return ( read_register(CD) & 1 );
jjeong 0:9d06cdd73bc7 1149 }
jjeong 0:9d06cdd73bc7 1150
jjeong 0:9d06cdd73bc7 1151 /****************************************************************************/
jjeong 0:9d06cdd73bc7 1152
jjeong 0:9d06cdd73bc7 1153 bool RF24::testRPD(void)
jjeong 0:9d06cdd73bc7 1154 {
jjeong 0:9d06cdd73bc7 1155 return ( read_register(RPD) & 1 ) ;
jjeong 0:9d06cdd73bc7 1156 }
jjeong 0:9d06cdd73bc7 1157
jjeong 0:9d06cdd73bc7 1158 /****************************************************************************/
jjeong 0:9d06cdd73bc7 1159
jjeong 0:9d06cdd73bc7 1160 void RF24::setPALevel(uint8_t level)
jjeong 0:9d06cdd73bc7 1161 {
jjeong 0:9d06cdd73bc7 1162
jjeong 0:9d06cdd73bc7 1163 uint8_t setup = read_register(RF_SETUP) & 0b11111000;
jjeong 0:9d06cdd73bc7 1164
jjeong 0:9d06cdd73bc7 1165 if(level > 3){ // If invalid level, go to max PA
jjeong 0:9d06cdd73bc7 1166 level = (RF24_PA_MAX << 1) + 1; // +1 to support the SI24R1 chip extra bit
jjeong 0:9d06cdd73bc7 1167 }else{
jjeong 0:9d06cdd73bc7 1168 level = (level << 1) + 1; // Else set level as requested
jjeong 0:9d06cdd73bc7 1169 }
jjeong 0:9d06cdd73bc7 1170
jjeong 0:9d06cdd73bc7 1171
jjeong 0:9d06cdd73bc7 1172 write_register( RF_SETUP, setup |= level ) ; // Write it to the chip
jjeong 0:9d06cdd73bc7 1173 }
jjeong 0:9d06cdd73bc7 1174
jjeong 0:9d06cdd73bc7 1175 /****************************************************************************/
jjeong 0:9d06cdd73bc7 1176
jjeong 0:9d06cdd73bc7 1177 uint8_t RF24::getPALevel(void)
jjeong 0:9d06cdd73bc7 1178 {
jjeong 0:9d06cdd73bc7 1179
jjeong 0:9d06cdd73bc7 1180 return (read_register(RF_SETUP) & (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH))) >> 1 ;
jjeong 0:9d06cdd73bc7 1181 }
jjeong 0:9d06cdd73bc7 1182
jjeong 0:9d06cdd73bc7 1183 /****************************************************************************/
jjeong 0:9d06cdd73bc7 1184
jjeong 0:9d06cdd73bc7 1185 bool RF24::setDataRate(rf24_datarate_e speed)
jjeong 0:9d06cdd73bc7 1186 {
jjeong 0:9d06cdd73bc7 1187 bool result = false;
jjeong 0:9d06cdd73bc7 1188 uint8_t setup = read_register(RF_SETUP) ;
jjeong 0:9d06cdd73bc7 1189
jjeong 0:9d06cdd73bc7 1190 // HIGH and LOW '00' is 1Mbs - our default
jjeong 0:9d06cdd73bc7 1191 setup &= ~(_BV(RF_DR_LOW) | _BV(RF_DR_HIGH)) ;
jjeong 0:9d06cdd73bc7 1192
jjeong 0:9d06cdd73bc7 1193
jjeong 0:9d06cdd73bc7 1194
jjeong 0:9d06cdd73bc7 1195
jjeong 0:9d06cdd73bc7 1196 txRxDelay=85;
jjeong 0:9d06cdd73bc7 1197
jjeong 0:9d06cdd73bc7 1198 if( speed == RF24_250KBPS )
jjeong 0:9d06cdd73bc7 1199 {
jjeong 0:9d06cdd73bc7 1200 // Must set the RF_DR_LOW to 1; RF_DR_HIGH (used to be RF_DR) is already 0
jjeong 0:9d06cdd73bc7 1201 // Making it '10'.
jjeong 0:9d06cdd73bc7 1202 setup |= _BV( RF_DR_LOW ) ;
jjeong 0:9d06cdd73bc7 1203
jjeong 0:9d06cdd73bc7 1204
jjeong 0:9d06cdd73bc7 1205
jjeong 0:9d06cdd73bc7 1206 txRxDelay=155;
jjeong 0:9d06cdd73bc7 1207
jjeong 0:9d06cdd73bc7 1208 }
jjeong 0:9d06cdd73bc7 1209 else
jjeong 0:9d06cdd73bc7 1210 {
jjeong 0:9d06cdd73bc7 1211 // Set 2Mbs, RF_DR (RF_DR_HIGH) is set 1
jjeong 0:9d06cdd73bc7 1212 // Making it '01'
jjeong 0:9d06cdd73bc7 1213 if ( speed == RF24_2MBPS )
jjeong 0:9d06cdd73bc7 1214 {
jjeong 0:9d06cdd73bc7 1215 setup |= _BV(RF_DR_HIGH);
jjeong 0:9d06cdd73bc7 1216
jjeong 0:9d06cdd73bc7 1217
jjeong 0:9d06cdd73bc7 1218 //txRxDelay=65;
jjeong 0:9d06cdd73bc7 1219 txRxDelay=15; //mbed works fine with this latency
jjeong 0:9d06cdd73bc7 1220
jjeong 0:9d06cdd73bc7 1221 }
jjeong 0:9d06cdd73bc7 1222 }
jjeong 0:9d06cdd73bc7 1223 write_register(RF_SETUP,setup);
jjeong 0:9d06cdd73bc7 1224
jjeong 0:9d06cdd73bc7 1225 // Verify our result
jjeong 0:9d06cdd73bc7 1226 if ( read_register(RF_SETUP) == setup )
jjeong 0:9d06cdd73bc7 1227 {
jjeong 0:9d06cdd73bc7 1228 result = true;
jjeong 0:9d06cdd73bc7 1229 }
jjeong 0:9d06cdd73bc7 1230 return result;
jjeong 0:9d06cdd73bc7 1231 }
jjeong 0:9d06cdd73bc7 1232
jjeong 0:9d06cdd73bc7 1233 /****************************************************************************/
jjeong 0:9d06cdd73bc7 1234
jjeong 0:9d06cdd73bc7 1235 rf24_datarate_e RF24::getDataRate( void )
jjeong 0:9d06cdd73bc7 1236 {
jjeong 0:9d06cdd73bc7 1237 rf24_datarate_e result ;
jjeong 0:9d06cdd73bc7 1238 uint8_t dr = read_register(RF_SETUP) & (_BV(RF_DR_LOW) | _BV(RF_DR_HIGH));
jjeong 0:9d06cdd73bc7 1239
jjeong 0:9d06cdd73bc7 1240 // switch uses RAM (evil!)
jjeong 0:9d06cdd73bc7 1241 // Order matters in our case below
jjeong 0:9d06cdd73bc7 1242 if ( dr == _BV(RF_DR_LOW) )
jjeong 0:9d06cdd73bc7 1243 {
jjeong 0:9d06cdd73bc7 1244 // '10' = 250KBPS
jjeong 0:9d06cdd73bc7 1245 result = RF24_250KBPS ;
jjeong 0:9d06cdd73bc7 1246 }
jjeong 0:9d06cdd73bc7 1247 else if ( dr == _BV(RF_DR_HIGH) )
jjeong 0:9d06cdd73bc7 1248 {
jjeong 0:9d06cdd73bc7 1249 // '01' = 2MBPS
jjeong 0:9d06cdd73bc7 1250 result = RF24_2MBPS ;
jjeong 0:9d06cdd73bc7 1251 }
jjeong 0:9d06cdd73bc7 1252 else
jjeong 0:9d06cdd73bc7 1253 {
jjeong 0:9d06cdd73bc7 1254 // '00' = 1MBPS
jjeong 0:9d06cdd73bc7 1255 result = RF24_1MBPS ;
jjeong 0:9d06cdd73bc7 1256 }
jjeong 0:9d06cdd73bc7 1257 return result ;
jjeong 0:9d06cdd73bc7 1258 }
jjeong 0:9d06cdd73bc7 1259
jjeong 0:9d06cdd73bc7 1260 /****************************************************************************/
jjeong 0:9d06cdd73bc7 1261
jjeong 0:9d06cdd73bc7 1262 void RF24::setCRCLength(rf24_crclength_e length)
jjeong 0:9d06cdd73bc7 1263 {
jjeong 0:9d06cdd73bc7 1264 uint8_t config = read_register(NRF_CONFIG) & ~( _BV(CRCO) | _BV(EN_CRC)) ;
jjeong 0:9d06cdd73bc7 1265
jjeong 0:9d06cdd73bc7 1266 // switch uses RAM (evil!)
jjeong 0:9d06cdd73bc7 1267 if ( length == RF24_CRC_DISABLED )
jjeong 0:9d06cdd73bc7 1268 {
jjeong 0:9d06cdd73bc7 1269 // Do nothing, we turned it off above.
jjeong 0:9d06cdd73bc7 1270 }
jjeong 0:9d06cdd73bc7 1271 else if ( length == RF24_CRC_8 )
jjeong 0:9d06cdd73bc7 1272 {
jjeong 0:9d06cdd73bc7 1273 config |= _BV(EN_CRC);
jjeong 0:9d06cdd73bc7 1274 }
jjeong 0:9d06cdd73bc7 1275 else
jjeong 0:9d06cdd73bc7 1276 {
jjeong 0:9d06cdd73bc7 1277 config |= _BV(EN_CRC);
jjeong 0:9d06cdd73bc7 1278 config |= _BV( CRCO );
jjeong 0:9d06cdd73bc7 1279 }
jjeong 0:9d06cdd73bc7 1280 write_register( NRF_CONFIG, config ) ;
jjeong 0:9d06cdd73bc7 1281 }
jjeong 0:9d06cdd73bc7 1282
jjeong 0:9d06cdd73bc7 1283 /****************************************************************************/
jjeong 0:9d06cdd73bc7 1284
jjeong 0:9d06cdd73bc7 1285 rf24_crclength_e RF24::getCRCLength(void)
jjeong 0:9d06cdd73bc7 1286 {
jjeong 0:9d06cdd73bc7 1287 rf24_crclength_e result = RF24_CRC_DISABLED;
jjeong 0:9d06cdd73bc7 1288
jjeong 0:9d06cdd73bc7 1289 uint8_t config = read_register(NRF_CONFIG) & ( _BV(CRCO) | _BV(EN_CRC)) ;
jjeong 0:9d06cdd73bc7 1290 uint8_t AA = read_register(EN_AA);
jjeong 0:9d06cdd73bc7 1291
jjeong 0:9d06cdd73bc7 1292 if ( config & _BV(EN_CRC ) || AA)
jjeong 0:9d06cdd73bc7 1293 {
jjeong 0:9d06cdd73bc7 1294 if ( config & _BV(CRCO) )
jjeong 0:9d06cdd73bc7 1295 result = RF24_CRC_16;
jjeong 0:9d06cdd73bc7 1296 else
jjeong 0:9d06cdd73bc7 1297 result = RF24_CRC_8;
jjeong 0:9d06cdd73bc7 1298 }
jjeong 0:9d06cdd73bc7 1299
jjeong 0:9d06cdd73bc7 1300 return result;
jjeong 0:9d06cdd73bc7 1301 }
jjeong 0:9d06cdd73bc7 1302
jjeong 0:9d06cdd73bc7 1303 /****************************************************************************/
jjeong 0:9d06cdd73bc7 1304
jjeong 0:9d06cdd73bc7 1305 void RF24::disableCRC( void )
jjeong 0:9d06cdd73bc7 1306 {
jjeong 0:9d06cdd73bc7 1307 uint8_t disable = read_register(NRF_CONFIG) & ~_BV(EN_CRC) ;
jjeong 0:9d06cdd73bc7 1308 write_register( NRF_CONFIG, disable ) ;
jjeong 0:9d06cdd73bc7 1309 }
jjeong 0:9d06cdd73bc7 1310
jjeong 0:9d06cdd73bc7 1311 /****************************************************************************/
jjeong 0:9d06cdd73bc7 1312 void RF24::setRetries(uint8_t delay, uint8_t count)
jjeong 0:9d06cdd73bc7 1313 {
jjeong 0:9d06cdd73bc7 1314 write_register(SETUP_RETR,(delay&0xf)<<ARD | (count&0xf)<<ARC);
jjeong 0:9d06cdd73bc7 1315 }
jjeong 0:9d06cdd73bc7 1316