Janek Mann / mbed-src-openwear

mbed library sources modified for open wear

Dependents:   openwear-lifelogger-example

Fork of mbed-src by mbed official

targets/hal/TARGET_Freescale/TARGET_K20D50M/spi_api.c@275:8287c40fc7ee, 2014-08-07 (annotated)

Committer:
mbed_official
Date:
Thu Aug 07 09:15:06 2014 +0100
Revision:
275:8287c40fc7ee
Parent:
255:20b371a9491b 
Synchronized with git revision 83b4b6d213bd3ca57392eaae0e13845c3b32015f



Full URL: https://github.com/mbedmicro/mbed/commit/83b4b6d213bd3ca57392eaae0e13845c3b32015f/



[Kinetis K] K64F and K20D50M - SPI Slave read bug fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 68:41613245dfd7 1 /* mbed Microcontroller Library
mbed_official 68:41613245dfd7 2 * Copyright (c) 2013 ARM Limited
mbed_official 68:41613245dfd7 3 *
mbed_official 68:41613245dfd7 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 68:41613245dfd7 5 * you may not use this file except in compliance with the License.
mbed_official 68:41613245dfd7 6 * You may obtain a copy of the License at
mbed_official 68:41613245dfd7 7 *
mbed_official 68:41613245dfd7 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 68:41613245dfd7 9 *
mbed_official 68:41613245dfd7 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 68:41613245dfd7 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 68:41613245dfd7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 68:41613245dfd7 13 * See the License for the specific language governing permissions and
mbed_official 68:41613245dfd7 14 * limitations under the License.
mbed_official 68:41613245dfd7 15 */
mbed_official 227:7bd0639b8911 16 #include "mbed_assert.h"
mbed_official 68:41613245dfd7 17 #include "spi_api.h"
mbed_official 68:41613245dfd7 18
mbed_official 68:41613245dfd7 19 #include <math.h>
mbed_official 68:41613245dfd7 20
mbed_official 68:41613245dfd7 21 #include "cmsis.h"
mbed_official 68:41613245dfd7 22 #include "pinmap.h"
mbed_official 73:299c67215126 23 #include "clk_freqs.h"
mbed_official 68:41613245dfd7 24
mbed_official 68:41613245dfd7 25 static const PinMap PinMap_SPI_SCLK[] = {
mbed_official 68:41613245dfd7 26 {PTC5, SPI_0, 2},
mbed_official 68:41613245dfd7 27 {PTD1, SPI_0, 2},
mbed_official 68:41613245dfd7 28 {NC , NC , 0}
mbed_official 68:41613245dfd7 29 };
mbed_official 68:41613245dfd7 30
mbed_official 68:41613245dfd7 31 static const PinMap PinMap_SPI_MOSI[] = {
mbed_official 68:41613245dfd7 32 {PTD2, SPI_0, 2},
mbed_official 68:41613245dfd7 33 {PTC6, SPI_0, 2},
mbed_official 68:41613245dfd7 34 {NC , NC , 0}
mbed_official 68:41613245dfd7 35 };
mbed_official 68:41613245dfd7 36
mbed_official 68:41613245dfd7 37 static const PinMap PinMap_SPI_MISO[] = {
mbed_official 68:41613245dfd7 38 {PTD3, SPI_0, 2},
mbed_official 68:41613245dfd7 39 {PTC7, SPI_0, 2},
mbed_official 68:41613245dfd7 40 {NC , NC , 0}
mbed_official 68:41613245dfd7 41 };
mbed_official 68:41613245dfd7 42
mbed_official 68:41613245dfd7 43 static const PinMap PinMap_SPI_SSEL[] = {
mbed_official 68:41613245dfd7 44 {PTD0, SPI_0, 2},
mbed_official 68:41613245dfd7 45 {PTC4, SPI_0, 2},
mbed_official 68:41613245dfd7 46 {NC , NC , 0}
mbed_official 68:41613245dfd7 47 };
mbed_official 68:41613245dfd7 48
mbed_official 68:41613245dfd7 49 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
mbed_official 68:41613245dfd7 50 // determine the SPI to use
mbed_official 68:41613245dfd7 51 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
mbed_official 68:41613245dfd7 52 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
mbed_official 68:41613245dfd7 53 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
mbed_official 68:41613245dfd7 54 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
mbed_official 68:41613245dfd7 55 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
mbed_official 68:41613245dfd7 56 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
mbed_official 195:442092318da6 57
mbed_official 68:41613245dfd7 58 obj->spi = (SPI_Type*)pinmap_merge(spi_data, spi_cntl);
mbed_official 227:7bd0639b8911 59 MBED_ASSERT((int)obj->spi != NC);
mbed_official 68:41613245dfd7 60
mbed_official 73:299c67215126 61 SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK;
mbed_official 73:299c67215126 62 SIM->SCGC6 |= SIM_SCGC6_SPI0_MASK;
mbed_official 68:41613245dfd7 63
mbed_official 195:442092318da6 64 obj->spi->MCR &= ~(SPI_MCR_MDIS_MASK | SPI_MCR_HALT_MASK);
mbed_official 195:442092318da6 65 //obj->spi->MCR |= SPI_MCR_DIS_RXF_MASK | SPI_MCR_DIS_TXF_MASK;
mbed_official 68:41613245dfd7 66
mbed_official 68:41613245dfd7 67 // set default format and frequency
mbed_official 68:41613245dfd7 68 if (ssel == NC) {
mbed_official 68:41613245dfd7 69 spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
mbed_official 68:41613245dfd7 70 } else {
mbed_official 68:41613245dfd7 71 spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
mbed_official 68:41613245dfd7 72 }
mbed_official 68:41613245dfd7 73 spi_frequency(obj, 1000000);
mbed_official 68:41613245dfd7 74
mbed_official 68:41613245dfd7 75 // not halt in the debug mode
mbed_official 68:41613245dfd7 76 obj->spi->SR |= SPI_SR_EOQF_MASK;
mbed_official 68:41613245dfd7 77
mbed_official 68:41613245dfd7 78 // pin out the spi pins
mbed_official 68:41613245dfd7 79 pinmap_pinout(mosi, PinMap_SPI_MOSI);
mbed_official 68:41613245dfd7 80 pinmap_pinout(miso, PinMap_SPI_MISO);
mbed_official 68:41613245dfd7 81 pinmap_pinout(sclk, PinMap_SPI_SCLK);
mbed_official 68:41613245dfd7 82 if (ssel != NC) {
mbed_official 68:41613245dfd7 83 pinmap_pinout(ssel, PinMap_SPI_SSEL);
mbed_official 68:41613245dfd7 84 }
mbed_official 68:41613245dfd7 85 }
mbed_official 68:41613245dfd7 86
mbed_official 68:41613245dfd7 87 void spi_free(spi_t *obj) {
mbed_official 68:41613245dfd7 88 // [TODO]
mbed_official 68:41613245dfd7 89 }
mbed_official 68:41613245dfd7 90 void spi_format(spi_t *obj, int bits, int mode, int slave) {
mbed_official 227:7bd0639b8911 91 MBED_ASSERT((bits > 4) || (bits < 16));
mbed_official 227:7bd0639b8911 92 MBED_ASSERT((mode >= 0) && (mode <= 3));
mbed_official 68:41613245dfd7 93
mbed_official 68:41613245dfd7 94 uint32_t polarity = (mode & 0x2) ? 1 : 0;
mbed_official 68:41613245dfd7 95 uint32_t phase = (mode & 0x1) ? 1 : 0;
mbed_official 68:41613245dfd7 96
mbed_official 68:41613245dfd7 97 // set master/slave
mbed_official 68:41613245dfd7 98 obj->spi->MCR &= ~SPI_MCR_MSTR_MASK;
mbed_official 68:41613245dfd7 99 obj->spi->MCR |= ((!slave) << SPI_MCR_MSTR_SHIFT);
mbed_official 68:41613245dfd7 100
mbed_official 68:41613245dfd7 101 // CTAR0 is used
mbed_official 195:442092318da6 102 obj->spi->CTAR[0] &= ~(SPI_CTAR_CPHA_MASK | SPI_CTAR_CPOL_MASK | SPI_CTAR_FMSZ_MASK);
mbed_official 195:442092318da6 103 obj->spi->CTAR[0] |= (polarity << SPI_CTAR_CPOL_SHIFT) | (phase << SPI_CTAR_CPHA_SHIFT) | ((bits - 1) << SPI_CTAR_FMSZ_SHIFT);
mbed_official 68:41613245dfd7 104 }
mbed_official 68:41613245dfd7 105
mbed_official 73:299c67215126 106 static const uint8_t baudrate_prescaler[] = {2,3,5,7};
mbed_official 195:442092318da6 107 static const uint16_t baudrate_scaler[] = {2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768};
mbed_official 73:299c67215126 108
mbed_official 68:41613245dfd7 109 void spi_frequency(spi_t *obj, int hz) {
mbed_official 195:442092318da6 110 uint32_t f_error = 0;
mbed_official 68:41613245dfd7 111 uint32_t p_error = 0xffffffff;
mbed_official 68:41613245dfd7 112 uint32_t ref = 0;
mbed_official 73:299c67215126 113 uint32_t br = 0;
mbed_official 68:41613245dfd7 114 uint32_t ref_spr = 0;
mbed_official 68:41613245dfd7 115 uint32_t ref_prescaler = 0;
mbed_official 195:442092318da6 116 uint32_t ref_dr = 0;
mbed_official 68:41613245dfd7 117
mbed_official 68:41613245dfd7 118 // bus clk
mbed_official 73:299c67215126 119 uint32_t PCLK = bus_frequency();
mbed_official 68:41613245dfd7 120
mbed_official 73:299c67215126 121 for (uint32_t i = 0; i < 4; i++) {
mbed_official 195:442092318da6 122 for (br = 0; br <= 15; br++) {
mbed_official 73:299c67215126 123 for (uint32_t dr = 0; dr < 2; dr++) {
mbed_official 195:442092318da6 124 ref = (PCLK * (1U + dr) / baudrate_prescaler[i]) / baudrate_scaler[br];
mbed_official 73:299c67215126 125 if (ref > (uint32_t)hz)
mbed_official 73:299c67215126 126 continue;
mbed_official 195:442092318da6 127 f_error = hz - ref;
mbed_official 195:442092318da6 128 if (f_error < p_error) {
mbed_official 73:299c67215126 129 ref_spr = br;
mbed_official 73:299c67215126 130 ref_prescaler = i;
mbed_official 195:442092318da6 131 ref_dr = dr;
mbed_official 195:442092318da6 132 p_error = f_error;
mbed_official 73:299c67215126 133 }
mbed_official 68:41613245dfd7 134 }
mbed_official 68:41613245dfd7 135 }
mbed_official 68:41613245dfd7 136 }
mbed_official 68:41613245dfd7 137
mbed_official 73:299c67215126 138 // set PBR and BR
mbed_official 195:442092318da6 139 obj->spi->CTAR[0] &= ~(SPI_CTAR_PBR_MASK | SPI_CTAR_BR_MASK | SPI_CTAR_DBR_MASK);
mbed_official 195:442092318da6 140 obj->spi->CTAR[0] |= (ref_prescaler << SPI_CTAR_PBR_SHIFT) | (ref_spr << SPI_CTAR_BR_SHIFT) | (ref_dr << SPI_CTAR_DBR_SHIFT);
mbed_official 68:41613245dfd7 141 }
mbed_official 68:41613245dfd7 142
mbed_official 73:299c67215126 143 static inline int spi_writeable(spi_t *obj) {
mbed_official 73:299c67215126 144 return (obj->spi->SR & SPI_SR_TFFF_MASK) ? 1 : 0;
mbed_official 68:41613245dfd7 145 }
mbed_official 68:41613245dfd7 146
mbed_official 73:299c67215126 147 static inline int spi_readable(spi_t *obj) {
mbed_official 195:442092318da6 148 return (obj->spi->SR & SPI_SR_RFDF_MASK) ? 1 : 0;
mbed_official 68:41613245dfd7 149 }
mbed_official 68:41613245dfd7 150
mbed_official 68:41613245dfd7 151 int spi_master_write(spi_t *obj, int value) {
mbed_official 195:442092318da6 152 //clear RX buffer flag
mbed_official 195:442092318da6 153 obj->spi->SR |= SPI_SR_RFDF_MASK;
mbed_official 68:41613245dfd7 154 // wait tx buffer empty
mbed_official 68:41613245dfd7 155 while(!spi_writeable(obj));
mbed_official 195:442092318da6 156 obj->spi->PUSHR = SPI_PUSHR_TXDATA(value & 0xffff) /*| SPI_PUSHR_EOQ_MASK*/;
mbed_official 68:41613245dfd7 157
mbed_official 68:41613245dfd7 158 // wait rx buffer full
mbed_official 68:41613245dfd7 159 while (!spi_readable(obj));
mbed_official 68:41613245dfd7 160 return obj->spi->POPR;
mbed_official 68:41613245dfd7 161 }
mbed_official 68:41613245dfd7 162
mbed_official 68:41613245dfd7 163 int spi_slave_receive(spi_t *obj) {
mbed_official 68:41613245dfd7 164 return spi_readable(obj);
mbed_official 68:41613245dfd7 165 }
mbed_official 68:41613245dfd7 166
mbed_official 68:41613245dfd7 167 int spi_slave_read(spi_t *obj) {
mbed_official 275:8287c40fc7ee 168 obj->spi->SR |= SPI_SR_RFDF_MASK;
mbed_official 68:41613245dfd7 169 return obj->spi->POPR;
mbed_official 68:41613245dfd7 170 }
mbed_official 68:41613245dfd7 171
mbed_official 68:41613245dfd7 172 void spi_slave_write(spi_t *obj, int value) {
mbed_official 68:41613245dfd7 173 while (!spi_writeable(obj));
mbed_official 68:41613245dfd7 174 }