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targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_rcc.h@610:813dcc80987e, 2015-08-14 (annotated)

Committer:: mbed_official
Date:: Fri Aug 14 13:15:17 2015 +0100
Revision:: 610:813dcc80987e

Synchronized with git revision 6d84db41c6833e0b9b024741eb0616a5f62d5599

Full URL: https://github.com/mbedmicro/mbed/commit/6d84db41c6833e0b9b024741eb0616a5f62d5599/

DISCO_F746NG - Improvements

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	610:813dcc80987e	1	/**
mbed_official	610:813dcc80987e	2	******************************************************************************
mbed_official	610:813dcc80987e	3	* @file stm32l4xx_hal_rcc.h
mbed_official	610:813dcc80987e	4	* @author MCD Application Team
mbed_official	610:813dcc80987e	5	* @version V1.0.0
mbed_official	610:813dcc80987e	6	* @date 26-June-2015
mbed_official	610:813dcc80987e	7	* @brief Header file of RCC HAL module.
mbed_official	610:813dcc80987e	8	******************************************************************************
mbed_official	610:813dcc80987e	9	* @attention
mbed_official	610:813dcc80987e	10	*
mbed_official	610:813dcc80987e	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official	610:813dcc80987e	12	*
mbed_official	610:813dcc80987e	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	610:813dcc80987e	14	* are permitted provided that the following conditions are met:
mbed_official	610:813dcc80987e	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	610:813dcc80987e	16	* this list of conditions and the following disclaimer.
mbed_official	610:813dcc80987e	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	610:813dcc80987e	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	610:813dcc80987e	19	* and/or other materials provided with the distribution.
mbed_official	610:813dcc80987e	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	610:813dcc80987e	21	* may be used to endorse or promote products derived from this software
mbed_official	610:813dcc80987e	22	* without specific prior written permission.
mbed_official	610:813dcc80987e	23	*
mbed_official	610:813dcc80987e	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	610:813dcc80987e	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	610:813dcc80987e	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	610:813dcc80987e	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	610:813dcc80987e	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	610:813dcc80987e	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	610:813dcc80987e	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	610:813dcc80987e	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	610:813dcc80987e	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	610:813dcc80987e	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	610:813dcc80987e	34	*
mbed_official	610:813dcc80987e	35	******************************************************************************
mbed_official	610:813dcc80987e	36	*/
mbed_official	610:813dcc80987e	37
mbed_official	610:813dcc80987e	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	610:813dcc80987e	39	#ifndef __STM32L4xx_HAL_RCC_H
mbed_official	610:813dcc80987e	40	#define __STM32L4xx_HAL_RCC_H
mbed_official	610:813dcc80987e	41
mbed_official	610:813dcc80987e	42	#ifdef __cplusplus
mbed_official	610:813dcc80987e	43	extern "C" {
mbed_official	610:813dcc80987e	44	#endif
mbed_official	610:813dcc80987e	45
mbed_official	610:813dcc80987e	46	/* Includes ------------------------------------------------------------------*/
mbed_official	610:813dcc80987e	47	#include "stm32l4xx_hal_def.h"
mbed_official	610:813dcc80987e	48
mbed_official	610:813dcc80987e	49	/** @addtogroup STM32L4xx_HAL_Driver
mbed_official	610:813dcc80987e	50	* @{
mbed_official	610:813dcc80987e	51	*/
mbed_official	610:813dcc80987e	52
mbed_official	610:813dcc80987e	53	/** @addtogroup RCC
mbed_official	610:813dcc80987e	54	* @{
mbed_official	610:813dcc80987e	55	*/
mbed_official	610:813dcc80987e	56
mbed_official	610:813dcc80987e	57	/* Exported types ------------------------------------------------------------*/
mbed_official	610:813dcc80987e	58	/** @defgroup RCC_Exported_Types RCC Exported Types
mbed_official	610:813dcc80987e	59	* @{
mbed_official	610:813dcc80987e	60	*/
mbed_official	610:813dcc80987e	61
mbed_official	610:813dcc80987e	62	/**
mbed_official	610:813dcc80987e	63	* @brief RCC PLL configuration structure definition
mbed_official	610:813dcc80987e	64	*/
mbed_official	610:813dcc80987e	65	typedef struct
mbed_official	610:813dcc80987e	66	{
mbed_official	610:813dcc80987e	67	uint32_t PLLState; /*!< The new state of the PLL.
mbed_official	610:813dcc80987e	68	This parameter can be a value of @ref RCC_PLL_Config */
mbed_official	610:813dcc80987e	69
mbed_official	610:813dcc80987e	70	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
mbed_official	610:813dcc80987e	71	This parameter must be a value of @ref RCC_PLL_Clock_Source */
mbed_official	610:813dcc80987e	72
mbed_official	610:813dcc80987e	73	uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
mbed_official	610:813dcc80987e	74	This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
mbed_official	610:813dcc80987e	75
mbed_official	610:813dcc80987e	76	uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
mbed_official	610:813dcc80987e	77	This parameter must be a number between Min_Data = 8 and Max_Data = 86 */
mbed_official	610:813dcc80987e	78
mbed_official	610:813dcc80987e	79	uint32_t PLLP; /*!< PLLP: Division factor for SAI clock.
mbed_official	610:813dcc80987e	80	This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
mbed_official	610:813dcc80987e	81
mbed_official	610:813dcc80987e	82	uint32_t PLLQ; /*!< PLLQ: Division factor for SDMMC1, RNG and USB clocks.
mbed_official	610:813dcc80987e	83	This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */
mbed_official	610:813dcc80987e	84
mbed_official	610:813dcc80987e	85	uint32_t PLLR; /*!< PLLR: Division for the main system clock.
mbed_official	610:813dcc80987e	86	User have to set the PLLR parameter correctly to not exceed max frequency 80MHZ.
mbed_official	610:813dcc80987e	87	This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
mbed_official	610:813dcc80987e	88
mbed_official	610:813dcc80987e	89	}RCC_PLLInitTypeDef;
mbed_official	610:813dcc80987e	90
mbed_official	610:813dcc80987e	91	/**
mbed_official	610:813dcc80987e	92	* @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition
mbed_official	610:813dcc80987e	93	*/
mbed_official	610:813dcc80987e	94	typedef struct
mbed_official	610:813dcc80987e	95	{
mbed_official	610:813dcc80987e	96	uint32_t OscillatorType; /*!< The oscillators to be configured.
mbed_official	610:813dcc80987e	97	This parameter can be a value of @ref RCC_Oscillator_Type */
mbed_official	610:813dcc80987e	98
mbed_official	610:813dcc80987e	99	uint32_t HSEState; /*!< The new state of the HSE.
mbed_official	610:813dcc80987e	100	This parameter can be a value of @ref RCC_HSE_Config */
mbed_official	610:813dcc80987e	101
mbed_official	610:813dcc80987e	102	uint32_t LSEState; /*!< The new state of the LSE.
mbed_official	610:813dcc80987e	103	This parameter can be a value of @ref RCC_LSE_Config */
mbed_official	610:813dcc80987e	104
mbed_official	610:813dcc80987e	105	uint32_t HSIState; /*!< The new state of the HSI.
mbed_official	610:813dcc80987e	106	This parameter can be a value of @ref RCC_HSI_Config */
mbed_official	610:813dcc80987e	107
mbed_official	610:813dcc80987e	108	uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
mbed_official	610:813dcc80987e	109	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
mbed_official	610:813dcc80987e	110
mbed_official	610:813dcc80987e	111	uint32_t LSIState; /*!< The new state of the LSI.
mbed_official	610:813dcc80987e	112	This parameter can be a value of @ref RCC_LSI_Config */
mbed_official	610:813dcc80987e	113
mbed_official	610:813dcc80987e	114	uint32_t MSIState; /*!< The new state of the MSI.
mbed_official	610:813dcc80987e	115	This parameter can be a value of @ref RCC_MSI_Config */
mbed_official	610:813dcc80987e	116
mbed_official	610:813dcc80987e	117	uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT).
mbed_official	610:813dcc80987e	118	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
mbed_official	610:813dcc80987e	119
mbed_official	610:813dcc80987e	120	uint32_t MSIClockRange; /*!< The MSI frequency range.
mbed_official	610:813dcc80987e	121	This parameter can be a value of @ref RCC_MSI_Clock_Range */
mbed_official	610:813dcc80987e	122
mbed_official	610:813dcc80987e	123	RCC_PLLInitTypeDef PLL; /!< Main PLL structure parameters /
mbed_official	610:813dcc80987e	124
mbed_official	610:813dcc80987e	125	}RCC_OscInitTypeDef;
mbed_official	610:813dcc80987e	126
mbed_official	610:813dcc80987e	127	/**
mbed_official	610:813dcc80987e	128	* @brief RCC System, AHB and APB busses clock configuration structure definition
mbed_official	610:813dcc80987e	129	*/
mbed_official	610:813dcc80987e	130	typedef struct
mbed_official	610:813dcc80987e	131	{
mbed_official	610:813dcc80987e	132	uint32_t ClockType; /*!< The clock to be configured.
mbed_official	610:813dcc80987e	133	This parameter can be a value of @ref RCC_System_Clock_Type */
mbed_official	610:813dcc80987e	134
mbed_official	610:813dcc80987e	135	uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK).
mbed_official	610:813dcc80987e	136	This parameter can be a value of @ref RCC_System_Clock_Source */
mbed_official	610:813dcc80987e	137
mbed_official	610:813dcc80987e	138	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
mbed_official	610:813dcc80987e	139	This parameter can be a value of @ref RCC_AHB_Clock_Source */
mbed_official	610:813dcc80987e	140
mbed_official	610:813dcc80987e	141	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
mbed_official	610:813dcc80987e	142	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
mbed_official	610:813dcc80987e	143
mbed_official	610:813dcc80987e	144	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
mbed_official	610:813dcc80987e	145	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
mbed_official	610:813dcc80987e	146
mbed_official	610:813dcc80987e	147	}RCC_ClkInitTypeDef;
mbed_official	610:813dcc80987e	148
mbed_official	610:813dcc80987e	149	/**
mbed_official	610:813dcc80987e	150	* @}
mbed_official	610:813dcc80987e	151	*/
mbed_official	610:813dcc80987e	152
mbed_official	610:813dcc80987e	153	/* Exported constants --------------------------------------------------------*/
mbed_official	610:813dcc80987e	154	/** @defgroup RCC_Exported_Constants RCC Exported Constants
mbed_official	610:813dcc80987e	155	* @{
mbed_official	610:813dcc80987e	156	*/
mbed_official	610:813dcc80987e	157
mbed_official	610:813dcc80987e	158	/** @defgroup RCC_Timeout_Value Timeout Values
mbed_official	610:813dcc80987e	159	* @{
mbed_official	610:813dcc80987e	160	*/
mbed_official	610:813dcc80987e	161	#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
mbed_official	610:813dcc80987e	162	#define RCC_LSE_TIMEOUT_VALUE ((uint32_t)5000)
mbed_official	610:813dcc80987e	163	/**
mbed_official	610:813dcc80987e	164	* @}
mbed_official	610:813dcc80987e	165	*/
mbed_official	610:813dcc80987e	166
mbed_official	610:813dcc80987e	167	/** @defgroup RCC_Oscillator_Type Oscillator Type
mbed_official	610:813dcc80987e	168	* @{
mbed_official	610:813dcc80987e	169	*/
mbed_official	610:813dcc80987e	170	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000) /!< Oscillator configuration unchanged /
mbed_official	610:813dcc80987e	171	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001) /!< HSE to configure /
mbed_official	610:813dcc80987e	172	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002) /!< HSI to configure /
mbed_official	610:813dcc80987e	173	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004) /!< LSE to configure /
mbed_official	610:813dcc80987e	174	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008) /!< LSI to configure /
mbed_official	610:813dcc80987e	175	#define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010) /!< MSI to configure /
mbed_official	610:813dcc80987e	176	/**
mbed_official	610:813dcc80987e	177	* @}
mbed_official	610:813dcc80987e	178	*/
mbed_official	610:813dcc80987e	179
mbed_official	610:813dcc80987e	180	/** @defgroup RCC_HSE_Config HSE Config
mbed_official	610:813dcc80987e	181	* @{
mbed_official	610:813dcc80987e	182	*/
mbed_official	610:813dcc80987e	183	#define RCC_HSE_OFF ((uint32_t)0x00000000) /!< HSE clock deactivation /
mbed_official	610:813dcc80987e	184	#define RCC_HSE_ON RCC_CR_HSEON /!< HSE clock activation /
mbed_official	610:813dcc80987e	185	#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP \| RCC_CR_HSEON)) /!< External clock source for HSE clock /
mbed_official	610:813dcc80987e	186	/**
mbed_official	610:813dcc80987e	187	* @}
mbed_official	610:813dcc80987e	188	*/
mbed_official	610:813dcc80987e	189
mbed_official	610:813dcc80987e	190	/** @defgroup RCC_LSE_Config LSE Config
mbed_official	610:813dcc80987e	191	* @{
mbed_official	610:813dcc80987e	192	*/
mbed_official	610:813dcc80987e	193	#define RCC_LSE_OFF ((uint32_t)0x00000000) /!< LSE clock deactivation /
mbed_official	610:813dcc80987e	194	#define RCC_LSE_ON RCC_BDCR_LSEON /!< LSE clock activation /
mbed_official	610:813dcc80987e	195	#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP \| RCC_BDCR_LSEON)) /!< External clock source for LSE clock /
mbed_official	610:813dcc80987e	196	/**
mbed_official	610:813dcc80987e	197	* @}
mbed_official	610:813dcc80987e	198	*/
mbed_official	610:813dcc80987e	199
mbed_official	610:813dcc80987e	200	/** @defgroup RCC_HSI_Config HSI Config
mbed_official	610:813dcc80987e	201	* @{
mbed_official	610:813dcc80987e	202	*/
mbed_official	610:813dcc80987e	203	#define RCC_HSI_OFF ((uint32_t)0x00000000) /!< HSI clock deactivation /
mbed_official	610:813dcc80987e	204	#define RCC_HSI_ON RCC_CR_HSION /!< HSI clock activation /
mbed_official	610:813dcc80987e	205
mbed_official	610:813dcc80987e	206	#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)16) /!< Default HSI calibration trimming value /
mbed_official	610:813dcc80987e	207	/**
mbed_official	610:813dcc80987e	208	* @}
mbed_official	610:813dcc80987e	209	*/
mbed_official	610:813dcc80987e	210
mbed_official	610:813dcc80987e	211	/** @defgroup RCC_LSI_Config LSI Config
mbed_official	610:813dcc80987e	212	* @{
mbed_official	610:813dcc80987e	213	*/
mbed_official	610:813dcc80987e	214	#define RCC_LSI_OFF ((uint32_t)0x00000000) /!< LSI clock deactivation /
mbed_official	610:813dcc80987e	215	#define RCC_LSI_ON RCC_CSR_LSION /!< LSI clock activation /
mbed_official	610:813dcc80987e	216	/**
mbed_official	610:813dcc80987e	217	* @}
mbed_official	610:813dcc80987e	218	*/
mbed_official	610:813dcc80987e	219
mbed_official	610:813dcc80987e	220	/** @defgroup RCC_MSI_Config MSI Config
mbed_official	610:813dcc80987e	221	* @{
mbed_official	610:813dcc80987e	222	*/
mbed_official	610:813dcc80987e	223	#define RCC_MSI_OFF ((uint32_t)0x00000000) /!< MSI clock deactivation /
mbed_official	610:813dcc80987e	224	#define RCC_MSI_ON RCC_CR_MSION /!< MSI clock activation /
mbed_official	610:813dcc80987e	225
mbed_official	610:813dcc80987e	226	#define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0) /!< Default MSI calibration trimming value /
mbed_official	610:813dcc80987e	227	/**
mbed_official	610:813dcc80987e	228	* @}
mbed_official	610:813dcc80987e	229	*/
mbed_official	610:813dcc80987e	230
mbed_official	610:813dcc80987e	231	/** @defgroup RCC_PLL_Config PLL Config
mbed_official	610:813dcc80987e	232	* @{
mbed_official	610:813dcc80987e	233	*/
mbed_official	610:813dcc80987e	234	#define RCC_PLL_NONE ((uint32_t)0x00000000) /!< PLL configuration unchanged /
mbed_official	610:813dcc80987e	235	#define RCC_PLL_OFF ((uint32_t)0x00000001) /!< PLL deactivation /
mbed_official	610:813dcc80987e	236	#define RCC_PLL_ON ((uint32_t)0x00000002) /!< PLL activation /
mbed_official	610:813dcc80987e	237	/**
mbed_official	610:813dcc80987e	238	* @}
mbed_official	610:813dcc80987e	239	*/
mbed_official	610:813dcc80987e	240
mbed_official	610:813dcc80987e	241	/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
mbed_official	610:813dcc80987e	242	* @{
mbed_official	610:813dcc80987e	243	*/
mbed_official	610:813dcc80987e	244	#define RCC_PLLP_DIV7 ((uint32_t)0x00000007) /!< PLLP division factor = 7 /
mbed_official	610:813dcc80987e	245	#define RCC_PLLP_DIV17 ((uint32_t)0x00000011) /!< PLLP division factor = 17 /
mbed_official	610:813dcc80987e	246	/**
mbed_official	610:813dcc80987e	247	* @}
mbed_official	610:813dcc80987e	248	*/
mbed_official	610:813dcc80987e	249
mbed_official	610:813dcc80987e	250	/** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider
mbed_official	610:813dcc80987e	251	* @{
mbed_official	610:813dcc80987e	252	*/
mbed_official	610:813dcc80987e	253	#define RCC_PLLQ_DIV2 ((uint32_t)0x00000002) /!< PLLQ division factor = 2 /
mbed_official	610:813dcc80987e	254	#define RCC_PLLQ_DIV4 ((uint32_t)0x00000004) /!< PLLQ division factor = 4 /
mbed_official	610:813dcc80987e	255	#define RCC_PLLQ_DIV6 ((uint32_t)0x00000006) /!< PLLQ division factor = 6 /
mbed_official	610:813dcc80987e	256	#define RCC_PLLQ_DIV8 ((uint32_t)0x00000008) /!< PLLQ division factor = 8 /
mbed_official	610:813dcc80987e	257	/**
mbed_official	610:813dcc80987e	258	* @}
mbed_official	610:813dcc80987e	259	*/
mbed_official	610:813dcc80987e	260
mbed_official	610:813dcc80987e	261	/** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider
mbed_official	610:813dcc80987e	262	* @{
mbed_official	610:813dcc80987e	263	*/
mbed_official	610:813dcc80987e	264	#define RCC_PLLR_DIV2 ((uint32_t)0x00000002) /!< PLLR division factor = 2 /
mbed_official	610:813dcc80987e	265	#define RCC_PLLR_DIV4 ((uint32_t)0x00000004) /!< PLLR division factor = 4 /
mbed_official	610:813dcc80987e	266	#define RCC_PLLR_DIV6 ((uint32_t)0x00000006) /!< PLLR division factor = 6 /
mbed_official	610:813dcc80987e	267	#define RCC_PLLR_DIV8 ((uint32_t)0x00000008) /!< PLLR division factor = 8 /
mbed_official	610:813dcc80987e	268	/**
mbed_official	610:813dcc80987e	269	* @}
mbed_official	610:813dcc80987e	270	*/
mbed_official	610:813dcc80987e	271
mbed_official	610:813dcc80987e	272	/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
mbed_official	610:813dcc80987e	273	* @{
mbed_official	610:813dcc80987e	274	*/
mbed_official	610:813dcc80987e	275	#define RCC_PLLSOURCE_NONE ((uint32_t)0x00000000) /!< No clock selected as PLL entry clock source /
mbed_official	610:813dcc80987e	276	#define RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /!< MSI clock selected as PLL entry clock source /
mbed_official	610:813dcc80987e	277	#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /!< HSI clock selected as PLL entry clock source /
mbed_official	610:813dcc80987e	278	#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /!< HSE clock selected as PLL entry clock source /
mbed_official	610:813dcc80987e	279	/**
mbed_official	610:813dcc80987e	280	* @}
mbed_official	610:813dcc80987e	281	*/
mbed_official	610:813dcc80987e	282
mbed_official	610:813dcc80987e	283	/** @defgroup RCC_PLL_Clock_Output PLL Clock Output
mbed_official	610:813dcc80987e	284	* @{
mbed_official	610:813dcc80987e	285	*/
mbed_official	610:813dcc80987e	286	#define RCC_PLL_SAI3CLK RCC_PLLCFGR_PLLPEN /!< PLLSAI3CLK selection from main PLL /
mbed_official	610:813dcc80987e	287	#define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN /!< PLL48M1CLK selection from main PLL /
mbed_official	610:813dcc80987e	288	#define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /!< PLLCLK selection from main PLL /
mbed_official	610:813dcc80987e	289	/**
mbed_official	610:813dcc80987e	290	* @}
mbed_official	610:813dcc80987e	291	*/
mbed_official	610:813dcc80987e	292
mbed_official	610:813dcc80987e	293	/** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output
mbed_official	610:813dcc80987e	294	* @{
mbed_official	610:813dcc80987e	295	*/
mbed_official	610:813dcc80987e	296	#define RCC_PLLSAI1_SAI1CLK RCC_PLLSAI1CFGR_PLLSAI1PEN /!< PLLSAI1CLK selection from PLLSAI1 /
mbed_official	610:813dcc80987e	297	#define RCC_PLLSAI1_48M2CLK RCC_PLLSAI1CFGR_PLLSAI1QEN /!< PLL48M2CLK selection from PLLSAI1 /
mbed_official	610:813dcc80987e	298	#define RCC_PLLSAI1_ADC1CLK RCC_PLLSAI1CFGR_PLLSAI1REN /!< PLLADC1CLK selection from PLLSAI1 /
mbed_official	610:813dcc80987e	299	/**
mbed_official	610:813dcc80987e	300	* @}
mbed_official	610:813dcc80987e	301	*/
mbed_official	610:813dcc80987e	302
mbed_official	610:813dcc80987e	303	/** @defgroup RCC_PLLSAI2_Clock_Output PLLSAI2 Clock Output
mbed_official	610:813dcc80987e	304	* @{
mbed_official	610:813dcc80987e	305	*/
mbed_official	610:813dcc80987e	306	#define RCC_PLLSAI2_SAI2CLK RCC_PLLSAI2CFGR_PLLSAI2PEN /!< PLLSAI2CLK selection from PLLSAI2 /
mbed_official	610:813dcc80987e	307	#define RCC_PLLSAI2_ADC2CLK RCC_PLLSAI2CFGR_PLLSAI2REN /!< PLLADC2CLK selection from PLLSAI2 /
mbed_official	610:813dcc80987e	308	/**
mbed_official	610:813dcc80987e	309	* @}
mbed_official	610:813dcc80987e	310	*/
mbed_official	610:813dcc80987e	311
mbed_official	610:813dcc80987e	312	/** @defgroup RCC_MSI_Clock_Range MSI Clock Range
mbed_official	610:813dcc80987e	313	* @{
mbed_official	610:813dcc80987e	314	*/
mbed_official	610:813dcc80987e	315	#define RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /!< MSI = 100 KHz /
mbed_official	610:813dcc80987e	316	#define RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /!< MSI = 200 KHz /
mbed_official	610:813dcc80987e	317	#define RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /!< MSI = 400 KHz /
mbed_official	610:813dcc80987e	318	#define RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /!< MSI = 800 KHz /
mbed_official	610:813dcc80987e	319	#define RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /!< MSI = 1 MHz /
mbed_official	610:813dcc80987e	320	#define RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /!< MSI = 2 MHz /
mbed_official	610:813dcc80987e	321	#define RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /!< MSI = 4 MHz /
mbed_official	610:813dcc80987e	322	#define RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /!< MSI = 8 MHz /
mbed_official	610:813dcc80987e	323	#define RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /!< MSI = 16 MHz /
mbed_official	610:813dcc80987e	324	#define RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /!< MSI = 24 MHz /
mbed_official	610:813dcc80987e	325	#define RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /!< MSI = 32 MHz /
mbed_official	610:813dcc80987e	326	#define RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /!< MSI = 48 MHz /
mbed_official	610:813dcc80987e	327	/**
mbed_official	610:813dcc80987e	328	* @}
mbed_official	610:813dcc80987e	329	*/
mbed_official	610:813dcc80987e	330
mbed_official	610:813dcc80987e	331	/** @defgroup RCC_System_Clock_Type System Clock Type
mbed_official	610:813dcc80987e	332	* @{
mbed_official	610:813dcc80987e	333	*/
mbed_official	610:813dcc80987e	334	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /!< SYSCLK to configure /
mbed_official	610:813dcc80987e	335	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /!< HCLK to configure /
mbed_official	610:813dcc80987e	336	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /!< PCLK1 to configure /
mbed_official	610:813dcc80987e	337	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) /!< PCLK2 to configure /
mbed_official	610:813dcc80987e	338	/**
mbed_official	610:813dcc80987e	339	* @}
mbed_official	610:813dcc80987e	340	*/
mbed_official	610:813dcc80987e	341
mbed_official	610:813dcc80987e	342	/** @defgroup RCC_System_Clock_Source System Clock Source
mbed_official	610:813dcc80987e	343	* @{
mbed_official	610:813dcc80987e	344	*/
mbed_official	610:813dcc80987e	345	#define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /!< MSI selection as system clock /
mbed_official	610:813dcc80987e	346	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selection as system clock /
mbed_official	610:813dcc80987e	347	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selection as system clock /
mbed_official	610:813dcc80987e	348	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /!< PLL selection as system clock /
mbed_official	610:813dcc80987e	349	/**
mbed_official	610:813dcc80987e	350	* @}
mbed_official	610:813dcc80987e	351	*/
mbed_official	610:813dcc80987e	352
mbed_official	610:813dcc80987e	353	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
mbed_official	610:813dcc80987e	354	* @{
mbed_official	610:813dcc80987e	355	*/
mbed_official	610:813dcc80987e	356	#define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /!< MSI used as system clock /
mbed_official	610:813dcc80987e	357	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
mbed_official	610:813dcc80987e	358	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
mbed_official	610:813dcc80987e	359	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /!< PLL used as system clock /
mbed_official	610:813dcc80987e	360	/**
mbed_official	610:813dcc80987e	361	* @}
mbed_official	610:813dcc80987e	362	*/
mbed_official	610:813dcc80987e	363
mbed_official	610:813dcc80987e	364	/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
mbed_official	610:813dcc80987e	365	* @{
mbed_official	610:813dcc80987e	366	*/
mbed_official	610:813dcc80987e	367	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
mbed_official	610:813dcc80987e	368	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
mbed_official	610:813dcc80987e	369	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
mbed_official	610:813dcc80987e	370	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
mbed_official	610:813dcc80987e	371	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
mbed_official	610:813dcc80987e	372	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
mbed_official	610:813dcc80987e	373	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
mbed_official	610:813dcc80987e	374	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
mbed_official	610:813dcc80987e	375	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
mbed_official	610:813dcc80987e	376	/**
mbed_official	610:813dcc80987e	377	* @}
mbed_official	610:813dcc80987e	378	*/
mbed_official	610:813dcc80987e	379
mbed_official	610:813dcc80987e	380	/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
mbed_official	610:813dcc80987e	381	* @{
mbed_official	610:813dcc80987e	382	*/
mbed_official	610:813dcc80987e	383	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
mbed_official	610:813dcc80987e	384	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
mbed_official	610:813dcc80987e	385	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
mbed_official	610:813dcc80987e	386	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
mbed_official	610:813dcc80987e	387	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
mbed_official	610:813dcc80987e	388	/**
mbed_official	610:813dcc80987e	389	* @}
mbed_official	610:813dcc80987e	390	*/
mbed_official	610:813dcc80987e	391
mbed_official	610:813dcc80987e	392	/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
mbed_official	610:813dcc80987e	393	* @{
mbed_official	610:813dcc80987e	394	*/
mbed_official	610:813dcc80987e	395	#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /!< LSE oscillator clock used as RTC clock /
mbed_official	610:813dcc80987e	396	#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /!< LSI oscillator clock used as RTC clock /
mbed_official	610:813dcc80987e	397	#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /!< HSE oscillator clock divided by 32 used as RTC clock /
mbed_official	610:813dcc80987e	398	/**
mbed_official	610:813dcc80987e	399	* @}
mbed_official	610:813dcc80987e	400	*/
mbed_official	610:813dcc80987e	401
mbed_official	610:813dcc80987e	402	/** @defgroup RCC_MCO_Index MCO Index
mbed_official	610:813dcc80987e	403	* @{
mbed_official	610:813dcc80987e	404	*/
mbed_official	610:813dcc80987e	405	#define RCC_MCO1 ((uint32_t)0x00000000)
mbed_official	610:813dcc80987e	406	#define RCC_MCO RCC_MCO1 /!< MCO1 to be compliant with other families with 2 MCOs/
mbed_official	610:813dcc80987e	407	/**
mbed_official	610:813dcc80987e	408	* @}
mbed_official	610:813dcc80987e	409	*/
mbed_official	610:813dcc80987e	410
mbed_official	610:813dcc80987e	411	/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
mbed_official	610:813dcc80987e	412	* @{
mbed_official	610:813dcc80987e	413	*/
mbed_official	610:813dcc80987e	414	#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /!< SYSCLK selection as MCO1 source /
mbed_official	610:813dcc80987e	415	#define RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /!< MSI selection as MCO1 source /
mbed_official	610:813dcc80987e	416	#define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0\| RCC_CFGR_MCOSEL_1) /!< HSI selection as MCO1 source /
mbed_official	610:813dcc80987e	417	#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /!< HSE selection as MCO1 source /
mbed_official	610:813dcc80987e	418	#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0\|RCC_CFGR_MCOSEL_2) /!< PLLCLK selection as MCO1 source /
mbed_official	610:813dcc80987e	419	#define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1\|RCC_CFGR_MCOSEL_2) /!< LSI selection as MCO1 source /
mbed_official	610:813dcc80987e	420	#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL /!< LSE selection as MCO1 source /
mbed_official	610:813dcc80987e	421	/**
mbed_official	610:813dcc80987e	422	* @}
mbed_official	610:813dcc80987e	423	*/
mbed_official	610:813dcc80987e	424
mbed_official	610:813dcc80987e	425	/** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler
mbed_official	610:813dcc80987e	426	* @{
mbed_official	610:813dcc80987e	427	*/
mbed_official	610:813dcc80987e	428	#define RCC_MCODIV_1 RCC_CFGR_MCO_PRE_1 /!< MCO not divided /
mbed_official	610:813dcc80987e	429	#define RCC_MCODIV_2 RCC_CFGR_MCO_PRE_2 /!< MCO divided by 2 /
mbed_official	610:813dcc80987e	430	#define RCC_MCODIV_4 RCC_CFGR_MCO_PRE_4 /!< MCO divided by 4 /
mbed_official	610:813dcc80987e	431	#define RCC_MCODIV_8 RCC_CFGR_MCO_PRE_8 /!< MCO divided by 8 /
mbed_official	610:813dcc80987e	432	#define RCC_MCODIV_16 RCC_CFGR_MCO_PRE_16 /!< MCO divided by 16 /
mbed_official	610:813dcc80987e	433	/**
mbed_official	610:813dcc80987e	434	* @}
mbed_official	610:813dcc80987e	435	*/
mbed_official	610:813dcc80987e	436
mbed_official	610:813dcc80987e	437	/** @defgroup RCC_Interrupt Interrupts
mbed_official	610:813dcc80987e	438	* @{
mbed_official	610:813dcc80987e	439	*/
mbed_official	610:813dcc80987e	440	#define RCC_IT_LSIRDY ((uint32_t)0x00000001) /!< LSI Ready Interrupt flag /
mbed_official	610:813dcc80987e	441	#define RCC_IT_LSERDY ((uint32_t)0x00000002) /!< LSE Ready Interrupt flag /
mbed_official	610:813dcc80987e	442	#define RCC_IT_MSIRDY ((uint32_t)0x00000004) /!< MSI Ready Interrupt flag /
mbed_official	610:813dcc80987e	443	#define RCC_IT_HSIRDY ((uint32_t)0x00000008) /!< HSI Ready Interrupt flag /
mbed_official	610:813dcc80987e	444	#define RCC_IT_HSERDY ((uint32_t)0x00000010) /!< HSE Ready Interrupt flag /
mbed_official	610:813dcc80987e	445	#define RCC_IT_PLLRDY ((uint32_t)0x00000020) /!< PLL Ready Interrupt flag /
mbed_official	610:813dcc80987e	446	#define RCC_IT_PLLSAI1RDY ((uint32_t)0x00000040) /!< PLLSAI1 Ready Interrupt flag /
mbed_official	610:813dcc80987e	447	#define RCC_IT_PLLSAI2RDY ((uint32_t)0x00000080) /!< PLLSAI2 Ready Interrupt flag /
mbed_official	610:813dcc80987e	448	#define RCC_IT_CSS ((uint32_t)0x00000100) /!< Clock Security System Interrupt flag /
mbed_official	610:813dcc80987e	449	#define RCC_IT_LSECSS ((uint32_t)0x00000200) /!< LSE Clock Security System Interrupt flag /
mbed_official	610:813dcc80987e	450	/**
mbed_official	610:813dcc80987e	451	* @}
mbed_official	610:813dcc80987e	452	*/
mbed_official	610:813dcc80987e	453
mbed_official	610:813dcc80987e	454	/** @defgroup RCC_Flag Flags
mbed_official	610:813dcc80987e	455	* Elements values convention: 0XXYYYYYb
mbed_official	610:813dcc80987e	456	* - YYYYY : Flag position in the register
mbed_official	610:813dcc80987e	457	* - 0XX : Register index
mbed_official	610:813dcc80987e	458	* - 01: CR register
mbed_official	610:813dcc80987e	459	* - 10: BDCR register
mbed_official	610:813dcc80987e	460	* - 11: CSR register
mbed_official	610:813dcc80987e	461	* @{
mbed_official	610:813dcc80987e	462	*/
mbed_official	610:813dcc80987e	463	/* Flags in the CR register */
mbed_official	610:813dcc80987e	464	#define RCC_FLAG_MSIRDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_MSIRDY))) /!< MSI Ready flag /
mbed_official	610:813dcc80987e	465	#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_HSIRDY))) /!< HSI Ready flag /
mbed_official	610:813dcc80987e	466	#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_HSERDY))) /!< HSE Ready flag /
mbed_official	610:813dcc80987e	467	#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_PLLRDY))) /!< PLL Ready flag /
mbed_official	610:813dcc80987e	468	#define RCC_FLAG_PLLSAI1RDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_PLLSAI1RDY))) /!< PLLSAI1 Ready flag /
mbed_official	610:813dcc80987e	469	#define RCC_FLAG_PLLSAI2RDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_PLLSAI2RDY))) /!< PLLSAI2 Ready flag /
mbed_official	610:813dcc80987e	470
mbed_official	610:813dcc80987e	471	/* Flags in the BDCR register */
mbed_official	610:813dcc80987e	472	#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) \| POSITION_VAL(RCC_BDCR_LSERDY))) /!< LSE Ready flag /
mbed_official	610:813dcc80987e	473	#define RCC_FLAG_LSECSSD ((uint8_t)((BDCR_REG_INDEX << 5) \| POSITION_VAL(RCC_BDCR_LSECSSD))) /!< LSE Clock Security System Interrupt flag /
mbed_official	610:813dcc80987e	474
mbed_official	610:813dcc80987e	475	/* Flags in the CSR register */
mbed_official	610:813dcc80987e	476	#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_LSIRDY))) /!< LSI Ready flag /
mbed_official	610:813dcc80987e	477	#define RCC_FLAG_RMVF ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_RMVF))) /!< Remove reset flag /
mbed_official	610:813dcc80987e	478	#define RCC_FLAG_FWRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_FWRSTF))) /!< Firewall reset flag /
mbed_official	610:813dcc80987e	479	#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_OBLRSTF))) /!< Option Byte Loader reset flag /
mbed_official	610:813dcc80987e	480	#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_PINRSTF))) /!< PIN reset flag /
mbed_official	610:813dcc80987e	481	#define RCC_FLAG_BORRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_BORRSTF))) /!< BOR reset flag /
mbed_official	610:813dcc80987e	482	#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_SFTRSTF))) /!< Software Reset flag /
mbed_official	610:813dcc80987e	483	#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_IWDGRSTF))) /!< Independent Watchdog reset flag /
mbed_official	610:813dcc80987e	484	#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_WWDGRSTF))) /!< Window watchdog reset flag /
mbed_official	610:813dcc80987e	485	#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_LPWRRSTF))) /!< Low-Power reset flag /
mbed_official	610:813dcc80987e	486	/**
mbed_official	610:813dcc80987e	487	* @}
mbed_official	610:813dcc80987e	488	*/
mbed_official	610:813dcc80987e	489
mbed_official	610:813dcc80987e	490	/** @defgroup RCC_LSEDrive_Config LSE Drive Config
mbed_official	610:813dcc80987e	491	* @{
mbed_official	610:813dcc80987e	492	*/
mbed_official	610:813dcc80987e	493	#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000) /!< LSE low drive capability /
mbed_official	610:813dcc80987e	494	#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /!< LSE medium low drive capability /
mbed_official	610:813dcc80987e	495	/* Workaround implementation on medium low */
mbed_official	610:813dcc80987e	496	#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /!< LSE medium high drive capability /
mbed_official	610:813dcc80987e	497	/* Workaround implementation on medium high */
mbed_official	610:813dcc80987e	498	#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /!< LSE high drive capability /
mbed_official	610:813dcc80987e	499	/**
mbed_official	610:813dcc80987e	500	* @}
mbed_official	610:813dcc80987e	501	*/
mbed_official	610:813dcc80987e	502
mbed_official	610:813dcc80987e	503	/** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock
mbed_official	610:813dcc80987e	504	* @{
mbed_official	610:813dcc80987e	505	*/
mbed_official	610:813dcc80987e	506	#define RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00000000) /!< MSI selection after wake-up from STOP /
mbed_official	610:813dcc80987e	507	#define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /!< HSI selection after wake-up from STOP /
mbed_official	610:813dcc80987e	508	/**
mbed_official	610:813dcc80987e	509	* @}
mbed_official	610:813dcc80987e	510	*/
mbed_official	610:813dcc80987e	511
mbed_official	610:813dcc80987e	512	/**
mbed_official	610:813dcc80987e	513	* @}
mbed_official	610:813dcc80987e	514	*/
mbed_official	610:813dcc80987e	515
mbed_official	610:813dcc80987e	516	/* Exported macros -----------------------------------------------------------*/
mbed_official	610:813dcc80987e	517
mbed_official	610:813dcc80987e	518	/** @defgroup RCC_Exported_Macros RCC Exported Macros
mbed_official	610:813dcc80987e	519	* @{
mbed_official	610:813dcc80987e	520	*/
mbed_official	610:813dcc80987e	521
mbed_official	610:813dcc80987e	522	/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
mbed_official	610:813dcc80987e	523	* @brief Enable or disable the AHB1 peripheral clock.
mbed_official	610:813dcc80987e	524	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	610:813dcc80987e	525	* is disabled and the application software has to enable this clock before
mbed_official	610:813dcc80987e	526	* using it.
mbed_official	610:813dcc80987e	527	* @{
mbed_official	610:813dcc80987e	528	*/
mbed_official	610:813dcc80987e	529
mbed_official	610:813dcc80987e	530	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	531	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	532	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
mbed_official	610:813dcc80987e	533	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	534	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
mbed_official	610:813dcc80987e	535	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	536	} while(0)
mbed_official	610:813dcc80987e	537
mbed_official	610:813dcc80987e	538	#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	539	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	540	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
mbed_official	610:813dcc80987e	541	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	542	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
mbed_official	610:813dcc80987e	543	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	544	} while(0)
mbed_official	610:813dcc80987e	545
mbed_official	610:813dcc80987e	546	#define __HAL_RCC_FLASH_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	547	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	548	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
mbed_official	610:813dcc80987e	549	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	550	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
mbed_official	610:813dcc80987e	551	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	552	} while(0)
mbed_official	610:813dcc80987e	553
mbed_official	610:813dcc80987e	554	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	555	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	556	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
mbed_official	610:813dcc80987e	557	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	558	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
mbed_official	610:813dcc80987e	559	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	560	} while(0)
mbed_official	610:813dcc80987e	561
mbed_official	610:813dcc80987e	562	#define __HAL_RCC_TSC_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	563	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	564	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
mbed_official	610:813dcc80987e	565	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	566	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
mbed_official	610:813dcc80987e	567	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	568	} while(0)
mbed_official	610:813dcc80987e	569
mbed_official	610:813dcc80987e	570	#define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN)
mbed_official	610:813dcc80987e	571
mbed_official	610:813dcc80987e	572	#define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN)
mbed_official	610:813dcc80987e	573
mbed_official	610:813dcc80987e	574	#define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)
mbed_official	610:813dcc80987e	575
mbed_official	610:813dcc80987e	576	#define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN)
mbed_official	610:813dcc80987e	577
mbed_official	610:813dcc80987e	578	#define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN)
mbed_official	610:813dcc80987e	579
mbed_official	610:813dcc80987e	580	/**
mbed_official	610:813dcc80987e	581	* @}
mbed_official	610:813dcc80987e	582	*/
mbed_official	610:813dcc80987e	583
mbed_official	610:813dcc80987e	584	/** @defgroup RCC_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
mbed_official	610:813dcc80987e	585	* @brief Enable or disable the AHB2 peripheral clock.
mbed_official	610:813dcc80987e	586	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	610:813dcc80987e	587	* is disabled and the application software has to enable this clock before
mbed_official	610:813dcc80987e	588	* using it.
mbed_official	610:813dcc80987e	589	* @{
mbed_official	610:813dcc80987e	590	*/
mbed_official	610:813dcc80987e	591
mbed_official	610:813dcc80987e	592	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	593	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	594	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
mbed_official	610:813dcc80987e	595	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	596	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
mbed_official	610:813dcc80987e	597	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	598	} while(0)
mbed_official	610:813dcc80987e	599
mbed_official	610:813dcc80987e	600	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	601	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	602	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
mbed_official	610:813dcc80987e	603	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	604	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
mbed_official	610:813dcc80987e	605	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	606	} while(0)
mbed_official	610:813dcc80987e	607
mbed_official	610:813dcc80987e	608	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	609	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	610	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
mbed_official	610:813dcc80987e	611	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	612	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
mbed_official	610:813dcc80987e	613	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	614	} while(0)
mbed_official	610:813dcc80987e	615
mbed_official	610:813dcc80987e	616	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	617	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	618	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
mbed_official	610:813dcc80987e	619	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	620	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
mbed_official	610:813dcc80987e	621	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	622	} while(0)
mbed_official	610:813dcc80987e	623
mbed_official	610:813dcc80987e	624	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	625	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	626	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
mbed_official	610:813dcc80987e	627	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	628	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
mbed_official	610:813dcc80987e	629	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	630	} while(0)
mbed_official	610:813dcc80987e	631
mbed_official	610:813dcc80987e	632	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	633	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	634	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
mbed_official	610:813dcc80987e	635	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	636	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
mbed_official	610:813dcc80987e	637	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	638	} while(0)
mbed_official	610:813dcc80987e	639
mbed_official	610:813dcc80987e	640	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	641	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	642	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
mbed_official	610:813dcc80987e	643	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	644	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
mbed_official	610:813dcc80987e	645	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	646	} while(0)
mbed_official	610:813dcc80987e	647
mbed_official	610:813dcc80987e	648	#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	649	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	650	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
mbed_official	610:813dcc80987e	651	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	652	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
mbed_official	610:813dcc80987e	653	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	654	} while(0)
mbed_official	610:813dcc80987e	655
mbed_official	610:813dcc80987e	656	#define __HAL_RCC_ADC_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	657	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	658	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
mbed_official	610:813dcc80987e	659	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	660	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
mbed_official	610:813dcc80987e	661	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	662	} while(0)
mbed_official	610:813dcc80987e	663
mbed_official	610:813dcc80987e	664	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	665	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	666	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
mbed_official	610:813dcc80987e	667	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	668	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
mbed_official	610:813dcc80987e	669	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	670	} while(0)
mbed_official	610:813dcc80987e	671
mbed_official	610:813dcc80987e	672	#define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN)
mbed_official	610:813dcc80987e	673
mbed_official	610:813dcc80987e	674	#define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN)
mbed_official	610:813dcc80987e	675
mbed_official	610:813dcc80987e	676	#define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN)
mbed_official	610:813dcc80987e	677
mbed_official	610:813dcc80987e	678	#define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN)
mbed_official	610:813dcc80987e	679
mbed_official	610:813dcc80987e	680	#define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN)
mbed_official	610:813dcc80987e	681
mbed_official	610:813dcc80987e	682	#define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN)
mbed_official	610:813dcc80987e	683
mbed_official	610:813dcc80987e	684	#define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN)
mbed_official	610:813dcc80987e	685
mbed_official	610:813dcc80987e	686	#define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN)
mbed_official	610:813dcc80987e	687
mbed_official	610:813dcc80987e	688	#define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN)
mbed_official	610:813dcc80987e	689
mbed_official	610:813dcc80987e	690	#define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN)
mbed_official	610:813dcc80987e	691
mbed_official	610:813dcc80987e	692	/**
mbed_official	610:813dcc80987e	693	* @}
mbed_official	610:813dcc80987e	694	*/
mbed_official	610:813dcc80987e	695
mbed_official	610:813dcc80987e	696	/** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
mbed_official	610:813dcc80987e	697	* @brief Enable or disable the AHB3 peripheral clock.
mbed_official	610:813dcc80987e	698	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	610:813dcc80987e	699	* is disabled and the application software has to enable this clock before
mbed_official	610:813dcc80987e	700	* using it.
mbed_official	610:813dcc80987e	701	* @{
mbed_official	610:813dcc80987e	702	*/
mbed_official	610:813dcc80987e	703
mbed_official	610:813dcc80987e	704	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	705	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	706	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
mbed_official	610:813dcc80987e	707	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	708	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
mbed_official	610:813dcc80987e	709	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	710	} while(0)
mbed_official	610:813dcc80987e	711
mbed_official	610:813dcc80987e	712	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	713	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	714	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
mbed_official	610:813dcc80987e	715	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	716	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
mbed_official	610:813dcc80987e	717	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	718	} while(0)
mbed_official	610:813dcc80987e	719
mbed_official	610:813dcc80987e	720	#define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)
mbed_official	610:813dcc80987e	721
mbed_official	610:813dcc80987e	722	#define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN)
mbed_official	610:813dcc80987e	723
mbed_official	610:813dcc80987e	724	/**
mbed_official	610:813dcc80987e	725	* @}
mbed_official	610:813dcc80987e	726	*/
mbed_official	610:813dcc80987e	727
mbed_official	610:813dcc80987e	728	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
mbed_official	610:813dcc80987e	729	* @brief Enable or disable the APB1 peripheral clock.
mbed_official	610:813dcc80987e	730	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	610:813dcc80987e	731	* is disabled and the application software has to enable this clock before
mbed_official	610:813dcc80987e	732	* using it.
mbed_official	610:813dcc80987e	733	* @{
mbed_official	610:813dcc80987e	734	*/
mbed_official	610:813dcc80987e	735
mbed_official	610:813dcc80987e	736	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	737	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	738	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
mbed_official	610:813dcc80987e	739	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	740	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
mbed_official	610:813dcc80987e	741	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	742	} while(0)
mbed_official	610:813dcc80987e	743
mbed_official	610:813dcc80987e	744	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	745	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	746	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
mbed_official	610:813dcc80987e	747	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	748	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
mbed_official	610:813dcc80987e	749	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	750	} while(0)
mbed_official	610:813dcc80987e	751
mbed_official	610:813dcc80987e	752	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	753	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	754	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
mbed_official	610:813dcc80987e	755	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	756	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
mbed_official	610:813dcc80987e	757	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	758	} while(0)
mbed_official	610:813dcc80987e	759
mbed_official	610:813dcc80987e	760	#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	761	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	762	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
mbed_official	610:813dcc80987e	763	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	764	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
mbed_official	610:813dcc80987e	765	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	766	} while(0)
mbed_official	610:813dcc80987e	767
mbed_official	610:813dcc80987e	768	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	769	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	770	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
mbed_official	610:813dcc80987e	771	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	772	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
mbed_official	610:813dcc80987e	773	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	774	} while(0)
mbed_official	610:813dcc80987e	775
mbed_official	610:813dcc80987e	776	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	777	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	778	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
mbed_official	610:813dcc80987e	779	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	780	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
mbed_official	610:813dcc80987e	781	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	782	} while(0)
mbed_official	610:813dcc80987e	783
mbed_official	610:813dcc80987e	784	#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	785	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	786	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
mbed_official	610:813dcc80987e	787	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	788	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
mbed_official	610:813dcc80987e	789	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	790	} while(0)
mbed_official	610:813dcc80987e	791
mbed_official	610:813dcc80987e	792	#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	793	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	794	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
mbed_official	610:813dcc80987e	795	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	796	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
mbed_official	610:813dcc80987e	797	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	798	} while(0)
mbed_official	610:813dcc80987e	799
mbed_official	610:813dcc80987e	800	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	801	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	802	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
mbed_official	610:813dcc80987e	803	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	804	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
mbed_official	610:813dcc80987e	805	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	806	} while(0)
mbed_official	610:813dcc80987e	807
mbed_official	610:813dcc80987e	808	#define __HAL_RCC_USART2_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	809	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	810	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
mbed_official	610:813dcc80987e	811	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	812	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
mbed_official	610:813dcc80987e	813	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	814	} while(0)
mbed_official	610:813dcc80987e	815
mbed_official	610:813dcc80987e	816	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	817	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	818	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
mbed_official	610:813dcc80987e	819	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	820	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
mbed_official	610:813dcc80987e	821	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	822	} while(0)
mbed_official	610:813dcc80987e	823
mbed_official	610:813dcc80987e	824	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	825	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	826	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
mbed_official	610:813dcc80987e	827	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	828	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
mbed_official	610:813dcc80987e	829	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	830	} while(0)
mbed_official	610:813dcc80987e	831
mbed_official	610:813dcc80987e	832	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	833	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	834	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
mbed_official	610:813dcc80987e	835	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	836	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
mbed_official	610:813dcc80987e	837	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	838	} while(0)
mbed_official	610:813dcc80987e	839
mbed_official	610:813dcc80987e	840	#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	841	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	842	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
mbed_official	610:813dcc80987e	843	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	844	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
mbed_official	610:813dcc80987e	845	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	846	} while(0)
mbed_official	610:813dcc80987e	847
mbed_official	610:813dcc80987e	848	#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	849	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	850	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
mbed_official	610:813dcc80987e	851	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	852	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
mbed_official	610:813dcc80987e	853	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	854	} while(0)
mbed_official	610:813dcc80987e	855
mbed_official	610:813dcc80987e	856	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	857	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	858	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
mbed_official	610:813dcc80987e	859	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	860	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
mbed_official	610:813dcc80987e	861	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	862	} while(0)
mbed_official	610:813dcc80987e	863
mbed_official	610:813dcc80987e	864	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	865	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	866	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \
mbed_official	610:813dcc80987e	867	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	868	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \
mbed_official	610:813dcc80987e	869	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	870	} while(0)
mbed_official	610:813dcc80987e	871
mbed_official	610:813dcc80987e	872	#define __HAL_RCC_PWR_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	873	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	874	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
mbed_official	610:813dcc80987e	875	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	876	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
mbed_official	610:813dcc80987e	877	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	878	} while(0)
mbed_official	610:813dcc80987e	879
mbed_official	610:813dcc80987e	880	#define __HAL_RCC_DAC1_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	881	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	882	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
mbed_official	610:813dcc80987e	883	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	884	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
mbed_official	610:813dcc80987e	885	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	886	} while(0)
mbed_official	610:813dcc80987e	887
mbed_official	610:813dcc80987e	888	#define __HAL_RCC_OPAMP_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	889	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	890	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
mbed_official	610:813dcc80987e	891	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	892	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
mbed_official	610:813dcc80987e	893	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	894	} while(0)
mbed_official	610:813dcc80987e	895
mbed_official	610:813dcc80987e	896	#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	897	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	898	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
mbed_official	610:813dcc80987e	899	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	900	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
mbed_official	610:813dcc80987e	901	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	902	} while(0)
mbed_official	610:813dcc80987e	903
mbed_official	610:813dcc80987e	904	#define __HAL_RCC_LPUART1_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	905	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	906	SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
mbed_official	610:813dcc80987e	907	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	908	tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
mbed_official	610:813dcc80987e	909	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	910	} while(0)
mbed_official	610:813dcc80987e	911
mbed_official	610:813dcc80987e	912	#define __HAL_RCC_SWPMI1_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	913	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	914	SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
mbed_official	610:813dcc80987e	915	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	916	tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
mbed_official	610:813dcc80987e	917	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	918	} while(0)
mbed_official	610:813dcc80987e	919
mbed_official	610:813dcc80987e	920	#define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	921	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	922	SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
mbed_official	610:813dcc80987e	923	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	924	tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
mbed_official	610:813dcc80987e	925	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	926	} while(0)
mbed_official	610:813dcc80987e	927
mbed_official	610:813dcc80987e	928	#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)
mbed_official	610:813dcc80987e	929
mbed_official	610:813dcc80987e	930	#define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)
mbed_official	610:813dcc80987e	931
mbed_official	610:813dcc80987e	932	#define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN)
mbed_official	610:813dcc80987e	933
mbed_official	610:813dcc80987e	934	#define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)
mbed_official	610:813dcc80987e	935
mbed_official	610:813dcc80987e	936	#define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN)
mbed_official	610:813dcc80987e	937
mbed_official	610:813dcc80987e	938	#define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)
mbed_official	610:813dcc80987e	939
mbed_official	610:813dcc80987e	940	#define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN)
mbed_official	610:813dcc80987e	941
mbed_official	610:813dcc80987e	942	#define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)
mbed_official	610:813dcc80987e	943
mbed_official	610:813dcc80987e	944	#define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN)
mbed_official	610:813dcc80987e	945
mbed_official	610:813dcc80987e	946	#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)
mbed_official	610:813dcc80987e	947
mbed_official	610:813dcc80987e	948	#define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)
mbed_official	610:813dcc80987e	949
mbed_official	610:813dcc80987e	950	#define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN)
mbed_official	610:813dcc80987e	951
mbed_official	610:813dcc80987e	952	#define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN)
mbed_official	610:813dcc80987e	953
mbed_official	610:813dcc80987e	954	#define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN)
mbed_official	610:813dcc80987e	955
mbed_official	610:813dcc80987e	956	#define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN)
mbed_official	610:813dcc80987e	957
mbed_official	610:813dcc80987e	958	#define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN)
mbed_official	610:813dcc80987e	959
mbed_official	610:813dcc80987e	960	#define __HAL_RCC_CAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN)
mbed_official	610:813dcc80987e	961
mbed_official	610:813dcc80987e	962	#define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)
mbed_official	610:813dcc80987e	963
mbed_official	610:813dcc80987e	964	#define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN)
mbed_official	610:813dcc80987e	965
mbed_official	610:813dcc80987e	966	#define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN)
mbed_official	610:813dcc80987e	967
mbed_official	610:813dcc80987e	968	#define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN)
mbed_official	610:813dcc80987e	969
mbed_official	610:813dcc80987e	970	#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN)
mbed_official	610:813dcc80987e	971
mbed_official	610:813dcc80987e	972	#define __HAL_RCC_SWPMI1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN)
mbed_official	610:813dcc80987e	973
mbed_official	610:813dcc80987e	974	#define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN)
mbed_official	610:813dcc80987e	975
mbed_official	610:813dcc80987e	976	/**
mbed_official	610:813dcc80987e	977	* @}
mbed_official	610:813dcc80987e	978	*/
mbed_official	610:813dcc80987e	979
mbed_official	610:813dcc80987e	980	/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
mbed_official	610:813dcc80987e	981	* @brief Enable or disable the APB2 peripheral clock.
mbed_official	610:813dcc80987e	982	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	610:813dcc80987e	983	* is disabled and the application software has to enable this clock before
mbed_official	610:813dcc80987e	984	* using it.
mbed_official	610:813dcc80987e	985	* @{
mbed_official	610:813dcc80987e	986	*/
mbed_official	610:813dcc80987e	987
mbed_official	610:813dcc80987e	988	#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	989	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	990	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
mbed_official	610:813dcc80987e	991	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	992	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
mbed_official	610:813dcc80987e	993	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	994	} while(0)
mbed_official	610:813dcc80987e	995
mbed_official	610:813dcc80987e	996	#define __HAL_RCC_FIREWALL_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	997	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	998	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
mbed_official	610:813dcc80987e	999	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	1000	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
mbed_official	610:813dcc80987e	1001	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	1002	} while(0)
mbed_official	610:813dcc80987e	1003
mbed_official	610:813dcc80987e	1004	#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	1005	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	1006	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
mbed_official	610:813dcc80987e	1007	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	1008	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
mbed_official	610:813dcc80987e	1009	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	1010	} while(0)
mbed_official	610:813dcc80987e	1011
mbed_official	610:813dcc80987e	1012	#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	1013	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	1014	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
mbed_official	610:813dcc80987e	1015	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	1016	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
mbed_official	610:813dcc80987e	1017	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	1018	} while(0)
mbed_official	610:813dcc80987e	1019
mbed_official	610:813dcc80987e	1020	#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	1021	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	1022	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
mbed_official	610:813dcc80987e	1023	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	1024	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
mbed_official	610:813dcc80987e	1025	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	1026	} while(0)
mbed_official	610:813dcc80987e	1027
mbed_official	610:813dcc80987e	1028	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	1029	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	1030	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
mbed_official	610:813dcc80987e	1031	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	1032	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
mbed_official	610:813dcc80987e	1033	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	1034	} while(0)
mbed_official	610:813dcc80987e	1035
mbed_official	610:813dcc80987e	1036	#define __HAL_RCC_USART1_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	1037	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	1038	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
mbed_official	610:813dcc80987e	1039	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	1040	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
mbed_official	610:813dcc80987e	1041	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	1042	} while(0)
mbed_official	610:813dcc80987e	1043
mbed_official	610:813dcc80987e	1044
mbed_official	610:813dcc80987e	1045	#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	1046	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	1047	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
mbed_official	610:813dcc80987e	1048	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	1049	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
mbed_official	610:813dcc80987e	1050	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	1051	} while(0)
mbed_official	610:813dcc80987e	1052
mbed_official	610:813dcc80987e	1053	#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	1054	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	1055	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
mbed_official	610:813dcc80987e	1056	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	1057	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
mbed_official	610:813dcc80987e	1058	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	1059	} while(0)
mbed_official	610:813dcc80987e	1060
mbed_official	610:813dcc80987e	1061	#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	1062	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	1063	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
mbed_official	610:813dcc80987e	1064	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	1065	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
mbed_official	610:813dcc80987e	1066	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	1067	} while(0)
mbed_official	610:813dcc80987e	1068
mbed_official	610:813dcc80987e	1069	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	1070	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	1071	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
mbed_official	610:813dcc80987e	1072	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	1073	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
mbed_official	610:813dcc80987e	1074	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	1075	} while(0)
mbed_official	610:813dcc80987e	1076
mbed_official	610:813dcc80987e	1077	#define __HAL_RCC_SAI2_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	1078	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	1079	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
mbed_official	610:813dcc80987e	1080	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	1081	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
mbed_official	610:813dcc80987e	1082	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	1083	} while(0)
mbed_official	610:813dcc80987e	1084
mbed_official	610:813dcc80987e	1085	#define __HAL_RCC_DFSDM_CLK_ENABLE() do { \
mbed_official	610:813dcc80987e	1086	__IO uint32_t tmpreg; \
mbed_official	610:813dcc80987e	1087	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDMEN); \
mbed_official	610:813dcc80987e	1088	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	610:813dcc80987e	1089	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDMEN); \
mbed_official	610:813dcc80987e	1090	UNUSED(tmpreg); \
mbed_official	610:813dcc80987e	1091	} while(0)
mbed_official	610:813dcc80987e	1092
mbed_official	610:813dcc80987e	1093	#define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN)
mbed_official	610:813dcc80987e	1094
mbed_official	610:813dcc80987e	1095	#define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN)
mbed_official	610:813dcc80987e	1096
mbed_official	610:813dcc80987e	1097	#define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)
mbed_official	610:813dcc80987e	1098
mbed_official	610:813dcc80987e	1099	#define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN)
mbed_official	610:813dcc80987e	1100
mbed_official	610:813dcc80987e	1101	#define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN)
mbed_official	610:813dcc80987e	1102
mbed_official	610:813dcc80987e	1103	#define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)
mbed_official	610:813dcc80987e	1104
mbed_official	610:813dcc80987e	1105	#define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN)
mbed_official	610:813dcc80987e	1106
mbed_official	610:813dcc80987e	1107	#define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN)
mbed_official	610:813dcc80987e	1108
mbed_official	610:813dcc80987e	1109	#define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN)
mbed_official	610:813dcc80987e	1110
mbed_official	610:813dcc80987e	1111	#define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)
mbed_official	610:813dcc80987e	1112
mbed_official	610:813dcc80987e	1113	#define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN)
mbed_official	610:813dcc80987e	1114
mbed_official	610:813dcc80987e	1115	#define __HAL_RCC_DFSDM_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDMEN)
mbed_official	610:813dcc80987e	1116
mbed_official	610:813dcc80987e	1117	/**
mbed_official	610:813dcc80987e	1118	* @}
mbed_official	610:813dcc80987e	1119	*/
mbed_official	610:813dcc80987e	1120
mbed_official	610:813dcc80987e	1121	/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status
mbed_official	610:813dcc80987e	1122	* @brief Check whether the AHB1 peripheral clock is enabled or not.
mbed_official	610:813dcc80987e	1123	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	610:813dcc80987e	1124	* is disabled and the application software has to enable this clock before
mbed_official	610:813dcc80987e	1125	* using it.
mbed_official	610:813dcc80987e	1126	* @{
mbed_official	610:813dcc80987e	1127	*/
mbed_official	610:813dcc80987e	1128
mbed_official	610:813dcc80987e	1129	#define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != RESET)
mbed_official	610:813dcc80987e	1130
mbed_official	610:813dcc80987e	1131	#define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != RESET)
mbed_official	610:813dcc80987e	1132
mbed_official	610:813dcc80987e	1133	#define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != RESET)
mbed_official	610:813dcc80987e	1134
mbed_official	610:813dcc80987e	1135	#define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != RESET)
mbed_official	610:813dcc80987e	1136
mbed_official	610:813dcc80987e	1137	#define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != RESET)
mbed_official	610:813dcc80987e	1138
mbed_official	610:813dcc80987e	1139	#define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == RESET)
mbed_official	610:813dcc80987e	1140
mbed_official	610:813dcc80987e	1141	#define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == RESET)
mbed_official	610:813dcc80987e	1142
mbed_official	610:813dcc80987e	1143	#define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == RESET)
mbed_official	610:813dcc80987e	1144
mbed_official	610:813dcc80987e	1145	#define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == RESET)
mbed_official	610:813dcc80987e	1146
mbed_official	610:813dcc80987e	1147	#define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == RESET)
mbed_official	610:813dcc80987e	1148
mbed_official	610:813dcc80987e	1149	/**
mbed_official	610:813dcc80987e	1150	* @}
mbed_official	610:813dcc80987e	1151	*/
mbed_official	610:813dcc80987e	1152
mbed_official	610:813dcc80987e	1153	/** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status
mbed_official	610:813dcc80987e	1154	* @brief Check whether the AHB2 peripheral clock is enabled or not.
mbed_official	610:813dcc80987e	1155	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	610:813dcc80987e	1156	* is disabled and the application software has to enable this clock before
mbed_official	610:813dcc80987e	1157	* using it.
mbed_official	610:813dcc80987e	1158	* @{
mbed_official	610:813dcc80987e	1159	*/
mbed_official	610:813dcc80987e	1160
mbed_official	610:813dcc80987e	1161	#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != RESET)
mbed_official	610:813dcc80987e	1162
mbed_official	610:813dcc80987e	1163	#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET)
mbed_official	610:813dcc80987e	1164
mbed_official	610:813dcc80987e	1165	#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET)
mbed_official	610:813dcc80987e	1166
mbed_official	610:813dcc80987e	1167	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != RESET)
mbed_official	610:813dcc80987e	1168
mbed_official	610:813dcc80987e	1169	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != RESET)
mbed_official	610:813dcc80987e	1170
mbed_official	610:813dcc80987e	1171	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != RESET)
mbed_official	610:813dcc80987e	1172
mbed_official	610:813dcc80987e	1173	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != RESET)
mbed_official	610:813dcc80987e	1174
mbed_official	610:813dcc80987e	1175	#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != RESET)
mbed_official	610:813dcc80987e	1176
mbed_official	610:813dcc80987e	1177	#define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != RESET)
mbed_official	610:813dcc80987e	1178
mbed_official	610:813dcc80987e	1179	#define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != RESET)
mbed_official	610:813dcc80987e	1180
mbed_official	610:813dcc80987e	1181	#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == RESET)
mbed_official	610:813dcc80987e	1182
mbed_official	610:813dcc80987e	1183	#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == RESET)
mbed_official	610:813dcc80987e	1184
mbed_official	610:813dcc80987e	1185	#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == RESET)
mbed_official	610:813dcc80987e	1186
mbed_official	610:813dcc80987e	1187	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == RESET)
mbed_official	610:813dcc80987e	1188
mbed_official	610:813dcc80987e	1189	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == RESET)
mbed_official	610:813dcc80987e	1190
mbed_official	610:813dcc80987e	1191	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == RESET)
mbed_official	610:813dcc80987e	1192
mbed_official	610:813dcc80987e	1193	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == RESET)
mbed_official	610:813dcc80987e	1194
mbed_official	610:813dcc80987e	1195	#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == RESET)
mbed_official	610:813dcc80987e	1196
mbed_official	610:813dcc80987e	1197	#define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == RESET)
mbed_official	610:813dcc80987e	1198
mbed_official	610:813dcc80987e	1199	#define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == RESET)
mbed_official	610:813dcc80987e	1200
mbed_official	610:813dcc80987e	1201	/**
mbed_official	610:813dcc80987e	1202	* @}
mbed_official	610:813dcc80987e	1203	*/
mbed_official	610:813dcc80987e	1204
mbed_official	610:813dcc80987e	1205	/** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status
mbed_official	610:813dcc80987e	1206	* @brief Check whether the AHB3 peripheral clock is enabled or not.
mbed_official	610:813dcc80987e	1207	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	610:813dcc80987e	1208	* is disabled and the application software has to enable this clock before
mbed_official	610:813dcc80987e	1209	* using it.
mbed_official	610:813dcc80987e	1210	* @{
mbed_official	610:813dcc80987e	1211	*/
mbed_official	610:813dcc80987e	1212
mbed_official	610:813dcc80987e	1213	#define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != RESET)
mbed_official	610:813dcc80987e	1214
mbed_official	610:813dcc80987e	1215	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != RESET)
mbed_official	610:813dcc80987e	1216
mbed_official	610:813dcc80987e	1217	#define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == RESET)
mbed_official	610:813dcc80987e	1218
mbed_official	610:813dcc80987e	1219	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == RESET)
mbed_official	610:813dcc80987e	1220
mbed_official	610:813dcc80987e	1221	/**
mbed_official	610:813dcc80987e	1222	* @}
mbed_official	610:813dcc80987e	1223	*/
mbed_official	610:813dcc80987e	1224
mbed_official	610:813dcc80987e	1225	/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status
mbed_official	610:813dcc80987e	1226	* @brief Check whether the APB1 peripheral clock is enabled or not.
mbed_official	610:813dcc80987e	1227	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	610:813dcc80987e	1228	* is disabled and the application software has to enable this clock before
mbed_official	610:813dcc80987e	1229	* using it.
mbed_official	610:813dcc80987e	1230	* @{
mbed_official	610:813dcc80987e	1231	*/
mbed_official	610:813dcc80987e	1232
mbed_official	610:813dcc80987e	1233	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != RESET)
mbed_official	610:813dcc80987e	1234
mbed_official	610:813dcc80987e	1235	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != RESET)
mbed_official	610:813dcc80987e	1236
mbed_official	610:813dcc80987e	1237	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != RESET)
mbed_official	610:813dcc80987e	1238
mbed_official	610:813dcc80987e	1239	#define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != RESET)
mbed_official	610:813dcc80987e	1240
mbed_official	610:813dcc80987e	1241	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != RESET)
mbed_official	610:813dcc80987e	1242
mbed_official	610:813dcc80987e	1243	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != RESET)
mbed_official	610:813dcc80987e	1244
mbed_official	610:813dcc80987e	1245	#define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != RESET)
mbed_official	610:813dcc80987e	1246
mbed_official	610:813dcc80987e	1247	#define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != RESET)
mbed_official	610:813dcc80987e	1248
mbed_official	610:813dcc80987e	1249	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != RESET)
mbed_official	610:813dcc80987e	1250
mbed_official	610:813dcc80987e	1251	#define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != RESET)
mbed_official	610:813dcc80987e	1252
mbed_official	610:813dcc80987e	1253	#define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != RESET)
mbed_official	610:813dcc80987e	1254
mbed_official	610:813dcc80987e	1255	#define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != RESET)
mbed_official	610:813dcc80987e	1256
mbed_official	610:813dcc80987e	1257	#define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != RESET)
mbed_official	610:813dcc80987e	1258
mbed_official	610:813dcc80987e	1259	#define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != RESET)
mbed_official	610:813dcc80987e	1260
mbed_official	610:813dcc80987e	1261	#define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != RESET)
mbed_official	610:813dcc80987e	1262
mbed_official	610:813dcc80987e	1263	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != RESET)
mbed_official	610:813dcc80987e	1264
mbed_official	610:813dcc80987e	1265	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != RESET)
mbed_official	610:813dcc80987e	1266
mbed_official	610:813dcc80987e	1267	#define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != RESET)
mbed_official	610:813dcc80987e	1268
mbed_official	610:813dcc80987e	1269	#define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != RESET)
mbed_official	610:813dcc80987e	1270
mbed_official	610:813dcc80987e	1271	#define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != RESET)
mbed_official	610:813dcc80987e	1272
mbed_official	610:813dcc80987e	1273	#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != RESET)
mbed_official	610:813dcc80987e	1274
mbed_official	610:813dcc80987e	1275	#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != RESET)
mbed_official	610:813dcc80987e	1276
mbed_official	610:813dcc80987e	1277	#define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) != RESET)
mbed_official	610:813dcc80987e	1278
mbed_official	610:813dcc80987e	1279	#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != RESET)
mbed_official	610:813dcc80987e	1280
mbed_official	610:813dcc80987e	1281	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == RESET)
mbed_official	610:813dcc80987e	1282
mbed_official	610:813dcc80987e	1283	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == RESET)
mbed_official	610:813dcc80987e	1284
mbed_official	610:813dcc80987e	1285	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == RESET)
mbed_official	610:813dcc80987e	1286
mbed_official	610:813dcc80987e	1287	#define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == RESET)
mbed_official	610:813dcc80987e	1288
mbed_official	610:813dcc80987e	1289	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == RESET)
mbed_official	610:813dcc80987e	1290
mbed_official	610:813dcc80987e	1291	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == RESET)
mbed_official	610:813dcc80987e	1292
mbed_official	610:813dcc80987e	1293	#define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == RESET)
mbed_official	610:813dcc80987e	1294
mbed_official	610:813dcc80987e	1295	#define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == RESET)
mbed_official	610:813dcc80987e	1296
mbed_official	610:813dcc80987e	1297	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == RESET)
mbed_official	610:813dcc80987e	1298
mbed_official	610:813dcc80987e	1299	#define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == RESET)
mbed_official	610:813dcc80987e	1300
mbed_official	610:813dcc80987e	1301	#define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == RESET)
mbed_official	610:813dcc80987e	1302
mbed_official	610:813dcc80987e	1303	#define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == RESET)
mbed_official	610:813dcc80987e	1304
mbed_official	610:813dcc80987e	1305	#define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == RESET)
mbed_official	610:813dcc80987e	1306
mbed_official	610:813dcc80987e	1307	#define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == RESET)
mbed_official	610:813dcc80987e	1308
mbed_official	610:813dcc80987e	1309	#define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == RESET)
mbed_official	610:813dcc80987e	1310
mbed_official	610:813dcc80987e	1311	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == RESET)
mbed_official	610:813dcc80987e	1312
mbed_official	610:813dcc80987e	1313	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == RESET)
mbed_official	610:813dcc80987e	1314
mbed_official	610:813dcc80987e	1315	#define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == RESET)
mbed_official	610:813dcc80987e	1316
mbed_official	610:813dcc80987e	1317	#define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == RESET)
mbed_official	610:813dcc80987e	1318
mbed_official	610:813dcc80987e	1319	#define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == RESET)
mbed_official	610:813dcc80987e	1320
mbed_official	610:813dcc80987e	1321	#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == RESET)
mbed_official	610:813dcc80987e	1322
mbed_official	610:813dcc80987e	1323	#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == RESET)
mbed_official	610:813dcc80987e	1324
mbed_official	610:813dcc80987e	1325	#define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) == RESET)
mbed_official	610:813dcc80987e	1326
mbed_official	610:813dcc80987e	1327	#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == RESET)
mbed_official	610:813dcc80987e	1328
mbed_official	610:813dcc80987e	1329	/**
mbed_official	610:813dcc80987e	1330	* @}
mbed_official	610:813dcc80987e	1331	*/
mbed_official	610:813dcc80987e	1332
mbed_official	610:813dcc80987e	1333	/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status
mbed_official	610:813dcc80987e	1334	* @brief Check whether the APB2 peripheral clock is enabled or not.
mbed_official	610:813dcc80987e	1335	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	610:813dcc80987e	1336	* is disabled and the application software has to enable this clock before
mbed_official	610:813dcc80987e	1337	* using it.
mbed_official	610:813dcc80987e	1338	* @{
mbed_official	610:813dcc80987e	1339	*/
mbed_official	610:813dcc80987e	1340
mbed_official	610:813dcc80987e	1341	#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != RESET)
mbed_official	610:813dcc80987e	1342
mbed_official	610:813dcc80987e	1343	#define __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != RESET)
mbed_official	610:813dcc80987e	1344
mbed_official	610:813dcc80987e	1345	#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != RESET)
mbed_official	610:813dcc80987e	1346
mbed_official	610:813dcc80987e	1347	#define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != RESET)
mbed_official	610:813dcc80987e	1348
mbed_official	610:813dcc80987e	1349	#define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != RESET)
mbed_official	610:813dcc80987e	1350
mbed_official	610:813dcc80987e	1351	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != RESET)
mbed_official	610:813dcc80987e	1352
mbed_official	610:813dcc80987e	1353	#define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != RESET)
mbed_official	610:813dcc80987e	1354
mbed_official	610:813dcc80987e	1355	#define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != RESET)
mbed_official	610:813dcc80987e	1356
mbed_official	610:813dcc80987e	1357	#define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != RESET)
mbed_official	610:813dcc80987e	1358
mbed_official	610:813dcc80987e	1359	#define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != RESET)
mbed_official	610:813dcc80987e	1360
mbed_official	610:813dcc80987e	1361	#define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != RESET)
mbed_official	610:813dcc80987e	1362
mbed_official	610:813dcc80987e	1363	#define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != RESET)
mbed_official	610:813dcc80987e	1364
mbed_official	610:813dcc80987e	1365	#define __HAL_RCC_DFSDM_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDMEN) != RESET)
mbed_official	610:813dcc80987e	1366
mbed_official	610:813dcc80987e	1367	#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == RESET)
mbed_official	610:813dcc80987e	1368
mbed_official	610:813dcc80987e	1369	#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == RESET)
mbed_official	610:813dcc80987e	1370
mbed_official	610:813dcc80987e	1371	#define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == RESET)
mbed_official	610:813dcc80987e	1372
mbed_official	610:813dcc80987e	1373	#define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == RESET)
mbed_official	610:813dcc80987e	1374
mbed_official	610:813dcc80987e	1375	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == RESET)
mbed_official	610:813dcc80987e	1376
mbed_official	610:813dcc80987e	1377	#define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == RESET)
mbed_official	610:813dcc80987e	1378
mbed_official	610:813dcc80987e	1379	#define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == RESET)
mbed_official	610:813dcc80987e	1380
mbed_official	610:813dcc80987e	1381	#define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == RESET)
mbed_official	610:813dcc80987e	1382
mbed_official	610:813dcc80987e	1383	#define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == RESET)
mbed_official	610:813dcc80987e	1384
mbed_official	610:813dcc80987e	1385	#define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == RESET)
mbed_official	610:813dcc80987e	1386
mbed_official	610:813dcc80987e	1387	#define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == RESET)
mbed_official	610:813dcc80987e	1388
mbed_official	610:813dcc80987e	1389	#define __HAL_RCC_DFSDM_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDMEN) == RESET)
mbed_official	610:813dcc80987e	1390
mbed_official	610:813dcc80987e	1391	/**
mbed_official	610:813dcc80987e	1392	* @}
mbed_official	610:813dcc80987e	1393	*/
mbed_official	610:813dcc80987e	1394
mbed_official	610:813dcc80987e	1395	/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset
mbed_official	610:813dcc80987e	1396	* @brief Force or release AHB1 peripheral reset.
mbed_official	610:813dcc80987e	1397	* @{
mbed_official	610:813dcc80987e	1398	*/
mbed_official	610:813dcc80987e	1399	#define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFF)
mbed_official	610:813dcc80987e	1400
mbed_official	610:813dcc80987e	1401	#define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
mbed_official	610:813dcc80987e	1402
mbed_official	610:813dcc80987e	1403	#define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
mbed_official	610:813dcc80987e	1404
mbed_official	610:813dcc80987e	1405	#define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
mbed_official	610:813dcc80987e	1406
mbed_official	610:813dcc80987e	1407	#define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
mbed_official	610:813dcc80987e	1408
mbed_official	610:813dcc80987e	1409	#define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
mbed_official	610:813dcc80987e	1410
mbed_official	610:813dcc80987e	1411	#define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000)
mbed_official	610:813dcc80987e	1412
mbed_official	610:813dcc80987e	1413	#define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
mbed_official	610:813dcc80987e	1414
mbed_official	610:813dcc80987e	1415	#define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
mbed_official	610:813dcc80987e	1416
mbed_official	610:813dcc80987e	1417	#define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
mbed_official	610:813dcc80987e	1418
mbed_official	610:813dcc80987e	1419	#define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
mbed_official	610:813dcc80987e	1420
mbed_official	610:813dcc80987e	1421	#define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
mbed_official	610:813dcc80987e	1422
mbed_official	610:813dcc80987e	1423	/**
mbed_official	610:813dcc80987e	1424	* @}
mbed_official	610:813dcc80987e	1425	*/
mbed_official	610:813dcc80987e	1426
mbed_official	610:813dcc80987e	1427	/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset
mbed_official	610:813dcc80987e	1428	* @brief Force or release AHB2 peripheral reset.
mbed_official	610:813dcc80987e	1429	* @{
mbed_official	610:813dcc80987e	1430	*/
mbed_official	610:813dcc80987e	1431	#define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFF)
mbed_official	610:813dcc80987e	1432
mbed_official	610:813dcc80987e	1433	#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
mbed_official	610:813dcc80987e	1434
mbed_official	610:813dcc80987e	1435	#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
mbed_official	610:813dcc80987e	1436
mbed_official	610:813dcc80987e	1437	#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
mbed_official	610:813dcc80987e	1438
mbed_official	610:813dcc80987e	1439	#define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
mbed_official	610:813dcc80987e	1440
mbed_official	610:813dcc80987e	1441	#define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
mbed_official	610:813dcc80987e	1442
mbed_official	610:813dcc80987e	1443	#define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
mbed_official	610:813dcc80987e	1444
mbed_official	610:813dcc80987e	1445	#define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
mbed_official	610:813dcc80987e	1446
mbed_official	610:813dcc80987e	1447	#define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
mbed_official	610:813dcc80987e	1448
mbed_official	610:813dcc80987e	1449	#define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
mbed_official	610:813dcc80987e	1450
mbed_official	610:813dcc80987e	1451	#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
mbed_official	610:813dcc80987e	1452
mbed_official	610:813dcc80987e	1453	#define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000)
mbed_official	610:813dcc80987e	1454
mbed_official	610:813dcc80987e	1455	#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
mbed_official	610:813dcc80987e	1456
mbed_official	610:813dcc80987e	1457	#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
mbed_official	610:813dcc80987e	1458
mbed_official	610:813dcc80987e	1459	#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
mbed_official	610:813dcc80987e	1460
mbed_official	610:813dcc80987e	1461	#define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
mbed_official	610:813dcc80987e	1462
mbed_official	610:813dcc80987e	1463	#define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
mbed_official	610:813dcc80987e	1464
mbed_official	610:813dcc80987e	1465	#define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
mbed_official	610:813dcc80987e	1466
mbed_official	610:813dcc80987e	1467	#define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
mbed_official	610:813dcc80987e	1468
mbed_official	610:813dcc80987e	1469	#define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
mbed_official	610:813dcc80987e	1470
mbed_official	610:813dcc80987e	1471	#define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
mbed_official	610:813dcc80987e	1472
mbed_official	610:813dcc80987e	1473	#define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
mbed_official	610:813dcc80987e	1474
mbed_official	610:813dcc80987e	1475	/**
mbed_official	610:813dcc80987e	1476	* @}
mbed_official	610:813dcc80987e	1477	*/
mbed_official	610:813dcc80987e	1478
mbed_official	610:813dcc80987e	1479	/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset
mbed_official	610:813dcc80987e	1480	* @brief Force or release AHB3 peripheral reset.
mbed_official	610:813dcc80987e	1481	* @{
mbed_official	610:813dcc80987e	1482	*/
mbed_official	610:813dcc80987e	1483	#define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFF)
mbed_official	610:813dcc80987e	1484
mbed_official	610:813dcc80987e	1485	#define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
mbed_official	610:813dcc80987e	1486
mbed_official	610:813dcc80987e	1487	#define __HAL_RCC_QSPI_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
mbed_official	610:813dcc80987e	1488
mbed_official	610:813dcc80987e	1489	#define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000)
mbed_official	610:813dcc80987e	1490
mbed_official	610:813dcc80987e	1491	#define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
mbed_official	610:813dcc80987e	1492
mbed_official	610:813dcc80987e	1493	#define __HAL_RCC_QSPI_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
mbed_official	610:813dcc80987e	1494
mbed_official	610:813dcc80987e	1495	/**
mbed_official	610:813dcc80987e	1496	* @}
mbed_official	610:813dcc80987e	1497	*/
mbed_official	610:813dcc80987e	1498
mbed_official	610:813dcc80987e	1499	/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
mbed_official	610:813dcc80987e	1500	* @brief Force or release APB1 peripheral reset.
mbed_official	610:813dcc80987e	1501	* @{
mbed_official	610:813dcc80987e	1502	*/
mbed_official	610:813dcc80987e	1503	#define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFF)
mbed_official	610:813dcc80987e	1504
mbed_official	610:813dcc80987e	1505	#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
mbed_official	610:813dcc80987e	1506
mbed_official	610:813dcc80987e	1507	#define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
mbed_official	610:813dcc80987e	1508
mbed_official	610:813dcc80987e	1509	#define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
mbed_official	610:813dcc80987e	1510
mbed_official	610:813dcc80987e	1511	#define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
mbed_official	610:813dcc80987e	1512
mbed_official	610:813dcc80987e	1513	#define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
mbed_official	610:813dcc80987e	1514
mbed_official	610:813dcc80987e	1515	#define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
mbed_official	610:813dcc80987e	1516
mbed_official	610:813dcc80987e	1517	#define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
mbed_official	610:813dcc80987e	1518
mbed_official	610:813dcc80987e	1519	#define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
mbed_official	610:813dcc80987e	1520
mbed_official	610:813dcc80987e	1521	#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
mbed_official	610:813dcc80987e	1522
mbed_official	610:813dcc80987e	1523	#define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
mbed_official	610:813dcc80987e	1524
mbed_official	610:813dcc80987e	1525	#define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
mbed_official	610:813dcc80987e	1526
mbed_official	610:813dcc80987e	1527	#define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
mbed_official	610:813dcc80987e	1528
mbed_official	610:813dcc80987e	1529	#define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
mbed_official	610:813dcc80987e	1530
mbed_official	610:813dcc80987e	1531	#define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
mbed_official	610:813dcc80987e	1532
mbed_official	610:813dcc80987e	1533	#define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
mbed_official	610:813dcc80987e	1534
mbed_official	610:813dcc80987e	1535	#define __HAL_RCC_CAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
mbed_official	610:813dcc80987e	1536
mbed_official	610:813dcc80987e	1537	#define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
mbed_official	610:813dcc80987e	1538
mbed_official	610:813dcc80987e	1539	#define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
mbed_official	610:813dcc80987e	1540
mbed_official	610:813dcc80987e	1541	#define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
mbed_official	610:813dcc80987e	1542
mbed_official	610:813dcc80987e	1543	#define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
mbed_official	610:813dcc80987e	1544
mbed_official	610:813dcc80987e	1545	#define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
mbed_official	610:813dcc80987e	1546
mbed_official	610:813dcc80987e	1547	#define __HAL_RCC_SWPMI1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
mbed_official	610:813dcc80987e	1548
mbed_official	610:813dcc80987e	1549	#define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
mbed_official	610:813dcc80987e	1550
mbed_official	610:813dcc80987e	1551	#define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APB1RSTR1, 0x00000000)
mbed_official	610:813dcc80987e	1552
mbed_official	610:813dcc80987e	1553	#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
mbed_official	610:813dcc80987e	1554
mbed_official	610:813dcc80987e	1555	#define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
mbed_official	610:813dcc80987e	1556
mbed_official	610:813dcc80987e	1557	#define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
mbed_official	610:813dcc80987e	1558
mbed_official	610:813dcc80987e	1559	#define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
mbed_official	610:813dcc80987e	1560
mbed_official	610:813dcc80987e	1561	#define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
mbed_official	610:813dcc80987e	1562
mbed_official	610:813dcc80987e	1563	#define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
mbed_official	610:813dcc80987e	1564
mbed_official	610:813dcc80987e	1565	#define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
mbed_official	610:813dcc80987e	1566
mbed_official	610:813dcc80987e	1567	#define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
mbed_official	610:813dcc80987e	1568
mbed_official	610:813dcc80987e	1569	#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
mbed_official	610:813dcc80987e	1570
mbed_official	610:813dcc80987e	1571	#define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
mbed_official	610:813dcc80987e	1572
mbed_official	610:813dcc80987e	1573	#define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
mbed_official	610:813dcc80987e	1574
mbed_official	610:813dcc80987e	1575	#define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
mbed_official	610:813dcc80987e	1576
mbed_official	610:813dcc80987e	1577	#define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
mbed_official	610:813dcc80987e	1578
mbed_official	610:813dcc80987e	1579	#define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
mbed_official	610:813dcc80987e	1580
mbed_official	610:813dcc80987e	1581	#define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
mbed_official	610:813dcc80987e	1582
mbed_official	610:813dcc80987e	1583	#define __HAL_RCC_CAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
mbed_official	610:813dcc80987e	1584
mbed_official	610:813dcc80987e	1585	#define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
mbed_official	610:813dcc80987e	1586
mbed_official	610:813dcc80987e	1587	#define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
mbed_official	610:813dcc80987e	1588
mbed_official	610:813dcc80987e	1589	#define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
mbed_official	610:813dcc80987e	1590
mbed_official	610:813dcc80987e	1591	#define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
mbed_official	610:813dcc80987e	1592
mbed_official	610:813dcc80987e	1593	#define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
mbed_official	610:813dcc80987e	1594
mbed_official	610:813dcc80987e	1595	#define __HAL_RCC_SWPMI1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
mbed_official	610:813dcc80987e	1596
mbed_official	610:813dcc80987e	1597	#define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
mbed_official	610:813dcc80987e	1598
mbed_official	610:813dcc80987e	1599	/**
mbed_official	610:813dcc80987e	1600	* @}
mbed_official	610:813dcc80987e	1601	*/
mbed_official	610:813dcc80987e	1602
mbed_official	610:813dcc80987e	1603	/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
mbed_official	610:813dcc80987e	1604	* @brief Force or release APB2 peripheral reset.
mbed_official	610:813dcc80987e	1605	* @{
mbed_official	610:813dcc80987e	1606	*/
mbed_official	610:813dcc80987e	1607	#define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFF)
mbed_official	610:813dcc80987e	1608
mbed_official	610:813dcc80987e	1609	#define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
mbed_official	610:813dcc80987e	1610
mbed_official	610:813dcc80987e	1611	#define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
mbed_official	610:813dcc80987e	1612
mbed_official	610:813dcc80987e	1613	#define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
mbed_official	610:813dcc80987e	1614
mbed_official	610:813dcc80987e	1615	#define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
mbed_official	610:813dcc80987e	1616
mbed_official	610:813dcc80987e	1617	#define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
mbed_official	610:813dcc80987e	1618
mbed_official	610:813dcc80987e	1619	#define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
mbed_official	610:813dcc80987e	1620
mbed_official	610:813dcc80987e	1621	#define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
mbed_official	610:813dcc80987e	1622
mbed_official	610:813dcc80987e	1623	#define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
mbed_official	610:813dcc80987e	1624
mbed_official	610:813dcc80987e	1625	#define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
mbed_official	610:813dcc80987e	1626
mbed_official	610:813dcc80987e	1627	#define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
mbed_official	610:813dcc80987e	1628
mbed_official	610:813dcc80987e	1629	#define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
mbed_official	610:813dcc80987e	1630
mbed_official	610:813dcc80987e	1631	#define __HAL_RCC_DFSDM_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDMRST)
mbed_official	610:813dcc80987e	1632
mbed_official	610:813dcc80987e	1633	#define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000)
mbed_official	610:813dcc80987e	1634
mbed_official	610:813dcc80987e	1635	#define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
mbed_official	610:813dcc80987e	1636
mbed_official	610:813dcc80987e	1637	#define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
mbed_official	610:813dcc80987e	1638
mbed_official	610:813dcc80987e	1639	#define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
mbed_official	610:813dcc80987e	1640
mbed_official	610:813dcc80987e	1641	#define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
mbed_official	610:813dcc80987e	1642
mbed_official	610:813dcc80987e	1643	#define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
mbed_official	610:813dcc80987e	1644
mbed_official	610:813dcc80987e	1645	#define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
mbed_official	610:813dcc80987e	1646
mbed_official	610:813dcc80987e	1647	#define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
mbed_official	610:813dcc80987e	1648
mbed_official	610:813dcc80987e	1649	#define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
mbed_official	610:813dcc80987e	1650
mbed_official	610:813dcc80987e	1651	#define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
mbed_official	610:813dcc80987e	1652
mbed_official	610:813dcc80987e	1653	#define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
mbed_official	610:813dcc80987e	1654
mbed_official	610:813dcc80987e	1655	#define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
mbed_official	610:813dcc80987e	1656
mbed_official	610:813dcc80987e	1657	#define __HAL_RCC_DFSDM_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDMRST)
mbed_official	610:813dcc80987e	1658
mbed_official	610:813dcc80987e	1659	/**
mbed_official	610:813dcc80987e	1660	* @}
mbed_official	610:813dcc80987e	1661	*/
mbed_official	610:813dcc80987e	1662
mbed_official	610:813dcc80987e	1663	/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable
mbed_official	610:813dcc80987e	1664	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
mbed_official	610:813dcc80987e	1665	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	610:813dcc80987e	1666	* power consumption.
mbed_official	610:813dcc80987e	1667	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	610:813dcc80987e	1668	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	610:813dcc80987e	1669	* @{
mbed_official	610:813dcc80987e	1670	*/
mbed_official	610:813dcc80987e	1671
mbed_official	610:813dcc80987e	1672	#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
mbed_official	610:813dcc80987e	1673
mbed_official	610:813dcc80987e	1674	#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
mbed_official	610:813dcc80987e	1675
mbed_official	610:813dcc80987e	1676	#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
mbed_official	610:813dcc80987e	1677
mbed_official	610:813dcc80987e	1678	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
mbed_official	610:813dcc80987e	1679
mbed_official	610:813dcc80987e	1680	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
mbed_official	610:813dcc80987e	1681
mbed_official	610:813dcc80987e	1682	#define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
mbed_official	610:813dcc80987e	1683
mbed_official	610:813dcc80987e	1684	#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
mbed_official	610:813dcc80987e	1685
mbed_official	610:813dcc80987e	1686	#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
mbed_official	610:813dcc80987e	1687
mbed_official	610:813dcc80987e	1688	#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
mbed_official	610:813dcc80987e	1689
mbed_official	610:813dcc80987e	1690	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
mbed_official	610:813dcc80987e	1691
mbed_official	610:813dcc80987e	1692	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
mbed_official	610:813dcc80987e	1693
mbed_official	610:813dcc80987e	1694	#define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
mbed_official	610:813dcc80987e	1695
mbed_official	610:813dcc80987e	1696	/**
mbed_official	610:813dcc80987e	1697	* @}
mbed_official	610:813dcc80987e	1698	*/
mbed_official	610:813dcc80987e	1699
mbed_official	610:813dcc80987e	1700	/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable
mbed_official	610:813dcc80987e	1701	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
mbed_official	610:813dcc80987e	1702	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	610:813dcc80987e	1703	* power consumption.
mbed_official	610:813dcc80987e	1704	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	610:813dcc80987e	1705	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	610:813dcc80987e	1706	* @{
mbed_official	610:813dcc80987e	1707	*/
mbed_official	610:813dcc80987e	1708
mbed_official	610:813dcc80987e	1709	#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
mbed_official	610:813dcc80987e	1710
mbed_official	610:813dcc80987e	1711	#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
mbed_official	610:813dcc80987e	1712
mbed_official	610:813dcc80987e	1713	#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
mbed_official	610:813dcc80987e	1714
mbed_official	610:813dcc80987e	1715	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
mbed_official	610:813dcc80987e	1716
mbed_official	610:813dcc80987e	1717	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
mbed_official	610:813dcc80987e	1718
mbed_official	610:813dcc80987e	1719	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
mbed_official	610:813dcc80987e	1720
mbed_official	610:813dcc80987e	1721	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
mbed_official	610:813dcc80987e	1722
mbed_official	610:813dcc80987e	1723	#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
mbed_official	610:813dcc80987e	1724
mbed_official	610:813dcc80987e	1725	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
mbed_official	610:813dcc80987e	1726
mbed_official	610:813dcc80987e	1727	#define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
mbed_official	610:813dcc80987e	1728
mbed_official	610:813dcc80987e	1729	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
mbed_official	610:813dcc80987e	1730
mbed_official	610:813dcc80987e	1731	#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
mbed_official	610:813dcc80987e	1732
mbed_official	610:813dcc80987e	1733	#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
mbed_official	610:813dcc80987e	1734
mbed_official	610:813dcc80987e	1735	#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
mbed_official	610:813dcc80987e	1736
mbed_official	610:813dcc80987e	1737	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
mbed_official	610:813dcc80987e	1738
mbed_official	610:813dcc80987e	1739	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
mbed_official	610:813dcc80987e	1740
mbed_official	610:813dcc80987e	1741	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
mbed_official	610:813dcc80987e	1742
mbed_official	610:813dcc80987e	1743	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
mbed_official	610:813dcc80987e	1744
mbed_official	610:813dcc80987e	1745	#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
mbed_official	610:813dcc80987e	1746
mbed_official	610:813dcc80987e	1747	#define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
mbed_official	610:813dcc80987e	1748
mbed_official	610:813dcc80987e	1749	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
mbed_official	610:813dcc80987e	1750
mbed_official	610:813dcc80987e	1751	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
mbed_official	610:813dcc80987e	1752
mbed_official	610:813dcc80987e	1753	/**
mbed_official	610:813dcc80987e	1754	* @}
mbed_official	610:813dcc80987e	1755	*/
mbed_official	610:813dcc80987e	1756
mbed_official	610:813dcc80987e	1757	/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable
mbed_official	610:813dcc80987e	1758	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
mbed_official	610:813dcc80987e	1759	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	610:813dcc80987e	1760	* power consumption.
mbed_official	610:813dcc80987e	1761	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	610:813dcc80987e	1762	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	610:813dcc80987e	1763	* @{
mbed_official	610:813dcc80987e	1764	*/
mbed_official	610:813dcc80987e	1765
mbed_official	610:813dcc80987e	1766	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
mbed_official	610:813dcc80987e	1767
mbed_official	610:813dcc80987e	1768	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
mbed_official	610:813dcc80987e	1769
mbed_official	610:813dcc80987e	1770	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
mbed_official	610:813dcc80987e	1771
mbed_official	610:813dcc80987e	1772	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
mbed_official	610:813dcc80987e	1773
mbed_official	610:813dcc80987e	1774	/**
mbed_official	610:813dcc80987e	1775	* @}
mbed_official	610:813dcc80987e	1776	*/
mbed_official	610:813dcc80987e	1777
mbed_official	610:813dcc80987e	1778	/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
mbed_official	610:813dcc80987e	1779	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
mbed_official	610:813dcc80987e	1780	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	610:813dcc80987e	1781	* power consumption.
mbed_official	610:813dcc80987e	1782	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	610:813dcc80987e	1783	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	610:813dcc80987e	1784	* @{
mbed_official	610:813dcc80987e	1785	*/
mbed_official	610:813dcc80987e	1786
mbed_official	610:813dcc80987e	1787	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
mbed_official	610:813dcc80987e	1788
mbed_official	610:813dcc80987e	1789	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
mbed_official	610:813dcc80987e	1790
mbed_official	610:813dcc80987e	1791	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
mbed_official	610:813dcc80987e	1792
mbed_official	610:813dcc80987e	1793	#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
mbed_official	610:813dcc80987e	1794
mbed_official	610:813dcc80987e	1795	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
mbed_official	610:813dcc80987e	1796
mbed_official	610:813dcc80987e	1797	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
mbed_official	610:813dcc80987e	1798
mbed_official	610:813dcc80987e	1799	#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
mbed_official	610:813dcc80987e	1800
mbed_official	610:813dcc80987e	1801	#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
mbed_official	610:813dcc80987e	1802
mbed_official	610:813dcc80987e	1803	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
mbed_official	610:813dcc80987e	1804
mbed_official	610:813dcc80987e	1805	#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
mbed_official	610:813dcc80987e	1806
mbed_official	610:813dcc80987e	1807	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
mbed_official	610:813dcc80987e	1808
mbed_official	610:813dcc80987e	1809	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
mbed_official	610:813dcc80987e	1810
mbed_official	610:813dcc80987e	1811	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
mbed_official	610:813dcc80987e	1812
mbed_official	610:813dcc80987e	1813	#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
mbed_official	610:813dcc80987e	1814
mbed_official	610:813dcc80987e	1815	#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
mbed_official	610:813dcc80987e	1816
mbed_official	610:813dcc80987e	1817	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
mbed_official	610:813dcc80987e	1818
mbed_official	610:813dcc80987e	1819	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
mbed_official	610:813dcc80987e	1820
mbed_official	610:813dcc80987e	1821	#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
mbed_official	610:813dcc80987e	1822
mbed_official	610:813dcc80987e	1823	#define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
mbed_official	610:813dcc80987e	1824
mbed_official	610:813dcc80987e	1825	#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
mbed_official	610:813dcc80987e	1826
mbed_official	610:813dcc80987e	1827	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
mbed_official	610:813dcc80987e	1828
mbed_official	610:813dcc80987e	1829	#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
mbed_official	610:813dcc80987e	1830
mbed_official	610:813dcc80987e	1831	#define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
mbed_official	610:813dcc80987e	1832
mbed_official	610:813dcc80987e	1833	#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
mbed_official	610:813dcc80987e	1834
mbed_official	610:813dcc80987e	1835	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
mbed_official	610:813dcc80987e	1836
mbed_official	610:813dcc80987e	1837	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
mbed_official	610:813dcc80987e	1838
mbed_official	610:813dcc80987e	1839	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
mbed_official	610:813dcc80987e	1840
mbed_official	610:813dcc80987e	1841	#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
mbed_official	610:813dcc80987e	1842
mbed_official	610:813dcc80987e	1843	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
mbed_official	610:813dcc80987e	1844
mbed_official	610:813dcc80987e	1845	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
mbed_official	610:813dcc80987e	1846
mbed_official	610:813dcc80987e	1847	#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
mbed_official	610:813dcc80987e	1848
mbed_official	610:813dcc80987e	1849	#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
mbed_official	610:813dcc80987e	1850
mbed_official	610:813dcc80987e	1851	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
mbed_official	610:813dcc80987e	1852
mbed_official	610:813dcc80987e	1853	#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
mbed_official	610:813dcc80987e	1854
mbed_official	610:813dcc80987e	1855	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
mbed_official	610:813dcc80987e	1856
mbed_official	610:813dcc80987e	1857	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
mbed_official	610:813dcc80987e	1858
mbed_official	610:813dcc80987e	1859	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
mbed_official	610:813dcc80987e	1860
mbed_official	610:813dcc80987e	1861	#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
mbed_official	610:813dcc80987e	1862
mbed_official	610:813dcc80987e	1863	#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
mbed_official	610:813dcc80987e	1864
mbed_official	610:813dcc80987e	1865	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
mbed_official	610:813dcc80987e	1866
mbed_official	610:813dcc80987e	1867	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
mbed_official	610:813dcc80987e	1868
mbed_official	610:813dcc80987e	1869	#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
mbed_official	610:813dcc80987e	1870
mbed_official	610:813dcc80987e	1871	#define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
mbed_official	610:813dcc80987e	1872
mbed_official	610:813dcc80987e	1873	#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
mbed_official	610:813dcc80987e	1874
mbed_official	610:813dcc80987e	1875	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
mbed_official	610:813dcc80987e	1876
mbed_official	610:813dcc80987e	1877	#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
mbed_official	610:813dcc80987e	1878
mbed_official	610:813dcc80987e	1879	#define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
mbed_official	610:813dcc80987e	1880
mbed_official	610:813dcc80987e	1881	#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
mbed_official	610:813dcc80987e	1882
mbed_official	610:813dcc80987e	1883	/**
mbed_official	610:813dcc80987e	1884	* @}
mbed_official	610:813dcc80987e	1885	*/
mbed_official	610:813dcc80987e	1886
mbed_official	610:813dcc80987e	1887	/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
mbed_official	610:813dcc80987e	1888	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
mbed_official	610:813dcc80987e	1889	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	610:813dcc80987e	1890	* power consumption.
mbed_official	610:813dcc80987e	1891	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	610:813dcc80987e	1892	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	610:813dcc80987e	1893	* @{
mbed_official	610:813dcc80987e	1894	*/
mbed_official	610:813dcc80987e	1895
mbed_official	610:813dcc80987e	1896	#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
mbed_official	610:813dcc80987e	1897
mbed_official	610:813dcc80987e	1898	#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
mbed_official	610:813dcc80987e	1899
mbed_official	610:813dcc80987e	1900	#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
mbed_official	610:813dcc80987e	1901
mbed_official	610:813dcc80987e	1902	#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
mbed_official	610:813dcc80987e	1903
mbed_official	610:813dcc80987e	1904	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
mbed_official	610:813dcc80987e	1905
mbed_official	610:813dcc80987e	1906	#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
mbed_official	610:813dcc80987e	1907
mbed_official	610:813dcc80987e	1908	#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
mbed_official	610:813dcc80987e	1909
mbed_official	610:813dcc80987e	1910	#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
mbed_official	610:813dcc80987e	1911
mbed_official	610:813dcc80987e	1912	#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
mbed_official	610:813dcc80987e	1913
mbed_official	610:813dcc80987e	1914	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
mbed_official	610:813dcc80987e	1915
mbed_official	610:813dcc80987e	1916	#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
mbed_official	610:813dcc80987e	1917
mbed_official	610:813dcc80987e	1918	#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDMSMEN)
mbed_official	610:813dcc80987e	1919
mbed_official	610:813dcc80987e	1920	#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
mbed_official	610:813dcc80987e	1921
mbed_official	610:813dcc80987e	1922	#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
mbed_official	610:813dcc80987e	1923
mbed_official	610:813dcc80987e	1924	#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
mbed_official	610:813dcc80987e	1925
mbed_official	610:813dcc80987e	1926	#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
mbed_official	610:813dcc80987e	1927
mbed_official	610:813dcc80987e	1928	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
mbed_official	610:813dcc80987e	1929
mbed_official	610:813dcc80987e	1930	#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
mbed_official	610:813dcc80987e	1931
mbed_official	610:813dcc80987e	1932	#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
mbed_official	610:813dcc80987e	1933
mbed_official	610:813dcc80987e	1934	#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
mbed_official	610:813dcc80987e	1935
mbed_official	610:813dcc80987e	1936	#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
mbed_official	610:813dcc80987e	1937
mbed_official	610:813dcc80987e	1938	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
mbed_official	610:813dcc80987e	1939
mbed_official	610:813dcc80987e	1940	#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
mbed_official	610:813dcc80987e	1941
mbed_official	610:813dcc80987e	1942	#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDMSMEN)
mbed_official	610:813dcc80987e	1943
mbed_official	610:813dcc80987e	1944	/**
mbed_official	610:813dcc80987e	1945	* @}
mbed_official	610:813dcc80987e	1946	*/
mbed_official	610:813dcc80987e	1947
mbed_official	610:813dcc80987e	1948	/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status
mbed_official	610:813dcc80987e	1949	* @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
mbed_official	610:813dcc80987e	1950	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	610:813dcc80987e	1951	* power consumption.
mbed_official	610:813dcc80987e	1952	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	610:813dcc80987e	1953	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	610:813dcc80987e	1954	* @{
mbed_official	610:813dcc80987e	1955	*/
mbed_official	610:813dcc80987e	1956
mbed_official	610:813dcc80987e	1957	#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != RESET)
mbed_official	610:813dcc80987e	1958
mbed_official	610:813dcc80987e	1959	#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != RESET)
mbed_official	610:813dcc80987e	1960
mbed_official	610:813dcc80987e	1961	#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != RESET)
mbed_official	610:813dcc80987e	1962
mbed_official	610:813dcc80987e	1963	#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != RESET)
mbed_official	610:813dcc80987e	1964
mbed_official	610:813dcc80987e	1965	#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != RESET)
mbed_official	610:813dcc80987e	1966
mbed_official	610:813dcc80987e	1967	#define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != RESET)
mbed_official	610:813dcc80987e	1968
mbed_official	610:813dcc80987e	1969	#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == RESET)
mbed_official	610:813dcc80987e	1970
mbed_official	610:813dcc80987e	1971	#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == RESET)
mbed_official	610:813dcc80987e	1972
mbed_official	610:813dcc80987e	1973	#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == RESET)
mbed_official	610:813dcc80987e	1974
mbed_official	610:813dcc80987e	1975	#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == RESET)
mbed_official	610:813dcc80987e	1976
mbed_official	610:813dcc80987e	1977	#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == RESET)
mbed_official	610:813dcc80987e	1978
mbed_official	610:813dcc80987e	1979	#define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == RESET)
mbed_official	610:813dcc80987e	1980
mbed_official	610:813dcc80987e	1981	/**
mbed_official	610:813dcc80987e	1982	* @}
mbed_official	610:813dcc80987e	1983	*/
mbed_official	610:813dcc80987e	1984
mbed_official	610:813dcc80987e	1985	/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status
mbed_official	610:813dcc80987e	1986	* @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
mbed_official	610:813dcc80987e	1987	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	610:813dcc80987e	1988	* power consumption.
mbed_official	610:813dcc80987e	1989	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	610:813dcc80987e	1990	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	610:813dcc80987e	1991	* @{
mbed_official	610:813dcc80987e	1992	*/
mbed_official	610:813dcc80987e	1993
mbed_official	610:813dcc80987e	1994	#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != RESET)
mbed_official	610:813dcc80987e	1995
mbed_official	610:813dcc80987e	1996	#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != RESET)
mbed_official	610:813dcc80987e	1997
mbed_official	610:813dcc80987e	1998	#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != RESET)
mbed_official	610:813dcc80987e	1999
mbed_official	610:813dcc80987e	2000	#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != RESET)
mbed_official	610:813dcc80987e	2001
mbed_official	610:813dcc80987e	2002	#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != RESET)
mbed_official	610:813dcc80987e	2003
mbed_official	610:813dcc80987e	2004	#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != RESET)
mbed_official	610:813dcc80987e	2005
mbed_official	610:813dcc80987e	2006	#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != RESET)
mbed_official	610:813dcc80987e	2007
mbed_official	610:813dcc80987e	2008	#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != RESET)
mbed_official	610:813dcc80987e	2009
mbed_official	610:813dcc80987e	2010	#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != RESET)
mbed_official	610:813dcc80987e	2011
mbed_official	610:813dcc80987e	2012	#define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != RESET)
mbed_official	610:813dcc80987e	2013
mbed_official	610:813dcc80987e	2014	#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != RESET)
mbed_official	610:813dcc80987e	2015
mbed_official	610:813dcc80987e	2016	#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == RESET)
mbed_official	610:813dcc80987e	2017
mbed_official	610:813dcc80987e	2018	#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == RESET)
mbed_official	610:813dcc80987e	2019
mbed_official	610:813dcc80987e	2020	#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == RESET)
mbed_official	610:813dcc80987e	2021
mbed_official	610:813dcc80987e	2022	#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == RESET)
mbed_official	610:813dcc80987e	2023
mbed_official	610:813dcc80987e	2024	#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == RESET)
mbed_official	610:813dcc80987e	2025
mbed_official	610:813dcc80987e	2026	#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == RESET)
mbed_official	610:813dcc80987e	2027
mbed_official	610:813dcc80987e	2028	#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == RESET)
mbed_official	610:813dcc80987e	2029
mbed_official	610:813dcc80987e	2030	#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == RESET)
mbed_official	610:813dcc80987e	2031
mbed_official	610:813dcc80987e	2032	#define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == RESET)
mbed_official	610:813dcc80987e	2033
mbed_official	610:813dcc80987e	2034	#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == RESET)
mbed_official	610:813dcc80987e	2035
mbed_official	610:813dcc80987e	2036	#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == RESET)
mbed_official	610:813dcc80987e	2037
mbed_official	610:813dcc80987e	2038	/**
mbed_official	610:813dcc80987e	2039	* @}
mbed_official	610:813dcc80987e	2040	*/
mbed_official	610:813dcc80987e	2041
mbed_official	610:813dcc80987e	2042	/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status
mbed_official	610:813dcc80987e	2043	* @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not.
mbed_official	610:813dcc80987e	2044	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	610:813dcc80987e	2045	* power consumption.
mbed_official	610:813dcc80987e	2046	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	610:813dcc80987e	2047	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	610:813dcc80987e	2048	* @{
mbed_official	610:813dcc80987e	2049	*/
mbed_official	610:813dcc80987e	2050
mbed_official	610:813dcc80987e	2051	#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != RESET)
mbed_official	610:813dcc80987e	2052
mbed_official	610:813dcc80987e	2053	#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != RESET)
mbed_official	610:813dcc80987e	2054
mbed_official	610:813dcc80987e	2055	#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == RESET)
mbed_official	610:813dcc80987e	2056
mbed_official	610:813dcc80987e	2057	#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == RESET)
mbed_official	610:813dcc80987e	2058
mbed_official	610:813dcc80987e	2059	/**
mbed_official	610:813dcc80987e	2060	* @}
mbed_official	610:813dcc80987e	2061	*/
mbed_official	610:813dcc80987e	2062
mbed_official	610:813dcc80987e	2063	/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status
mbed_official	610:813dcc80987e	2064	* @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
mbed_official	610:813dcc80987e	2065	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	610:813dcc80987e	2066	* power consumption.
mbed_official	610:813dcc80987e	2067	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	610:813dcc80987e	2068	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	610:813dcc80987e	2069	* @{
mbed_official	610:813dcc80987e	2070	*/
mbed_official	610:813dcc80987e	2071
mbed_official	610:813dcc80987e	2072	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != RESET)
mbed_official	610:813dcc80987e	2073
mbed_official	610:813dcc80987e	2074	#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != RESET)
mbed_official	610:813dcc80987e	2075
mbed_official	610:813dcc80987e	2076	#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != RESET)
mbed_official	610:813dcc80987e	2077
mbed_official	610:813dcc80987e	2078	#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != RESET)
mbed_official	610:813dcc80987e	2079
mbed_official	610:813dcc80987e	2080	#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != RESET)
mbed_official	610:813dcc80987e	2081
mbed_official	610:813dcc80987e	2082	#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != RESET)
mbed_official	610:813dcc80987e	2083
mbed_official	610:813dcc80987e	2084	#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != RESET)
mbed_official	610:813dcc80987e	2085
mbed_official	610:813dcc80987e	2086	#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != RESET)
mbed_official	610:813dcc80987e	2087
mbed_official	610:813dcc80987e	2088	#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != RESET)
mbed_official	610:813dcc80987e	2089
mbed_official	610:813dcc80987e	2090	#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != RESET)
mbed_official	610:813dcc80987e	2091
mbed_official	610:813dcc80987e	2092	#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != RESET)
mbed_official	610:813dcc80987e	2093
mbed_official	610:813dcc80987e	2094	#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != RESET)
mbed_official	610:813dcc80987e	2095
mbed_official	610:813dcc80987e	2096	#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != RESET)
mbed_official	610:813dcc80987e	2097
mbed_official	610:813dcc80987e	2098	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != RESET)
mbed_official	610:813dcc80987e	2099
mbed_official	610:813dcc80987e	2100	#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != RESET)
mbed_official	610:813dcc80987e	2101
mbed_official	610:813dcc80987e	2102	#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != RESET)
mbed_official	610:813dcc80987e	2103
mbed_official	610:813dcc80987e	2104	#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != RESET)
mbed_official	610:813dcc80987e	2105
mbed_official	610:813dcc80987e	2106	#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != RESET)
mbed_official	610:813dcc80987e	2107
mbed_official	610:813dcc80987e	2108	#define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != RESET)
mbed_official	610:813dcc80987e	2109
mbed_official	610:813dcc80987e	2110	#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != RESET)
mbed_official	610:813dcc80987e	2111
mbed_official	610:813dcc80987e	2112	#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != RESET)
mbed_official	610:813dcc80987e	2113
mbed_official	610:813dcc80987e	2114	#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != RESET)
mbed_official	610:813dcc80987e	2115
mbed_official	610:813dcc80987e	2116	#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) != RESET)
mbed_official	610:813dcc80987e	2117
mbed_official	610:813dcc80987e	2118	#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != RESET)
mbed_official	610:813dcc80987e	2119
mbed_official	610:813dcc80987e	2120	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == RESET)
mbed_official	610:813dcc80987e	2121
mbed_official	610:813dcc80987e	2122	#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == RESET)
mbed_official	610:813dcc80987e	2123
mbed_official	610:813dcc80987e	2124	#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == RESET)
mbed_official	610:813dcc80987e	2125
mbed_official	610:813dcc80987e	2126	#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == RESET)
mbed_official	610:813dcc80987e	2127
mbed_official	610:813dcc80987e	2128	#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == RESET)
mbed_official	610:813dcc80987e	2129
mbed_official	610:813dcc80987e	2130	#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == RESET)
mbed_official	610:813dcc80987e	2131
mbed_official	610:813dcc80987e	2132	#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == RESET)
mbed_official	610:813dcc80987e	2133
mbed_official	610:813dcc80987e	2134	#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == RESET)
mbed_official	610:813dcc80987e	2135
mbed_official	610:813dcc80987e	2136	#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == RESET)
mbed_official	610:813dcc80987e	2137
mbed_official	610:813dcc80987e	2138	#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == RESET)
mbed_official	610:813dcc80987e	2139
mbed_official	610:813dcc80987e	2140	#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == RESET)
mbed_official	610:813dcc80987e	2141
mbed_official	610:813dcc80987e	2142	#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == RESET)
mbed_official	610:813dcc80987e	2143
mbed_official	610:813dcc80987e	2144	#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == RESET)
mbed_official	610:813dcc80987e	2145
mbed_official	610:813dcc80987e	2146	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == RESET)
mbed_official	610:813dcc80987e	2147
mbed_official	610:813dcc80987e	2148	#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == RESET)
mbed_official	610:813dcc80987e	2149
mbed_official	610:813dcc80987e	2150	#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == RESET)
mbed_official	610:813dcc80987e	2151
mbed_official	610:813dcc80987e	2152	#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == RESET)
mbed_official	610:813dcc80987e	2153
mbed_official	610:813dcc80987e	2154	#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == RESET)
mbed_official	610:813dcc80987e	2155
mbed_official	610:813dcc80987e	2156	#define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == RESET)
mbed_official	610:813dcc80987e	2157
mbed_official	610:813dcc80987e	2158	#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == RESET)
mbed_official	610:813dcc80987e	2159
mbed_official	610:813dcc80987e	2160	#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == RESET)
mbed_official	610:813dcc80987e	2161
mbed_official	610:813dcc80987e	2162	#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == RESET)
mbed_official	610:813dcc80987e	2163
mbed_official	610:813dcc80987e	2164	#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) == RESET)
mbed_official	610:813dcc80987e	2165
mbed_official	610:813dcc80987e	2166	#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == RESET)
mbed_official	610:813dcc80987e	2167
mbed_official	610:813dcc80987e	2168	/**
mbed_official	610:813dcc80987e	2169	* @}
mbed_official	610:813dcc80987e	2170	*/
mbed_official	610:813dcc80987e	2171
mbed_official	610:813dcc80987e	2172	/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status
mbed_official	610:813dcc80987e	2173	* @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
mbed_official	610:813dcc80987e	2174	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	610:813dcc80987e	2175	* power consumption.
mbed_official	610:813dcc80987e	2176	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	610:813dcc80987e	2177	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	610:813dcc80987e	2178	* @{
mbed_official	610:813dcc80987e	2179	*/
mbed_official	610:813dcc80987e	2180
mbed_official	610:813dcc80987e	2181	#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != RESET)
mbed_official	610:813dcc80987e	2182
mbed_official	610:813dcc80987e	2183	#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != RESET)
mbed_official	610:813dcc80987e	2184
mbed_official	610:813dcc80987e	2185	#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != RESET)
mbed_official	610:813dcc80987e	2186
mbed_official	610:813dcc80987e	2187	#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != RESET)
mbed_official	610:813dcc80987e	2188
mbed_official	610:813dcc80987e	2189	#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != RESET)
mbed_official	610:813dcc80987e	2190
mbed_official	610:813dcc80987e	2191	#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET)
mbed_official	610:813dcc80987e	2192
mbed_official	610:813dcc80987e	2193	#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != RESET)
mbed_official	610:813dcc80987e	2194
mbed_official	610:813dcc80987e	2195	#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != RESET)
mbed_official	610:813dcc80987e	2196
mbed_official	610:813dcc80987e	2197	#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != RESET)
mbed_official	610:813dcc80987e	2198
mbed_official	610:813dcc80987e	2199	#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != RESET)
mbed_official	610:813dcc80987e	2200
mbed_official	610:813dcc80987e	2201	#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != RESET)
mbed_official	610:813dcc80987e	2202
mbed_official	610:813dcc80987e	2203	#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDMSMEN) != RESET)
mbed_official	610:813dcc80987e	2204
mbed_official	610:813dcc80987e	2205	#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == RESET)
mbed_official	610:813dcc80987e	2206
mbed_official	610:813dcc80987e	2207	#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == RESET)
mbed_official	610:813dcc80987e	2208
mbed_official	610:813dcc80987e	2209	#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET)
mbed_official	610:813dcc80987e	2210
mbed_official	610:813dcc80987e	2211	#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == RESET)
mbed_official	610:813dcc80987e	2212
mbed_official	610:813dcc80987e	2213	#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == RESET)
mbed_official	610:813dcc80987e	2214
mbed_official	610:813dcc80987e	2215	#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == RESET)
mbed_official	610:813dcc80987e	2216
mbed_official	610:813dcc80987e	2217	#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == RESET)
mbed_official	610:813dcc80987e	2218
mbed_official	610:813dcc80987e	2219	#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == RESET)
mbed_official	610:813dcc80987e	2220
mbed_official	610:813dcc80987e	2221	#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == RESET)
mbed_official	610:813dcc80987e	2222
mbed_official	610:813dcc80987e	2223	#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == RESET)
mbed_official	610:813dcc80987e	2224
mbed_official	610:813dcc80987e	2225	#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == RESET)
mbed_official	610:813dcc80987e	2226
mbed_official	610:813dcc80987e	2227	#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDMSMEN) == RESET)
mbed_official	610:813dcc80987e	2228
mbed_official	610:813dcc80987e	2229	/**
mbed_official	610:813dcc80987e	2230	* @}
mbed_official	610:813dcc80987e	2231	*/
mbed_official	610:813dcc80987e	2232
mbed_official	610:813dcc80987e	2233	/** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset
mbed_official	610:813dcc80987e	2234	* @{
mbed_official	610:813dcc80987e	2235	*/
mbed_official	610:813dcc80987e	2236
mbed_official	610:813dcc80987e	2237	/** @brief Macros to force or release the Backup domain reset.
mbed_official	610:813dcc80987e	2238	* @note This function resets the RTC peripheral (including the backup registers)
mbed_official	610:813dcc80987e	2239	* and the RTC clock source selection in RCC_CSR register.
mbed_official	610:813dcc80987e	2240	* @note The BKPSRAM is not affected by this reset.
mbed_official	610:813dcc80987e	2241	* @retval None
mbed_official	610:813dcc80987e	2242	*/
mbed_official	610:813dcc80987e	2243	#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
mbed_official	610:813dcc80987e	2244
mbed_official	610:813dcc80987e	2245	#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
mbed_official	610:813dcc80987e	2246
mbed_official	610:813dcc80987e	2247	/**
mbed_official	610:813dcc80987e	2248	* @}
mbed_official	610:813dcc80987e	2249	*/
mbed_official	610:813dcc80987e	2250
mbed_official	610:813dcc80987e	2251	/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
mbed_official	610:813dcc80987e	2252	* @{
mbed_official	610:813dcc80987e	2253	*/
mbed_official	610:813dcc80987e	2254
mbed_official	610:813dcc80987e	2255	/** @brief Macros to enable or disable the RTC clock.
mbed_official	610:813dcc80987e	2256	* @note As the RTC is in the Backup domain and write access is denied to
mbed_official	610:813dcc80987e	2257	* this domain after reset, you have to enable write access using
mbed_official	610:813dcc80987e	2258	* HAL_PWR_EnableBkUpAccess() function before to configure the RTC
mbed_official	610:813dcc80987e	2259	* (to be done once after reset).
mbed_official	610:813dcc80987e	2260	* @note These macros must be used after the RTC clock source was selected.
mbed_official	610:813dcc80987e	2261	* @retval None
mbed_official	610:813dcc80987e	2262	*/
mbed_official	610:813dcc80987e	2263	#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
mbed_official	610:813dcc80987e	2264
mbed_official	610:813dcc80987e	2265	#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
mbed_official	610:813dcc80987e	2266
mbed_official	610:813dcc80987e	2267	/**
mbed_official	610:813dcc80987e	2268	* @}
mbed_official	610:813dcc80987e	2269	*/
mbed_official	610:813dcc80987e	2270
mbed_official	610:813dcc80987e	2271	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
mbed_official	610:813dcc80987e	2272	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	610:813dcc80987e	2273	* It is used (enabled by hardware) as system clock source after startup
mbed_official	610:813dcc80987e	2274	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
mbed_official	610:813dcc80987e	2275	* of the HSE used directly or indirectly as system clock (if the Clock
mbed_official	610:813dcc80987e	2276	* Security System CSS is enabled).
mbed_official	610:813dcc80987e	2277	* @note HSI can not be stopped if it is used as system clock source. In this case,
mbed_official	610:813dcc80987e	2278	* you have to select another source of the system clock then stop the HSI.
mbed_official	610:813dcc80987e	2279	* @note After enabling the HSI, the application software should wait on HSIRDY
mbed_official	610:813dcc80987e	2280	* flag to be set indicating that HSI clock is stable and can be used as
mbed_official	610:813dcc80987e	2281	* system clock source.
mbed_official	610:813dcc80987e	2282	* This parameter can be: ENABLE or DISABLE.
mbed_official	610:813dcc80987e	2283	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
mbed_official	610:813dcc80987e	2284	* clock cycles.
mbed_official	610:813dcc80987e	2285	* @retval None
mbed_official	610:813dcc80987e	2286	*/
mbed_official	610:813dcc80987e	2287	#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
mbed_official	610:813dcc80987e	2288
mbed_official	610:813dcc80987e	2289	#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
mbed_official	610:813dcc80987e	2290
mbed_official	610:813dcc80987e	2291	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
mbed_official	610:813dcc80987e	2292	* @note The calibration is used to compensate for the variations in voltage
mbed_official	610:813dcc80987e	2293	* and temperature that influence the frequency of the internal HSI RC.
mbed_official	610:813dcc80987e	2294	* @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value
mbed_official	610:813dcc80987e	2295	* (default is RCC_HSICALIBRATION_DEFAULT).
mbed_official	610:813dcc80987e	2296	* This parameter must be a number between 0 and 31.
mbed_official	610:813dcc80987e	2297	* @retval None
mbed_official	610:813dcc80987e	2298	*/
mbed_official	610:813dcc80987e	2299	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \
mbed_official	610:813dcc80987e	2300	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_ICSCR_HSITRIM))
mbed_official	610:813dcc80987e	2301
mbed_official	610:813dcc80987e	2302	/**
mbed_official	610:813dcc80987e	2303	* @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI)
mbed_official	610:813dcc80987e	2304	* in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup.
mbed_official	610:813dcc80987e	2305	* @note The enable of this function has not effect on the HSION bit.
mbed_official	610:813dcc80987e	2306	* This parameter can be: ENABLE or DISABLE.
mbed_official	610:813dcc80987e	2307	* @retval None
mbed_official	610:813dcc80987e	2308	*/
mbed_official	610:813dcc80987e	2309	#define __HAL_RCC_HSIAUTOMATIC_START_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIASFS)
mbed_official	610:813dcc80987e	2310
mbed_official	610:813dcc80987e	2311	#define __HAL_RCC_HSIAUTOMATIC_START_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS)
mbed_official	610:813dcc80987e	2312
mbed_official	610:813dcc80987e	2313	/**
mbed_official	610:813dcc80987e	2314	* @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
mbed_official	610:813dcc80987e	2315	* in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
mbed_official	610:813dcc80987e	2316	* @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
mbed_official	610:813dcc80987e	2317	* speed because of the HSI startup time.
mbed_official	610:813dcc80987e	2318	* @note The enable of this function has not effect on the HSION bit.
mbed_official	610:813dcc80987e	2319	* This parameter can be: ENABLE or DISABLE.
mbed_official	610:813dcc80987e	2320	* @retval None
mbed_official	610:813dcc80987e	2321	*/
mbed_official	610:813dcc80987e	2322	#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
mbed_official	610:813dcc80987e	2323
mbed_official	610:813dcc80987e	2324	#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
mbed_official	610:813dcc80987e	2325
mbed_official	610:813dcc80987e	2326	/**
mbed_official	610:813dcc80987e	2327	* @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI).
mbed_official	610:813dcc80987e	2328	* @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	610:813dcc80987e	2329	* It is used (enabled by hardware) as system clock source after
mbed_official	610:813dcc80987e	2330	* startup from Reset, wakeup from STOP and STANDBY mode, or in case
mbed_official	610:813dcc80987e	2331	* of failure of the HSE used directly or indirectly as system clock
mbed_official	610:813dcc80987e	2332	* (if the Clock Security System CSS is enabled).
mbed_official	610:813dcc80987e	2333	* @note MSI can not be stopped if it is used as system clock source.
mbed_official	610:813dcc80987e	2334	* In this case, you have to select another source of the system
mbed_official	610:813dcc80987e	2335	* clock then stop the MSI.
mbed_official	610:813dcc80987e	2336	* @note After enabling the MSI, the application software should wait on
mbed_official	610:813dcc80987e	2337	* MSIRDY flag to be set indicating that MSI clock is stable and can
mbed_official	610:813dcc80987e	2338	* be used as system clock source.
mbed_official	610:813dcc80987e	2339	* @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
mbed_official	610:813dcc80987e	2340	* clock cycles.
mbed_official	610:813dcc80987e	2341	* @retval None
mbed_official	610:813dcc80987e	2342	*/
mbed_official	610:813dcc80987e	2343	#define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION)
mbed_official	610:813dcc80987e	2344
mbed_official	610:813dcc80987e	2345	#define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
mbed_official	610:813dcc80987e	2346
mbed_official	610:813dcc80987e	2347	/** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
mbed_official	610:813dcc80987e	2348	* @note The calibration is used to compensate for the variations in voltage
mbed_official	610:813dcc80987e	2349	* and temperature that influence the frequency of the internal MSI RC.
mbed_official	610:813dcc80987e	2350	* Refer to the Application Note AN3300 for more details on how to
mbed_official	610:813dcc80987e	2351	* calibrate the MSI.
mbed_official	610:813dcc80987e	2352	* @param __MSICALIBRATIONVALUE__: specifies the calibration trimming value
mbed_official	610:813dcc80987e	2353	* (default is RCC_MSICALIBRATION_DEFAULT).
mbed_official	610:813dcc80987e	2354	* This parameter must be a number between 0 and 255.
mbed_official	610:813dcc80987e	2355	* @retval None
mbed_official	610:813dcc80987e	2356	*/
mbed_official	610:813dcc80987e	2357	#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \
mbed_official	610:813dcc80987e	2358	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(__MSICALIBRATIONVALUE__) << 8)
mbed_official	610:813dcc80987e	2359
mbed_official	610:813dcc80987e	2360	/**
mbed_official	610:813dcc80987e	2361	* @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode
mbed_official	610:813dcc80987e	2362	* @note After restart from Reset , the MSI clock is around 4 MHz.
mbed_official	610:813dcc80987e	2363	* After stop the startup clock can be MSI (at any of its possible
mbed_official	610:813dcc80987e	2364	* frequencies, the one that was used before entering stop mode) or HSI.
mbed_official	610:813dcc80987e	2365	* After Standby its frequency can be selected between 4 possible values
mbed_official	610:813dcc80987e	2366	* (1, 2, 4 or 8 MHz).
mbed_official	610:813dcc80987e	2367	* @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready
mbed_official	610:813dcc80987e	2368	* (MSIRDY=1).
mbed_official	610:813dcc80987e	2369	* @note The MSI clock range after reset can be modified on the fly.
mbed_official	610:813dcc80987e	2370	* @param __MSIRANGEVALUE__: specifies the MSI clock range.
mbed_official	610:813dcc80987e	2371	* This parameter must be one of the following values:
mbed_official	610:813dcc80987e	2372	* @arg RCC_MSIRANGE_0: MSI clock is around 100 KHz
mbed_official	610:813dcc80987e	2373	* @arg RCC_MSIRANGE_1: MSI clock is around 200 KHz
mbed_official	610:813dcc80987e	2374	* @arg RCC_MSIRANGE_2: MSI clock is around 400 KHz
mbed_official	610:813dcc80987e	2375	* @arg RCC_MSIRANGE_3: MSI clock is around 800 KHz
mbed_official	610:813dcc80987e	2376	* @arg RCC_MSIRANGE_4: MSI clock is around 1 MHz
mbed_official	610:813dcc80987e	2377	* @arg RCC_MSIRANGE_5: MSI clock is around 2MHz
mbed_official	610:813dcc80987e	2378	* @arg RCC_MSIRANGE_6: MSI clock is around 4MHz (default after Reset)
mbed_official	610:813dcc80987e	2379	* @arg RCC_MSIRANGE_7: MSI clock is around 8 MHz
mbed_official	610:813dcc80987e	2380	* @arg RCC_MSIRANGE_8: MSI clock is around 16 MHz
mbed_official	610:813dcc80987e	2381	* @arg RCC_MSIRANGE_9: MSI clock is around 24 MHz
mbed_official	610:813dcc80987e	2382	* @arg RCC_MSIRANGE_10: MSI clock is around 32 MHz
mbed_official	610:813dcc80987e	2383	* @arg RCC_MSIRANGE_11: MSI clock is around 48 MHz
mbed_official	610:813dcc80987e	2384	* @retval None
mbed_official	610:813dcc80987e	2385	*/
mbed_official	610:813dcc80987e	2386	#define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \
mbed_official	610:813dcc80987e	2387	do { \
mbed_official	610:813dcc80987e	2388	SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); \
mbed_official	610:813dcc80987e	2389	MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \
mbed_official	610:813dcc80987e	2390	} while(0)
mbed_official	610:813dcc80987e	2391
mbed_official	610:813dcc80987e	2392	/**
mbed_official	610:813dcc80987e	2393	* @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode
mbed_official	610:813dcc80987e	2394	* After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).
mbed_official	610:813dcc80987e	2395	* @param __MSIRANGEVALUE__: specifies the MSI clock range.
mbed_official	610:813dcc80987e	2396	* This parameter must be one of the following values:
mbed_official	610:813dcc80987e	2397	* @arg RCC_MSIRANGE_4: MSI clock is around 1 MHz
mbed_official	610:813dcc80987e	2398	* @arg RCC_MSIRANGE_5: MSI clock is around 2MHz
mbed_official	610:813dcc80987e	2399	* @arg RCC_MSIRANGE_6: MSI clock is around 4MHz (default after Reset)
mbed_official	610:813dcc80987e	2400	* @arg RCC_MSIRANGE_7: MSI clock is around 8 MHz
mbed_official	610:813dcc80987e	2401	* @retval None
mbed_official	610:813dcc80987e	2402	*/
mbed_official	610:813dcc80987e	2403	#define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) \
mbed_official	610:813dcc80987e	2404	MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U)
mbed_official	610:813dcc80987e	2405
mbed_official	610:813dcc80987e	2406	/** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode
mbed_official	610:813dcc80987e	2407	* @retval MSI clock range.
mbed_official	610:813dcc80987e	2408	* This parameter must be one of the following values:
mbed_official	610:813dcc80987e	2409	* @arg RCC_MSIRANGE_0: MSI clock is around 100 KHz
mbed_official	610:813dcc80987e	2410	* @arg RCC_MSIRANGE_1: MSI clock is around 200 KHz
mbed_official	610:813dcc80987e	2411	* @arg RCC_MSIRANGE_2: MSI clock is around 400 KHz
mbed_official	610:813dcc80987e	2412	* @arg RCC_MSIRANGE_3: MSI clock is around 800 KHz
mbed_official	610:813dcc80987e	2413	* @arg RCC_MSIRANGE_4: MSI clock is around 1 MHz
mbed_official	610:813dcc80987e	2414	* @arg RCC_MSIRANGE_5: MSI clock is around 2MHz
mbed_official	610:813dcc80987e	2415	* @arg RCC_MSIRANGE_6: MSI clock is around 4MHz (default after Reset)
mbed_official	610:813dcc80987e	2416	* @arg RCC_MSIRANGE_7: MSI clock is around 8 MHz
mbed_official	610:813dcc80987e	2417	* @arg RCC_MSIRANGE_8: MSI clock is around 16 MHz
mbed_official	610:813dcc80987e	2418	* @arg RCC_MSIRANGE_9: MSI clock is around 24 MHz
mbed_official	610:813dcc80987e	2419	* @arg RCC_MSIRANGE_10: MSI clock is around 32 MHz
mbed_official	610:813dcc80987e	2420	* @arg RCC_MSIRANGE_11: MSI clock is around 48 MHz
mbed_official	610:813dcc80987e	2421	*/
mbed_official	610:813dcc80987e	2422	#define __HAL_RCC_GET_MSI_RANGE() \
mbed_official	610:813dcc80987e	2423	((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != RESET) ? \
mbed_official	610:813dcc80987e	2424	(uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)) : \
mbed_official	610:813dcc80987e	2425	(uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4))
mbed_official	610:813dcc80987e	2426
mbed_official	610:813dcc80987e	2427	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
mbed_official	610:813dcc80987e	2428	* @note After enabling the LSI, the application software should wait on
mbed_official	610:813dcc80987e	2429	* LSIRDY flag to be set indicating that LSI clock is stable and can
mbed_official	610:813dcc80987e	2430	* be used to clock the IWDG and/or the RTC.
mbed_official	610:813dcc80987e	2431	* @note LSI can not be disabled if the IWDG is running.
mbed_official	610:813dcc80987e	2432	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
mbed_official	610:813dcc80987e	2433	* clock cycles.
mbed_official	610:813dcc80987e	2434	* @retval None
mbed_official	610:813dcc80987e	2435	*/
mbed_official	610:813dcc80987e	2436	#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
mbed_official	610:813dcc80987e	2437
mbed_official	610:813dcc80987e	2438	#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
mbed_official	610:813dcc80987e	2439
mbed_official	610:813dcc80987e	2440	/**
mbed_official	610:813dcc80987e	2441	* @brief Macro to configure the External High Speed oscillator (HSE).
mbed_official	610:813dcc80987e	2442	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
mbed_official	610:813dcc80987e	2443	* supported by this macro. User should request a transition to HSE Off
mbed_official	610:813dcc80987e	2444	* first and then HSE On or HSE Bypass.
mbed_official	610:813dcc80987e	2445	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
mbed_official	610:813dcc80987e	2446	* software should wait on HSERDY flag to be set indicating that HSE clock
mbed_official	610:813dcc80987e	2447	* is stable and can be used to clock the PLL and/or system clock.
mbed_official	610:813dcc80987e	2448	* @note HSE state can not be changed if it is used directly or through the
mbed_official	610:813dcc80987e	2449	* PLL as system clock. In this case, you have to select another source
mbed_official	610:813dcc80987e	2450	* of the system clock then change the HSE state (ex. disable it).
mbed_official	610:813dcc80987e	2451	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	610:813dcc80987e	2452	* @note This function reset the CSSON bit, so if the clock security system(CSS)
mbed_official	610:813dcc80987e	2453	* was previously enabled you have to enable it again after calling this
mbed_official	610:813dcc80987e	2454	* function.
mbed_official	610:813dcc80987e	2455	* @param __STATE__: specifies the new state of the HSE.
mbed_official	610:813dcc80987e	2456	* This parameter can be one of the following values:
mbed_official	610:813dcc80987e	2457	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
mbed_official	610:813dcc80987e	2458	* 6 HSE oscillator clock cycles.
mbed_official	610:813dcc80987e	2459	* @arg RCC_HSE_ON: turn ON the HSE oscillator.
mbed_official	610:813dcc80987e	2460	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
mbed_official	610:813dcc80987e	2461	* @retval None
mbed_official	610:813dcc80987e	2462	*/
mbed_official	610:813dcc80987e	2463	#define __HAL_RCC_HSE_CONFIG(__STATE__) \
mbed_official	610:813dcc80987e	2464	do { \
mbed_official	610:813dcc80987e	2465	if((__STATE__) == RCC_HSE_ON) \
mbed_official	610:813dcc80987e	2466	{ \
mbed_official	610:813dcc80987e	2467	SET_BIT(RCC->CR, RCC_CR_HSEON); \
mbed_official	610:813dcc80987e	2468	} \
mbed_official	610:813dcc80987e	2469	else if((__STATE__) == RCC_HSE_BYPASS) \
mbed_official	610:813dcc80987e	2470	{ \
mbed_official	610:813dcc80987e	2471	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
mbed_official	610:813dcc80987e	2472	SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
mbed_official	610:813dcc80987e	2473	SET_BIT(RCC->CR, RCC_CR_HSEON); \
mbed_official	610:813dcc80987e	2474	} \
mbed_official	610:813dcc80987e	2475	else \
mbed_official	610:813dcc80987e	2476	{ \
mbed_official	610:813dcc80987e	2477	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
mbed_official	610:813dcc80987e	2478	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
mbed_official	610:813dcc80987e	2479	} \
mbed_official	610:813dcc80987e	2480	} while(0)
mbed_official	610:813dcc80987e	2481
mbed_official	610:813dcc80987e	2482	/**
mbed_official	610:813dcc80987e	2483	* @brief Macro to configure the External Low Speed oscillator (LSE).
mbed_official	610:813dcc80987e	2484	* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
mbed_official	610:813dcc80987e	2485	* supported by this macro. User should request a transition to LSE Off
mbed_official	610:813dcc80987e	2486	* first and then LSE On or LSE Bypass.
mbed_official	610:813dcc80987e	2487	* @note As the LSE is in the Backup domain and write access is denied to
mbed_official	610:813dcc80987e	2488	* this domain after reset, you have to enable write access using
mbed_official	610:813dcc80987e	2489	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
mbed_official	610:813dcc80987e	2490	* (to be done once after reset).
mbed_official	610:813dcc80987e	2491	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
mbed_official	610:813dcc80987e	2492	* software should wait on LSERDY flag to be set indicating that LSE clock
mbed_official	610:813dcc80987e	2493	* is stable and can be used to clock the RTC.
mbed_official	610:813dcc80987e	2494	* @param __STATE__: specifies the new state of the LSE.
mbed_official	610:813dcc80987e	2495	* This parameter can be one of the following values:
mbed_official	610:813dcc80987e	2496	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
mbed_official	610:813dcc80987e	2497	* 6 LSE oscillator clock cycles.
mbed_official	610:813dcc80987e	2498	* @arg RCC_LSE_ON: turn ON the LSE oscillator.
mbed_official	610:813dcc80987e	2499	* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
mbed_official	610:813dcc80987e	2500	* @retval None
mbed_official	610:813dcc80987e	2501	*/
mbed_official	610:813dcc80987e	2502	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
mbed_official	610:813dcc80987e	2503	do { \
mbed_official	610:813dcc80987e	2504	if((__STATE__) == RCC_LSE_ON) \
mbed_official	610:813dcc80987e	2505	{ \
mbed_official	610:813dcc80987e	2506	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
mbed_official	610:813dcc80987e	2507	} \
mbed_official	610:813dcc80987e	2508	else if((__STATE__) == RCC_LSE_OFF) \
mbed_official	610:813dcc80987e	2509	{ \
mbed_official	610:813dcc80987e	2510	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
mbed_official	610:813dcc80987e	2511	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
mbed_official	610:813dcc80987e	2512	} \
mbed_official	610:813dcc80987e	2513	else if((__STATE__) == RCC_LSE_BYPASS) \
mbed_official	610:813dcc80987e	2514	{ \
mbed_official	610:813dcc80987e	2515	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
mbed_official	610:813dcc80987e	2516	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
mbed_official	610:813dcc80987e	2517	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
mbed_official	610:813dcc80987e	2518	} \
mbed_official	610:813dcc80987e	2519	else \
mbed_official	610:813dcc80987e	2520	{ \
mbed_official	610:813dcc80987e	2521	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
mbed_official	610:813dcc80987e	2522	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
mbed_official	610:813dcc80987e	2523	} \
mbed_official	610:813dcc80987e	2524	} while(0)
mbed_official	610:813dcc80987e	2525
mbed_official	610:813dcc80987e	2526	/** @brief Macros to configure the RTC clock (RTCCLK).
mbed_official	610:813dcc80987e	2527	* @note As the RTC clock configuration bits are in the Backup domain and write
mbed_official	610:813dcc80987e	2528	* access is denied to this domain after reset, you have to enable write
mbed_official	610:813dcc80987e	2529	* access using the Power Backup Access macro before to configure
mbed_official	610:813dcc80987e	2530	* the RTC clock source (to be done once after reset).
mbed_official	610:813dcc80987e	2531	* @note Once the RTC clock is configured it cannot be changed unless the
mbed_official	610:813dcc80987e	2532	* Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
mbed_official	610:813dcc80987e	2533	* a Power On Reset (POR).
mbed_official	610:813dcc80987e	2534	*
mbed_official	610:813dcc80987e	2535	* @param __RTC_CLKSOURCE__: specifies the RTC clock source.
mbed_official	610:813dcc80987e	2536	* This parameter can be one of the following values:
mbed_official	610:813dcc80987e	2537	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
mbed_official	610:813dcc80987e	2538	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
mbed_official	610:813dcc80987e	2539	* @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 selected
mbed_official	610:813dcc80987e	2540	*
mbed_official	610:813dcc80987e	2541	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
mbed_official	610:813dcc80987e	2542	* work in STOP and STANDBY modes, and can be used as wakeup source.
mbed_official	610:813dcc80987e	2543	* However, when the HSE clock is used as RTC clock source, the RTC
mbed_official	610:813dcc80987e	2544	* cannot be used in STOP and STANDBY modes.
mbed_official	610:813dcc80987e	2545	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
mbed_official	610:813dcc80987e	2546	* RTC clock source).
mbed_official	610:813dcc80987e	2547	* @retval None
mbed_official	610:813dcc80987e	2548	*/
mbed_official	610:813dcc80987e	2549	#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \
mbed_official	610:813dcc80987e	2550	MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
mbed_official	610:813dcc80987e	2551
mbed_official	610:813dcc80987e	2552
mbed_official	610:813dcc80987e	2553	/** @brief Macro to get the RTC clock source.
mbed_official	610:813dcc80987e	2554	* @retval The returned value can be one of the following:
mbed_official	610:813dcc80987e	2555	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
mbed_official	610:813dcc80987e	2556	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
mbed_official	610:813dcc80987e	2557	* @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 selected
mbed_official	610:813dcc80987e	2558	*/
mbed_official	610:813dcc80987e	2559	#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
mbed_official	610:813dcc80987e	2560
mbed_official	610:813dcc80987e	2561	/** @brief Macros to enable or disable the main PLL.
mbed_official	610:813dcc80987e	2562	* @note After enabling the main PLL, the application software should wait on
mbed_official	610:813dcc80987e	2563	* PLLRDY flag to be set indicating that PLL clock is stable and can
mbed_official	610:813dcc80987e	2564	* be used as system clock source.
mbed_official	610:813dcc80987e	2565	* @note The main PLL can not be disabled if it is used as system clock source
mbed_official	610:813dcc80987e	2566	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
mbed_official	610:813dcc80987e	2567	* @retval None
mbed_official	610:813dcc80987e	2568	*/
mbed_official	610:813dcc80987e	2569	#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
mbed_official	610:813dcc80987e	2570
mbed_official	610:813dcc80987e	2571	#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
mbed_official	610:813dcc80987e	2572
mbed_official	610:813dcc80987e	2573	/** @brief Macro to configure the PLL clock source.
mbed_official	610:813dcc80987e	2574	* @note This function must be used only when the main PLL is disabled.
mbed_official	610:813dcc80987e	2575	* @param __PLLSOURCE__: specifies the PLL entry clock source.
mbed_official	610:813dcc80987e	2576	* This parameter can be one of the following values:
mbed_official	610:813dcc80987e	2577	* @arg RCC_PLLSOURCE_NONE: No clock selected as PLL clock entry
mbed_official	610:813dcc80987e	2578	* @arg RCC_PLLSOURCE_MSI: MSI oscillator clock selected as PLL clock entry
mbed_official	610:813dcc80987e	2579	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
mbed_official	610:813dcc80987e	2580	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
mbed_official	610:813dcc80987e	2581	* @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).
mbed_official	610:813dcc80987e	2582	* @retval None
mbed_official	610:813dcc80987e	2583	*
mbed_official	610:813dcc80987e	2584	*/
mbed_official	610:813dcc80987e	2585	#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \
mbed_official	610:813dcc80987e	2586	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
mbed_official	610:813dcc80987e	2587
mbed_official	610:813dcc80987e	2588	/** @brief Macro to configure the PLL multiplication factor.
mbed_official	610:813dcc80987e	2589	* @note This function must be used only when the main PLL is disabled.
mbed_official	610:813dcc80987e	2590	* @param __PLLM__: specifies the division factor for PLL VCO input clock
mbed_official	610:813dcc80987e	2591	* This parameter must be a number between Min_Data = 1 and Max_Data = 8.
mbed_official	610:813dcc80987e	2592	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
mbed_official	610:813dcc80987e	2593	* frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
mbed_official	610:813dcc80987e	2594	* of 16 MHz to limit PLL jitter.
mbed_official	610:813dcc80987e	2595	* @retval None
mbed_official	610:813dcc80987e	2596	*
mbed_official	610:813dcc80987e	2597	*/
mbed_official	610:813dcc80987e	2598	#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \
mbed_official	610:813dcc80987e	2599	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U)
mbed_official	610:813dcc80987e	2600
mbed_official	610:813dcc80987e	2601	/**
mbed_official	610:813dcc80987e	2602	* @brief Macro to configure the main PLL clock source, multiplication and division factors.
mbed_official	610:813dcc80987e	2603	* @note This function must be used only when the main PLL is disabled.
mbed_official	610:813dcc80987e	2604	*
mbed_official	610:813dcc80987e	2605	* @param __PLLSOURCE__: specifies the PLL entry clock source.
mbed_official	610:813dcc80987e	2606	* This parameter can be one of the following values:
mbed_official	610:813dcc80987e	2607	* @arg RCC_PLLSOURCE_NONE: No clock selected as PLL clock entry
mbed_official	610:813dcc80987e	2608	* @arg RCC_PLLSOURCE_MSI: MSI oscillator clock selected as PLL clock entry
mbed_official	610:813dcc80987e	2609	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
mbed_official	610:813dcc80987e	2610	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
mbed_official	610:813dcc80987e	2611	* @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).
mbed_official	610:813dcc80987e	2612	*
mbed_official	610:813dcc80987e	2613	* @param __PLLM__: specifies the division factor for PLL VCO input clock.
mbed_official	610:813dcc80987e	2614	* This parameter must be a number between 1 and 8.
mbed_official	610:813dcc80987e	2615	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
mbed_official	610:813dcc80987e	2616	* frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
mbed_official	610:813dcc80987e	2617	* of 16 MHz to limit PLL jitter.
mbed_official	610:813dcc80987e	2618	*
mbed_official	610:813dcc80987e	2619	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock.
mbed_official	610:813dcc80987e	2620	* This parameter must be a number between 8 and 86.
mbed_official	610:813dcc80987e	2621	* @note You have to set the PLLN parameter correctly to ensure that the VCO
mbed_official	610:813dcc80987e	2622	* output frequency is between 64 and 344 MHz.
mbed_official	610:813dcc80987e	2623	*
mbed_official	610:813dcc80987e	2624	* @param __PLLP__: specifies the division factor for SAI clock.
mbed_official	610:813dcc80987e	2625	* This parameter must be a number in the range (7 or 17).
mbed_official	610:813dcc80987e	2626	*
mbed_official	610:813dcc80987e	2627	* @param __PLLQ__: specifies the division factor for OTG FS, SDMMC1 and RNG clocks.
mbed_official	610:813dcc80987e	2628	* This parameter must be in the range (2, 4, 6 or 8).
mbed_official	610:813dcc80987e	2629	* @note If the USB OTG FS is used in your application, you have to set the
mbed_official	610:813dcc80987e	2630	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
mbed_official	610:813dcc80987e	2631	* the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work
mbed_official	610:813dcc80987e	2632	* correctly.
mbed_official	610:813dcc80987e	2633	* @param __PLLR__: specifies the division factor for the main system clock.
mbed_official	610:813dcc80987e	2634	* @note You have to set the PLLR parameter correctly to not exceed 80MHZ.
mbed_official	610:813dcc80987e	2635	* This parameter must be in the range (2, 4, 6 or 8).
mbed_official	610:813dcc80987e	2636	* @retval None
mbed_official	610:813dcc80987e	2637	*/
mbed_official	610:813dcc80987e	2638	#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
mbed_official	610:813dcc80987e	2639	(RCC->PLLCFGR = (((__PLLM__) - 1) << 4U) \| ((__PLLN__) << 8U) \| (((__PLLP__) >> 4U ) << 17U) \| \
mbed_official	610:813dcc80987e	2640	(__PLLSOURCE__) \| ((((__PLLQ__) >> 1U) - 1) << 21U) \| ((((__PLLR__) >> 1U) - 1) << 25U))
mbed_official	610:813dcc80987e	2641
mbed_official	610:813dcc80987e	2642	/** @brief Macro to get the oscillator used as PLL clock source.
mbed_official	610:813dcc80987e	2643	* @retval The oscillator used as PLL clock source. The returned value can be one
mbed_official	610:813dcc80987e	2644	* of the following:
mbed_official	610:813dcc80987e	2645	* - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
mbed_official	610:813dcc80987e	2646	* - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source.
mbed_official	610:813dcc80987e	2647	* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
mbed_official	610:813dcc80987e	2648	* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
mbed_official	610:813dcc80987e	2649	*/
mbed_official	610:813dcc80987e	2650	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
mbed_official	610:813dcc80987e	2651
mbed_official	610:813dcc80987e	2652	/**
mbed_official	610:813dcc80987e	2653	* @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
mbed_official	610:813dcc80987e	2654	* @note Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime
mbed_official	610:813dcc80987e	2655	* without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot
mbed_official	610:813dcc80987e	2656	* be stopped if used as System Clock.
mbed_official	610:813dcc80987e	2657	* @param __PLLCLOCKOUT__: specifies the PLL clock to be output.
mbed_official	610:813dcc80987e	2658	* This parameter can be one or a combination of the following values:
mbed_official	610:813dcc80987e	2659	* @arg RCC_PLL_SAI3CLK: This clock is used to generate an accurate clock to achieve
mbed_official	610:813dcc80987e	2660	* high-quality audio performance on SAI interface in case.
mbed_official	610:813dcc80987e	2661	* @arg RCC_PLL_48M1CLK: This Clock is used to generate the clock for the USB OTG FS (48 MHz),
mbed_official	610:813dcc80987e	2662	* the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
mbed_official	610:813dcc80987e	2663	* @arg RCC_PLL_SYSCLK: This Clock is used to generate the high speed system clock (up to 80MHz)
mbed_official	610:813dcc80987e	2664	* @retval None
mbed_official	610:813dcc80987e	2665	*/
mbed_official	610:813dcc80987e	2666	#define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
mbed_official	610:813dcc80987e	2667
mbed_official	610:813dcc80987e	2668	#define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
mbed_official	610:813dcc80987e	2669
mbed_official	610:813dcc80987e	2670	/**
mbed_official	610:813dcc80987e	2671	* @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
mbed_official	610:813dcc80987e	2672	* @param __PLLCLOCKOUT__: specifies the output PLL clock to be checked.
mbed_official	610:813dcc80987e	2673	* This parameter can be one of the following values:
mbed_official	610:813dcc80987e	2674	* @arg RCC_PLL_SAI3CLK: This clock is used to generate an accurate clock to achieve
mbed_official	610:813dcc80987e	2675	* high-quality audio performance on SAI interface in case.
mbed_official	610:813dcc80987e	2676	* @arg RCC_PLL_48M1CLK: This Clock is used to generate the clock for the USB OTG FS (48 MHz),
mbed_official	610:813dcc80987e	2677	* the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
mbed_official	610:813dcc80987e	2678	* @arg RCC_PLL_SYSCLK: This Clock is used to generate the high speed system clock (up to 80MHz)
mbed_official	610:813dcc80987e	2679	* @retval SET / RESET
mbed_official	610:813dcc80987e	2680	*/
mbed_official	610:813dcc80987e	2681	#define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
mbed_official	610:813dcc80987e	2682
mbed_official	610:813dcc80987e	2683	/**
mbed_official	610:813dcc80987e	2684	* @brief Macro to configure the system clock source.
mbed_official	610:813dcc80987e	2685	* @param __SYSCLKSOURCE__: specifies the system clock source.
mbed_official	610:813dcc80987e	2686	* This parameter can be one of the following values:
mbed_official	610:813dcc80987e	2687	* - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source.
mbed_official	610:813dcc80987e	2688	* - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
mbed_official	610:813dcc80987e	2689	* - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
mbed_official	610:813dcc80987e	2690	* - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
mbed_official	610:813dcc80987e	2691	* @retval None
mbed_official	610:813dcc80987e	2692	*/
mbed_official	610:813dcc80987e	2693	#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
mbed_official	610:813dcc80987e	2694	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
mbed_official	610:813dcc80987e	2695
mbed_official	610:813dcc80987e	2696	/** @brief Macro to get the clock source used as system clock.
mbed_official	610:813dcc80987e	2697	* @retval The clock source used as system clock. The returned value can be one
mbed_official	610:813dcc80987e	2698	* of the following:
mbed_official	610:813dcc80987e	2699	* - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock.
mbed_official	610:813dcc80987e	2700	* - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
mbed_official	610:813dcc80987e	2701	* - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
mbed_official	610:813dcc80987e	2702	* - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
mbed_official	610:813dcc80987e	2703	*/
mbed_official	610:813dcc80987e	2704	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
mbed_official	610:813dcc80987e	2705
mbed_official	610:813dcc80987e	2706	/**
mbed_official	610:813dcc80987e	2707	* @brief Macro to configures the External Low Speed oscillator (LSE) drive capability.
mbed_official	610:813dcc80987e	2708	* @note As the LSE is in the Backup domain and write access is denied to
mbed_official	610:813dcc80987e	2709	* this domain after reset, you have to enable write access using
mbed_official	610:813dcc80987e	2710	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
mbed_official	610:813dcc80987e	2711	* (to be done once after reset).
mbed_official	610:813dcc80987e	2712	* @param __LSEDRIVE__: specifies the new state of the LSE drive capability.
mbed_official	610:813dcc80987e	2713	* This parameter can be one of the following values:
mbed_official	610:813dcc80987e	2714	* @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
mbed_official	610:813dcc80987e	2715	* @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
mbed_official	610:813dcc80987e	2716	* @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
mbed_official	610:813dcc80987e	2717	* @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
mbed_official	610:813dcc80987e	2718	* @retval None
mbed_official	610:813dcc80987e	2719	*/
mbed_official	610:813dcc80987e	2720	#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
mbed_official	610:813dcc80987e	2721	MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__))
mbed_official	610:813dcc80987e	2722
mbed_official	610:813dcc80987e	2723	/**
mbed_official	610:813dcc80987e	2724	* @brief Macro to configures the wake up from stop clock.
mbed_official	610:813dcc80987e	2725	* @param __STOPWUCLK__: specifies the clock source used after wake up from stop.
mbed_official	610:813dcc80987e	2726	* This parameter can be one of the following values:
mbed_official	610:813dcc80987e	2727	* @arg RCC_STOP_WAKEUPCLOCK_MSI: MSI selected as system clock source
mbed_official	610:813dcc80987e	2728	* @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI selected as system clock source
mbed_official	610:813dcc80987e	2729	* @retval None
mbed_official	610:813dcc80987e	2730	*/
mbed_official	610:813dcc80987e	2731	#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \
mbed_official	610:813dcc80987e	2732	MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__))
mbed_official	610:813dcc80987e	2733
mbed_official	610:813dcc80987e	2734
mbed_official	610:813dcc80987e	2735	/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
mbed_official	610:813dcc80987e	2736	* @brief macros to manage the specified RCC Flags and interrupts.
mbed_official	610:813dcc80987e	2737	* @{
mbed_official	610:813dcc80987e	2738	*/
mbed_official	610:813dcc80987e	2739
mbed_official	610:813dcc80987e	2740	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
mbed_official	610:813dcc80987e	2741	* the selected interrupts).
mbed_official	610:813dcc80987e	2742	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
mbed_official	610:813dcc80987e	2743	* This parameter can be any combination of the following values:
mbed_official	610:813dcc80987e	2744	* @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official	610:813dcc80987e	2745	* @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official	610:813dcc80987e	2746	* @arg RCC_IT_MSIRDY: HSI ready interrupt
mbed_official	610:813dcc80987e	2747	* @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official	610:813dcc80987e	2748	* @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official	610:813dcc80987e	2749	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
mbed_official	610:813dcc80987e	2750	* @arg RCC_IT_PLLSAI1RDY: PLLSAI1 ready interrupt
mbed_official	610:813dcc80987e	2751	* @arg RCC_IT_PLLSAI2RDY: PLLSAI2 ready interrupt
mbed_official	610:813dcc80987e	2752	* @arg RCC_IT_LSECSS: Clock security system interrupt
mbed_official	610:813dcc80987e	2753	* @retval None
mbed_official	610:813dcc80987e	2754	*/
mbed_official	610:813dcc80987e	2755	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
mbed_official	610:813dcc80987e	2756
mbed_official	610:813dcc80987e	2757	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
mbed_official	610:813dcc80987e	2758	* the selected interrupts).
mbed_official	610:813dcc80987e	2759	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
mbed_official	610:813dcc80987e	2760	* This parameter can be any combination of the following values:
mbed_official	610:813dcc80987e	2761	* @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official	610:813dcc80987e	2762	* @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official	610:813dcc80987e	2763	* @arg RCC_IT_MSIRDY: HSI ready interrupt
mbed_official	610:813dcc80987e	2764	* @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official	610:813dcc80987e	2765	* @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official	610:813dcc80987e	2766	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
mbed_official	610:813dcc80987e	2767	* @arg RCC_IT_PLLSAI1RDY: PLLSAI1 ready interrupt
mbed_official	610:813dcc80987e	2768	* @arg RCC_IT_PLLSAI2RDY: PLLSAI2 ready interrupt
mbed_official	610:813dcc80987e	2769	* @arg RCC_IT_LSECSS: Clock security system interrupt
mbed_official	610:813dcc80987e	2770	* @retval None
mbed_official	610:813dcc80987e	2771	*/
mbed_official	610:813dcc80987e	2772	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
mbed_official	610:813dcc80987e	2773
mbed_official	610:813dcc80987e	2774	/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
mbed_official	610:813dcc80987e	2775	* bits to clear the selected interrupt pending bits.
mbed_official	610:813dcc80987e	2776	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
mbed_official	610:813dcc80987e	2777	* This parameter can be any combination of the following values:
mbed_official	610:813dcc80987e	2778	* @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official	610:813dcc80987e	2779	* @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official	610:813dcc80987e	2780	* @arg RCC_IT_MSIRDY: MSI ready interrupt
mbed_official	610:813dcc80987e	2781	* @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official	610:813dcc80987e	2782	* @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official	610:813dcc80987e	2783	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
mbed_official	610:813dcc80987e	2784	* @arg RCC_IT_PLLSAI1RDY: PLLSAI1 ready interrupt
mbed_official	610:813dcc80987e	2785	* @arg RCC_IT_PLLSAI2RDY: PLLSAI2 ready interrupt
mbed_official	610:813dcc80987e	2786	* @arg RCC_IT_HSECSS: HSE Clock Security interrupt
mbed_official	610:813dcc80987e	2787	* @arg RCC_IT_LSECSS: Clock security system interrupt
mbed_official	610:813dcc80987e	2788	* @retval None
mbed_official	610:813dcc80987e	2789	*/
mbed_official	610:813dcc80987e	2790	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
mbed_official	610:813dcc80987e	2791
mbed_official	610:813dcc80987e	2792	/** @brief Check whether the RCC interrupt has occurred or not.
mbed_official	610:813dcc80987e	2793	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
mbed_official	610:813dcc80987e	2794	* This parameter can be one of the following values:
mbed_official	610:813dcc80987e	2795	* @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official	610:813dcc80987e	2796	* @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official	610:813dcc80987e	2797	* @arg RCC_IT_MSIRDY: MSI ready interrupt
mbed_official	610:813dcc80987e	2798	* @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official	610:813dcc80987e	2799	* @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official	610:813dcc80987e	2800	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
mbed_official	610:813dcc80987e	2801	* @arg RCC_IT_PLLSAI1RDY: PLLSAI1 ready interrupt
mbed_official	610:813dcc80987e	2802	* @arg RCC_IT_PLLSAI2RDY: PLLSAI2 ready interrupt
mbed_official	610:813dcc80987e	2803	* @arg RCC_IT_HSECSS: HSE Clock Security interrupt
mbed_official	610:813dcc80987e	2804	* @arg RCC_IT_LSECSS: Clock security system interrupt
mbed_official	610:813dcc80987e	2805	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
mbed_official	610:813dcc80987e	2806	*/
mbed_official	610:813dcc80987e	2807	#define __HAL_RCC_GET_IT_SOURCE(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
mbed_official	610:813dcc80987e	2808
mbed_official	610:813dcc80987e	2809	/** @brief Set RMVF bit to clear the reset flags.
mbed_official	610:813dcc80987e	2810	* The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST,
mbed_official	610:813dcc80987e	2811	* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
mbed_official	610:813dcc80987e	2812	* @retval None
mbed_official	610:813dcc80987e	2813	*/
mbed_official	610:813dcc80987e	2814	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
mbed_official	610:813dcc80987e	2815
mbed_official	610:813dcc80987e	2816	/** @brief Check whether the selected RCC flag is set or not.
mbed_official	610:813dcc80987e	2817	* @param __FLAG__: specifies the flag to check.
mbed_official	610:813dcc80987e	2818	* This parameter can be one of the following values:
mbed_official	610:813dcc80987e	2819	* @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready
mbed_official	610:813dcc80987e	2820	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
mbed_official	610:813dcc80987e	2821	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
mbed_official	610:813dcc80987e	2822	* @arg RCC_FLAG_PLLRDY: main PLL clock ready
mbed_official	610:813dcc80987e	2823	* @arg RCC_FLAG_PLLSAI2RDY: PLLSAI2 clock ready
mbed_official	610:813dcc80987e	2824	* @arg RCC_FLAG_PLLSAI1RDY: PLLSAI1 clock ready
mbed_official	610:813dcc80987e	2825	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
mbed_official	610:813dcc80987e	2826	* @arg RCC_FLAG_LSECSSD: Clock security system failure on LSE oscillator detection
mbed_official	610:813dcc80987e	2827	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
mbed_official	610:813dcc80987e	2828	* @arg RCC_FLAG_BORRST: BOR reset
mbed_official	610:813dcc80987e	2829	* @arg RCC_FLAG_OBLRST: OBLRST reset
mbed_official	610:813dcc80987e	2830	* @arg RCC_FLAG_PINRST: Pin reset
mbed_official	610:813dcc80987e	2831	* @arg RCC_FLAG_FWRST: FIREWALL reset
mbed_official	610:813dcc80987e	2832	* @arg RCC_FLAG_RMVF: Remove reset Flag
mbed_official	610:813dcc80987e	2833	* @arg RCC_FLAG_SFTRST: Software reset
mbed_official	610:813dcc80987e	2834	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
mbed_official	610:813dcc80987e	2835	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset
mbed_official	610:813dcc80987e	2836	* @arg RCC_FLAG_LPWRRST: Low Power reset
mbed_official	610:813dcc80987e	2837	* @retval The new state of __FLAG__ (TRUE or FALSE).
mbed_official	610:813dcc80987e	2838	*/
mbed_official	610:813dcc80987e	2839	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \
mbed_official	610:813dcc80987e	2840	((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
mbed_official	610:813dcc80987e	2841	((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) & \
mbed_official	610:813dcc80987e	2842	((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != 0) \
mbed_official	610:813dcc80987e	2843	? 1 : 0)
mbed_official	610:813dcc80987e	2844
mbed_official	610:813dcc80987e	2845	/**
mbed_official	610:813dcc80987e	2846	* @}
mbed_official	610:813dcc80987e	2847	*/
mbed_official	610:813dcc80987e	2848
mbed_official	610:813dcc80987e	2849	/**
mbed_official	610:813dcc80987e	2850	* @}
mbed_official	610:813dcc80987e	2851	*/
mbed_official	610:813dcc80987e	2852
mbed_official	610:813dcc80987e	2853	/* Private constants ---------------------------------------------------------*/
mbed_official	610:813dcc80987e	2854	/** @defgroup RCC_Private_Constants RCC Private Constants
mbed_official	610:813dcc80987e	2855	* @{
mbed_official	610:813dcc80987e	2856	*/
mbed_official	610:813dcc80987e	2857	/* Defines used for Flags */
mbed_official	610:813dcc80987e	2858	#define CR_REG_INDEX ((uint8_t)1)
mbed_official	610:813dcc80987e	2859	#define BDCR_REG_INDEX ((uint8_t)2)
mbed_official	610:813dcc80987e	2860	#define CSR_REG_INDEX ((uint8_t)3)
mbed_official	610:813dcc80987e	2861
mbed_official	610:813dcc80987e	2862	#define RCC_FLAG_MASK ((uint8_t)0x1F)
mbed_official	610:813dcc80987e	2863	/**
mbed_official	610:813dcc80987e	2864	* @}
mbed_official	610:813dcc80987e	2865	*/
mbed_official	610:813dcc80987e	2866
mbed_official	610:813dcc80987e	2867	/* Private macros ------------------------------------------------------------*/
mbed_official	610:813dcc80987e	2868	/** @addtogroup RCC_Private_Macros
mbed_official	610:813dcc80987e	2869	* @{
mbed_official	610:813dcc80987e	2870	*/
mbed_official	610:813dcc80987e	2871
mbed_official	610:813dcc80987e	2872	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) \|\| \
mbed_official	610:813dcc80987e	2873	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
mbed_official	610:813dcc80987e	2874	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
mbed_official	610:813dcc80987e	2875	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) \|\| \
mbed_official	610:813dcc80987e	2876	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
mbed_official	610:813dcc80987e	2877	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
mbed_official	610:813dcc80987e	2878
mbed_official	610:813dcc80987e	2879	#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) \|\| ((__HSE__) == RCC_HSE_ON) \|\| \
mbed_official	610:813dcc80987e	2880	((__HSE__) == RCC_HSE_BYPASS))
mbed_official	610:813dcc80987e	2881
mbed_official	610:813dcc80987e	2882	#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) \|\| ((__LSE__) == RCC_LSE_ON) \|\| \
mbed_official	610:813dcc80987e	2883	((__LSE__) == RCC_LSE_BYPASS))
mbed_official	610:813dcc80987e	2884
mbed_official	610:813dcc80987e	2885	#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON))
mbed_official	610:813dcc80987e	2886
mbed_official	610:813dcc80987e	2887	#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)31)
mbed_official	610:813dcc80987e	2888
mbed_official	610:813dcc80987e	2889	#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) \|\| ((__LSI__) == RCC_LSI_ON))
mbed_official	610:813dcc80987e	2890
mbed_official	610:813dcc80987e	2891	#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) \|\| ((__MSI__) == RCC_MSI_ON))
mbed_official	610:813dcc80987e	2892
mbed_official	610:813dcc80987e	2893	#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)255)
mbed_official	610:813dcc80987e	2894
mbed_official	610:813dcc80987e	2895	#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) \|\|((__PLL__) == RCC_PLL_OFF) \|\| \
mbed_official	610:813dcc80987e	2896	((__PLL__) == RCC_PLL_ON))
mbed_official	610:813dcc80987e	2897
mbed_official	610:813dcc80987e	2898	#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) \|\| \
mbed_official	610:813dcc80987e	2899	((__SOURCE__) == RCC_PLLSOURCE_MSI) \|\| \
mbed_official	610:813dcc80987e	2900	((__SOURCE__) == RCC_PLLSOURCE_HSI) \|\| \
mbed_official	610:813dcc80987e	2901	((__SOURCE__) == RCC_PLLSOURCE_HSE))
mbed_official	610:813dcc80987e	2902
mbed_official	610:813dcc80987e	2903	#define IS_RCC_PLLM_VALUE(__VALUE__) ((__VALUE__) <= 8)
mbed_official	610:813dcc80987e	2904
mbed_official	610:813dcc80987e	2905	#define IS_RCC_PLLN_VALUE(__VALUE__) ((8 <= (__VALUE__)) && ((__VALUE__) <= 86))
mbed_official	610:813dcc80987e	2906
mbed_official	610:813dcc80987e	2907	#define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) == 7) \|\| ((__VALUE__) == 17) )
mbed_official	610:813dcc80987e	2908
mbed_official	610:813dcc80987e	2909	#define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2 ) \|\| ((__VALUE__) == 4) \|\| \
mbed_official	610:813dcc80987e	2910	((__VALUE__) == 6) \|\| ((__VALUE__) == 8))
mbed_official	610:813dcc80987e	2911
mbed_official	610:813dcc80987e	2912	#define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2 ) \|\| ((__VALUE__) == 4) \|\| \
mbed_official	610:813dcc80987e	2913	((__VALUE__) == 6) \|\| ((__VALUE__) == 8))
mbed_official	610:813dcc80987e	2914
mbed_official	610:813dcc80987e	2915	#define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) \|\| \
mbed_official	610:813dcc80987e	2916	(((__VALUE__) & RCC_PLLSAI1_48M2CLK) == RCC_PLLSAI1_48M2CLK) \|\| \
mbed_official	610:813dcc80987e	2917	(((__VALUE__) & RCC_PLLSAI1_ADC1CLK) == RCC_PLLSAI1_ADC1CLK)) && \
mbed_official	610:813dcc80987e	2918	(((__VALUE__) & ~(RCC_PLLSAI1_SAI1CLK\|RCC_PLLSAI1_48M2CLK\|RCC_PLLSAI1_ADC1CLK)) == 0))
mbed_official	610:813dcc80987e	2919
mbed_official	610:813dcc80987e	2920	#define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK ) \|\| \
mbed_official	610:813dcc80987e	2921	(((__VALUE__) & RCC_PLLSAI2_ADC2CLK) == RCC_PLLSAI2_ADC2CLK)) && \
mbed_official	610:813dcc80987e	2922	(((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK\|RCC_PLLSAI2_ADC2CLK)) == 0))
mbed_official	610:813dcc80987e	2923
mbed_official	610:813dcc80987e	2924	#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) \|\| \
mbed_official	610:813dcc80987e	2925	((__RANGE__) == RCC_MSIRANGE_1) \|\| \
mbed_official	610:813dcc80987e	2926	((__RANGE__) == RCC_MSIRANGE_2) \|\| \
mbed_official	610:813dcc80987e	2927	((__RANGE__) == RCC_MSIRANGE_3) \|\| \
mbed_official	610:813dcc80987e	2928	((__RANGE__) == RCC_MSIRANGE_4) \|\| \
mbed_official	610:813dcc80987e	2929	((__RANGE__) == RCC_MSIRANGE_5) \|\| \
mbed_official	610:813dcc80987e	2930	((__RANGE__) == RCC_MSIRANGE_6) \|\| \
mbed_official	610:813dcc80987e	2931	((__RANGE__) == RCC_MSIRANGE_7) \|\| \
mbed_official	610:813dcc80987e	2932	((__RANGE__) == RCC_MSIRANGE_8) \|\| \
mbed_official	610:813dcc80987e	2933	((__RANGE__) == RCC_MSIRANGE_9) \|\| \
mbed_official	610:813dcc80987e	2934	((__RANGE__) == RCC_MSIRANGE_10) \|\| \
mbed_official	610:813dcc80987e	2935	((__RANGE__) == RCC_MSIRANGE_11))
mbed_official	610:813dcc80987e	2936
mbed_official	610:813dcc80987e	2937	#define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4) \|\| \
mbed_official	610:813dcc80987e	2938	((__RANGE__) == RCC_MSIRANGE_5) \|\| \
mbed_official	610:813dcc80987e	2939	((__RANGE__) == RCC_MSIRANGE_6) \|\| \
mbed_official	610:813dcc80987e	2940	((__RANGE__) == RCC_MSIRANGE_7))
mbed_official	610:813dcc80987e	2941
mbed_official	610:813dcc80987e	2942	#define IS_RCC_CLOCKTYPE(__CLK__) ((1 <= (__CLK__)) && ((__CLK__) <= 15))
mbed_official	610:813dcc80987e	2943
mbed_official	610:813dcc80987e	2944	#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) \|\| \
mbed_official	610:813dcc80987e	2945	((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) \|\| \
mbed_official	610:813dcc80987e	2946	((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) \|\| \
mbed_official	610:813dcc80987e	2947	((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
mbed_official	610:813dcc80987e	2948
mbed_official	610:813dcc80987e	2949	#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|\| \
mbed_official	610:813dcc80987e	2950	((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \
mbed_official	610:813dcc80987e	2951	((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \
mbed_official	610:813dcc80987e	2952	((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \
mbed_official	610:813dcc80987e	2953	((__HCLK__) == RCC_SYSCLK_DIV512))
mbed_official	610:813dcc80987e	2954
mbed_official	610:813dcc80987e	2955	#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) \|\| ((__PCLK__) == RCC_HCLK_DIV2) \|\| \
mbed_official	610:813dcc80987e	2956	((__PCLK__) == RCC_HCLK_DIV4) \|\| ((__PCLK__) == RCC_HCLK_DIV8) \|\| \
mbed_official	610:813dcc80987e	2957	((__PCLK__) == RCC_HCLK_DIV16))
mbed_official	610:813dcc80987e	2958
mbed_official	610:813dcc80987e	2959	#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) \|\| \
mbed_official	610:813dcc80987e	2960	((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) \|\| \
mbed_official	610:813dcc80987e	2961	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
mbed_official	610:813dcc80987e	2962
mbed_official	610:813dcc80987e	2963	#define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1)
mbed_official	610:813dcc80987e	2964
mbed_official	610:813dcc80987e	2965	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| \
mbed_official	610:813dcc80987e	2966	((__SOURCE__) == RCC_MCO1SOURCE_MSI) \|\| \
mbed_official	610:813dcc80987e	2967	((__SOURCE__) == RCC_MCO1SOURCE_HSI) \|\| \
mbed_official	610:813dcc80987e	2968	((__SOURCE__) == RCC_MCO1SOURCE_HSE) \|\| \
mbed_official	610:813dcc80987e	2969	((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \|\| \
mbed_official	610:813dcc80987e	2970	((__SOURCE__) == RCC_MCO1SOURCE_LSI) \|\| \
mbed_official	610:813dcc80987e	2971	((__SOURCE__) == RCC_MCO1SOURCE_LSE))
mbed_official	610:813dcc80987e	2972
mbed_official	610:813dcc80987e	2973	#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) \|\| ((__DIV__) == RCC_MCODIV_2) \|\| \
mbed_official	610:813dcc80987e	2974	((__DIV__) == RCC_MCODIV_4) \|\| ((__DIV__) == RCC_MCODIV_8) \|\| \
mbed_official	610:813dcc80987e	2975	((__DIV__) == RCC_MCODIV_16))
mbed_official	610:813dcc80987e	2976
mbed_official	610:813dcc80987e	2977	#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) \|\| \
mbed_official	610:813dcc80987e	2978	((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) \|\| \
mbed_official	610:813dcc80987e	2979	((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) \|\| \
mbed_official	610:813dcc80987e	2980	((__DRIVE__) == RCC_LSEDRIVE_HIGH))
mbed_official	610:813dcc80987e	2981
mbed_official	610:813dcc80987e	2982	#define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) \|\| \
mbed_official	610:813dcc80987e	2983	((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI))
mbed_official	610:813dcc80987e	2984	/**
mbed_official	610:813dcc80987e	2985	* @}
mbed_official	610:813dcc80987e	2986	*/
mbed_official	610:813dcc80987e	2987
mbed_official	610:813dcc80987e	2988	/* Include RCC HAL Extended module */
mbed_official	610:813dcc80987e	2989	#include "stm32l4xx_hal_rcc_ex.h"
mbed_official	610:813dcc80987e	2990
mbed_official	610:813dcc80987e	2991	/* Exported functions --------------------------------------------------------*/
mbed_official	610:813dcc80987e	2992	/** @addtogroup RCC_Exported_Functions
mbed_official	610:813dcc80987e	2993	* @{
mbed_official	610:813dcc80987e	2994	*/
mbed_official	610:813dcc80987e	2995
mbed_official	610:813dcc80987e	2996
mbed_official	610:813dcc80987e	2997	/** @addtogroup RCC_Exported_Functions_Group1
mbed_official	610:813dcc80987e	2998	* @{
mbed_official	610:813dcc80987e	2999	*/
mbed_official	610:813dcc80987e	3000
mbed_official	610:813dcc80987e	3001	/* Initialization and de-initialization functions ******************************/
mbed_official	610:813dcc80987e	3002	void HAL_RCC_DeInit(void);
mbed_official	610:813dcc80987e	3003	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
mbed_official	610:813dcc80987e	3004	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
mbed_official	610:813dcc80987e	3005
mbed_official	610:813dcc80987e	3006	/**
mbed_official	610:813dcc80987e	3007	* @}
mbed_official	610:813dcc80987e	3008	*/
mbed_official	610:813dcc80987e	3009
mbed_official	610:813dcc80987e	3010	/** @addtogroup RCC_Exported_Functions_Group2
mbed_official	610:813dcc80987e	3011	* @{
mbed_official	610:813dcc80987e	3012	*/
mbed_official	610:813dcc80987e	3013
mbed_official	610:813dcc80987e	3014	/* Peripheral Control functions ************************************************/
mbed_official	610:813dcc80987e	3015	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
mbed_official	610:813dcc80987e	3016	void HAL_RCC_EnableCSS(void);
mbed_official	610:813dcc80987e	3017	uint32_t HAL_RCC_GetSysClockFreq(void);
mbed_official	610:813dcc80987e	3018	uint32_t HAL_RCC_GetHCLKFreq(void);
mbed_official	610:813dcc80987e	3019	uint32_t HAL_RCC_GetPCLK1Freq(void);
mbed_official	610:813dcc80987e	3020	uint32_t HAL_RCC_GetPCLK2Freq(void);
mbed_official	610:813dcc80987e	3021	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
mbed_official	610:813dcc80987e	3022	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
mbed_official	610:813dcc80987e	3023	/* CSS NMI IRQ handler */
mbed_official	610:813dcc80987e	3024	void HAL_RCC_NMI_IRQHandler(void);
mbed_official	610:813dcc80987e	3025	/* User Callbacks in non blocking mode (IT mode) */
mbed_official	610:813dcc80987e	3026	void HAL_RCC_CSSCallback(void);
mbed_official	610:813dcc80987e	3027
mbed_official	610:813dcc80987e	3028	/**
mbed_official	610:813dcc80987e	3029	* @}
mbed_official	610:813dcc80987e	3030	*/
mbed_official	610:813dcc80987e	3031
mbed_official	610:813dcc80987e	3032	/**
mbed_official	610:813dcc80987e	3033	* @}
mbed_official	610:813dcc80987e	3034	*/
mbed_official	610:813dcc80987e	3035
mbed_official	610:813dcc80987e	3036	/**
mbed_official	610:813dcc80987e	3037	* @}
mbed_official	610:813dcc80987e	3038	*/
mbed_official	610:813dcc80987e	3039
mbed_official	610:813dcc80987e	3040	/**
mbed_official	610:813dcc80987e	3041	* @}
mbed_official	610:813dcc80987e	3042	*/
mbed_official	610:813dcc80987e	3043
mbed_official	610:813dcc80987e	3044	#ifdef __cplusplus
mbed_official	610:813dcc80987e	3045	}
mbed_official	610:813dcc80987e	3046	#endif
mbed_official	610:813dcc80987e	3047
mbed_official	610:813dcc80987e	3048	#endif /* __STM32L4xx_HAL_RCC_H */
mbed_official	610:813dcc80987e	3049
mbed_official	610:813dcc80987e	3050	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	26 Nov 2015
Imports:	17
Forks:	0
Commits:	638
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_rcc.h@610:813dcc80987e, 2015-08-14 (annotated)

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