scmRTOS_test - Quick and dirty port of scmRTOS demo to mbed 1768…

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Igor Skochinsky / Mbed 2 deprecated scmRTOS_test

Quick and dirty port of scmRTOS demo to mbed 1768. scmRTOS is a small RTOS written using C++. Offers (static) processes, critical sections, mutexes, messages, channels.

Dependencies: mbed

scmRTOS/CortexM3/OS_Target.h@0:a405220cf420, 2010-09-09 (annotated)

Committer:: igorsk
Date:: Thu Sep 09 21:19:01 2010 +0000
Revision:: 0:a405220cf420

Who changed what in which revision?

User	Revision	Line number	New contents of line
igorsk	0:a405220cf420	1	//******************************************************************************
igorsk	0:a405220cf420	2	//*
igorsk	0:a405220cf420	3	//* FULLNAME: Single-Chip Microcontroller Real-Time Operating System
igorsk	0:a405220cf420	4	//*
igorsk	0:a405220cf420	5	//* NICKNAME: scmRTOS
igorsk	0:a405220cf420	6	//*
igorsk	0:a405220cf420	7	//* PROCESSOR: ARM Cortex-M3
igorsk	0:a405220cf420	8	//*
igorsk	0:a405220cf420	9	//* TOOLKIT: RVCT (ARM)
igorsk	0:a405220cf420	10	//*
igorsk	0:a405220cf420	11	//* PURPOSE: Target Dependent Stuff Header. Declarations And Definitions
igorsk	0:a405220cf420	12	//*
igorsk	0:a405220cf420	13	//* Version: 3.10
igorsk	0:a405220cf420	14	//*
igorsk	0:a405220cf420	15	//* $Revision: 195 $
igorsk	0:a405220cf420	16	//* $Date:: 2008-06-19 #$
igorsk	0:a405220cf420	17	//*
igorsk	0:a405220cf420	18	//* Copyright (c) 2003-2010, Harry E. Zhurov
igorsk	0:a405220cf420	19	//*
igorsk	0:a405220cf420	20	//* Permission is hereby granted, free of charge, to any person
igorsk	0:a405220cf420	21	//* obtaining a copy of this software and associated documentation
igorsk	0:a405220cf420	22	//* files (the "Software"), to deal in the Software without restriction,
igorsk	0:a405220cf420	23	//* including without limitation the rights to use, copy, modify, merge,
igorsk	0:a405220cf420	24	//* publish, distribute, sublicense, and/or sell copies of the Software,
igorsk	0:a405220cf420	25	//* and to permit persons to whom the Software is furnished to do so,
igorsk	0:a405220cf420	26	//* subject to the following conditions:
igorsk	0:a405220cf420	27	//*
igorsk	0:a405220cf420	28	//* The above copyright notice and this permission notice shall be included
igorsk	0:a405220cf420	29	//* in all copies or substantial portions of the Software.
igorsk	0:a405220cf420	30	//*
igorsk	0:a405220cf420	31	//* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
igorsk	0:a405220cf420	32	//* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
igorsk	0:a405220cf420	33	//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
igorsk	0:a405220cf420	34	//* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
igorsk	0:a405220cf420	35	//* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
igorsk	0:a405220cf420	36	//* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH
igorsk	0:a405220cf420	37	//* THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
igorsk	0:a405220cf420	38	//*
igorsk	0:a405220cf420	39	//* =================================================================
igorsk	0:a405220cf420	40	//* See http://scmrtos.sourceforge.net for documentation, latest
igorsk	0:a405220cf420	41	//* information, license and contact details.
igorsk	0:a405220cf420	42	//* =================================================================
igorsk	0:a405220cf420	43	//*
igorsk	0:a405220cf420	44	//******************************************************************************
igorsk	0:a405220cf420	45	//* Ported by Andrey Chuikin, Copyright (c) 2008-2010
igorsk	0:a405220cf420	46
igorsk	0:a405220cf420	47	#ifndef scmRTOS_CORTEXM3_H
igorsk	0:a405220cf420	48	#define scmRTOS_CORTEXM3_H
igorsk	0:a405220cf420	49
igorsk	0:a405220cf420	50	#include <commdefs.h>
igorsk	0:a405220cf420	51
igorsk	0:a405220cf420	52	//------------------------------------------------------------------------------
igorsk	0:a405220cf420	53	//
igorsk	0:a405220cf420	54	// Compiler and Target checks
igorsk	0:a405220cf420	55	//
igorsk	0:a405220cf420	56	//
igorsk	0:a405220cf420	57	#ifndef __ARMCC_VERSION
igorsk	0:a405220cf420	58	#error "This file should only be compiled with ARM RVCT Compiler"
igorsk	0:a405220cf420	59	#endif // __ARMCC_VERSION
igorsk	0:a405220cf420	60
igorsk	0:a405220cf420	61	#if __TARGET_ARCH_ARM != 0 \|\| __TARGET_ARCH_THUMB != 4
igorsk	0:a405220cf420	62	#error "This file must be compiled for ARMv7-M (Cortex-M3) processor only."
igorsk	0:a405220cf420	63	#endif
igorsk	0:a405220cf420	64
igorsk	0:a405220cf420	65	//------------------------------------------------------------------------------
igorsk	0:a405220cf420	66	//
igorsk	0:a405220cf420	67	// Target specific types
igorsk	0:a405220cf420	68	//
igorsk	0:a405220cf420	69	//
igorsk	0:a405220cf420	70	typedef dword TStackItem;
igorsk	0:a405220cf420	71	typedef dword TStatusReg;
igorsk	0:a405220cf420	72
igorsk	0:a405220cf420	73	//-----------------------------------------------------------------------------
igorsk	0:a405220cf420	74	//
igorsk	0:a405220cf420	75	// Configuration macros
igorsk	0:a405220cf420	76	//
igorsk	0:a405220cf420	77	//
igorsk	0:a405220cf420	78	#define OS_PROCESS __attribute__((__noreturn__))
igorsk	0:a405220cf420	79	#define OS_INTERRUPT
igorsk	0:a405220cf420	80	#define DUMMY_INSTR() __NOP()
igorsk	0:a405220cf420	81	#define INLINE_PROCESS_CTOR INLINE inline
igorsk	0:a405220cf420	82
igorsk	0:a405220cf420	83	//-----------------------------------------------------------------------------
igorsk	0:a405220cf420	84	//
igorsk	0:a405220cf420	85	// Uncomment macro value below for SystemTimer() run in critical section
igorsk	0:a405220cf420	86	//
igorsk	0:a405220cf420	87	// This is useful (and necessary) when target processor has hardware
igorsk	0:a405220cf420	88	// enabled nested interrups. Cortex-M3 have such interrupts.
igorsk	0:a405220cf420	89	//
igorsk	0:a405220cf420	90	#define SYS_TIMER_CRIT_SECT() TCritSect cs
igorsk	0:a405220cf420	91
igorsk	0:a405220cf420	92	//-----------------------------------------------------------------------------
igorsk	0:a405220cf420	93	// Separate return stack not required
igorsk	0:a405220cf420	94	#define SEPARATE_RETURN_STACK 0
igorsk	0:a405220cf420	95
igorsk	0:a405220cf420	96	//-----------------------------------------------------------------------------
igorsk	0:a405220cf420	97	// Software interrupt stack switching not supported in Cortex-M3 port
igorsk	0:a405220cf420	98	// because processor implements hardware stack switching.
igorsk	0:a405220cf420	99	// So, system timer isr wrapper can't be choosen at project level
igorsk	0:a405220cf420	100	//
igorsk	0:a405220cf420	101	#define scmRTOS_ISRW_TYPE TISRW
igorsk	0:a405220cf420	102
igorsk	0:a405220cf420	103	//-----------------------------------------------------------------------------
igorsk	0:a405220cf420	104	//
igorsk	0:a405220cf420	105	// scmRTOS Context Switch Scheme
igorsk	0:a405220cf420	106	//
igorsk	0:a405220cf420	107	// The macro defines a context switch manner. Value 0 sets direct context
igorsk	0:a405220cf420	108	// switch in the scheduler and in the OS ISRs. This is the primary method.
igorsk	0:a405220cf420	109	// Value 1 sets the second way to switch context - by using of software
igorsk	0:a405220cf420	110	// interrupt. See documentation fo details.
igorsk	0:a405220cf420	111	// Cortex-M3 port supports software interrupt switch method only.
igorsk	0:a405220cf420	112	//
igorsk	0:a405220cf420	113	#define scmRTOS_CONTEXT_SWITCH_SCHEME 1
igorsk	0:a405220cf420	114
igorsk	0:a405220cf420	115	//-----------------------------------------------------------------------------
igorsk	0:a405220cf420	116	//
igorsk	0:a405220cf420	117	// Include project-level configurations
igorsk	0:a405220cf420	118	// !!! The order of includes is important !!!
igorsk	0:a405220cf420	119	//
igorsk	0:a405220cf420	120	#include "../../scmRTOS_config.h"
igorsk	0:a405220cf420	121	#include "../scmRTOS_TARGET_CFG.h"
igorsk	0:a405220cf420	122	#include <scmRTOS_defs.h>
igorsk	0:a405220cf420	123	#include <LPC17xx.h>
igorsk	0:a405220cf420	124
igorsk	0:a405220cf420	125	//-----------------------------------------------------------------------------
igorsk	0:a405220cf420	126	//
igorsk	0:a405220cf420	127	// The Critital Section Wrapper
igorsk	0:a405220cf420	128	//
igorsk	0:a405220cf420	129	//
igorsk	0:a405220cf420	130	#define __enable_interrupt() __enable_irq()
igorsk	0:a405220cf420	131	#define __disable_interrupt() __disable_irq()
igorsk	0:a405220cf420	132
igorsk	0:a405220cf420	133	#define __set_interrupt_state(status) __set_PRIMASK(status)
igorsk	0:a405220cf420	134	#define __get_interrupt_state() __get_PRIMASK()
igorsk	0:a405220cf420	135
igorsk	0:a405220cf420	136	class TCritSect
igorsk	0:a405220cf420	137	{
igorsk	0:a405220cf420	138	public:
igorsk	0:a405220cf420	139	TCritSect () : StatusReg(__get_interrupt_state()) { __disable_interrupt(); }
igorsk	0:a405220cf420	140	~TCritSect() { __set_interrupt_state(StatusReg); }
igorsk	0:a405220cf420	141
igorsk	0:a405220cf420	142	private:
igorsk	0:a405220cf420	143	TStatusReg StatusReg;
igorsk	0:a405220cf420	144	};
igorsk	0:a405220cf420	145	//-----------------------------------------------------------------------------
igorsk	0:a405220cf420	146
igorsk	0:a405220cf420	147	//-----------------------------------------------------------------------------
igorsk	0:a405220cf420	148	//
igorsk	0:a405220cf420	149	// Priority stuff
igorsk	0:a405220cf420	150	//
igorsk	0:a405220cf420	151	//
igorsk	0:a405220cf420	152	namespace OS
igorsk	0:a405220cf420	153	{
igorsk	0:a405220cf420	154	INLINE inline OS::TProcessMap GetPrioTag(const byte pr) { return static_cast<OS::TProcessMap> (1 << pr); }
igorsk	0:a405220cf420	155
igorsk	0:a405220cf420	156	#if scmRTOS_PRIORITY_ORDER == 0
igorsk	0:a405220cf420	157	INLINE inline byte GetHighPriority(TProcessMap pm)
igorsk	0:a405220cf420	158	{
igorsk	0:a405220cf420	159	byte pr = 0;
igorsk	0:a405220cf420	160
igorsk	0:a405220cf420	161	while( !(pm & 0x0001) )
igorsk	0:a405220cf420	162	{
igorsk	0:a405220cf420	163	pr++;
igorsk	0:a405220cf420	164	pm >>= 1;
igorsk	0:a405220cf420	165	}
igorsk	0:a405220cf420	166	return pr;
igorsk	0:a405220cf420	167	}
igorsk	0:a405220cf420	168	#else
igorsk	0:a405220cf420	169	INLINE inline byte GetHighPriority(TProcessMap pm) { return (31 - __clz(pm)); }
igorsk	0:a405220cf420	170	#endif // scmRTOS_PRIORITY_ORDER
igorsk	0:a405220cf420	171	}
igorsk	0:a405220cf420	172
igorsk	0:a405220cf420	173	//-----------------------------------------------------------------------------
igorsk	0:a405220cf420	174	//
igorsk	0:a405220cf420	175	// Interrupt and Interrupt Service Routines support
igorsk	0:a405220cf420	176	//
igorsk	0:a405220cf420	177	INLINE inline TStatusReg GetInterruptState( ) { return __get_interrupt_state(); }
igorsk	0:a405220cf420	178	INLINE inline void SetInterruptState(TStatusReg sr) { __set_interrupt_state(sr); }
igorsk	0:a405220cf420	179
igorsk	0:a405220cf420	180	INLINE inline void EnableInterrupts() { __enable_interrupt(); }
igorsk	0:a405220cf420	181	INLINE inline void DisableInterrupts() { __disable_interrupt(); }
igorsk	0:a405220cf420	182
igorsk	0:a405220cf420	183
igorsk	0:a405220cf420	184	namespace OS
igorsk	0:a405220cf420	185	{
igorsk	0:a405220cf420	186	INLINE inline void EnableContextSwitch() { EnableInterrupts(); }
igorsk	0:a405220cf420	187	INLINE inline void DisableContextSwitch() { DisableInterrupts(); }
igorsk	0:a405220cf420	188	}
igorsk	0:a405220cf420	189
igorsk	0:a405220cf420	190	#include <OS_Kernel.h>
igorsk	0:a405220cf420	191
igorsk	0:a405220cf420	192	namespace OS
igorsk	0:a405220cf420	193	{
igorsk	0:a405220cf420	194	//--------------------------------------------------------------------------
igorsk	0:a405220cf420	195	//
igorsk	0:a405220cf420	196	// NAME : OS ISR support
igorsk	0:a405220cf420	197	//
igorsk	0:a405220cf420	198	// PURPOSE : Implements common actions on interrupt enter and exit
igorsk	0:a405220cf420	199	// under the OS
igorsk	0:a405220cf420	200	//
igorsk	0:a405220cf420	201	// DESCRIPTION:
igorsk	0:a405220cf420	202	//
igorsk	0:a405220cf420	203	//
igorsk	0:a405220cf420	204	class TISRW
igorsk	0:a405220cf420	205	{
igorsk	0:a405220cf420	206	public:
igorsk	0:a405220cf420	207	INLINE TISRW() { ISR_Enter(); }
igorsk	0:a405220cf420	208	INLINE ~TISRW() { ISR_Exit(); }
igorsk	0:a405220cf420	209
igorsk	0:a405220cf420	210	private:
igorsk	0:a405220cf420	211	//-----------------------------------------------------
igorsk	0:a405220cf420	212	INLINE void ISR_Enter()
igorsk	0:a405220cf420	213	{
igorsk	0:a405220cf420	214	TCritSect cs;
igorsk	0:a405220cf420	215	Kernel.ISR_NestCount++;
igorsk	0:a405220cf420	216	}
igorsk	0:a405220cf420	217	//-----------------------------------------------------
igorsk	0:a405220cf420	218	INLINE void ISR_Exit()
igorsk	0:a405220cf420	219	{
igorsk	0:a405220cf420	220	TCritSect cs;
igorsk	0:a405220cf420	221	if(--Kernel.ISR_NestCount) return;
igorsk	0:a405220cf420	222	Kernel.SchedISR();
igorsk	0:a405220cf420	223	}
igorsk	0:a405220cf420	224	//-----------------------------------------------------
igorsk	0:a405220cf420	225	};
igorsk	0:a405220cf420	226
igorsk	0:a405220cf420	227	// No software interrupt stack switching provided,
igorsk	0:a405220cf420	228	// TISRW_SS declared to be the same as TISRW for porting compability
igorsk	0:a405220cf420	229	#define TISRW_SS TISRW
igorsk	0:a405220cf420	230
igorsk	0:a405220cf420	231	} // ns OS
igorsk	0:a405220cf420	232	//-----------------------------------------------------------------------------
igorsk	0:a405220cf420	233
igorsk	0:a405220cf420	234	#endif // scmRTOS_CORTEXM3_H
igorsk	0:a405220cf420	235	//-----------------------------------------------------------------------------
igorsk	0:a405220cf420	236

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	09 Sep 2010
Imports:	69
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	4

scmRTOS/CortexM3/OS_Target.h@0:a405220cf420, 2010-09-09 (annotated)

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