lpc17xx_ssp.h

00001 /***********************************************************************//**
00002  * @file    : lpc17xx_ssp.h
00003  * @brief    : Contains all macro definitions and function prototypes
00004  *                 support for SSP firmware library on LPC17xx
00005  * @version    : 1.0
00006  * @date    : 9. April. 2009
00007  * @author    : HieuNguyen
00008  **************************************************************************
00009  * Software that is described herein is for illustrative purposes only
00010  * which provides customers with programming information regarding the
00011  * products. This software is supplied "AS IS" without any warranties.
00012  * NXP Semiconductors assumes no responsibility or liability for the
00013  * use of the software, conveys no license or title under any patent,
00014  * copyright, or mask work right to the product. NXP Semiconductors
00015  * reserves the right to make changes in the software without
00016  * notification. NXP Semiconductors also make no representation or
00017  * warranty that such application will be suitable for the specified
00018  * use without further testing or modification.
00019  **************************************************************************/
00020 
00021 /* Peripheral group ----------------------------------------------------------- */
00022 /** @defgroup SSP
00023  * @ingroup LPC1700CMSIS_FwLib_Drivers
00024  * @{
00025  */
00026 
00027 #ifndef LPC17XX_SSP_H_
00028 #define LPC17XX_SSP_H_
00029 
00030 /* Includes ------------------------------------------------------------------- */
00031 #include "cmsis.h"
00032 #include "lpc_types.h"
00033 
00034 
00035 #ifdef __cplusplus
00036 extern "C"
00037 {
00038 #endif
00039 
00040 
00041 /* Private Macros ------------------------------------------------------------- */
00042 /** @defgroup SSP_Private_Macros
00043  * @{
00044  */
00045 
00046 /*********************************************************************//**
00047  * Macro defines for CR0 register
00048  **********************************************************************/
00049 
00050 /** @defgroup SSP_REGISTER_BIT_DEFINITION
00051  * @{
00052  */
00053 
00054 /** SSP data size select, must be 4 bits to 16 bits */
00055 #define SSP_CR0_DSS(n)           ((uint32_t)((n-1)&0xF))
00056 /** SSP control 0 Motorola SPI mode */
00057 #define SSP_CR0_FRF_SPI          ((uint32_t)(0<<4))
00058 /** SSP control 0 TI synchronous serial mode */
00059 #define SSP_CR0_FRF_TI           ((uint32_t)(1<<4))
00060 /** SSP control 0 National Micro-wire mode */
00061 #define SSP_CR0_FRF_MICROWIRE      ((uint32_t)(2<<4))
00062 /** SPI clock polarity bit (used in SPI mode only), (1) = maintains the
00063    bus clock high between frames, (0) = low */
00064 #define SSP_CR0_CPOL_HI        ((uint32_t)(1<<6))
00065 /** SPI clock out phase bit (used in SPI mode only), (1) = captures data
00066    on the second clock transition of the frame, (0) = first */
00067 #define SSP_CR0_CPHA_SECOND    ((uint32_t)(1<<7))
00068 /** SSP serial clock rate value load macro, divider rate is
00069    PERIPH_CLK / (cpsr * (SCR + 1)) */
00070 #define SSP_CR0_SCR(n)       ((uint32_t)((n&0xFF)<<8))
00071 /** SSP CR0 bit mask */
00072 #define SSP_CR0_BITMASK        ((uint32_t)(0xFFFF))
00073 
00074 
00075 /*********************************************************************//**
00076  * Macro defines for CR1 register
00077  **********************************************************************/
00078 /** SSP control 1 loopback mode enable bit */
00079 #define SSP_CR1_LBM_EN        ((uint32_t)(1<<0))
00080 /** SSP control 1 enable bit */
00081 #define SSP_CR1_SSP_EN        ((uint32_t)(1<<1))
00082 /** SSP control 1 slave enable */
00083 #define SSP_CR1_SLAVE_EN    ((uint32_t)(1<<2))
00084 /** SSP control 1 slave out disable bit, disables transmit line in slave
00085    mode */
00086 #define SSP_CR1_SO_DISABLE    ((uint32_t)(1<<3))
00087 /** SSP CR1 bit mask */
00088 #define SSP_CR1_BITMASK        ((uint32_t)(0x0F))
00089 
00090 
00091 /*********************************************************************//**
00092  * Macro defines for DR register
00093  **********************************************************************/
00094 /** SSP data bit mask */
00095 #define SSP_DR_BITMASK(n)   ((n)&0xFFFF)
00096 
00097 /*********************************************************************//**
00098  * Macro defines for SR register
00099  **********************************************************************/
00100 /** SSP status TX FIFO Empty bit */
00101 #define SSP_SR_TFE      ((uint32_t)(1<<0))
00102 /** SSP status TX FIFO not full bit */
00103 #define SSP_SR_TNF      ((uint32_t)(1<<1))
00104 /** SSP status RX FIFO not empty bit */
00105 #define SSP_SR_RNE      ((uint32_t)(1<<2))
00106 /** SSP status RX FIFO full bit */
00107 #define SSP_SR_RFF      ((uint32_t)(1<<3))
00108 /** SSP status SSP Busy bit */
00109 #define SSP_SR_BSY      ((uint32_t)(1<<4))
00110 /** SSP SR bit mask */
00111 #define SSP_SR_BITMASK    ((uint32_t)(0x1F))
00112 
00113 
00114 /*********************************************************************//**
00115  * Macro defines for CPSR register
00116  **********************************************************************/
00117 /** SSP clock prescaler */
00118 #define SSP_CPSR_CPDVSR(n)     ((uint32_t)(n&0xFF))
00119 /** SSP CPSR bit mask */
00120 #define SSP_CPSR_BITMASK    ((uint32_t)(0xFF))
00121 
00122 
00123 /*********************************************************************//**
00124  * Macro define for (IMSC) Interrupt Mask Set/Clear registers
00125  **********************************************************************/
00126 /** Receive Overrun */
00127 #define SSP_IMSC_ROR    ((uint32_t)(1<<0))
00128 /** Receive TimeOut */
00129 #define SSP_IMSC_RT        ((uint32_t)(1<<1))
00130 /** Rx FIFO is at least half full */
00131 #define SSP_IMSC_RX        ((uint32_t)(1<<2))
00132 /** Tx FIFO is at least half empty */
00133 #define SSP_IMSC_TX        ((uint32_t)(1<<3))
00134 /** IMSC bit mask */
00135 #define SSP_IMSC_BITMASK    ((uint32_t)(0x0F))
00136 
00137 /*********************************************************************//**
00138  * Macro define for (RIS) Raw Interrupt Status registers
00139  **********************************************************************/
00140 /** Receive Overrun */
00141 #define SSP_RIS_ROR        ((uint32_t)(1<<0))
00142 /** Receive TimeOut */
00143 #define SSP_RIS_RT        ((uint32_t)(1<<1))
00144 /** Rx FIFO is at least half full */
00145 #define SSP_RIS_RX        ((uint32_t)(1<<2))
00146 /** Tx FIFO is at least half empty */
00147 #define SSP_RIS_TX        ((uint32_t)(1<<3))
00148 /** RIS bit mask */
00149 #define SSP_RIS_BITMASK    ((uint32_t)(0x0F))
00150 
00151 
00152 /*********************************************************************//**
00153  * Macro define for (MIS) Masked Interrupt Status registers
00154  **********************************************************************/
00155 /** Receive Overrun */
00156 #define SSP_MIS_ROR        ((uint32_t)(1<<0))
00157 /** Receive TimeOut */
00158 #define SSP_MIS_RT        ((uint32_t)(1<<1))
00159 /** Rx FIFO is at least half full */
00160 #define SSP_MIS_RX        ((uint32_t)(1<<2))
00161 /** Tx FIFO is at least half empty */
00162 #define SSP_MIS_TX        ((uint32_t)(1<<3))
00163 /** MIS bit mask */
00164 #define SSP_MIS_BITMASK    ((uint32_t)(0x0F))
00165 
00166 
00167 /*********************************************************************//**
00168  * Macro define for (ICR) Interrupt Clear registers
00169  **********************************************************************/
00170 /** Writing a 1 to this bit clears the "frame was received when
00171  * RxFIFO was full" interrupt */
00172 #define SSP_ICR_ROR        ((uint32_t)(1<<0))
00173 /** Writing a 1 to this bit clears the "Rx FIFO was not empty and
00174  * has not been read for a timeout period" interrupt */
00175 #define SSP_ICR_RT        ((uint32_t)(1<<1))
00176 /** ICR bit mask */
00177 #define SSP_ICR_BITMASK    ((uint32_t)(0x03))
00178 
00179 
00180 /*********************************************************************//**
00181  * Macro defines for DMACR register
00182  **********************************************************************/
00183 /** SSP bit for enabling RX DMA */
00184 #define SSP_DMA_RXDMA_EN      ((uint32_t)(1<<0))
00185 /** SSP bit for enabling TX DMA */
00186 #define SSP_DMA_TXDMA_EN      ((uint32_t)(1<<1))
00187 /** DMACR    bit mask */
00188 #define SSP_DMA_BITMASK        ((uint32_t)(0x03))
00189 
00190 /**
00191  * @}
00192  */
00193 
00194 /**
00195  * @}
00196  */
00197 
00198 
00199 /* Public Types --------------------------------------------------------------- */
00200 /** @defgroup SSP_Public_Types
00201  * @{
00202  */
00203 
00204 /** @brief SSP configuration structure */
00205 typedef struct {
00206     uint32_t Databit;         /** Databit number, should be SSP_DATABIT_x,
00207                             where x is in range from 4 - 16 */
00208     uint32_t CPHA;            /** Clock phase, should be:
00209                             - SSP_CPHA_FIRST: first clock edge
00210                             - SSP_CPHA_SECOND: second clock edge */
00211     uint32_t CPOL;            /** Clock polarity, should be:
00212                             - SSP_CPOL_HI: high level
00213                             - SSP_CPOL_LO: low level */
00214     uint32_t Mode;            /** SSP mode, should be:
00215                             - SSP_MASTER_MODE: Master mode
00216                             - SSP_SLAVE_MODE: Slave mode */
00217     uint32_t FrameFormat;    /** Frame Format:
00218                             - SSP_FRAME_SPI: Motorola SPI frame format
00219                             - SSP_FRAME_TI: TI frame format
00220                             - SSP_FRAME_MICROWIRE: National Microwire frame format */
00221     uint32_t ClockRate;        /** Clock rate,in Hz */
00222 } SSP_CFG_Type;
00223 
00224 /**
00225  * @brief SSP Transfer Type definitions
00226  */
00227 typedef enum {
00228     SSP_TRANSFER_POLLING = 0,    /**< Polling transfer */
00229     SSP_TRANSFER_INTERRUPT        /**< Interrupt transfer */
00230 } SSP_TRANSFER_Type;
00231 
00232 /**
00233  * @brief SPI Data configuration structure definitions
00234  */
00235 typedef struct {
00236     void *tx_data;                /**< Pointer to transmit data */
00237     uint32_t tx_cnt;            /**< Transmit counter */
00238     void *rx_data;                /**< Pointer to transmit data */
00239     uint32_t rx_cnt;            /**< Receive counter */
00240     uint32_t length;            /**< Length of transfer data */
00241     uint32_t status;            /**< Current status of SSP activity */
00242     void (*callback)(void);        /**< Pointer to Call back function when transmission complete
00243                                 used in interrupt transfer mode */
00244 } SSP_DATA_SETUP_Type;
00245 
00246 
00247 /**
00248  * @}
00249  */
00250 
00251 
00252 /* Public Macros -------------------------------------------------------------- */
00253 /** @defgroup SSP_Public_Macros
00254  * @{
00255  */
00256 
00257 /** Macro to determine if it is valid SSP port number */
00258 #define PARAM_SSPx(n)    ((((uint32_t *)n)==((uint32_t *)LPC_SSP0)) \
00259 || (((uint32_t *)n)==((uint32_t *)LPC_SSP1)))
00260 
00261 /*********************************************************************//**
00262  * SSP configuration parameter defines
00263  **********************************************************************/
00264 /** Clock phase control bit */
00265 #define SSP_CPHA_FIRST            ((uint32_t)(0))
00266 #define SSP_CPHA_SECOND            SSP_CR0_CPHA_SECOND
00267 #define PARAM_SSP_CPHA(n)         ((n==SSP_CPHA_FIRST) || (n==SSP_CPHA_SECOND))
00268 
00269 /** Clock polarity control bit */
00270 /* There's no bug here!!!
00271  * - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames.
00272  * That means the active clock is in HI state.
00273  * - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock
00274  * high between frames. That means the active clock is in LO state.
00275  */
00276 #define SSP_CPOL_HI                ((uint32_t)(0))
00277 #define SSP_CPOL_LO                SSP_CR0_CPOL_HI
00278 #define PARAM_SSP_CPOL(n)        ((n==SSP_CPOL_HI) || (n==SSP_CPOL_LO))
00279 
00280 /** SSP master mode enable */
00281 #define SSP_SLAVE_MODE            SSP_CR1_SLAVE_EN
00282 #define SSP_MASTER_MODE            ((uint32_t)(0))
00283 #define PARAM_SSP_MODE(n)        ((n==SSP_SLAVE_MODE) || (n==SSP_MASTER_MODE))
00284 
00285 /** SSP data bit number defines */
00286 #define SSP_DATABIT_4        SSP_CR0_DSS(4)             /*!< Databit number = 4 */
00287 #define SSP_DATABIT_5        SSP_CR0_DSS(5)             /*!< Databit number = 5 */
00288 #define SSP_DATABIT_6        SSP_CR0_DSS(6)             /*!< Databit number = 6 */
00289 #define SSP_DATABIT_7        SSP_CR0_DSS(7)             /*!< Databit number = 7 */
00290 #define SSP_DATABIT_8        SSP_CR0_DSS(8)             /*!< Databit number = 8 */
00291 #define SSP_DATABIT_9        SSP_CR0_DSS(9)             /*!< Databit number = 9 */
00292 #define SSP_DATABIT_10        SSP_CR0_DSS(10)         /*!< Databit number = 10 */
00293 #define SSP_DATABIT_11        SSP_CR0_DSS(11)         /*!< Databit number = 11 */
00294 #define SSP_DATABIT_12        SSP_CR0_DSS(12)         /*!< Databit number = 12 */
00295 #define SSP_DATABIT_13        SSP_CR0_DSS(13)         /*!< Databit number = 13 */
00296 #define SSP_DATABIT_14        SSP_CR0_DSS(14)         /*!< Databit number = 14 */
00297 #define SSP_DATABIT_15        SSP_CR0_DSS(15)         /*!< Databit number = 15 */
00298 #define SSP_DATABIT_16        SSP_CR0_DSS(16)         /*!< Databit number = 16 */
00299 #define PARAM_SSP_DATABIT(n)     ((n==SSP_DATABIT_4) || (n==SSP_DATABIT_5) \
00300 || (n==SSP_DATABIT_6) || (n==SSP_DATABIT_16) \
00301 || (n==SSP_DATABIT_7) || (n==SSP_DATABIT_8) \
00302 || (n==SSP_DATABIT_9) || (n==SSP_DATABIT_10) \
00303 || (n==SSP_DATABIT_11) || (n==SSP_DATABIT_12) \
00304 || (n==SSP_DATABIT_13) || (n==SSP_DATABIT_14) \
00305 || (n==SSP_DATABIT_15))
00306 
00307 /** SSP Frame Format definition */
00308 /** Motorola SPI mode */
00309 #define SSP_FRAME_SPI        SSP_CR0_FRF_SPI
00310 /** TI synchronous serial mode */
00311 #define SSP_FRAME_TI        SSP_CR0_FRF_TI
00312 /** National Micro-wire mode */
00313 #define SSP_FRAME_MICROWIRE    SSP_CR0_FRF_MICROWIRE
00314 
00315 #define PARAM_SSP_FRAME(n) ((n==SSP_FRAME_SPI) || (n==SSP_FRAME_TI)\
00316 || (n==SSP_FRAME_MICROWIRE))
00317 
00318 
00319 /*********************************************************************//**
00320  * SSP Status defines
00321  **********************************************************************/
00322 /** SSP status TX FIFO Empty bit */
00323 #define SSP_STAT_TXFIFO_EMPTY        SSP_SR_TFE
00324 /** SSP status TX FIFO not full bit */
00325 #define SSP_STAT_TXFIFO_NOTFULL        SSP_SR_TNF
00326 /** SSP status RX FIFO not empty bit */
00327 #define SSP_STAT_RXFIFO_NOTEMPTY    SSP_SR_RNE
00328 /** SSP status RX FIFO full bit */
00329 #define SSP_STAT_RXFIFO_FULL        SSP_SR_RFF
00330 /** SSP status SSP Busy bit */
00331 #define SSP_STAT_BUSY                SSP_SR_BSY
00332 
00333 #define PARAM_SSP_STAT(n) ((n==SSP_STAT_TXFIFO_EMPTY) || (n==SSP_STAT_TXFIFO_NOTFULL) \
00334 || (n==SSP_STAT_RXFIFO_NOTEMPTY) || (n==SSP_STAT_RXFIFO_FULL) \
00335 || (n==SSP_STAT_BUSY))
00336 
00337 
00338 /*********************************************************************//**
00339  * SSP Interrupt Configuration defines
00340  **********************************************************************/
00341 /** Receive Overrun */
00342 #define SSP_INTCFG_ROR        SSP_IMSC_ROR
00343 /** Receive TimeOut */
00344 #define SSP_INTCFG_RT        SSP_IMSC_RT
00345 /** Rx FIFO is at least half full */
00346 #define SSP_INTCFG_RX        SSP_IMSC_RX
00347 /** Tx FIFO is at least half empty */
00348 #define SSP_INTCFG_TX        SSP_IMSC_TX
00349 
00350 #define PARAM_SSP_INTCFG(n)    ((n==SSP_INTCFG_ROR) || (n==SSP_INTCFG_RT) \
00351 || (n==SSP_INTCFG_RX) || (n==SSP_INTCFG_TX))
00352 
00353 
00354 /*********************************************************************//**
00355  * SSP Configured Interrupt Status defines
00356  **********************************************************************/
00357 /** Receive Overrun */
00358 #define SSP_INTSTAT_ROR        SSP_MIS_ROR
00359 /** Receive TimeOut */
00360 #define SSP_INTSTAT_RT        SSP_MIS_RT
00361 /** Rx FIFO is at least half full */
00362 #define SSP_INTSTAT_RX        SSP_MIS_RX
00363 /** Tx FIFO is at least half empty */
00364 #define SSP_INTSTAT_TX        SSP_MIS_TX
00365 
00366 #define PARAM_SSP_INTSTAT(n) ((n==SSP_INTSTAT_ROR) || (n==SSP_INTSTAT_RT) \
00367 || (n==SSP_INTSTAT_RX) || (n==SSP_INTSTAT_TX))
00368 
00369 
00370 /*********************************************************************//**
00371  * SSP Raw Interrupt Status defines
00372  **********************************************************************/
00373 /** Receive Overrun */
00374 #define SSP_INTSTAT_RAW_ROR        SSP_RIS_ROR
00375 /** Receive TimeOut */
00376 #define SSP_INTSTAT_RAW_RT        SSP_RIS_RT
00377 /** Rx FIFO is at least half full */
00378 #define SSP_INTSTAT_RAW_RX        SSP_RIS_RX
00379 /** Tx FIFO is at least half empty */
00380 #define SSP_INTSTAT_RAW_TX        SSP_RIS_TX
00381 
00382 #define PARAM_SSP_INTSTAT_RAW(n)    ((n==SSP_INTSTAT_RAW_ROR) || (n==SSP_INTSTAT_RAW_RT) \
00383 || (n==SSP_INTSTAT_RAW_RX) || (n==SSP_INTSTAT_RAW_TX))
00384 
00385 
00386 /*********************************************************************//**
00387  * SSP Interrupt Clear defines
00388  **********************************************************************/
00389 /** Writing a 1 to this bit clears the "frame was received when
00390  * RxFIFO was full" interrupt */
00391 #define SSP_INTCLR_ROR        SSP_ICR_ROR
00392 /** Writing a 1 to this bit clears the "Rx FIFO was not empty and
00393  * has not been read for a timeout period" interrupt */
00394 #define SSP_INTCLR_RT        SSP_ICR_RT
00395 
00396 #define PARAM_SSP_INTCLR(n)    ((n==SSP_INTCLR_ROR) || (n==SSP_INTCLR_RT))
00397 
00398 
00399 /*********************************************************************//**
00400  * SSP DMA defines
00401  **********************************************************************/
00402 /** SSP bit for enabling RX DMA */
00403 #define SSP_DMA_TX        SSP_DMA_RXDMA_EN
00404 /** SSP bit for enabling TX DMA */
00405 #define SSP_DMA_RX        SSP_DMA_TXDMA_EN
00406 
00407 #define PARAM_SSP_DMA(n)    ((n==SSP_DMA_TX) || (n==SSP_DMA_RX))
00408 
00409 /* SSP Status Implementation definitions */
00410 #define SSP_STAT_DONE        (1UL<<8)        /**< Done */
00411 #define SSP_STAT_ERROR        (1UL<<9)        /**< Error */
00412 
00413 /**
00414  * @}
00415  */
00416 
00417 
00418 /* Public Functions ----------------------------------------------------------- */
00419 /** @defgroup SSP_Public_Functions
00420  * @{
00421  */
00422 
00423 void SSP_SetClock (LPC_SSP_TypeDef *SSPx, uint32_t target_clock);
00424 void SSP_DeInit(LPC_SSP_TypeDef* SSPx);
00425 void SSP_Init(LPC_SSP_TypeDef *SSPx, SSP_CFG_Type *SSP_ConfigStruct);
00426 void SSP_ConfigStructInit(SSP_CFG_Type *SSP_InitStruct);
00427 void SSP_Cmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState);
00428 void SSP_LoopBackCmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState);
00429 void SSP_SlaveOutputCmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState);
00430 void SSP_SendData(LPC_SSP_TypeDef* SSPx, uint16_t Data);
00431 uint16_t SSP_ReceiveData(LPC_SSP_TypeDef* SSPx);
00432 int32_t SSP_ReadWrite (LPC_SSP_TypeDef *SSPx, SSP_DATA_SETUP_Type *dataCfg, \
00433                         SSP_TRANSFER_Type xfType);
00434 FlagStatus SSP_GetStatus(LPC_SSP_TypeDef* SSPx, uint32_t FlagType);
00435 void SSP_IntConfig(LPC_SSP_TypeDef *SSPx, uint32_t IntType, FunctionalState NewState);
00436 IntStatus SSP_GetRawIntStatus(LPC_SSP_TypeDef *SSPx, uint32_t RawIntType);
00437 IntStatus SSP_GetIntStatus (LPC_SSP_TypeDef *SSPx, uint32_t IntType);
00438 void SSP_ClearIntPending(LPC_SSP_TypeDef *SSPx, uint32_t IntType);
00439 void SSP_DMACmd(LPC_SSP_TypeDef *SSPx, uint32_t DMAMode, FunctionalState NewState);
00440 void SSP0_StdIntHandler(void);
00441 void SSP1_StdIntHandler(void);
00442 
00443 /**
00444  * @}
00445  */
00446 
00447 #ifdef __cplusplus
00448 }
00449 #endif
00450 
00451 #endif /* LPC17XX_SSP_H_ */
00452 
00453 /**
00454  * @}
00455  */
00456 
00457 /* --------------------------------- End Of File ------------------------------ */