DriverLibrary - NXP's driver library for LPC17xx, ported to mbed'…

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Igor Skochinsky / Mbed 2 deprecated DriverLibrary

NXP's driver library for LPC17xx, ported to mbed's online compiler. Not tested! I had to fix a lot of warings and found a couple of pretty obvious bugs, so the chances are there are more. Original: http://ics.nxp.com/support/documents/microcontrollers/zip/lpc17xx.cmsis.driver.library.zip

Dependencies: mbed

include/lpc17xx_qei.h@0:1063a091a062, 2010-02-17 (annotated)

Committer:: igorsk
Date:: Wed Feb 17 16:22:39 2010 +0000
Revision:: 0:1063a091a062

Who changed what in which revision?

User	Revision	Line number	New contents of line
igorsk	0:1063a091a062	1	/*********************************************************************//
igorsk	0:1063a091a062	2	* @file : lpc17xx_qei.h
igorsk	0:1063a091a062	3	* @brief : Contains all macro definitions and function prototypes
igorsk	0:1063a091a062	4	* support for QEI firmware library on LPC17xx
igorsk	0:1063a091a062	5	* @version : 1.0
igorsk	0:1063a091a062	6	* @date : 26. May. 2009
igorsk	0:1063a091a062	7	* @author : HieuNguyen
igorsk	0:1063a091a062	8	**************************************************************************
igorsk	0:1063a091a062	9	* Software that is described herein is for illustrative purposes only
igorsk	0:1063a091a062	10	* which provides customers with programming information regarding the
igorsk	0:1063a091a062	11	* products. This software is supplied "AS IS" without any warranties.
igorsk	0:1063a091a062	12	* NXP Semiconductors assumes no responsibility or liability for the
igorsk	0:1063a091a062	13	* use of the software, conveys no license or title under any patent,
igorsk	0:1063a091a062	14	* copyright, or mask work right to the product. NXP Semiconductors
igorsk	0:1063a091a062	15	* reserves the right to make changes in the software without
igorsk	0:1063a091a062	16	* notification. NXP Semiconductors also make no representation or
igorsk	0:1063a091a062	17	* warranty that such application will be suitable for the specified
igorsk	0:1063a091a062	18	* use without further testing or modification.
igorsk	0:1063a091a062	19	**************************************************************************/
igorsk	0:1063a091a062	20
igorsk	0:1063a091a062	21	/* Peripheral group ----------------------------------------------------------- */
igorsk	0:1063a091a062	22	/** @defgroup QEI
igorsk	0:1063a091a062	23	* @ingroup LPC1700CMSIS_FwLib_Drivers
igorsk	0:1063a091a062	24	* @{
igorsk	0:1063a091a062	25	*/
igorsk	0:1063a091a062	26
igorsk	0:1063a091a062	27	#ifndef LPC17XX_QEI_H_
igorsk	0:1063a091a062	28	#define LPC17XX_QEI_H_
igorsk	0:1063a091a062	29
igorsk	0:1063a091a062	30	/* Includes ------------------------------------------------------------------- */
igorsk	0:1063a091a062	31	#include "cmsis.h"
igorsk	0:1063a091a062	32	#include "lpc_types.h"
igorsk	0:1063a091a062	33
igorsk	0:1063a091a062	34
igorsk	0:1063a091a062	35	#ifdef __cplusplus
igorsk	0:1063a091a062	36	extern "C"
igorsk	0:1063a091a062	37	{
igorsk	0:1063a091a062	38	#endif
igorsk	0:1063a091a062	39
igorsk	0:1063a091a062	40
igorsk	0:1063a091a062	41	/* Private Macros ------------------------------------------------------------- */
igorsk	0:1063a091a062	42	/** @defgroup QEI_Private_Macros
igorsk	0:1063a091a062	43	* @{
igorsk	0:1063a091a062	44	*/
igorsk	0:1063a091a062	45
igorsk	0:1063a091a062	46	/** @defgroup QEI_REGISTER_BIT_DEFINITIONS
igorsk	0:1063a091a062	47	* @{
igorsk	0:1063a091a062	48	*/
igorsk	0:1063a091a062	49
igorsk	0:1063a091a062	50	/* Quadrature Encoder Interface Control Register Definition --------------------- */
igorsk	0:1063a091a062	51	/* QEI Control register */
igorsk	0:1063a091a062	52	#define QEI_CON_RESP ((uint32_t)(1<<0)) /*< Reset position counter /
igorsk	0:1063a091a062	53	#define QEI_CON_RESPI ((uint32_t)(1<<1)) /*< Reset Posistion Counter on Index /
igorsk	0:1063a091a062	54	#define QEI_CON_RESV ((uint32_t)(1<<2)) /*< Reset Velocity /
igorsk	0:1063a091a062	55	#define QEI_CON_RESI ((uint32_t)(1<<3)) /*< Reset Index Counter /
igorsk	0:1063a091a062	56	#define QEI_CON_BITMASK ((uint32_t)(0x0F)) /*< QEI Control register bit-mask /
igorsk	0:1063a091a062	57
igorsk	0:1063a091a062	58	/* QEI Configuration register */
igorsk	0:1063a091a062	59	#define QEI_CONF_DIRINV ((uint32_t)(1<<0)) /*< Direction Invert /
igorsk	0:1063a091a062	60	#define QEI_CONF_SIGMODE ((uint32_t)(1<<1)) /*< Signal mode /
igorsk	0:1063a091a062	61	#define QEI_CONF_CAPMODE ((uint32_t)(1<<2)) /*< Capture mode /
igorsk	0:1063a091a062	62	#define QEI_CONF_INVINX ((uint32_t)(1<<3)) /*< Invert index /
igorsk	0:1063a091a062	63	#define QEI_CONF_BITMASK ((uint32_t)(0x0F)) /*< QEI Configuration register bit-mask /
igorsk	0:1063a091a062	64
igorsk	0:1063a091a062	65	/* QEI Status register */
igorsk	0:1063a091a062	66	#define QEI_STAT_DIR ((uint32_t)(1<<0)) /*< Direction bit /
igorsk	0:1063a091a062	67	#define QEI_STAT_BITMASK ((uint32_t)(1<<0)) /*< QEI status register bit-mask /
igorsk	0:1063a091a062	68
igorsk	0:1063a091a062	69	/* Quadrature Encoder Interface Position, index and timer Register Definitions --- */
igorsk	0:1063a091a062	70	/* QEI Position register */
igorsk	0:1063a091a062	71
igorsk	0:1063a091a062	72	/* QEI Maximum Position register */
igorsk	0:1063a091a062	73
igorsk	0:1063a091a062	74	/* QEI Position Compare register 0 */
igorsk	0:1063a091a062	75
igorsk	0:1063a091a062	76	/* QEI Position Compare register 1 */
igorsk	0:1063a091a062	77
igorsk	0:1063a091a062	78	/* QEI Position Compare register 2 */
igorsk	0:1063a091a062	79
igorsk	0:1063a091a062	80	/* QEI Index Count register */
igorsk	0:1063a091a062	81
igorsk	0:1063a091a062	82	/* QEI Index Compare register */
igorsk	0:1063a091a062	83
igorsk	0:1063a091a062	84	/* QEI Timer Reload register */
igorsk	0:1063a091a062	85
igorsk	0:1063a091a062	86	/* QEI Timer register */
igorsk	0:1063a091a062	87
igorsk	0:1063a091a062	88	/* QEI Velocity register */
igorsk	0:1063a091a062	89
igorsk	0:1063a091a062	90	/* QEI Velocity Capture register */
igorsk	0:1063a091a062	91
igorsk	0:1063a091a062	92	/* QEI Velocity Compare register */
igorsk	0:1063a091a062	93
igorsk	0:1063a091a062	94	/* QEI Digital Filter register */
igorsk	0:1063a091a062	95
igorsk	0:1063a091a062	96	/* Quadrature Encoder Interface Interrupt registers definitions --------------------- */
igorsk	0:1063a091a062	97	/* QEI Interrupt Status register */
igorsk	0:1063a091a062	98	#define QEI_INTSTAT_INX_Int ((uint32_t)(1<<0)) /*< Indicates that an index pulse was detected /
igorsk	0:1063a091a062	99	#define QEI_INTSTAT_TIM_Int ((uint32_t)(1<<1)) /*< Indicates that a velocity timer overflow occurred /
igorsk	0:1063a091a062	100	#define QEI_INTSTAT_VELC_Int ((uint32_t)(1<<2)) /*< Indicates that capture velocity is less than compare velocity /
igorsk	0:1063a091a062	101	#define QEI_INTSTAT_DIR_Int ((uint32_t)(1<<3)) /*< Indicates that a change of direction was detected /
igorsk	0:1063a091a062	102	#define QEI_INTSTAT_ERR_Int ((uint32_t)(1<<4)) /*< Indicates that an encoder phase error was detected /
igorsk	0:1063a091a062	103	#define QEI_INTSTAT_ENCLK_Int ((uint32_t)(1<<5)) /*< Indicates that and encoder clock pulse was detected /
igorsk	0:1063a091a062	104	#define QEI_INTSTAT_POS0_Int ((uint32_t)(1<<6)) /**< Indicates that the position 0 compare value is equal to the
igorsk	0:1063a091a062	105	current position */
igorsk	0:1063a091a062	106	#define QEI_INTSTAT_POS1_Int ((uint32_t)(1<<7)) /**< Indicates that the position 1compare value is equal to the
igorsk	0:1063a091a062	107	current position */
igorsk	0:1063a091a062	108	#define QEI_INTSTAT_POS2_Int ((uint32_t)(1<<8)) /**< Indicates that the position 2 compare value is equal to the
igorsk	0:1063a091a062	109	current position */
igorsk	0:1063a091a062	110	#define QEI_INTSTAT_REV_Int ((uint32_t)(1<<9)) /**< Indicates that the index compare value is equal to the current
igorsk	0:1063a091a062	111	index count */
igorsk	0:1063a091a062	112	#define QEI_INTSTAT_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt. Set when
igorsk	0:1063a091a062	113	both the POS0_Int bit is set and the REV_Int is set */
igorsk	0:1063a091a062	114	#define QEI_INTSTAT_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt. Set when
igorsk	0:1063a091a062	115	both the POS1_Int bit is set and the REV_Int is set */
igorsk	0:1063a091a062	116	#define QEI_INTSTAT_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt. Set when
igorsk	0:1063a091a062	117	both the POS2_Int bit is set and the REV_Int is set */
igorsk	0:1063a091a062	118	#define QEI_INTSTAT_BITMASK ((uint32_t)(0x1FFF)) /*< QEI Interrupt Status register bit-mask /
igorsk	0:1063a091a062	119
igorsk	0:1063a091a062	120	/* QEI Interrupt Set register */
igorsk	0:1063a091a062	121	#define QEI_INTSET_INX_Int ((uint32_t)(1<<0)) /*< Set Bit Indicates that an index pulse was detected /
igorsk	0:1063a091a062	122	#define QEI_INTSET_TIM_Int ((uint32_t)(1<<1)) /*< Set Bit Indicates that a velocity timer overflow occurred /
igorsk	0:1063a091a062	123	#define QEI_INTSET_VELC_Int ((uint32_t)(1<<2)) /*< Set Bit Indicates that capture velocity is less than compare velocity /
igorsk	0:1063a091a062	124	#define QEI_INTSET_DIR_Int ((uint32_t)(1<<3)) /*< Set Bit Indicates that a change of direction was detected /
igorsk	0:1063a091a062	125	#define QEI_INTSET_ERR_Int ((uint32_t)(1<<4)) /*< Set Bit Indicates that an encoder phase error was detected /
igorsk	0:1063a091a062	126	#define QEI_INTSET_ENCLK_Int ((uint32_t)(1<<5)) /*< Set Bit Indicates that and encoder clock pulse was detected /
igorsk	0:1063a091a062	127	#define QEI_INTSET_POS0_Int ((uint32_t)(1<<6)) /**< Set Bit Indicates that the position 0 compare value is equal to the
igorsk	0:1063a091a062	128	current position */
igorsk	0:1063a091a062	129	#define QEI_INTSET_POS1_Int ((uint32_t)(1<<7)) /**< Set Bit Indicates that the position 1compare value is equal to the
igorsk	0:1063a091a062	130	current position */
igorsk	0:1063a091a062	131	#define QEI_INTSET_POS2_Int ((uint32_t)(1<<8)) /**< Set Bit Indicates that the position 2 compare value is equal to the
igorsk	0:1063a091a062	132	current position */
igorsk	0:1063a091a062	133	#define QEI_INTSET_REV_Int ((uint32_t)(1<<9)) /**< Set Bit Indicates that the index compare value is equal to the current
igorsk	0:1063a091a062	134	index count */
igorsk	0:1063a091a062	135	#define QEI_INTSET_POS0REV_Int ((uint32_t)(1<<10)) /*< Set Bit that combined position 0 and revolution count interrupt /
igorsk	0:1063a091a062	136	#define QEI_INTSET_POS1REV_Int ((uint32_t)(1<<11)) /*< Set Bit that Combined position 1 and revolution count interrupt /
igorsk	0:1063a091a062	137	#define QEI_INTSET_POS2REV_Int ((uint32_t)(1<<12)) /*< Set Bit that Combined position 2 and revolution count interrupt /
igorsk	0:1063a091a062	138	#define QEI_INTSET_BITMASK ((uint32_t)(0x1FFF)) /*< QEI Interrupt Set register bit-mask /
igorsk	0:1063a091a062	139
igorsk	0:1063a091a062	140	/* QEI Interrupt Clear register */
igorsk	0:1063a091a062	141	#define QEI_INTCLR_INX_Int ((uint32_t)(1<<0)) /*< Clear Bit Indicates that an index pulse was detected /
igorsk	0:1063a091a062	142	#define QEI_INTCLR_TIM_Int ((uint32_t)(1<<1)) /*< Clear Bit Indicates that a velocity timer overflow occurred /
igorsk	0:1063a091a062	143	#define QEI_INTCLR_VELC_Int ((uint32_t)(1<<2)) /*< Clear Bit Indicates that capture velocity is less than compare velocity /
igorsk	0:1063a091a062	144	#define QEI_INTCLR_DIR_Int ((uint32_t)(1<<3)) /*< Clear Bit Indicates that a change of direction was detected /
igorsk	0:1063a091a062	145	#define QEI_INTCLR_ERR_Int ((uint32_t)(1<<4)) /*< Clear Bit Indicates that an encoder phase error was detected /
igorsk	0:1063a091a062	146	#define QEI_INTCLR_ENCLK_Int ((uint32_t)(1<<5)) /*< Clear Bit Indicates that and encoder clock pulse was detected /
igorsk	0:1063a091a062	147	#define QEI_INTCLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Bit Indicates that the position 0 compare value is equal to the
igorsk	0:1063a091a062	148	current position */
igorsk	0:1063a091a062	149	#define QEI_INTCLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Bit Indicates that the position 1compare value is equal to the
igorsk	0:1063a091a062	150	current position */
igorsk	0:1063a091a062	151	#define QEI_INTCLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Bit Indicates that the position 2 compare value is equal to the
igorsk	0:1063a091a062	152	current position */
igorsk	0:1063a091a062	153	#define QEI_INTCLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Bit Indicates that the index compare value is equal to the current
igorsk	0:1063a091a062	154	index count */
igorsk	0:1063a091a062	155	#define QEI_INTCLR_POS0REV_Int ((uint32_t)(1<<10)) /*< Clear Bit that combined position 0 and revolution count interrupt /
igorsk	0:1063a091a062	156	#define QEI_INTCLR_POS1REV_Int ((uint32_t)(1<<11)) /*< Clear Bit that Combined position 1 and revolution count interrupt /
igorsk	0:1063a091a062	157	#define QEI_INTCLR_POS2REV_Int ((uint32_t)(1<<12)) /*< Clear Bit that Combined position 2 and revolution count interrupt /
igorsk	0:1063a091a062	158	#define QEI_INTCLR_BITMASK ((uint32_t)(0x1FFF)) /*< QEI Interrupt Clear register bit-mask /
igorsk	0:1063a091a062	159
igorsk	0:1063a091a062	160	/* QEI Interrupt Enable register */
igorsk	0:1063a091a062	161	#define QEI_INTEN_INX_Int ((uint32_t)(1<<0)) /*< Enabled Interrupt Bit Indicates that an index pulse was detected /
igorsk	0:1063a091a062	162	#define QEI_INTEN_TIM_Int ((uint32_t)(1<<1)) /*< Enabled Interrupt Bit Indicates that a velocity timer overflow occurred /
igorsk	0:1063a091a062	163	#define QEI_INTEN_VELC_Int ((uint32_t)(1<<2)) /*< Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity /
igorsk	0:1063a091a062	164	#define QEI_INTEN_DIR_Int ((uint32_t)(1<<3)) /*< Enabled Interrupt Bit Indicates that a change of direction was detected /
igorsk	0:1063a091a062	165	#define QEI_INTEN_ERR_Int ((uint32_t)(1<<4)) /*< Enabled Interrupt Bit Indicates that an encoder phase error was detected /
igorsk	0:1063a091a062	166	#define QEI_INTEN_ENCLK_Int ((uint32_t)(1<<5)) /*< Enabled Interrupt Bit Indicates that and encoder clock pulse was detected /
igorsk	0:1063a091a062	167	#define QEI_INTEN_POS0_Int ((uint32_t)(1<<6)) /**< Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the
igorsk	0:1063a091a062	168	current position */
igorsk	0:1063a091a062	169	#define QEI_INTEN_POS1_Int ((uint32_t)(1<<7)) /**< Enabled Interrupt Bit Indicates that the position 1compare value is equal to the
igorsk	0:1063a091a062	170	current position */
igorsk	0:1063a091a062	171	#define QEI_INTEN_POS2_Int ((uint32_t)(1<<8)) /**< Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the
igorsk	0:1063a091a062	172	current position */
igorsk	0:1063a091a062	173	#define QEI_INTEN_REV_Int ((uint32_t)(1<<9)) /**< Enabled Interrupt Bit Indicates that the index compare value is equal to the current
igorsk	0:1063a091a062	174	index count */
igorsk	0:1063a091a062	175	#define QEI_INTEN_POS0REV_Int ((uint32_t)(1<<10)) /*< Enabled Interrupt Bit that combined position 0 and revolution count interrupt /
igorsk	0:1063a091a062	176	#define QEI_INTEN_POS1REV_Int ((uint32_t)(1<<11)) /*< Enabled Interrupt Bit that Combined position 1 and revolution count interrupt /
igorsk	0:1063a091a062	177	#define QEI_INTEN_POS2REV_Int ((uint32_t)(1<<12)) /*< Enabled Interrupt Bit that Combined position 2 and revolution count interrupt /
igorsk	0:1063a091a062	178	#define QEI_INTEN_BITMASK ((uint32_t)(0x1FFF)) /*< QEI Interrupt Enable register bit-mask /
igorsk	0:1063a091a062	179
igorsk	0:1063a091a062	180	/* QEI Interrupt Enable Set register */
igorsk	0:1063a091a062	181	#define QEI_IESET_INX_Int ((uint32_t)(1<<0)) /*< Set Enable Interrupt Bit Indicates that an index pulse was detected /
igorsk	0:1063a091a062	182	#define QEI_IESET_TIM_Int ((uint32_t)(1<<1)) /*< Set Enable Interrupt Bit Indicates that a velocity timer overflow occurred /
igorsk	0:1063a091a062	183	#define QEI_IESET_VELC_Int ((uint32_t)(1<<2)) /*< Set Enable Interrupt Bit Indicates that capture velocity is less than compare velocity /
igorsk	0:1063a091a062	184	#define QEI_IESET_DIR_Int ((uint32_t)(1<<3)) /*< Set Enable Interrupt Bit Indicates that a change of direction was detected /
igorsk	0:1063a091a062	185	#define QEI_IESET_ERR_Int ((uint32_t)(1<<4)) /*< Set Enable Interrupt Bit Indicates that an encoder phase error was detected /
igorsk	0:1063a091a062	186	#define QEI_IESET_ENCLK_Int ((uint32_t)(1<<5)) /*< Set Enable Interrupt Bit Indicates that and encoder clock pulse was detected /
igorsk	0:1063a091a062	187	#define QEI_IESET_POS0_Int ((uint32_t)(1<<6)) /**< Set Enable Interrupt Bit Indicates that the position 0 compare value is equal to the
igorsk	0:1063a091a062	188	current position */
igorsk	0:1063a091a062	189	#define QEI_IESET_POS1_Int ((uint32_t)(1<<7)) /**< Set Enable Interrupt Bit Indicates that the position 1compare value is equal to the
igorsk	0:1063a091a062	190	current position */
igorsk	0:1063a091a062	191	#define QEI_IESET_POS2_Int ((uint32_t)(1<<8)) /**< Set Enable Interrupt Bit Indicates that the position 2 compare value is equal to the
igorsk	0:1063a091a062	192	current position */
igorsk	0:1063a091a062	193	#define QEI_IESET_REV_Int ((uint32_t)(1<<9)) /**< Set Enable Interrupt Bit Indicates that the index compare value is equal to the current
igorsk	0:1063a091a062	194	index count */
igorsk	0:1063a091a062	195	#define QEI_IESET_POS0REV_Int ((uint32_t)(1<<10)) /*< Set Enable Interrupt Bit that combined position 0 and revolution count interrupt /
igorsk	0:1063a091a062	196	#define QEI_IESET_POS1REV_Int ((uint32_t)(1<<11)) /*< Set Enable Interrupt Bit that Combined position 1 and revolution count interrupt /
igorsk	0:1063a091a062	197	#define QEI_IESET_POS2REV_Int ((uint32_t)(1<<12)) /*< Set Enable Interrupt Bit that Combined position 2 and revolution count interrupt /
igorsk	0:1063a091a062	198	#define QEI_IESET_BITMASK ((uint32_t)(0x1FFF)) /*< QEI Interrupt Enable Set register bit-mask /
igorsk	0:1063a091a062	199
igorsk	0:1063a091a062	200	/* QEI Interrupt Enable Clear register */
igorsk	0:1063a091a062	201	#define QEI_IECLR_INX_Int ((uint32_t)(1<<0)) /*< Clear Enabled Interrupt Bit Indicates that an index pulse was detected /
igorsk	0:1063a091a062	202	#define QEI_IECLR_TIM_Int ((uint32_t)(1<<1)) /*< Clear Enabled Interrupt Bit Indicates that a velocity timer overflow occurred /
igorsk	0:1063a091a062	203	#define QEI_IECLR_VELC_Int ((uint32_t)(1<<2)) /*< Clear Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity /
igorsk	0:1063a091a062	204	#define QEI_IECLR_DIR_Int ((uint32_t)(1<<3)) /*< Clear Enabled Interrupt Bit Indicates that a change of direction was detected /
igorsk	0:1063a091a062	205	#define QEI_IECLR_ERR_Int ((uint32_t)(1<<4)) /*< Clear Enabled Interrupt Bit Indicates that an encoder phase error was detected /
igorsk	0:1063a091a062	206	#define QEI_IECLR_ENCLK_Int ((uint32_t)(1<<5)) /*< Clear Enabled Interrupt Bit Indicates that and encoder clock pulse was detected /
igorsk	0:1063a091a062	207	#define QEI_IECLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the
igorsk	0:1063a091a062	208	current position */
igorsk	0:1063a091a062	209	#define QEI_IECLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Enabled Interrupt Bit Indicates that the position 1compare value is equal to the
igorsk	0:1063a091a062	210	current position */
igorsk	0:1063a091a062	211	#define QEI_IECLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the
igorsk	0:1063a091a062	212	current position */
igorsk	0:1063a091a062	213	#define QEI_IECLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Enabled Interrupt Bit Indicates that the index compare value is equal to the current
igorsk	0:1063a091a062	214	index count */
igorsk	0:1063a091a062	215	#define QEI_IECLR_POS0REV_Int ((uint32_t)(1<<10)) /*< Clear Enabled Interrupt Bit that combined position 0 and revolution count interrupt /
igorsk	0:1063a091a062	216	#define QEI_IECLR_POS1REV_Int ((uint32_t)(1<<11)) /*< Clear Enabled Interrupt Bit that Combined position 1 and revolution count interrupt /
igorsk	0:1063a091a062	217	#define QEI_IECLR_POS2REV_Int ((uint32_t)(1<<12)) /*< Clear Enabled Interrupt Bit that Combined position 2 and revolution count interrupt /
igorsk	0:1063a091a062	218	#define QEI_IECLR_BITMASK ((uint32_t)(0x1FFF)) /*< QEI Interrupt Enable Clear register bit-mask /
igorsk	0:1063a091a062	219
igorsk	0:1063a091a062	220
igorsk	0:1063a091a062	221	/**
igorsk	0:1063a091a062	222	* @}
igorsk	0:1063a091a062	223	*/
igorsk	0:1063a091a062	224
igorsk	0:1063a091a062	225	/**
igorsk	0:1063a091a062	226	* @}
igorsk	0:1063a091a062	227	*/
igorsk	0:1063a091a062	228
igorsk	0:1063a091a062	229
igorsk	0:1063a091a062	230	/* Public Types --------------------------------------------------------------- */
igorsk	0:1063a091a062	231	/** @defgroup QEI_Public_Types
igorsk	0:1063a091a062	232	* @{
igorsk	0:1063a091a062	233	*/
igorsk	0:1063a091a062	234
igorsk	0:1063a091a062	235	/**
igorsk	0:1063a091a062	236	* @brief QEI Configuration structure type definition
igorsk	0:1063a091a062	237	*/
igorsk	0:1063a091a062	238	typedef struct {
igorsk	0:1063a091a062	239	uint32_t DirectionInvert :1; /**< Direction invert option:
igorsk	0:1063a091a062	240	- QEI_DIRINV_NONE: QEI Direction is normal
igorsk	0:1063a091a062	241	- QEI_DIRINV_CMPL: QEI Direction is complemented
igorsk	0:1063a091a062	242	*/
igorsk	0:1063a091a062	243	uint32_t SignalMode :1; /**< Signal mode Option:
igorsk	0:1063a091a062	244	- QEI_SIGNALMODE_QUAD: Signal is in Quadrature phase mode
igorsk	0:1063a091a062	245	- QEI_SIGNALMODE_CLKDIR: Signal is in Clock/Direction mode
igorsk	0:1063a091a062	246	*/
igorsk	0:1063a091a062	247	uint32_t CaptureMode :1; /**< Capture Mode Option:
igorsk	0:1063a091a062	248	- QEI_CAPMODE_2X: Only Phase-A edges are counted (2X)
igorsk	0:1063a091a062	249	- QEI_CAPMODE_4X: BOTH Phase-A and Phase-B edges are counted (4X)
igorsk	0:1063a091a062	250	*/
igorsk	0:1063a091a062	251	uint32_t InvertIndex :1; /**< Invert Index Option:
igorsk	0:1063a091a062	252	- QEI_INVINX_NONE: the sense of the index input is normal
igorsk	0:1063a091a062	253	- QEI_INVINX_EN: inverts the sense of the index input
igorsk	0:1063a091a062	254	*/
igorsk	0:1063a091a062	255	} QEI_CFG_Type;
igorsk	0:1063a091a062	256
igorsk	0:1063a091a062	257	/**
igorsk	0:1063a091a062	258	* @brief Timer Reload Configuration structure type definition
igorsk	0:1063a091a062	259	*/
igorsk	0:1063a091a062	260	typedef struct {
igorsk	0:1063a091a062	261
igorsk	0:1063a091a062	262	uint8_t ReloadOption; /**< Velocity Timer Reload Option, should be:
igorsk	0:1063a091a062	263	- QEI_TIMERRELOAD_TICKVAL: Reload value in absolute value
igorsk	0:1063a091a062	264	- QEI_TIMERRELOAD_USVAL: Reload value in microsecond value
igorsk	0:1063a091a062	265	*/
igorsk	0:1063a091a062	266	uint8_t Reserved[3];
igorsk	0:1063a091a062	267	uint32_t ReloadValue; /**< Velocity Timer Reload Value, 32-bit long, should be matched
igorsk	0:1063a091a062	268	with Velocity Timer Reload Option
igorsk	0:1063a091a062	269	*/
igorsk	0:1063a091a062	270	} QEI_RELOADCFG_Type;
igorsk	0:1063a091a062	271
igorsk	0:1063a091a062	272	/**
igorsk	0:1063a091a062	273	* @}
igorsk	0:1063a091a062	274	*/
igorsk	0:1063a091a062	275
igorsk	0:1063a091a062	276
igorsk	0:1063a091a062	277	/* Public Macros -------------------------------------------------------------- */
igorsk	0:1063a091a062	278	/** @defgroup QEI_Public_Macros
igorsk	0:1063a091a062	279	* @{
igorsk	0:1063a091a062	280	*/
igorsk	0:1063a091a062	281
igorsk	0:1063a091a062	282	#define PARAM_QEIx(n) ((n==LPC_QEI))
igorsk	0:1063a091a062	283
igorsk	0:1063a091a062	284	/* QEI Reset types */
igorsk	0:1063a091a062	285	#define QEI_RESET_POS QEI_CON_RESP /*< Reset position counter /
igorsk	0:1063a091a062	286	#define QEI_RESET_POSOnIDX QEI_CON_RESPI /*< Reset Posistion Counter on Index /
igorsk	0:1063a091a062	287	#define QEI_RESET_VEL QEI_CON_RESV /*< Reset Velocity /
igorsk	0:1063a091a062	288	#define QEI_RESET_IDX QEI_CON_RESI /*< Reset Index Counter /
igorsk	0:1063a091a062	289
igorsk	0:1063a091a062	290	#define PARAM_QEI_RESET(n) ((n==QEI_CON_RESP) \
igorsk	0:1063a091a062	291	\|\| (n==QEI_RESET_POSOnIDX) \
igorsk	0:1063a091a062	292	\|\| (n==QEI_RESET_VEL) \
igorsk	0:1063a091a062	293	\|\| (n==QEI_RESET_IDX))
igorsk	0:1063a091a062	294
igorsk	0:1063a091a062	295	/* QEI Direction Invert Type Option */
igorsk	0:1063a091a062	296	#define QEI_DIRINV_NONE ((uint32_t)(0)) /*< Direction is not inverted /
igorsk	0:1063a091a062	297	#define QEI_DIRINV_CMPL ((uint32_t)(1)) /*< Direction is complemented /
igorsk	0:1063a091a062	298
igorsk	0:1063a091a062	299	#define PARAM_QEI_DIRINV(n) ((n==QEI_DIRINV_NONE) \|\| (n==QEI_DIRINV_CMPL))
igorsk	0:1063a091a062	300
igorsk	0:1063a091a062	301	/* QEI Signal Mode Option */
igorsk	0:1063a091a062	302	#define QEI_SIGNALMODE_QUAD ((uint32_t)(0)) /*< Signal operation: Quadrature phase mode /
igorsk	0:1063a091a062	303	#define QEI_SIGNALMODE_CLKDIR ((uint32_t)(1)) /*< Signal operation: Clock/Direction mode /
igorsk	0:1063a091a062	304
igorsk	0:1063a091a062	305	#define PARAM_QEI_SIGNALMODE(n) ((n==QEI_SIGNALMODE_QUAD) \|\| (n==QEI_SIGNALMODE_CLKDIR))
igorsk	0:1063a091a062	306
igorsk	0:1063a091a062	307	/* QEI Capture Mode Option */
igorsk	0:1063a091a062	308	#define QEI_CAPMODE_2X ((uint32_t)(0)) /*< Capture mode: Only Phase-A edges are counted (2X) /
igorsk	0:1063a091a062	309	#define QEI_CAPMODE_4X ((uint32_t)(1)) /*< Capture mode: BOTH PhA and PhB edges are counted (4X)/
igorsk	0:1063a091a062	310
igorsk	0:1063a091a062	311	#define PARAM_QEI_CAPMODE(n) ((n==QEI_CAPMODE_2X) \|\| (n==QEI_CAPMODE_4X))
igorsk	0:1063a091a062	312
igorsk	0:1063a091a062	313	/* QEI Invert Index Signal Option */
igorsk	0:1063a091a062	314	#define QEI_INVINX_NONE ((uint32_t)(0)) /*< Invert Index signal option: None /
igorsk	0:1063a091a062	315	#define QEI_INVINX_EN ((uint32_t)(1)) /*< Invert Index signal option: Enable /
igorsk	0:1063a091a062	316
igorsk	0:1063a091a062	317	#define PARAM_QEI_INVINX(n) ((n==QEI_INVINX_NONE) \|\| (n==QEI_INVINX_EN))
igorsk	0:1063a091a062	318
igorsk	0:1063a091a062	319	/* QEI timer reload option */
igorsk	0:1063a091a062	320	#define QEI_TIMERRELOAD_TICKVAL ((uint8_t)(0)) /*< Reload value in absolute value /
igorsk	0:1063a091a062	321	#define QEI_TIMERRELOAD_USVAL ((uint8_t)(1)) /*< Reload value in microsecond value /
igorsk	0:1063a091a062	322	#define PARAM_QEI_TIMERRELOAD(n) ((n==QEI_TIMERRELOAD_TICKVAL) \|\| (n==QEI_TIMERRELOAD_USVAL))
igorsk	0:1063a091a062	323
igorsk	0:1063a091a062	324	/* QEI Flag Status type */
igorsk	0:1063a091a062	325	#define QEI_STATUS_DIR ((uint32_t)(1<<0)) /*< Direction status /
igorsk	0:1063a091a062	326	#define PARAM_QEI_STATUS(n) ((n==QEI_STATUS_DIR))
igorsk	0:1063a091a062	327
igorsk	0:1063a091a062	328	/* QEI Compare Position channel option */
igorsk	0:1063a091a062	329	#define QEI_COMPPOS_CH_0 ((uint8_t)(0)) /*< QEI compare position channel 0 /
igorsk	0:1063a091a062	330	#define QEI_COMPPOS_CH_1 ((uint8_t)(1)) /*< QEI compare position channel 1 /
igorsk	0:1063a091a062	331	#define QEI_COMPPOS_CH_2 ((uint8_t)(2)) /*< QEI compare position channel 2 /
igorsk	0:1063a091a062	332	#define PARAM_QEI_COMPPOS_CH(n) ((n==QEI_COMPPOS_CH_0) \|\| (n==QEI_COMPPOS_CH_1) \|\| (n==QEI_COMPPOS_CH_2))
igorsk	0:1063a091a062	333
igorsk	0:1063a091a062	334	/* QEI interrupt flag type */
igorsk	0:1063a091a062	335	#define QEI_INTFLAG_INX_Int ((uint32_t)(1<<0)) /*< index pulse was detected interrupt /
igorsk	0:1063a091a062	336	#define QEI_INTFLAG_TIM_Int ((uint32_t)(1<<1)) /*< Velocity timer over flow interrupt /
igorsk	0:1063a091a062	337	#define QEI_INTFLAG_VELC_Int ((uint32_t)(1<<2)) /*< Capture velocity is less than compare interrupt /
igorsk	0:1063a091a062	338	#define QEI_INTFLAG_DIR_Int ((uint32_t)(1<<3)) /*< Change of direction interrupt /
igorsk	0:1063a091a062	339	#define QEI_INTFLAG_ERR_Int ((uint32_t)(1<<4)) /*< An encoder phase error interrupt /
igorsk	0:1063a091a062	340	#define QEI_INTFLAG_ENCLK_Int ((uint32_t)(1<<5)) /*< An encoder clock pulse was detected interrupt /
igorsk	0:1063a091a062	341	#define QEI_INTFLAG_POS0_Int ((uint32_t)(1<<6)) /**< position 0 compare value is equal to the
igorsk	0:1063a091a062	342	current position interrupt */
igorsk	0:1063a091a062	343	#define QEI_INTFLAG_POS1_Int ((uint32_t)(1<<7)) /**< position 1 compare value is equal to the
igorsk	0:1063a091a062	344	current position interrupt */
igorsk	0:1063a091a062	345	#define QEI_INTFLAG_POS2_Int ((uint32_t)(1<<8)) /**< position 2 compare value is equal to the
igorsk	0:1063a091a062	346	current position interrupt */
igorsk	0:1063a091a062	347	#define QEI_INTFLAG_REV_Int ((uint32_t)(1<<9)) /**< Index compare value is equal to the current
igorsk	0:1063a091a062	348	index count interrupt */
igorsk	0:1063a091a062	349	#define QEI_INTFLAG_POS0REV_Int ((uint32_t)(1<<10)) /*< Combined position 0 and revolution count interrupt /
igorsk	0:1063a091a062	350	#define QEI_INTFLAG_POS1REV_Int ((uint32_t)(1<<11)) /*< Combined position 1 and revolution count interrupt /
igorsk	0:1063a091a062	351	#define QEI_INTFLAG_POS2REV_Int ((uint32_t)(1<<12)) /*< Combined position 2 and revolution count interrupt /
igorsk	0:1063a091a062	352
igorsk	0:1063a091a062	353	#define PARAM_QEI_INTFLAG(n) ((n==QEI_INTFLAG_INX_Int) \
igorsk	0:1063a091a062	354	\|\| (n==QEI_INTFLAG_TIM_Int) \
igorsk	0:1063a091a062	355	\|\| (n==QEI_INTFLAG_VELC_Int) \
igorsk	0:1063a091a062	356	\|\| (n==QEI_INTFLAG_DIR_Int) \
igorsk	0:1063a091a062	357	\|\| (n==QEI_INTFLAG_ERR_Int) \
igorsk	0:1063a091a062	358	\|\| (n==QEI_INTFLAG_ENCLK_Int) \
igorsk	0:1063a091a062	359	\|\| (n==QEI_INTFLAG_POS0_Int) \
igorsk	0:1063a091a062	360	\|\| (n==QEI_INTFLAG_POS1_Int) \
igorsk	0:1063a091a062	361	\|\| (n==QEI_INTFLAG_POS2_Int) \
igorsk	0:1063a091a062	362	\|\| (n==QEI_INTFLAG_REV_Int) \
igorsk	0:1063a091a062	363	\|\| (n==QEI_INTFLAG_POS0REV_Int) \
igorsk	0:1063a091a062	364	\|\| (n==QEI_INTFLAG_POS1REV_Int) \
igorsk	0:1063a091a062	365	\|\| (n==QEI_INTFLAG_POS2REV_Int))
igorsk	0:1063a091a062	366
igorsk	0:1063a091a062	367	/**
igorsk	0:1063a091a062	368	* @}
igorsk	0:1063a091a062	369	*/
igorsk	0:1063a091a062	370
igorsk	0:1063a091a062	371
igorsk	0:1063a091a062	372	/* Public Functions ----------------------------------------------------------- */
igorsk	0:1063a091a062	373	/** @defgroup QEI_Public_Functions
igorsk	0:1063a091a062	374	* @{
igorsk	0:1063a091a062	375	*/
igorsk	0:1063a091a062	376
igorsk	0:1063a091a062	377	void QEI_Reset(LPC_QEI_TypeDef *QEIx, uint32_t ulResetType);
igorsk	0:1063a091a062	378	void QEI_Init(LPC_QEI_TypeDef QEIx, QEI_CFG_Type QEI_ConfigStruct);
igorsk	0:1063a091a062	379	void QEI_ConfigStructInit(QEI_CFG_Type *QIE_InitStruct);
igorsk	0:1063a091a062	380	void QEI_DeInit(LPC_QEI_TypeDef *QEIx);
igorsk	0:1063a091a062	381	FlagStatus QEI_GetStatus(LPC_QEI_TypeDef *QEIx, uint32_t ulFlagType);
igorsk	0:1063a091a062	382	uint32_t QEI_GetPosition(LPC_QEI_TypeDef *QEIx);
igorsk	0:1063a091a062	383	void QEI_SetMaxPosition(LPC_QEI_TypeDef *QEIx, uint32_t ulMaxPos);
igorsk	0:1063a091a062	384	void QEI_SetPositionComp(LPC_QEI_TypeDef *QEIx, uint8_t bPosCompCh, uint32_t ulPosComp);
igorsk	0:1063a091a062	385	uint32_t QEI_GetIndex(LPC_QEI_TypeDef *QEIx);
igorsk	0:1063a091a062	386	void QEI_SetIndexComp(LPC_QEI_TypeDef *QEIx, uint32_t ulIndexComp);
igorsk	0:1063a091a062	387	void QEI_SetTimerReload(LPC_QEI_TypeDef QEIx, QEI_RELOADCFG_Type QEIReloadStruct);
igorsk	0:1063a091a062	388	uint32_t QEI_GetTimer(LPC_QEI_TypeDef *QEIx);
igorsk	0:1063a091a062	389	uint32_t QEI_GetVelocity(LPC_QEI_TypeDef *QEIx);
igorsk	0:1063a091a062	390	uint32_t QEI_GetVelocityCap(LPC_QEI_TypeDef *QEIx);
igorsk	0:1063a091a062	391	void QEI_SetVelocityComp(LPC_QEI_TypeDef *QEIx, uint32_t ulVelComp);
igorsk	0:1063a091a062	392	void QEI_SetDigiFilter(LPC_QEI_TypeDef *QEIx, uint32_t ulSamplingPulse);
igorsk	0:1063a091a062	393	FlagStatus QEI_GetIntStatus(LPC_QEI_TypeDef *QEIx, uint32_t ulIntType);
igorsk	0:1063a091a062	394	void QEI_IntCmd(LPC_QEI_TypeDef *QEIx, uint32_t ulIntType, FunctionalState NewState);
igorsk	0:1063a091a062	395	void QEI_IntSet(LPC_QEI_TypeDef *QEIx, uint32_t ulIntType);
igorsk	0:1063a091a062	396	void QEI_IntClear(LPC_QEI_TypeDef *QEIx, uint32_t ulIntType);
igorsk	0:1063a091a062	397	uint32_t QEI_CalculateRPM(LPC_QEI_TypeDef *QEIx, uint32_t ulVelCapValue, uint32_t ulPPR);
igorsk	0:1063a091a062	398
igorsk	0:1063a091a062	399
igorsk	0:1063a091a062	400	/**
igorsk	0:1063a091a062	401	* @}
igorsk	0:1063a091a062	402	*/
igorsk	0:1063a091a062	403
igorsk	0:1063a091a062	404	#ifdef __cplusplus
igorsk	0:1063a091a062	405	}
igorsk	0:1063a091a062	406	#endif
igorsk	0:1063a091a062	407
igorsk	0:1063a091a062	408	#endif /* LPC17XX_QEI_H_ */
igorsk	0:1063a091a062	409
igorsk	0:1063a091a062	410	/**
igorsk	0:1063a091a062	411	* @}
igorsk	0:1063a091a062	412	*/
igorsk	0:1063a091a062	413
igorsk	0:1063a091a062	414	/* --------------------------------- End Of File ------------------------------ */

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	17 Feb 2010
Imports:	121
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	5

include/lpc17xx_qei.h@0:1063a091a062, 2010-02-17 (annotated)

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