iforce2d Chris / Mbed 2 deprecated ubxDistanceMeter

Displays distance to start location on OLED screen.

Dependencies:   mbed

u8g_dev_ssd1351_128x128.c@0:972874f31c98, 2018-03-07 (annotated)

Committer:
iforce2d
Date:
Wed Mar 07 12:49:14 2018 +0000
Revision:
0:972874f31c98
First commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
iforce2d 0:972874f31c98 1 /*
iforce2d 0:972874f31c98 2
iforce2d 0:972874f31c98 3 u8g_dev_ssd1351_128x128.c
iforce2d 0:972874f31c98 4
iforce2d 0:972874f31c98 5 Universal 8bit Graphics Library
iforce2d 0:972874f31c98 6
iforce2d 0:972874f31c98 7 Copyright (c) 2013, jamjardavies@gmail.com
iforce2d 0:972874f31c98 8 Copyright (c) 2013, olikraus@gmail.com
iforce2d 0:972874f31c98 9 All rights reserved.
iforce2d 0:972874f31c98 10
iforce2d 0:972874f31c98 11 Redistribution and use in source and binary forms, with or without modification,
iforce2d 0:972874f31c98 12 are permitted provided that the following conditions are met:
iforce2d 0:972874f31c98 13
iforce2d 0:972874f31c98 14 * Redistributions of source code must retain the above copyright notice, this list
iforce2d 0:972874f31c98 15 of conditions and the following disclaimer.
iforce2d 0:972874f31c98 16
iforce2d 0:972874f31c98 17 * Redistributions in binary form must reproduce the above copyright notice, this
iforce2d 0:972874f31c98 18 list of conditions and the following disclaimer in the documentation and/or other
iforce2d 0:972874f31c98 19 materials provided with the distribution.
iforce2d 0:972874f31c98 20
iforce2d 0:972874f31c98 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
iforce2d 0:972874f31c98 22 CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
iforce2d 0:972874f31c98 23 INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
iforce2d 0:972874f31c98 24 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
iforce2d 0:972874f31c98 25 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
iforce2d 0:972874f31c98 26 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
iforce2d 0:972874f31c98 27 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
iforce2d 0:972874f31c98 28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
iforce2d 0:972874f31c98 29 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
iforce2d 0:972874f31c98 30 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
iforce2d 0:972874f31c98 31 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
iforce2d 0:972874f31c98 32 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
iforce2d 0:972874f31c98 33 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
iforce2d 0:972874f31c98 34
iforce2d 0:972874f31c98 35 History:
iforce2d 0:972874f31c98 36 Initial version 20 May 2013 jamjardavies@gmail.com
iforce2d 0:972874f31c98 37 indexed device 22 May 2013 olikraus@gmail.com
iforce2d 0:972874f31c98 38
iforce2d 0:972874f31c98 39 */
iforce2d 0:972874f31c98 40
iforce2d 0:972874f31c98 41 #include "u8g.h"
iforce2d 0:972874f31c98 42
iforce2d 0:972874f31c98 43 #define WIDTH 128
iforce2d 0:972874f31c98 44 #define HEIGHT 128
iforce2d 0:972874f31c98 45 #define PAGE_HEIGHT 8
iforce2d 0:972874f31c98 46
iforce2d 0:972874f31c98 47 static const uint8_t u8g_dev_ssd1351_128x128_init_seq[] PROGMEM = {
iforce2d 0:972874f31c98 48 U8G_ESC_CS(0), /* disable chip */
iforce2d 0:972874f31c98 49 U8G_ESC_DLY(50),
iforce2d 0:972874f31c98 50 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 51 U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
iforce2d 0:972874f31c98 52 U8G_ESC_CS(1), /* enable chip */
iforce2d 0:972874f31c98 53 U8G_ESC_DLY(50),
iforce2d 0:972874f31c98 54
iforce2d 0:972874f31c98 55 0xfd, /* Command Lock */
iforce2d 0:972874f31c98 56 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 57 0x12,
iforce2d 0:972874f31c98 58
iforce2d 0:972874f31c98 59 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 60 0xfd,
iforce2d 0:972874f31c98 61 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 62 0xb1, /* Command Lock */
iforce2d 0:972874f31c98 63
iforce2d 0:972874f31c98 64 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 65 0xae, /* Set Display Off */
iforce2d 0:972874f31c98 66
iforce2d 0:972874f31c98 67 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 68 0xb3,
iforce2d 0:972874f31c98 69 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 70 0xf1, /* Front Clock Div */
iforce2d 0:972874f31c98 71
iforce2d 0:972874f31c98 72 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 73 0xca,
iforce2d 0:972874f31c98 74 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 75 0x7f, /* Set Multiplex Ratio */
iforce2d 0:972874f31c98 76
iforce2d 0:972874f31c98 77 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 78 0xa0,
iforce2d 0:972874f31c98 79 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 80 0xb4, /* Set Colour Depth */
iforce2d 0:972874f31c98 81
iforce2d 0:972874f31c98 82 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 83 0x15,
iforce2d 0:972874f31c98 84 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 85 0x00, 0x7f, /* Set Column Address */
iforce2d 0:972874f31c98 86
iforce2d 0:972874f31c98 87 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 88 0x75,
iforce2d 0:972874f31c98 89 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 90 0x00, 0x7f, /* Set Row Address */
iforce2d 0:972874f31c98 91
iforce2d 0:972874f31c98 92 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 93 0xa1,
iforce2d 0:972874f31c98 94 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 95 0x00, /* Set Display Start Line */
iforce2d 0:972874f31c98 96
iforce2d 0:972874f31c98 97 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 98 0xa2,
iforce2d 0:972874f31c98 99 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 100 0x00, /* Set Display Offset */
iforce2d 0:972874f31c98 101
iforce2d 0:972874f31c98 102 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 103 0xb5,
iforce2d 0:972874f31c98 104 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 105 0x00, /* Set GPIO */
iforce2d 0:972874f31c98 106
iforce2d 0:972874f31c98 107 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 108 0xab,
iforce2d 0:972874f31c98 109 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 110 0x01, /* Set Function Selection */
iforce2d 0:972874f31c98 111
iforce2d 0:972874f31c98 112 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 113 0xb1,
iforce2d 0:972874f31c98 114 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 115 0x32, /* Set Phase Length */
iforce2d 0:972874f31c98 116
iforce2d 0:972874f31c98 117 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 118 0xb4,
iforce2d 0:972874f31c98 119 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 120 0xa0, 0xb5, 0x55, /* Set Segment Low Voltage */
iforce2d 0:972874f31c98 121
iforce2d 0:972874f31c98 122 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 123 0xbb,
iforce2d 0:972874f31c98 124 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 125 0x17, /* Set Precharge Voltage */
iforce2d 0:972874f31c98 126
iforce2d 0:972874f31c98 127 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 128 0xbe,
iforce2d 0:972874f31c98 129 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 130 0x05, /* Set VComH Voltage */
iforce2d 0:972874f31c98 131
iforce2d 0:972874f31c98 132 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 133 0xc1,
iforce2d 0:972874f31c98 134 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 135 0xc8, 0x80, 0xc8, /* Set Contrast */
iforce2d 0:972874f31c98 136
iforce2d 0:972874f31c98 137 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 138 0xc7,
iforce2d 0:972874f31c98 139 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 140 0x0f, /* Set Master Contrast */
iforce2d 0:972874f31c98 141
iforce2d 0:972874f31c98 142 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 143 0xb6,
iforce2d 0:972874f31c98 144 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 145 0x01, /* Set Second Precharge Period */
iforce2d 0:972874f31c98 146
iforce2d 0:972874f31c98 147 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 148 0xa6, /* Set Display Mode Reset */
iforce2d 0:972874f31c98 149
iforce2d 0:972874f31c98 150
iforce2d 0:972874f31c98 151 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 152 0xb8, /* Set CMD Grayscale Lookup */
iforce2d 0:972874f31c98 153 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 154 0x05,
iforce2d 0:972874f31c98 155 0x06,
iforce2d 0:972874f31c98 156 0x07,
iforce2d 0:972874f31c98 157 0x08,
iforce2d 0:972874f31c98 158 0x09,
iforce2d 0:972874f31c98 159 0x0a,
iforce2d 0:972874f31c98 160 0x0b,
iforce2d 0:972874f31c98 161 0x0c,
iforce2d 0:972874f31c98 162 0x0D,
iforce2d 0:972874f31c98 163 0x0E,
iforce2d 0:972874f31c98 164 0x0F,
iforce2d 0:972874f31c98 165 0x10,
iforce2d 0:972874f31c98 166 0x11,
iforce2d 0:972874f31c98 167 0x12,
iforce2d 0:972874f31c98 168 0x13,
iforce2d 0:972874f31c98 169 0x14,
iforce2d 0:972874f31c98 170 0x15,
iforce2d 0:972874f31c98 171 0x16,
iforce2d 0:972874f31c98 172 0x18,
iforce2d 0:972874f31c98 173 0x1a,
iforce2d 0:972874f31c98 174 0x1b,
iforce2d 0:972874f31c98 175 0x1C,
iforce2d 0:972874f31c98 176 0x1D,
iforce2d 0:972874f31c98 177 0x1F,
iforce2d 0:972874f31c98 178 0x21,
iforce2d 0:972874f31c98 179 0x23,
iforce2d 0:972874f31c98 180 0x25,
iforce2d 0:972874f31c98 181 0x27,
iforce2d 0:972874f31c98 182 0x2A,
iforce2d 0:972874f31c98 183 0x2D,
iforce2d 0:972874f31c98 184 0x30,
iforce2d 0:972874f31c98 185 0x33,
iforce2d 0:972874f31c98 186 0x36,
iforce2d 0:972874f31c98 187 0x39,
iforce2d 0:972874f31c98 188 0x3C,
iforce2d 0:972874f31c98 189 0x3F,
iforce2d 0:972874f31c98 190 0x42,
iforce2d 0:972874f31c98 191 0x45,
iforce2d 0:972874f31c98 192 0x48,
iforce2d 0:972874f31c98 193 0x4C,
iforce2d 0:972874f31c98 194 0x50,
iforce2d 0:972874f31c98 195 0x54,
iforce2d 0:972874f31c98 196 0x58,
iforce2d 0:972874f31c98 197 0x5C,
iforce2d 0:972874f31c98 198 0x60,
iforce2d 0:972874f31c98 199 0x64,
iforce2d 0:972874f31c98 200 0x68,
iforce2d 0:972874f31c98 201 0x6C,
iforce2d 0:972874f31c98 202 0x70,
iforce2d 0:972874f31c98 203 0x74,
iforce2d 0:972874f31c98 204 0x78,
iforce2d 0:972874f31c98 205 0x7D,
iforce2d 0:972874f31c98 206 0x82,
iforce2d 0:972874f31c98 207 0x87,
iforce2d 0:972874f31c98 208 0x8C,
iforce2d 0:972874f31c98 209 0x91,
iforce2d 0:972874f31c98 210 0x96,
iforce2d 0:972874f31c98 211 0x9B,
iforce2d 0:972874f31c98 212 0xA0,
iforce2d 0:972874f31c98 213 0xA5,
iforce2d 0:972874f31c98 214 0xAA,
iforce2d 0:972874f31c98 215 0xAF,
iforce2d 0:972874f31c98 216 0xB4,
iforce2d 0:972874f31c98 217
iforce2d 0:972874f31c98 218 U8G_ESC_ADR(0),
iforce2d 0:972874f31c98 219 0xaf, /* Set Display On */
iforce2d 0:972874f31c98 220 0x5c,
iforce2d 0:972874f31c98 221 U8G_ESC_DLY(50),
iforce2d 0:972874f31c98 222 U8G_ESC_CS(0), /* disable chip */
iforce2d 0:972874f31c98 223 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 224 U8G_ESC_END /* end of sequence */
iforce2d 0:972874f31c98 225 };
iforce2d 0:972874f31c98 226
iforce2d 0:972874f31c98 227
iforce2d 0:972874f31c98 228 /* set gpio to high */
iforce2d 0:972874f31c98 229 static const uint8_t u8g_dev_ssd1351_128x128gh_init_seq[] PROGMEM = {
iforce2d 0:972874f31c98 230 U8G_ESC_CS(0), /* disable chip */
iforce2d 0:972874f31c98 231 U8G_ESC_DLY(50),
iforce2d 0:972874f31c98 232 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 233 U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
iforce2d 0:972874f31c98 234 U8G_ESC_CS(1), /* enable chip */
iforce2d 0:972874f31c98 235 U8G_ESC_DLY(50),
iforce2d 0:972874f31c98 236
iforce2d 0:972874f31c98 237 0xfd, /* Command Lock */
iforce2d 0:972874f31c98 238 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 239 0x12,
iforce2d 0:972874f31c98 240
iforce2d 0:972874f31c98 241 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 242 0xfd,
iforce2d 0:972874f31c98 243 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 244 0xb1, /* Command Lock */
iforce2d 0:972874f31c98 245
iforce2d 0:972874f31c98 246 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 247 0xae, /* Set Display Off */
iforce2d 0:972874f31c98 248
iforce2d 0:972874f31c98 249 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 250 0xb3,
iforce2d 0:972874f31c98 251 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 252 0xf1, /* Front Clock Div */
iforce2d 0:972874f31c98 253
iforce2d 0:972874f31c98 254 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 255 0xca,
iforce2d 0:972874f31c98 256 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 257 0x7f, /* Set Multiplex Ratio */
iforce2d 0:972874f31c98 258
iforce2d 0:972874f31c98 259 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 260 0xa0,
iforce2d 0:972874f31c98 261 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 262 0xb4, /* Set Colour Depth */
iforce2d 0:972874f31c98 263
iforce2d 0:972874f31c98 264 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 265 0x15,
iforce2d 0:972874f31c98 266 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 267 0x00, 0x7f, /* Set Column Address */
iforce2d 0:972874f31c98 268
iforce2d 0:972874f31c98 269 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 270 0x75,
iforce2d 0:972874f31c98 271 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 272 0x00, 0x7f, /* Set Row Address */
iforce2d 0:972874f31c98 273
iforce2d 0:972874f31c98 274 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 275 0xa1,
iforce2d 0:972874f31c98 276 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 277 0x00, /* Set Display Start Line */
iforce2d 0:972874f31c98 278
iforce2d 0:972874f31c98 279 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 280 0xa2,
iforce2d 0:972874f31c98 281 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 282 0x00, /* Set Display Offset */
iforce2d 0:972874f31c98 283
iforce2d 0:972874f31c98 284 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 285 0xb5,
iforce2d 0:972874f31c98 286 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 287 0x03, /* Set GPIO to High Level */
iforce2d 0:972874f31c98 288
iforce2d 0:972874f31c98 289 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 290 0xab,
iforce2d 0:972874f31c98 291 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 292 0x01, /* Set Function Selection */
iforce2d 0:972874f31c98 293
iforce2d 0:972874f31c98 294 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 295 0xb1,
iforce2d 0:972874f31c98 296 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 297 0x32, /* Set Phase Length */
iforce2d 0:972874f31c98 298
iforce2d 0:972874f31c98 299 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 300 0xb4,
iforce2d 0:972874f31c98 301 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 302 0xa0, 0xb5, 0x55, /* Set Segment Low Voltage */
iforce2d 0:972874f31c98 303
iforce2d 0:972874f31c98 304 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 305 0xbb,
iforce2d 0:972874f31c98 306 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 307 0x17, /* Set Precharge Voltage */
iforce2d 0:972874f31c98 308
iforce2d 0:972874f31c98 309 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 310 0xbe,
iforce2d 0:972874f31c98 311 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 312 0x05, /* Set VComH Voltage */
iforce2d 0:972874f31c98 313
iforce2d 0:972874f31c98 314 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 315 0xc1,
iforce2d 0:972874f31c98 316 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 317 0xc8, 0x80, 0xc8, /* Set Contrast */
iforce2d 0:972874f31c98 318
iforce2d 0:972874f31c98 319 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 320 0xc7,
iforce2d 0:972874f31c98 321 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 322 0x0f, /* Set Master Contrast */
iforce2d 0:972874f31c98 323
iforce2d 0:972874f31c98 324 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 325 0xb6,
iforce2d 0:972874f31c98 326 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 327 0x01, /* Set Second Precharge Period */
iforce2d 0:972874f31c98 328
iforce2d 0:972874f31c98 329 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 330 0xa6, /* Set Display Mode Reset */
iforce2d 0:972874f31c98 331
iforce2d 0:972874f31c98 332
iforce2d 0:972874f31c98 333 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 334 0xb8, /* Set CMD Grayscale Lookup */
iforce2d 0:972874f31c98 335 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 336 0x05,
iforce2d 0:972874f31c98 337 0x06,
iforce2d 0:972874f31c98 338 0x07,
iforce2d 0:972874f31c98 339 0x08,
iforce2d 0:972874f31c98 340 0x09,
iforce2d 0:972874f31c98 341 0x0a,
iforce2d 0:972874f31c98 342 0x0b,
iforce2d 0:972874f31c98 343 0x0c,
iforce2d 0:972874f31c98 344 0x0D,
iforce2d 0:972874f31c98 345 0x0E,
iforce2d 0:972874f31c98 346 0x0F,
iforce2d 0:972874f31c98 347 0x10,
iforce2d 0:972874f31c98 348 0x11,
iforce2d 0:972874f31c98 349 0x12,
iforce2d 0:972874f31c98 350 0x13,
iforce2d 0:972874f31c98 351 0x14,
iforce2d 0:972874f31c98 352 0x15,
iforce2d 0:972874f31c98 353 0x16,
iforce2d 0:972874f31c98 354 0x18,
iforce2d 0:972874f31c98 355 0x1a,
iforce2d 0:972874f31c98 356 0x1b,
iforce2d 0:972874f31c98 357 0x1C,
iforce2d 0:972874f31c98 358 0x1D,
iforce2d 0:972874f31c98 359 0x1F,
iforce2d 0:972874f31c98 360 0x21,
iforce2d 0:972874f31c98 361 0x23,
iforce2d 0:972874f31c98 362 0x25,
iforce2d 0:972874f31c98 363 0x27,
iforce2d 0:972874f31c98 364 0x2A,
iforce2d 0:972874f31c98 365 0x2D,
iforce2d 0:972874f31c98 366 0x30,
iforce2d 0:972874f31c98 367 0x33,
iforce2d 0:972874f31c98 368 0x36,
iforce2d 0:972874f31c98 369 0x39,
iforce2d 0:972874f31c98 370 0x3C,
iforce2d 0:972874f31c98 371 0x3F,
iforce2d 0:972874f31c98 372 0x42,
iforce2d 0:972874f31c98 373 0x45,
iforce2d 0:972874f31c98 374 0x48,
iforce2d 0:972874f31c98 375 0x4C,
iforce2d 0:972874f31c98 376 0x50,
iforce2d 0:972874f31c98 377 0x54,
iforce2d 0:972874f31c98 378 0x58,
iforce2d 0:972874f31c98 379 0x5C,
iforce2d 0:972874f31c98 380 0x60,
iforce2d 0:972874f31c98 381 0x64,
iforce2d 0:972874f31c98 382 0x68,
iforce2d 0:972874f31c98 383 0x6C,
iforce2d 0:972874f31c98 384 0x70,
iforce2d 0:972874f31c98 385 0x74,
iforce2d 0:972874f31c98 386 0x78,
iforce2d 0:972874f31c98 387 0x7D,
iforce2d 0:972874f31c98 388 0x82,
iforce2d 0:972874f31c98 389 0x87,
iforce2d 0:972874f31c98 390 0x8C,
iforce2d 0:972874f31c98 391 0x91,
iforce2d 0:972874f31c98 392 0x96,
iforce2d 0:972874f31c98 393 0x9B,
iforce2d 0:972874f31c98 394 0xA0,
iforce2d 0:972874f31c98 395 0xA5,
iforce2d 0:972874f31c98 396 0xAA,
iforce2d 0:972874f31c98 397 0xAF,
iforce2d 0:972874f31c98 398 0xB4,
iforce2d 0:972874f31c98 399
iforce2d 0:972874f31c98 400 U8G_ESC_ADR(0),
iforce2d 0:972874f31c98 401 0xaf, /* Set Display On */
iforce2d 0:972874f31c98 402 0x5c,
iforce2d 0:972874f31c98 403 U8G_ESC_DLY(50),
iforce2d 0:972874f31c98 404 U8G_ESC_CS(0), /* disable chip */
iforce2d 0:972874f31c98 405 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 406 U8G_ESC_END /* end of sequence */
iforce2d 0:972874f31c98 407 };
iforce2d 0:972874f31c98 408
iforce2d 0:972874f31c98 409 #define u8g_dev_ssd1351_128x128_init_seq u8g_dev_ssd1351_128x128_init_seq
iforce2d 0:972874f31c98 410
iforce2d 0:972874f31c98 411 static const uint8_t u8g_dev_ssd1351_128x128_column_seq[] PROGMEM = {
iforce2d 0:972874f31c98 412 U8G_ESC_CS(1),
iforce2d 0:972874f31c98 413 U8G_ESC_ADR(0), 0x15,
iforce2d 0:972874f31c98 414 U8G_ESC_ADR(1), 0x00, 0x7f,
iforce2d 0:972874f31c98 415 U8G_ESC_ADR(0), 0x75,
iforce2d 0:972874f31c98 416 U8G_ESC_ADR(1), 0x00, 0x7f,
iforce2d 0:972874f31c98 417 U8G_ESC_ADR(0), 0x5c,
iforce2d 0:972874f31c98 418 U8G_ESC_ADR(1),
iforce2d 0:972874f31c98 419 U8G_ESC_CS(0),
iforce2d 0:972874f31c98 420 U8G_ESC_END
iforce2d 0:972874f31c98 421 };
iforce2d 0:972874f31c98 422
iforce2d 0:972874f31c98 423 #define RGB332_STREAM_BYTES 8
iforce2d 0:972874f31c98 424 static uint8_t u8g_ssd1351_stream_bytes[RGB332_STREAM_BYTES*3];
iforce2d 0:972874f31c98 425
iforce2d 0:972874f31c98 426 void u8g_ssd1351_to_stream(uint8_t *ptr)
iforce2d 0:972874f31c98 427 {
iforce2d 0:972874f31c98 428 uint8_t cnt = RGB332_STREAM_BYTES;
iforce2d 0:972874f31c98 429 uint8_t val;
iforce2d 0:972874f31c98 430 uint8_t *dest = u8g_ssd1351_stream_bytes;
iforce2d 0:972874f31c98 431 for( cnt = 0; cnt < RGB332_STREAM_BYTES; cnt++ )
iforce2d 0:972874f31c98 432 {
iforce2d 0:972874f31c98 433 val = *ptr++;
iforce2d 0:972874f31c98 434 *dest++ = ((val & 0xe0) >> 2);
iforce2d 0:972874f31c98 435 *dest++ = ((val & 0x1c) << 1);
iforce2d 0:972874f31c98 436 *dest++ = ((val & 0x03) << 4);
iforce2d 0:972874f31c98 437 }
iforce2d 0:972874f31c98 438 }
iforce2d 0:972874f31c98 439
iforce2d 0:972874f31c98 440
iforce2d 0:972874f31c98 441 #ifdef OBSOLETE
iforce2d 0:972874f31c98 442 // Convert the internal RGB 332 to R
iforce2d 0:972874f31c98 443 static uint8_t u8g_ssd1351_get_r(uint8_t colour)
iforce2d 0:972874f31c98 444 {
iforce2d 0:972874f31c98 445 //return ((colour & 0xe0) >> 5) * 9;
iforce2d 0:972874f31c98 446 //return ((colour & 0xe0) >> 5) * 8;
iforce2d 0:972874f31c98 447 return ((colour & 0xe0) >> 2) ;
iforce2d 0:972874f31c98 448 }
iforce2d 0:972874f31c98 449
iforce2d 0:972874f31c98 450 // Convert the internal RGB 332 to G
iforce2d 0:972874f31c98 451 static uint8_t u8g_ssd1351_get_g(uint8_t colour)
iforce2d 0:972874f31c98 452 {
iforce2d 0:972874f31c98 453 //return ((colour & 0x1c) >> 2) * 9;
iforce2d 0:972874f31c98 454 //return ((colour & 0x1c) >> 2) * 8;
iforce2d 0:972874f31c98 455 return ((colour & 0x1c) << 1);
iforce2d 0:972874f31c98 456 }
iforce2d 0:972874f31c98 457
iforce2d 0:972874f31c98 458 // Convert the internal RGB 332 to B
iforce2d 0:972874f31c98 459 static uint8_t u8g_ssd1351_get_b(uint8_t colour)
iforce2d 0:972874f31c98 460 {
iforce2d 0:972874f31c98 461 //return (colour & 0x03) * 21;
iforce2d 0:972874f31c98 462 return (colour & 0x03) * 16;
iforce2d 0:972874f31c98 463 }
iforce2d 0:972874f31c98 464 #endif
iforce2d 0:972874f31c98 465
iforce2d 0:972874f31c98 466
iforce2d 0:972874f31c98 467 uint8_t u8g_dev_ssd1351_128x128_332_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
iforce2d 0:972874f31c98 468 {
iforce2d 0:972874f31c98 469 // u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
iforce2d 0:972874f31c98 470
iforce2d 0:972874f31c98 471 switch(msg)
iforce2d 0:972874f31c98 472 {
iforce2d 0:972874f31c98 473 case U8G_DEV_MSG_INIT:
iforce2d 0:972874f31c98 474 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_50NS);
iforce2d 0:972874f31c98 475 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128_init_seq);
iforce2d 0:972874f31c98 476 break;
iforce2d 0:972874f31c98 477
iforce2d 0:972874f31c98 478 case U8G_DEV_MSG_STOP:
iforce2d 0:972874f31c98 479 break;
iforce2d 0:972874f31c98 480
iforce2d 0:972874f31c98 481 case U8G_DEV_MSG_PAGE_FIRST:
iforce2d 0:972874f31c98 482 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128_column_seq);
iforce2d 0:972874f31c98 483 break;
iforce2d 0:972874f31c98 484
iforce2d 0:972874f31c98 485 case U8G_DEV_MSG_PAGE_NEXT:
iforce2d 0:972874f31c98 486 {
iforce2d 0:972874f31c98 487 u8g_uint_t x;
iforce2d 0:972874f31c98 488 uint8_t page_height;
iforce2d 0:972874f31c98 489 uint8_t i;
iforce2d 0:972874f31c98 490 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
iforce2d 0:972874f31c98 491 uint8_t *ptr = pb->buf;
iforce2d 0:972874f31c98 492
iforce2d 0:972874f31c98 493 u8g_SetChipSelect(u8g, dev, 1);
iforce2d 0:972874f31c98 494
iforce2d 0:972874f31c98 495 page_height = pb->p.page_y1;
iforce2d 0:972874f31c98 496 page_height -= pb->p.page_y0;
iforce2d 0:972874f31c98 497 page_height++;
iforce2d 0:972874f31c98 498 for( i = 0; i < page_height; i++ )
iforce2d 0:972874f31c98 499 {
iforce2d 0:972874f31c98 500
iforce2d 0:972874f31c98 501 for (x = 0; x < pb->width; x+=RGB332_STREAM_BYTES)
iforce2d 0:972874f31c98 502 {
iforce2d 0:972874f31c98 503 u8g_ssd1351_to_stream(ptr);
iforce2d 0:972874f31c98 504 u8g_WriteSequence(u8g, dev, RGB332_STREAM_BYTES*3, u8g_ssd1351_stream_bytes);
iforce2d 0:972874f31c98 505 ptr += RGB332_STREAM_BYTES;
iforce2d 0:972874f31c98 506 }
iforce2d 0:972874f31c98 507 }
iforce2d 0:972874f31c98 508 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 509 }
iforce2d 0:972874f31c98 510
iforce2d 0:972874f31c98 511 break;
iforce2d 0:972874f31c98 512 case U8G_DEV_MSG_GET_MODE:
iforce2d 0:972874f31c98 513 return U8G_MODE_R3G3B2;
iforce2d 0:972874f31c98 514 }
iforce2d 0:972874f31c98 515
iforce2d 0:972874f31c98 516 return u8g_dev_pb8h8_base_fn(u8g, dev, msg, arg);
iforce2d 0:972874f31c98 517 }
iforce2d 0:972874f31c98 518
iforce2d 0:972874f31c98 519 uint8_t u8g_dev_ssd1351_128x128gh_332_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
iforce2d 0:972874f31c98 520 {
iforce2d 0:972874f31c98 521 // u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
iforce2d 0:972874f31c98 522
iforce2d 0:972874f31c98 523 switch(msg)
iforce2d 0:972874f31c98 524 {
iforce2d 0:972874f31c98 525 case U8G_DEV_MSG_INIT:
iforce2d 0:972874f31c98 526 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_50NS);
iforce2d 0:972874f31c98 527 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128gh_init_seq);
iforce2d 0:972874f31c98 528 break;
iforce2d 0:972874f31c98 529
iforce2d 0:972874f31c98 530 case U8G_DEV_MSG_STOP:
iforce2d 0:972874f31c98 531 break;
iforce2d 0:972874f31c98 532
iforce2d 0:972874f31c98 533 case U8G_DEV_MSG_PAGE_FIRST:
iforce2d 0:972874f31c98 534 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128_column_seq);
iforce2d 0:972874f31c98 535 break;
iforce2d 0:972874f31c98 536
iforce2d 0:972874f31c98 537 case U8G_DEV_MSG_PAGE_NEXT:
iforce2d 0:972874f31c98 538 {
iforce2d 0:972874f31c98 539 u8g_uint_t x;
iforce2d 0:972874f31c98 540 uint8_t page_height;
iforce2d 0:972874f31c98 541 uint8_t i;
iforce2d 0:972874f31c98 542 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
iforce2d 0:972874f31c98 543 uint8_t *ptr = pb->buf;
iforce2d 0:972874f31c98 544
iforce2d 0:972874f31c98 545 u8g_SetChipSelect(u8g, dev, 1);
iforce2d 0:972874f31c98 546
iforce2d 0:972874f31c98 547 page_height = pb->p.page_y1;
iforce2d 0:972874f31c98 548 page_height -= pb->p.page_y0;
iforce2d 0:972874f31c98 549 page_height++;
iforce2d 0:972874f31c98 550 for( i = 0; i < page_height; i++ )
iforce2d 0:972874f31c98 551 {
iforce2d 0:972874f31c98 552
iforce2d 0:972874f31c98 553 for (x = 0; x < pb->width; x+=RGB332_STREAM_BYTES)
iforce2d 0:972874f31c98 554 {
iforce2d 0:972874f31c98 555 u8g_ssd1351_to_stream(ptr);
iforce2d 0:972874f31c98 556 u8g_WriteSequence(u8g, dev, RGB332_STREAM_BYTES*3, u8g_ssd1351_stream_bytes);
iforce2d 0:972874f31c98 557 ptr += RGB332_STREAM_BYTES;
iforce2d 0:972874f31c98 558 }
iforce2d 0:972874f31c98 559 }
iforce2d 0:972874f31c98 560 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 561 }
iforce2d 0:972874f31c98 562
iforce2d 0:972874f31c98 563 break;
iforce2d 0:972874f31c98 564 case U8G_DEV_MSG_GET_MODE:
iforce2d 0:972874f31c98 565 return U8G_MODE_R3G3B2;
iforce2d 0:972874f31c98 566 }
iforce2d 0:972874f31c98 567
iforce2d 0:972874f31c98 568 return u8g_dev_pb8h8_base_fn(u8g, dev, msg, arg);
iforce2d 0:972874f31c98 569 }
iforce2d 0:972874f31c98 570
iforce2d 0:972874f31c98 571 static uint8_t u8g_dev_ssd1351_128x128_r[256];
iforce2d 0:972874f31c98 572 static uint8_t u8g_dev_ssd1351_128x128_g[256];
iforce2d 0:972874f31c98 573 static uint8_t u8g_dev_ssd1351_128x128_b[256];
iforce2d 0:972874f31c98 574
iforce2d 0:972874f31c98 575 uint8_t u8g_dev_ssd1351_128x128_idx_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
iforce2d 0:972874f31c98 576 {
iforce2d 0:972874f31c98 577 // u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
iforce2d 0:972874f31c98 578
iforce2d 0:972874f31c98 579 switch(msg)
iforce2d 0:972874f31c98 580 {
iforce2d 0:972874f31c98 581 case U8G_DEV_MSG_INIT:
iforce2d 0:972874f31c98 582 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_50NS);
iforce2d 0:972874f31c98 583 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128_init_seq);
iforce2d 0:972874f31c98 584 break;
iforce2d 0:972874f31c98 585
iforce2d 0:972874f31c98 586 case U8G_DEV_MSG_STOP:
iforce2d 0:972874f31c98 587 break;
iforce2d 0:972874f31c98 588
iforce2d 0:972874f31c98 589 case U8G_DEV_MSG_SET_COLOR_ENTRY:
iforce2d 0:972874f31c98 590 u8g_dev_ssd1351_128x128_r[ ((u8g_dev_arg_irgb_t *)arg)->idx ] = ((u8g_dev_arg_irgb_t *)arg)->r;
iforce2d 0:972874f31c98 591 u8g_dev_ssd1351_128x128_g[ ((u8g_dev_arg_irgb_t *)arg)->idx ] = ((u8g_dev_arg_irgb_t *)arg)->g;
iforce2d 0:972874f31c98 592 u8g_dev_ssd1351_128x128_b[ ((u8g_dev_arg_irgb_t *)arg)->idx ] = ((u8g_dev_arg_irgb_t *)arg)->b;
iforce2d 0:972874f31c98 593 break;
iforce2d 0:972874f31c98 594
iforce2d 0:972874f31c98 595 case U8G_DEV_MSG_PAGE_FIRST:
iforce2d 0:972874f31c98 596 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128_column_seq);
iforce2d 0:972874f31c98 597 break;
iforce2d 0:972874f31c98 598
iforce2d 0:972874f31c98 599 case U8G_DEV_MSG_PAGE_NEXT:
iforce2d 0:972874f31c98 600 {
iforce2d 0:972874f31c98 601 int x;
iforce2d 0:972874f31c98 602 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
iforce2d 0:972874f31c98 603 uint8_t *ptr = pb->buf;
iforce2d 0:972874f31c98 604
iforce2d 0:972874f31c98 605 u8g_SetChipSelect(u8g, dev, 1);
iforce2d 0:972874f31c98 606
iforce2d 0:972874f31c98 607 for (x = 0; x < pb->width; x++)
iforce2d 0:972874f31c98 608 {
iforce2d 0:972874f31c98 609 u8g_WriteByte(u8g, dev, u8g_dev_ssd1351_128x128_r[(*ptr)>>2]);
iforce2d 0:972874f31c98 610 u8g_WriteByte(u8g, dev, u8g_dev_ssd1351_128x128_g[(*ptr)>>2]);
iforce2d 0:972874f31c98 611 u8g_WriteByte(u8g, dev, u8g_dev_ssd1351_128x128_b[(*ptr)>>2]);
iforce2d 0:972874f31c98 612
iforce2d 0:972874f31c98 613 ptr++;
iforce2d 0:972874f31c98 614 }
iforce2d 0:972874f31c98 615
iforce2d 0:972874f31c98 616 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 617 }
iforce2d 0:972874f31c98 618
iforce2d 0:972874f31c98 619 break;
iforce2d 0:972874f31c98 620 case U8G_DEV_MSG_GET_MODE:
iforce2d 0:972874f31c98 621 return U8G_MODE_INDEX;
iforce2d 0:972874f31c98 622 }
iforce2d 0:972874f31c98 623
iforce2d 0:972874f31c98 624 return u8g_dev_pb8h8_base_fn(u8g, dev, msg, arg);
iforce2d 0:972874f31c98 625 }
iforce2d 0:972874f31c98 626
iforce2d 0:972874f31c98 627 void u8g_ssd1351_hicolor_to_stream(uint8_t *ptr)
iforce2d 0:972874f31c98 628 {
iforce2d 0:972874f31c98 629 register uint8_t cnt = RGB332_STREAM_BYTES;
iforce2d 0:972874f31c98 630 register uint8_t low, high, r, g, b;
iforce2d 0:972874f31c98 631 uint8_t *dest = u8g_ssd1351_stream_bytes;
iforce2d 0:972874f31c98 632 for( cnt = 0; cnt < RGB332_STREAM_BYTES; cnt++ )
iforce2d 0:972874f31c98 633 {
iforce2d 0:972874f31c98 634 low = *ptr++;
iforce2d 0:972874f31c98 635 high = *ptr++;
iforce2d 0:972874f31c98 636
iforce2d 0:972874f31c98 637 r = high & ~7;
iforce2d 0:972874f31c98 638 r >>= 2;
iforce2d 0:972874f31c98 639 b = low & 31;
iforce2d 0:972874f31c98 640 b <<= 1;
iforce2d 0:972874f31c98 641 g = high & 7;
iforce2d 0:972874f31c98 642 g <<= 3;
iforce2d 0:972874f31c98 643 g |= (low>>5)&7;
iforce2d 0:972874f31c98 644
iforce2d 0:972874f31c98 645 *dest++ = r;
iforce2d 0:972874f31c98 646 *dest++ = g;
iforce2d 0:972874f31c98 647 *dest++ = b;
iforce2d 0:972874f31c98 648 }
iforce2d 0:972874f31c98 649 }
iforce2d 0:972874f31c98 650
iforce2d 0:972874f31c98 651
iforce2d 0:972874f31c98 652 uint8_t u8g_dev_ssd1351_128x128_hicolor_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
iforce2d 0:972874f31c98 653 {
iforce2d 0:972874f31c98 654 switch(msg)
iforce2d 0:972874f31c98 655 {
iforce2d 0:972874f31c98 656 case U8G_DEV_MSG_INIT:
iforce2d 0:972874f31c98 657 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_50NS);
iforce2d 0:972874f31c98 658 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128_init_seq);
iforce2d 0:972874f31c98 659 break;
iforce2d 0:972874f31c98 660 case U8G_DEV_MSG_STOP:
iforce2d 0:972874f31c98 661 break;
iforce2d 0:972874f31c98 662 case U8G_DEV_MSG_PAGE_FIRST:
iforce2d 0:972874f31c98 663 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128_column_seq);
iforce2d 0:972874f31c98 664 break;
iforce2d 0:972874f31c98 665 case U8G_DEV_MSG_PAGE_NEXT:
iforce2d 0:972874f31c98 666 {
iforce2d 0:972874f31c98 667 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
iforce2d 0:972874f31c98 668 uint8_t i, j;
iforce2d 0:972874f31c98 669 uint8_t page_height;
iforce2d 0:972874f31c98 670 uint8_t *ptr = pb->buf;
iforce2d 0:972874f31c98 671
iforce2d 0:972874f31c98 672 u8g_SetChipSelect(u8g, dev, 1);
iforce2d 0:972874f31c98 673
iforce2d 0:972874f31c98 674 page_height = pb->p.page_y1;
iforce2d 0:972874f31c98 675 page_height -= pb->p.page_y0;
iforce2d 0:972874f31c98 676 page_height++;
iforce2d 0:972874f31c98 677 for( j = 0; j < page_height; j++ )
iforce2d 0:972874f31c98 678 {
iforce2d 0:972874f31c98 679 for (i = 0; i < pb->width; i+=RGB332_STREAM_BYTES)
iforce2d 0:972874f31c98 680 {
iforce2d 0:972874f31c98 681 u8g_ssd1351_hicolor_to_stream(ptr);
iforce2d 0:972874f31c98 682 u8g_WriteSequence(u8g, dev, RGB332_STREAM_BYTES*3, u8g_ssd1351_stream_bytes);
iforce2d 0:972874f31c98 683 ptr += RGB332_STREAM_BYTES*2;
iforce2d 0:972874f31c98 684 }
iforce2d 0:972874f31c98 685
iforce2d 0:972874f31c98 686 }
iforce2d 0:972874f31c98 687
iforce2d 0:972874f31c98 688 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 689
iforce2d 0:972874f31c98 690 }
iforce2d 0:972874f31c98 691 break; /* continue to base fn */
iforce2d 0:972874f31c98 692 case U8G_DEV_MSG_GET_MODE:
iforce2d 0:972874f31c98 693 return U8G_MODE_HICOLOR;
iforce2d 0:972874f31c98 694 }
iforce2d 0:972874f31c98 695 return u8g_dev_pbxh16_base_fn(u8g, dev, msg, arg);
iforce2d 0:972874f31c98 696 }
iforce2d 0:972874f31c98 697
iforce2d 0:972874f31c98 698 uint8_t u8g_dev_ssd1351_128x128gh_hicolor_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
iforce2d 0:972874f31c98 699 {
iforce2d 0:972874f31c98 700 switch(msg)
iforce2d 0:972874f31c98 701 {
iforce2d 0:972874f31c98 702 case U8G_DEV_MSG_INIT:
iforce2d 0:972874f31c98 703 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_50NS);
iforce2d 0:972874f31c98 704 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128gh_init_seq);
iforce2d 0:972874f31c98 705 break;
iforce2d 0:972874f31c98 706 case U8G_DEV_MSG_STOP:
iforce2d 0:972874f31c98 707 break;
iforce2d 0:972874f31c98 708 case U8G_DEV_MSG_PAGE_FIRST:
iforce2d 0:972874f31c98 709 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128_column_seq);
iforce2d 0:972874f31c98 710 break;
iforce2d 0:972874f31c98 711 case U8G_DEV_MSG_PAGE_NEXT:
iforce2d 0:972874f31c98 712 {
iforce2d 0:972874f31c98 713 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
iforce2d 0:972874f31c98 714 uint8_t i, j;
iforce2d 0:972874f31c98 715 uint8_t page_height;
iforce2d 0:972874f31c98 716 uint8_t *ptr = pb->buf;
iforce2d 0:972874f31c98 717
iforce2d 0:972874f31c98 718 u8g_SetChipSelect(u8g, dev, 1);
iforce2d 0:972874f31c98 719
iforce2d 0:972874f31c98 720 page_height = pb->p.page_y1;
iforce2d 0:972874f31c98 721 page_height -= pb->p.page_y0;
iforce2d 0:972874f31c98 722 page_height++;
iforce2d 0:972874f31c98 723 for( j = 0; j < page_height; j++ )
iforce2d 0:972874f31c98 724 {
iforce2d 0:972874f31c98 725 for (i = 0; i < pb->width; i+=RGB332_STREAM_BYTES)
iforce2d 0:972874f31c98 726 {
iforce2d 0:972874f31c98 727 u8g_ssd1351_hicolor_to_stream(ptr);
iforce2d 0:972874f31c98 728 u8g_WriteSequence(u8g, dev, RGB332_STREAM_BYTES*3, u8g_ssd1351_stream_bytes);
iforce2d 0:972874f31c98 729 ptr += RGB332_STREAM_BYTES*2;
iforce2d 0:972874f31c98 730 }
iforce2d 0:972874f31c98 731
iforce2d 0:972874f31c98 732 }
iforce2d 0:972874f31c98 733
iforce2d 0:972874f31c98 734 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 735
iforce2d 0:972874f31c98 736 }
iforce2d 0:972874f31c98 737 break; /* continue to base fn */
iforce2d 0:972874f31c98 738 case U8G_DEV_MSG_GET_MODE:
iforce2d 0:972874f31c98 739 return U8G_MODE_HICOLOR;
iforce2d 0:972874f31c98 740 }
iforce2d 0:972874f31c98 741 return u8g_dev_pbxh16_base_fn(u8g, dev, msg, arg);
iforce2d 0:972874f31c98 742 }
iforce2d 0:972874f31c98 743
iforce2d 0:972874f31c98 744
iforce2d 0:972874f31c98 745 uint8_t u8g_dev_ssd1351_128x128_byte_buf[WIDTH*PAGE_HEIGHT] U8G_NOCOMMON ;
iforce2d 0:972874f31c98 746
iforce2d 0:972874f31c98 747 u8g_pb_t u8g_dev_ssd1351_128x128_byte_pb = { {PAGE_HEIGHT, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_ssd1351_128x128_byte_buf};
iforce2d 0:972874f31c98 748 u8g_dev_t u8g_dev_ssd1351_128x128_332_sw_spi = { u8g_dev_ssd1351_128x128_332_fn, &u8g_dev_ssd1351_128x128_byte_pb, U8G_COM_SW_SPI };
iforce2d 0:972874f31c98 749 u8g_dev_t u8g_dev_ssd1351_128x128_332_hw_spi = { u8g_dev_ssd1351_128x128_332_fn, &u8g_dev_ssd1351_128x128_byte_pb, U8G_COM_HW_SPI };
iforce2d 0:972874f31c98 750 u8g_dev_t u8g_dev_ssd1351_128x128gh_332_sw_spi = { u8g_dev_ssd1351_128x128gh_332_fn, &u8g_dev_ssd1351_128x128_byte_pb, U8G_COM_SW_SPI };
iforce2d 0:972874f31c98 751 u8g_dev_t u8g_dev_ssd1351_128x128gh_332_hw_spi = { u8g_dev_ssd1351_128x128gh_332_fn, &u8g_dev_ssd1351_128x128_byte_pb, U8G_COM_HW_SPI };
iforce2d 0:972874f31c98 752
iforce2d 0:972874f31c98 753 //u8g_dev_t u8g_dev_ssd1351_128x128_idx_sw_spi = { u8g_dev_ssd1351_128x128_idx_fn, &u8g_dev_ssd1351_128x128_byte_pb, U8G_COM_SW_SPI };
iforce2d 0:972874f31c98 754 //u8g_dev_t u8g_dev_ssd1351_128x128_idx_hw_spi = { u8g_dev_ssd1351_128x128_idx_fn, &u8g_dev_ssd1351_128x128_byte_pb, U8G_COM_HW_SPI };
iforce2d 0:972874f31c98 755
iforce2d 0:972874f31c98 756
iforce2d 0:972874f31c98 757 /* only half of the height, because two bytes are needed for one pixel */
iforce2d 0:972874f31c98 758 u8g_pb_t u8g_dev_ssd1351_128x128_hicolor_byte_pb = { {PAGE_HEIGHT/2, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_ssd1351_128x128_byte_buf};
iforce2d 0:972874f31c98 759 u8g_dev_t u8g_dev_ssd1351_128x128_hicolor_sw_spi = { u8g_dev_ssd1351_128x128_hicolor_fn, &u8g_dev_ssd1351_128x128_hicolor_byte_pb, U8G_COM_SW_SPI };
iforce2d 0:972874f31c98 760 u8g_dev_t u8g_dev_ssd1351_128x128_hicolor_hw_spi = { u8g_dev_ssd1351_128x128_hicolor_fn, &u8g_dev_ssd1351_128x128_hicolor_byte_pb, U8G_COM_HW_SPI };
iforce2d 0:972874f31c98 761 u8g_dev_t u8g_dev_ssd1351_128x128gh_hicolor_sw_spi = { u8g_dev_ssd1351_128x128gh_hicolor_fn, &u8g_dev_ssd1351_128x128_hicolor_byte_pb, U8G_COM_SW_SPI };
iforce2d 0:972874f31c98 762 u8g_dev_t u8g_dev_ssd1351_128x128gh_hicolor_hw_spi = { u8g_dev_ssd1351_128x128gh_hicolor_fn, &u8g_dev_ssd1351_128x128_hicolor_byte_pb, U8G_COM_HW_SPI };
iforce2d 0:972874f31c98 763
iforce2d 0:972874f31c98 764
iforce2d 0:972874f31c98 765 uint8_t u8g_dev_ssd1351_128x128_4x_byte_buf[WIDTH*PAGE_HEIGHT*4] U8G_NOCOMMON ;
iforce2d 0:972874f31c98 766
iforce2d 0:972874f31c98 767 u8g_pb_t u8g_dev_ssd1351_128x128_4x_332_byte_pb = { {PAGE_HEIGHT*4, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_ssd1351_128x128_4x_byte_buf};
iforce2d 0:972874f31c98 768 u8g_dev_t u8g_dev_ssd1351_128x128_4x_332_sw_spi = { u8g_dev_ssd1351_128x128_332_fn, &u8g_dev_ssd1351_128x128_4x_332_byte_pb, U8G_COM_SW_SPI };
iforce2d 0:972874f31c98 769 u8g_dev_t u8g_dev_ssd1351_128x128_4x_332_hw_spi = { u8g_dev_ssd1351_128x128_332_fn, &u8g_dev_ssd1351_128x128_4x_332_byte_pb, U8G_COM_HW_SPI };
iforce2d 0:972874f31c98 770 u8g_dev_t u8g_dev_ssd1351_128x128gh_4x_332_sw_spi = { u8g_dev_ssd1351_128x128gh_332_fn, &u8g_dev_ssd1351_128x128_4x_332_byte_pb, U8G_COM_SW_SPI };
iforce2d 0:972874f31c98 771 u8g_dev_t u8g_dev_ssd1351_128x128gh_4x_332_hw_spi = { u8g_dev_ssd1351_128x128gh_332_fn, &u8g_dev_ssd1351_128x128_4x_332_byte_pb, U8G_COM_HW_SPI };
iforce2d 0:972874f31c98 772
iforce2d 0:972874f31c98 773 u8g_pb_t u8g_dev_ssd1351_128x128_4x_hicolor_byte_pb = { {PAGE_HEIGHT/2*4, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_ssd1351_128x128_4x_byte_buf};
iforce2d 0:972874f31c98 774 u8g_dev_t u8g_dev_ssd1351_128x128_4x_hicolor_sw_spi = { u8g_dev_ssd1351_128x128_hicolor_fn, &u8g_dev_ssd1351_128x128_4x_hicolor_byte_pb, U8G_COM_SW_SPI };
iforce2d 0:972874f31c98 775 u8g_dev_t u8g_dev_ssd1351_128x128_4x_hicolor_hw_spi = { u8g_dev_ssd1351_128x128_hicolor_fn, &u8g_dev_ssd1351_128x128_4x_hicolor_byte_pb, U8G_COM_HW_SPI };
iforce2d 0:972874f31c98 776 u8g_dev_t u8g_dev_ssd1351_128x128gh_4x_hicolor_sw_spi = { u8g_dev_ssd1351_128x128gh_hicolor_fn, &u8g_dev_ssd1351_128x128_4x_hicolor_byte_pb, U8G_COM_SW_SPI };
iforce2d 0:972874f31c98 777 u8g_dev_t u8g_dev_ssd1351_128x128gh_4x_hicolor_hw_spi = { u8g_dev_ssd1351_128x128gh_hicolor_fn, &u8g_dev_ssd1351_128x128_4x_hicolor_byte_pb, U8G_COM_HW_SPI };
iforce2d 0:972874f31c98 778
iforce2d 0:972874f31c98 779
iforce2d 0:972874f31c98 780 /*
iforce2d 0:972874f31c98 781 U8G_PB_DEV(u8g_dev_ssd1351_128x128_332_sw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1351_128x128_332_fn, U8G_COM_SW_SPI);
iforce2d 0:972874f31c98 782 U8G_PB_DEV(u8g_dev_ssd1351_128x128_332_hw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1351_128x128_332_fn, U8G_COM_HW_SPI);
iforce2d 0:972874f31c98 783
iforce2d 0:972874f31c98 784 U8G_PB_DEV(u8g_dev_ssd1351_128x128_idx_sw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1351_128x128_idx_fn, U8G_COM_SW_SPI);
iforce2d 0:972874f31c98 785 U8G_PB_DEV(u8g_dev_ssd1351_128x128_idx_hw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1351_128x128_idx_fn, U8G_COM_HW_SPI);
iforce2d 0:972874f31c98 786 */
iforce2d 0:972874f31c98 787
iforce2d 0:972874f31c98 788